src/cpu/ppc/vm/assembler_ppc.hpp

*** 2045,2054 ****
--- 2045,2059 ----
    inline void stvx(  VectorRegister d, Register s2);
    inline void stvxl( VectorRegister d, Register s2);
    inline void lvsl(  VectorRegister d, Register s2);
    inline void lvsr(  VectorRegister d, Register s2);
  
+   // Endianess specific concatenation of 2 loaded vectors.
+   inline void load_perm(VectorRegister perm, Register addr);
+   inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
+   inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
+ 
    // RegisterOrConstant versions.
    // These emitters choose between the versions using two registers and
    // those with register and immediate, depending on the content of roc.
    // If the constant is not encodable as immediate, instructions to
    // load the constant are emitted beforehand. Store instructions need a