--- old/src/cpu/ppc/vm/assembler_ppc.hpp	2018-11-18 19:23:40.449083945 +0900
+++ new/src/cpu/ppc/vm/assembler_ppc.hpp	2018-11-18 19:23:40.379083378 +0900
@@ -2047,6 +2047,11 @@
   inline void lvsl(  VectorRegister d, Register s2);
   inline void lvsr(  VectorRegister d, Register s2);
 
+  // Endianess specific concatenation of 2 loaded vectors.
+  inline void load_perm(VectorRegister perm, Register addr);
+  inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
+  inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
+
   // RegisterOrConstant versions.
   // These emitters choose between the versions using two registers and
   // those with register and immediate, depending on the content of roc.