hotspot Sdiff src/cpu/ppc/vm

src/cpu/ppc/vm/assembler_ppc.hpp

2030   inline void lfsx(  FloatRegister d, Register b);
2031   inline void lfd(   FloatRegister d, int si16);
2032   inline void lfdx(  FloatRegister d, Register b);
2033   inline void stfs(  FloatRegister s, int si16);
2034   inline void stfsx( FloatRegister s, Register b);
2035   inline void stfd(  FloatRegister s, int si16);
2036   inline void stfdx( FloatRegister s, Register b);
2037   inline void lvebx( VectorRegister d, Register s2);
2038   inline void lvehx( VectorRegister d, Register s2);
2039   inline void lvewx( VectorRegister d, Register s2);
2040   inline void lvx(   VectorRegister d, Register s2);
2041   inline void lvxl(  VectorRegister d, Register s2);
2042   inline void stvebx(VectorRegister d, Register s2);
2043   inline void stvehx(VectorRegister d, Register s2);
2044   inline void stvewx(VectorRegister d, Register s2);
2045   inline void stvx(  VectorRegister d, Register s2);
2046   inline void stvxl( VectorRegister d, Register s2);
2047   inline void lvsl(  VectorRegister d, Register s2);
2048   inline void lvsr(  VectorRegister d, Register s2);
2049 





2050   // RegisterOrConstant versions.
2051   // These emitters choose between the versions using two registers and
2052   // those with register and immediate, depending on the content of roc.
2053   // If the constant is not encodable as immediate, instructions to
2054   // load the constant are emitted beforehand. Store instructions need a
2055   // tmp reg if the constant is not encodable as immediate.
2056   // Size unpredictable.
2057   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2058   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2059   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2060   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2061   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2062   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2063   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2064   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2065   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2066   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2067   void add( Register d, RegisterOrConstant roc, Register s1);
2068   void subf(Register d, RegisterOrConstant roc, Register s1);
2069   void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);

2030   inline void lfsx(  FloatRegister d, Register b);
2031   inline void lfd(   FloatRegister d, int si16);
2032   inline void lfdx(  FloatRegister d, Register b);
2033   inline void stfs(  FloatRegister s, int si16);
2034   inline void stfsx( FloatRegister s, Register b);
2035   inline void stfd(  FloatRegister s, int si16);
2036   inline void stfdx( FloatRegister s, Register b);
2037   inline void lvebx( VectorRegister d, Register s2);
2038   inline void lvehx( VectorRegister d, Register s2);
2039   inline void lvewx( VectorRegister d, Register s2);
2040   inline void lvx(   VectorRegister d, Register s2);
2041   inline void lvxl(  VectorRegister d, Register s2);
2042   inline void stvebx(VectorRegister d, Register s2);
2043   inline void stvehx(VectorRegister d, Register s2);
2044   inline void stvewx(VectorRegister d, Register s2);
2045   inline void stvx(  VectorRegister d, Register s2);
2046   inline void stvxl( VectorRegister d, Register s2);
2047   inline void lvsl(  VectorRegister d, Register s2);
2048   inline void lvsr(  VectorRegister d, Register s2);
2049 
2050   // Endianess specific concatenation of 2 loaded vectors.
2051   inline void load_perm(VectorRegister perm, Register addr);
2052   inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
2053   inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
2054 
2055   // RegisterOrConstant versions.
2056   // These emitters choose between the versions using two registers and
2057   // those with register and immediate, depending on the content of roc.
2058   // If the constant is not encodable as immediate, instructions to
2059   // load the constant are emitted beforehand. Store instructions need a
2060   // tmp reg if the constant is not encodable as immediate.
2061   // Size unpredictable.
2062   void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2063   void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2064   void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2065   void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2066   void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2067   void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2068   void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2069   void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2070   void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2071   void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2072   void add( Register d, RegisterOrConstant roc, Register s1);
2073   void subf(Register d, RegisterOrConstant roc, Register s1);
2074   void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);

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