src/cpu/aarch64/vm/interp_masm_aarch64.cpp

*** 187,200 ****
                                                                          int bcp_offset,
                                                                          size_t index_size) {
    get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size);
    // We use a 32-bit load here since the layout of 64-bit words on
    // little-endian machines allow us that.
!   // n.b. unlike x86 cache alreeady includes the index offset
!   ldrw(bytecode, Address(cache,
                           ConstantPoolCache::base_offset()
                           + ConstantPoolCacheEntry::indices_offset()));
    const int shift_count = (1 + byte_no) * BitsPerByte;
    ubfx(bytecode, bytecode, shift_count, BitsPerByte);
  }
  
  void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,
--- 187,201 ----
                                                                          int bcp_offset,
                                                                          size_t index_size) {
    get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size);
    // We use a 32-bit load here since the layout of 64-bit words on
    // little-endian machines allow us that.
!   // n.b. unlike x86 cache already includes the index offset
!   lea(bytecode, Address(cache,
                           ConstantPoolCache::base_offset()
                           + ConstantPoolCacheEntry::indices_offset()));
+   ldarw(bytecode, bytecode);
    const int shift_count = (1 + byte_no) * BitsPerByte;
    ubfx(bytecode, bytecode, shift_count, BitsPerByte);
  }
  
  void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,