1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
94
95 // Implementation of Address
96
97 #ifdef _LP64
98
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
105
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
134
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
143
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
152
153 #endif // _LP64
154
155
156
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
176
177 // Implementation of Assembler
178
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
182
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
189
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
199
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
208
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
216
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
226
227
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
242
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
252
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
267
268
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
274
275
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
281
282 // Encode the registers as needed in the fields they are used in
283
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
287
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
366
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
370
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
382
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
393
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
399
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
402
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
406
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
413
414 // If "which" is end_pc_operand, find the end of the instruction.
415
416 address ip = inst;
417 bool is_64bit = false;
418
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
421
422 again_after_prefix:
423 switch (0xFF & *ip++) {
424
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
431
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
442
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
454
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
466
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
475
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
482
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
519
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
530 #endif // _LP64
531 return ip;
532
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
538
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
547
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
553
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
567
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
583
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
589
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
594
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
603
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
610
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
616
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
626
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
641
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
649
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
665
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
668
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
688
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
700
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
706
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
710
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
737
738 default:
739 ShouldNotReachHere();
740
741 #undef REP8
742 #undef REP16
743 }
744
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
753
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
765
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
773
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
780
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
787
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
796
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
801
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
805
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
813
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
818
819
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
825
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
843
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
850
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
857
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
862
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
868
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
874
875
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
882
883
884 // Now the Assembler instructions (identical for 32/64 bits)
885
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
891
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
898
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
903
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
910
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
915
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
921
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
928
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
933
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
940
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
945
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
954
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
964
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
985
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
990
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1013
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1020
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1028
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1035
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1043
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1050
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1058
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1065
1066
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)0xBD);
1118 emit_int8((unsigned char)(0xC0 | encode));
1119 }
1120
1121 void Assembler::bswapl(Register reg) { // bswap
1122 int encode = prefix_and_encode(reg->encoding());
1123 emit_int8(0x0F);
1124 emit_int8((unsigned char)(0xC8 | encode));
1125 }
1126
1127 void Assembler::blsil(Register dst, Register src) {
1128 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1129 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1130 emit_int8((unsigned char)0xF3);
1131 emit_int8((unsigned char)(0xC0 | encode));
1132 }
1133
1134 void Assembler::blsil(Register dst, Address src) {
1135 InstructionMark im(this);
1136 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1137 vex_prefix_0F38(rbx, dst, src);
1138 emit_int8((unsigned char)0xF3);
1139 emit_operand(rbx, src);
1140 }
1141
1142 void Assembler::blsmskl(Register dst, Register src) {
1143 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1144 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1145 emit_int8((unsigned char)0xF3);
1146 emit_int8((unsigned char)(0xC0 | encode));
1147 }
1148
1149 void Assembler::blsmskl(Register dst, Address src) {
1150 InstructionMark im(this);
1151 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1152 vex_prefix_0F38(rdx, dst, src);
1153 emit_int8((unsigned char)0xF3);
1154 emit_operand(rdx, src);
1155 }
1156
1157 void Assembler::blsrl(Register dst, Register src) {
1158 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1159 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1160 emit_int8((unsigned char)0xF3);
1161 emit_int8((unsigned char)(0xC0 | encode));
1162 }
1163
1164 void Assembler::blsrl(Register dst, Address src) {
1165 InstructionMark im(this);
1166 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1167 vex_prefix_0F38(rcx, dst, src);
1168 emit_int8((unsigned char)0xF3);
1169 emit_operand(rcx, src);
1170 }
1171
1172 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1173 // suspect disp32 is always good
1174 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1175
1176 if (L.is_bound()) {
1177 const int long_size = 5;
1178 int offs = (int)( target(L) - pc() );
1179 assert(offs <= 0, "assembler error");
1180 InstructionMark im(this);
1181 // 1110 1000 #32-bit disp
1182 emit_int8((unsigned char)0xE8);
1183 emit_data(offs - long_size, rtype, operand);
1184 } else {
1185 InstructionMark im(this);
1186 // 1110 1000 #32-bit disp
1187 L.add_patch_at(code(), locator());
1188
1189 emit_int8((unsigned char)0xE8);
1190 emit_data(int(0), rtype, operand);
1191 }
1192 }
1193
1194 void Assembler::call(Register dst) {
1195 int encode = prefix_and_encode(dst->encoding());
1196 emit_int8((unsigned char)0xFF);
1197 emit_int8((unsigned char)(0xD0 | encode));
1198 }
1199
1200
1201 void Assembler::call(Address adr) {
1202 InstructionMark im(this);
1203 prefix(adr);
1204 emit_int8((unsigned char)0xFF);
1205 emit_operand(rdx, adr);
1206 }
1207
1208 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1209 assert(entry != NULL, "call most probably wrong");
1210 InstructionMark im(this);
1211 emit_int8((unsigned char)0xE8);
1212 intptr_t disp = entry - (pc() + sizeof(int32_t));
1213 assert(is_simm32(disp), "must be 32bit offset (call2)");
1214 // Technically, should use call32_operand, but this format is
1215 // implied by the fact that we're emitting a call instruction.
1216
1217 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1218 emit_data((int) disp, rspec, operand);
1219 }
1220
1221 void Assembler::cdql() {
1222 emit_int8((unsigned char)0x99);
1223 }
1224
1225 void Assembler::cld() {
1226 emit_int8((unsigned char)0xFC);
1227 }
1228
1229 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1230 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1231 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1232 emit_int8(0x0F);
1233 emit_int8(0x40 | cc);
1234 emit_int8((unsigned char)(0xC0 | encode));
1235 }
1236
1237
1238 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1239 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1240 prefix(src, dst);
1241 emit_int8(0x0F);
1242 emit_int8(0x40 | cc);
1243 emit_operand(dst, src);
1244 }
1245
1246 void Assembler::cmpb(Address dst, int imm8) {
1247 InstructionMark im(this);
1248 prefix(dst);
1249 emit_int8((unsigned char)0x80);
1250 emit_operand(rdi, dst, 1);
1251 emit_int8(imm8);
1252 }
1253
1254 void Assembler::cmpl(Address dst, int32_t imm32) {
1255 InstructionMark im(this);
1256 prefix(dst);
1257 emit_int8((unsigned char)0x81);
1258 emit_operand(rdi, dst, 4);
1259 emit_int32(imm32);
1260 }
1261
1262 void Assembler::cmpl(Register dst, int32_t imm32) {
1263 prefix(dst);
1264 emit_arith(0x81, 0xF8, dst, imm32);
1265 }
1266
1267 void Assembler::cmpl(Register dst, Register src) {
1268 (void) prefix_and_encode(dst->encoding(), src->encoding());
1269 emit_arith(0x3B, 0xC0, dst, src);
1270 }
1271
1272
1273 void Assembler::cmpl(Register dst, Address src) {
1274 InstructionMark im(this);
1275 prefix(src, dst);
1276 emit_int8((unsigned char)0x3B);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::cmpw(Address dst, int imm16) {
1281 InstructionMark im(this);
1282 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1283 emit_int8(0x66);
1284 emit_int8((unsigned char)0x81);
1285 emit_operand(rdi, dst, 2);
1286 emit_int16(imm16);
1287 }
1288
1289 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1290 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1291 // The ZF is set if the compared values were equal, and cleared otherwise.
1292 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1293 InstructionMark im(this);
1294 prefix(adr, reg);
1295 emit_int8(0x0F);
1296 emit_int8((unsigned char)0xB1);
1297 emit_operand(reg, adr);
1298 }
1299
1300 void Assembler::comisd(XMMRegister dst, Address src) {
1301 // NOTE: dbx seems to decode this as comiss even though the
1302 // 0x66 is there. Strangly ucomisd comes out correct
1303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1304 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1305 }
1306
1307 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1309 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1310 }
1311
1312 void Assembler::comiss(XMMRegister dst, Address src) {
1313 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1314 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1315 }
1316
1317 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1318 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1319 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1320 }
1321
1322 void Assembler::cpuid() {
1323 emit_int8(0x0F);
1324 emit_int8((unsigned char)0xA2);
1325 }
1326
1327 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1329 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1330 }
1331
1332 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1334 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1335 }
1336
1337 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1339 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1340 }
1341
1342 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1344 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1345 }
1346
1347 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1350 emit_int8(0x2A);
1351 emit_int8((unsigned char)(0xC0 | encode));
1352 }
1353
1354 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1356 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1357 }
1358
1359 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1360 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1361 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1362 emit_int8(0x2A);
1363 emit_int8((unsigned char)(0xC0 | encode));
1364 }
1365
1366 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1367 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1368 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1369 }
1370
1371 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1373 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1374 }
1375
1376 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1378 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1379 }
1380
1381
1382 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1384 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1385 emit_int8(0x2C);
1386 emit_int8((unsigned char)(0xC0 | encode));
1387 }
1388
1389 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1390 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1391 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1392 emit_int8(0x2C);
1393 emit_int8((unsigned char)(0xC0 | encode));
1394 }
1395
1396 void Assembler::decl(Address dst) {
1397 // Don't use it directly. Use MacroAssembler::decrement() instead.
1398 InstructionMark im(this);
1399 prefix(dst);
1400 emit_int8((unsigned char)0xFF);
1401 emit_operand(rcx, dst);
1402 }
1403
1404 void Assembler::divsd(XMMRegister dst, Address src) {
1405 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1406 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1407 }
1408
1409 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1411 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1412 }
1413
1414 void Assembler::divss(XMMRegister dst, Address src) {
1415 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1416 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1417 }
1418
1419 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1420 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1421 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1422 }
1423
1424 void Assembler::emms() {
1425 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1426 emit_int8(0x0F);
1427 emit_int8(0x77);
1428 }
1429
1430 void Assembler::hlt() {
1431 emit_int8((unsigned char)0xF4);
1432 }
1433
1434 void Assembler::idivl(Register src) {
1435 int encode = prefix_and_encode(src->encoding());
1436 emit_int8((unsigned char)0xF7);
1437 emit_int8((unsigned char)(0xF8 | encode));
1438 }
1439
1440 void Assembler::divl(Register src) { // Unsigned
1441 int encode = prefix_and_encode(src->encoding());
1442 emit_int8((unsigned char)0xF7);
1443 emit_int8((unsigned char)(0xF0 | encode));
1444 }
1445
1446 void Assembler::imull(Register dst, Register src) {
1447 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1448 emit_int8(0x0F);
1449 emit_int8((unsigned char)0xAF);
1450 emit_int8((unsigned char)(0xC0 | encode));
1451 }
1452
1453
1454 void Assembler::imull(Register dst, Register src, int value) {
1455 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1456 if (is8bit(value)) {
1457 emit_int8(0x6B);
1458 emit_int8((unsigned char)(0xC0 | encode));
1459 emit_int8(value & 0xFF);
1460 } else {
1461 emit_int8(0x69);
1462 emit_int8((unsigned char)(0xC0 | encode));
1463 emit_int32(value);
1464 }
1465 }
1466
1467 void Assembler::imull(Register dst, Address src) {
1468 InstructionMark im(this);
1469 prefix(src, dst);
1470 emit_int8(0x0F);
1471 emit_int8((unsigned char) 0xAF);
1472 emit_operand(dst, src);
1473 }
1474
1475
1476 void Assembler::incl(Address dst) {
1477 // Don't use it directly. Use MacroAssembler::increment() instead.
1478 InstructionMark im(this);
1479 prefix(dst);
1480 emit_int8((unsigned char)0xFF);
1481 emit_operand(rax, dst);
1482 }
1483
1484 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1485 InstructionMark im(this);
1486 assert((0 <= cc) && (cc < 16), "illegal cc");
1487 if (L.is_bound()) {
1488 address dst = target(L);
1489 assert(dst != NULL, "jcc most probably wrong");
1490
1491 const int short_size = 2;
1492 const int long_size = 6;
1493 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1494 if (maybe_short && is8bit(offs - short_size)) {
1495 // 0111 tttn #8-bit disp
1496 emit_int8(0x70 | cc);
1497 emit_int8((offs - short_size) & 0xFF);
1498 } else {
1499 // 0000 1111 1000 tttn #32-bit disp
1500 assert(is_simm32(offs - long_size),
1501 "must be 32bit offset (call4)");
1502 emit_int8(0x0F);
1503 emit_int8((unsigned char)(0x80 | cc));
1504 emit_int32(offs - long_size);
1505 }
1506 } else {
1507 // Note: could eliminate cond. jumps to this jump if condition
1508 // is the same however, seems to be rather unlikely case.
1509 // Note: use jccb() if label to be bound is very close to get
1510 // an 8-bit displacement
1511 L.add_patch_at(code(), locator());
1512 emit_int8(0x0F);
1513 emit_int8((unsigned char)(0x80 | cc));
1514 emit_int32(0);
1515 }
1516 }
1517
1518 void Assembler::jccb(Condition cc, Label& L) {
1519 if (L.is_bound()) {
1520 const int short_size = 2;
1521 address entry = target(L);
1522 #ifdef ASSERT
1523 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1524 intptr_t delta = short_branch_delta();
1525 if (delta != 0) {
1526 dist += (dist < 0 ? (-delta) :delta);
1527 }
1528 assert(is8bit(dist), "Dispacement too large for a short jmp");
1529 #endif
1530 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1531 // 0111 tttn #8-bit disp
1532 emit_int8(0x70 | cc);
1533 emit_int8((offs - short_size) & 0xFF);
1534 } else {
1535 InstructionMark im(this);
1536 L.add_patch_at(code(), locator());
1537 emit_int8(0x70 | cc);
1538 emit_int8(0);
1539 }
1540 }
1541
1542 void Assembler::jmp(Address adr) {
1543 InstructionMark im(this);
1544 prefix(adr);
1545 emit_int8((unsigned char)0xFF);
1546 emit_operand(rsp, adr);
1547 }
1548
1549 void Assembler::jmp(Label& L, bool maybe_short) {
1550 if (L.is_bound()) {
1551 address entry = target(L);
1552 assert(entry != NULL, "jmp most probably wrong");
1553 InstructionMark im(this);
1554 const int short_size = 2;
1555 const int long_size = 5;
1556 intptr_t offs = entry - pc();
1557 if (maybe_short && is8bit(offs - short_size)) {
1558 emit_int8((unsigned char)0xEB);
1559 emit_int8((offs - short_size) & 0xFF);
1560 } else {
1561 emit_int8((unsigned char)0xE9);
1562 emit_int32(offs - long_size);
1563 }
1564 } else {
1565 // By default, forward jumps are always 32-bit displacements, since
1566 // we can't yet know where the label will be bound. If you're sure that
1567 // the forward jump will not run beyond 256 bytes, use jmpb to
1568 // force an 8-bit displacement.
1569 InstructionMark im(this);
1570 L.add_patch_at(code(), locator());
1571 emit_int8((unsigned char)0xE9);
1572 emit_int32(0);
1573 }
1574 }
1575
1576 void Assembler::jmp(Register entry) {
1577 int encode = prefix_and_encode(entry->encoding());
1578 emit_int8((unsigned char)0xFF);
1579 emit_int8((unsigned char)(0xE0 | encode));
1580 }
1581
1582 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1583 InstructionMark im(this);
1584 emit_int8((unsigned char)0xE9);
1585 assert(dest != NULL, "must have a target");
1586 intptr_t disp = dest - (pc() + sizeof(int32_t));
1587 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1588 emit_data(disp, rspec.reloc(), call32_operand);
1589 }
1590
1591 void Assembler::jmpb(Label& L) {
1592 if (L.is_bound()) {
1593 const int short_size = 2;
1594 address entry = target(L);
1595 assert(entry != NULL, "jmp most probably wrong");
1596 #ifdef ASSERT
1597 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1598 intptr_t delta = short_branch_delta();
1599 if (delta != 0) {
1600 dist += (dist < 0 ? (-delta) :delta);
1601 }
1602 assert(is8bit(dist), "Dispacement too large for a short jmp");
1603 #endif
1604 intptr_t offs = entry - pc();
1605 emit_int8((unsigned char)0xEB);
1606 emit_int8((offs - short_size) & 0xFF);
1607 } else {
1608 InstructionMark im(this);
1609 L.add_patch_at(code(), locator());
1610 emit_int8((unsigned char)0xEB);
1611 emit_int8(0);
1612 }
1613 }
1614
1615 void Assembler::ldmxcsr( Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 prefix(src);
1619 emit_int8(0x0F);
1620 emit_int8((unsigned char)0xAE);
1621 emit_operand(as_Register(2), src);
1622 }
1623
1624 void Assembler::leal(Register dst, Address src) {
1625 InstructionMark im(this);
1626 #ifdef _LP64
1627 emit_int8(0x67); // addr32
1628 prefix(src, dst);
1629 #endif // LP64
1630 emit_int8((unsigned char)0x8D);
1631 emit_operand(dst, src);
1632 }
1633
1634 void Assembler::lfence() {
1635 emit_int8(0x0F);
1636 emit_int8((unsigned char)0xAE);
1637 emit_int8((unsigned char)0xE8);
1638 }
1639
1640 void Assembler::lock() {
1641 emit_int8((unsigned char)0xF0);
1642 }
1643
1644 void Assembler::lzcntl(Register dst, Register src) {
1645 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1646 emit_int8((unsigned char)0xF3);
1647 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1648 emit_int8(0x0F);
1649 emit_int8((unsigned char)0xBD);
1650 emit_int8((unsigned char)(0xC0 | encode));
1651 }
1652
1653 // Emit mfence instruction
1654 void Assembler::mfence() {
1655 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1656 emit_int8(0x0F);
1657 emit_int8((unsigned char)0xAE);
1658 emit_int8((unsigned char)0xF0);
1659 }
1660
1661 void Assembler::mov(Register dst, Register src) {
1662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1663 }
1664
1665 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1667 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1668 }
1669
1670 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1671 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1672 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1673 }
1674
1675 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1676 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1677 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1678 emit_int8(0x16);
1679 emit_int8((unsigned char)(0xC0 | encode));
1680 }
1681
1682 void Assembler::movb(Register dst, Address src) {
1683 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1684 InstructionMark im(this);
1685 prefix(src, dst, true);
1686 emit_int8((unsigned char)0x8A);
1687 emit_operand(dst, src);
1688 }
1689
1690
1691 void Assembler::movb(Address dst, int imm8) {
1692 InstructionMark im(this);
1693 prefix(dst);
1694 emit_int8((unsigned char)0xC6);
1695 emit_operand(rax, dst, 1);
1696 emit_int8(imm8);
1697 }
1698
1699
1700 void Assembler::movb(Address dst, Register src) {
1701 assert(src->has_byte_register(), "must have byte register");
1702 InstructionMark im(this);
1703 prefix(dst, src, true);
1704 emit_int8((unsigned char)0x88);
1705 emit_operand(src, dst);
1706 }
1707
1708 void Assembler::movdl(XMMRegister dst, Register src) {
1709 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1710 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1711 emit_int8(0x6E);
1712 emit_int8((unsigned char)(0xC0 | encode));
1713 }
1714
1715 void Assembler::movdl(Register dst, XMMRegister src) {
1716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1717 // swap src/dst to get correct prefix
1718 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1719 emit_int8(0x7E);
1720 emit_int8((unsigned char)(0xC0 | encode));
1721 }
1722
1723 void Assembler::movdl(XMMRegister dst, Address src) {
1724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1725 InstructionMark im(this);
1726 simd_prefix(dst, src, VEX_SIMD_66);
1727 emit_int8(0x6E);
1728 emit_operand(dst, src);
1729 }
1730
1731 void Assembler::movdl(Address dst, XMMRegister src) {
1732 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1733 InstructionMark im(this);
1734 simd_prefix(dst, src, VEX_SIMD_66);
1735 emit_int8(0x7E);
1736 emit_operand(src, dst);
1737 }
1738
1739 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1741 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1742 }
1743
1744 void Assembler::movdqa(XMMRegister dst, Address src) {
1745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1746 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1747 }
1748
1749 void Assembler::movdqu(XMMRegister dst, Address src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1752 }
1753
1754 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1756 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1757 }
1758
1759 void Assembler::movdqu(Address dst, XMMRegister src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 simd_prefix(dst, src, VEX_SIMD_F3);
1763 emit_int8(0x7F);
1764 emit_operand(src, dst);
1765 }
1766
1767 // Move Unaligned 256bit Vector
1768 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1769 assert(UseAVX > 0, "");
1770 bool vector256 = true;
1771 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1772 emit_int8(0x6F);
1773 emit_int8((unsigned char)(0xC0 | encode));
1774 }
1775
1776 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1777 assert(UseAVX > 0, "");
1778 InstructionMark im(this);
1779 bool vector256 = true;
1780 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1781 emit_int8(0x6F);
1782 emit_operand(dst, src);
1783 }
1784
1785 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1786 assert(UseAVX > 0, "");
1787 InstructionMark im(this);
1788 bool vector256 = true;
1789 // swap src<->dst for encoding
1790 assert(src != xnoreg, "sanity");
1791 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1792 emit_int8(0x7F);
1793 emit_operand(src, dst);
1794 }
1795
1796 // Uses zero extension on 64bit
1797
1798 void Assembler::movl(Register dst, int32_t imm32) {
1799 int encode = prefix_and_encode(dst->encoding());
1800 emit_int8((unsigned char)(0xB8 | encode));
1801 emit_int32(imm32);
1802 }
1803
1804 void Assembler::movl(Register dst, Register src) {
1805 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1806 emit_int8((unsigned char)0x8B);
1807 emit_int8((unsigned char)(0xC0 | encode));
1808 }
1809
1810 void Assembler::movl(Register dst, Address src) {
1811 InstructionMark im(this);
1812 prefix(src, dst);
1813 emit_int8((unsigned char)0x8B);
1814 emit_operand(dst, src);
1815 }
1816
1817 void Assembler::movl(Address dst, int32_t imm32) {
1818 InstructionMark im(this);
1819 prefix(dst);
1820 emit_int8((unsigned char)0xC7);
1821 emit_operand(rax, dst, 4);
1822 emit_int32(imm32);
1823 }
1824
1825 void Assembler::movl(Address dst, Register src) {
1826 InstructionMark im(this);
1827 prefix(dst, src);
1828 emit_int8((unsigned char)0x89);
1829 emit_operand(src, dst);
1830 }
1831
1832 // New cpus require to use movsd and movss to avoid partial register stall
1833 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1834 // The selection is done in MacroAssembler::movdbl() and movflt().
1835 void Assembler::movlpd(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1838 }
1839
1840 void Assembler::movq( MMXRegister dst, Address src ) {
1841 assert( VM_Version::supports_mmx(), "" );
1842 emit_int8(0x0F);
1843 emit_int8(0x6F);
1844 emit_operand(dst, src);
1845 }
1846
1847 void Assembler::movq( Address dst, MMXRegister src ) {
1848 assert( VM_Version::supports_mmx(), "" );
1849 emit_int8(0x0F);
1850 emit_int8(0x7F);
1851 // workaround gcc (3.2.1-7a) bug
1852 // In that version of gcc with only an emit_operand(MMX, Address)
1853 // gcc will tail jump and try and reverse the parameters completely
1854 // obliterating dst in the process. By having a version available
1855 // that doesn't need to swap the args at the tail jump the bug is
1856 // avoided.
1857 emit_operand(dst, src);
1858 }
1859
1860 void Assembler::movq(XMMRegister dst, Address src) {
1861 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1862 InstructionMark im(this);
1863 simd_prefix(dst, src, VEX_SIMD_F3);
1864 emit_int8(0x7E);
1865 emit_operand(dst, src);
1866 }
1867
1868 void Assembler::movq(Address dst, XMMRegister src) {
1869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1870 InstructionMark im(this);
1871 simd_prefix(dst, src, VEX_SIMD_66);
1872 emit_int8((unsigned char)0xD6);
1873 emit_operand(src, dst);
1874 }
1875
1876 void Assembler::movsbl(Register dst, Address src) { // movsxb
1877 InstructionMark im(this);
1878 prefix(src, dst);
1879 emit_int8(0x0F);
1880 emit_int8((unsigned char)0xBE);
1881 emit_operand(dst, src);
1882 }
1883
1884 void Assembler::movsbl(Register dst, Register src) { // movsxb
1885 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1886 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1887 emit_int8(0x0F);
1888 emit_int8((unsigned char)0xBE);
1889 emit_int8((unsigned char)(0xC0 | encode));
1890 }
1891
1892 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1894 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1895 }
1896
1897 void Assembler::movsd(XMMRegister dst, Address src) {
1898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1899 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1900 }
1901
1902 void Assembler::movsd(Address dst, XMMRegister src) {
1903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1904 InstructionMark im(this);
1905 simd_prefix(dst, src, VEX_SIMD_F2);
1906 emit_int8(0x11);
1907 emit_operand(src, dst);
1908 }
1909
1910 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1911 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1912 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1913 }
1914
1915 void Assembler::movss(XMMRegister dst, Address src) {
1916 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1917 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1918 }
1919
1920 void Assembler::movss(Address dst, XMMRegister src) {
1921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1922 InstructionMark im(this);
1923 simd_prefix(dst, src, VEX_SIMD_F3);
1924 emit_int8(0x11);
1925 emit_operand(src, dst);
1926 }
1927
1928 void Assembler::movswl(Register dst, Address src) { // movsxw
1929 InstructionMark im(this);
1930 prefix(src, dst);
1931 emit_int8(0x0F);
1932 emit_int8((unsigned char)0xBF);
1933 emit_operand(dst, src);
1934 }
1935
1936 void Assembler::movswl(Register dst, Register src) { // movsxw
1937 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1938 emit_int8(0x0F);
1939 emit_int8((unsigned char)0xBF);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943 void Assembler::movw(Address dst, int imm16) {
1944 InstructionMark im(this);
1945
1946 emit_int8(0x66); // switch to 16-bit mode
1947 prefix(dst);
1948 emit_int8((unsigned char)0xC7);
1949 emit_operand(rax, dst, 2);
1950 emit_int16(imm16);
1951 }
1952
1953 void Assembler::movw(Register dst, Address src) {
1954 InstructionMark im(this);
1955 emit_int8(0x66);
1956 prefix(src, dst);
1957 emit_int8((unsigned char)0x8B);
1958 emit_operand(dst, src);
1959 }
1960
1961 void Assembler::movw(Address dst, Register src) {
1962 InstructionMark im(this);
1963 emit_int8(0x66);
1964 prefix(dst, src);
1965 emit_int8((unsigned char)0x89);
1966 emit_operand(src, dst);
1967 }
1968
1969 void Assembler::movzbl(Register dst, Address src) { // movzxb
1970 InstructionMark im(this);
1971 prefix(src, dst);
1972 emit_int8(0x0F);
1973 emit_int8((unsigned char)0xB6);
1974 emit_operand(dst, src);
1975 }
1976
1977 void Assembler::movzbl(Register dst, Register src) { // movzxb
1978 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1979 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xB6);
1982 emit_int8(0xC0 | encode);
1983 }
1984
1985 void Assembler::movzwl(Register dst, Address src) { // movzxw
1986 InstructionMark im(this);
1987 prefix(src, dst);
1988 emit_int8(0x0F);
1989 emit_int8((unsigned char)0xB7);
1990 emit_operand(dst, src);
1991 }
1992
1993 void Assembler::movzwl(Register dst, Register src) { // movzxw
1994 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1995 emit_int8(0x0F);
1996 emit_int8((unsigned char)0xB7);
1997 emit_int8(0xC0 | encode);
1998 }
1999
2000 void Assembler::mull(Address src) {
2001 InstructionMark im(this);
2002 prefix(src);
2003 emit_int8((unsigned char)0xF7);
2004 emit_operand(rsp, src);
2005 }
2006
2007 void Assembler::mull(Register src) {
2008 int encode = prefix_and_encode(src->encoding());
2009 emit_int8((unsigned char)0xF7);
2010 emit_int8((unsigned char)(0xE0 | encode));
2011 }
2012
2013 void Assembler::mulsd(XMMRegister dst, Address src) {
2014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2015 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2016 }
2017
2018 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2020 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2021 }
2022
2023 void Assembler::mulss(XMMRegister dst, Address src) {
2024 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2025 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2026 }
2027
2028 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2029 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2030 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2031 }
2032
2033 void Assembler::negl(Register dst) {
2034 int encode = prefix_and_encode(dst->encoding());
2035 emit_int8((unsigned char)0xF7);
2036 emit_int8((unsigned char)(0xD8 | encode));
2037 }
2038
2039 void Assembler::nop(int i) {
2040 #ifdef ASSERT
2041 assert(i > 0, " ");
2042 // The fancy nops aren't currently recognized by debuggers making it a
2043 // pain to disassemble code while debugging. If asserts are on clearly
2044 // speed is not an issue so simply use the single byte traditional nop
2045 // to do alignment.
2046
2047 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2048 return;
2049
2050 #endif // ASSERT
2051
2052 if (UseAddressNop && VM_Version::is_intel()) {
2053 //
2054 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2055 // 1: 0x90
2056 // 2: 0x66 0x90
2057 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2058 // 4: 0x0F 0x1F 0x40 0x00
2059 // 5: 0x0F 0x1F 0x44 0x00 0x00
2060 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2061 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2062 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2063 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2064 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2065 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2066
2067 // The rest coding is Intel specific - don't use consecutive address nops
2068
2069 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2070 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2071 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2072 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2073
2074 while(i >= 15) {
2075 // For Intel don't generate consecutive addess nops (mix with regular nops)
2076 i -= 15;
2077 emit_int8(0x66); // size prefix
2078 emit_int8(0x66); // size prefix
2079 emit_int8(0x66); // size prefix
2080 addr_nop_8();
2081 emit_int8(0x66); // size prefix
2082 emit_int8(0x66); // size prefix
2083 emit_int8(0x66); // size prefix
2084 emit_int8((unsigned char)0x90);
2085 // nop
2086 }
2087 switch (i) {
2088 case 14:
2089 emit_int8(0x66); // size prefix
2090 case 13:
2091 emit_int8(0x66); // size prefix
2092 case 12:
2093 addr_nop_8();
2094 emit_int8(0x66); // size prefix
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 emit_int8((unsigned char)0x90);
2098 // nop
2099 break;
2100 case 11:
2101 emit_int8(0x66); // size prefix
2102 case 10:
2103 emit_int8(0x66); // size prefix
2104 case 9:
2105 emit_int8(0x66); // size prefix
2106 case 8:
2107 addr_nop_8();
2108 break;
2109 case 7:
2110 addr_nop_7();
2111 break;
2112 case 6:
2113 emit_int8(0x66); // size prefix
2114 case 5:
2115 addr_nop_5();
2116 break;
2117 case 4:
2118 addr_nop_4();
2119 break;
2120 case 3:
2121 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2122 emit_int8(0x66); // size prefix
2123 case 2:
2124 emit_int8(0x66); // size prefix
2125 case 1:
2126 emit_int8((unsigned char)0x90);
2127 // nop
2128 break;
2129 default:
2130 assert(i == 0, " ");
2131 }
2132 return;
2133 }
2134 if (UseAddressNop && VM_Version::is_amd()) {
2135 //
2136 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2137 // 1: 0x90
2138 // 2: 0x66 0x90
2139 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2140 // 4: 0x0F 0x1F 0x40 0x00
2141 // 5: 0x0F 0x1F 0x44 0x00 0x00
2142 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2143 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2144 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2145 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2146 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2147 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2148
2149 // The rest coding is AMD specific - use consecutive address nops
2150
2151 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2152 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2153 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2154 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2155 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2156 // Size prefixes (0x66) are added for larger sizes
2157
2158 while(i >= 22) {
2159 i -= 11;
2160 emit_int8(0x66); // size prefix
2161 emit_int8(0x66); // size prefix
2162 emit_int8(0x66); // size prefix
2163 addr_nop_8();
2164 }
2165 // Generate first nop for size between 21-12
2166 switch (i) {
2167 case 21:
2168 i -= 1;
2169 emit_int8(0x66); // size prefix
2170 case 20:
2171 case 19:
2172 i -= 1;
2173 emit_int8(0x66); // size prefix
2174 case 18:
2175 case 17:
2176 i -= 1;
2177 emit_int8(0x66); // size prefix
2178 case 16:
2179 case 15:
2180 i -= 8;
2181 addr_nop_8();
2182 break;
2183 case 14:
2184 case 13:
2185 i -= 7;
2186 addr_nop_7();
2187 break;
2188 case 12:
2189 i -= 6;
2190 emit_int8(0x66); // size prefix
2191 addr_nop_5();
2192 break;
2193 default:
2194 assert(i < 12, " ");
2195 }
2196
2197 // Generate second nop for size between 11-1
2198 switch (i) {
2199 case 11:
2200 emit_int8(0x66); // size prefix
2201 case 10:
2202 emit_int8(0x66); // size prefix
2203 case 9:
2204 emit_int8(0x66); // size prefix
2205 case 8:
2206 addr_nop_8();
2207 break;
2208 case 7:
2209 addr_nop_7();
2210 break;
2211 case 6:
2212 emit_int8(0x66); // size prefix
2213 case 5:
2214 addr_nop_5();
2215 break;
2216 case 4:
2217 addr_nop_4();
2218 break;
2219 case 3:
2220 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2221 emit_int8(0x66); // size prefix
2222 case 2:
2223 emit_int8(0x66); // size prefix
2224 case 1:
2225 emit_int8((unsigned char)0x90);
2226 // nop
2227 break;
2228 default:
2229 assert(i == 0, " ");
2230 }
2231 return;
2232 }
2233
2234 // Using nops with size prefixes "0x66 0x90".
2235 // From AMD Optimization Guide:
2236 // 1: 0x90
2237 // 2: 0x66 0x90
2238 // 3: 0x66 0x66 0x90
2239 // 4: 0x66 0x66 0x66 0x90
2240 // 5: 0x66 0x66 0x90 0x66 0x90
2241 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2242 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2243 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2244 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2245 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2246 //
2247 while(i > 12) {
2248 i -= 4;
2249 emit_int8(0x66); // size prefix
2250 emit_int8(0x66);
2251 emit_int8(0x66);
2252 emit_int8((unsigned char)0x90);
2253 // nop
2254 }
2255 // 1 - 12 nops
2256 if(i > 8) {
2257 if(i > 9) {
2258 i -= 1;
2259 emit_int8(0x66);
2260 }
2261 i -= 3;
2262 emit_int8(0x66);
2263 emit_int8(0x66);
2264 emit_int8((unsigned char)0x90);
2265 }
2266 // 1 - 8 nops
2267 if(i > 4) {
2268 if(i > 6) {
2269 i -= 1;
2270 emit_int8(0x66);
2271 }
2272 i -= 3;
2273 emit_int8(0x66);
2274 emit_int8(0x66);
2275 emit_int8((unsigned char)0x90);
2276 }
2277 switch (i) {
2278 case 4:
2279 emit_int8(0x66);
2280 case 3:
2281 emit_int8(0x66);
2282 case 2:
2283 emit_int8(0x66);
2284 case 1:
2285 emit_int8((unsigned char)0x90);
2286 break;
2287 default:
2288 assert(i == 0, " ");
2289 }
2290 }
2291
2292 void Assembler::notl(Register dst) {
2293 int encode = prefix_and_encode(dst->encoding());
2294 emit_int8((unsigned char)0xF7);
2295 emit_int8((unsigned char)(0xD0 | encode));
2296 }
2297
2298 void Assembler::orl(Address dst, int32_t imm32) {
2299 InstructionMark im(this);
2300 prefix(dst);
2301 emit_arith_operand(0x81, rcx, dst, imm32);
2302 }
2303
2304 void Assembler::orl(Register dst, int32_t imm32) {
2305 prefix(dst);
2306 emit_arith(0x81, 0xC8, dst, imm32);
2307 }
2308
2309 void Assembler::orl(Register dst, Address src) {
2310 InstructionMark im(this);
2311 prefix(src, dst);
2312 emit_int8(0x0B);
2313 emit_operand(dst, src);
2314 }
2315
2316 void Assembler::orl(Register dst, Register src) {
2317 (void) prefix_and_encode(dst->encoding(), src->encoding());
2318 emit_arith(0x0B, 0xC0, dst, src);
2319 }
2320
2321 void Assembler::packuswb(XMMRegister dst, Address src) {
2322 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2323 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2324 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2325 }
2326
2327 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2329 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2330 }
2331
2332 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2333 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2334 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2335 }
2336
2337 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2338 assert(VM_Version::supports_avx2(), "");
2339 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2340 emit_int8(0x00);
2341 emit_int8(0xC0 | encode);
2342 emit_int8(imm8);
2343 }
2344
2345 void Assembler::pause() {
2346 emit_int8((unsigned char)0xF3);
2347 emit_int8((unsigned char)0x90);
2348 }
2349
2350 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2351 assert(VM_Version::supports_sse4_2(), "");
2352 InstructionMark im(this);
2353 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2354 emit_int8(0x61);
2355 emit_operand(dst, src);
2356 emit_int8(imm8);
2357 }
2358
2359 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2360 assert(VM_Version::supports_sse4_2(), "");
2361 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2362 emit_int8(0x61);
2363 emit_int8((unsigned char)(0xC0 | encode));
2364 emit_int8(imm8);
2365 }
2366
2367 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2368 assert(VM_Version::supports_sse4_1(), "");
2369 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2370 emit_int8(0x16);
2371 emit_int8((unsigned char)(0xC0 | encode));
2372 emit_int8(imm8);
2373 }
2374
2375 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2376 assert(VM_Version::supports_sse4_1(), "");
2377 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2378 emit_int8(0x16);
2379 emit_int8((unsigned char)(0xC0 | encode));
2380 emit_int8(imm8);
2381 }
2382
2383 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2384 assert(VM_Version::supports_sse4_1(), "");
2385 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2386 emit_int8(0x22);
2387 emit_int8((unsigned char)(0xC0 | encode));
2388 emit_int8(imm8);
2389 }
2390
2391 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2392 assert(VM_Version::supports_sse4_1(), "");
2393 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2394 emit_int8(0x22);
2395 emit_int8((unsigned char)(0xC0 | encode));
2396 emit_int8(imm8);
2397 }
2398
2399 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2400 assert(VM_Version::supports_sse4_1(), "");
2401 InstructionMark im(this);
2402 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2403 emit_int8(0x30);
2404 emit_operand(dst, src);
2405 }
2406
2407 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2408 assert(VM_Version::supports_sse4_1(), "");
2409 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2410 emit_int8(0x30);
2411 emit_int8((unsigned char)(0xC0 | encode));
2412 }
2413
2414 // generic
2415 void Assembler::pop(Register dst) {
2416 int encode = prefix_and_encode(dst->encoding());
2417 emit_int8(0x58 | encode);
2418 }
2419
2420 void Assembler::popcntl(Register dst, Address src) {
2421 assert(VM_Version::supports_popcnt(), "must support");
2422 InstructionMark im(this);
2423 emit_int8((unsigned char)0xF3);
2424 prefix(src, dst);
2425 emit_int8(0x0F);
2426 emit_int8((unsigned char)0xB8);
2427 emit_operand(dst, src);
2428 }
2429
2430 void Assembler::popcntl(Register dst, Register src) {
2431 assert(VM_Version::supports_popcnt(), "must support");
2432 emit_int8((unsigned char)0xF3);
2433 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2434 emit_int8(0x0F);
2435 emit_int8((unsigned char)0xB8);
2436 emit_int8((unsigned char)(0xC0 | encode));
2437 }
2438
2439 void Assembler::popf() {
2440 emit_int8((unsigned char)0x9D);
2441 }
2442
2443 #ifndef _LP64 // no 32bit push/pop on amd64
2444 void Assembler::popl(Address dst) {
2445 // NOTE: this will adjust stack by 8byte on 64bits
2446 InstructionMark im(this);
2447 prefix(dst);
2448 emit_int8((unsigned char)0x8F);
2449 emit_operand(rax, dst);
2450 }
2451 #endif
2452
2453 void Assembler::prefetch_prefix(Address src) {
2454 prefix(src);
2455 emit_int8(0x0F);
2456 }
2457
2458 void Assembler::prefetchnta(Address src) {
2459 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2460 InstructionMark im(this);
2461 prefetch_prefix(src);
2462 emit_int8(0x18);
2463 emit_operand(rax, src); // 0, src
2464 }
2465
2466 void Assembler::prefetchr(Address src) {
2467 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2468 InstructionMark im(this);
2469 prefetch_prefix(src);
2470 emit_int8(0x0D);
2471 emit_operand(rax, src); // 0, src
2472 }
2473
2474 void Assembler::prefetcht0(Address src) {
2475 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2476 InstructionMark im(this);
2477 prefetch_prefix(src);
2478 emit_int8(0x18);
2479 emit_operand(rcx, src); // 1, src
2480 }
2481
2482 void Assembler::prefetcht1(Address src) {
2483 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2484 InstructionMark im(this);
2485 prefetch_prefix(src);
2486 emit_int8(0x18);
2487 emit_operand(rdx, src); // 2, src
2488 }
2489
2490 void Assembler::prefetcht2(Address src) {
2491 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2492 InstructionMark im(this);
2493 prefetch_prefix(src);
2494 emit_int8(0x18);
2495 emit_operand(rbx, src); // 3, src
2496 }
2497
2498 void Assembler::prefetchw(Address src) {
2499 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2500 InstructionMark im(this);
2501 prefetch_prefix(src);
2502 emit_int8(0x0D);
2503 emit_operand(rcx, src); // 1, src
2504 }
2505
2506 void Assembler::prefix(Prefix p) {
2507 emit_int8(p);
2508 }
2509
2510 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2511 assert(VM_Version::supports_ssse3(), "");
2512 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2513 emit_int8(0x00);
2514 emit_int8((unsigned char)(0xC0 | encode));
2515 }
2516
2517 void Assembler::pshufb(XMMRegister dst, Address src) {
2518 assert(VM_Version::supports_ssse3(), "");
2519 InstructionMark im(this);
2520 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2521 emit_int8(0x00);
2522 emit_operand(dst, src);
2523 }
2524
2525 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2526 assert(isByte(mode), "invalid value");
2527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2528 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2529 emit_int8(mode & 0xFF);
2530
2531 }
2532
2533 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2534 assert(isByte(mode), "invalid value");
2535 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2536 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2537 InstructionMark im(this);
2538 simd_prefix(dst, src, VEX_SIMD_66);
2539 emit_int8(0x70);
2540 emit_operand(dst, src);
2541 emit_int8(mode & 0xFF);
2542 }
2543
2544 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2545 assert(isByte(mode), "invalid value");
2546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2547 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2548 emit_int8(mode & 0xFF);
2549 }
2550
2551 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2552 assert(isByte(mode), "invalid value");
2553 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2554 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2555 InstructionMark im(this);
2556 simd_prefix(dst, src, VEX_SIMD_F2);
2557 emit_int8(0x70);
2558 emit_operand(dst, src);
2559 emit_int8(mode & 0xFF);
2560 }
2561
2562 void Assembler::psrldq(XMMRegister dst, int shift) {
2563 // Shift 128 bit value in xmm register by number of bytes.
2564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2565 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2566 emit_int8(0x73);
2567 emit_int8((unsigned char)(0xC0 | encode));
2568 emit_int8(shift);
2569 }
2570
2571 void Assembler::ptest(XMMRegister dst, Address src) {
2572 assert(VM_Version::supports_sse4_1(), "");
2573 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2574 InstructionMark im(this);
2575 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2576 emit_int8(0x17);
2577 emit_operand(dst, src);
2578 }
2579
2580 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2581 assert(VM_Version::supports_sse4_1(), "");
2582 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2583 emit_int8(0x17);
2584 emit_int8((unsigned char)(0xC0 | encode));
2585 }
2586
2587 void Assembler::vptest(XMMRegister dst, Address src) {
2588 assert(VM_Version::supports_avx(), "");
2589 InstructionMark im(this);
2590 bool vector256 = true;
2591 assert(dst != xnoreg, "sanity");
2592 int dst_enc = dst->encoding();
2593 // swap src<->dst for encoding
2594 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2595 emit_int8(0x17);
2596 emit_operand(dst, src);
2597 }
2598
2599 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2600 assert(VM_Version::supports_avx(), "");
2601 bool vector256 = true;
2602 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2603 emit_int8(0x17);
2604 emit_int8((unsigned char)(0xC0 | encode));
2605 }
2606
2607 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2609 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2610 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2611 }
2612
2613 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2615 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2616 }
2617
2618 void Assembler::punpckldq(XMMRegister dst, Address src) {
2619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2620 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2621 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2622 }
2623
2624 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2626 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2627 }
2628
2629 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2631 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2632 }
2633
2634 void Assembler::push(int32_t imm32) {
2635 // in 64bits we push 64bits onto the stack but only
2636 // take a 32bit immediate
2637 emit_int8(0x68);
2638 emit_int32(imm32);
2639 }
2640
2641 void Assembler::push(Register src) {
2642 int encode = prefix_and_encode(src->encoding());
2643
2644 emit_int8(0x50 | encode);
2645 }
2646
2647 void Assembler::pushf() {
2648 emit_int8((unsigned char)0x9C);
2649 }
2650
2651 #ifndef _LP64 // no 32bit push/pop on amd64
2652 void Assembler::pushl(Address src) {
2653 // Note this will push 64bit on 64bit
2654 InstructionMark im(this);
2655 prefix(src);
2656 emit_int8((unsigned char)0xFF);
2657 emit_operand(rsi, src);
2658 }
2659 #endif
2660
2661 void Assembler::rcll(Register dst, int imm8) {
2662 assert(isShiftCount(imm8), "illegal shift count");
2663 int encode = prefix_and_encode(dst->encoding());
2664 if (imm8 == 1) {
2665 emit_int8((unsigned char)0xD1);
2666 emit_int8((unsigned char)(0xD0 | encode));
2667 } else {
2668 emit_int8((unsigned char)0xC1);
2669 emit_int8((unsigned char)0xD0 | encode);
2670 emit_int8(imm8);
2671 }
2672 }
2673
2674 void Assembler::rdtsc() {
2675 emit_int8((unsigned char)0x0F);
2676 emit_int8((unsigned char)0x31);
2677 }
2678
2679 // copies data from [esi] to [edi] using rcx pointer sized words
2680 // generic
2681 void Assembler::rep_mov() {
2682 emit_int8((unsigned char)0xF3);
2683 // MOVSQ
2684 LP64_ONLY(prefix(REX_W));
2685 emit_int8((unsigned char)0xA5);
2686 }
2687
2688 // sets rcx bytes with rax, value at [edi]
2689 void Assembler::rep_stosb() {
2690 emit_int8((unsigned char)0xF3); // REP
2691 LP64_ONLY(prefix(REX_W));
2692 emit_int8((unsigned char)0xAA); // STOSB
2693 }
2694
2695 // sets rcx pointer sized words with rax, value at [edi]
2696 // generic
2697 void Assembler::rep_stos() {
2698 emit_int8((unsigned char)0xF3); // REP
2699 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2700 emit_int8((unsigned char)0xAB);
2701 }
2702
2703 // scans rcx pointer sized words at [edi] for occurance of rax,
2704 // generic
2705 void Assembler::repne_scan() { // repne_scan
2706 emit_int8((unsigned char)0xF2);
2707 // SCASQ
2708 LP64_ONLY(prefix(REX_W));
2709 emit_int8((unsigned char)0xAF);
2710 }
2711
2712 #ifdef _LP64
2713 // scans rcx 4 byte words at [edi] for occurance of rax,
2714 // generic
2715 void Assembler::repne_scanl() { // repne_scan
2716 emit_int8((unsigned char)0xF2);
2717 // SCASL
2718 emit_int8((unsigned char)0xAF);
2719 }
2720 #endif
2721
2722 void Assembler::ret(int imm16) {
2723 if (imm16 == 0) {
2724 emit_int8((unsigned char)0xC3);
2725 } else {
2726 emit_int8((unsigned char)0xC2);
2727 emit_int16(imm16);
2728 }
2729 }
2730
2731 void Assembler::sahf() {
2732 #ifdef _LP64
2733 // Not supported in 64bit mode
2734 ShouldNotReachHere();
2735 #endif
2736 emit_int8((unsigned char)0x9E);
2737 }
2738
2739 void Assembler::sarl(Register dst, int imm8) {
2740 int encode = prefix_and_encode(dst->encoding());
2741 assert(isShiftCount(imm8), "illegal shift count");
2742 if (imm8 == 1) {
2743 emit_int8((unsigned char)0xD1);
2744 emit_int8((unsigned char)(0xF8 | encode));
2745 } else {
2746 emit_int8((unsigned char)0xC1);
2747 emit_int8((unsigned char)(0xF8 | encode));
2748 emit_int8(imm8);
2749 }
2750 }
2751
2752 void Assembler::sarl(Register dst) {
2753 int encode = prefix_and_encode(dst->encoding());
2754 emit_int8((unsigned char)0xD3);
2755 emit_int8((unsigned char)(0xF8 | encode));
2756 }
2757
2758 void Assembler::sbbl(Address dst, int32_t imm32) {
2759 InstructionMark im(this);
2760 prefix(dst);
2761 emit_arith_operand(0x81, rbx, dst, imm32);
2762 }
2763
2764 void Assembler::sbbl(Register dst, int32_t imm32) {
2765 prefix(dst);
2766 emit_arith(0x81, 0xD8, dst, imm32);
2767 }
2768
2769
2770 void Assembler::sbbl(Register dst, Address src) {
2771 InstructionMark im(this);
2772 prefix(src, dst);
2773 emit_int8(0x1B);
2774 emit_operand(dst, src);
2775 }
2776
2777 void Assembler::sbbl(Register dst, Register src) {
2778 (void) prefix_and_encode(dst->encoding(), src->encoding());
2779 emit_arith(0x1B, 0xC0, dst, src);
2780 }
2781
2782 void Assembler::setb(Condition cc, Register dst) {
2783 assert(0 <= cc && cc < 16, "illegal cc");
2784 int encode = prefix_and_encode(dst->encoding(), true);
2785 emit_int8(0x0F);
2786 emit_int8((unsigned char)0x90 | cc);
2787 emit_int8((unsigned char)(0xC0 | encode));
2788 }
2789
2790 void Assembler::shll(Register dst, int imm8) {
2791 assert(isShiftCount(imm8), "illegal shift count");
2792 int encode = prefix_and_encode(dst->encoding());
2793 if (imm8 == 1 ) {
2794 emit_int8((unsigned char)0xD1);
2795 emit_int8((unsigned char)(0xE0 | encode));
2796 } else {
2797 emit_int8((unsigned char)0xC1);
2798 emit_int8((unsigned char)(0xE0 | encode));
2799 emit_int8(imm8);
2800 }
2801 }
2802
2803 void Assembler::shll(Register dst) {
2804 int encode = prefix_and_encode(dst->encoding());
2805 emit_int8((unsigned char)0xD3);
2806 emit_int8((unsigned char)(0xE0 | encode));
2807 }
2808
2809 void Assembler::shrl(Register dst, int imm8) {
2810 assert(isShiftCount(imm8), "illegal shift count");
2811 int encode = prefix_and_encode(dst->encoding());
2812 emit_int8((unsigned char)0xC1);
2813 emit_int8((unsigned char)(0xE8 | encode));
2814 emit_int8(imm8);
2815 }
2816
2817 void Assembler::shrl(Register dst) {
2818 int encode = prefix_and_encode(dst->encoding());
2819 emit_int8((unsigned char)0xD3);
2820 emit_int8((unsigned char)(0xE8 | encode));
2821 }
2822
2823 // copies a single word from [esi] to [edi]
2824 void Assembler::smovl() {
2825 emit_int8((unsigned char)0xA5);
2826 }
2827
2828 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2829 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2830 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2831 }
2832
2833 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2834 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2835 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2836 }
2837
2838 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2839 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2840 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2841 }
2842
2843 void Assembler::std() {
2844 emit_int8((unsigned char)0xFD);
2845 }
2846
2847 void Assembler::sqrtss(XMMRegister dst, Address src) {
2848 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2849 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2850 }
2851
2852 void Assembler::stmxcsr( Address dst) {
2853 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2854 InstructionMark im(this);
2855 prefix(dst);
2856 emit_int8(0x0F);
2857 emit_int8((unsigned char)0xAE);
2858 emit_operand(as_Register(3), dst);
2859 }
2860
2861 void Assembler::subl(Address dst, int32_t imm32) {
2862 InstructionMark im(this);
2863 prefix(dst);
2864 emit_arith_operand(0x81, rbp, dst, imm32);
2865 }
2866
2867 void Assembler::subl(Address dst, Register src) {
2868 InstructionMark im(this);
2869 prefix(dst, src);
2870 emit_int8(0x29);
2871 emit_operand(src, dst);
2872 }
2873
2874 void Assembler::subl(Register dst, int32_t imm32) {
2875 prefix(dst);
2876 emit_arith(0x81, 0xE8, dst, imm32);
2877 }
2878
2879 // Force generation of a 4 byte immediate value even if it fits into 8bit
2880 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2881 prefix(dst);
2882 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2883 }
2884
2885 void Assembler::subl(Register dst, Address src) {
2886 InstructionMark im(this);
2887 prefix(src, dst);
2888 emit_int8(0x2B);
2889 emit_operand(dst, src);
2890 }
2891
2892 void Assembler::subl(Register dst, Register src) {
2893 (void) prefix_and_encode(dst->encoding(), src->encoding());
2894 emit_arith(0x2B, 0xC0, dst, src);
2895 }
2896
2897 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2899 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2900 }
2901
2902 void Assembler::subsd(XMMRegister dst, Address src) {
2903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2904 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2905 }
2906
2907 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2908 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2909 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2910 }
2911
2912 void Assembler::subss(XMMRegister dst, Address src) {
2913 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2914 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2915 }
2916
2917 void Assembler::testb(Register dst, int imm8) {
2918 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2919 (void) prefix_and_encode(dst->encoding(), true);
2920 emit_arith_b(0xF6, 0xC0, dst, imm8);
2921 }
2922
2923 void Assembler::testl(Register dst, int32_t imm32) {
2924 // not using emit_arith because test
2925 // doesn't support sign-extension of
2926 // 8bit operands
2927 int encode = dst->encoding();
2928 if (encode == 0) {
2929 emit_int8((unsigned char)0xA9);
2930 } else {
2931 encode = prefix_and_encode(encode);
2932 emit_int8((unsigned char)0xF7);
2933 emit_int8((unsigned char)(0xC0 | encode));
2934 }
2935 emit_int32(imm32);
2936 }
2937
2938 void Assembler::testl(Register dst, Register src) {
2939 (void) prefix_and_encode(dst->encoding(), src->encoding());
2940 emit_arith(0x85, 0xC0, dst, src);
2941 }
2942
2943 void Assembler::testl(Register dst, Address src) {
2944 InstructionMark im(this);
2945 prefix(src, dst);
2946 emit_int8((unsigned char)0x85);
2947 emit_operand(dst, src);
2948 }
2949
2950 void Assembler::tzcntl(Register dst, Register src) {
2951 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2952 emit_int8((unsigned char)0xF3);
2953 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2954 emit_int8(0x0F);
2955 emit_int8((unsigned char)0xBC);
2956 emit_int8((unsigned char)0xC0 | encode);
2957 }
2958
2959 void Assembler::tzcntq(Register dst, Register src) {
2960 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2961 emit_int8((unsigned char)0xF3);
2962 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2963 emit_int8(0x0F);
2964 emit_int8((unsigned char)0xBC);
2965 emit_int8((unsigned char)(0xC0 | encode));
2966 }
2967
2968 void Assembler::ucomisd(XMMRegister dst, Address src) {
2969 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2970 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2971 }
2972
2973 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2974 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2975 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2976 }
2977
2978 void Assembler::ucomiss(XMMRegister dst, Address src) {
2979 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2980 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2981 }
2982
2983 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2984 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2985 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2986 }
2987
2988 void Assembler::xabort(int8_t imm8) {
2989 emit_int8((unsigned char)0xC6);
2990 emit_int8((unsigned char)0xF8);
2991 emit_int8((unsigned char)(imm8 & 0xFF));
2992 }
2993
2994 void Assembler::xaddl(Address dst, Register src) {
2995 InstructionMark im(this);
2996 prefix(dst, src);
2997 emit_int8(0x0F);
2998 emit_int8((unsigned char)0xC1);
2999 emit_operand(src, dst);
3000 }
3001
3002 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3003 InstructionMark im(this);
3004 relocate(rtype);
3005 if (abort.is_bound()) {
3006 address entry = target(abort);
3007 assert(entry != NULL, "abort entry NULL");
3008 intptr_t offset = entry - pc();
3009 emit_int8((unsigned char)0xC7);
3010 emit_int8((unsigned char)0xF8);
3011 emit_int32(offset - 6); // 2 opcode + 4 address
3012 } else {
3013 abort.add_patch_at(code(), locator());
3014 emit_int8((unsigned char)0xC7);
3015 emit_int8((unsigned char)0xF8);
3016 emit_int32(0);
3017 }
3018 }
3019
3020 void Assembler::xchgl(Register dst, Address src) { // xchg
3021 InstructionMark im(this);
3022 prefix(src, dst);
3023 emit_int8((unsigned char)0x87);
3024 emit_operand(dst, src);
3025 }
3026
3027 void Assembler::xchgl(Register dst, Register src) {
3028 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3029 emit_int8((unsigned char)0x87);
3030 emit_int8((unsigned char)(0xC0 | encode));
3031 }
3032
3033 void Assembler::xend() {
3034 emit_int8((unsigned char)0x0F);
3035 emit_int8((unsigned char)0x01);
3036 emit_int8((unsigned char)0xD5);
3037 }
3038
3039 void Assembler::xgetbv() {
3040 emit_int8(0x0F);
3041 emit_int8(0x01);
3042 emit_int8((unsigned char)0xD0);
3043 }
3044
3045 void Assembler::xorl(Register dst, int32_t imm32) {
3046 prefix(dst);
3047 emit_arith(0x81, 0xF0, dst, imm32);
3048 }
3049
3050 void Assembler::xorl(Register dst, Address src) {
3051 InstructionMark im(this);
3052 prefix(src, dst);
3053 emit_int8(0x33);
3054 emit_operand(dst, src);
3055 }
3056
3057 void Assembler::xorl(Register dst, Register src) {
3058 (void) prefix_and_encode(dst->encoding(), src->encoding());
3059 emit_arith(0x33, 0xC0, dst, src);
3060 }
3061
3062
3063 // AVX 3-operands scalar float-point arithmetic instructions
3064
3065 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3066 assert(VM_Version::supports_avx(), "");
3067 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3068 }
3069
3070 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3071 assert(VM_Version::supports_avx(), "");
3072 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3073 }
3074
3075 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3076 assert(VM_Version::supports_avx(), "");
3077 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3078 }
3079
3080 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3081 assert(VM_Version::supports_avx(), "");
3082 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3083 }
3084
3085 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3086 assert(VM_Version::supports_avx(), "");
3087 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3088 }
3089
3090 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3091 assert(VM_Version::supports_avx(), "");
3092 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3093 }
3094
3095 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3096 assert(VM_Version::supports_avx(), "");
3097 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3098 }
3099
3100 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3101 assert(VM_Version::supports_avx(), "");
3102 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3103 }
3104
3105 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3106 assert(VM_Version::supports_avx(), "");
3107 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3108 }
3109
3110 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3111 assert(VM_Version::supports_avx(), "");
3112 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3113 }
3114
3115 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3116 assert(VM_Version::supports_avx(), "");
3117 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3118 }
3119
3120 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3121 assert(VM_Version::supports_avx(), "");
3122 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3123 }
3124
3125 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3126 assert(VM_Version::supports_avx(), "");
3127 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3128 }
3129
3130 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3131 assert(VM_Version::supports_avx(), "");
3132 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3133 }
3134
3135 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3136 assert(VM_Version::supports_avx(), "");
3137 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3138 }
3139
3140 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3141 assert(VM_Version::supports_avx(), "");
3142 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3143 }
3144
3145 //====================VECTOR ARITHMETIC=====================================
3146
3147 // Float-point vector arithmetic
3148
3149 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3150 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3151 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3152 }
3153
3154 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3155 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3156 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3157 }
3158
3159 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3160 assert(VM_Version::supports_avx(), "");
3161 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3162 }
3163
3164 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3165 assert(VM_Version::supports_avx(), "");
3166 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3167 }
3168
3169 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3170 assert(VM_Version::supports_avx(), "");
3171 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3172 }
3173
3174 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3175 assert(VM_Version::supports_avx(), "");
3176 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3177 }
3178
3179 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3180 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3181 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3182 }
3183
3184 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3185 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3186 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3187 }
3188
3189 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3190 assert(VM_Version::supports_avx(), "");
3191 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3192 }
3193
3194 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3195 assert(VM_Version::supports_avx(), "");
3196 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3197 }
3198
3199 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3200 assert(VM_Version::supports_avx(), "");
3201 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3202 }
3203
3204 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3205 assert(VM_Version::supports_avx(), "");
3206 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3207 }
3208
3209 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3210 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3211 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3212 }
3213
3214 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3215 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3216 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3217 }
3218
3219 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3220 assert(VM_Version::supports_avx(), "");
3221 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3222 }
3223
3224 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3225 assert(VM_Version::supports_avx(), "");
3226 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3227 }
3228
3229 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3230 assert(VM_Version::supports_avx(), "");
3231 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3232 }
3233
3234 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3235 assert(VM_Version::supports_avx(), "");
3236 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3237 }
3238
3239 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3240 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3241 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3242 }
3243
3244 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3245 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3246 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3247 }
3248
3249 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3250 assert(VM_Version::supports_avx(), "");
3251 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3252 }
3253
3254 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3255 assert(VM_Version::supports_avx(), "");
3256 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3257 }
3258
3259 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3260 assert(VM_Version::supports_avx(), "");
3261 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3262 }
3263
3264 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3265 assert(VM_Version::supports_avx(), "");
3266 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3267 }
3268
3269 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3270 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3271 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3272 }
3273
3274 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3275 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3276 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3277 }
3278
3279 void Assembler::andps(XMMRegister dst, Address src) {
3280 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3281 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3282 }
3283
3284 void Assembler::andpd(XMMRegister dst, Address src) {
3285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3286 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3287 }
3288
3289 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3290 assert(VM_Version::supports_avx(), "");
3291 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3292 }
3293
3294 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3295 assert(VM_Version::supports_avx(), "");
3296 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3297 }
3298
3299 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3300 assert(VM_Version::supports_avx(), "");
3301 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3302 }
3303
3304 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3305 assert(VM_Version::supports_avx(), "");
3306 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3307 }
3308
3309 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3310 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3311 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3312 }
3313
3314 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3315 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3316 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3317 }
3318
3319 void Assembler::xorpd(XMMRegister dst, Address src) {
3320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3321 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3322 }
3323
3324 void Assembler::xorps(XMMRegister dst, Address src) {
3325 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3326 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3327 }
3328
3329 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3330 assert(VM_Version::supports_avx(), "");
3331 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3332 }
3333
3334 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3335 assert(VM_Version::supports_avx(), "");
3336 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3337 }
3338
3339 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3340 assert(VM_Version::supports_avx(), "");
3341 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3342 }
3343
3344 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3345 assert(VM_Version::supports_avx(), "");
3346 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3347 }
3348
3349
3350 // Integer vector arithmetic
3351 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3353 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3354 }
3355
3356 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3357 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3358 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3359 }
3360
3361 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3363 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3364 }
3365
3366 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3368 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3369 }
3370
3371 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3372 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3373 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3374 }
3375
3376 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3377 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3378 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3379 }
3380
3381 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3382 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3383 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3384 }
3385
3386 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3387 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3388 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3389 }
3390
3391 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3392 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3393 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3394 }
3395
3396 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3397 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3398 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3399 }
3400
3401 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3402 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3403 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3404 }
3405
3406 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3407 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3408 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3409 }
3410
3411 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3412 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3413 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3414 }
3415
3416 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3417 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3418 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3419 }
3420
3421 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3423 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3424 }
3425
3426 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3427 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3428 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3429 }
3430
3431 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3432 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3433 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3434 }
3435
3436 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3437 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3438 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3439 }
3440
3441 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3442 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3443 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3444 }
3445
3446 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3447 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3448 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3449 }
3450
3451 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3452 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3453 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3454 }
3455
3456 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3457 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3458 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3459 }
3460
3461 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3462 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3463 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3464 }
3465
3466 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3467 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3468 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3469 }
3470
3471 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3472 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3473 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3474 }
3475
3476 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3477 assert(VM_Version::supports_sse4_1(), "");
3478 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3479 emit_int8(0x40);
3480 emit_int8((unsigned char)(0xC0 | encode));
3481 }
3482
3483 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3484 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3485 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3486 }
3487
3488 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3489 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3490 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3491 emit_int8(0x40);
3492 emit_int8((unsigned char)(0xC0 | encode));
3493 }
3494
3495 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3496 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3497 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3498 }
3499
3500 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3501 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3502 InstructionMark im(this);
3503 int dst_enc = dst->encoding();
3504 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3505 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3506 emit_int8(0x40);
3507 emit_operand(dst, src);
3508 }
3509
3510 // Shift packed integers left by specified number of bits.
3511 void Assembler::psllw(XMMRegister dst, int shift) {
3512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3513 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3514 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3515 emit_int8(0x71);
3516 emit_int8((unsigned char)(0xC0 | encode));
3517 emit_int8(shift & 0xFF);
3518 }
3519
3520 void Assembler::pslld(XMMRegister dst, int shift) {
3521 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3522 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3523 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3524 emit_int8(0x72);
3525 emit_int8((unsigned char)(0xC0 | encode));
3526 emit_int8(shift & 0xFF);
3527 }
3528
3529 void Assembler::psllq(XMMRegister dst, int shift) {
3530 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3531 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3532 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3533 emit_int8(0x73);
3534 emit_int8((unsigned char)(0xC0 | encode));
3535 emit_int8(shift & 0xFF);
3536 }
3537
3538 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3539 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3540 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3541 }
3542
3543 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3544 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3545 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3546 }
3547
3548 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3550 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3551 }
3552
3553 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3554 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3555 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3556 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3557 emit_int8(shift & 0xFF);
3558 }
3559
3560 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3561 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3562 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3563 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3564 emit_int8(shift & 0xFF);
3565 }
3566
3567 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3568 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3569 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3570 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3571 emit_int8(shift & 0xFF);
3572 }
3573
3574 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3575 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3576 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3577 }
3578
3579 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3580 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3581 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3582 }
3583
3584 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3585 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3586 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3587 }
3588
3589 // Shift packed integers logically right by specified number of bits.
3590 void Assembler::psrlw(XMMRegister dst, int shift) {
3591 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3592 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3593 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3594 emit_int8(0x71);
3595 emit_int8((unsigned char)(0xC0 | encode));
3596 emit_int8(shift & 0xFF);
3597 }
3598
3599 void Assembler::psrld(XMMRegister dst, int shift) {
3600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3601 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3602 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3603 emit_int8(0x72);
3604 emit_int8((unsigned char)(0xC0 | encode));
3605 emit_int8(shift & 0xFF);
3606 }
3607
3608 void Assembler::psrlq(XMMRegister dst, int shift) {
3609 // Do not confuse it with psrldq SSE2 instruction which
3610 // shifts 128 bit value in xmm register by number of bytes.
3611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3612 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3613 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3614 emit_int8(0x73);
3615 emit_int8((unsigned char)(0xC0 | encode));
3616 emit_int8(shift & 0xFF);
3617 }
3618
3619 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3621 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3622 }
3623
3624 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3626 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3627 }
3628
3629 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3631 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3632 }
3633
3634 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3635 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3636 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3637 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3638 emit_int8(shift & 0xFF);
3639 }
3640
3641 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3642 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3643 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3644 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3645 emit_int8(shift & 0xFF);
3646 }
3647
3648 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3649 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3650 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3651 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3652 emit_int8(shift & 0xFF);
3653 }
3654
3655 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3656 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3657 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3658 }
3659
3660 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3661 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3662 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3663 }
3664
3665 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3666 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3667 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3668 }
3669
3670 // Shift packed integers arithmetically right by specified number of bits.
3671 void Assembler::psraw(XMMRegister dst, int shift) {
3672 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3673 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3674 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3675 emit_int8(0x71);
3676 emit_int8((unsigned char)(0xC0 | encode));
3677 emit_int8(shift & 0xFF);
3678 }
3679
3680 void Assembler::psrad(XMMRegister dst, int shift) {
3681 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3682 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3683 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3684 emit_int8(0x72);
3685 emit_int8((unsigned char)(0xC0 | encode));
3686 emit_int8(shift & 0xFF);
3687 }
3688
3689 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3690 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3691 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3692 }
3693
3694 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3695 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3696 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3697 }
3698
3699 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3700 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3701 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3702 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3703 emit_int8(shift & 0xFF);
3704 }
3705
3706 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3707 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3708 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3709 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3710 emit_int8(shift & 0xFF);
3711 }
3712
3713 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3714 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3715 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3716 }
3717
3718 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3719 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3720 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3721 }
3722
3723
3724 // AND packed integers
3725 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3727 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3728 }
3729
3730 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3731 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3732 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3733 }
3734
3735 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3736 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3737 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3738 }
3739
3740 void Assembler::por(XMMRegister dst, XMMRegister src) {
3741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3742 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3743 }
3744
3745 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3746 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3747 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3748 }
3749
3750 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3751 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3752 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3753 }
3754
3755 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3757 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3758 }
3759
3760 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3761 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3762 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3763 }
3764
3765 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3766 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3767 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3768 }
3769
3770
3771 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3772 assert(VM_Version::supports_avx(), "");
3773 bool vector256 = true;
3774 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3775 emit_int8(0x18);
3776 emit_int8((unsigned char)(0xC0 | encode));
3777 // 0x00 - insert into lower 128 bits
3778 // 0x01 - insert into upper 128 bits
3779 emit_int8(0x01);
3780 }
3781
3782 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3783 assert(VM_Version::supports_avx(), "");
3784 InstructionMark im(this);
3785 bool vector256 = true;
3786 assert(dst != xnoreg, "sanity");
3787 int dst_enc = dst->encoding();
3788 // swap src<->dst for encoding
3789 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3790 emit_int8(0x18);
3791 emit_operand(dst, src);
3792 // 0x01 - insert into upper 128 bits
3793 emit_int8(0x01);
3794 }
3795
3796 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3797 assert(VM_Version::supports_avx(), "");
3798 InstructionMark im(this);
3799 bool vector256 = true;
3800 assert(src != xnoreg, "sanity");
3801 int src_enc = src->encoding();
3802 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3803 emit_int8(0x19);
3804 emit_operand(src, dst);
3805 // 0x01 - extract from upper 128 bits
3806 emit_int8(0x01);
3807 }
3808
3809 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3810 assert(VM_Version::supports_avx2(), "");
3811 bool vector256 = true;
3812 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3813 emit_int8(0x38);
3814 emit_int8((unsigned char)(0xC0 | encode));
3815 // 0x00 - insert into lower 128 bits
3816 // 0x01 - insert into upper 128 bits
3817 emit_int8(0x01);
3818 }
3819
3820 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3821 assert(VM_Version::supports_avx2(), "");
3822 InstructionMark im(this);
3823 bool vector256 = true;
3824 assert(dst != xnoreg, "sanity");
3825 int dst_enc = dst->encoding();
3826 // swap src<->dst for encoding
3827 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3828 emit_int8(0x38);
3829 emit_operand(dst, src);
3830 // 0x01 - insert into upper 128 bits
3831 emit_int8(0x01);
3832 }
3833
3834 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3835 assert(VM_Version::supports_avx2(), "");
3836 InstructionMark im(this);
3837 bool vector256 = true;
3838 assert(src != xnoreg, "sanity");
3839 int src_enc = src->encoding();
3840 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3841 emit_int8(0x39);
3842 emit_operand(src, dst);
3843 // 0x01 - extract from upper 128 bits
3844 emit_int8(0x01);
3845 }
3846
3847 // duplicate 4-bytes integer data from src into 8 locations in dest
3848 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3849 assert(VM_Version::supports_avx2(), "");
3850 bool vector256 = true;
3851 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3852 emit_int8(0x58);
3853 emit_int8((unsigned char)(0xC0 | encode));
3854 }
3855
3856 // Carry-Less Multiplication Quadword
3857 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
3858 assert(VM_Version::supports_clmul(), "");
3859 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
3860 emit_int8(0x44);
3861 emit_int8((unsigned char)(0xC0 | encode));
3862 emit_int8((unsigned char)mask);
3863 }
3864
3865 // Carry-Less Multiplication Quadword
3866 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3867 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3868 bool vector256 = false;
3869 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3870 emit_int8(0x44);
3871 emit_int8((unsigned char)(0xC0 | encode));
3872 emit_int8((unsigned char)mask);
3873 }
3874
3875 void Assembler::vzeroupper() {
3876 assert(VM_Version::supports_avx(), "");
3877 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3878 emit_int8(0x77);
3879 }
3880
3881
3882 #ifndef _LP64
3883 // 32bit only pieces of the assembler
3884
3885 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3886 // NO PREFIX AS NEVER 64BIT
3887 InstructionMark im(this);
3888 emit_int8((unsigned char)0x81);
3889 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3890 emit_data(imm32, rspec, 0);
3891 }
3892
3893 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3894 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3895 InstructionMark im(this);
3896 emit_int8((unsigned char)0x81);
3897 emit_operand(rdi, src1);
3898 emit_data(imm32, rspec, 0);
3899 }
3900
3901 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3902 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3903 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3904 void Assembler::cmpxchg8(Address adr) {
3905 InstructionMark im(this);
3906 emit_int8(0x0F);
3907 emit_int8((unsigned char)0xC7);
3908 emit_operand(rcx, adr);
3909 }
3910
3911 void Assembler::decl(Register dst) {
3912 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3913 emit_int8(0x48 | dst->encoding());
3914 }
3915
3916 #endif // _LP64
3917
3918 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3919
3920 void Assembler::fabs() {
3921 emit_int8((unsigned char)0xD9);
3922 emit_int8((unsigned char)0xE1);
3923 }
3924
3925 void Assembler::fadd(int i) {
3926 emit_farith(0xD8, 0xC0, i);
3927 }
3928
3929 void Assembler::fadd_d(Address src) {
3930 InstructionMark im(this);
3931 emit_int8((unsigned char)0xDC);
3932 emit_operand32(rax, src);
3933 }
3934
3935 void Assembler::fadd_s(Address src) {
3936 InstructionMark im(this);
3937 emit_int8((unsigned char)0xD8);
3938 emit_operand32(rax, src);
3939 }
3940
3941 void Assembler::fadda(int i) {
3942 emit_farith(0xDC, 0xC0, i);
3943 }
3944
3945 void Assembler::faddp(int i) {
3946 emit_farith(0xDE, 0xC0, i);
3947 }
3948
3949 void Assembler::fchs() {
3950 emit_int8((unsigned char)0xD9);
3951 emit_int8((unsigned char)0xE0);
3952 }
3953
3954 void Assembler::fcom(int i) {
3955 emit_farith(0xD8, 0xD0, i);
3956 }
3957
3958 void Assembler::fcomp(int i) {
3959 emit_farith(0xD8, 0xD8, i);
3960 }
3961
3962 void Assembler::fcomp_d(Address src) {
3963 InstructionMark im(this);
3964 emit_int8((unsigned char)0xDC);
3965 emit_operand32(rbx, src);
3966 }
3967
3968 void Assembler::fcomp_s(Address src) {
3969 InstructionMark im(this);
3970 emit_int8((unsigned char)0xD8);
3971 emit_operand32(rbx, src);
3972 }
3973
3974 void Assembler::fcompp() {
3975 emit_int8((unsigned char)0xDE);
3976 emit_int8((unsigned char)0xD9);
3977 }
3978
3979 void Assembler::fcos() {
3980 emit_int8((unsigned char)0xD9);
3981 emit_int8((unsigned char)0xFF);
3982 }
3983
3984 void Assembler::fdecstp() {
3985 emit_int8((unsigned char)0xD9);
3986 emit_int8((unsigned char)0xF6);
3987 }
3988
3989 void Assembler::fdiv(int i) {
3990 emit_farith(0xD8, 0xF0, i);
3991 }
3992
3993 void Assembler::fdiv_d(Address src) {
3994 InstructionMark im(this);
3995 emit_int8((unsigned char)0xDC);
3996 emit_operand32(rsi, src);
3997 }
3998
3999 void Assembler::fdiv_s(Address src) {
4000 InstructionMark im(this);
4001 emit_int8((unsigned char)0xD8);
4002 emit_operand32(rsi, src);
4003 }
4004
4005 void Assembler::fdiva(int i) {
4006 emit_farith(0xDC, 0xF8, i);
4007 }
4008
4009 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
4010 // is erroneous for some of the floating-point instructions below.
4011
4012 void Assembler::fdivp(int i) {
4013 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
4014 }
4015
4016 void Assembler::fdivr(int i) {
4017 emit_farith(0xD8, 0xF8, i);
4018 }
4019
4020 void Assembler::fdivr_d(Address src) {
4021 InstructionMark im(this);
4022 emit_int8((unsigned char)0xDC);
4023 emit_operand32(rdi, src);
4024 }
4025
4026 void Assembler::fdivr_s(Address src) {
4027 InstructionMark im(this);
4028 emit_int8((unsigned char)0xD8);
4029 emit_operand32(rdi, src);
4030 }
4031
4032 void Assembler::fdivra(int i) {
4033 emit_farith(0xDC, 0xF0, i);
4034 }
4035
4036 void Assembler::fdivrp(int i) {
4037 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
4038 }
4039
4040 void Assembler::ffree(int i) {
4041 emit_farith(0xDD, 0xC0, i);
4042 }
4043
4044 void Assembler::fild_d(Address adr) {
4045 InstructionMark im(this);
4046 emit_int8((unsigned char)0xDF);
4047 emit_operand32(rbp, adr);
4048 }
4049
4050 void Assembler::fild_s(Address adr) {
4051 InstructionMark im(this);
4052 emit_int8((unsigned char)0xDB);
4053 emit_operand32(rax, adr);
4054 }
4055
4056 void Assembler::fincstp() {
4057 emit_int8((unsigned char)0xD9);
4058 emit_int8((unsigned char)0xF7);
4059 }
4060
4061 void Assembler::finit() {
4062 emit_int8((unsigned char)0x9B);
4063 emit_int8((unsigned char)0xDB);
4064 emit_int8((unsigned char)0xE3);
4065 }
4066
4067 void Assembler::fist_s(Address adr) {
4068 InstructionMark im(this);
4069 emit_int8((unsigned char)0xDB);
4070 emit_operand32(rdx, adr);
4071 }
4072
4073 void Assembler::fistp_d(Address adr) {
4074 InstructionMark im(this);
4075 emit_int8((unsigned char)0xDF);
4076 emit_operand32(rdi, adr);
4077 }
4078
4079 void Assembler::fistp_s(Address adr) {
4080 InstructionMark im(this);
4081 emit_int8((unsigned char)0xDB);
4082 emit_operand32(rbx, adr);
4083 }
4084
4085 void Assembler::fld1() {
4086 emit_int8((unsigned char)0xD9);
4087 emit_int8((unsigned char)0xE8);
4088 }
4089
4090 void Assembler::fld_d(Address adr) {
4091 InstructionMark im(this);
4092 emit_int8((unsigned char)0xDD);
4093 emit_operand32(rax, adr);
4094 }
4095
4096 void Assembler::fld_s(Address adr) {
4097 InstructionMark im(this);
4098 emit_int8((unsigned char)0xD9);
4099 emit_operand32(rax, adr);
4100 }
4101
4102
4103 void Assembler::fld_s(int index) {
4104 emit_farith(0xD9, 0xC0, index);
4105 }
4106
4107 void Assembler::fld_x(Address adr) {
4108 InstructionMark im(this);
4109 emit_int8((unsigned char)0xDB);
4110 emit_operand32(rbp, adr);
4111 }
4112
4113 void Assembler::fldcw(Address src) {
4114 InstructionMark im(this);
4115 emit_int8((unsigned char)0xD9);
4116 emit_operand32(rbp, src);
4117 }
4118
4119 void Assembler::fldenv(Address src) {
4120 InstructionMark im(this);
4121 emit_int8((unsigned char)0xD9);
4122 emit_operand32(rsp, src);
4123 }
4124
4125 void Assembler::fldlg2() {
4126 emit_int8((unsigned char)0xD9);
4127 emit_int8((unsigned char)0xEC);
4128 }
4129
4130 void Assembler::fldln2() {
4131 emit_int8((unsigned char)0xD9);
4132 emit_int8((unsigned char)0xED);
4133 }
4134
4135 void Assembler::fldz() {
4136 emit_int8((unsigned char)0xD9);
4137 emit_int8((unsigned char)0xEE);
4138 }
4139
4140 void Assembler::flog() {
4141 fldln2();
4142 fxch();
4143 fyl2x();
4144 }
4145
4146 void Assembler::flog10() {
4147 fldlg2();
4148 fxch();
4149 fyl2x();
4150 }
4151
4152 void Assembler::fmul(int i) {
4153 emit_farith(0xD8, 0xC8, i);
4154 }
4155
4156 void Assembler::fmul_d(Address src) {
4157 InstructionMark im(this);
4158 emit_int8((unsigned char)0xDC);
4159 emit_operand32(rcx, src);
4160 }
4161
4162 void Assembler::fmul_s(Address src) {
4163 InstructionMark im(this);
4164 emit_int8((unsigned char)0xD8);
4165 emit_operand32(rcx, src);
4166 }
4167
4168 void Assembler::fmula(int i) {
4169 emit_farith(0xDC, 0xC8, i);
4170 }
4171
4172 void Assembler::fmulp(int i) {
4173 emit_farith(0xDE, 0xC8, i);
4174 }
4175
4176 void Assembler::fnsave(Address dst) {
4177 InstructionMark im(this);
4178 emit_int8((unsigned char)0xDD);
4179 emit_operand32(rsi, dst);
4180 }
4181
4182 void Assembler::fnstcw(Address src) {
4183 InstructionMark im(this);
4184 emit_int8((unsigned char)0x9B);
4185 emit_int8((unsigned char)0xD9);
4186 emit_operand32(rdi, src);
4187 }
4188
4189 void Assembler::fnstsw_ax() {
4190 emit_int8((unsigned char)0xDF);
4191 emit_int8((unsigned char)0xE0);
4192 }
4193
4194 void Assembler::fprem() {
4195 emit_int8((unsigned char)0xD9);
4196 emit_int8((unsigned char)0xF8);
4197 }
4198
4199 void Assembler::fprem1() {
4200 emit_int8((unsigned char)0xD9);
4201 emit_int8((unsigned char)0xF5);
4202 }
4203
4204 void Assembler::frstor(Address src) {
4205 InstructionMark im(this);
4206 emit_int8((unsigned char)0xDD);
4207 emit_operand32(rsp, src);
4208 }
4209
4210 void Assembler::fsin() {
4211 emit_int8((unsigned char)0xD9);
4212 emit_int8((unsigned char)0xFE);
4213 }
4214
4215 void Assembler::fsqrt() {
4216 emit_int8((unsigned char)0xD9);
4217 emit_int8((unsigned char)0xFA);
4218 }
4219
4220 void Assembler::fst_d(Address adr) {
4221 InstructionMark im(this);
4222 emit_int8((unsigned char)0xDD);
4223 emit_operand32(rdx, adr);
4224 }
4225
4226 void Assembler::fst_s(Address adr) {
4227 InstructionMark im(this);
4228 emit_int8((unsigned char)0xD9);
4229 emit_operand32(rdx, adr);
4230 }
4231
4232 void Assembler::fstp_d(Address adr) {
4233 InstructionMark im(this);
4234 emit_int8((unsigned char)0xDD);
4235 emit_operand32(rbx, adr);
4236 }
4237
4238 void Assembler::fstp_d(int index) {
4239 emit_farith(0xDD, 0xD8, index);
4240 }
4241
4242 void Assembler::fstp_s(Address adr) {
4243 InstructionMark im(this);
4244 emit_int8((unsigned char)0xD9);
4245 emit_operand32(rbx, adr);
4246 }
4247
4248 void Assembler::fstp_x(Address adr) {
4249 InstructionMark im(this);
4250 emit_int8((unsigned char)0xDB);
4251 emit_operand32(rdi, adr);
4252 }
4253
4254 void Assembler::fsub(int i) {
4255 emit_farith(0xD8, 0xE0, i);
4256 }
4257
4258 void Assembler::fsub_d(Address src) {
4259 InstructionMark im(this);
4260 emit_int8((unsigned char)0xDC);
4261 emit_operand32(rsp, src);
4262 }
4263
4264 void Assembler::fsub_s(Address src) {
4265 InstructionMark im(this);
4266 emit_int8((unsigned char)0xD8);
4267 emit_operand32(rsp, src);
4268 }
4269
4270 void Assembler::fsuba(int i) {
4271 emit_farith(0xDC, 0xE8, i);
4272 }
4273
4274 void Assembler::fsubp(int i) {
4275 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4276 }
4277
4278 void Assembler::fsubr(int i) {
4279 emit_farith(0xD8, 0xE8, i);
4280 }
4281
4282 void Assembler::fsubr_d(Address src) {
4283 InstructionMark im(this);
4284 emit_int8((unsigned char)0xDC);
4285 emit_operand32(rbp, src);
4286 }
4287
4288 void Assembler::fsubr_s(Address src) {
4289 InstructionMark im(this);
4290 emit_int8((unsigned char)0xD8);
4291 emit_operand32(rbp, src);
4292 }
4293
4294 void Assembler::fsubra(int i) {
4295 emit_farith(0xDC, 0xE0, i);
4296 }
4297
4298 void Assembler::fsubrp(int i) {
4299 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4300 }
4301
4302 void Assembler::ftan() {
4303 emit_int8((unsigned char)0xD9);
4304 emit_int8((unsigned char)0xF2);
4305 emit_int8((unsigned char)0xDD);
4306 emit_int8((unsigned char)0xD8);
4307 }
4308
4309 void Assembler::ftst() {
4310 emit_int8((unsigned char)0xD9);
4311 emit_int8((unsigned char)0xE4);
4312 }
4313
4314 void Assembler::fucomi(int i) {
4315 // make sure the instruction is supported (introduced for P6, together with cmov)
4316 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4317 emit_farith(0xDB, 0xE8, i);
4318 }
4319
4320 void Assembler::fucomip(int i) {
4321 // make sure the instruction is supported (introduced for P6, together with cmov)
4322 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4323 emit_farith(0xDF, 0xE8, i);
4324 }
4325
4326 void Assembler::fwait() {
4327 emit_int8((unsigned char)0x9B);
4328 }
4329
4330 void Assembler::fxch(int i) {
4331 emit_farith(0xD9, 0xC8, i);
4332 }
4333
4334 void Assembler::fyl2x() {
4335 emit_int8((unsigned char)0xD9);
4336 emit_int8((unsigned char)0xF1);
4337 }
4338
4339 void Assembler::frndint() {
4340 emit_int8((unsigned char)0xD9);
4341 emit_int8((unsigned char)0xFC);
4342 }
4343
4344 void Assembler::f2xm1() {
4345 emit_int8((unsigned char)0xD9);
4346 emit_int8((unsigned char)0xF0);
4347 }
4348
4349 void Assembler::fldl2e() {
4350 emit_int8((unsigned char)0xD9);
4351 emit_int8((unsigned char)0xEA);
4352 }
4353
4354 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4355 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4356 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4357 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4358
4359 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4360 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4361 if (pre > 0) {
4362 emit_int8(simd_pre[pre]);
4363 }
4364 if (rex_w) {
4365 prefixq(adr, xreg);
4366 } else {
4367 prefix(adr, xreg);
4368 }
4369 if (opc > 0) {
4370 emit_int8(0x0F);
4371 int opc2 = simd_opc[opc];
4372 if (opc2 > 0) {
4373 emit_int8(opc2);
4374 }
4375 }
4376 }
4377
4378 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4379 if (pre > 0) {
4380 emit_int8(simd_pre[pre]);
4381 }
4382 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4383 prefix_and_encode(dst_enc, src_enc);
4384 if (opc > 0) {
4385 emit_int8(0x0F);
4386 int opc2 = simd_opc[opc];
4387 if (opc2 > 0) {
4388 emit_int8(opc2);
4389 }
4390 }
4391 return encode;
4392 }
4393
4394
4395 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4396 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4397 prefix(VEX_3bytes);
4398
4399 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4400 byte1 = (~byte1) & 0xE0;
4401 byte1 |= opc;
4402 emit_int8(byte1);
4403
4404 int byte2 = ((~nds_enc) & 0xf) << 3;
4405 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4406 emit_int8(byte2);
4407 } else {
4408 prefix(VEX_2bytes);
4409
4410 int byte1 = vex_r ? VEX_R : 0;
4411 byte1 = (~byte1) & 0x80;
4412 byte1 |= ((~nds_enc) & 0xf) << 3;
4413 byte1 |= (vector256 ? 4 : 0) | pre;
4414 emit_int8(byte1);
4415 }
4416 }
4417
4418 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4419 bool vex_r = (xreg_enc >= 8);
4420 bool vex_b = adr.base_needs_rex();
4421 bool vex_x = adr.index_needs_rex();
4422 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4423 }
4424
4425 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4426 bool vex_r = (dst_enc >= 8);
4427 bool vex_b = (src_enc >= 8);
4428 bool vex_x = false;
4429 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4430 return (((dst_enc & 7) << 3) | (src_enc & 7));
4431 }
4432
4433
4434 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4435 if (UseAVX > 0) {
4436 int xreg_enc = xreg->encoding();
4437 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4438 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4439 } else {
4440 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4441 rex_prefix(adr, xreg, pre, opc, rex_w);
4442 }
4443 }
4444
4445 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4446 int dst_enc = dst->encoding();
4447 int src_enc = src->encoding();
4448 if (UseAVX > 0) {
4449 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4450 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4451 } else {
4452 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4453 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4454 }
4455 }
4456
4457 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4458 InstructionMark im(this);
4459 simd_prefix(dst, dst, src, pre);
4460 emit_int8(opcode);
4461 emit_operand(dst, src);
4462 }
4463
4464 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4465 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4466 emit_int8(opcode);
4467 emit_int8((unsigned char)(0xC0 | encode));
4468 }
4469
4470 // Versions with no second source register (non-destructive source).
4471 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4472 InstructionMark im(this);
4473 simd_prefix(dst, xnoreg, src, pre);
4474 emit_int8(opcode);
4475 emit_operand(dst, src);
4476 }
4477
4478 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4479 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4480 emit_int8(opcode);
4481 emit_int8((unsigned char)(0xC0 | encode));
4482 }
4483
4484 // 3-operands AVX instructions
4485 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4486 Address src, VexSimdPrefix pre, bool vector256) {
4487 InstructionMark im(this);
4488 vex_prefix(dst, nds, src, pre, vector256);
4489 emit_int8(opcode);
4490 emit_operand(dst, src);
4491 }
4492
4493 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4494 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4495 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4496 emit_int8(opcode);
4497 emit_int8((unsigned char)(0xC0 | encode));
4498 }
4499
4500 #ifndef _LP64
4501
4502 void Assembler::incl(Register dst) {
4503 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4504 emit_int8(0x40 | dst->encoding());
4505 }
4506
4507 void Assembler::lea(Register dst, Address src) {
4508 leal(dst, src);
4509 }
4510
4511 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4512 InstructionMark im(this);
4513 emit_int8((unsigned char)0xC7);
4514 emit_operand(rax, dst);
4515 emit_data((int)imm32, rspec, 0);
4516 }
4517
4518 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4519 InstructionMark im(this);
4520 int encode = prefix_and_encode(dst->encoding());
4521 emit_int8((unsigned char)(0xB8 | encode));
4522 emit_data((int)imm32, rspec, 0);
4523 }
4524
4525 void Assembler::popa() { // 32bit
4526 emit_int8(0x61);
4527 }
4528
4529 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4530 InstructionMark im(this);
4531 emit_int8(0x68);
4532 emit_data(imm32, rspec, 0);
4533 }
4534
4535 void Assembler::pusha() { // 32bit
4536 emit_int8(0x60);
4537 }
4538
4539 void Assembler::set_byte_if_not_zero(Register dst) {
4540 emit_int8(0x0F);
4541 emit_int8((unsigned char)0x95);
4542 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4543 }
4544
4545 void Assembler::shldl(Register dst, Register src) {
4546 emit_int8(0x0F);
4547 emit_int8((unsigned char)0xA5);
4548 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4549 }
4550
4551 void Assembler::shrdl(Register dst, Register src) {
4552 emit_int8(0x0F);
4553 emit_int8((unsigned char)0xAD);
4554 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4555 }
4556
4557 #else // LP64
4558
4559 void Assembler::set_byte_if_not_zero(Register dst) {
4560 int enc = prefix_and_encode(dst->encoding(), true);
4561 emit_int8(0x0F);
4562 emit_int8((unsigned char)0x95);
4563 emit_int8((unsigned char)(0xE0 | enc));
4564 }
4565
4566 // 64bit only pieces of the assembler
4567 // This should only be used by 64bit instructions that can use rip-relative
4568 // it cannot be used by instructions that want an immediate value.
4569
4570 bool Assembler::reachable(AddressLiteral adr) {
4571 int64_t disp;
4572 // None will force a 64bit literal to the code stream. Likely a placeholder
4573 // for something that will be patched later and we need to certain it will
4574 // always be reachable.
4575 if (adr.reloc() == relocInfo::none) {
4576 return false;
4577 }
4578 if (adr.reloc() == relocInfo::internal_word_type) {
4579 // This should be rip relative and easily reachable.
4580 return true;
4581 }
4582 if (adr.reloc() == relocInfo::virtual_call_type ||
4583 adr.reloc() == relocInfo::opt_virtual_call_type ||
4584 adr.reloc() == relocInfo::static_call_type ||
4585 adr.reloc() == relocInfo::static_stub_type ) {
4586 // This should be rip relative within the code cache and easily
4587 // reachable until we get huge code caches. (At which point
4588 // ic code is going to have issues).
4589 return true;
4590 }
4591 if (adr.reloc() != relocInfo::external_word_type &&
4592 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4593 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4594 adr.reloc() != relocInfo::runtime_call_type ) {
4595 return false;
4596 }
4597
4598 // Stress the correction code
4599 if (ForceUnreachable) {
4600 // Must be runtimecall reloc, see if it is in the codecache
4601 // Flipping stuff in the codecache to be unreachable causes issues
4602 // with things like inline caches where the additional instructions
4603 // are not handled.
4604 if (CodeCache::find_blob(adr._target) == NULL) {
4605 return false;
4606 }
4607 }
4608 // For external_word_type/runtime_call_type if it is reachable from where we
4609 // are now (possibly a temp buffer) and where we might end up
4610 // anywhere in the codeCache then we are always reachable.
4611 // This would have to change if we ever save/restore shared code
4612 // to be more pessimistic.
4613 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4614 if (!is_simm32(disp)) return false;
4615 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4616 if (!is_simm32(disp)) return false;
4617
4618 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4619
4620 // Because rip relative is a disp + address_of_next_instruction and we
4621 // don't know the value of address_of_next_instruction we apply a fudge factor
4622 // to make sure we will be ok no matter the size of the instruction we get placed into.
4623 // We don't have to fudge the checks above here because they are already worst case.
4624
4625 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4626 // + 4 because better safe than sorry.
4627 const int fudge = 12 + 4;
4628 if (disp < 0) {
4629 disp -= fudge;
4630 } else {
4631 disp += fudge;
4632 }
4633 return is_simm32(disp);
4634 }
4635
4636 // Check if the polling page is not reachable from the code cache using rip-relative
4637 // addressing.
4638 bool Assembler::is_polling_page_far() {
4639 intptr_t addr = (intptr_t)os::get_polling_page();
4640 return ForceUnreachable ||
4641 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4642 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4643 }
4644
4645 void Assembler::emit_data64(jlong data,
4646 relocInfo::relocType rtype,
4647 int format) {
4648 if (rtype == relocInfo::none) {
4649 emit_int64(data);
4650 } else {
4651 emit_data64(data, Relocation::spec_simple(rtype), format);
4652 }
4653 }
4654
4655 void Assembler::emit_data64(jlong data,
4656 RelocationHolder const& rspec,
4657 int format) {
4658 assert(imm_operand == 0, "default format must be immediate in this file");
4659 assert(imm_operand == format, "must be immediate");
4660 assert(inst_mark() != NULL, "must be inside InstructionMark");
4661 // Do not use AbstractAssembler::relocate, which is not intended for
4662 // embedded words. Instead, relocate to the enclosing instruction.
4663 code_section()->relocate(inst_mark(), rspec, format);
4664 #ifdef ASSERT
4665 check_relocation(rspec, format);
4666 #endif
4667 emit_int64(data);
4668 }
4669
4670 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4671 if (reg_enc >= 8) {
4672 prefix(REX_B);
4673 reg_enc -= 8;
4674 } else if (byteinst && reg_enc >= 4) {
4675 prefix(REX);
4676 }
4677 return reg_enc;
4678 }
4679
4680 int Assembler::prefixq_and_encode(int reg_enc) {
4681 if (reg_enc < 8) {
4682 prefix(REX_W);
4683 } else {
4684 prefix(REX_WB);
4685 reg_enc -= 8;
4686 }
4687 return reg_enc;
4688 }
4689
4690 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4691 if (dst_enc < 8) {
4692 if (src_enc >= 8) {
4693 prefix(REX_B);
4694 src_enc -= 8;
4695 } else if (byteinst && src_enc >= 4) {
4696 prefix(REX);
4697 }
4698 } else {
4699 if (src_enc < 8) {
4700 prefix(REX_R);
4701 } else {
4702 prefix(REX_RB);
4703 src_enc -= 8;
4704 }
4705 dst_enc -= 8;
4706 }
4707 return dst_enc << 3 | src_enc;
4708 }
4709
4710 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4711 if (dst_enc < 8) {
4712 if (src_enc < 8) {
4713 prefix(REX_W);
4714 } else {
4715 prefix(REX_WB);
4716 src_enc -= 8;
4717 }
4718 } else {
4719 if (src_enc < 8) {
4720 prefix(REX_WR);
4721 } else {
4722 prefix(REX_WRB);
4723 src_enc -= 8;
4724 }
4725 dst_enc -= 8;
4726 }
4727 return dst_enc << 3 | src_enc;
4728 }
4729
4730 void Assembler::prefix(Register reg) {
4731 if (reg->encoding() >= 8) {
4732 prefix(REX_B);
4733 }
4734 }
4735
4736 void Assembler::prefix(Address adr) {
4737 if (adr.base_needs_rex()) {
4738 if (adr.index_needs_rex()) {
4739 prefix(REX_XB);
4740 } else {
4741 prefix(REX_B);
4742 }
4743 } else {
4744 if (adr.index_needs_rex()) {
4745 prefix(REX_X);
4746 }
4747 }
4748 }
4749
4750 void Assembler::prefixq(Address adr) {
4751 if (adr.base_needs_rex()) {
4752 if (adr.index_needs_rex()) {
4753 prefix(REX_WXB);
4754 } else {
4755 prefix(REX_WB);
4756 }
4757 } else {
4758 if (adr.index_needs_rex()) {
4759 prefix(REX_WX);
4760 } else {
4761 prefix(REX_W);
4762 }
4763 }
4764 }
4765
4766
4767 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4768 if (reg->encoding() < 8) {
4769 if (adr.base_needs_rex()) {
4770 if (adr.index_needs_rex()) {
4771 prefix(REX_XB);
4772 } else {
4773 prefix(REX_B);
4774 }
4775 } else {
4776 if (adr.index_needs_rex()) {
4777 prefix(REX_X);
4778 } else if (byteinst && reg->encoding() >= 4 ) {
4779 prefix(REX);
4780 }
4781 }
4782 } else {
4783 if (adr.base_needs_rex()) {
4784 if (adr.index_needs_rex()) {
4785 prefix(REX_RXB);
4786 } else {
4787 prefix(REX_RB);
4788 }
4789 } else {
4790 if (adr.index_needs_rex()) {
4791 prefix(REX_RX);
4792 } else {
4793 prefix(REX_R);
4794 }
4795 }
4796 }
4797 }
4798
4799 void Assembler::prefixq(Address adr, Register src) {
4800 if (src->encoding() < 8) {
4801 if (adr.base_needs_rex()) {
4802 if (adr.index_needs_rex()) {
4803 prefix(REX_WXB);
4804 } else {
4805 prefix(REX_WB);
4806 }
4807 } else {
4808 if (adr.index_needs_rex()) {
4809 prefix(REX_WX);
4810 } else {
4811 prefix(REX_W);
4812 }
4813 }
4814 } else {
4815 if (adr.base_needs_rex()) {
4816 if (adr.index_needs_rex()) {
4817 prefix(REX_WRXB);
4818 } else {
4819 prefix(REX_WRB);
4820 }
4821 } else {
4822 if (adr.index_needs_rex()) {
4823 prefix(REX_WRX);
4824 } else {
4825 prefix(REX_WR);
4826 }
4827 }
4828 }
4829 }
4830
4831 void Assembler::prefix(Address adr, XMMRegister reg) {
4832 if (reg->encoding() < 8) {
4833 if (adr.base_needs_rex()) {
4834 if (adr.index_needs_rex()) {
4835 prefix(REX_XB);
4836 } else {
4837 prefix(REX_B);
4838 }
4839 } else {
4840 if (adr.index_needs_rex()) {
4841 prefix(REX_X);
4842 }
4843 }
4844 } else {
4845 if (adr.base_needs_rex()) {
4846 if (adr.index_needs_rex()) {
4847 prefix(REX_RXB);
4848 } else {
4849 prefix(REX_RB);
4850 }
4851 } else {
4852 if (adr.index_needs_rex()) {
4853 prefix(REX_RX);
4854 } else {
4855 prefix(REX_R);
4856 }
4857 }
4858 }
4859 }
4860
4861 void Assembler::prefixq(Address adr, XMMRegister src) {
4862 if (src->encoding() < 8) {
4863 if (adr.base_needs_rex()) {
4864 if (adr.index_needs_rex()) {
4865 prefix(REX_WXB);
4866 } else {
4867 prefix(REX_WB);
4868 }
4869 } else {
4870 if (adr.index_needs_rex()) {
4871 prefix(REX_WX);
4872 } else {
4873 prefix(REX_W);
4874 }
4875 }
4876 } else {
4877 if (adr.base_needs_rex()) {
4878 if (adr.index_needs_rex()) {
4879 prefix(REX_WRXB);
4880 } else {
4881 prefix(REX_WRB);
4882 }
4883 } else {
4884 if (adr.index_needs_rex()) {
4885 prefix(REX_WRX);
4886 } else {
4887 prefix(REX_WR);
4888 }
4889 }
4890 }
4891 }
4892
4893 void Assembler::adcq(Register dst, int32_t imm32) {
4894 (void) prefixq_and_encode(dst->encoding());
4895 emit_arith(0x81, 0xD0, dst, imm32);
4896 }
4897
4898 void Assembler::adcq(Register dst, Address src) {
4899 InstructionMark im(this);
4900 prefixq(src, dst);
4901 emit_int8(0x13);
4902 emit_operand(dst, src);
4903 }
4904
4905 void Assembler::adcq(Register dst, Register src) {
4906 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4907 emit_arith(0x13, 0xC0, dst, src);
4908 }
4909
4910 void Assembler::addq(Address dst, int32_t imm32) {
4911 InstructionMark im(this);
4912 prefixq(dst);
4913 emit_arith_operand(0x81, rax, dst,imm32);
4914 }
4915
4916 void Assembler::addq(Address dst, Register src) {
4917 InstructionMark im(this);
4918 prefixq(dst, src);
4919 emit_int8(0x01);
4920 emit_operand(src, dst);
4921 }
4922
4923 void Assembler::addq(Register dst, int32_t imm32) {
4924 (void) prefixq_and_encode(dst->encoding());
4925 emit_arith(0x81, 0xC0, dst, imm32);
4926 }
4927
4928 void Assembler::addq(Register dst, Address src) {
4929 InstructionMark im(this);
4930 prefixq(src, dst);
4931 emit_int8(0x03);
4932 emit_operand(dst, src);
4933 }
4934
4935 void Assembler::addq(Register dst, Register src) {
4936 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4937 emit_arith(0x03, 0xC0, dst, src);
4938 }
4939
4940 void Assembler::adcxq(Register dst, Register src) {
4941 //assert(VM_Version::supports_adx(), "adx instructions not supported");
4942 emit_int8((unsigned char)0x66);
4943 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4944 emit_int8(0x0F);
4945 emit_int8(0x38);
4946 emit_int8((unsigned char)0xF6);
4947 emit_int8((unsigned char)(0xC0 | encode));
4948 }
4949
4950 void Assembler::adoxq(Register dst, Register src) {
4951 //assert(VM_Version::supports_adx(), "adx instructions not supported");
4952 emit_int8((unsigned char)0xF3);
4953 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4954 emit_int8(0x0F);
4955 emit_int8(0x38);
4956 emit_int8((unsigned char)0xF6);
4957 emit_int8((unsigned char)(0xC0 | encode));
4958 }
4959
4960 void Assembler::andq(Address dst, int32_t imm32) {
4961 InstructionMark im(this);
4962 prefixq(dst);
4963 emit_int8((unsigned char)0x81);
4964 emit_operand(rsp, dst, 4);
4965 emit_int32(imm32);
4966 }
4967
4968 void Assembler::andq(Register dst, int32_t imm32) {
4969 (void) prefixq_and_encode(dst->encoding());
4970 emit_arith(0x81, 0xE0, dst, imm32);
4971 }
4972
4973 void Assembler::andq(Register dst, Address src) {
4974 InstructionMark im(this);
4975 prefixq(src, dst);
4976 emit_int8(0x23);
4977 emit_operand(dst, src);
4978 }
4979
4980 void Assembler::andq(Register dst, Register src) {
4981 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4982 emit_arith(0x23, 0xC0, dst, src);
4983 }
4984
4985 void Assembler::andnq(Register dst, Register src1, Register src2) {
4986 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4987 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4988 emit_int8((unsigned char)0xF2);
4989 emit_int8((unsigned char)(0xC0 | encode));
4990 }
4991
4992 void Assembler::andnq(Register dst, Register src1, Address src2) {
4993 InstructionMark im(this);
4994 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4995 vex_prefix_0F38_q(dst, src1, src2);
4996 emit_int8((unsigned char)0xF2);
4997 emit_operand(dst, src2);
4998 }
4999
5000 void Assembler::bsfq(Register dst, Register src) {
5001 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5002 emit_int8(0x0F);
5003 emit_int8((unsigned char)0xBC);
5004 emit_int8((unsigned char)(0xC0 | encode));
5005 }
5006
5007 void Assembler::bsrq(Register dst, Register src) {
5008 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5009 emit_int8(0x0F);
5010 emit_int8((unsigned char)0xBD);
5011 emit_int8((unsigned char)(0xC0 | encode));
5012 }
5013
5014 void Assembler::bswapq(Register reg) {
5015 int encode = prefixq_and_encode(reg->encoding());
5016 emit_int8(0x0F);
5017 emit_int8((unsigned char)(0xC8 | encode));
5018 }
5019
5020 void Assembler::blsiq(Register dst, Register src) {
5021 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5022 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
5023 emit_int8((unsigned char)0xF3);
5024 emit_int8((unsigned char)(0xC0 | encode));
5025 }
5026
5027 void Assembler::blsiq(Register dst, Address src) {
5028 InstructionMark im(this);
5029 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5030 vex_prefix_0F38_q(rbx, dst, src);
5031 emit_int8((unsigned char)0xF3);
5032 emit_operand(rbx, src);
5033 }
5034
5035 void Assembler::blsmskq(Register dst, Register src) {
5036 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5037 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
5038 emit_int8((unsigned char)0xF3);
5039 emit_int8((unsigned char)(0xC0 | encode));
5040 }
5041
5042 void Assembler::blsmskq(Register dst, Address src) {
5043 InstructionMark im(this);
5044 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5045 vex_prefix_0F38_q(rdx, dst, src);
5046 emit_int8((unsigned char)0xF3);
5047 emit_operand(rdx, src);
5048 }
5049
5050 void Assembler::blsrq(Register dst, Register src) {
5051 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5052 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
5053 emit_int8((unsigned char)0xF3);
5054 emit_int8((unsigned char)(0xC0 | encode));
5055 }
5056
5057 void Assembler::blsrq(Register dst, Address src) {
5058 InstructionMark im(this);
5059 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5060 vex_prefix_0F38_q(rcx, dst, src);
5061 emit_int8((unsigned char)0xF3);
5062 emit_operand(rcx, src);
5063 }
5064
5065 void Assembler::cdqq() {
5066 prefix(REX_W);
5067 emit_int8((unsigned char)0x99);
5068 }
5069
5070 void Assembler::clflush(Address adr) {
5071 prefix(adr);
5072 emit_int8(0x0F);
5073 emit_int8((unsigned char)0xAE);
5074 emit_operand(rdi, adr);
5075 }
5076
5077 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5078 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5079 emit_int8(0x0F);
5080 emit_int8(0x40 | cc);
5081 emit_int8((unsigned char)(0xC0 | encode));
5082 }
5083
5084 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5085 InstructionMark im(this);
5086 prefixq(src, dst);
5087 emit_int8(0x0F);
5088 emit_int8(0x40 | cc);
5089 emit_operand(dst, src);
5090 }
5091
5092 void Assembler::cmpq(Address dst, int32_t imm32) {
5093 InstructionMark im(this);
5094 prefixq(dst);
5095 emit_int8((unsigned char)0x81);
5096 emit_operand(rdi, dst, 4);
5097 emit_int32(imm32);
5098 }
5099
5100 void Assembler::cmpq(Register dst, int32_t imm32) {
5101 (void) prefixq_and_encode(dst->encoding());
5102 emit_arith(0x81, 0xF8, dst, imm32);
5103 }
5104
5105 void Assembler::cmpq(Address dst, Register src) {
5106 InstructionMark im(this);
5107 prefixq(dst, src);
5108 emit_int8(0x3B);
5109 emit_operand(src, dst);
5110 }
5111
5112 void Assembler::cmpq(Register dst, Register src) {
5113 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5114 emit_arith(0x3B, 0xC0, dst, src);
5115 }
5116
5117 void Assembler::cmpq(Register dst, Address src) {
5118 InstructionMark im(this);
5119 prefixq(src, dst);
5120 emit_int8(0x3B);
5121 emit_operand(dst, src);
5122 }
5123
5124 void Assembler::cmpxchgq(Register reg, Address adr) {
5125 InstructionMark im(this);
5126 prefixq(adr, reg);
5127 emit_int8(0x0F);
5128 emit_int8((unsigned char)0xB1);
5129 emit_operand(reg, adr);
5130 }
5131
5132 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5133 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5134 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5135 emit_int8(0x2A);
5136 emit_int8((unsigned char)(0xC0 | encode));
5137 }
5138
5139 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5141 InstructionMark im(this);
5142 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5143 emit_int8(0x2A);
5144 emit_operand(dst, src);
5145 }
5146
5147 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5148 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5149 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5150 emit_int8(0x2A);
5151 emit_int8((unsigned char)(0xC0 | encode));
5152 }
5153
5154 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5155 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5156 InstructionMark im(this);
5157 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5158 emit_int8(0x2A);
5159 emit_operand(dst, src);
5160 }
5161
5162 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5164 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5165 emit_int8(0x2C);
5166 emit_int8((unsigned char)(0xC0 | encode));
5167 }
5168
5169 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5170 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5171 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5172 emit_int8(0x2C);
5173 emit_int8((unsigned char)(0xC0 | encode));
5174 }
5175
5176 void Assembler::decl(Register dst) {
5177 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5178 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5179 int encode = prefix_and_encode(dst->encoding());
5180 emit_int8((unsigned char)0xFF);
5181 emit_int8((unsigned char)(0xC8 | encode));
5182 }
5183
5184 void Assembler::decq(Register dst) {
5185 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5186 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5187 int encode = prefixq_and_encode(dst->encoding());
5188 emit_int8((unsigned char)0xFF);
5189 emit_int8(0xC8 | encode);
5190 }
5191
5192 void Assembler::decq(Address dst) {
5193 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5194 InstructionMark im(this);
5195 prefixq(dst);
5196 emit_int8((unsigned char)0xFF);
5197 emit_operand(rcx, dst);
5198 }
5199
5200 void Assembler::fxrstor(Address src) {
5201 prefixq(src);
5202 emit_int8(0x0F);
5203 emit_int8((unsigned char)0xAE);
5204 emit_operand(as_Register(1), src);
5205 }
5206
5207 void Assembler::fxsave(Address dst) {
5208 prefixq(dst);
5209 emit_int8(0x0F);
5210 emit_int8((unsigned char)0xAE);
5211 emit_operand(as_Register(0), dst);
5212 }
5213
5214 void Assembler::idivq(Register src) {
5215 int encode = prefixq_and_encode(src->encoding());
5216 emit_int8((unsigned char)0xF7);
5217 emit_int8((unsigned char)(0xF8 | encode));
5218 }
5219
5220 void Assembler::imulq(Register dst, Register src) {
5221 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5222 emit_int8(0x0F);
5223 emit_int8((unsigned char)0xAF);
5224 emit_int8((unsigned char)(0xC0 | encode));
5225 }
5226
5227 void Assembler::imulq(Register dst, Register src, int value) {
5228 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5229 if (is8bit(value)) {
5230 emit_int8(0x6B);
5231 emit_int8((unsigned char)(0xC0 | encode));
5232 emit_int8(value & 0xFF);
5233 } else {
5234 emit_int8(0x69);
5235 emit_int8((unsigned char)(0xC0 | encode));
5236 emit_int32(value);
5237 }
5238 }
5239
5240 void Assembler::imulq(Register dst, Address src) {
5241 InstructionMark im(this);
5242 prefixq(src, dst);
5243 emit_int8(0x0F);
5244 emit_int8((unsigned char) 0xAF);
5245 emit_operand(dst, src);
5246 }
5247
5248 void Assembler::incl(Register dst) {
5249 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5250 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5251 int encode = prefix_and_encode(dst->encoding());
5252 emit_int8((unsigned char)0xFF);
5253 emit_int8((unsigned char)(0xC0 | encode));
5254 }
5255
5256 void Assembler::incq(Register dst) {
5257 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5258 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5259 int encode = prefixq_and_encode(dst->encoding());
5260 emit_int8((unsigned char)0xFF);
5261 emit_int8((unsigned char)(0xC0 | encode));
5262 }
5263
5264 void Assembler::incq(Address dst) {
5265 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5266 InstructionMark im(this);
5267 prefixq(dst);
5268 emit_int8((unsigned char)0xFF);
5269 emit_operand(rax, dst);
5270 }
5271
5272 void Assembler::lea(Register dst, Address src) {
5273 leaq(dst, src);
5274 }
5275
5276 void Assembler::leaq(Register dst, Address src) {
5277 InstructionMark im(this);
5278 prefixq(src, dst);
5279 emit_int8((unsigned char)0x8D);
5280 emit_operand(dst, src);
5281 }
5282
5283 void Assembler::mov64(Register dst, int64_t imm64) {
5284 InstructionMark im(this);
5285 int encode = prefixq_and_encode(dst->encoding());
5286 emit_int8((unsigned char)(0xB8 | encode));
5287 emit_int64(imm64);
5288 }
5289
5290 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5291 InstructionMark im(this);
5292 int encode = prefixq_and_encode(dst->encoding());
5293 emit_int8(0xB8 | encode);
5294 emit_data64(imm64, rspec);
5295 }
5296
5297 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5298 InstructionMark im(this);
5299 int encode = prefix_and_encode(dst->encoding());
5300 emit_int8((unsigned char)(0xB8 | encode));
5301 emit_data((int)imm32, rspec, narrow_oop_operand);
5302 }
5303
5304 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5305 InstructionMark im(this);
5306 prefix(dst);
5307 emit_int8((unsigned char)0xC7);
5308 emit_operand(rax, dst, 4);
5309 emit_data((int)imm32, rspec, narrow_oop_operand);
5310 }
5311
5312 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5313 InstructionMark im(this);
5314 int encode = prefix_and_encode(src1->encoding());
5315 emit_int8((unsigned char)0x81);
5316 emit_int8((unsigned char)(0xF8 | encode));
5317 emit_data((int)imm32, rspec, narrow_oop_operand);
5318 }
5319
5320 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5321 InstructionMark im(this);
5322 prefix(src1);
5323 emit_int8((unsigned char)0x81);
5324 emit_operand(rax, src1, 4);
5325 emit_data((int)imm32, rspec, narrow_oop_operand);
5326 }
5327
5328 void Assembler::lzcntq(Register dst, Register src) {
5329 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5330 emit_int8((unsigned char)0xF3);
5331 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5332 emit_int8(0x0F);
5333 emit_int8((unsigned char)0xBD);
5334 emit_int8((unsigned char)(0xC0 | encode));
5335 }
5336
5337 void Assembler::movdq(XMMRegister dst, Register src) {
5338 // table D-1 says MMX/SSE2
5339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5340 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5341 emit_int8(0x6E);
5342 emit_int8((unsigned char)(0xC0 | encode));
5343 }
5344
5345 void Assembler::movdq(Register dst, XMMRegister src) {
5346 // table D-1 says MMX/SSE2
5347 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5348 // swap src/dst to get correct prefix
5349 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5350 emit_int8(0x7E);
5351 emit_int8((unsigned char)(0xC0 | encode));
5352 }
5353
5354 void Assembler::movq(Register dst, Register src) {
5355 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5356 emit_int8((unsigned char)0x8B);
5357 emit_int8((unsigned char)(0xC0 | encode));
5358 }
5359
5360 void Assembler::movq(Register dst, Address src) {
5361 InstructionMark im(this);
5362 prefixq(src, dst);
5363 emit_int8((unsigned char)0x8B);
5364 emit_operand(dst, src);
5365 }
5366
5367 void Assembler::movq(Address dst, Register src) {
5368 InstructionMark im(this);
5369 prefixq(dst, src);
5370 emit_int8((unsigned char)0x89);
5371 emit_operand(src, dst);
5372 }
5373
5374 void Assembler::movsbq(Register dst, Address src) {
5375 InstructionMark im(this);
5376 prefixq(src, dst);
5377 emit_int8(0x0F);
5378 emit_int8((unsigned char)0xBE);
5379 emit_operand(dst, src);
5380 }
5381
5382 void Assembler::movsbq(Register dst, Register src) {
5383 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5384 emit_int8(0x0F);
5385 emit_int8((unsigned char)0xBE);
5386 emit_int8((unsigned char)(0xC0 | encode));
5387 }
5388
5389 void Assembler::movslq(Register dst, int32_t imm32) {
5390 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5391 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5392 // as a result we shouldn't use until tested at runtime...
5393 ShouldNotReachHere();
5394 InstructionMark im(this);
5395 int encode = prefixq_and_encode(dst->encoding());
5396 emit_int8((unsigned char)(0xC7 | encode));
5397 emit_int32(imm32);
5398 }
5399
5400 void Assembler::movslq(Address dst, int32_t imm32) {
5401 assert(is_simm32(imm32), "lost bits");
5402 InstructionMark im(this);
5403 prefixq(dst);
5404 emit_int8((unsigned char)0xC7);
5405 emit_operand(rax, dst, 4);
5406 emit_int32(imm32);
5407 }
5408
5409 void Assembler::movslq(Register dst, Address src) {
5410 InstructionMark im(this);
5411 prefixq(src, dst);
5412 emit_int8(0x63);
5413 emit_operand(dst, src);
5414 }
5415
5416 void Assembler::movslq(Register dst, Register src) {
5417 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5418 emit_int8(0x63);
5419 emit_int8((unsigned char)(0xC0 | encode));
5420 }
5421
5422 void Assembler::movswq(Register dst, Address src) {
5423 InstructionMark im(this);
5424 prefixq(src, dst);
5425 emit_int8(0x0F);
5426 emit_int8((unsigned char)0xBF);
5427 emit_operand(dst, src);
5428 }
5429
5430 void Assembler::movswq(Register dst, Register src) {
5431 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5432 emit_int8((unsigned char)0x0F);
5433 emit_int8((unsigned char)0xBF);
5434 emit_int8((unsigned char)(0xC0 | encode));
5435 }
5436
5437 void Assembler::movzbq(Register dst, Address src) {
5438 InstructionMark im(this);
5439 prefixq(src, dst);
5440 emit_int8((unsigned char)0x0F);
5441 emit_int8((unsigned char)0xB6);
5442 emit_operand(dst, src);
5443 }
5444
5445 void Assembler::movzbq(Register dst, Register src) {
5446 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5447 emit_int8(0x0F);
5448 emit_int8((unsigned char)0xB6);
5449 emit_int8(0xC0 | encode);
5450 }
5451
5452 void Assembler::movzwq(Register dst, Address src) {
5453 InstructionMark im(this);
5454 prefixq(src, dst);
5455 emit_int8((unsigned char)0x0F);
5456 emit_int8((unsigned char)0xB7);
5457 emit_operand(dst, src);
5458 }
5459
5460 void Assembler::movzwq(Register dst, Register src) {
5461 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5462 emit_int8((unsigned char)0x0F);
5463 emit_int8((unsigned char)0xB7);
5464 emit_int8((unsigned char)(0xC0 | encode));
5465 }
5466
5467 void Assembler::mulq(Address src) {
5468 InstructionMark im(this);
5469 prefixq(src);
5470 emit_int8((unsigned char)0xF7);
5471 emit_operand(rsp, src);
5472 }
5473
5474 void Assembler::mulq(Register src) {
5475 int encode = prefixq_and_encode(src->encoding());
5476 emit_int8((unsigned char)0xF7);
5477 emit_int8((unsigned char)(0xE0 | encode));
5478 }
5479
5480 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
5481 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5482 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, true, false);
5483 emit_int8((unsigned char)0xF6);
5484 emit_int8((unsigned char)(0xC0 | encode));
5485 }
5486
5487 void Assembler::negq(Register dst) {
5488 int encode = prefixq_and_encode(dst->encoding());
5489 emit_int8((unsigned char)0xF7);
5490 emit_int8((unsigned char)(0xD8 | encode));
5491 }
5492
5493 void Assembler::notq(Register dst) {
5494 int encode = prefixq_and_encode(dst->encoding());
5495 emit_int8((unsigned char)0xF7);
5496 emit_int8((unsigned char)(0xD0 | encode));
5497 }
5498
5499 void Assembler::orq(Address dst, int32_t imm32) {
5500 InstructionMark im(this);
5501 prefixq(dst);
5502 emit_int8((unsigned char)0x81);
5503 emit_operand(rcx, dst, 4);
5504 emit_int32(imm32);
5505 }
5506
5507 void Assembler::orq(Register dst, int32_t imm32) {
5508 (void) prefixq_and_encode(dst->encoding());
5509 emit_arith(0x81, 0xC8, dst, imm32);
5510 }
5511
5512 void Assembler::orq(Register dst, Address src) {
5513 InstructionMark im(this);
5514 prefixq(src, dst);
5515 emit_int8(0x0B);
5516 emit_operand(dst, src);
5517 }
5518
5519 void Assembler::orq(Register dst, Register src) {
5520 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5521 emit_arith(0x0B, 0xC0, dst, src);
5522 }
5523
5524 void Assembler::popa() { // 64bit
5525 movq(r15, Address(rsp, 0));
5526 movq(r14, Address(rsp, wordSize));
5527 movq(r13, Address(rsp, 2 * wordSize));
5528 movq(r12, Address(rsp, 3 * wordSize));
5529 movq(r11, Address(rsp, 4 * wordSize));
5530 movq(r10, Address(rsp, 5 * wordSize));
5531 movq(r9, Address(rsp, 6 * wordSize));
5532 movq(r8, Address(rsp, 7 * wordSize));
5533 movq(rdi, Address(rsp, 8 * wordSize));
5534 movq(rsi, Address(rsp, 9 * wordSize));
5535 movq(rbp, Address(rsp, 10 * wordSize));
5536 // skip rsp
5537 movq(rbx, Address(rsp, 12 * wordSize));
5538 movq(rdx, Address(rsp, 13 * wordSize));
5539 movq(rcx, Address(rsp, 14 * wordSize));
5540 movq(rax, Address(rsp, 15 * wordSize));
5541
5542 addq(rsp, 16 * wordSize);
5543 }
5544
5545 void Assembler::popcntq(Register dst, Address src) {
5546 assert(VM_Version::supports_popcnt(), "must support");
5547 InstructionMark im(this);
5548 emit_int8((unsigned char)0xF3);
5549 prefixq(src, dst);
5550 emit_int8((unsigned char)0x0F);
5551 emit_int8((unsigned char)0xB8);
5552 emit_operand(dst, src);
5553 }
5554
5555 void Assembler::popcntq(Register dst, Register src) {
5556 assert(VM_Version::supports_popcnt(), "must support");
5557 emit_int8((unsigned char)0xF3);
5558 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5559 emit_int8((unsigned char)0x0F);
5560 emit_int8((unsigned char)0xB8);
5561 emit_int8((unsigned char)(0xC0 | encode));
5562 }
5563
5564 void Assembler::popq(Address dst) {
5565 InstructionMark im(this);
5566 prefixq(dst);
5567 emit_int8((unsigned char)0x8F);
5568 emit_operand(rax, dst);
5569 }
5570
5571 void Assembler::pusha() { // 64bit
5572 // we have to store original rsp. ABI says that 128 bytes
5573 // below rsp are local scratch.
5574 movq(Address(rsp, -5 * wordSize), rsp);
5575
5576 subq(rsp, 16 * wordSize);
5577
5578 movq(Address(rsp, 15 * wordSize), rax);
5579 movq(Address(rsp, 14 * wordSize), rcx);
5580 movq(Address(rsp, 13 * wordSize), rdx);
5581 movq(Address(rsp, 12 * wordSize), rbx);
5582 // skip rsp
5583 movq(Address(rsp, 10 * wordSize), rbp);
5584 movq(Address(rsp, 9 * wordSize), rsi);
5585 movq(Address(rsp, 8 * wordSize), rdi);
5586 movq(Address(rsp, 7 * wordSize), r8);
5587 movq(Address(rsp, 6 * wordSize), r9);
5588 movq(Address(rsp, 5 * wordSize), r10);
5589 movq(Address(rsp, 4 * wordSize), r11);
5590 movq(Address(rsp, 3 * wordSize), r12);
5591 movq(Address(rsp, 2 * wordSize), r13);
5592 movq(Address(rsp, wordSize), r14);
5593 movq(Address(rsp, 0), r15);
5594 }
5595
5596 void Assembler::pushq(Address src) {
5597 InstructionMark im(this);
5598 prefixq(src);
5599 emit_int8((unsigned char)0xFF);
5600 emit_operand(rsi, src);
5601 }
5602
5603 void Assembler::rclq(Register dst, int imm8) {
5604 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5605 int encode = prefixq_and_encode(dst->encoding());
5606 if (imm8 == 1) {
5607 emit_int8((unsigned char)0xD1);
5608 emit_int8((unsigned char)(0xD0 | encode));
5609 } else {
5610 emit_int8((unsigned char)0xC1);
5611 emit_int8((unsigned char)(0xD0 | encode));
5612 emit_int8(imm8);
5613 }
5614 }
5615
5616 void Assembler::rorq(Register dst, int imm8) {
5617 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5618 int encode = prefixq_and_encode(dst->encoding());
5619 if (imm8 == 1) {
5620 emit_int8((unsigned char)0xD1);
5621 emit_int8((unsigned char)(0xC8 | encode));
5622 } else {
5623 emit_int8((unsigned char)0xC1);
5624 emit_int8((unsigned char)(0xc8 | encode));
5625 emit_int8(imm8);
5626 }
5627 }
5628
5629 void Assembler::rorxq(Register dst, Register src, int imm8) {
5630 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5631 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false);
5632 emit_int8((unsigned char)0xF0);
5633 emit_int8((unsigned char)(0xC0 | encode));
5634 emit_int8(imm8);
5635 }
5636
5637 void Assembler::sarq(Register dst, int imm8) {
5638 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5639 int encode = prefixq_and_encode(dst->encoding());
5640 if (imm8 == 1) {
5641 emit_int8((unsigned char)0xD1);
5642 emit_int8((unsigned char)(0xF8 | encode));
5643 } else {
5644 emit_int8((unsigned char)0xC1);
5645 emit_int8((unsigned char)(0xF8 | encode));
5646 emit_int8(imm8);
5647 }
5648 }
5649
5650 void Assembler::sarq(Register dst) {
5651 int encode = prefixq_and_encode(dst->encoding());
5652 emit_int8((unsigned char)0xD3);
5653 emit_int8((unsigned char)(0xF8 | encode));
5654 }
5655
5656 void Assembler::sbbq(Address dst, int32_t imm32) {
5657 InstructionMark im(this);
5658 prefixq(dst);
5659 emit_arith_operand(0x81, rbx, dst, imm32);
5660 }
5661
5662 void Assembler::sbbq(Register dst, int32_t imm32) {
5663 (void) prefixq_and_encode(dst->encoding());
5664 emit_arith(0x81, 0xD8, dst, imm32);
5665 }
5666
5667 void Assembler::sbbq(Register dst, Address src) {
5668 InstructionMark im(this);
5669 prefixq(src, dst);
5670 emit_int8(0x1B);
5671 emit_operand(dst, src);
5672 }
5673
5674 void Assembler::sbbq(Register dst, Register src) {
5675 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5676 emit_arith(0x1B, 0xC0, dst, src);
5677 }
5678
5679 void Assembler::shlq(Register dst, int imm8) {
5680 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5681 int encode = prefixq_and_encode(dst->encoding());
5682 if (imm8 == 1) {
5683 emit_int8((unsigned char)0xD1);
5684 emit_int8((unsigned char)(0xE0 | encode));
5685 } else {
5686 emit_int8((unsigned char)0xC1);
5687 emit_int8((unsigned char)(0xE0 | encode));
5688 emit_int8(imm8);
5689 }
5690 }
5691
5692 void Assembler::shlq(Register dst) {
5693 int encode = prefixq_and_encode(dst->encoding());
5694 emit_int8((unsigned char)0xD3);
5695 emit_int8((unsigned char)(0xE0 | encode));
5696 }
5697
5698 void Assembler::shrq(Register dst, int imm8) {
5699 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5700 int encode = prefixq_and_encode(dst->encoding());
5701 emit_int8((unsigned char)0xC1);
5702 emit_int8((unsigned char)(0xE8 | encode));
5703 emit_int8(imm8);
5704 }
5705
5706 void Assembler::shrq(Register dst) {
5707 int encode = prefixq_and_encode(dst->encoding());
5708 emit_int8((unsigned char)0xD3);
5709 emit_int8(0xE8 | encode);
5710 }
5711
5712 void Assembler::subq(Address dst, int32_t imm32) {
5713 InstructionMark im(this);
5714 prefixq(dst);
5715 emit_arith_operand(0x81, rbp, dst, imm32);
5716 }
5717
5718 void Assembler::subq(Address dst, Register src) {
5719 InstructionMark im(this);
5720 prefixq(dst, src);
5721 emit_int8(0x29);
5722 emit_operand(src, dst);
5723 }
5724
5725 void Assembler::subq(Register dst, int32_t imm32) {
5726 (void) prefixq_and_encode(dst->encoding());
5727 emit_arith(0x81, 0xE8, dst, imm32);
5728 }
5729
5730 // Force generation of a 4 byte immediate value even if it fits into 8bit
5731 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5732 (void) prefixq_and_encode(dst->encoding());
5733 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5734 }
5735
5736 void Assembler::subq(Register dst, Address src) {
5737 InstructionMark im(this);
5738 prefixq(src, dst);
5739 emit_int8(0x2B);
5740 emit_operand(dst, src);
5741 }
5742
5743 void Assembler::subq(Register dst, Register src) {
5744 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5745 emit_arith(0x2B, 0xC0, dst, src);
5746 }
5747
5748 void Assembler::testq(Register dst, int32_t imm32) {
5749 // not using emit_arith because test
5750 // doesn't support sign-extension of
5751 // 8bit operands
5752 int encode = dst->encoding();
5753 if (encode == 0) {
5754 prefix(REX_W);
5755 emit_int8((unsigned char)0xA9);
5756 } else {
5757 encode = prefixq_and_encode(encode);
5758 emit_int8((unsigned char)0xF7);
5759 emit_int8((unsigned char)(0xC0 | encode));
5760 }
5761 emit_int32(imm32);
5762 }
5763
5764 void Assembler::testq(Register dst, Register src) {
5765 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5766 emit_arith(0x85, 0xC0, dst, src);
5767 }
5768
5769 void Assembler::xaddq(Address dst, Register src) {
5770 InstructionMark im(this);
5771 prefixq(dst, src);
5772 emit_int8(0x0F);
5773 emit_int8((unsigned char)0xC1);
5774 emit_operand(src, dst);
5775 }
5776
5777 void Assembler::xchgq(Register dst, Address src) {
5778 InstructionMark im(this);
5779 prefixq(src, dst);
5780 emit_int8((unsigned char)0x87);
5781 emit_operand(dst, src);
5782 }
5783
5784 void Assembler::xchgq(Register dst, Register src) {
5785 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5786 emit_int8((unsigned char)0x87);
5787 emit_int8((unsigned char)(0xc0 | encode));
5788 }
5789
5790 void Assembler::xorq(Register dst, Register src) {
5791 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5792 emit_arith(0x33, 0xC0, dst, src);
5793 }
5794
5795 void Assembler::xorq(Register dst, Address src) {
5796 InstructionMark im(this);
5797 prefixq(src, dst);
5798 emit_int8(0x33);
5799 emit_operand(dst, src);
5800 }
5801
5802 #endif // !LP64