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src/hotspot/cpu/ppc/globals_ppc.hpp

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*** 73,200 **** // 2x unrolled loop is shorter with more than 9 HeapWords. define_pd_global(intx, InitArrayShortSize, 9*BytesPerLong); // Platform dependent flag handling: flags only defined on this platform. ! #define ARCH_FLAGS(develop, \ ! product, \ ! diagnostic, \ ! experimental, \ ! notproduct, \ ! range, \ ! constraint) \ ! \ ! product(uintx, PowerArchitecturePPC64, 0, \ ! "CPU Version: x for PowerX. Currently recognizes Power5 to " \ ! "Power8. Default is 0. Newer CPUs will be recognized as Power8.") \ ! \ ! product(bool, SuperwordUseVSX, false, \ ! "Use Power8 VSX instructions for superword optimization.") \ ! \ ! /* Reoptimize code-sequences of calls at runtime, e.g. replace an */ \ ! /* indirect call by a direct call. */ \ ! product(bool, ReoptimizeCallSequences, true, \ ! "Reoptimize code-sequences of calls at runtime.") \ ! \ ! /* Power 8: Configure Data Stream Control Register. */ \ ! product(uint64_t,DSCR_PPC64, (uintx)-1, \ ! "Power8 or later: Specify encoded value for Data Stream Control " \ ! "Register") \ ! product(uint64_t,DSCR_DPFD_PPC64, 8, \ ! "Power8 or later: DPFD (default prefetch depth) value of the " \ ! "Data Stream Control Register." \ ! " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ ! product(uint64_t,DSCR_URG_PPC64, 8, \ ! "Power8 or later: URG (depth attainment urgency) value of the " \ ! "Data Stream Control Register." \ ! " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ ! \ ! product(bool, UseLoadInstructionsForStackBangingPPC64, false, \ ! "Use load instructions for stack banging.") \ ! \ ! /* special instructions */ \ ! \ ! product(bool, UseCountLeadingZerosInstructionsPPC64, true, \ ! "Use count leading zeros instructions.") \ ! \ ! product(bool, UseCountTrailingZerosInstructionsPPC64, false, \ ! "Use count trailing zeros instructions.") \ ! \ ! product(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, \ ! "Use extended versions of load-and-reserve instructions.") \ ! \ ! product(bool, UseRotateAndMaskInstructionsPPC64, true, \ ! "Use rotate and mask instructions.") \ ! \ ! product(bool, UseStaticBranchPredictionInCompareAndSwapPPC64, true, \ ! "Use static branch prediction hints in CAS operations.") \ ! product(bool, UseStaticBranchPredictionForUncommonPathsPPC64, false, \ ! "Use static branch prediction hints for uncommon paths.") \ ! \ ! product(bool, UsePower6SchedulerPPC64, false, \ ! "Use Power6 Scheduler.") \ ! \ ! product(bool, InsertEndGroupPPC64, false, \ ! "Insert EndGroup instructions to optimize for Power6.") \ ! \ ! /* Trap based checks. */ \ ! /* Trap based checks use the ppc trap instructions to check certain */ \ ! /* conditions. This instruction raises a SIGTRAP caught by the */ \ ! /* exception handler of the VM. */ \ ! product(bool, UseSIGTRAP, true, \ ! "Allow trap instructions that make use of SIGTRAP. Use this to " \ ! "switch off all optimizations requiring SIGTRAP.") \ ! product(bool, TrapBasedICMissChecks, true, \ ! "Raise and handle SIGTRAP if inline cache miss detected.") \ ! product(bool, TrapBasedNotEntrantChecks, true, \ ! "Raise and handle SIGTRAP if calling not entrant or zombie" \ ! " method.") \ ! product(bool, TraceTraps, false, "Trace all traps the signal handler" \ ! "handles.") \ ! \ ! product(bool, ZapMemory, false, "Write 0x0101... to empty memory." \ ! " Use this to ease debugging.") \ ! \ ! /* Use Restricted Transactional Memory for lock elision */ \ ! product(bool, UseRTMLocking, false, \ ! "Enable RTM lock eliding for inflated locks in compiled code") \ ! \ ! experimental(bool, UseRTMForStackLocks, false, \ ! "Enable RTM lock eliding for stack locks in compiled code") \ ! \ ! product(bool, UseRTMDeopt, false, \ ! "Perform deopt and recompilation based on RTM abort ratio") \ ! \ ! product(int, RTMRetryCount, 5, \ ! "Number of RTM retries on lock abort or busy") \ ! range(0, max_jint) \ ! \ ! experimental(int, RTMSpinLoopCount, 100, \ ! "Spin count for lock to become free before RTM retry") \ ! range(0, 32767) /* immediate operand limit on ppc */ \ ! \ ! experimental(int, RTMAbortThreshold, 1000, \ ! "Calculate abort ratio after this number of aborts") \ ! range(0, max_jint) \ ! \ ! experimental(int, RTMLockingThreshold, 10000, \ ! "Lock count at which to do RTM lock eliding without " \ ! "abort ratio calculation") \ ! range(0, max_jint) \ ! \ ! experimental(int, RTMAbortRatio, 50, \ ! "Lock abort ratio at which to stop use RTM lock eliding") \ ! range(0, 100) /* natural range */ \ ! \ ! experimental(int, RTMTotalCountIncrRate, 64, \ ! "Increment total RTM attempted lock count once every n times") \ ! range(1, 32767) /* immediate operand limit on ppc */ \ ! constraint(RTMTotalCountIncrRateConstraintFunc,AfterErgo) \ ! \ ! experimental(intx, RTMLockingCalculationDelay, 0, \ ! "Number of milliseconds to wait before start calculating aborts " \ ! "for RTM locking") \ ! \ ! experimental(bool, UseRTMXendForLockBusy, true, \ ! "Use RTM Xend instead of Xabort when lock busy") \ #endif // CPU_PPC_GLOBALS_PPC_HPP --- 73,204 ---- // 2x unrolled loop is shorter with more than 9 HeapWords. define_pd_global(intx, InitArrayShortSize, 9*BytesPerLong); // Platform dependent flag handling: flags only defined on this platform. ! #include "runtime/flags/jvmFlag.hpp" ! PRODUCT_FLAG(uintx, PowerArchitecturePPC64, 0, JVMFlag::DEFAULT, ! "CPU Version: x for PowerX. Currently recognizes Power5 to " ! "Power8. Default is 0. Newer CPUs will be recognized as Power8."); + PRODUCT_FLAG(bool, SuperwordUseVSX, false, JVMFlag::DEFAULT, + "Use Power8 VSX instructions for superword optimization."); + + + // Reoptimize code-sequences of calls at runtime, e.g. replace an + // indirect call by a direct call. + PRODUCT_FLAG(bool, ReoptimizeCallSequences, true, JVMFlag::DEFAULT, + "Reoptimize code-sequences of calls at runtime."); + + + // Power 8: Configure Data Stream Control Register. + PRODUCT_FLAG(uint64_t, DSCR_PPC64, (uintx)-1, JVMFlag::DEFAULT, + "Power8 or later: Specify encoded value for Data Stream Control " + "Register"); + + PRODUCT_FLAG(uint64_t, DSCR_DPFD_PPC64, 8, JVMFlag::DEFAULT, + "Power8 or later: DPFD (default prefetch depth) value of the " + "Data Stream Control Register." + " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch"); + + PRODUCT_FLAG(uint64_t, DSCR_URG_PPC64, 8, JVMFlag::DEFAULT, + "Power8 or later: URG (depth attainment urgency) value of the " + "Data Stream Control Register." + " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch"); + + PRODUCT_FLAG(bool, UseLoadInstructionsForStackBangingPPC64, false, JVMFlag::DEFAULT, + "Use load instructions for stack banging."); + + + // special instructions + PRODUCT_FLAG(bool, UseCountLeadingZerosInstructionsPPC64, true, JVMFlag::DEFAULT, + "Use count leading zeros instructions."); + + PRODUCT_FLAG(bool, UseCountTrailingZerosInstructionsPPC64, false, JVMFlag::DEFAULT, + "Use count trailing zeros instructions."); + + PRODUCT_FLAG(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, JVMFlag::DEFAULT, + "Use extended versions of load-and-reserve instructions."); + + PRODUCT_FLAG(bool, UseRotateAndMaskInstructionsPPC64, true, JVMFlag::DEFAULT, + "Use rotate and mask instructions."); + + PRODUCT_FLAG(bool, UseStaticBranchPredictionInCompareAndSwapPPC64, true, JVMFlag::DEFAULT, + "Use static branch prediction hints in CAS operations."); + + PRODUCT_FLAG(bool, UseStaticBranchPredictionForUncommonPathsPPC64, false, JVMFlag::DEFAULT, + "Use static branch prediction hints for uncommon paths."); + + PRODUCT_FLAG(bool, UsePower6SchedulerPPC64, false, JVMFlag::DEFAULT, + "Use Power6 Scheduler."); + + PRODUCT_FLAG(bool, InsertEndGroupPPC64, false, JVMFlag::DEFAULT, + "Insert EndGroup instructions to optimize for Power6."); + + + // Trap based checks. + // Trap based checks use the ppc trap instructions to check certain + // conditions. This instruction raises a SIGTRAP caught by the + // exception handler of the VM. + PRODUCT_FLAG(bool, UseSIGTRAP, true, JVMFlag::DEFAULT, + "Allow trap instructions that make use of SIGTRAP. Use this to " + "switch off all optimizations requiring SIGTRAP."); + + PRODUCT_FLAG(bool, TrapBasedICMissChecks, true, JVMFlag::DEFAULT, + "Raise and handle SIGTRAP if inline cache miss detected."); + + PRODUCT_FLAG(bool, TrapBasedNotEntrantChecks, true, JVMFlag::DEFAULT, + "Raise and handle SIGTRAP if calling not entrant or zombie" + " method."); + + PRODUCT_FLAG(bool, TraceTraps, false, JVMFlag::DEFAULT, + "Trace all traps the signal handler" + "handles."); + + PRODUCT_FLAG(bool, ZapMemory, false, JVMFlag::DEFAULT, + "Write 0x0101... to empty memory." + " Use this to ease debugging."); + + + // Use Restricted Transactional Memory for lock elision + PRODUCT_FLAG(bool, UseRTMLocking, false, JVMFlag::DEFAULT, + "Enable RTM lock eliding for inflated locks in compiled code"); + + PRODUCT_FLAG(bool, UseRTMForStackLocks, false, JVMFlag::EXPERIMENTAL, + "Enable RTM lock eliding for stack locks in compiled code"); + + PRODUCT_FLAG(bool, UseRTMDeopt, false, JVMFlag::DEFAULT, + "Perform deopt and recompilation based on RTM abort ratio"); + + PRODUCT_FLAG(int, RTMRetryCount, 5, JVMFlag::RANGE, + "Number of RTM retries on lock abort or busy"); + FLAG_RANGE( RTMRetryCount, 0, max_jint); + + PRODUCT_FLAG(int, RTMSpinLoopCount, 100, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, + "Spin count for lock to become free before RTM retry"); + FLAG_RANGE( RTMSpinLoopCount, 0, 32767); + + PRODUCT_FLAG(int, RTMAbortThreshold, 1000, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, + "Calculate abort ratio after this number of aborts"); + FLAG_RANGE( RTMAbortThreshold, 0, max_jint); + + PRODUCT_FLAG(int, RTMLockingThreshold, 10000, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, + "Lock count at which to do RTM lock eliding without " + "abort ratio calculation"); + FLAG_RANGE( RTMLockingThreshold, 0, max_jint); + + PRODUCT_FLAG(int, RTMAbortRatio, 50, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, + "Lock abort ratio at which to stop use RTM lock eliding"); + FLAG_RANGE( RTMAbortRatio, 0, 100); + + PRODUCT_FLAG(int, RTMTotalCountIncrRate, 64, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE | JVMFlag::CONSTRAINT, + "Increment total RTM attempted lock count once every n times"); + FLAG_RANGE( RTMTotalCountIncrRate, 1, 32767); + FLAG_CONSTRAINT( RTMTotalCountIncrRate, (void*)RTMTotalCountIncrRateConstraintFunc, JVMFlag::AfterErgo); + + PRODUCT_FLAG(intx, RTMLockingCalculationDelay, 0, JVMFlag::EXPERIMENTAL, + "Number of milliseconds to wait before start calculating aborts " + "for RTM locking"); + + PRODUCT_FLAG(bool, UseRTMXendForLockBusy, true, JVMFlag::EXPERIMENTAL, + "Use RTM Xend instead of Xabort when lock busy"); #endif // CPU_PPC_GLOBALS_PPC_HPP
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