58 define_pd_global(uintx, CodeCacheSegmentSize, 128); 59 define_pd_global(intx, CodeEntryAlignment, 128); 60 define_pd_global(intx, OptoLoopAlignment, 16); 61 define_pd_global(intx, InlineFrequencyCount, 100); 62 define_pd_global(intx, InlineSmallCode, 1500); 63 64 // Flags for template interpreter. 65 define_pd_global(bool, RewriteBytecodes, true); 66 define_pd_global(bool, RewriteFrequentPairs, true); 67 68 define_pd_global(bool, PreserveFramePointer, false); 69 70 define_pd_global(uintx, TypeProfileLevel, 111); 71 72 define_pd_global(bool, CompactStrings, true); 73 74 // 2x unrolled loop is shorter with more than 9 HeapWords. 75 define_pd_global(intx, InitArrayShortSize, 9*BytesPerLong); 76 77 // Platform dependent flag handling: flags only defined on this platform. 78 #define ARCH_FLAGS(develop, \ 79 product, \ 80 diagnostic, \ 81 experimental, \ 82 notproduct, \ 83 range, \ 84 constraint) \ 85 \ 86 product(uintx, PowerArchitecturePPC64, 0, \ 87 "CPU Version: x for PowerX. Currently recognizes Power5 to " \ 88 "Power8. Default is 0. Newer CPUs will be recognized as Power8.") \ 89 \ 90 product(bool, SuperwordUseVSX, false, \ 91 "Use Power8 VSX instructions for superword optimization.") \ 92 \ 93 /* Reoptimize code-sequences of calls at runtime, e.g. replace an */ \ 94 /* indirect call by a direct call. */ \ 95 product(bool, ReoptimizeCallSequences, true, \ 96 "Reoptimize code-sequences of calls at runtime.") \ 97 \ 98 /* Power 8: Configure Data Stream Control Register. */ \ 99 product(uint64_t,DSCR_PPC64, (uintx)-1, \ 100 "Power8 or later: Specify encoded value for Data Stream Control " \ 101 "Register") \ 102 product(uint64_t,DSCR_DPFD_PPC64, 8, \ 103 "Power8 or later: DPFD (default prefetch depth) value of the " \ 104 "Data Stream Control Register." \ 105 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ 106 product(uint64_t,DSCR_URG_PPC64, 8, \ 107 "Power8 or later: URG (depth attainment urgency) value of the " \ 108 "Data Stream Control Register." \ 109 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ 110 \ 111 product(bool, UseLoadInstructionsForStackBangingPPC64, false, \ 112 "Use load instructions for stack banging.") \ 113 \ 114 /* special instructions */ \ 115 \ 116 product(bool, UseCountLeadingZerosInstructionsPPC64, true, \ 117 "Use count leading zeros instructions.") \ 118 \ 119 product(bool, UseCountTrailingZerosInstructionsPPC64, false, \ 120 "Use count trailing zeros instructions.") \ 121 \ 122 product(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, \ 123 "Use extended versions of load-and-reserve instructions.") \ 124 \ 125 product(bool, UseRotateAndMaskInstructionsPPC64, true, \ 126 "Use rotate and mask instructions.") \ 127 \ 128 product(bool, UseStaticBranchPredictionInCompareAndSwapPPC64, true, \ 129 "Use static branch prediction hints in CAS operations.") \ 130 product(bool, UseStaticBranchPredictionForUncommonPathsPPC64, false, \ 131 "Use static branch prediction hints for uncommon paths.") \ 132 \ 133 product(bool, UsePower6SchedulerPPC64, false, \ 134 "Use Power6 Scheduler.") \ 135 \ 136 product(bool, InsertEndGroupPPC64, false, \ 137 "Insert EndGroup instructions to optimize for Power6.") \ 138 \ 139 /* Trap based checks. */ \ 140 /* Trap based checks use the ppc trap instructions to check certain */ \ 141 /* conditions. This instruction raises a SIGTRAP caught by the */ \ 142 /* exception handler of the VM. */ \ 143 product(bool, UseSIGTRAP, true, \ 144 "Allow trap instructions that make use of SIGTRAP. Use this to " \ 145 "switch off all optimizations requiring SIGTRAP.") \ 146 product(bool, TrapBasedICMissChecks, true, \ 147 "Raise and handle SIGTRAP if inline cache miss detected.") \ 148 product(bool, TrapBasedNotEntrantChecks, true, \ 149 "Raise and handle SIGTRAP if calling not entrant or zombie" \ 150 " method.") \ 151 product(bool, TraceTraps, false, "Trace all traps the signal handler" \ 152 "handles.") \ 153 \ 154 product(bool, ZapMemory, false, "Write 0x0101... to empty memory." \ 155 " Use this to ease debugging.") \ 156 \ 157 /* Use Restricted Transactional Memory for lock elision */ \ 158 product(bool, UseRTMLocking, false, \ 159 "Enable RTM lock eliding for inflated locks in compiled code") \ 160 \ 161 experimental(bool, UseRTMForStackLocks, false, \ 162 "Enable RTM lock eliding for stack locks in compiled code") \ 163 \ 164 product(bool, UseRTMDeopt, false, \ 165 "Perform deopt and recompilation based on RTM abort ratio") \ 166 \ 167 product(int, RTMRetryCount, 5, \ 168 "Number of RTM retries on lock abort or busy") \ 169 range(0, max_jint) \ 170 \ 171 experimental(int, RTMSpinLoopCount, 100, \ 172 "Spin count for lock to become free before RTM retry") \ 173 range(0, 32767) /* immediate operand limit on ppc */ \ 174 \ 175 experimental(int, RTMAbortThreshold, 1000, \ 176 "Calculate abort ratio after this number of aborts") \ 177 range(0, max_jint) \ 178 \ 179 experimental(int, RTMLockingThreshold, 10000, \ 180 "Lock count at which to do RTM lock eliding without " \ 181 "abort ratio calculation") \ 182 range(0, max_jint) \ 183 \ 184 experimental(int, RTMAbortRatio, 50, \ 185 "Lock abort ratio at which to stop use RTM lock eliding") \ 186 range(0, 100) /* natural range */ \ 187 \ 188 experimental(int, RTMTotalCountIncrRate, 64, \ 189 "Increment total RTM attempted lock count once every n times") \ 190 range(1, 32767) /* immediate operand limit on ppc */ \ 191 constraint(RTMTotalCountIncrRateConstraintFunc,AfterErgo) \ 192 \ 193 experimental(intx, RTMLockingCalculationDelay, 0, \ 194 "Number of milliseconds to wait before start calculating aborts " \ 195 "for RTM locking") \ 196 \ 197 experimental(bool, UseRTMXendForLockBusy, true, \ 198 "Use RTM Xend instead of Xabort when lock busy") \ 199 200 #endif // CPU_PPC_GLOBALS_PPC_HPP | 58 define_pd_global(uintx, CodeCacheSegmentSize, 128); 59 define_pd_global(intx, CodeEntryAlignment, 128); 60 define_pd_global(intx, OptoLoopAlignment, 16); 61 define_pd_global(intx, InlineFrequencyCount, 100); 62 define_pd_global(intx, InlineSmallCode, 1500); 63 64 // Flags for template interpreter. 65 define_pd_global(bool, RewriteBytecodes, true); 66 define_pd_global(bool, RewriteFrequentPairs, true); 67 68 define_pd_global(bool, PreserveFramePointer, false); 69 70 define_pd_global(uintx, TypeProfileLevel, 111); 71 72 define_pd_global(bool, CompactStrings, true); 73 74 // 2x unrolled loop is shorter with more than 9 HeapWords. 75 define_pd_global(intx, InitArrayShortSize, 9*BytesPerLong); 76 77 // Platform dependent flag handling: flags only defined on this platform. 78 #include "runtime/flags/jvmFlag.hpp" 79 PRODUCT_FLAG(uintx, PowerArchitecturePPC64, 0, JVMFlag::DEFAULT, 80 "CPU Version: x for PowerX. Currently recognizes Power5 to " 81 "Power8. Default is 0. Newer CPUs will be recognized as Power8."); 82 83 PRODUCT_FLAG(bool, SuperwordUseVSX, false, JVMFlag::DEFAULT, 84 "Use Power8 VSX instructions for superword optimization."); 85 86 87 // Reoptimize code-sequences of calls at runtime, e.g. replace an 88 // indirect call by a direct call. 89 PRODUCT_FLAG(bool, ReoptimizeCallSequences, true, JVMFlag::DEFAULT, 90 "Reoptimize code-sequences of calls at runtime."); 91 92 93 // Power 8: Configure Data Stream Control Register. 94 PRODUCT_FLAG(uint64_t, DSCR_PPC64, (uintx)-1, JVMFlag::DEFAULT, 95 "Power8 or later: Specify encoded value for Data Stream Control " 96 "Register"); 97 98 PRODUCT_FLAG(uint64_t, DSCR_DPFD_PPC64, 8, JVMFlag::DEFAULT, 99 "Power8 or later: DPFD (default prefetch depth) value of the " 100 "Data Stream Control Register." 101 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch"); 102 103 PRODUCT_FLAG(uint64_t, DSCR_URG_PPC64, 8, JVMFlag::DEFAULT, 104 "Power8 or later: URG (depth attainment urgency) value of the " 105 "Data Stream Control Register." 106 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch"); 107 108 PRODUCT_FLAG(bool, UseLoadInstructionsForStackBangingPPC64, false, JVMFlag::DEFAULT, 109 "Use load instructions for stack banging."); 110 111 112 // special instructions 113 PRODUCT_FLAG(bool, UseCountLeadingZerosInstructionsPPC64, true, JVMFlag::DEFAULT, 114 "Use count leading zeros instructions."); 115 116 PRODUCT_FLAG(bool, UseCountTrailingZerosInstructionsPPC64, false, JVMFlag::DEFAULT, 117 "Use count trailing zeros instructions."); 118 119 PRODUCT_FLAG(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, JVMFlag::DEFAULT, 120 "Use extended versions of load-and-reserve instructions."); 121 122 PRODUCT_FLAG(bool, UseRotateAndMaskInstructionsPPC64, true, JVMFlag::DEFAULT, 123 "Use rotate and mask instructions."); 124 125 PRODUCT_FLAG(bool, UseStaticBranchPredictionInCompareAndSwapPPC64, true, JVMFlag::DEFAULT, 126 "Use static branch prediction hints in CAS operations."); 127 128 PRODUCT_FLAG(bool, UseStaticBranchPredictionForUncommonPathsPPC64, false, JVMFlag::DEFAULT, 129 "Use static branch prediction hints for uncommon paths."); 130 131 PRODUCT_FLAG(bool, UsePower6SchedulerPPC64, false, JVMFlag::DEFAULT, 132 "Use Power6 Scheduler."); 133 134 PRODUCT_FLAG(bool, InsertEndGroupPPC64, false, JVMFlag::DEFAULT, 135 "Insert EndGroup instructions to optimize for Power6."); 136 137 138 // Trap based checks. 139 // Trap based checks use the ppc trap instructions to check certain 140 // conditions. This instruction raises a SIGTRAP caught by the 141 // exception handler of the VM. 142 PRODUCT_FLAG(bool, UseSIGTRAP, true, JVMFlag::DEFAULT, 143 "Allow trap instructions that make use of SIGTRAP. Use this to " 144 "switch off all optimizations requiring SIGTRAP."); 145 146 PRODUCT_FLAG(bool, TrapBasedICMissChecks, true, JVMFlag::DEFAULT, 147 "Raise and handle SIGTRAP if inline cache miss detected."); 148 149 PRODUCT_FLAG(bool, TrapBasedNotEntrantChecks, true, JVMFlag::DEFAULT, 150 "Raise and handle SIGTRAP if calling not entrant or zombie" 151 " method."); 152 153 PRODUCT_FLAG(bool, TraceTraps, false, JVMFlag::DEFAULT, 154 "Trace all traps the signal handler" 155 "handles."); 156 157 PRODUCT_FLAG(bool, ZapMemory, false, JVMFlag::DEFAULT, 158 "Write 0x0101... to empty memory." 159 " Use this to ease debugging."); 160 161 162 // Use Restricted Transactional Memory for lock elision 163 PRODUCT_FLAG(bool, UseRTMLocking, false, JVMFlag::DEFAULT, 164 "Enable RTM lock eliding for inflated locks in compiled code"); 165 166 PRODUCT_FLAG(bool, UseRTMForStackLocks, false, JVMFlag::EXPERIMENTAL, 167 "Enable RTM lock eliding for stack locks in compiled code"); 168 169 PRODUCT_FLAG(bool, UseRTMDeopt, false, JVMFlag::DEFAULT, 170 "Perform deopt and recompilation based on RTM abort ratio"); 171 172 PRODUCT_FLAG(int, RTMRetryCount, 5, JVMFlag::RANGE, 173 "Number of RTM retries on lock abort or busy"); 174 FLAG_RANGE( RTMRetryCount, 0, max_jint); 175 176 PRODUCT_FLAG(int, RTMSpinLoopCount, 100, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, 177 "Spin count for lock to become free before RTM retry"); 178 FLAG_RANGE( RTMSpinLoopCount, 0, 32767); 179 180 PRODUCT_FLAG(int, RTMAbortThreshold, 1000, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, 181 "Calculate abort ratio after this number of aborts"); 182 FLAG_RANGE( RTMAbortThreshold, 0, max_jint); 183 184 PRODUCT_FLAG(int, RTMLockingThreshold, 10000, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, 185 "Lock count at which to do RTM lock eliding without " 186 "abort ratio calculation"); 187 FLAG_RANGE( RTMLockingThreshold, 0, max_jint); 188 189 PRODUCT_FLAG(int, RTMAbortRatio, 50, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE, 190 "Lock abort ratio at which to stop use RTM lock eliding"); 191 FLAG_RANGE( RTMAbortRatio, 0, 100); 192 193 PRODUCT_FLAG(int, RTMTotalCountIncrRate, 64, JVMFlag::EXPERIMENTAL | JVMFlag::RANGE | JVMFlag::CONSTRAINT, 194 "Increment total RTM attempted lock count once every n times"); 195 FLAG_RANGE( RTMTotalCountIncrRate, 1, 32767); 196 FLAG_CONSTRAINT( RTMTotalCountIncrRate, (void*)RTMTotalCountIncrRateConstraintFunc, JVMFlag::AfterErgo); 197 198 PRODUCT_FLAG(intx, RTMLockingCalculationDelay, 0, JVMFlag::EXPERIMENTAL, 199 "Number of milliseconds to wait before start calculating aborts " 200 "for RTM locking"); 201 202 PRODUCT_FLAG(bool, UseRTMXendForLockBusy, true, JVMFlag::EXPERIMENTAL, 203 "Use RTM Xend instead of Xabort when lock busy"); 204 #endif // CPU_PPC_GLOBALS_PPC_HPP |