1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "vmreg_x86.inline.hpp"
44
45
46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
47 // instructions, to allow sign-masking or sign-bit flipping. They allow
48 // fast versions of NegF/NegD and AbsF/AbsD.
49
50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
53 // of 128-bits operands for SSE instructions.
54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
55 // Store the value to a 128-bits operand.
56 operand[0] = lo;
57 operand[1] = hi;
58 return operand;
59 }
60
61 // Buffer for 128-bits masks used by SSE instructions.
62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
63
64 // Static initialization during VM startup.
65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
69
70
71 NEEDS_CLEANUP // remove this definitions ?
72 const Register IC_Klass = rax; // where the IC klass is cached
73 const Register SYNC_header = rax; // synchronization header
74 const Register SHIFT_count = rcx; // where count for shift operations must be
75
76 #define __ _masm->
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp2 = extra;
89 }
90 assert_different_registers(preserve, tmp1, tmp2);
91 }
92
93
94
95 static void select_different_registers(Register preserve,
96 Register extra,
97 Register &tmp1,
98 Register &tmp2,
99 Register &tmp3) {
100 if (tmp1 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp1 = extra;
103 } else if (tmp2 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp2 = extra;
106 } else if (tmp3 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp3 = extra;
109 }
110 assert_different_registers(preserve, tmp1, tmp2, tmp3);
111 }
112
113
114
115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
116 if (opr->is_constant()) {
117 LIR_Const* constant = opr->as_constant_ptr();
118 switch (constant->type()) {
119 case T_INT: {
120 return true;
121 }
122
123 default:
124 return false;
125 }
126 }
127 return false;
128 }
129
130
131 LIR_Opr LIR_Assembler::receiverOpr() {
132 return FrameMap::receiver_opr;
133 }
134
135 LIR_Opr LIR_Assembler::osrBufferPointer() {
136 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
137 }
138
139 //--------------fpu register translations-----------------------
140
141
142 address LIR_Assembler::float_constant(float f) {
143 address const_addr = __ float_constant(f);
144 if (const_addr == NULL) {
145 bailout("const section overflow");
146 return __ code()->consts()->start();
147 } else {
148 return const_addr;
149 }
150 }
151
152
153 address LIR_Assembler::double_constant(double d) {
154 address const_addr = __ double_constant(d);
155 if (const_addr == NULL) {
156 bailout("const section overflow");
157 return __ code()->consts()->start();
158 } else {
159 return const_addr;
160 }
161 }
162
163
164 void LIR_Assembler::set_24bit_FPU() {
165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
166 }
167
168 void LIR_Assembler::reset_FPU() {
169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
170 }
171
172 void LIR_Assembler::fpop() {
173 __ fpop();
174 }
175
176 void LIR_Assembler::fxch(int i) {
177 __ fxch(i);
178 }
179
180 void LIR_Assembler::fld(int i) {
181 __ fld_s(i);
182 }
183
184 void LIR_Assembler::ffree(int i) {
185 __ ffree(i);
186 }
187
188 void LIR_Assembler::breakpoint() {
189 __ int3();
190 }
191
192 void LIR_Assembler::push(LIR_Opr opr) {
193 if (opr->is_single_cpu()) {
194 __ push_reg(opr->as_register());
195 } else if (opr->is_double_cpu()) {
196 NOT_LP64(__ push_reg(opr->as_register_hi()));
197 __ push_reg(opr->as_register_lo());
198 } else if (opr->is_stack()) {
199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
200 } else if (opr->is_constant()) {
201 LIR_Const* const_opr = opr->as_constant_ptr();
202 if (const_opr->type() == T_OBJECT || const_opr->type() == T_VALUETYPE) {
203 __ push_oop(const_opr->as_jobject());
204 } else if (const_opr->type() == T_INT) {
205 __ push_jint(const_opr->as_jint());
206 } else {
207 ShouldNotReachHere();
208 }
209
210 } else {
211 ShouldNotReachHere();
212 }
213 }
214
215 void LIR_Assembler::pop(LIR_Opr opr) {
216 if (opr->is_single_cpu()) {
217 __ pop_reg(opr->as_register());
218 } else {
219 ShouldNotReachHere();
220 }
221 }
222
223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
224 return addr->base()->is_illegal() && addr->index()->is_illegal();
225 }
226
227 //-------------------------------------------
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr) {
230 return as_Address(addr, rscratch1);
231 }
232
233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
234 if (addr->base()->is_illegal()) {
235 assert(addr->index()->is_illegal(), "must be illegal too");
236 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
237 if (! __ reachable(laddr)) {
238 __ movptr(tmp, laddr.addr());
239 Address res(tmp, 0);
240 return res;
241 } else {
242 return __ as_Address(laddr);
243 }
244 }
245
246 Register base = addr->base()->as_pointer_register();
247
248 if (addr->index()->is_illegal()) {
249 return Address( base, addr->disp());
250 } else if (addr->index()->is_cpu_register()) {
251 Register index = addr->index()->as_pointer_register();
252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
253 } else if (addr->index()->is_constant()) {
254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
255 assert(Assembler::is_simm32(addr_offset), "must be");
256
257 return Address(base, addr_offset);
258 } else {
259 Unimplemented();
260 return Address();
261 }
262 }
263
264
265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
266 Address base = as_Address(addr);
267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
268 }
269
270
271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
272 return as_Address(addr);
273 }
274
275
276 void LIR_Assembler::osr_entry() {
277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
278 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
279 ValueStack* entry_state = osr_entry->state();
280 int number_of_locks = entry_state->locks_size();
281
282 // we jump here if osr happens with the interpreter
283 // state set up to continue at the beginning of the
284 // loop that triggered osr - in particular, we have
285 // the following registers setup:
286 //
287 // rcx: osr buffer
288 //
289
290 // build frame
291 ciMethod* m = compilation()->method();
292 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
293
294 // OSR buffer is
295 //
296 // locals[nlocals-1..0]
297 // monitors[0..number_of_locks]
298 //
299 // locals is a direct copy of the interpreter frame so in the osr buffer
300 // so first slot in the local array is the last local from the interpreter
301 // and last slot is local[0] (receiver) from the interpreter
302 //
303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
305 // in the interpreter frame (the method lock if a sync method)
306
307 // Initialize monitors in the compiled activation.
308 // rcx: pointer to osr buffer
309 //
310 // All other registers are dead at this point and the locals will be
311 // copied into place by code emitted in the IR.
312
313 Register OSR_buf = osrBufferPointer()->as_pointer_register();
314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
315 int monitor_offset = BytesPerWord * method()->max_locals() +
316 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
318 // the OSR buffer using 2 word entries: first the lock and then
319 // the oop.
320 for (int i = 0; i < number_of_locks; i++) {
321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
322 #ifdef ASSERT
323 // verify the interpreter's monitor has a non-null object
324 {
325 Label L;
326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
327 __ jcc(Assembler::notZero, L);
328 __ stop("locked object is NULL");
329 __ bind(L);
330 }
331 #endif
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
335 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
336 }
337 }
338 }
339
340
341 // inline cache check; done before the frame is built.
342 int LIR_Assembler::check_icache() {
343 Register receiver = FrameMap::receiver_opr->as_register();
344 Register ic_klass = IC_Klass;
345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
346 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
347 if (!do_post_padding) {
348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
349 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
350 }
351 int offset = __ offset();
352 __ inline_cache_check(receiver, IC_Klass);
353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
354 if (do_post_padding) {
355 // force alignment after the cache check.
356 // It's been verified to be aligned if !VerifyOops
357 __ align(CodeEntryAlignment);
358 }
359 return offset;
360 }
361
362
363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
364 jobject o = NULL;
365 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
366 __ movoop(reg, o);
367 patching_epilog(patch, lir_patch_normal, reg, info);
368 }
369
370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
371 Metadata* o = NULL;
372 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
373 __ mov_metadata(reg, o);
374 patching_epilog(patch, lir_patch_normal, reg, info);
375 }
376
377 // This specifies the rsp decrement needed to build the frame
378 int LIR_Assembler::initial_frame_size_in_bytes() const {
379 // if rounding, must let FrameMap know!
380
381 // The frame_map records size in slots (32bit word)
382
383 // subtract two words to account for return address and link
384 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
385 }
386
387
388 int LIR_Assembler::emit_exception_handler() {
389 // if the last instruction is a call (typically to do a throw which
390 // is coming at the end after block reordering) the return address
391 // must still point into the code area in order to avoid assertion
392 // failures when searching for the corresponding bci => add a nop
393 // (was bug 5/14/1999 - gri)
394 __ nop();
395
396 // generate code for exception handler
397 address handler_base = __ start_a_stub(exception_handler_size());
398 if (handler_base == NULL) {
399 // not enough space left for the handler
400 bailout("exception handler overflow");
401 return -1;
402 }
403
404 int offset = code_offset();
405
406 // the exception oop and pc are in rax, and rdx
407 // no other registers need to be preserved, so invalidate them
408 __ invalidate_registers(false, true, true, false, true, true);
409
410 // check that there is really an exception
411 __ verify_not_null_oop(rax);
412
413 // search an exception handler (rax: exception oop, rdx: throwing pc)
414 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
415 __ should_not_reach_here();
416 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
417 __ end_a_stub();
418
419 return offset;
420 }
421
422
423 // Emit the code to remove the frame from the stack in the exception
424 // unwind path.
425 int LIR_Assembler::emit_unwind_handler() {
426 #ifndef PRODUCT
427 if (CommentedAssembly) {
428 _masm->block_comment("Unwind handler");
429 }
430 #endif
431
432 int offset = code_offset();
433
434 // Fetch the exception from TLS and clear out exception related thread state
435 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
436 NOT_LP64(__ get_thread(rsi));
437 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
438 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
439 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
440
441 __ bind(_unwind_handler_entry);
442 __ verify_not_null_oop(rax);
443 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
444 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
445 }
446
447 // Preform needed unlocking
448 MonitorExitStub* stub = NULL;
449 if (method()->is_synchronized()) {
450 monitor_address(0, FrameMap::rax_opr);
451 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
452 __ unlock_object(rdi, rsi, rax, *stub->entry());
453 __ bind(*stub->continuation());
454 }
455
456 if (compilation()->env()->dtrace_method_probes()) {
457 #ifdef _LP64
458 __ mov(rdi, r15_thread);
459 __ mov_metadata(rsi, method()->constant_encoding());
460 #else
461 __ get_thread(rax);
462 __ movptr(Address(rsp, 0), rax);
463 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
464 #endif
465 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
466 }
467
468 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
469 __ mov(rax, rbx); // Restore the exception
470 }
471
472 // remove the activation and dispatch to the unwind handler
473 __ remove_frame(initial_frame_size_in_bytes());
474 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
475
476 // Emit the slow path assembly
477 if (stub != NULL) {
478 stub->emit_code(this);
479 }
480
481 return offset;
482 }
483
484
485 int LIR_Assembler::emit_deopt_handler() {
486 // if the last instruction is a call (typically to do a throw which
487 // is coming at the end after block reordering) the return address
488 // must still point into the code area in order to avoid assertion
489 // failures when searching for the corresponding bci => add a nop
490 // (was bug 5/14/1999 - gri)
491 __ nop();
492
493 // generate code for exception handler
494 address handler_base = __ start_a_stub(deopt_handler_size());
495 if (handler_base == NULL) {
496 // not enough space left for the handler
497 bailout("deopt handler overflow");
498 return -1;
499 }
500
501 int offset = code_offset();
502 InternalAddress here(__ pc());
503
504 __ pushptr(here.addr());
505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
506 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
507 __ end_a_stub();
508
509 return offset;
510 }
511
512
513 void LIR_Assembler::return_op(LIR_Opr result) {
514 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
515 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
516 assert(result->fpu() == 0, "result must already be on TOS");
517 }
518
519 // Pop the stack before the safepoint code
520 __ remove_frame(initial_frame_size_in_bytes());
521
522 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
523 __ reserved_stack_check();
524 }
525
526 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
527
528 // Note: we do not need to round double result; float result has the right precision
529 // the poll sets the condition code, but no data registers
530
531 if (SafepointMechanism::uses_thread_local_poll()) {
532 #ifdef _LP64
533 const Register poll_addr = rscratch1;
534 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
535 #else
536 const Register poll_addr = rbx;
537 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
538 __ get_thread(poll_addr);
539 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
540 #endif
541 __ relocate(relocInfo::poll_return_type);
542 __ testl(rax, Address(poll_addr, 0));
543 } else {
544 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
545
546 if (Assembler::is_polling_page_far()) {
547 __ lea(rscratch1, polling_page);
548 __ relocate(relocInfo::poll_return_type);
549 __ testl(rax, Address(rscratch1, 0));
550 } else {
551 __ testl(rax, polling_page);
552 }
553 }
554 __ ret(0);
555 }
556
557
558 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
559 guarantee(info != NULL, "Shouldn't be NULL");
560 int offset = __ offset();
561 if (SafepointMechanism::uses_thread_local_poll()) {
562 #ifdef _LP64
563 const Register poll_addr = rscratch1;
564 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
565 #else
566 assert(tmp->is_cpu_register(), "needed");
567 const Register poll_addr = tmp->as_register();
568 __ get_thread(poll_addr);
569 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
570 #endif
571 add_debug_info_for_branch(info);
572 __ relocate(relocInfo::poll_type);
573 address pre_pc = __ pc();
574 __ testl(rax, Address(poll_addr, 0));
575 address post_pc = __ pc();
576 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
577 } else {
578 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
579 if (Assembler::is_polling_page_far()) {
580 __ lea(rscratch1, polling_page);
581 offset = __ offset();
582 add_debug_info_for_branch(info);
583 __ relocate(relocInfo::poll_type);
584 __ testl(rax, Address(rscratch1, 0));
585 } else {
586 add_debug_info_for_branch(info);
587 __ testl(rax, polling_page);
588 }
589 }
590 return offset;
591 }
592
593
594 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
595 if (from_reg != to_reg) __ mov(to_reg, from_reg);
596 }
597
598 void LIR_Assembler::swap_reg(Register a, Register b) {
599 __ xchgptr(a, b);
600 }
601
602
603 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
604 assert(src->is_constant(), "should not call otherwise");
605 assert(dest->is_register(), "should not call otherwise");
606 LIR_Const* c = src->as_constant_ptr();
607
608 switch (c->type()) {
609 case T_INT: {
610 assert(patch_code == lir_patch_none, "no patching handled here");
611 __ movl(dest->as_register(), c->as_jint());
612 break;
613 }
614
615 case T_ADDRESS: {
616 assert(patch_code == lir_patch_none, "no patching handled here");
617 __ movptr(dest->as_register(), c->as_jint());
618 break;
619 }
620
621 case T_LONG: {
622 assert(patch_code == lir_patch_none, "no patching handled here");
623 #ifdef _LP64
624 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
625 #else
626 __ movptr(dest->as_register_lo(), c->as_jint_lo());
627 __ movptr(dest->as_register_hi(), c->as_jint_hi());
628 #endif // _LP64
629 break;
630 }
631
632 case T_VALUETYPE: // Fall through
633 case T_OBJECT: {
634 if (patch_code != lir_patch_none) {
635 jobject2reg_with_patching(dest->as_register(), info);
636 } else {
637 __ movoop(dest->as_register(), c->as_jobject());
638 }
639 break;
640 }
641
642 case T_METADATA: {
643 if (patch_code != lir_patch_none) {
644 klass2reg_with_patching(dest->as_register(), info);
645 } else {
646 __ mov_metadata(dest->as_register(), c->as_metadata());
647 }
648 break;
649 }
650
651 case T_FLOAT: {
652 if (dest->is_single_xmm()) {
653 if (LP64_ONLY(UseAVX < 2 &&) c->is_zero_float()) {
654 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
655 } else {
656 __ movflt(dest->as_xmm_float_reg(),
657 InternalAddress(float_constant(c->as_jfloat())));
658 }
659 } else {
660 assert(dest->is_single_fpu(), "must be");
661 assert(dest->fpu_regnr() == 0, "dest must be TOS");
662 if (c->is_zero_float()) {
663 __ fldz();
664 } else if (c->is_one_float()) {
665 __ fld1();
666 } else {
667 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
668 }
669 }
670 break;
671 }
672
673 case T_DOUBLE: {
674 if (dest->is_double_xmm()) {
675 if (LP64_ONLY(UseAVX < 2 &&) c->is_zero_double()) {
676 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
677 } else {
678 __ movdbl(dest->as_xmm_double_reg(),
679 InternalAddress(double_constant(c->as_jdouble())));
680 }
681 } else {
682 assert(dest->is_double_fpu(), "must be");
683 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
684 if (c->is_zero_double()) {
685 __ fldz();
686 } else if (c->is_one_double()) {
687 __ fld1();
688 } else {
689 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
690 }
691 }
692 break;
693 }
694
695 default:
696 ShouldNotReachHere();
697 }
698 }
699
700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
701 assert(src->is_constant(), "should not call otherwise");
702 assert(dest->is_stack(), "should not call otherwise");
703 LIR_Const* c = src->as_constant_ptr();
704
705 switch (c->type()) {
706 case T_INT: // fall through
707 case T_FLOAT:
708 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
709 break;
710
711 case T_ADDRESS:
712 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
713 break;
714
715 case T_VALUETYPE: // Fall through
716 case T_OBJECT:
717 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
718 break;
719
720 case T_LONG: // fall through
721 case T_DOUBLE:
722 #ifdef _LP64
723 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
724 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
725 #else
726 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
727 lo_word_offset_in_bytes), c->as_jint_lo_bits());
728 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
729 hi_word_offset_in_bytes), c->as_jint_hi_bits());
730 #endif // _LP64
731 break;
732
733 default:
734 ShouldNotReachHere();
735 }
736 }
737
738 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
739 assert(src->is_constant(), "should not call otherwise");
740 assert(dest->is_address(), "should not call otherwise");
741 LIR_Const* c = src->as_constant_ptr();
742 LIR_Address* addr = dest->as_address_ptr();
743
744 int null_check_here = code_offset();
745 switch (type) {
746 case T_INT: // fall through
747 case T_FLOAT:
748 __ movl(as_Address(addr), c->as_jint_bits());
749 break;
750
751 case T_ADDRESS:
752 __ movptr(as_Address(addr), c->as_jint_bits());
753 break;
754
755 case T_VALUETYPE: // fall through
756 case T_OBJECT: // fall through
757 case T_ARRAY:
758 if (c->as_jobject() == NULL) {
759 if (UseCompressedOops && !wide) {
760 __ movl(as_Address(addr), (int32_t)NULL_WORD);
761 } else {
762 #ifdef _LP64
763 __ xorptr(rscratch1, rscratch1);
764 null_check_here = code_offset();
765 __ movptr(as_Address(addr), rscratch1);
766 #else
767 __ movptr(as_Address(addr), NULL_WORD);
768 #endif
769 }
770 } else {
771 if (is_literal_address(addr)) {
772 ShouldNotReachHere();
773 __ movoop(as_Address(addr, noreg), c->as_jobject());
774 } else {
775 #ifdef _LP64
776 __ movoop(rscratch1, c->as_jobject());
777 if (UseCompressedOops && !wide) {
778 __ encode_heap_oop(rscratch1);
779 null_check_here = code_offset();
780 __ movl(as_Address_lo(addr), rscratch1);
781 } else {
782 null_check_here = code_offset();
783 __ movptr(as_Address_lo(addr), rscratch1);
784 }
785 #else
786 __ movoop(as_Address(addr), c->as_jobject());
787 #endif
788 }
789 }
790 break;
791
792 case T_LONG: // fall through
793 case T_DOUBLE:
794 #ifdef _LP64
795 if (is_literal_address(addr)) {
796 ShouldNotReachHere();
797 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
798 } else {
799 __ movptr(r10, (intptr_t)c->as_jlong_bits());
800 null_check_here = code_offset();
801 __ movptr(as_Address_lo(addr), r10);
802 }
803 #else
804 // Always reachable in 32bit so this doesn't produce useless move literal
805 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
806 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
807 #endif // _LP64
808 break;
809
810 case T_BOOLEAN: // fall through
811 case T_BYTE:
812 __ movb(as_Address(addr), c->as_jint() & 0xFF);
813 break;
814
815 case T_CHAR: // fall through
816 case T_SHORT:
817 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
818 break;
819
820 default:
821 ShouldNotReachHere();
822 };
823
824 if (info != NULL) {
825 add_debug_info_for_null_check(null_check_here, info);
826 }
827 }
828
829
830 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
831 assert(src->is_register(), "should not call otherwise");
832 assert(dest->is_register(), "should not call otherwise");
833
834 // move between cpu-registers
835 if (dest->is_single_cpu()) {
836 #ifdef _LP64
837 if (src->type() == T_LONG) {
838 // Can do LONG -> OBJECT
839 move_regs(src->as_register_lo(), dest->as_register());
840 return;
841 }
842 #endif
843 assert(src->is_single_cpu(), "must match");
844 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
845 __ verify_oop(src->as_register());
846 }
847 move_regs(src->as_register(), dest->as_register());
848
849 } else if (dest->is_double_cpu()) {
850 #ifdef _LP64
851 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
852 // Surprising to me but we can see move of a long to t_object
853 __ verify_oop(src->as_register());
854 move_regs(src->as_register(), dest->as_register_lo());
855 return;
856 }
857 #endif
858 assert(src->is_double_cpu(), "must match");
859 Register f_lo = src->as_register_lo();
860 Register f_hi = src->as_register_hi();
861 Register t_lo = dest->as_register_lo();
862 Register t_hi = dest->as_register_hi();
863 #ifdef _LP64
864 assert(f_hi == f_lo, "must be same");
865 assert(t_hi == t_lo, "must be same");
866 move_regs(f_lo, t_lo);
867 #else
868 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
869
870
871 if (f_lo == t_hi && f_hi == t_lo) {
872 swap_reg(f_lo, f_hi);
873 } else if (f_hi == t_lo) {
874 assert(f_lo != t_hi, "overwriting register");
875 move_regs(f_hi, t_hi);
876 move_regs(f_lo, t_lo);
877 } else {
878 assert(f_hi != t_lo, "overwriting register");
879 move_regs(f_lo, t_lo);
880 move_regs(f_hi, t_hi);
881 }
882 #endif // LP64
883
884 // special moves from fpu-register to xmm-register
885 // necessary for method results
886 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
887 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
888 __ fld_s(Address(rsp, 0));
889 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
890 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
891 __ fld_d(Address(rsp, 0));
892 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
893 __ fstp_s(Address(rsp, 0));
894 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
895 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
896 __ fstp_d(Address(rsp, 0));
897 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
898
899 // move between xmm-registers
900 } else if (dest->is_single_xmm()) {
901 assert(src->is_single_xmm(), "must match");
902 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
903 } else if (dest->is_double_xmm()) {
904 assert(src->is_double_xmm(), "must match");
905 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
906
907 // move between fpu-registers (no instruction necessary because of fpu-stack)
908 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
909 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
910 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
911 } else {
912 ShouldNotReachHere();
913 }
914 }
915
916 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
917 assert(src->is_register(), "should not call otherwise");
918 assert(dest->is_stack(), "should not call otherwise");
919
920 if (src->is_single_cpu()) {
921 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
922 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) {
923 __ verify_oop(src->as_register());
924 __ movptr (dst, src->as_register());
925 } else if (type == T_METADATA) {
926 __ movptr (dst, src->as_register());
927 } else {
928 __ movl (dst, src->as_register());
929 }
930
931 } else if (src->is_double_cpu()) {
932 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
933 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
934 __ movptr (dstLO, src->as_register_lo());
935 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
936
937 } else if (src->is_single_xmm()) {
938 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
939 __ movflt(dst_addr, src->as_xmm_float_reg());
940
941 } else if (src->is_double_xmm()) {
942 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
943 __ movdbl(dst_addr, src->as_xmm_double_reg());
944
945 } else if (src->is_single_fpu()) {
946 assert(src->fpu_regnr() == 0, "argument must be on TOS");
947 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
948 if (pop_fpu_stack) __ fstp_s (dst_addr);
949 else __ fst_s (dst_addr);
950
951 } else if (src->is_double_fpu()) {
952 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
953 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
954 if (pop_fpu_stack) __ fstp_d (dst_addr);
955 else __ fst_d (dst_addr);
956
957 } else {
958 ShouldNotReachHere();
959 }
960 }
961
962
963 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
964 LIR_Address* to_addr = dest->as_address_ptr();
965 PatchingStub* patch = NULL;
966 Register compressed_src = rscratch1;
967
968 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
969 __ verify_oop(src->as_register());
970 #ifdef _LP64
971 if (UseCompressedOops && !wide) {
972 __ movptr(compressed_src, src->as_register());
973 __ encode_heap_oop(compressed_src);
974 if (patch_code != lir_patch_none) {
975 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
976 }
977 }
978 #endif
979 }
980
981 if (patch_code != lir_patch_none) {
982 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
983 Address toa = as_Address(to_addr);
984 assert(toa.disp() != 0, "must have");
985 }
986
987 int null_check_here = code_offset();
988 switch (type) {
989 case T_FLOAT: {
990 if (src->is_single_xmm()) {
991 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
992 } else {
993 assert(src->is_single_fpu(), "must be");
994 assert(src->fpu_regnr() == 0, "argument must be on TOS");
995 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
996 else __ fst_s (as_Address(to_addr));
997 }
998 break;
999 }
1000
1001 case T_DOUBLE: {
1002 if (src->is_double_xmm()) {
1003 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1004 } else {
1005 assert(src->is_double_fpu(), "must be");
1006 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1007 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1008 else __ fst_d (as_Address(to_addr));
1009 }
1010 break;
1011 }
1012
1013 case T_VALUETYPE: // fall through
1014 case T_ARRAY: // fall through
1015 case T_OBJECT: // fall through
1016 if (UseCompressedOops && !wide) {
1017 __ movl(as_Address(to_addr), compressed_src);
1018 } else {
1019 __ movptr(as_Address(to_addr), src->as_register());
1020 }
1021 break;
1022 case T_METADATA:
1023 // We get here to store a method pointer to the stack to pass to
1024 // a dtrace runtime call. This can't work on 64 bit with
1025 // compressed klass ptrs: T_METADATA can be a compressed klass
1026 // ptr or a 64 bit method pointer.
1027 LP64_ONLY(ShouldNotReachHere());
1028 __ movptr(as_Address(to_addr), src->as_register());
1029 break;
1030 case T_ADDRESS:
1031 __ movptr(as_Address(to_addr), src->as_register());
1032 break;
1033 case T_INT:
1034 __ movl(as_Address(to_addr), src->as_register());
1035 break;
1036
1037 case T_LONG: {
1038 Register from_lo = src->as_register_lo();
1039 Register from_hi = src->as_register_hi();
1040 #ifdef _LP64
1041 __ movptr(as_Address_lo(to_addr), from_lo);
1042 #else
1043 Register base = to_addr->base()->as_register();
1044 Register index = noreg;
1045 if (to_addr->index()->is_register()) {
1046 index = to_addr->index()->as_register();
1047 }
1048 if (base == from_lo || index == from_lo) {
1049 assert(base != from_hi, "can't be");
1050 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1051 __ movl(as_Address_hi(to_addr), from_hi);
1052 if (patch != NULL) {
1053 patching_epilog(patch, lir_patch_high, base, info);
1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1055 patch_code = lir_patch_low;
1056 }
1057 __ movl(as_Address_lo(to_addr), from_lo);
1058 } else {
1059 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1060 __ movl(as_Address_lo(to_addr), from_lo);
1061 if (patch != NULL) {
1062 patching_epilog(patch, lir_patch_low, base, info);
1063 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1064 patch_code = lir_patch_high;
1065 }
1066 __ movl(as_Address_hi(to_addr), from_hi);
1067 }
1068 #endif // _LP64
1069 break;
1070 }
1071
1072 case T_BYTE: // fall through
1073 case T_BOOLEAN: {
1074 Register src_reg = src->as_register();
1075 Address dst_addr = as_Address(to_addr);
1076 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1077 __ movb(dst_addr, src_reg);
1078 break;
1079 }
1080
1081 case T_CHAR: // fall through
1082 case T_SHORT:
1083 __ movw(as_Address(to_addr), src->as_register());
1084 break;
1085
1086 default:
1087 ShouldNotReachHere();
1088 }
1089 if (info != NULL) {
1090 add_debug_info_for_null_check(null_check_here, info);
1091 }
1092
1093 if (patch_code != lir_patch_none) {
1094 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1095 }
1096 }
1097
1098
1099 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1100 assert(src->is_stack(), "should not call otherwise");
1101 assert(dest->is_register(), "should not call otherwise");
1102
1103 if (dest->is_single_cpu()) {
1104 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1105 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1106 __ verify_oop(dest->as_register());
1107 } else if (type == T_METADATA) {
1108 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1109 } else {
1110 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1111 }
1112
1113 } else if (dest->is_double_cpu()) {
1114 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1115 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1116 __ movptr(dest->as_register_lo(), src_addr_LO);
1117 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1118
1119 } else if (dest->is_single_xmm()) {
1120 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1121 __ movflt(dest->as_xmm_float_reg(), src_addr);
1122
1123 } else if (dest->is_double_xmm()) {
1124 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1125 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1126
1127 } else if (dest->is_single_fpu()) {
1128 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1129 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1130 __ fld_s(src_addr);
1131
1132 } else if (dest->is_double_fpu()) {
1133 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1134 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1135 __ fld_d(src_addr);
1136
1137 } else {
1138 ShouldNotReachHere();
1139 }
1140 }
1141
1142
1143 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1144 if (src->is_single_stack()) {
1145 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) {
1146 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1147 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1148 } else {
1149 #ifndef _LP64
1150 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1151 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1152 #else
1153 //no pushl on 64bits
1154 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1155 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1156 #endif
1157 }
1158
1159 } else if (src->is_double_stack()) {
1160 #ifdef _LP64
1161 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1162 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1163 #else
1164 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1165 // push and pop the part at src + wordSize, adding wordSize for the previous push
1166 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1167 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1168 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1169 #endif // _LP64
1170
1171 } else {
1172 ShouldNotReachHere();
1173 }
1174 }
1175
1176
1177 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1178 assert(src->is_address(), "should not call otherwise");
1179 assert(dest->is_register(), "should not call otherwise");
1180
1181 LIR_Address* addr = src->as_address_ptr();
1182 Address from_addr = as_Address(addr);
1183
1184 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
1185 __ verify_oop(addr->base()->as_pointer_register());
1186 }
1187
1188 switch (type) {
1189 case T_BOOLEAN: // fall through
1190 case T_BYTE: // fall through
1191 case T_CHAR: // fall through
1192 case T_SHORT:
1193 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1194 // on pre P6 processors we may get partial register stalls
1195 // so blow away the value of to_rinfo before loading a
1196 // partial word into it. Do it here so that it precedes
1197 // the potential patch point below.
1198 __ xorptr(dest->as_register(), dest->as_register());
1199 }
1200 break;
1201 default:
1202 break;
1203 }
1204
1205 PatchingStub* patch = NULL;
1206 if (patch_code != lir_patch_none) {
1207 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1208 assert(from_addr.disp() != 0, "must have");
1209 }
1210 if (info != NULL) {
1211 add_debug_info_for_null_check_here(info);
1212 }
1213
1214 switch (type) {
1215 case T_FLOAT: {
1216 if (dest->is_single_xmm()) {
1217 __ movflt(dest->as_xmm_float_reg(), from_addr);
1218 } else {
1219 assert(dest->is_single_fpu(), "must be");
1220 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1221 __ fld_s(from_addr);
1222 }
1223 break;
1224 }
1225
1226 case T_DOUBLE: {
1227 if (dest->is_double_xmm()) {
1228 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1229 } else {
1230 assert(dest->is_double_fpu(), "must be");
1231 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1232 __ fld_d(from_addr);
1233 }
1234 break;
1235 }
1236
1237 case T_VALUETYPE: // fall through
1238 case T_OBJECT: // fall through
1239 case T_ARRAY: // fall through
1240 if (UseCompressedOops && !wide) {
1241 __ movl(dest->as_register(), from_addr);
1242 } else {
1243 __ movptr(dest->as_register(), from_addr);
1244 }
1245 break;
1246
1247 case T_ADDRESS:
1248 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1249 __ movl(dest->as_register(), from_addr);
1250 } else {
1251 __ movptr(dest->as_register(), from_addr);
1252 }
1253 break;
1254 case T_INT:
1255 __ movl(dest->as_register(), from_addr);
1256 break;
1257
1258 case T_LONG: {
1259 Register to_lo = dest->as_register_lo();
1260 Register to_hi = dest->as_register_hi();
1261 #ifdef _LP64
1262 __ movptr(to_lo, as_Address_lo(addr));
1263 #else
1264 Register base = addr->base()->as_register();
1265 Register index = noreg;
1266 if (addr->index()->is_register()) {
1267 index = addr->index()->as_register();
1268 }
1269 if ((base == to_lo && index == to_hi) ||
1270 (base == to_hi && index == to_lo)) {
1271 // addresses with 2 registers are only formed as a result of
1272 // array access so this code will never have to deal with
1273 // patches or null checks.
1274 assert(info == NULL && patch == NULL, "must be");
1275 __ lea(to_hi, as_Address(addr));
1276 __ movl(to_lo, Address(to_hi, 0));
1277 __ movl(to_hi, Address(to_hi, BytesPerWord));
1278 } else if (base == to_lo || index == to_lo) {
1279 assert(base != to_hi, "can't be");
1280 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1281 __ movl(to_hi, as_Address_hi(addr));
1282 if (patch != NULL) {
1283 patching_epilog(patch, lir_patch_high, base, info);
1284 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1285 patch_code = lir_patch_low;
1286 }
1287 __ movl(to_lo, as_Address_lo(addr));
1288 } else {
1289 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1290 __ movl(to_lo, as_Address_lo(addr));
1291 if (patch != NULL) {
1292 patching_epilog(patch, lir_patch_low, base, info);
1293 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1294 patch_code = lir_patch_high;
1295 }
1296 __ movl(to_hi, as_Address_hi(addr));
1297 }
1298 #endif // _LP64
1299 break;
1300 }
1301
1302 case T_BOOLEAN: // fall through
1303 case T_BYTE: {
1304 Register dest_reg = dest->as_register();
1305 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1306 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1307 __ movsbl(dest_reg, from_addr);
1308 } else {
1309 __ movb(dest_reg, from_addr);
1310 __ shll(dest_reg, 24);
1311 __ sarl(dest_reg, 24);
1312 }
1313 break;
1314 }
1315
1316 case T_CHAR: {
1317 Register dest_reg = dest->as_register();
1318 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1319 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1320 __ movzwl(dest_reg, from_addr);
1321 } else {
1322 __ movw(dest_reg, from_addr);
1323 }
1324 break;
1325 }
1326
1327 case T_SHORT: {
1328 Register dest_reg = dest->as_register();
1329 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1330 __ movswl(dest_reg, from_addr);
1331 } else {
1332 __ movw(dest_reg, from_addr);
1333 __ shll(dest_reg, 16);
1334 __ sarl(dest_reg, 16);
1335 }
1336 break;
1337 }
1338
1339 default:
1340 ShouldNotReachHere();
1341 }
1342
1343 if (patch != NULL) {
1344 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1345 }
1346
1347 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1348 #ifdef _LP64
1349 if (UseCompressedOops && !wide) {
1350 __ decode_heap_oop(dest->as_register());
1351 }
1352 #endif
1353
1354 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1355 if (!UseZGC) {
1356 __ verify_oop(dest->as_register());
1357 }
1358 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1359 #ifdef _LP64
1360 if (UseCompressedClassPointers) {
1361 __ decode_klass_not_null(dest->as_register());
1362 }
1363 #endif
1364 }
1365 }
1366
1367
1368 NEEDS_CLEANUP; // This could be static?
1369 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1370 int elem_size = type2aelembytes(type);
1371 switch (elem_size) {
1372 case 1: return Address::times_1;
1373 case 2: return Address::times_2;
1374 case 4: return Address::times_4;
1375 case 8: return Address::times_8;
1376 }
1377 ShouldNotReachHere();
1378 return Address::no_scale;
1379 }
1380
1381
1382 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1383 switch (op->code()) {
1384 case lir_idiv:
1385 case lir_irem:
1386 arithmetic_idiv(op->code(),
1387 op->in_opr1(),
1388 op->in_opr2(),
1389 op->in_opr3(),
1390 op->result_opr(),
1391 op->info());
1392 break;
1393 case lir_fmad:
1394 __ fmad(op->result_opr()->as_xmm_double_reg(),
1395 op->in_opr1()->as_xmm_double_reg(),
1396 op->in_opr2()->as_xmm_double_reg(),
1397 op->in_opr3()->as_xmm_double_reg());
1398 break;
1399 case lir_fmaf:
1400 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1401 op->in_opr1()->as_xmm_float_reg(),
1402 op->in_opr2()->as_xmm_float_reg(),
1403 op->in_opr3()->as_xmm_float_reg());
1404 break;
1405 default: ShouldNotReachHere(); break;
1406 }
1407 }
1408
1409 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1410 #ifdef ASSERT
1411 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1412 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1413 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1414 #endif
1415
1416 if (op->cond() == lir_cond_always) {
1417 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1418 __ jmp (*(op->label()));
1419 } else {
1420 Assembler::Condition acond = Assembler::zero;
1421 if (op->code() == lir_cond_float_branch) {
1422 assert(op->ublock() != NULL, "must have unordered successor");
1423 __ jcc(Assembler::parity, *(op->ublock()->label()));
1424 switch(op->cond()) {
1425 case lir_cond_equal: acond = Assembler::equal; break;
1426 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1427 case lir_cond_less: acond = Assembler::below; break;
1428 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1429 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1430 case lir_cond_greater: acond = Assembler::above; break;
1431 default: ShouldNotReachHere();
1432 }
1433 } else {
1434 switch (op->cond()) {
1435 case lir_cond_equal: acond = Assembler::equal; break;
1436 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1437 case lir_cond_less: acond = Assembler::less; break;
1438 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1439 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1440 case lir_cond_greater: acond = Assembler::greater; break;
1441 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1442 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1443 default: ShouldNotReachHere();
1444 }
1445 }
1446 __ jcc(acond,*(op->label()));
1447 }
1448 }
1449
1450 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1451 LIR_Opr src = op->in_opr();
1452 LIR_Opr dest = op->result_opr();
1453
1454 switch (op->bytecode()) {
1455 case Bytecodes::_i2l:
1456 #ifdef _LP64
1457 __ movl2ptr(dest->as_register_lo(), src->as_register());
1458 #else
1459 move_regs(src->as_register(), dest->as_register_lo());
1460 move_regs(src->as_register(), dest->as_register_hi());
1461 __ sarl(dest->as_register_hi(), 31);
1462 #endif // LP64
1463 break;
1464
1465 case Bytecodes::_l2i:
1466 #ifdef _LP64
1467 __ movl(dest->as_register(), src->as_register_lo());
1468 #else
1469 move_regs(src->as_register_lo(), dest->as_register());
1470 #endif
1471 break;
1472
1473 case Bytecodes::_i2b:
1474 move_regs(src->as_register(), dest->as_register());
1475 __ sign_extend_byte(dest->as_register());
1476 break;
1477
1478 case Bytecodes::_i2c:
1479 move_regs(src->as_register(), dest->as_register());
1480 __ andl(dest->as_register(), 0xFFFF);
1481 break;
1482
1483 case Bytecodes::_i2s:
1484 move_regs(src->as_register(), dest->as_register());
1485 __ sign_extend_short(dest->as_register());
1486 break;
1487
1488
1489 case Bytecodes::_f2d:
1490 case Bytecodes::_d2f:
1491 if (dest->is_single_xmm()) {
1492 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1493 } else if (dest->is_double_xmm()) {
1494 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1495 } else {
1496 assert(src->fpu() == dest->fpu(), "register must be equal");
1497 // do nothing (float result is rounded later through spilling)
1498 }
1499 break;
1500
1501 case Bytecodes::_i2f:
1502 case Bytecodes::_i2d:
1503 if (dest->is_single_xmm()) {
1504 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1505 } else if (dest->is_double_xmm()) {
1506 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1507 } else {
1508 assert(dest->fpu() == 0, "result must be on TOS");
1509 __ movl(Address(rsp, 0), src->as_register());
1510 __ fild_s(Address(rsp, 0));
1511 }
1512 break;
1513
1514 case Bytecodes::_f2i:
1515 case Bytecodes::_d2i:
1516 if (src->is_single_xmm()) {
1517 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1518 } else if (src->is_double_xmm()) {
1519 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1520 } else {
1521 assert(src->fpu() == 0, "input must be on TOS");
1522 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1523 __ fist_s(Address(rsp, 0));
1524 __ movl(dest->as_register(), Address(rsp, 0));
1525 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1526 }
1527
1528 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1529 assert(op->stub() != NULL, "stub required");
1530 __ cmpl(dest->as_register(), 0x80000000);
1531 __ jcc(Assembler::equal, *op->stub()->entry());
1532 __ bind(*op->stub()->continuation());
1533 break;
1534
1535 case Bytecodes::_l2f:
1536 case Bytecodes::_l2d:
1537 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1538 assert(dest->fpu() == 0, "result must be on TOS");
1539
1540 __ movptr(Address(rsp, 0), src->as_register_lo());
1541 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1542 __ fild_d(Address(rsp, 0));
1543 // float result is rounded later through spilling
1544 break;
1545
1546 case Bytecodes::_f2l:
1547 case Bytecodes::_d2l:
1548 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1549 assert(src->fpu() == 0, "input must be on TOS");
1550 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1551
1552 // instruction sequence too long to inline it here
1553 {
1554 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1555 }
1556 break;
1557
1558 default: ShouldNotReachHere();
1559 }
1560 }
1561
1562 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1563 if (op->init_check()) {
1564 add_debug_info_for_null_check_here(op->stub()->info());
1565 __ cmpb(Address(op->klass()->as_register(),
1566 InstanceKlass::init_state_offset()),
1567 InstanceKlass::fully_initialized);
1568 __ jcc(Assembler::notEqual, *op->stub()->entry());
1569 }
1570 __ allocate_object(op->obj()->as_register(),
1571 op->tmp1()->as_register(),
1572 op->tmp2()->as_register(),
1573 op->header_size(),
1574 op->object_size(),
1575 op->klass()->as_register(),
1576 *op->stub()->entry());
1577 __ bind(*op->stub()->continuation());
1578 }
1579
1580 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1581 Register len = op->len()->as_register();
1582 LP64_ONLY( __ movslq(len, len); )
1583
1584 if (UseSlowPath || op->type() == T_VALUETYPE ||
1585 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1586 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1587 __ jmp(*op->stub()->entry());
1588 } else {
1589 Register tmp1 = op->tmp1()->as_register();
1590 Register tmp2 = op->tmp2()->as_register();
1591 Register tmp3 = op->tmp3()->as_register();
1592 if (len == tmp1) {
1593 tmp1 = tmp3;
1594 } else if (len == tmp2) {
1595 tmp2 = tmp3;
1596 } else if (len == tmp3) {
1597 // everything is ok
1598 } else {
1599 __ mov(tmp3, len);
1600 }
1601 __ allocate_array(op->obj()->as_register(),
1602 len,
1603 tmp1,
1604 tmp2,
1605 arrayOopDesc::header_size(op->type()),
1606 array_element_size(op->type()),
1607 op->klass()->as_register(),
1608 *op->stub()->entry());
1609 }
1610 __ bind(*op->stub()->continuation());
1611 }
1612
1613 void LIR_Assembler::type_profile_helper(Register mdo,
1614 ciMethodData *md, ciProfileData *data,
1615 Register recv, Label* update_done) {
1616 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1617 Label next_test;
1618 // See if the receiver is receiver[n].
1619 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1620 __ jccb(Assembler::notEqual, next_test);
1621 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1622 __ addptr(data_addr, DataLayout::counter_increment);
1623 __ jmp(*update_done);
1624 __ bind(next_test);
1625 }
1626
1627 // Didn't find receiver; find next empty slot and fill it in
1628 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1629 Label next_test;
1630 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1631 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1632 __ jccb(Assembler::notEqual, next_test);
1633 __ movptr(recv_addr, recv);
1634 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1635 __ jmp(*update_done);
1636 __ bind(next_test);
1637 }
1638 }
1639
1640 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1641 // we always need a stub for the failure case.
1642 CodeStub* stub = op->stub();
1643 Register obj = op->object()->as_register();
1644 Register k_RInfo = op->tmp1()->as_register();
1645 Register klass_RInfo = op->tmp2()->as_register();
1646 Register dst = op->result_opr()->as_register();
1647 ciKlass* k = op->klass();
1648 Register Rtmp1 = noreg;
1649
1650 // check if it needs to be profiled
1651 ciMethodData* md = NULL;
1652 ciProfileData* data = NULL;
1653
1654 if (op->should_profile()) {
1655 ciMethod* method = op->profiled_method();
1656 assert(method != NULL, "Should have method");
1657 int bci = op->profiled_bci();
1658 md = method->method_data_or_null();
1659 assert(md != NULL, "Sanity");
1660 data = md->bci_to_data(bci);
1661 assert(data != NULL, "need data for type check");
1662 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1663 }
1664 Label profile_cast_success, profile_cast_failure;
1665 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1666 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1667
1668 if (obj == k_RInfo) {
1669 k_RInfo = dst;
1670 } else if (obj == klass_RInfo) {
1671 klass_RInfo = dst;
1672 }
1673 if (k->is_loaded() && !UseCompressedClassPointers) {
1674 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1675 } else {
1676 Rtmp1 = op->tmp3()->as_register();
1677 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1678 }
1679
1680 assert_different_registers(obj, k_RInfo, klass_RInfo);
1681
1682 __ cmpptr(obj, (int32_t)NULL_WORD);
1683 if (op->should_profile()) {
1684 Label not_null;
1685 __ jccb(Assembler::notEqual, not_null);
1686 // Object is null; update MDO and exit
1687 Register mdo = klass_RInfo;
1688 __ mov_metadata(mdo, md->constant_encoding());
1689 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1690 int header_bits = BitData::null_seen_byte_constant();
1691 __ orb(data_addr, header_bits);
1692 __ jmp(*obj_is_null);
1693 __ bind(not_null);
1694 } else {
1695 __ jcc(Assembler::equal, *obj_is_null);
1696 }
1697
1698 if (!k->is_loaded()) {
1699 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1700 } else {
1701 #ifdef _LP64
1702 __ mov_metadata(k_RInfo, k->constant_encoding());
1703 #endif // _LP64
1704 }
1705 __ verify_oop(obj);
1706
1707 if (op->fast_check()) {
1708 // get object class
1709 // not a safepoint as obj null check happens earlier
1710 #ifdef _LP64
1711 if (UseCompressedClassPointers) {
1712 __ load_klass(Rtmp1, obj);
1713 __ cmpptr(k_RInfo, Rtmp1);
1714 } else {
1715 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1716 }
1717 #else
1718 if (k->is_loaded()) {
1719 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1720 } else {
1721 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1722 }
1723 #endif
1724 __ jcc(Assembler::notEqual, *failure_target);
1725 // successful cast, fall through to profile or jump
1726 } else {
1727 // get object class
1728 // not a safepoint as obj null check happens earlier
1729 __ load_klass(klass_RInfo, obj);
1730 if (k->is_loaded()) {
1731 // See if we get an immediate positive hit
1732 #ifdef _LP64
1733 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1734 #else
1735 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1736 #endif // _LP64
1737 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1738 __ jcc(Assembler::notEqual, *failure_target);
1739 // successful cast, fall through to profile or jump
1740 } else {
1741 // See if we get an immediate positive hit
1742 __ jcc(Assembler::equal, *success_target);
1743 // check for self
1744 #ifdef _LP64
1745 __ cmpptr(klass_RInfo, k_RInfo);
1746 #else
1747 __ cmpklass(klass_RInfo, k->constant_encoding());
1748 #endif // _LP64
1749 __ jcc(Assembler::equal, *success_target);
1750
1751 __ push(klass_RInfo);
1752 #ifdef _LP64
1753 __ push(k_RInfo);
1754 #else
1755 __ pushklass(k->constant_encoding());
1756 #endif // _LP64
1757 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1758 __ pop(klass_RInfo);
1759 __ pop(klass_RInfo);
1760 // result is a boolean
1761 __ cmpl(klass_RInfo, 0);
1762 __ jcc(Assembler::equal, *failure_target);
1763 // successful cast, fall through to profile or jump
1764 }
1765 } else {
1766 // perform the fast part of the checking logic
1767 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1768 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1769 __ push(klass_RInfo);
1770 __ push(k_RInfo);
1771 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1772 __ pop(klass_RInfo);
1773 __ pop(k_RInfo);
1774 // result is a boolean
1775 __ cmpl(k_RInfo, 0);
1776 __ jcc(Assembler::equal, *failure_target);
1777 // successful cast, fall through to profile or jump
1778 }
1779 }
1780 if (op->should_profile()) {
1781 Register mdo = klass_RInfo, recv = k_RInfo;
1782 __ bind(profile_cast_success);
1783 __ mov_metadata(mdo, md->constant_encoding());
1784 __ load_klass(recv, obj);
1785 type_profile_helper(mdo, md, data, recv, success);
1786 __ jmp(*success);
1787
1788 __ bind(profile_cast_failure);
1789 __ mov_metadata(mdo, md->constant_encoding());
1790 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1791 __ subptr(counter_addr, DataLayout::counter_increment);
1792 __ jmp(*failure);
1793 }
1794 __ jmp(*success);
1795 }
1796
1797
1798 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1799 LIR_Code code = op->code();
1800 if (code == lir_store_check) {
1801 Register value = op->object()->as_register();
1802 Register array = op->array()->as_register();
1803 Register k_RInfo = op->tmp1()->as_register();
1804 Register klass_RInfo = op->tmp2()->as_register();
1805 Register Rtmp1 = op->tmp3()->as_register();
1806
1807 CodeStub* stub = op->stub();
1808
1809 // check if it needs to be profiled
1810 ciMethodData* md = NULL;
1811 ciProfileData* data = NULL;
1812
1813 if (op->should_profile()) {
1814 ciMethod* method = op->profiled_method();
1815 assert(method != NULL, "Should have method");
1816 int bci = op->profiled_bci();
1817 md = method->method_data_or_null();
1818 assert(md != NULL, "Sanity");
1819 data = md->bci_to_data(bci);
1820 assert(data != NULL, "need data for type check");
1821 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1822 }
1823 Label profile_cast_success, profile_cast_failure, done;
1824 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1825 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1826
1827 __ cmpptr(value, (int32_t)NULL_WORD);
1828 if (op->should_profile()) {
1829 Label not_null;
1830 __ jccb(Assembler::notEqual, not_null);
1831 // Object is null; update MDO and exit
1832 Register mdo = klass_RInfo;
1833 __ mov_metadata(mdo, md->constant_encoding());
1834 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1835 int header_bits = BitData::null_seen_byte_constant();
1836 __ orb(data_addr, header_bits);
1837 __ jmp(done);
1838 __ bind(not_null);
1839 } else {
1840 __ jcc(Assembler::equal, done);
1841 }
1842
1843 add_debug_info_for_null_check_here(op->info_for_exception());
1844 __ load_klass(k_RInfo, array);
1845 __ load_klass(klass_RInfo, value);
1846
1847 // get instance klass (it's already uncompressed)
1848 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1849 // perform the fast part of the checking logic
1850 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1851 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1852 __ push(klass_RInfo);
1853 __ push(k_RInfo);
1854 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1855 __ pop(klass_RInfo);
1856 __ pop(k_RInfo);
1857 // result is a boolean
1858 __ cmpl(k_RInfo, 0);
1859 __ jcc(Assembler::equal, *failure_target);
1860 // fall through to the success case
1861
1862 if (op->should_profile()) {
1863 Register mdo = klass_RInfo, recv = k_RInfo;
1864 __ bind(profile_cast_success);
1865 __ mov_metadata(mdo, md->constant_encoding());
1866 __ load_klass(recv, value);
1867 type_profile_helper(mdo, md, data, recv, &done);
1868 __ jmpb(done);
1869
1870 __ bind(profile_cast_failure);
1871 __ mov_metadata(mdo, md->constant_encoding());
1872 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1873 __ subptr(counter_addr, DataLayout::counter_increment);
1874 __ jmp(*stub->entry());
1875 }
1876
1877 __ bind(done);
1878 } else
1879 if (code == lir_checkcast) {
1880 Register obj = op->object()->as_register();
1881 Register dst = op->result_opr()->as_register();
1882 Label success;
1883 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1884 __ bind(success);
1885 if (dst != obj) {
1886 __ mov(dst, obj);
1887 }
1888 } else
1889 if (code == lir_instanceof) {
1890 Register obj = op->object()->as_register();
1891 Register dst = op->result_opr()->as_register();
1892 Label success, failure, done;
1893 emit_typecheck_helper(op, &success, &failure, &failure);
1894 __ bind(failure);
1895 __ xorptr(dst, dst);
1896 __ jmpb(done);
1897 __ bind(success);
1898 __ movptr(dst, 1);
1899 __ bind(done);
1900 } else {
1901 ShouldNotReachHere();
1902 }
1903
1904 }
1905
1906
1907 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1908 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1909 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1910 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1911 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1912 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1913 Register addr = op->addr()->as_register();
1914 __ lock();
1915 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1916
1917 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1918 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1919 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1920 Register newval = op->new_value()->as_register();
1921 Register cmpval = op->cmp_value()->as_register();
1922 assert(cmpval == rax, "wrong register");
1923 assert(newval != NULL, "new val must be register");
1924 assert(cmpval != newval, "cmp and new values must be in different registers");
1925 assert(cmpval != addr, "cmp and addr must be in different registers");
1926 assert(newval != addr, "new value and addr must be in different registers");
1927
1928 if ( op->code() == lir_cas_obj) {
1929 #ifdef _LP64
1930 if (UseCompressedOops) {
1931 __ encode_heap_oop(cmpval);
1932 __ mov(rscratch1, newval);
1933 __ encode_heap_oop(rscratch1);
1934 __ lock();
1935 // cmpval (rax) is implicitly used by this instruction
1936 __ cmpxchgl(rscratch1, Address(addr, 0));
1937 } else
1938 #endif
1939 {
1940 __ lock();
1941 __ cmpxchgptr(newval, Address(addr, 0));
1942 }
1943 } else {
1944 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1945 __ lock();
1946 __ cmpxchgl(newval, Address(addr, 0));
1947 }
1948 #ifdef _LP64
1949 } else if (op->code() == lir_cas_long) {
1950 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1951 Register newval = op->new_value()->as_register_lo();
1952 Register cmpval = op->cmp_value()->as_register_lo();
1953 assert(cmpval == rax, "wrong register");
1954 assert(newval != NULL, "new val must be register");
1955 assert(cmpval != newval, "cmp and new values must be in different registers");
1956 assert(cmpval != addr, "cmp and addr must be in different registers");
1957 assert(newval != addr, "new value and addr must be in different registers");
1958 __ lock();
1959 __ cmpxchgq(newval, Address(addr, 0));
1960 #endif // _LP64
1961 } else {
1962 Unimplemented();
1963 }
1964 }
1965
1966 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1967 Assembler::Condition acond, ncond;
1968 switch (condition) {
1969 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1970 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1971 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1972 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1973 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1974 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1975 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1976 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1977 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1978 ShouldNotReachHere();
1979 }
1980
1981 if (opr1->is_cpu_register()) {
1982 reg2reg(opr1, result);
1983 } else if (opr1->is_stack()) {
1984 stack2reg(opr1, result, result->type());
1985 } else if (opr1->is_constant()) {
1986 const2reg(opr1, result, lir_patch_none, NULL);
1987 } else {
1988 ShouldNotReachHere();
1989 }
1990
1991 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1992 // optimized version that does not require a branch
1993 if (opr2->is_single_cpu()) {
1994 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1995 __ cmov(ncond, result->as_register(), opr2->as_register());
1996 } else if (opr2->is_double_cpu()) {
1997 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1998 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1999 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2000 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2001 } else if (opr2->is_single_stack()) {
2002 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2003 } else if (opr2->is_double_stack()) {
2004 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2005 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2006 } else {
2007 ShouldNotReachHere();
2008 }
2009
2010 } else {
2011 Label skip;
2012 __ jcc (acond, skip);
2013 if (opr2->is_cpu_register()) {
2014 reg2reg(opr2, result);
2015 } else if (opr2->is_stack()) {
2016 stack2reg(opr2, result, result->type());
2017 } else if (opr2->is_constant()) {
2018 const2reg(opr2, result, lir_patch_none, NULL);
2019 } else {
2020 ShouldNotReachHere();
2021 }
2022 __ bind(skip);
2023 }
2024 }
2025
2026
2027 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2028 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2029
2030 if (left->is_single_cpu()) {
2031 assert(left == dest, "left and dest must be equal");
2032 Register lreg = left->as_register();
2033
2034 if (right->is_single_cpu()) {
2035 // cpu register - cpu register
2036 Register rreg = right->as_register();
2037 switch (code) {
2038 case lir_add: __ addl (lreg, rreg); break;
2039 case lir_sub: __ subl (lreg, rreg); break;
2040 case lir_mul: __ imull(lreg, rreg); break;
2041 default: ShouldNotReachHere();
2042 }
2043
2044 } else if (right->is_stack()) {
2045 // cpu register - stack
2046 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2047 switch (code) {
2048 case lir_add: __ addl(lreg, raddr); break;
2049 case lir_sub: __ subl(lreg, raddr); break;
2050 default: ShouldNotReachHere();
2051 }
2052
2053 } else if (right->is_constant()) {
2054 // cpu register - constant
2055 jint c = right->as_constant_ptr()->as_jint();
2056 switch (code) {
2057 case lir_add: {
2058 __ incrementl(lreg, c);
2059 break;
2060 }
2061 case lir_sub: {
2062 __ decrementl(lreg, c);
2063 break;
2064 }
2065 default: ShouldNotReachHere();
2066 }
2067
2068 } else {
2069 ShouldNotReachHere();
2070 }
2071
2072 } else if (left->is_double_cpu()) {
2073 assert(left == dest, "left and dest must be equal");
2074 Register lreg_lo = left->as_register_lo();
2075 Register lreg_hi = left->as_register_hi();
2076
2077 if (right->is_double_cpu()) {
2078 // cpu register - cpu register
2079 Register rreg_lo = right->as_register_lo();
2080 Register rreg_hi = right->as_register_hi();
2081 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2082 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2083 switch (code) {
2084 case lir_add:
2085 __ addptr(lreg_lo, rreg_lo);
2086 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2087 break;
2088 case lir_sub:
2089 __ subptr(lreg_lo, rreg_lo);
2090 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2091 break;
2092 case lir_mul:
2093 #ifdef _LP64
2094 __ imulq(lreg_lo, rreg_lo);
2095 #else
2096 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2097 __ imull(lreg_hi, rreg_lo);
2098 __ imull(rreg_hi, lreg_lo);
2099 __ addl (rreg_hi, lreg_hi);
2100 __ mull (rreg_lo);
2101 __ addl (lreg_hi, rreg_hi);
2102 #endif // _LP64
2103 break;
2104 default:
2105 ShouldNotReachHere();
2106 }
2107
2108 } else if (right->is_constant()) {
2109 // cpu register - constant
2110 #ifdef _LP64
2111 jlong c = right->as_constant_ptr()->as_jlong_bits();
2112 __ movptr(r10, (intptr_t) c);
2113 switch (code) {
2114 case lir_add:
2115 __ addptr(lreg_lo, r10);
2116 break;
2117 case lir_sub:
2118 __ subptr(lreg_lo, r10);
2119 break;
2120 default:
2121 ShouldNotReachHere();
2122 }
2123 #else
2124 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2125 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2126 switch (code) {
2127 case lir_add:
2128 __ addptr(lreg_lo, c_lo);
2129 __ adcl(lreg_hi, c_hi);
2130 break;
2131 case lir_sub:
2132 __ subptr(lreg_lo, c_lo);
2133 __ sbbl(lreg_hi, c_hi);
2134 break;
2135 default:
2136 ShouldNotReachHere();
2137 }
2138 #endif // _LP64
2139
2140 } else {
2141 ShouldNotReachHere();
2142 }
2143
2144 } else if (left->is_single_xmm()) {
2145 assert(left == dest, "left and dest must be equal");
2146 XMMRegister lreg = left->as_xmm_float_reg();
2147
2148 if (right->is_single_xmm()) {
2149 XMMRegister rreg = right->as_xmm_float_reg();
2150 switch (code) {
2151 case lir_add: __ addss(lreg, rreg); break;
2152 case lir_sub: __ subss(lreg, rreg); break;
2153 case lir_mul_strictfp: // fall through
2154 case lir_mul: __ mulss(lreg, rreg); break;
2155 case lir_div_strictfp: // fall through
2156 case lir_div: __ divss(lreg, rreg); break;
2157 default: ShouldNotReachHere();
2158 }
2159 } else {
2160 Address raddr;
2161 if (right->is_single_stack()) {
2162 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2163 } else if (right->is_constant()) {
2164 // hack for now
2165 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2166 } else {
2167 ShouldNotReachHere();
2168 }
2169 switch (code) {
2170 case lir_add: __ addss(lreg, raddr); break;
2171 case lir_sub: __ subss(lreg, raddr); break;
2172 case lir_mul_strictfp: // fall through
2173 case lir_mul: __ mulss(lreg, raddr); break;
2174 case lir_div_strictfp: // fall through
2175 case lir_div: __ divss(lreg, raddr); break;
2176 default: ShouldNotReachHere();
2177 }
2178 }
2179
2180 } else if (left->is_double_xmm()) {
2181 assert(left == dest, "left and dest must be equal");
2182
2183 XMMRegister lreg = left->as_xmm_double_reg();
2184 if (right->is_double_xmm()) {
2185 XMMRegister rreg = right->as_xmm_double_reg();
2186 switch (code) {
2187 case lir_add: __ addsd(lreg, rreg); break;
2188 case lir_sub: __ subsd(lreg, rreg); break;
2189 case lir_mul_strictfp: // fall through
2190 case lir_mul: __ mulsd(lreg, rreg); break;
2191 case lir_div_strictfp: // fall through
2192 case lir_div: __ divsd(lreg, rreg); break;
2193 default: ShouldNotReachHere();
2194 }
2195 } else {
2196 Address raddr;
2197 if (right->is_double_stack()) {
2198 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2199 } else if (right->is_constant()) {
2200 // hack for now
2201 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2202 } else {
2203 ShouldNotReachHere();
2204 }
2205 switch (code) {
2206 case lir_add: __ addsd(lreg, raddr); break;
2207 case lir_sub: __ subsd(lreg, raddr); break;
2208 case lir_mul_strictfp: // fall through
2209 case lir_mul: __ mulsd(lreg, raddr); break;
2210 case lir_div_strictfp: // fall through
2211 case lir_div: __ divsd(lreg, raddr); break;
2212 default: ShouldNotReachHere();
2213 }
2214 }
2215
2216 } else if (left->is_single_fpu()) {
2217 assert(dest->is_single_fpu(), "fpu stack allocation required");
2218
2219 if (right->is_single_fpu()) {
2220 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2221
2222 } else {
2223 assert(left->fpu_regnr() == 0, "left must be on TOS");
2224 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2225
2226 Address raddr;
2227 if (right->is_single_stack()) {
2228 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2229 } else if (right->is_constant()) {
2230 address const_addr = float_constant(right->as_jfloat());
2231 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2232 // hack for now
2233 raddr = __ as_Address(InternalAddress(const_addr));
2234 } else {
2235 ShouldNotReachHere();
2236 }
2237
2238 switch (code) {
2239 case lir_add: __ fadd_s(raddr); break;
2240 case lir_sub: __ fsub_s(raddr); break;
2241 case lir_mul_strictfp: // fall through
2242 case lir_mul: __ fmul_s(raddr); break;
2243 case lir_div_strictfp: // fall through
2244 case lir_div: __ fdiv_s(raddr); break;
2245 default: ShouldNotReachHere();
2246 }
2247 }
2248
2249 } else if (left->is_double_fpu()) {
2250 assert(dest->is_double_fpu(), "fpu stack allocation required");
2251
2252 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2253 // Double values require special handling for strictfp mul/div on x86
2254 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2255 __ fmulp(left->fpu_regnrLo() + 1);
2256 }
2257
2258 if (right->is_double_fpu()) {
2259 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2260
2261 } else {
2262 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2263 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2264
2265 Address raddr;
2266 if (right->is_double_stack()) {
2267 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2268 } else if (right->is_constant()) {
2269 // hack for now
2270 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2271 } else {
2272 ShouldNotReachHere();
2273 }
2274
2275 switch (code) {
2276 case lir_add: __ fadd_d(raddr); break;
2277 case lir_sub: __ fsub_d(raddr); break;
2278 case lir_mul_strictfp: // fall through
2279 case lir_mul: __ fmul_d(raddr); break;
2280 case lir_div_strictfp: // fall through
2281 case lir_div: __ fdiv_d(raddr); break;
2282 default: ShouldNotReachHere();
2283 }
2284 }
2285
2286 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2287 // Double values require special handling for strictfp mul/div on x86
2288 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2289 __ fmulp(dest->fpu_regnrLo() + 1);
2290 }
2291
2292 } else if (left->is_single_stack() || left->is_address()) {
2293 assert(left == dest, "left and dest must be equal");
2294
2295 Address laddr;
2296 if (left->is_single_stack()) {
2297 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2298 } else if (left->is_address()) {
2299 laddr = as_Address(left->as_address_ptr());
2300 } else {
2301 ShouldNotReachHere();
2302 }
2303
2304 if (right->is_single_cpu()) {
2305 Register rreg = right->as_register();
2306 switch (code) {
2307 case lir_add: __ addl(laddr, rreg); break;
2308 case lir_sub: __ subl(laddr, rreg); break;
2309 default: ShouldNotReachHere();
2310 }
2311 } else if (right->is_constant()) {
2312 jint c = right->as_constant_ptr()->as_jint();
2313 switch (code) {
2314 case lir_add: {
2315 __ incrementl(laddr, c);
2316 break;
2317 }
2318 case lir_sub: {
2319 __ decrementl(laddr, c);
2320 break;
2321 }
2322 default: ShouldNotReachHere();
2323 }
2324 } else {
2325 ShouldNotReachHere();
2326 }
2327
2328 } else {
2329 ShouldNotReachHere();
2330 }
2331 }
2332
2333 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2334 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2335 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2336 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2337
2338 bool left_is_tos = (left_index == 0);
2339 bool dest_is_tos = (dest_index == 0);
2340 int non_tos_index = (left_is_tos ? right_index : left_index);
2341
2342 switch (code) {
2343 case lir_add:
2344 if (pop_fpu_stack) __ faddp(non_tos_index);
2345 else if (dest_is_tos) __ fadd (non_tos_index);
2346 else __ fadda(non_tos_index);
2347 break;
2348
2349 case lir_sub:
2350 if (left_is_tos) {
2351 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2352 else if (dest_is_tos) __ fsub (non_tos_index);
2353 else __ fsubra(non_tos_index);
2354 } else {
2355 if (pop_fpu_stack) __ fsubp (non_tos_index);
2356 else if (dest_is_tos) __ fsubr (non_tos_index);
2357 else __ fsuba (non_tos_index);
2358 }
2359 break;
2360
2361 case lir_mul_strictfp: // fall through
2362 case lir_mul:
2363 if (pop_fpu_stack) __ fmulp(non_tos_index);
2364 else if (dest_is_tos) __ fmul (non_tos_index);
2365 else __ fmula(non_tos_index);
2366 break;
2367
2368 case lir_div_strictfp: // fall through
2369 case lir_div:
2370 if (left_is_tos) {
2371 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2372 else if (dest_is_tos) __ fdiv (non_tos_index);
2373 else __ fdivra(non_tos_index);
2374 } else {
2375 if (pop_fpu_stack) __ fdivp (non_tos_index);
2376 else if (dest_is_tos) __ fdivr (non_tos_index);
2377 else __ fdiva (non_tos_index);
2378 }
2379 break;
2380
2381 case lir_rem:
2382 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2383 __ fremr(noreg);
2384 break;
2385
2386 default:
2387 ShouldNotReachHere();
2388 }
2389 }
2390
2391
2392 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2393 if (value->is_double_xmm()) {
2394 switch(code) {
2395 case lir_abs :
2396 {
2397 #ifdef _LP64
2398 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2399 assert(tmp->is_valid(), "need temporary");
2400 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2401 } else
2402 #endif
2403 {
2404 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2405 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2406 }
2407 assert(!tmp->is_valid(), "do not need temporary");
2408 __ andpd(dest->as_xmm_double_reg(),
2409 ExternalAddress((address)double_signmask_pool));
2410 }
2411 }
2412 break;
2413
2414 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2415 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2416 default : ShouldNotReachHere();
2417 }
2418
2419 } else if (value->is_double_fpu()) {
2420 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2421 switch(code) {
2422 case lir_abs : __ fabs() ; break;
2423 case lir_sqrt : __ fsqrt(); break;
2424 default : ShouldNotReachHere();
2425 }
2426 } else {
2427 Unimplemented();
2428 }
2429 }
2430
2431 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2432 // assert(left->destroys_register(), "check");
2433 if (left->is_single_cpu()) {
2434 Register reg = left->as_register();
2435 if (right->is_constant()) {
2436 int val = right->as_constant_ptr()->as_jint();
2437 switch (code) {
2438 case lir_logic_and: __ andl (reg, val); break;
2439 case lir_logic_or: __ orl (reg, val); break;
2440 case lir_logic_xor: __ xorl (reg, val); break;
2441 default: ShouldNotReachHere();
2442 }
2443 } else if (right->is_stack()) {
2444 // added support for stack operands
2445 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2446 switch (code) {
2447 case lir_logic_and: __ andl (reg, raddr); break;
2448 case lir_logic_or: __ orl (reg, raddr); break;
2449 case lir_logic_xor: __ xorl (reg, raddr); break;
2450 default: ShouldNotReachHere();
2451 }
2452 } else {
2453 Register rright = right->as_register();
2454 switch (code) {
2455 case lir_logic_and: __ andptr (reg, rright); break;
2456 case lir_logic_or : __ orptr (reg, rright); break;
2457 case lir_logic_xor: __ xorptr (reg, rright); break;
2458 default: ShouldNotReachHere();
2459 }
2460 }
2461 move_regs(reg, dst->as_register());
2462 } else {
2463 Register l_lo = left->as_register_lo();
2464 Register l_hi = left->as_register_hi();
2465 if (right->is_constant()) {
2466 #ifdef _LP64
2467 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2468 switch (code) {
2469 case lir_logic_and:
2470 __ andq(l_lo, rscratch1);
2471 break;
2472 case lir_logic_or:
2473 __ orq(l_lo, rscratch1);
2474 break;
2475 case lir_logic_xor:
2476 __ xorq(l_lo, rscratch1);
2477 break;
2478 default: ShouldNotReachHere();
2479 }
2480 #else
2481 int r_lo = right->as_constant_ptr()->as_jint_lo();
2482 int r_hi = right->as_constant_ptr()->as_jint_hi();
2483 switch (code) {
2484 case lir_logic_and:
2485 __ andl(l_lo, r_lo);
2486 __ andl(l_hi, r_hi);
2487 break;
2488 case lir_logic_or:
2489 __ orl(l_lo, r_lo);
2490 __ orl(l_hi, r_hi);
2491 break;
2492 case lir_logic_xor:
2493 __ xorl(l_lo, r_lo);
2494 __ xorl(l_hi, r_hi);
2495 break;
2496 default: ShouldNotReachHere();
2497 }
2498 #endif // _LP64
2499 } else {
2500 #ifdef _LP64
2501 Register r_lo;
2502 if (right->type() == T_OBJECT || right->type() == T_ARRAY || right->type() == T_VALUETYPE) {
2503 r_lo = right->as_register();
2504 } else {
2505 r_lo = right->as_register_lo();
2506 }
2507 #else
2508 Register r_lo = right->as_register_lo();
2509 Register r_hi = right->as_register_hi();
2510 assert(l_lo != r_hi, "overwriting registers");
2511 #endif
2512 switch (code) {
2513 case lir_logic_and:
2514 __ andptr(l_lo, r_lo);
2515 NOT_LP64(__ andptr(l_hi, r_hi);)
2516 break;
2517 case lir_logic_or:
2518 __ orptr(l_lo, r_lo);
2519 NOT_LP64(__ orptr(l_hi, r_hi);)
2520 break;
2521 case lir_logic_xor:
2522 __ xorptr(l_lo, r_lo);
2523 NOT_LP64(__ xorptr(l_hi, r_hi);)
2524 break;
2525 default: ShouldNotReachHere();
2526 }
2527 }
2528
2529 Register dst_lo = dst->as_register_lo();
2530 Register dst_hi = dst->as_register_hi();
2531
2532 #ifdef _LP64
2533 move_regs(l_lo, dst_lo);
2534 #else
2535 if (dst_lo == l_hi) {
2536 assert(dst_hi != l_lo, "overwriting registers");
2537 move_regs(l_hi, dst_hi);
2538 move_regs(l_lo, dst_lo);
2539 } else {
2540 assert(dst_lo != l_hi, "overwriting registers");
2541 move_regs(l_lo, dst_lo);
2542 move_regs(l_hi, dst_hi);
2543 }
2544 #endif // _LP64
2545 }
2546 }
2547
2548
2549 // we assume that rax, and rdx can be overwritten
2550 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2551
2552 assert(left->is_single_cpu(), "left must be register");
2553 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2554 assert(result->is_single_cpu(), "result must be register");
2555
2556 // assert(left->destroys_register(), "check");
2557 // assert(right->destroys_register(), "check");
2558
2559 Register lreg = left->as_register();
2560 Register dreg = result->as_register();
2561
2562 if (right->is_constant()) {
2563 jint divisor = right->as_constant_ptr()->as_jint();
2564 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2565 if (code == lir_idiv) {
2566 assert(lreg == rax, "must be rax,");
2567 assert(temp->as_register() == rdx, "tmp register must be rdx");
2568 __ cdql(); // sign extend into rdx:rax
2569 if (divisor == 2) {
2570 __ subl(lreg, rdx);
2571 } else {
2572 __ andl(rdx, divisor - 1);
2573 __ addl(lreg, rdx);
2574 }
2575 __ sarl(lreg, log2_jint(divisor));
2576 move_regs(lreg, dreg);
2577 } else if (code == lir_irem) {
2578 Label done;
2579 __ mov(dreg, lreg);
2580 __ andl(dreg, 0x80000000 | (divisor - 1));
2581 __ jcc(Assembler::positive, done);
2582 __ decrement(dreg);
2583 __ orl(dreg, ~(divisor - 1));
2584 __ increment(dreg);
2585 __ bind(done);
2586 } else {
2587 ShouldNotReachHere();
2588 }
2589 } else {
2590 Register rreg = right->as_register();
2591 assert(lreg == rax, "left register must be rax,");
2592 assert(rreg != rdx, "right register must not be rdx");
2593 assert(temp->as_register() == rdx, "tmp register must be rdx");
2594
2595 move_regs(lreg, rax);
2596
2597 int idivl_offset = __ corrected_idivl(rreg);
2598 if (ImplicitDiv0Checks) {
2599 add_debug_info_for_div0(idivl_offset, info);
2600 }
2601 if (code == lir_irem) {
2602 move_regs(rdx, dreg); // result is in rdx
2603 } else {
2604 move_regs(rax, dreg);
2605 }
2606 }
2607 }
2608
2609
2610 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2611 if (opr1->is_single_cpu()) {
2612 Register reg1 = opr1->as_register();
2613 if (opr2->is_single_cpu()) {
2614 // cpu register - cpu register
2615 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2616 __ cmpoop(reg1, opr2->as_register());
2617 } else {
2618 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
2619 __ cmpl(reg1, opr2->as_register());
2620 }
2621 } else if (opr2->is_stack()) {
2622 // cpu register - stack
2623 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2624 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2625 } else {
2626 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2627 }
2628 } else if (opr2->is_constant()) {
2629 // cpu register - constant
2630 LIR_Const* c = opr2->as_constant_ptr();
2631 if (c->type() == T_INT) {
2632 __ cmpl(reg1, c->as_jint());
2633 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2634 // In 64bit oops are single register
2635 jobject o = c->as_jobject();
2636 if (o == NULL) {
2637 __ cmpptr(reg1, (int32_t)NULL_WORD);
2638 } else {
2639 __ cmpoop(reg1, o);
2640 }
2641 } else {
2642 fatal("unexpected type: %s", basictype_to_str(c->type()));
2643 }
2644 // cpu register - address
2645 } else if (opr2->is_address()) {
2646 if (op->info() != NULL) {
2647 add_debug_info_for_null_check_here(op->info());
2648 }
2649 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2650 } else {
2651 ShouldNotReachHere();
2652 }
2653
2654 } else if(opr1->is_double_cpu()) {
2655 Register xlo = opr1->as_register_lo();
2656 Register xhi = opr1->as_register_hi();
2657 if (opr2->is_double_cpu()) {
2658 #ifdef _LP64
2659 __ cmpptr(xlo, opr2->as_register_lo());
2660 #else
2661 // cpu register - cpu register
2662 Register ylo = opr2->as_register_lo();
2663 Register yhi = opr2->as_register_hi();
2664 __ subl(xlo, ylo);
2665 __ sbbl(xhi, yhi);
2666 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2667 __ orl(xhi, xlo);
2668 }
2669 #endif // _LP64
2670 } else if (opr2->is_constant()) {
2671 // cpu register - constant 0
2672 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2673 #ifdef _LP64
2674 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2675 #else
2676 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2677 __ orl(xhi, xlo);
2678 #endif // _LP64
2679 } else {
2680 ShouldNotReachHere();
2681 }
2682
2683 } else if (opr1->is_single_xmm()) {
2684 XMMRegister reg1 = opr1->as_xmm_float_reg();
2685 if (opr2->is_single_xmm()) {
2686 // xmm register - xmm register
2687 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2688 } else if (opr2->is_stack()) {
2689 // xmm register - stack
2690 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2691 } else if (opr2->is_constant()) {
2692 // xmm register - constant
2693 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2694 } else if (opr2->is_address()) {
2695 // xmm register - address
2696 if (op->info() != NULL) {
2697 add_debug_info_for_null_check_here(op->info());
2698 }
2699 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2700 } else {
2701 ShouldNotReachHere();
2702 }
2703
2704 } else if (opr1->is_double_xmm()) {
2705 XMMRegister reg1 = opr1->as_xmm_double_reg();
2706 if (opr2->is_double_xmm()) {
2707 // xmm register - xmm register
2708 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2709 } else if (opr2->is_stack()) {
2710 // xmm register - stack
2711 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2712 } else if (opr2->is_constant()) {
2713 // xmm register - constant
2714 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2715 } else if (opr2->is_address()) {
2716 // xmm register - address
2717 if (op->info() != NULL) {
2718 add_debug_info_for_null_check_here(op->info());
2719 }
2720 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2721 } else {
2722 ShouldNotReachHere();
2723 }
2724
2725 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2726 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2727 assert(opr2->is_fpu_register(), "both must be registers");
2728 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2729
2730 } else if (opr1->is_address() && opr2->is_constant()) {
2731 LIR_Const* c = opr2->as_constant_ptr();
2732 #ifdef _LP64
2733 if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2734 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2735 __ movoop(rscratch1, c->as_jobject());
2736 }
2737 #endif // LP64
2738 if (op->info() != NULL) {
2739 add_debug_info_for_null_check_here(op->info());
2740 }
2741 // special case: address - constant
2742 LIR_Address* addr = opr1->as_address_ptr();
2743 if (c->type() == T_INT) {
2744 __ cmpl(as_Address(addr), c->as_jint());
2745 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2746 #ifdef _LP64
2747 // %%% Make this explode if addr isn't reachable until we figure out a
2748 // better strategy by giving noreg as the temp for as_Address
2749 __ cmpoop(rscratch1, as_Address(addr, noreg));
2750 #else
2751 __ cmpoop(as_Address(addr), c->as_jobject());
2752 #endif // _LP64
2753 } else {
2754 ShouldNotReachHere();
2755 }
2756
2757 } else {
2758 ShouldNotReachHere();
2759 }
2760 }
2761
2762 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2763 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2764 if (left->is_single_xmm()) {
2765 assert(right->is_single_xmm(), "must match");
2766 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2767 } else if (left->is_double_xmm()) {
2768 assert(right->is_double_xmm(), "must match");
2769 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2770
2771 } else {
2772 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2773 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2774
2775 assert(left->fpu() == 0, "left must be on TOS");
2776 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2777 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2778 }
2779 } else {
2780 assert(code == lir_cmp_l2i, "check");
2781 #ifdef _LP64
2782 Label done;
2783 Register dest = dst->as_register();
2784 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2785 __ movl(dest, -1);
2786 __ jccb(Assembler::less, done);
2787 __ set_byte_if_not_zero(dest);
2788 __ movzbl(dest, dest);
2789 __ bind(done);
2790 #else
2791 __ lcmp2int(left->as_register_hi(),
2792 left->as_register_lo(),
2793 right->as_register_hi(),
2794 right->as_register_lo());
2795 move_regs(left->as_register_hi(), dst->as_register());
2796 #endif // _LP64
2797 }
2798 }
2799
2800
2801 void LIR_Assembler::align_call(LIR_Code code) {
2802 // make sure that the displacement word of the call ends up word aligned
2803 int offset = __ offset();
2804 switch (code) {
2805 case lir_static_call:
2806 case lir_optvirtual_call:
2807 case lir_dynamic_call:
2808 offset += NativeCall::displacement_offset;
2809 break;
2810 case lir_icvirtual_call:
2811 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2812 break;
2813 case lir_virtual_call: // currently, sparc-specific for niagara
2814 default: ShouldNotReachHere();
2815 }
2816 __ align(BytesPerWord, offset);
2817 }
2818
2819
2820 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2821 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2822 "must be aligned");
2823 __ call(AddressLiteral(op->addr(), rtype));
2824 add_call_info(code_offset(), op->info());
2825 }
2826
2827
2828 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2829 __ ic_call(op->addr());
2830 add_call_info(code_offset(), op->info());
2831 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2832 "must be aligned");
2833 }
2834
2835
2836 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2837 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2838 ShouldNotReachHere();
2839 }
2840
2841
2842 void LIR_Assembler::emit_static_call_stub() {
2843 address call_pc = __ pc();
2844 address stub = __ start_a_stub(call_stub_size());
2845 if (stub == NULL) {
2846 bailout("static call stub overflow");
2847 return;
2848 }
2849
2850 int start = __ offset();
2851
2852 // make sure that the displacement word of the call ends up word aligned
2853 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2854 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2855 __ mov_metadata(rbx, (Metadata*)NULL);
2856 // must be set to -1 at code generation time
2857 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2858 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2859 __ jump(RuntimeAddress(__ pc()));
2860
2861 if (UseAOT) {
2862 // Trampoline to aot code
2863 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2864 #ifdef _LP64
2865 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2866 #else
2867 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2868 #endif
2869 __ jmp(rax);
2870 }
2871 assert(__ offset() - start <= call_stub_size(), "stub too big");
2872 __ end_a_stub();
2873 }
2874
2875
2876 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2877 assert(exceptionOop->as_register() == rax, "must match");
2878 assert(exceptionPC->as_register() == rdx, "must match");
2879
2880 // exception object is not added to oop map by LinearScan
2881 // (LinearScan assumes that no oops are in fixed registers)
2882 info->add_register_oop(exceptionOop);
2883 Runtime1::StubID unwind_id;
2884
2885 // get current pc information
2886 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2887 int pc_for_athrow_offset = __ offset();
2888 InternalAddress pc_for_athrow(__ pc());
2889 __ lea(exceptionPC->as_register(), pc_for_athrow);
2890 add_call_info(pc_for_athrow_offset, info); // for exception handler
2891
2892 __ verify_not_null_oop(rax);
2893 // search an exception handler (rax: exception oop, rdx: throwing pc)
2894 if (compilation()->has_fpu_code()) {
2895 unwind_id = Runtime1::handle_exception_id;
2896 } else {
2897 unwind_id = Runtime1::handle_exception_nofpu_id;
2898 }
2899 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2900
2901 // enough room for two byte trap
2902 __ nop();
2903 }
2904
2905
2906 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2907 assert(exceptionOop->as_register() == rax, "must match");
2908
2909 __ jmp(_unwind_handler_entry);
2910 }
2911
2912
2913 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2914
2915 // optimized version for linear scan:
2916 // * count must be already in ECX (guaranteed by LinearScan)
2917 // * left and dest must be equal
2918 // * tmp must be unused
2919 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2920 assert(left == dest, "left and dest must be equal");
2921 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2922
2923 if (left->is_single_cpu()) {
2924 Register value = left->as_register();
2925 assert(value != SHIFT_count, "left cannot be ECX");
2926
2927 switch (code) {
2928 case lir_shl: __ shll(value); break;
2929 case lir_shr: __ sarl(value); break;
2930 case lir_ushr: __ shrl(value); break;
2931 default: ShouldNotReachHere();
2932 }
2933 } else if (left->is_double_cpu()) {
2934 Register lo = left->as_register_lo();
2935 Register hi = left->as_register_hi();
2936 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2937 #ifdef _LP64
2938 switch (code) {
2939 case lir_shl: __ shlptr(lo); break;
2940 case lir_shr: __ sarptr(lo); break;
2941 case lir_ushr: __ shrptr(lo); break;
2942 default: ShouldNotReachHere();
2943 }
2944 #else
2945
2946 switch (code) {
2947 case lir_shl: __ lshl(hi, lo); break;
2948 case lir_shr: __ lshr(hi, lo, true); break;
2949 case lir_ushr: __ lshr(hi, lo, false); break;
2950 default: ShouldNotReachHere();
2951 }
2952 #endif // LP64
2953 } else {
2954 ShouldNotReachHere();
2955 }
2956 }
2957
2958
2959 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2960 if (dest->is_single_cpu()) {
2961 // first move left into dest so that left is not destroyed by the shift
2962 Register value = dest->as_register();
2963 count = count & 0x1F; // Java spec
2964
2965 move_regs(left->as_register(), value);
2966 switch (code) {
2967 case lir_shl: __ shll(value, count); break;
2968 case lir_shr: __ sarl(value, count); break;
2969 case lir_ushr: __ shrl(value, count); break;
2970 default: ShouldNotReachHere();
2971 }
2972 } else if (dest->is_double_cpu()) {
2973 #ifndef _LP64
2974 Unimplemented();
2975 #else
2976 // first move left into dest so that left is not destroyed by the shift
2977 Register value = dest->as_register_lo();
2978 count = count & 0x1F; // Java spec
2979
2980 move_regs(left->as_register_lo(), value);
2981 switch (code) {
2982 case lir_shl: __ shlptr(value, count); break;
2983 case lir_shr: __ sarptr(value, count); break;
2984 case lir_ushr: __ shrptr(value, count); break;
2985 default: ShouldNotReachHere();
2986 }
2987 #endif // _LP64
2988 } else {
2989 ShouldNotReachHere();
2990 }
2991 }
2992
2993
2994 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2995 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2996 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2997 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2998 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2999 }
3000
3001
3002 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3003 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3004 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3005 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3006 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3007 }
3008
3009
3010 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3011 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3012 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3013 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3014 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3015 }
3016
3017
3018 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3019 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3020 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3021 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3022 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3023 }
3024
3025
3026 // This code replaces a call to arraycopy; no exception may
3027 // be thrown in this code, they must be thrown in the System.arraycopy
3028 // activation frame; we could save some checks if this would not be the case
3029 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3030 ciArrayKlass* default_type = op->expected_type();
3031 Register src = op->src()->as_register();
3032 Register dst = op->dst()->as_register();
3033 Register src_pos = op->src_pos()->as_register();
3034 Register dst_pos = op->dst_pos()->as_register();
3035 Register length = op->length()->as_register();
3036 Register tmp = op->tmp()->as_register();
3037
3038 __ resolve(ACCESS_READ, src);
3039 __ resolve(ACCESS_WRITE, dst);
3040
3041 CodeStub* stub = op->stub();
3042 int flags = op->flags();
3043 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3044 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3045
3046 // if we don't know anything, just go through the generic arraycopy
3047 if (default_type == NULL) {
3048 // save outgoing arguments on stack in case call to System.arraycopy is needed
3049 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3050 // for interpreter calling conventions. Now we have to do it in new style conventions.
3051 // For the moment until C1 gets the new register allocator I just force all the
3052 // args to the right place (except the register args) and then on the back side
3053 // reload the register args properly if we go slow path. Yuck
3054
3055 // These are proper for the calling convention
3056 store_parameter(length, 2);
3057 store_parameter(dst_pos, 1);
3058 store_parameter(dst, 0);
3059
3060 // these are just temporary placements until we need to reload
3061 store_parameter(src_pos, 3);
3062 store_parameter(src, 4);
3063 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3064
3065 address copyfunc_addr = StubRoutines::generic_arraycopy();
3066 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3067
3068 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3069 #ifdef _LP64
3070 // The arguments are in java calling convention so we can trivially shift them to C
3071 // convention
3072 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3073 __ mov(c_rarg0, j_rarg0);
3074 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3075 __ mov(c_rarg1, j_rarg1);
3076 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3077 __ mov(c_rarg2, j_rarg2);
3078 assert_different_registers(c_rarg3, j_rarg4);
3079 __ mov(c_rarg3, j_rarg3);
3080 #ifdef _WIN64
3081 // Allocate abi space for args but be sure to keep stack aligned
3082 __ subptr(rsp, 6*wordSize);
3083 store_parameter(j_rarg4, 4);
3084 #ifndef PRODUCT
3085 if (PrintC1Statistics) {
3086 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3087 }
3088 #endif
3089 __ call(RuntimeAddress(copyfunc_addr));
3090 __ addptr(rsp, 6*wordSize);
3091 #else
3092 __ mov(c_rarg4, j_rarg4);
3093 #ifndef PRODUCT
3094 if (PrintC1Statistics) {
3095 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3096 }
3097 #endif
3098 __ call(RuntimeAddress(copyfunc_addr));
3099 #endif // _WIN64
3100 #else
3101 __ push(length);
3102 __ push(dst_pos);
3103 __ push(dst);
3104 __ push(src_pos);
3105 __ push(src);
3106
3107 #ifndef PRODUCT
3108 if (PrintC1Statistics) {
3109 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3110 }
3111 #endif
3112 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3113
3114 #endif // _LP64
3115
3116 __ cmpl(rax, 0);
3117 __ jcc(Assembler::equal, *stub->continuation());
3118
3119 __ mov(tmp, rax);
3120 __ xorl(tmp, -1);
3121
3122 // Reload values from the stack so they are where the stub
3123 // expects them.
3124 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3125 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3126 __ movptr (length, Address(rsp, 2*BytesPerWord));
3127 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3128 __ movptr (src, Address(rsp, 4*BytesPerWord));
3129
3130 __ subl(length, tmp);
3131 __ addl(src_pos, tmp);
3132 __ addl(dst_pos, tmp);
3133 __ jmp(*stub->entry());
3134
3135 __ bind(*stub->continuation());
3136 return;
3137 }
3138
3139 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3140
3141 int elem_size = type2aelembytes(basic_type);
3142 Address::ScaleFactor scale;
3143
3144 switch (elem_size) {
3145 case 1 :
3146 scale = Address::times_1;
3147 break;
3148 case 2 :
3149 scale = Address::times_2;
3150 break;
3151 case 4 :
3152 scale = Address::times_4;
3153 break;
3154 case 8 :
3155 scale = Address::times_8;
3156 break;
3157 default:
3158 scale = Address::no_scale;
3159 ShouldNotReachHere();
3160 }
3161
3162 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3163 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3164 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3165 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3166
3167 // length and pos's are all sign extended at this point on 64bit
3168
3169 // test for NULL
3170 if (flags & LIR_OpArrayCopy::src_null_check) {
3171 __ testptr(src, src);
3172 __ jcc(Assembler::zero, *stub->entry());
3173 }
3174 if (flags & LIR_OpArrayCopy::dst_null_check) {
3175 __ testptr(dst, dst);
3176 __ jcc(Assembler::zero, *stub->entry());
3177 }
3178
3179 // If the compiler was not able to prove that exact type of the source or the destination
3180 // of the arraycopy is an array type, check at runtime if the source or the destination is
3181 // an instance type.
3182 if (flags & LIR_OpArrayCopy::type_check) {
3183 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3184 __ load_klass(tmp, dst);
3185 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3186 __ jcc(Assembler::greaterEqual, *stub->entry());
3187 }
3188
3189 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3190 __ load_klass(tmp, src);
3191 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3192 __ jcc(Assembler::greaterEqual, *stub->entry());
3193 }
3194 }
3195
3196 // check if negative
3197 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3198 __ testl(src_pos, src_pos);
3199 __ jcc(Assembler::less, *stub->entry());
3200 }
3201 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3202 __ testl(dst_pos, dst_pos);
3203 __ jcc(Assembler::less, *stub->entry());
3204 }
3205
3206 if (flags & LIR_OpArrayCopy::src_range_check) {
3207 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3208 __ cmpl(tmp, src_length_addr);
3209 __ jcc(Assembler::above, *stub->entry());
3210 }
3211 if (flags & LIR_OpArrayCopy::dst_range_check) {
3212 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3213 __ cmpl(tmp, dst_length_addr);
3214 __ jcc(Assembler::above, *stub->entry());
3215 }
3216
3217 if (flags & LIR_OpArrayCopy::length_positive_check) {
3218 __ testl(length, length);
3219 __ jcc(Assembler::less, *stub->entry());
3220 }
3221
3222 #ifdef _LP64
3223 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3224 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3225 #endif
3226
3227 if (flags & LIR_OpArrayCopy::type_check) {
3228 // We don't know the array types are compatible
3229 if (basic_type != T_OBJECT) {
3230 // Simple test for basic type arrays
3231 if (UseCompressedClassPointers) {
3232 __ movl(tmp, src_klass_addr);
3233 __ cmpl(tmp, dst_klass_addr);
3234 } else {
3235 __ movptr(tmp, src_klass_addr);
3236 __ cmpptr(tmp, dst_klass_addr);
3237 }
3238 __ jcc(Assembler::notEqual, *stub->entry());
3239 } else {
3240 // For object arrays, if src is a sub class of dst then we can
3241 // safely do the copy.
3242 Label cont, slow;
3243
3244 __ push(src);
3245 __ push(dst);
3246
3247 __ load_klass(src, src);
3248 __ load_klass(dst, dst);
3249
3250 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3251
3252 __ push(src);
3253 __ push(dst);
3254 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3255 __ pop(dst);
3256 __ pop(src);
3257
3258 __ cmpl(src, 0);
3259 __ jcc(Assembler::notEqual, cont);
3260
3261 __ bind(slow);
3262 __ pop(dst);
3263 __ pop(src);
3264
3265 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3266 if (copyfunc_addr != NULL) { // use stub if available
3267 // src is not a sub class of dst so we have to do a
3268 // per-element check.
3269
3270 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3271 if ((flags & mask) != mask) {
3272 // Check that at least both of them object arrays.
3273 assert(flags & mask, "one of the two should be known to be an object array");
3274
3275 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3276 __ load_klass(tmp, src);
3277 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3278 __ load_klass(tmp, dst);
3279 }
3280 int lh_offset = in_bytes(Klass::layout_helper_offset());
3281 Address klass_lh_addr(tmp, lh_offset);
3282 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3283 __ cmpl(klass_lh_addr, objArray_lh);
3284 __ jcc(Assembler::notEqual, *stub->entry());
3285 }
3286
3287 // Spill because stubs can use any register they like and it's
3288 // easier to restore just those that we care about.
3289 store_parameter(dst, 0);
3290 store_parameter(dst_pos, 1);
3291 store_parameter(length, 2);
3292 store_parameter(src_pos, 3);
3293 store_parameter(src, 4);
3294
3295 #ifndef _LP64
3296 __ movptr(tmp, dst_klass_addr);
3297 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3298 __ push(tmp);
3299 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3300 __ push(tmp);
3301 __ push(length);
3302 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3303 __ push(tmp);
3304 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3305 __ push(tmp);
3306
3307 __ call_VM_leaf(copyfunc_addr, 5);
3308 #else
3309 __ movl2ptr(length, length); //higher 32bits must be null
3310
3311 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3312 assert_different_registers(c_rarg0, dst, dst_pos, length);
3313 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3314 assert_different_registers(c_rarg1, dst, length);
3315
3316 __ mov(c_rarg2, length);
3317 assert_different_registers(c_rarg2, dst);
3318
3319 #ifdef _WIN64
3320 // Allocate abi space for args but be sure to keep stack aligned
3321 __ subptr(rsp, 6*wordSize);
3322 __ load_klass(c_rarg3, dst);
3323 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3324 store_parameter(c_rarg3, 4);
3325 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3326 __ call(RuntimeAddress(copyfunc_addr));
3327 __ addptr(rsp, 6*wordSize);
3328 #else
3329 __ load_klass(c_rarg4, dst);
3330 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3331 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3332 __ call(RuntimeAddress(copyfunc_addr));
3333 #endif
3334
3335 #endif
3336
3337 #ifndef PRODUCT
3338 if (PrintC1Statistics) {
3339 Label failed;
3340 __ testl(rax, rax);
3341 __ jcc(Assembler::notZero, failed);
3342 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3343 __ bind(failed);
3344 }
3345 #endif
3346
3347 __ testl(rax, rax);
3348 __ jcc(Assembler::zero, *stub->continuation());
3349
3350 #ifndef PRODUCT
3351 if (PrintC1Statistics) {
3352 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3353 }
3354 #endif
3355
3356 __ mov(tmp, rax);
3357
3358 __ xorl(tmp, -1);
3359
3360 // Restore previously spilled arguments
3361 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3362 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3363 __ movptr (length, Address(rsp, 2*BytesPerWord));
3364 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3365 __ movptr (src, Address(rsp, 4*BytesPerWord));
3366
3367
3368 __ subl(length, tmp);
3369 __ addl(src_pos, tmp);
3370 __ addl(dst_pos, tmp);
3371 }
3372
3373 __ jmp(*stub->entry());
3374
3375 __ bind(cont);
3376 __ pop(dst);
3377 __ pop(src);
3378 }
3379 }
3380
3381 #ifdef ASSERT
3382 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3383 // Sanity check the known type with the incoming class. For the
3384 // primitive case the types must match exactly with src.klass and
3385 // dst.klass each exactly matching the default type. For the
3386 // object array case, if no type check is needed then either the
3387 // dst type is exactly the expected type and the src type is a
3388 // subtype which we can't check or src is the same array as dst
3389 // but not necessarily exactly of type default_type.
3390 Label known_ok, halt;
3391 __ mov_metadata(tmp, default_type->constant_encoding());
3392 #ifdef _LP64
3393 if (UseCompressedClassPointers) {
3394 __ encode_klass_not_null(tmp);
3395 }
3396 #endif
3397
3398 if (basic_type != T_OBJECT) {
3399
3400 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3401 else __ cmpptr(tmp, dst_klass_addr);
3402 __ jcc(Assembler::notEqual, halt);
3403 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3404 else __ cmpptr(tmp, src_klass_addr);
3405 __ jcc(Assembler::equal, known_ok);
3406 } else {
3407 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3408 else __ cmpptr(tmp, dst_klass_addr);
3409 __ jcc(Assembler::equal, known_ok);
3410 __ cmpptr(src, dst);
3411 __ jcc(Assembler::equal, known_ok);
3412 }
3413 __ bind(halt);
3414 __ stop("incorrect type information in arraycopy");
3415 __ bind(known_ok);
3416 }
3417 #endif
3418
3419 #ifndef PRODUCT
3420 if (PrintC1Statistics) {
3421 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3422 }
3423 #endif
3424
3425 #ifdef _LP64
3426 assert_different_registers(c_rarg0, dst, dst_pos, length);
3427 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3428 assert_different_registers(c_rarg1, length);
3429 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3430 __ mov(c_rarg2, length);
3431
3432 #else
3433 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3434 store_parameter(tmp, 0);
3435 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3436 store_parameter(tmp, 1);
3437 store_parameter(length, 2);
3438 #endif // _LP64
3439
3440 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3441 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3442 const char *name;
3443 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3444 __ call_VM_leaf(entry, 0);
3445
3446 __ bind(*stub->continuation());
3447 }
3448
3449 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3450 assert(op->crc()->is_single_cpu(), "crc must be register");
3451 assert(op->val()->is_single_cpu(), "byte value must be register");
3452 assert(op->result_opr()->is_single_cpu(), "result must be register");
3453 Register crc = op->crc()->as_register();
3454 Register val = op->val()->as_register();
3455 Register res = op->result_opr()->as_register();
3456
3457 assert_different_registers(val, crc, res);
3458
3459 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3460 __ notl(crc); // ~crc
3461 __ update_byte_crc32(crc, val, res);
3462 __ notl(crc); // ~crc
3463 __ mov(res, crc);
3464 }
3465
3466 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3467 Register obj = op->obj_opr()->as_register(); // may not be an oop
3468 Register hdr = op->hdr_opr()->as_register();
3469 Register lock = op->lock_opr()->as_register();
3470 if (!UseFastLocking) {
3471 __ jmp(*op->stub()->entry());
3472 } else if (op->code() == lir_lock) {
3473 Register scratch = noreg;
3474 if (UseBiasedLocking) {
3475 scratch = op->scratch_opr()->as_register();
3476 }
3477 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3478 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3479 // add debug info for NullPointerException only if one is possible
3480 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3481 if (op->info() != NULL) {
3482 add_debug_info_for_null_check(null_check_offset, op->info());
3483 }
3484 // done
3485 } else if (op->code() == lir_unlock) {
3486 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3487 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3488 } else {
3489 Unimplemented();
3490 }
3491 __ bind(*op->stub()->continuation());
3492 }
3493
3494
3495 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3496 ciMethod* method = op->profiled_method();
3497 int bci = op->profiled_bci();
3498 ciMethod* callee = op->profiled_callee();
3499
3500 // Update counter for all call types
3501 ciMethodData* md = method->method_data_or_null();
3502 assert(md != NULL, "Sanity");
3503 ciProfileData* data = md->bci_to_data(bci);
3504 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3505 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3506 Register mdo = op->mdo()->as_register();
3507 __ mov_metadata(mdo, md->constant_encoding());
3508 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3509 // Perform additional virtual call profiling for invokevirtual and
3510 // invokeinterface bytecodes
3511 if (op->should_profile_receiver_type()) {
3512 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3513 Register recv = op->recv()->as_register();
3514 assert_different_registers(mdo, recv);
3515 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3516 ciKlass* known_klass = op->known_holder();
3517 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3518 // We know the type that will be seen at this call site; we can
3519 // statically update the MethodData* rather than needing to do
3520 // dynamic tests on the receiver type
3521
3522 // NOTE: we should probably put a lock around this search to
3523 // avoid collisions by concurrent compilations
3524 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3525 uint i;
3526 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3527 ciKlass* receiver = vc_data->receiver(i);
3528 if (known_klass->equals(receiver)) {
3529 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3530 __ addptr(data_addr, DataLayout::counter_increment);
3531 return;
3532 }
3533 }
3534
3535 // Receiver type not found in profile data; select an empty slot
3536
3537 // Note that this is less efficient than it should be because it
3538 // always does a write to the receiver part of the
3539 // VirtualCallData rather than just the first time
3540 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3541 ciKlass* receiver = vc_data->receiver(i);
3542 if (receiver == NULL) {
3543 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3544 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3545 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3546 __ addptr(data_addr, DataLayout::counter_increment);
3547 return;
3548 }
3549 }
3550 } else {
3551 __ load_klass(recv, recv);
3552 Label update_done;
3553 type_profile_helper(mdo, md, data, recv, &update_done);
3554 // Receiver did not match any saved receiver and there is no empty row for it.
3555 // Increment total counter to indicate polymorphic case.
3556 __ addptr(counter_addr, DataLayout::counter_increment);
3557
3558 __ bind(update_done);
3559 }
3560 } else {
3561 // Static call
3562 __ addptr(counter_addr, DataLayout::counter_increment);
3563 }
3564 }
3565
3566 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3567 Register obj = op->obj()->as_register();
3568 Register tmp = op->tmp()->as_pointer_register();
3569 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3570 ciKlass* exact_klass = op->exact_klass();
3571 intptr_t current_klass = op->current_klass();
3572 bool not_null = op->not_null();
3573 bool no_conflict = op->no_conflict();
3574
3575 Label update, next, none;
3576
3577 bool do_null = !not_null;
3578 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3579 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3580
3581 assert(do_null || do_update, "why are we here?");
3582 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3583
3584 __ verify_oop(obj);
3585
3586 if (tmp != obj) {
3587 __ mov(tmp, obj);
3588 }
3589 if (do_null) {
3590 __ testptr(tmp, tmp);
3591 __ jccb(Assembler::notZero, update);
3592 if (!TypeEntries::was_null_seen(current_klass)) {
3593 __ orptr(mdo_addr, TypeEntries::null_seen);
3594 }
3595 if (do_update) {
3596 #ifndef ASSERT
3597 __ jmpb(next);
3598 }
3599 #else
3600 __ jmp(next);
3601 }
3602 } else {
3603 __ testptr(tmp, tmp);
3604 __ jcc(Assembler::notZero, update);
3605 __ stop("unexpect null obj");
3606 #endif
3607 }
3608
3609 __ bind(update);
3610
3611 if (do_update) {
3612 #ifdef ASSERT
3613 if (exact_klass != NULL) {
3614 Label ok;
3615 __ load_klass(tmp, tmp);
3616 __ push(tmp);
3617 __ mov_metadata(tmp, exact_klass->constant_encoding());
3618 __ cmpptr(tmp, Address(rsp, 0));
3619 __ jcc(Assembler::equal, ok);
3620 __ stop("exact klass and actual klass differ");
3621 __ bind(ok);
3622 __ pop(tmp);
3623 }
3624 #endif
3625 if (!no_conflict) {
3626 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3627 if (exact_klass != NULL) {
3628 __ mov_metadata(tmp, exact_klass->constant_encoding());
3629 } else {
3630 __ load_klass(tmp, tmp);
3631 }
3632
3633 __ xorptr(tmp, mdo_addr);
3634 __ testptr(tmp, TypeEntries::type_klass_mask);
3635 // klass seen before, nothing to do. The unknown bit may have been
3636 // set already but no need to check.
3637 __ jccb(Assembler::zero, next);
3638
3639 __ testptr(tmp, TypeEntries::type_unknown);
3640 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3641
3642 if (TypeEntries::is_type_none(current_klass)) {
3643 __ cmpptr(mdo_addr, 0);
3644 __ jccb(Assembler::equal, none);
3645 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3646 __ jccb(Assembler::equal, none);
3647 // There is a chance that the checks above (re-reading profiling
3648 // data from memory) fail if another thread has just set the
3649 // profiling to this obj's klass
3650 __ xorptr(tmp, mdo_addr);
3651 __ testptr(tmp, TypeEntries::type_klass_mask);
3652 __ jccb(Assembler::zero, next);
3653 }
3654 } else {
3655 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3656 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3657
3658 __ movptr(tmp, mdo_addr);
3659 __ testptr(tmp, TypeEntries::type_unknown);
3660 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3661 }
3662
3663 // different than before. Cannot keep accurate profile.
3664 __ orptr(mdo_addr, TypeEntries::type_unknown);
3665
3666 if (TypeEntries::is_type_none(current_klass)) {
3667 __ jmpb(next);
3668
3669 __ bind(none);
3670 // first time here. Set profile type.
3671 __ movptr(mdo_addr, tmp);
3672 }
3673 } else {
3674 // There's a single possible klass at this profile point
3675 assert(exact_klass != NULL, "should be");
3676 if (TypeEntries::is_type_none(current_klass)) {
3677 __ mov_metadata(tmp, exact_klass->constant_encoding());
3678 __ xorptr(tmp, mdo_addr);
3679 __ testptr(tmp, TypeEntries::type_klass_mask);
3680 #ifdef ASSERT
3681 __ jcc(Assembler::zero, next);
3682
3683 {
3684 Label ok;
3685 __ push(tmp);
3686 __ cmpptr(mdo_addr, 0);
3687 __ jcc(Assembler::equal, ok);
3688 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3689 __ jcc(Assembler::equal, ok);
3690 // may have been set by another thread
3691 __ mov_metadata(tmp, exact_klass->constant_encoding());
3692 __ xorptr(tmp, mdo_addr);
3693 __ testptr(tmp, TypeEntries::type_mask);
3694 __ jcc(Assembler::zero, ok);
3695
3696 __ stop("unexpected profiling mismatch");
3697 __ bind(ok);
3698 __ pop(tmp);
3699 }
3700 #else
3701 __ jccb(Assembler::zero, next);
3702 #endif
3703 // first time here. Set profile type.
3704 __ movptr(mdo_addr, tmp);
3705 } else {
3706 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3707 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3708
3709 __ movptr(tmp, mdo_addr);
3710 __ testptr(tmp, TypeEntries::type_unknown);
3711 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3712
3713 __ orptr(mdo_addr, TypeEntries::type_unknown);
3714 }
3715 }
3716
3717 __ bind(next);
3718 }
3719 }
3720
3721 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3722 Unimplemented();
3723 }
3724
3725
3726 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3727 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3728 }
3729
3730
3731 void LIR_Assembler::align_backward_branch_target() {
3732 __ align(BytesPerWord);
3733 }
3734
3735
3736 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3737 if (left->is_single_cpu()) {
3738 __ negl(left->as_register());
3739 move_regs(left->as_register(), dest->as_register());
3740
3741 } else if (left->is_double_cpu()) {
3742 Register lo = left->as_register_lo();
3743 #ifdef _LP64
3744 Register dst = dest->as_register_lo();
3745 __ movptr(dst, lo);
3746 __ negptr(dst);
3747 #else
3748 Register hi = left->as_register_hi();
3749 __ lneg(hi, lo);
3750 if (dest->as_register_lo() == hi) {
3751 assert(dest->as_register_hi() != lo, "destroying register");
3752 move_regs(hi, dest->as_register_hi());
3753 move_regs(lo, dest->as_register_lo());
3754 } else {
3755 move_regs(lo, dest->as_register_lo());
3756 move_regs(hi, dest->as_register_hi());
3757 }
3758 #endif // _LP64
3759
3760 } else if (dest->is_single_xmm()) {
3761 #ifdef _LP64
3762 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3763 assert(tmp->is_valid(), "need temporary");
3764 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3765 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3766 }
3767 else
3768 #endif
3769 {
3770 assert(!tmp->is_valid(), "do not need temporary");
3771 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3772 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3773 }
3774 __ xorps(dest->as_xmm_float_reg(),
3775 ExternalAddress((address)float_signflip_pool));
3776 }
3777 } else if (dest->is_double_xmm()) {
3778 #ifdef _LP64
3779 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3780 assert(tmp->is_valid(), "need temporary");
3781 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3782 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3783 }
3784 else
3785 #endif
3786 {
3787 assert(!tmp->is_valid(), "do not need temporary");
3788 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3789 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3790 }
3791 __ xorpd(dest->as_xmm_double_reg(),
3792 ExternalAddress((address)double_signflip_pool));
3793 }
3794 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3795 assert(left->fpu() == 0, "arg must be on TOS");
3796 assert(dest->fpu() == 0, "dest must be TOS");
3797 __ fchs();
3798
3799 } else {
3800 ShouldNotReachHere();
3801 }
3802 }
3803
3804
3805 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3806 assert(src->is_address(), "must be an address");
3807 assert(dest->is_register(), "must be a register");
3808
3809 PatchingStub* patch = NULL;
3810 if (patch_code != lir_patch_none) {
3811 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3812 }
3813
3814 Register reg = dest->as_pointer_register();
3815 LIR_Address* addr = src->as_address_ptr();
3816 __ lea(reg, as_Address(addr));
3817
3818 if (patch != NULL) {
3819 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3820 }
3821 }
3822
3823
3824
3825 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3826 assert(!tmp->is_valid(), "don't need temporary");
3827 __ call(RuntimeAddress(dest));
3828 if (info != NULL) {
3829 add_call_info_here(info);
3830 }
3831 }
3832
3833
3834 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3835 assert(type == T_LONG, "only for volatile long fields");
3836
3837 if (info != NULL) {
3838 add_debug_info_for_null_check_here(info);
3839 }
3840
3841 if (src->is_double_xmm()) {
3842 if (dest->is_double_cpu()) {
3843 #ifdef _LP64
3844 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3845 #else
3846 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3847 __ psrlq(src->as_xmm_double_reg(), 32);
3848 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3849 #endif // _LP64
3850 } else if (dest->is_double_stack()) {
3851 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3852 } else if (dest->is_address()) {
3853 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3854 } else {
3855 ShouldNotReachHere();
3856 }
3857
3858 } else if (dest->is_double_xmm()) {
3859 if (src->is_double_stack()) {
3860 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3861 } else if (src->is_address()) {
3862 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3863 } else {
3864 ShouldNotReachHere();
3865 }
3866
3867 } else if (src->is_double_fpu()) {
3868 assert(src->fpu_regnrLo() == 0, "must be TOS");
3869 if (dest->is_double_stack()) {
3870 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3871 } else if (dest->is_address()) {
3872 __ fistp_d(as_Address(dest->as_address_ptr()));
3873 } else {
3874 ShouldNotReachHere();
3875 }
3876
3877 } else if (dest->is_double_fpu()) {
3878 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3879 if (src->is_double_stack()) {
3880 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3881 } else if (src->is_address()) {
3882 __ fild_d(as_Address(src->as_address_ptr()));
3883 } else {
3884 ShouldNotReachHere();
3885 }
3886 } else {
3887 ShouldNotReachHere();
3888 }
3889 }
3890
3891 #ifdef ASSERT
3892 // emit run-time assertion
3893 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3894 assert(op->code() == lir_assert, "must be");
3895
3896 if (op->in_opr1()->is_valid()) {
3897 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3898 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3899 } else {
3900 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3901 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3902 }
3903
3904 Label ok;
3905 if (op->condition() != lir_cond_always) {
3906 Assembler::Condition acond = Assembler::zero;
3907 switch (op->condition()) {
3908 case lir_cond_equal: acond = Assembler::equal; break;
3909 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3910 case lir_cond_less: acond = Assembler::less; break;
3911 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3912 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3913 case lir_cond_greater: acond = Assembler::greater; break;
3914 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3915 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3916 default: ShouldNotReachHere();
3917 }
3918 __ jcc(acond, ok);
3919 }
3920 if (op->halt()) {
3921 const char* str = __ code_string(op->msg());
3922 __ stop(str);
3923 } else {
3924 breakpoint();
3925 }
3926 __ bind(ok);
3927 }
3928 #endif
3929
3930 void LIR_Assembler::membar() {
3931 // QQQ sparc TSO uses this,
3932 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3933 }
3934
3935 void LIR_Assembler::membar_acquire() {
3936 // No x86 machines currently require load fences
3937 }
3938
3939 void LIR_Assembler::membar_release() {
3940 // No x86 machines currently require store fences
3941 }
3942
3943 void LIR_Assembler::membar_loadload() {
3944 // no-op
3945 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3946 }
3947
3948 void LIR_Assembler::membar_storestore() {
3949 // no-op
3950 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3951 }
3952
3953 void LIR_Assembler::membar_loadstore() {
3954 // no-op
3955 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3956 }
3957
3958 void LIR_Assembler::membar_storeload() {
3959 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3960 }
3961
3962 void LIR_Assembler::on_spin_wait() {
3963 __ pause ();
3964 }
3965
3966 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3967 assert(result_reg->is_register(), "check");
3968 #ifdef _LP64
3969 // __ get_thread(result_reg->as_register_lo());
3970 __ mov(result_reg->as_register(), r15_thread);
3971 #else
3972 __ get_thread(result_reg->as_register());
3973 #endif // _LP64
3974 }
3975
3976
3977 void LIR_Assembler::peephole(LIR_List*) {
3978 // do nothing for now
3979 }
3980
3981 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3982 assert(data == dest, "xchg/xadd uses only 2 operands");
3983
3984 if (data->type() == T_INT) {
3985 if (code == lir_xadd) {
3986 __ lock();
3987 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3988 } else {
3989 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3990 }
3991 } else if (data->is_oop()) {
3992 assert (code == lir_xchg, "xadd for oops");
3993 Register obj = data->as_register();
3994 #ifdef _LP64
3995 if (UseCompressedOops) {
3996 __ encode_heap_oop(obj);
3997 __ xchgl(obj, as_Address(src->as_address_ptr()));
3998 __ decode_heap_oop(obj);
3999 } else {
4000 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4001 }
4002 #else
4003 __ xchgl(obj, as_Address(src->as_address_ptr()));
4004 #endif
4005 } else if (data->type() == T_LONG) {
4006 #ifdef _LP64
4007 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4008 if (code == lir_xadd) {
4009 __ lock();
4010 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4011 } else {
4012 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4013 }
4014 #else
4015 ShouldNotReachHere();
4016 #endif
4017 } else {
4018 ShouldNotReachHere();
4019 }
4020 }
4021
4022 #undef __