1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "ci/ciValueKlass.hpp"
36 #include "gc/shared/barrierSet.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "vmreg_x86.inline.hpp"
45
46
47 // These masks are used to provide 128-bit aligned bitmasks to the XMM
48 // instructions, to allow sign-masking or sign-bit flipping. They allow
49 // fast versions of NegF/NegD and AbsF/AbsD.
50
51 // Note: 'double' and 'long long' have 32-bits alignment on x86.
52 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
53 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
54 // of 128-bits operands for SSE instructions.
55 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
56 // Store the value to a 128-bits operand.
57 operand[0] = lo;
58 operand[1] = hi;
59 return operand;
60 }
61
62 // Buffer for 128-bits masks used by SSE instructions.
63 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
64
65 // Static initialization during VM startup.
66 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
67 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
68 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
69 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
70
71
72 NEEDS_CLEANUP // remove this definitions ?
73 const Register IC_Klass = rax; // where the IC klass is cached
74 const Register SYNC_header = rax; // synchronization header
75 const Register SHIFT_count = rcx; // where count for shift operations must be
76
77 #define __ _masm->
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp2 = extra;
90 }
91 assert_different_registers(preserve, tmp1, tmp2);
92 }
93
94
95
96 static void select_different_registers(Register preserve,
97 Register extra,
98 Register &tmp1,
99 Register &tmp2,
100 Register &tmp3) {
101 if (tmp1 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp1 = extra;
104 } else if (tmp2 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp2 = extra;
107 } else if (tmp3 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp3 = extra;
110 }
111 assert_different_registers(preserve, tmp1, tmp2, tmp3);
112 }
113
114
115
116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
117 if (opr->is_constant()) {
118 LIR_Const* constant = opr->as_constant_ptr();
119 switch (constant->type()) {
120 case T_INT: {
121 return true;
122 }
123
124 default:
125 return false;
126 }
127 }
128 return false;
129 }
130
131
132 LIR_Opr LIR_Assembler::receiverOpr() {
133 return FrameMap::receiver_opr;
134 }
135
136 LIR_Opr LIR_Assembler::osrBufferPointer() {
137 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
138 }
139
140 //--------------fpu register translations-----------------------
141
142
143 address LIR_Assembler::float_constant(float f) {
144 address const_addr = __ float_constant(f);
145 if (const_addr == NULL) {
146 bailout("const section overflow");
147 return __ code()->consts()->start();
148 } else {
149 return const_addr;
150 }
151 }
152
153
154 address LIR_Assembler::double_constant(double d) {
155 address const_addr = __ double_constant(d);
156 if (const_addr == NULL) {
157 bailout("const section overflow");
158 return __ code()->consts()->start();
159 } else {
160 return const_addr;
161 }
162 }
163
164
165 void LIR_Assembler::set_24bit_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
167 }
168
169 void LIR_Assembler::reset_FPU() {
170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
171 }
172
173 void LIR_Assembler::fpop() {
174 __ fpop();
175 }
176
177 void LIR_Assembler::fxch(int i) {
178 __ fxch(i);
179 }
180
181 void LIR_Assembler::fld(int i) {
182 __ fld_s(i);
183 }
184
185 void LIR_Assembler::ffree(int i) {
186 __ ffree(i);
187 }
188
189 void LIR_Assembler::breakpoint() {
190 __ int3();
191 }
192
193 void LIR_Assembler::push(LIR_Opr opr) {
194 if (opr->is_single_cpu()) {
195 __ push_reg(opr->as_register());
196 } else if (opr->is_double_cpu()) {
197 NOT_LP64(__ push_reg(opr->as_register_hi()));
198 __ push_reg(opr->as_register_lo());
199 } else if (opr->is_stack()) {
200 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
201 } else if (opr->is_constant()) {
202 LIR_Const* const_opr = opr->as_constant_ptr();
203 if (const_opr->type() == T_OBJECT || const_opr->type() == T_VALUETYPE) {
204 __ push_oop(const_opr->as_jobject());
205 } else if (const_opr->type() == T_INT) {
206 __ push_jint(const_opr->as_jint());
207 } else {
208 ShouldNotReachHere();
209 }
210
211 } else {
212 ShouldNotReachHere();
213 }
214 }
215
216 void LIR_Assembler::pop(LIR_Opr opr) {
217 if (opr->is_single_cpu()) {
218 __ pop_reg(opr->as_register());
219 } else {
220 ShouldNotReachHere();
221 }
222 }
223
224 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
225 return addr->base()->is_illegal() && addr->index()->is_illegal();
226 }
227
228 //-------------------------------------------
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr) {
231 return as_Address(addr, rscratch1);
232 }
233
234 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
235 if (addr->base()->is_illegal()) {
236 assert(addr->index()->is_illegal(), "must be illegal too");
237 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
238 if (! __ reachable(laddr)) {
239 __ movptr(tmp, laddr.addr());
240 Address res(tmp, 0);
241 return res;
242 } else {
243 return __ as_Address(laddr);
244 }
245 }
246
247 Register base = addr->base()->as_pointer_register();
248
249 if (addr->index()->is_illegal()) {
250 return Address( base, addr->disp());
251 } else if (addr->index()->is_cpu_register()) {
252 Register index = addr->index()->as_pointer_register();
253 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
254 } else if (addr->index()->is_constant()) {
255 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
256 assert(Assembler::is_simm32(addr_offset), "must be");
257
258 return Address(base, addr_offset);
259 } else {
260 Unimplemented();
261 return Address();
262 }
263 }
264
265
266 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
267 Address base = as_Address(addr);
268 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
269 }
270
271
272 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
273 return as_Address(addr);
274 }
275
276
277 void LIR_Assembler::osr_entry() {
278 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
279 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
280 ValueStack* entry_state = osr_entry->state();
281 int number_of_locks = entry_state->locks_size();
282
283 // we jump here if osr happens with the interpreter
284 // state set up to continue at the beginning of the
285 // loop that triggered osr - in particular, we have
286 // the following registers setup:
287 //
288 // rcx: osr buffer
289 //
290
291 // build frame
292 ciMethod* m = compilation()->method();
293 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes(),
294 needs_stack_repair(), NULL);
295
296 // OSR buffer is
297 //
298 // locals[nlocals-1..0]
299 // monitors[0..number_of_locks]
300 //
301 // locals is a direct copy of the interpreter frame so in the osr buffer
302 // so first slot in the local array is the last local from the interpreter
303 // and last slot is local[0] (receiver) from the interpreter
304 //
305 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
306 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
307 // in the interpreter frame (the method lock if a sync method)
308
309 // Initialize monitors in the compiled activation.
310 // rcx: pointer to osr buffer
311 //
312 // All other registers are dead at this point and the locals will be
313 // copied into place by code emitted in the IR.
314
315 Register OSR_buf = osrBufferPointer()->as_pointer_register();
316 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
317 int monitor_offset = BytesPerWord * method()->max_locals() +
318 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
319 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
320 // the OSR buffer using 2 word entries: first the lock and then
321 // the oop.
322 for (int i = 0; i < number_of_locks; i++) {
323 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
324 #ifdef ASSERT
325 // verify the interpreter's monitor has a non-null object
326 {
327 Label L;
328 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
329 __ jcc(Assembler::notZero, L);
330 __ stop("locked object is NULL");
331 __ bind(L);
332 }
333 #endif
334 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
335 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
336 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
337 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
338 }
339 }
340 }
341
342
343 // inline cache check; done before the frame is built.
344 int LIR_Assembler::check_icache() {
345 Register receiver = FrameMap::receiver_opr->as_register();
346 Register ic_klass = IC_Klass;
347 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
348 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
349 if (!do_post_padding) {
350 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
351 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
352 }
353 int offset = __ offset();
354 __ inline_cache_check(receiver, IC_Klass);
355 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
356 if (do_post_padding) {
357 // force alignment after the cache check.
358 // It's been verified to be aligned if !VerifyOops
359 __ align(CodeEntryAlignment);
360 }
361 return offset;
362 }
363
364
365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
366 jobject o = NULL;
367 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
368 __ movoop(reg, o);
369 patching_epilog(patch, lir_patch_normal, reg, info);
370 }
371
372 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
373 Metadata* o = NULL;
374 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
375 __ mov_metadata(reg, o);
376 patching_epilog(patch, lir_patch_normal, reg, info);
377 }
378
379 // This specifies the rsp decrement needed to build the frame
380 int LIR_Assembler::initial_frame_size_in_bytes() const {
381 // if rounding, must let FrameMap know!
382
383 // The frame_map records size in slots (32bit word)
384
385 // subtract two words to account for return address and link
386 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
387 }
388
389
390 int LIR_Assembler::emit_exception_handler() {
391 // if the last instruction is a call (typically to do a throw which
392 // is coming at the end after block reordering) the return address
393 // must still point into the code area in order to avoid assertion
394 // failures when searching for the corresponding bci => add a nop
395 // (was bug 5/14/1999 - gri)
396 __ nop();
397
398 // generate code for exception handler
399 address handler_base = __ start_a_stub(exception_handler_size());
400 if (handler_base == NULL) {
401 // not enough space left for the handler
402 bailout("exception handler overflow");
403 return -1;
404 }
405
406 int offset = code_offset();
407
408 // the exception oop and pc are in rax, and rdx
409 // no other registers need to be preserved, so invalidate them
410 __ invalidate_registers(false, true, true, false, true, true);
411
412 // check that there is really an exception
413 __ verify_not_null_oop(rax);
414
415 // search an exception handler (rax: exception oop, rdx: throwing pc)
416 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
417 __ should_not_reach_here();
418 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
419 __ end_a_stub();
420
421 return offset;
422 }
423
424
425 // Emit the code to remove the frame from the stack in the exception
426 // unwind path.
427 int LIR_Assembler::emit_unwind_handler() {
428 #ifndef PRODUCT
429 if (CommentedAssembly) {
430 _masm->block_comment("Unwind handler");
431 }
432 #endif
433
434 int offset = code_offset();
435
436 // Fetch the exception from TLS and clear out exception related thread state
437 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
438 NOT_LP64(__ get_thread(rsi));
439 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
440 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
441 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
442
443 __ bind(_unwind_handler_entry);
444 __ verify_not_null_oop(rax);
445 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
446 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
447 }
448
449 // Preform needed unlocking
450 MonitorExitStub* stub = NULL;
451 if (method()->is_synchronized()) {
452 monitor_address(0, FrameMap::rax_opr);
453 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
454 __ unlock_object(rdi, rsi, rax, *stub->entry());
455 __ bind(*stub->continuation());
456 }
457
458 if (compilation()->env()->dtrace_method_probes()) {
459 #ifdef _LP64
460 __ mov(rdi, r15_thread);
461 __ mov_metadata(rsi, method()->constant_encoding());
462 #else
463 __ get_thread(rax);
464 __ movptr(Address(rsp, 0), rax);
465 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
466 #endif
467 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
468 }
469
470 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
471 __ mov(rax, rbx); // Restore the exception
472 }
473
474 // remove the activation and dispatch to the unwind handler
475 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
476 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
477
478 // Emit the slow path assembly
479 if (stub != NULL) {
480 stub->emit_code(this);
481 }
482
483 return offset;
484 }
485
486
487 int LIR_Assembler::emit_deopt_handler() {
488 // if the last instruction is a call (typically to do a throw which
489 // is coming at the end after block reordering) the return address
490 // must still point into the code area in order to avoid assertion
491 // failures when searching for the corresponding bci => add a nop
492 // (was bug 5/14/1999 - gri)
493 __ nop();
494
495 // generate code for exception handler
496 address handler_base = __ start_a_stub(deopt_handler_size());
497 if (handler_base == NULL) {
498 // not enough space left for the handler
499 bailout("deopt handler overflow");
500 return -1;
501 }
502
503 int offset = code_offset();
504 InternalAddress here(__ pc());
505
506 __ pushptr(here.addr());
507 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
508 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
509 __ end_a_stub();
510
511 return offset;
512 }
513
514
515 void LIR_Assembler::return_op(LIR_Opr result) {
516 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
517 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
518 assert(result->fpu() == 0, "result must already be on TOS");
519 }
520
521 ciMethod* method = compilation()->method();
522 if (ValueTypeReturnedAsFields && method->signature()->returns_never_null()) {
523 ciType* return_type = method->return_type();
524 if (return_type->is_valuetype()) {
525 ciValueKlass* vk = return_type->as_value_klass();
526 if (vk->can_be_returned_as_fields()) {
527 #ifndef _LP64
528 Unimplemented();
529 #else
530 address unpack_handler = vk->unpack_handler();
531 assert(unpack_handler != NULL, "must be");
532 __ call(RuntimeAddress(unpack_handler));
533 // At this point, rax points to the value object (for interpreter or C1 caller).
534 // The fields of the object are copied into registers (for C2 caller).
535 #endif
536 }
537 }
538 }
539
540 // Pop the stack before the safepoint code
541 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
542
543 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
544 __ reserved_stack_check();
545 }
546
547 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
548
549 // Note: we do not need to round double result; float result has the right precision
550 // the poll sets the condition code, but no data registers
551
552 if (SafepointMechanism::uses_thread_local_poll()) {
553 #ifdef _LP64
554 const Register poll_addr = rscratch1;
555 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
556 #else
557 const Register poll_addr = rbx;
558 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
559 __ get_thread(poll_addr);
560 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
561 #endif
562 __ relocate(relocInfo::poll_return_type);
563 __ testl(rax, Address(poll_addr, 0));
564 } else {
565 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
566
567 if (Assembler::is_polling_page_far()) {
568 __ lea(rscratch1, polling_page);
569 __ relocate(relocInfo::poll_return_type);
570 __ testl(rax, Address(rscratch1, 0));
571 } else {
572 __ testl(rax, polling_page);
573 }
574 }
575 __ ret(0);
576 }
577
578
579 void LIR_Assembler::store_value_type_fields_to_buf(ciValueKlass* vk) {
580 __ store_value_type_fields_to_buf(vk);
581 }
582
583 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
584 guarantee(info != NULL, "Shouldn't be NULL");
585 int offset = __ offset();
586 if (SafepointMechanism::uses_thread_local_poll()) {
587 #ifdef _LP64
588 const Register poll_addr = rscratch1;
589 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
590 #else
591 assert(tmp->is_cpu_register(), "needed");
592 const Register poll_addr = tmp->as_register();
593 __ get_thread(poll_addr);
594 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
595 #endif
596 add_debug_info_for_branch(info);
597 __ relocate(relocInfo::poll_type);
598 address pre_pc = __ pc();
599 __ testl(rax, Address(poll_addr, 0));
600 address post_pc = __ pc();
601 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
602 } else {
603 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
604 if (Assembler::is_polling_page_far()) {
605 __ lea(rscratch1, polling_page);
606 offset = __ offset();
607 add_debug_info_for_branch(info);
608 __ relocate(relocInfo::poll_type);
609 __ testl(rax, Address(rscratch1, 0));
610 } else {
611 add_debug_info_for_branch(info);
612 __ testl(rax, polling_page);
613 }
614 }
615 return offset;
616 }
617
618
619 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
620 if (from_reg != to_reg) __ mov(to_reg, from_reg);
621 }
622
623 void LIR_Assembler::swap_reg(Register a, Register b) {
624 __ xchgptr(a, b);
625 }
626
627
628 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
629 assert(src->is_constant(), "should not call otherwise");
630 assert(dest->is_register(), "should not call otherwise");
631 LIR_Const* c = src->as_constant_ptr();
632
633 switch (c->type()) {
634 case T_INT: {
635 assert(patch_code == lir_patch_none, "no patching handled here");
636 __ movl(dest->as_register(), c->as_jint());
637 break;
638 }
639
640 case T_ADDRESS: {
641 assert(patch_code == lir_patch_none, "no patching handled here");
642 __ movptr(dest->as_register(), c->as_jint());
643 break;
644 }
645
646 case T_LONG: {
647 assert(patch_code == lir_patch_none, "no patching handled here");
648 #ifdef _LP64
649 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
650 #else
651 __ movptr(dest->as_register_lo(), c->as_jint_lo());
652 __ movptr(dest->as_register_hi(), c->as_jint_hi());
653 #endif // _LP64
654 break;
655 }
656
657 case T_VALUETYPE: // Fall through
658 case T_OBJECT: {
659 if (patch_code != lir_patch_none) {
660 jobject2reg_with_patching(dest->as_register(), info);
661 } else {
662 __ movoop(dest->as_register(), c->as_jobject());
663 }
664 break;
665 }
666
667 case T_METADATA: {
668 if (patch_code != lir_patch_none) {
669 klass2reg_with_patching(dest->as_register(), info);
670 } else {
671 __ mov_metadata(dest->as_register(), c->as_metadata());
672 }
673 break;
674 }
675
676 case T_FLOAT: {
677 if (dest->is_single_xmm()) {
678 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
679 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
680 } else {
681 __ movflt(dest->as_xmm_float_reg(),
682 InternalAddress(float_constant(c->as_jfloat())));
683 }
684 } else {
685 assert(dest->is_single_fpu(), "must be");
686 assert(dest->fpu_regnr() == 0, "dest must be TOS");
687 if (c->is_zero_float()) {
688 __ fldz();
689 } else if (c->is_one_float()) {
690 __ fld1();
691 } else {
692 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
693 }
694 }
695 break;
696 }
697
698 case T_DOUBLE: {
699 if (dest->is_double_xmm()) {
700 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
701 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
702 } else {
703 __ movdbl(dest->as_xmm_double_reg(),
704 InternalAddress(double_constant(c->as_jdouble())));
705 }
706 } else {
707 assert(dest->is_double_fpu(), "must be");
708 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
709 if (c->is_zero_double()) {
710 __ fldz();
711 } else if (c->is_one_double()) {
712 __ fld1();
713 } else {
714 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
715 }
716 }
717 break;
718 }
719
720 default:
721 ShouldNotReachHere();
722 }
723 }
724
725 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
726 assert(src->is_constant(), "should not call otherwise");
727 assert(dest->is_stack(), "should not call otherwise");
728 LIR_Const* c = src->as_constant_ptr();
729
730 switch (c->type()) {
731 case T_INT: // fall through
732 case T_FLOAT:
733 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
734 break;
735
736 case T_ADDRESS:
737 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
738 break;
739
740 case T_VALUETYPE: // Fall through
741 case T_OBJECT:
742 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
743 break;
744
745 case T_LONG: // fall through
746 case T_DOUBLE:
747 #ifdef _LP64
748 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
749 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
750 #else
751 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
752 lo_word_offset_in_bytes), c->as_jint_lo_bits());
753 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
754 hi_word_offset_in_bytes), c->as_jint_hi_bits());
755 #endif // _LP64
756 break;
757
758 default:
759 ShouldNotReachHere();
760 }
761 }
762
763 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
764 assert(src->is_constant(), "should not call otherwise");
765 assert(dest->is_address(), "should not call otherwise");
766 LIR_Const* c = src->as_constant_ptr();
767 LIR_Address* addr = dest->as_address_ptr();
768
769 int null_check_here = code_offset();
770 switch (type) {
771 case T_INT: // fall through
772 case T_FLOAT:
773 __ movl(as_Address(addr), c->as_jint_bits());
774 break;
775
776 case T_ADDRESS:
777 __ movptr(as_Address(addr), c->as_jint_bits());
778 break;
779
780 case T_VALUETYPE: // fall through
781 case T_OBJECT: // fall through
782 case T_ARRAY:
783 if (c->as_jobject() == NULL) {
784 if (UseCompressedOops && !wide) {
785 __ movl(as_Address(addr), (int32_t)NULL_WORD);
786 } else {
787 #ifdef _LP64
788 __ xorptr(rscratch1, rscratch1);
789 null_check_here = code_offset();
790 __ movptr(as_Address(addr), rscratch1);
791 #else
792 __ movptr(as_Address(addr), NULL_WORD);
793 #endif
794 }
795 } else {
796 if (is_literal_address(addr)) {
797 ShouldNotReachHere();
798 __ movoop(as_Address(addr, noreg), c->as_jobject());
799 } else {
800 #ifdef _LP64
801 __ movoop(rscratch1, c->as_jobject());
802 if (UseCompressedOops && !wide) {
803 __ encode_heap_oop(rscratch1);
804 null_check_here = code_offset();
805 __ movl(as_Address_lo(addr), rscratch1);
806 } else {
807 null_check_here = code_offset();
808 __ movptr(as_Address_lo(addr), rscratch1);
809 }
810 #else
811 __ movoop(as_Address(addr), c->as_jobject());
812 #endif
813 }
814 }
815 break;
816
817 case T_LONG: // fall through
818 case T_DOUBLE:
819 #ifdef _LP64
820 if (is_literal_address(addr)) {
821 ShouldNotReachHere();
822 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
823 } else {
824 __ movptr(r10, (intptr_t)c->as_jlong_bits());
825 null_check_here = code_offset();
826 __ movptr(as_Address_lo(addr), r10);
827 }
828 #else
829 // Always reachable in 32bit so this doesn't produce useless move literal
830 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
831 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
832 #endif // _LP64
833 break;
834
835 case T_BOOLEAN: // fall through
836 case T_BYTE:
837 __ movb(as_Address(addr), c->as_jint() & 0xFF);
838 break;
839
840 case T_CHAR: // fall through
841 case T_SHORT:
842 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
843 break;
844
845 default:
846 ShouldNotReachHere();
847 };
848
849 if (info != NULL) {
850 add_debug_info_for_null_check(null_check_here, info);
851 }
852 }
853
854
855 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
856 assert(src->is_register(), "should not call otherwise");
857 assert(dest->is_register(), "should not call otherwise");
858
859 // move between cpu-registers
860 if (dest->is_single_cpu()) {
861 #ifdef _LP64
862 if (src->type() == T_LONG) {
863 // Can do LONG -> OBJECT
864 move_regs(src->as_register_lo(), dest->as_register());
865 return;
866 }
867 #endif
868 assert(src->is_single_cpu(), "must match");
869 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
870 __ verify_oop(src->as_register());
871 }
872 move_regs(src->as_register(), dest->as_register());
873
874 } else if (dest->is_double_cpu()) {
875 #ifdef _LP64
876 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
877 // Surprising to me but we can see move of a long to t_object
878 __ verify_oop(src->as_register());
879 move_regs(src->as_register(), dest->as_register_lo());
880 return;
881 }
882 #endif
883 assert(src->is_double_cpu(), "must match");
884 Register f_lo = src->as_register_lo();
885 Register f_hi = src->as_register_hi();
886 Register t_lo = dest->as_register_lo();
887 Register t_hi = dest->as_register_hi();
888 #ifdef _LP64
889 assert(f_hi == f_lo, "must be same");
890 assert(t_hi == t_lo, "must be same");
891 move_regs(f_lo, t_lo);
892 #else
893 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
894
895
896 if (f_lo == t_hi && f_hi == t_lo) {
897 swap_reg(f_lo, f_hi);
898 } else if (f_hi == t_lo) {
899 assert(f_lo != t_hi, "overwriting register");
900 move_regs(f_hi, t_hi);
901 move_regs(f_lo, t_lo);
902 } else {
903 assert(f_hi != t_lo, "overwriting register");
904 move_regs(f_lo, t_lo);
905 move_regs(f_hi, t_hi);
906 }
907 #endif // LP64
908
909 // special moves from fpu-register to xmm-register
910 // necessary for method results
911 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
912 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
913 __ fld_s(Address(rsp, 0));
914 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
915 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
916 __ fld_d(Address(rsp, 0));
917 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
918 __ fstp_s(Address(rsp, 0));
919 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
920 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
921 __ fstp_d(Address(rsp, 0));
922 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
923
924 // move between xmm-registers
925 } else if (dest->is_single_xmm()) {
926 assert(src->is_single_xmm(), "must match");
927 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
928 } else if (dest->is_double_xmm()) {
929 assert(src->is_double_xmm(), "must match");
930 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
931
932 // move between fpu-registers (no instruction necessary because of fpu-stack)
933 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
934 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
935 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
936 } else {
937 ShouldNotReachHere();
938 }
939 }
940
941 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
942 assert(src->is_register(), "should not call otherwise");
943 assert(dest->is_stack(), "should not call otherwise");
944
945 if (src->is_single_cpu()) {
946 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
947 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) {
948 __ verify_oop(src->as_register());
949 __ movptr (dst, src->as_register());
950 } else if (type == T_METADATA) {
951 __ movptr (dst, src->as_register());
952 } else {
953 __ movl (dst, src->as_register());
954 }
955
956 } else if (src->is_double_cpu()) {
957 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
958 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
959 __ movptr (dstLO, src->as_register_lo());
960 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
961
962 } else if (src->is_single_xmm()) {
963 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
964 __ movflt(dst_addr, src->as_xmm_float_reg());
965
966 } else if (src->is_double_xmm()) {
967 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
968 __ movdbl(dst_addr, src->as_xmm_double_reg());
969
970 } else if (src->is_single_fpu()) {
971 assert(src->fpu_regnr() == 0, "argument must be on TOS");
972 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
973 if (pop_fpu_stack) __ fstp_s (dst_addr);
974 else __ fst_s (dst_addr);
975
976 } else if (src->is_double_fpu()) {
977 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
978 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
979 if (pop_fpu_stack) __ fstp_d (dst_addr);
980 else __ fst_d (dst_addr);
981
982 } else {
983 ShouldNotReachHere();
984 }
985 }
986
987
988 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
989 LIR_Address* to_addr = dest->as_address_ptr();
990 PatchingStub* patch = NULL;
991 Register compressed_src = rscratch1;
992
993 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
994 __ verify_oop(src->as_register());
995 #ifdef _LP64
996 if (UseCompressedOops && !wide) {
997 __ movptr(compressed_src, src->as_register());
998 __ encode_heap_oop(compressed_src);
999 if (patch_code != lir_patch_none) {
1000 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1001 }
1002 }
1003 #endif
1004 }
1005
1006 if (patch_code != lir_patch_none) {
1007 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1008 Address toa = as_Address(to_addr);
1009 assert(toa.disp() != 0, "must have");
1010 }
1011
1012 int null_check_here = code_offset();
1013 switch (type) {
1014 case T_FLOAT: {
1015 if (src->is_single_xmm()) {
1016 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1017 } else {
1018 assert(src->is_single_fpu(), "must be");
1019 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1020 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1021 else __ fst_s (as_Address(to_addr));
1022 }
1023 break;
1024 }
1025
1026 case T_DOUBLE: {
1027 if (src->is_double_xmm()) {
1028 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1029 } else {
1030 assert(src->is_double_fpu(), "must be");
1031 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1032 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1033 else __ fst_d (as_Address(to_addr));
1034 }
1035 break;
1036 }
1037
1038 case T_VALUETYPE: // fall through
1039 case T_ARRAY: // fall through
1040 case T_OBJECT: // fall through
1041 if (UseCompressedOops && !wide) {
1042 __ movl(as_Address(to_addr), compressed_src);
1043 } else {
1044 __ movptr(as_Address(to_addr), src->as_register());
1045 }
1046 break;
1047 case T_METADATA:
1048 // We get here to store a method pointer to the stack to pass to
1049 // a dtrace runtime call. This can't work on 64 bit with
1050 // compressed klass ptrs: T_METADATA can be a compressed klass
1051 // ptr or a 64 bit method pointer.
1052 LP64_ONLY(ShouldNotReachHere());
1053 __ movptr(as_Address(to_addr), src->as_register());
1054 break;
1055 case T_ADDRESS:
1056 __ movptr(as_Address(to_addr), src->as_register());
1057 break;
1058 case T_INT:
1059 __ movl(as_Address(to_addr), src->as_register());
1060 break;
1061
1062 case T_LONG: {
1063 Register from_lo = src->as_register_lo();
1064 Register from_hi = src->as_register_hi();
1065 #ifdef _LP64
1066 __ movptr(as_Address_lo(to_addr), from_lo);
1067 #else
1068 Register base = to_addr->base()->as_register();
1069 Register index = noreg;
1070 if (to_addr->index()->is_register()) {
1071 index = to_addr->index()->as_register();
1072 }
1073 if (base == from_lo || index == from_lo) {
1074 assert(base != from_hi, "can't be");
1075 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1076 __ movl(as_Address_hi(to_addr), from_hi);
1077 if (patch != NULL) {
1078 patching_epilog(patch, lir_patch_high, base, info);
1079 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1080 patch_code = lir_patch_low;
1081 }
1082 __ movl(as_Address_lo(to_addr), from_lo);
1083 } else {
1084 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1085 __ movl(as_Address_lo(to_addr), from_lo);
1086 if (patch != NULL) {
1087 patching_epilog(patch, lir_patch_low, base, info);
1088 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1089 patch_code = lir_patch_high;
1090 }
1091 __ movl(as_Address_hi(to_addr), from_hi);
1092 }
1093 #endif // _LP64
1094 break;
1095 }
1096
1097 case T_BYTE: // fall through
1098 case T_BOOLEAN: {
1099 Register src_reg = src->as_register();
1100 Address dst_addr = as_Address(to_addr);
1101 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1102 __ movb(dst_addr, src_reg);
1103 break;
1104 }
1105
1106 case T_CHAR: // fall through
1107 case T_SHORT:
1108 __ movw(as_Address(to_addr), src->as_register());
1109 break;
1110
1111 default:
1112 ShouldNotReachHere();
1113 }
1114 if (info != NULL) {
1115 add_debug_info_for_null_check(null_check_here, info);
1116 }
1117
1118 if (patch_code != lir_patch_none) {
1119 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1120 }
1121 }
1122
1123
1124 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1125 assert(src->is_stack(), "should not call otherwise");
1126 assert(dest->is_register(), "should not call otherwise");
1127
1128 if (dest->is_single_cpu()) {
1129 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1130 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1131 __ verify_oop(dest->as_register());
1132 } else if (type == T_METADATA) {
1133 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1134 } else {
1135 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1136 }
1137
1138 } else if (dest->is_double_cpu()) {
1139 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1140 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1141 __ movptr(dest->as_register_lo(), src_addr_LO);
1142 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1143
1144 } else if (dest->is_single_xmm()) {
1145 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1146 __ movflt(dest->as_xmm_float_reg(), src_addr);
1147
1148 } else if (dest->is_double_xmm()) {
1149 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1150 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1151
1152 } else if (dest->is_single_fpu()) {
1153 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1154 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1155 __ fld_s(src_addr);
1156
1157 } else if (dest->is_double_fpu()) {
1158 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1159 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1160 __ fld_d(src_addr);
1161
1162 } else {
1163 ShouldNotReachHere();
1164 }
1165 }
1166
1167
1168 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1169 if (src->is_single_stack()) {
1170 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) {
1171 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1172 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1173 } else {
1174 #ifndef _LP64
1175 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1176 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1177 #else
1178 //no pushl on 64bits
1179 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1180 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1181 #endif
1182 }
1183
1184 } else if (src->is_double_stack()) {
1185 #ifdef _LP64
1186 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1187 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1188 #else
1189 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1190 // push and pop the part at src + wordSize, adding wordSize for the previous push
1191 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1192 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1193 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1194 #endif // _LP64
1195
1196 } else {
1197 ShouldNotReachHere();
1198 }
1199 }
1200
1201
1202 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1203 assert(src->is_address(), "should not call otherwise");
1204 assert(dest->is_register(), "should not call otherwise");
1205
1206 LIR_Address* addr = src->as_address_ptr();
1207 Address from_addr = as_Address(addr);
1208
1209 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
1210 __ verify_oop(addr->base()->as_pointer_register());
1211 }
1212
1213 switch (type) {
1214 case T_BOOLEAN: // fall through
1215 case T_BYTE: // fall through
1216 case T_CHAR: // fall through
1217 case T_SHORT:
1218 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1219 // on pre P6 processors we may get partial register stalls
1220 // so blow away the value of to_rinfo before loading a
1221 // partial word into it. Do it here so that it precedes
1222 // the potential patch point below.
1223 __ xorptr(dest->as_register(), dest->as_register());
1224 }
1225 break;
1226 default:
1227 break;
1228 }
1229
1230 PatchingStub* patch = NULL;
1231 if (patch_code != lir_patch_none) {
1232 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1233 assert(from_addr.disp() != 0, "must have");
1234 }
1235 if (info != NULL) {
1236 add_debug_info_for_null_check_here(info);
1237 }
1238
1239 switch (type) {
1240 case T_FLOAT: {
1241 if (dest->is_single_xmm()) {
1242 __ movflt(dest->as_xmm_float_reg(), from_addr);
1243 } else {
1244 assert(dest->is_single_fpu(), "must be");
1245 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1246 __ fld_s(from_addr);
1247 }
1248 break;
1249 }
1250
1251 case T_DOUBLE: {
1252 if (dest->is_double_xmm()) {
1253 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1254 } else {
1255 assert(dest->is_double_fpu(), "must be");
1256 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1257 __ fld_d(from_addr);
1258 }
1259 break;
1260 }
1261
1262 case T_VALUETYPE: // fall through
1263 case T_OBJECT: // fall through
1264 case T_ARRAY: // fall through
1265 if (UseCompressedOops && !wide) {
1266 __ movl(dest->as_register(), from_addr);
1267 } else {
1268 __ movptr(dest->as_register(), from_addr);
1269 }
1270 break;
1271
1272 case T_ADDRESS:
1273 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1274 __ movl(dest->as_register(), from_addr);
1275 } else {
1276 __ movptr(dest->as_register(), from_addr);
1277 }
1278 break;
1279 case T_INT:
1280 __ movl(dest->as_register(), from_addr);
1281 break;
1282
1283 case T_LONG: {
1284 Register to_lo = dest->as_register_lo();
1285 Register to_hi = dest->as_register_hi();
1286 #ifdef _LP64
1287 __ movptr(to_lo, as_Address_lo(addr));
1288 #else
1289 Register base = addr->base()->as_register();
1290 Register index = noreg;
1291 if (addr->index()->is_register()) {
1292 index = addr->index()->as_register();
1293 }
1294 if ((base == to_lo && index == to_hi) ||
1295 (base == to_hi && index == to_lo)) {
1296 // addresses with 2 registers are only formed as a result of
1297 // array access so this code will never have to deal with
1298 // patches or null checks.
1299 assert(info == NULL && patch == NULL, "must be");
1300 __ lea(to_hi, as_Address(addr));
1301 __ movl(to_lo, Address(to_hi, 0));
1302 __ movl(to_hi, Address(to_hi, BytesPerWord));
1303 } else if (base == to_lo || index == to_lo) {
1304 assert(base != to_hi, "can't be");
1305 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1306 __ movl(to_hi, as_Address_hi(addr));
1307 if (patch != NULL) {
1308 patching_epilog(patch, lir_patch_high, base, info);
1309 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1310 patch_code = lir_patch_low;
1311 }
1312 __ movl(to_lo, as_Address_lo(addr));
1313 } else {
1314 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1315 __ movl(to_lo, as_Address_lo(addr));
1316 if (patch != NULL) {
1317 patching_epilog(patch, lir_patch_low, base, info);
1318 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1319 patch_code = lir_patch_high;
1320 }
1321 __ movl(to_hi, as_Address_hi(addr));
1322 }
1323 #endif // _LP64
1324 break;
1325 }
1326
1327 case T_BOOLEAN: // fall through
1328 case T_BYTE: {
1329 Register dest_reg = dest->as_register();
1330 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1331 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1332 __ movsbl(dest_reg, from_addr);
1333 } else {
1334 __ movb(dest_reg, from_addr);
1335 __ shll(dest_reg, 24);
1336 __ sarl(dest_reg, 24);
1337 }
1338 break;
1339 }
1340
1341 case T_CHAR: {
1342 Register dest_reg = dest->as_register();
1343 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1344 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1345 __ movzwl(dest_reg, from_addr);
1346 } else {
1347 __ movw(dest_reg, from_addr);
1348 }
1349 break;
1350 }
1351
1352 case T_SHORT: {
1353 Register dest_reg = dest->as_register();
1354 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1355 __ movswl(dest_reg, from_addr);
1356 } else {
1357 __ movw(dest_reg, from_addr);
1358 __ shll(dest_reg, 16);
1359 __ sarl(dest_reg, 16);
1360 }
1361 break;
1362 }
1363
1364 default:
1365 ShouldNotReachHere();
1366 }
1367
1368 if (patch != NULL) {
1369 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1370 }
1371
1372 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1373 #ifdef _LP64
1374 if (UseCompressedOops && !wide) {
1375 __ decode_heap_oop(dest->as_register());
1376 }
1377 #endif
1378
1379 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1380 if (!UseZGC) {
1381 __ verify_oop(dest->as_register());
1382 }
1383 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1384 #ifdef _LP64
1385 if (UseCompressedClassPointers) {
1386 __ decode_klass_not_null(dest->as_register());
1387 }
1388 #endif
1389 }
1390 }
1391
1392
1393 NEEDS_CLEANUP; // This could be static?
1394 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1395 int elem_size = type2aelembytes(type);
1396 switch (elem_size) {
1397 case 1: return Address::times_1;
1398 case 2: return Address::times_2;
1399 case 4: return Address::times_4;
1400 case 8: return Address::times_8;
1401 }
1402 ShouldNotReachHere();
1403 return Address::no_scale;
1404 }
1405
1406
1407 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1408 switch (op->code()) {
1409 case lir_idiv:
1410 case lir_irem:
1411 arithmetic_idiv(op->code(),
1412 op->in_opr1(),
1413 op->in_opr2(),
1414 op->in_opr3(),
1415 op->result_opr(),
1416 op->info());
1417 break;
1418 case lir_fmad:
1419 __ fmad(op->result_opr()->as_xmm_double_reg(),
1420 op->in_opr1()->as_xmm_double_reg(),
1421 op->in_opr2()->as_xmm_double_reg(),
1422 op->in_opr3()->as_xmm_double_reg());
1423 break;
1424 case lir_fmaf:
1425 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1426 op->in_opr1()->as_xmm_float_reg(),
1427 op->in_opr2()->as_xmm_float_reg(),
1428 op->in_opr3()->as_xmm_float_reg());
1429 break;
1430 default: ShouldNotReachHere(); break;
1431 }
1432 }
1433
1434 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1435 #ifdef ASSERT
1436 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1437 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1438 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1439 #endif
1440
1441 if (op->cond() == lir_cond_always) {
1442 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1443 __ jmp (*(op->label()));
1444 } else {
1445 Assembler::Condition acond = Assembler::zero;
1446 if (op->code() == lir_cond_float_branch) {
1447 assert(op->ublock() != NULL, "must have unordered successor");
1448 __ jcc(Assembler::parity, *(op->ublock()->label()));
1449 switch(op->cond()) {
1450 case lir_cond_equal: acond = Assembler::equal; break;
1451 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1452 case lir_cond_less: acond = Assembler::below; break;
1453 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1454 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1455 case lir_cond_greater: acond = Assembler::above; break;
1456 default: ShouldNotReachHere();
1457 }
1458 } else {
1459 switch (op->cond()) {
1460 case lir_cond_equal: acond = Assembler::equal; break;
1461 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1462 case lir_cond_less: acond = Assembler::less; break;
1463 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1464 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1465 case lir_cond_greater: acond = Assembler::greater; break;
1466 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1467 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1468 default: ShouldNotReachHere();
1469 }
1470 }
1471 __ jcc(acond,*(op->label()));
1472 }
1473 }
1474
1475 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1476 LIR_Opr src = op->in_opr();
1477 LIR_Opr dest = op->result_opr();
1478
1479 switch (op->bytecode()) {
1480 case Bytecodes::_i2l:
1481 #ifdef _LP64
1482 __ movl2ptr(dest->as_register_lo(), src->as_register());
1483 #else
1484 move_regs(src->as_register(), dest->as_register_lo());
1485 move_regs(src->as_register(), dest->as_register_hi());
1486 __ sarl(dest->as_register_hi(), 31);
1487 #endif // LP64
1488 break;
1489
1490 case Bytecodes::_l2i:
1491 #ifdef _LP64
1492 __ movl(dest->as_register(), src->as_register_lo());
1493 #else
1494 move_regs(src->as_register_lo(), dest->as_register());
1495 #endif
1496 break;
1497
1498 case Bytecodes::_i2b:
1499 move_regs(src->as_register(), dest->as_register());
1500 __ sign_extend_byte(dest->as_register());
1501 break;
1502
1503 case Bytecodes::_i2c:
1504 move_regs(src->as_register(), dest->as_register());
1505 __ andl(dest->as_register(), 0xFFFF);
1506 break;
1507
1508 case Bytecodes::_i2s:
1509 move_regs(src->as_register(), dest->as_register());
1510 __ sign_extend_short(dest->as_register());
1511 break;
1512
1513
1514 case Bytecodes::_f2d:
1515 case Bytecodes::_d2f:
1516 if (dest->is_single_xmm()) {
1517 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1518 } else if (dest->is_double_xmm()) {
1519 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1520 } else {
1521 assert(src->fpu() == dest->fpu(), "register must be equal");
1522 // do nothing (float result is rounded later through spilling)
1523 }
1524 break;
1525
1526 case Bytecodes::_i2f:
1527 case Bytecodes::_i2d:
1528 if (dest->is_single_xmm()) {
1529 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1530 } else if (dest->is_double_xmm()) {
1531 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1532 } else {
1533 assert(dest->fpu() == 0, "result must be on TOS");
1534 __ movl(Address(rsp, 0), src->as_register());
1535 __ fild_s(Address(rsp, 0));
1536 }
1537 break;
1538
1539 case Bytecodes::_f2i:
1540 case Bytecodes::_d2i:
1541 if (src->is_single_xmm()) {
1542 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1543 } else if (src->is_double_xmm()) {
1544 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1545 } else {
1546 assert(src->fpu() == 0, "input must be on TOS");
1547 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1548 __ fist_s(Address(rsp, 0));
1549 __ movl(dest->as_register(), Address(rsp, 0));
1550 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1551 }
1552
1553 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1554 assert(op->stub() != NULL, "stub required");
1555 __ cmpl(dest->as_register(), 0x80000000);
1556 __ jcc(Assembler::equal, *op->stub()->entry());
1557 __ bind(*op->stub()->continuation());
1558 break;
1559
1560 case Bytecodes::_l2f:
1561 case Bytecodes::_l2d:
1562 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1563 assert(dest->fpu() == 0, "result must be on TOS");
1564
1565 __ movptr(Address(rsp, 0), src->as_register_lo());
1566 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1567 __ fild_d(Address(rsp, 0));
1568 // float result is rounded later through spilling
1569 break;
1570
1571 case Bytecodes::_f2l:
1572 case Bytecodes::_d2l:
1573 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1574 assert(src->fpu() == 0, "input must be on TOS");
1575 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1576
1577 // instruction sequence too long to inline it here
1578 {
1579 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1580 }
1581 break;
1582
1583 default: ShouldNotReachHere();
1584 }
1585 }
1586
1587 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1588 if (op->init_check()) {
1589 add_debug_info_for_null_check_here(op->stub()->info());
1590 __ cmpb(Address(op->klass()->as_register(),
1591 InstanceKlass::init_state_offset()),
1592 InstanceKlass::fully_initialized);
1593 __ jcc(Assembler::notEqual, *op->stub()->entry());
1594 }
1595 __ allocate_object(op->obj()->as_register(),
1596 op->tmp1()->as_register(),
1597 op->tmp2()->as_register(),
1598 op->header_size(),
1599 op->object_size(),
1600 op->klass()->as_register(),
1601 *op->stub()->entry());
1602 __ bind(*op->stub()->continuation());
1603 }
1604
1605 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1606 Register len = op->len()->as_register();
1607 LP64_ONLY( __ movslq(len, len); )
1608
1609 if (UseSlowPath || op->type() == T_VALUETYPE ||
1610 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1611 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1612 __ jmp(*op->stub()->entry());
1613 } else {
1614 Register tmp1 = op->tmp1()->as_register();
1615 Register tmp2 = op->tmp2()->as_register();
1616 Register tmp3 = op->tmp3()->as_register();
1617 if (len == tmp1) {
1618 tmp1 = tmp3;
1619 } else if (len == tmp2) {
1620 tmp2 = tmp3;
1621 } else if (len == tmp3) {
1622 // everything is ok
1623 } else {
1624 __ mov(tmp3, len);
1625 }
1626 __ allocate_array(op->obj()->as_register(),
1627 len,
1628 tmp1,
1629 tmp2,
1630 arrayOopDesc::header_size(op->type()),
1631 array_element_size(op->type()),
1632 op->klass()->as_register(),
1633 *op->stub()->entry());
1634 }
1635 __ bind(*op->stub()->continuation());
1636 }
1637
1638 void LIR_Assembler::type_profile_helper(Register mdo,
1639 ciMethodData *md, ciProfileData *data,
1640 Register recv, Label* update_done) {
1641 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1642 Label next_test;
1643 // See if the receiver is receiver[n].
1644 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1645 __ jccb(Assembler::notEqual, next_test);
1646 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1647 __ addptr(data_addr, DataLayout::counter_increment);
1648 __ jmp(*update_done);
1649 __ bind(next_test);
1650 }
1651
1652 // Didn't find receiver; find next empty slot and fill it in
1653 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1654 Label next_test;
1655 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1656 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1657 __ jccb(Assembler::notEqual, next_test);
1658 __ movptr(recv_addr, recv);
1659 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1660 __ jmp(*update_done);
1661 __ bind(next_test);
1662 }
1663 }
1664
1665 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1666 // we always need a stub for the failure case.
1667 CodeStub* stub = op->stub();
1668 Register obj = op->object()->as_register();
1669 Register k_RInfo = op->tmp1()->as_register();
1670 Register klass_RInfo = op->tmp2()->as_register();
1671 Register dst = op->result_opr()->as_register();
1672 ciKlass* k = op->klass();
1673 Register Rtmp1 = noreg;
1674
1675 // check if it needs to be profiled
1676 ciMethodData* md = NULL;
1677 ciProfileData* data = NULL;
1678
1679 if (op->should_profile()) {
1680 ciMethod* method = op->profiled_method();
1681 assert(method != NULL, "Should have method");
1682 int bci = op->profiled_bci();
1683 md = method->method_data_or_null();
1684 assert(md != NULL, "Sanity");
1685 data = md->bci_to_data(bci);
1686 assert(data != NULL, "need data for type check");
1687 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1688 }
1689 Label profile_cast_success, profile_cast_failure;
1690 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1691 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1692
1693 if (obj == k_RInfo) {
1694 k_RInfo = dst;
1695 } else if (obj == klass_RInfo) {
1696 klass_RInfo = dst;
1697 }
1698 if (k->is_loaded() && !UseCompressedClassPointers) {
1699 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1700 } else {
1701 Rtmp1 = op->tmp3()->as_register();
1702 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1703 }
1704
1705 assert_different_registers(obj, k_RInfo, klass_RInfo);
1706
1707 if (op->need_null_check()) {
1708 __ cmpptr(obj, (int32_t)NULL_WORD);
1709 if (op->should_profile()) {
1710 Label not_null;
1711 __ jccb(Assembler::notEqual, not_null);
1712 // Object is null; update MDO and exit
1713 Register mdo = klass_RInfo;
1714 __ mov_metadata(mdo, md->constant_encoding());
1715 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1716 int header_bits = BitData::null_seen_byte_constant();
1717 __ orb(data_addr, header_bits);
1718 __ jmp(*obj_is_null);
1719 __ bind(not_null);
1720 } else {
1721 __ jcc(Assembler::equal, *obj_is_null);
1722 }
1723 }
1724
1725 if (!k->is_loaded()) {
1726 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1727 } else {
1728 #ifdef _LP64
1729 __ mov_metadata(k_RInfo, k->constant_encoding());
1730 #endif // _LP64
1731 }
1732 __ verify_oop(obj);
1733
1734 if (op->fast_check()) {
1735 // get object class
1736 // not a safepoint as obj null check happens earlier
1737 #ifdef _LP64
1738 if (UseCompressedClassPointers) {
1739 __ load_klass(Rtmp1, obj);
1740 __ cmpptr(k_RInfo, Rtmp1);
1741 } else {
1742 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1743 }
1744 #else
1745 if (k->is_loaded()) {
1746 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1747 } else {
1748 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1749 }
1750 #endif
1751 __ jcc(Assembler::notEqual, *failure_target);
1752 // successful cast, fall through to profile or jump
1753 } else {
1754 // get object class
1755 // not a safepoint as obj null check happens earlier
1756 __ load_klass(klass_RInfo, obj);
1757 if (k->is_loaded()) {
1758 // See if we get an immediate positive hit
1759 #ifdef _LP64
1760 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1761 #else
1762 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1763 #endif // _LP64
1764 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1765 __ jcc(Assembler::notEqual, *failure_target);
1766 // successful cast, fall through to profile or jump
1767 } else {
1768 // See if we get an immediate positive hit
1769 __ jcc(Assembler::equal, *success_target);
1770 // check for self
1771 #ifdef _LP64
1772 __ cmpptr(klass_RInfo, k_RInfo);
1773 #else
1774 __ cmpklass(klass_RInfo, k->constant_encoding());
1775 #endif // _LP64
1776 __ jcc(Assembler::equal, *success_target);
1777
1778 __ push(klass_RInfo);
1779 #ifdef _LP64
1780 __ push(k_RInfo);
1781 #else
1782 __ pushklass(k->constant_encoding());
1783 #endif // _LP64
1784 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1785 __ pop(klass_RInfo);
1786 __ pop(klass_RInfo);
1787 // result is a boolean
1788 __ cmpl(klass_RInfo, 0);
1789 __ jcc(Assembler::equal, *failure_target);
1790 // successful cast, fall through to profile or jump
1791 }
1792 } else {
1793 // perform the fast part of the checking logic
1794 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1795 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1796 __ push(klass_RInfo);
1797 __ push(k_RInfo);
1798 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1799 __ pop(klass_RInfo);
1800 __ pop(k_RInfo);
1801 // result is a boolean
1802 __ cmpl(k_RInfo, 0);
1803 __ jcc(Assembler::equal, *failure_target);
1804 // successful cast, fall through to profile or jump
1805 }
1806 }
1807 if (op->should_profile()) {
1808 Register mdo = klass_RInfo, recv = k_RInfo;
1809 __ bind(profile_cast_success);
1810 __ mov_metadata(mdo, md->constant_encoding());
1811 __ load_klass(recv, obj);
1812 type_profile_helper(mdo, md, data, recv, success);
1813 __ jmp(*success);
1814
1815 __ bind(profile_cast_failure);
1816 __ mov_metadata(mdo, md->constant_encoding());
1817 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1818 __ subptr(counter_addr, DataLayout::counter_increment);
1819 __ jmp(*failure);
1820 }
1821 __ jmp(*success);
1822 }
1823
1824
1825 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1826 LIR_Code code = op->code();
1827 if (code == lir_store_check) {
1828 Register value = op->object()->as_register();
1829 Register array = op->array()->as_register();
1830 Register k_RInfo = op->tmp1()->as_register();
1831 Register klass_RInfo = op->tmp2()->as_register();
1832 Register Rtmp1 = op->tmp3()->as_register();
1833
1834 CodeStub* stub = op->stub();
1835
1836 // check if it needs to be profiled
1837 ciMethodData* md = NULL;
1838 ciProfileData* data = NULL;
1839
1840 if (op->should_profile()) {
1841 ciMethod* method = op->profiled_method();
1842 assert(method != NULL, "Should have method");
1843 int bci = op->profiled_bci();
1844 md = method->method_data_or_null();
1845 assert(md != NULL, "Sanity");
1846 data = md->bci_to_data(bci);
1847 assert(data != NULL, "need data for type check");
1848 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1849 }
1850 Label profile_cast_success, profile_cast_failure, done;
1851 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1852 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1853
1854 __ cmpptr(value, (int32_t)NULL_WORD);
1855 if (op->should_profile()) {
1856 Label not_null;
1857 __ jccb(Assembler::notEqual, not_null);
1858 // Object is null; update MDO and exit
1859 Register mdo = klass_RInfo;
1860 __ mov_metadata(mdo, md->constant_encoding());
1861 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1862 int header_bits = BitData::null_seen_byte_constant();
1863 __ orb(data_addr, header_bits);
1864 __ jmp(done);
1865 __ bind(not_null);
1866 } else {
1867 __ jcc(Assembler::equal, done);
1868 }
1869
1870 add_debug_info_for_null_check_here(op->info_for_exception());
1871 __ load_klass(k_RInfo, array);
1872 __ load_klass(klass_RInfo, value);
1873
1874 // get instance klass (it's already uncompressed)
1875 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1876 // perform the fast part of the checking logic
1877 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1878 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1879 __ push(klass_RInfo);
1880 __ push(k_RInfo);
1881 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1882 __ pop(klass_RInfo);
1883 __ pop(k_RInfo);
1884 // result is a boolean
1885 __ cmpl(k_RInfo, 0);
1886 __ jcc(Assembler::equal, *failure_target);
1887 // fall through to the success case
1888
1889 if (op->should_profile()) {
1890 Register mdo = klass_RInfo, recv = k_RInfo;
1891 __ bind(profile_cast_success);
1892 __ mov_metadata(mdo, md->constant_encoding());
1893 __ load_klass(recv, value);
1894 type_profile_helper(mdo, md, data, recv, &done);
1895 __ jmpb(done);
1896
1897 __ bind(profile_cast_failure);
1898 __ mov_metadata(mdo, md->constant_encoding());
1899 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1900 __ subptr(counter_addr, DataLayout::counter_increment);
1901 __ jmp(*stub->entry());
1902 }
1903
1904 __ bind(done);
1905 } else
1906 if (code == lir_checkcast) {
1907 Register obj = op->object()->as_register();
1908 Register dst = op->result_opr()->as_register();
1909 Label success;
1910 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1911 __ bind(success);
1912 if (dst != obj) {
1913 __ mov(dst, obj);
1914 }
1915 } else
1916 if (code == lir_instanceof) {
1917 Register obj = op->object()->as_register();
1918 Register dst = op->result_opr()->as_register();
1919 Label success, failure, done;
1920 emit_typecheck_helper(op, &success, &failure, &failure);
1921 __ bind(failure);
1922 __ xorptr(dst, dst);
1923 __ jmpb(done);
1924 __ bind(success);
1925 __ movptr(dst, 1);
1926 __ bind(done);
1927 } else {
1928 ShouldNotReachHere();
1929 }
1930
1931 }
1932
1933 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1934 // We are loading/storing an array that *may* be a flattened array (e.g., the declared type
1935 // is Object[]). If this array is flattened, take slow path.
1936
1937 __ load_storage_props(op->tmp()->as_register(), op->array()->as_register());
1938 __ testb(op->tmp()->as_register(), ArrayStorageProperties::flattened_value);
1939 __ jcc(Assembler::notZero, *op->stub()->entry());
1940 if (!op->value()->is_illegal()) {
1941 // We are storing into the array.
1942 Label skip;
1943 __ testb(op->tmp()->as_register(), ArrayStorageProperties::null_free_value);
1944 __ jcc(Assembler::zero, skip);
1945 // The array is not flattened, but it is null_free. If we are storing
1946 // a null, take the slow path (which will throw NPE).
1947 __ cmpptr(op->value()->as_register(), (int32_t)NULL_WORD);
1948 __ jcc(Assembler::zero, *op->stub()->entry());
1949 __ bind(skip);
1950 }
1951 }
1952
1953 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1954 // This is called when we use aastore into a an array declared as "[LVT;",
1955 // where we know VT is not flattenable (due to ValueArrayElemMaxFlatOops, etc).
1956 // However, we need to do a NULL check if the actual array is a "QLVT;".
1957
1958 __ load_storage_props(op->tmp()->as_register(), op->array()->as_register());
1959 __ testb(op->tmp()->as_register(), ArrayStorageProperties::null_free_value);
1960 }
1961
1962 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1963 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1964 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1965 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1966 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1967 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1968 Register addr = op->addr()->as_register();
1969 __ lock();
1970 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1971
1972 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1973 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1974 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1975 Register newval = op->new_value()->as_register();
1976 Register cmpval = op->cmp_value()->as_register();
1977 assert(cmpval == rax, "wrong register");
1978 assert(newval != NULL, "new val must be register");
1979 assert(cmpval != newval, "cmp and new values must be in different registers");
1980 assert(cmpval != addr, "cmp and addr must be in different registers");
1981 assert(newval != addr, "new value and addr must be in different registers");
1982
1983 if ( op->code() == lir_cas_obj) {
1984 #ifdef _LP64
1985 if (UseCompressedOops) {
1986 __ encode_heap_oop(cmpval);
1987 __ mov(rscratch1, newval);
1988 __ encode_heap_oop(rscratch1);
1989 __ lock();
1990 // cmpval (rax) is implicitly used by this instruction
1991 __ cmpxchgl(rscratch1, Address(addr, 0));
1992 } else
1993 #endif
1994 {
1995 __ lock();
1996 __ cmpxchgptr(newval, Address(addr, 0));
1997 }
1998 } else {
1999 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2000 __ lock();
2001 __ cmpxchgl(newval, Address(addr, 0));
2002 }
2003 #ifdef _LP64
2004 } else if (op->code() == lir_cas_long) {
2005 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2006 Register newval = op->new_value()->as_register_lo();
2007 Register cmpval = op->cmp_value()->as_register_lo();
2008 assert(cmpval == rax, "wrong register");
2009 assert(newval != NULL, "new val must be register");
2010 assert(cmpval != newval, "cmp and new values must be in different registers");
2011 assert(cmpval != addr, "cmp and addr must be in different registers");
2012 assert(newval != addr, "new value and addr must be in different registers");
2013 __ lock();
2014 __ cmpxchgq(newval, Address(addr, 0));
2015 #endif // _LP64
2016 } else {
2017 Unimplemented();
2018 }
2019 }
2020
2021 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2022 Assembler::Condition acond, ncond;
2023 switch (condition) {
2024 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2025 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2026 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2027 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2028 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2029 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2030 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2031 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2032 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2033 ShouldNotReachHere();
2034 }
2035
2036 if (opr1->is_cpu_register()) {
2037 reg2reg(opr1, result);
2038 } else if (opr1->is_stack()) {
2039 stack2reg(opr1, result, result->type());
2040 } else if (opr1->is_constant()) {
2041 const2reg(opr1, result, lir_patch_none, NULL);
2042 } else {
2043 ShouldNotReachHere();
2044 }
2045
2046 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2047 // optimized version that does not require a branch
2048 if (opr2->is_single_cpu()) {
2049 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2050 __ cmov(ncond, result->as_register(), opr2->as_register());
2051 } else if (opr2->is_double_cpu()) {
2052 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2053 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2054 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2055 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2056 } else if (opr2->is_single_stack()) {
2057 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2058 } else if (opr2->is_double_stack()) {
2059 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2060 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2061 } else {
2062 ShouldNotReachHere();
2063 }
2064
2065 } else {
2066 Label skip;
2067 __ jcc (acond, skip);
2068 if (opr2->is_cpu_register()) {
2069 reg2reg(opr2, result);
2070 } else if (opr2->is_stack()) {
2071 stack2reg(opr2, result, result->type());
2072 } else if (opr2->is_constant()) {
2073 const2reg(opr2, result, lir_patch_none, NULL);
2074 } else {
2075 ShouldNotReachHere();
2076 }
2077 __ bind(skip);
2078 }
2079 }
2080
2081
2082 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2083 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2084
2085 if (left->is_single_cpu()) {
2086 assert(left == dest, "left and dest must be equal");
2087 Register lreg = left->as_register();
2088
2089 if (right->is_single_cpu()) {
2090 // cpu register - cpu register
2091 Register rreg = right->as_register();
2092 switch (code) {
2093 case lir_add: __ addl (lreg, rreg); break;
2094 case lir_sub: __ subl (lreg, rreg); break;
2095 case lir_mul: __ imull(lreg, rreg); break;
2096 default: ShouldNotReachHere();
2097 }
2098
2099 } else if (right->is_stack()) {
2100 // cpu register - stack
2101 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2102 switch (code) {
2103 case lir_add: __ addl(lreg, raddr); break;
2104 case lir_sub: __ subl(lreg, raddr); break;
2105 default: ShouldNotReachHere();
2106 }
2107
2108 } else if (right->is_constant()) {
2109 // cpu register - constant
2110 jint c = right->as_constant_ptr()->as_jint();
2111 switch (code) {
2112 case lir_add: {
2113 __ incrementl(lreg, c);
2114 break;
2115 }
2116 case lir_sub: {
2117 __ decrementl(lreg, c);
2118 break;
2119 }
2120 default: ShouldNotReachHere();
2121 }
2122
2123 } else {
2124 ShouldNotReachHere();
2125 }
2126
2127 } else if (left->is_double_cpu()) {
2128 assert(left == dest, "left and dest must be equal");
2129 Register lreg_lo = left->as_register_lo();
2130 Register lreg_hi = left->as_register_hi();
2131
2132 if (right->is_double_cpu()) {
2133 // cpu register - cpu register
2134 Register rreg_lo = right->as_register_lo();
2135 Register rreg_hi = right->as_register_hi();
2136 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2137 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2138 switch (code) {
2139 case lir_add:
2140 __ addptr(lreg_lo, rreg_lo);
2141 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2142 break;
2143 case lir_sub:
2144 __ subptr(lreg_lo, rreg_lo);
2145 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2146 break;
2147 case lir_mul:
2148 #ifdef _LP64
2149 __ imulq(lreg_lo, rreg_lo);
2150 #else
2151 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2152 __ imull(lreg_hi, rreg_lo);
2153 __ imull(rreg_hi, lreg_lo);
2154 __ addl (rreg_hi, lreg_hi);
2155 __ mull (rreg_lo);
2156 __ addl (lreg_hi, rreg_hi);
2157 #endif // _LP64
2158 break;
2159 default:
2160 ShouldNotReachHere();
2161 }
2162
2163 } else if (right->is_constant()) {
2164 // cpu register - constant
2165 #ifdef _LP64
2166 jlong c = right->as_constant_ptr()->as_jlong_bits();
2167 __ movptr(r10, (intptr_t) c);
2168 switch (code) {
2169 case lir_add:
2170 __ addptr(lreg_lo, r10);
2171 break;
2172 case lir_sub:
2173 __ subptr(lreg_lo, r10);
2174 break;
2175 default:
2176 ShouldNotReachHere();
2177 }
2178 #else
2179 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2180 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2181 switch (code) {
2182 case lir_add:
2183 __ addptr(lreg_lo, c_lo);
2184 __ adcl(lreg_hi, c_hi);
2185 break;
2186 case lir_sub:
2187 __ subptr(lreg_lo, c_lo);
2188 __ sbbl(lreg_hi, c_hi);
2189 break;
2190 default:
2191 ShouldNotReachHere();
2192 }
2193 #endif // _LP64
2194
2195 } else {
2196 ShouldNotReachHere();
2197 }
2198
2199 } else if (left->is_single_xmm()) {
2200 assert(left == dest, "left and dest must be equal");
2201 XMMRegister lreg = left->as_xmm_float_reg();
2202
2203 if (right->is_single_xmm()) {
2204 XMMRegister rreg = right->as_xmm_float_reg();
2205 switch (code) {
2206 case lir_add: __ addss(lreg, rreg); break;
2207 case lir_sub: __ subss(lreg, rreg); break;
2208 case lir_mul_strictfp: // fall through
2209 case lir_mul: __ mulss(lreg, rreg); break;
2210 case lir_div_strictfp: // fall through
2211 case lir_div: __ divss(lreg, rreg); break;
2212 default: ShouldNotReachHere();
2213 }
2214 } else {
2215 Address raddr;
2216 if (right->is_single_stack()) {
2217 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2218 } else if (right->is_constant()) {
2219 // hack for now
2220 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2221 } else {
2222 ShouldNotReachHere();
2223 }
2224 switch (code) {
2225 case lir_add: __ addss(lreg, raddr); break;
2226 case lir_sub: __ subss(lreg, raddr); break;
2227 case lir_mul_strictfp: // fall through
2228 case lir_mul: __ mulss(lreg, raddr); break;
2229 case lir_div_strictfp: // fall through
2230 case lir_div: __ divss(lreg, raddr); break;
2231 default: ShouldNotReachHere();
2232 }
2233 }
2234
2235 } else if (left->is_double_xmm()) {
2236 assert(left == dest, "left and dest must be equal");
2237
2238 XMMRegister lreg = left->as_xmm_double_reg();
2239 if (right->is_double_xmm()) {
2240 XMMRegister rreg = right->as_xmm_double_reg();
2241 switch (code) {
2242 case lir_add: __ addsd(lreg, rreg); break;
2243 case lir_sub: __ subsd(lreg, rreg); break;
2244 case lir_mul_strictfp: // fall through
2245 case lir_mul: __ mulsd(lreg, rreg); break;
2246 case lir_div_strictfp: // fall through
2247 case lir_div: __ divsd(lreg, rreg); break;
2248 default: ShouldNotReachHere();
2249 }
2250 } else {
2251 Address raddr;
2252 if (right->is_double_stack()) {
2253 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2254 } else if (right->is_constant()) {
2255 // hack for now
2256 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2257 } else {
2258 ShouldNotReachHere();
2259 }
2260 switch (code) {
2261 case lir_add: __ addsd(lreg, raddr); break;
2262 case lir_sub: __ subsd(lreg, raddr); break;
2263 case lir_mul_strictfp: // fall through
2264 case lir_mul: __ mulsd(lreg, raddr); break;
2265 case lir_div_strictfp: // fall through
2266 case lir_div: __ divsd(lreg, raddr); break;
2267 default: ShouldNotReachHere();
2268 }
2269 }
2270
2271 } else if (left->is_single_fpu()) {
2272 assert(dest->is_single_fpu(), "fpu stack allocation required");
2273
2274 if (right->is_single_fpu()) {
2275 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2276
2277 } else {
2278 assert(left->fpu_regnr() == 0, "left must be on TOS");
2279 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2280
2281 Address raddr;
2282 if (right->is_single_stack()) {
2283 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2284 } else if (right->is_constant()) {
2285 address const_addr = float_constant(right->as_jfloat());
2286 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2287 // hack for now
2288 raddr = __ as_Address(InternalAddress(const_addr));
2289 } else {
2290 ShouldNotReachHere();
2291 }
2292
2293 switch (code) {
2294 case lir_add: __ fadd_s(raddr); break;
2295 case lir_sub: __ fsub_s(raddr); break;
2296 case lir_mul_strictfp: // fall through
2297 case lir_mul: __ fmul_s(raddr); break;
2298 case lir_div_strictfp: // fall through
2299 case lir_div: __ fdiv_s(raddr); break;
2300 default: ShouldNotReachHere();
2301 }
2302 }
2303
2304 } else if (left->is_double_fpu()) {
2305 assert(dest->is_double_fpu(), "fpu stack allocation required");
2306
2307 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2308 // Double values require special handling for strictfp mul/div on x86
2309 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2310 __ fmulp(left->fpu_regnrLo() + 1);
2311 }
2312
2313 if (right->is_double_fpu()) {
2314 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2315
2316 } else {
2317 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2318 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2319
2320 Address raddr;
2321 if (right->is_double_stack()) {
2322 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2323 } else if (right->is_constant()) {
2324 // hack for now
2325 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2326 } else {
2327 ShouldNotReachHere();
2328 }
2329
2330 switch (code) {
2331 case lir_add: __ fadd_d(raddr); break;
2332 case lir_sub: __ fsub_d(raddr); break;
2333 case lir_mul_strictfp: // fall through
2334 case lir_mul: __ fmul_d(raddr); break;
2335 case lir_div_strictfp: // fall through
2336 case lir_div: __ fdiv_d(raddr); break;
2337 default: ShouldNotReachHere();
2338 }
2339 }
2340
2341 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2342 // Double values require special handling for strictfp mul/div on x86
2343 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2344 __ fmulp(dest->fpu_regnrLo() + 1);
2345 }
2346
2347 } else if (left->is_single_stack() || left->is_address()) {
2348 assert(left == dest, "left and dest must be equal");
2349
2350 Address laddr;
2351 if (left->is_single_stack()) {
2352 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2353 } else if (left->is_address()) {
2354 laddr = as_Address(left->as_address_ptr());
2355 } else {
2356 ShouldNotReachHere();
2357 }
2358
2359 if (right->is_single_cpu()) {
2360 Register rreg = right->as_register();
2361 switch (code) {
2362 case lir_add: __ addl(laddr, rreg); break;
2363 case lir_sub: __ subl(laddr, rreg); break;
2364 default: ShouldNotReachHere();
2365 }
2366 } else if (right->is_constant()) {
2367 jint c = right->as_constant_ptr()->as_jint();
2368 switch (code) {
2369 case lir_add: {
2370 __ incrementl(laddr, c);
2371 break;
2372 }
2373 case lir_sub: {
2374 __ decrementl(laddr, c);
2375 break;
2376 }
2377 default: ShouldNotReachHere();
2378 }
2379 } else {
2380 ShouldNotReachHere();
2381 }
2382
2383 } else {
2384 ShouldNotReachHere();
2385 }
2386 }
2387
2388 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2389 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2390 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2391 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2392
2393 bool left_is_tos = (left_index == 0);
2394 bool dest_is_tos = (dest_index == 0);
2395 int non_tos_index = (left_is_tos ? right_index : left_index);
2396
2397 switch (code) {
2398 case lir_add:
2399 if (pop_fpu_stack) __ faddp(non_tos_index);
2400 else if (dest_is_tos) __ fadd (non_tos_index);
2401 else __ fadda(non_tos_index);
2402 break;
2403
2404 case lir_sub:
2405 if (left_is_tos) {
2406 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2407 else if (dest_is_tos) __ fsub (non_tos_index);
2408 else __ fsubra(non_tos_index);
2409 } else {
2410 if (pop_fpu_stack) __ fsubp (non_tos_index);
2411 else if (dest_is_tos) __ fsubr (non_tos_index);
2412 else __ fsuba (non_tos_index);
2413 }
2414 break;
2415
2416 case lir_mul_strictfp: // fall through
2417 case lir_mul:
2418 if (pop_fpu_stack) __ fmulp(non_tos_index);
2419 else if (dest_is_tos) __ fmul (non_tos_index);
2420 else __ fmula(non_tos_index);
2421 break;
2422
2423 case lir_div_strictfp: // fall through
2424 case lir_div:
2425 if (left_is_tos) {
2426 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2427 else if (dest_is_tos) __ fdiv (non_tos_index);
2428 else __ fdivra(non_tos_index);
2429 } else {
2430 if (pop_fpu_stack) __ fdivp (non_tos_index);
2431 else if (dest_is_tos) __ fdivr (non_tos_index);
2432 else __ fdiva (non_tos_index);
2433 }
2434 break;
2435
2436 case lir_rem:
2437 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2438 __ fremr(noreg);
2439 break;
2440
2441 default:
2442 ShouldNotReachHere();
2443 }
2444 }
2445
2446
2447 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2448 if (value->is_double_xmm()) {
2449 switch(code) {
2450 case lir_abs :
2451 {
2452 #ifdef _LP64
2453 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2454 assert(tmp->is_valid(), "need temporary");
2455 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2456 } else
2457 #endif
2458 {
2459 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2460 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2461 }
2462 assert(!tmp->is_valid(), "do not need temporary");
2463 __ andpd(dest->as_xmm_double_reg(),
2464 ExternalAddress((address)double_signmask_pool));
2465 }
2466 }
2467 break;
2468
2469 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2470 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2471 default : ShouldNotReachHere();
2472 }
2473
2474 } else if (value->is_double_fpu()) {
2475 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2476 switch(code) {
2477 case lir_abs : __ fabs() ; break;
2478 case lir_sqrt : __ fsqrt(); break;
2479 default : ShouldNotReachHere();
2480 }
2481 } else {
2482 Unimplemented();
2483 }
2484 }
2485
2486 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2487 // assert(left->destroys_register(), "check");
2488 if (left->is_single_cpu()) {
2489 Register reg = left->as_register();
2490 if (right->is_constant()) {
2491 int val = right->as_constant_ptr()->as_jint();
2492 switch (code) {
2493 case lir_logic_and: __ andl (reg, val); break;
2494 case lir_logic_or: __ orl (reg, val); break;
2495 case lir_logic_xor: __ xorl (reg, val); break;
2496 default: ShouldNotReachHere();
2497 }
2498 } else if (right->is_stack()) {
2499 // added support for stack operands
2500 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2501 switch (code) {
2502 case lir_logic_and: __ andl (reg, raddr); break;
2503 case lir_logic_or: __ orl (reg, raddr); break;
2504 case lir_logic_xor: __ xorl (reg, raddr); break;
2505 default: ShouldNotReachHere();
2506 }
2507 } else {
2508 Register rright = right->as_register();
2509 switch (code) {
2510 case lir_logic_and: __ andptr (reg, rright); break;
2511 case lir_logic_or : __ orptr (reg, rright); break;
2512 case lir_logic_xor: __ xorptr (reg, rright); break;
2513 default: ShouldNotReachHere();
2514 }
2515 }
2516 move_regs(reg, dst->as_register());
2517 } else {
2518 Register l_lo = left->as_register_lo();
2519 Register l_hi = left->as_register_hi();
2520 if (right->is_constant()) {
2521 #ifdef _LP64
2522 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2523 switch (code) {
2524 case lir_logic_and:
2525 __ andq(l_lo, rscratch1);
2526 break;
2527 case lir_logic_or:
2528 __ orq(l_lo, rscratch1);
2529 break;
2530 case lir_logic_xor:
2531 __ xorq(l_lo, rscratch1);
2532 break;
2533 default: ShouldNotReachHere();
2534 }
2535 #else
2536 int r_lo = right->as_constant_ptr()->as_jint_lo();
2537 int r_hi = right->as_constant_ptr()->as_jint_hi();
2538 switch (code) {
2539 case lir_logic_and:
2540 __ andl(l_lo, r_lo);
2541 __ andl(l_hi, r_hi);
2542 break;
2543 case lir_logic_or:
2544 __ orl(l_lo, r_lo);
2545 __ orl(l_hi, r_hi);
2546 break;
2547 case lir_logic_xor:
2548 __ xorl(l_lo, r_lo);
2549 __ xorl(l_hi, r_hi);
2550 break;
2551 default: ShouldNotReachHere();
2552 }
2553 #endif // _LP64
2554 } else {
2555 #ifdef _LP64
2556 Register r_lo;
2557 if (right->type() == T_OBJECT || right->type() == T_ARRAY || right->type() == T_VALUETYPE) {
2558 r_lo = right->as_register();
2559 } else {
2560 r_lo = right->as_register_lo();
2561 }
2562 #else
2563 Register r_lo = right->as_register_lo();
2564 Register r_hi = right->as_register_hi();
2565 assert(l_lo != r_hi, "overwriting registers");
2566 #endif
2567 switch (code) {
2568 case lir_logic_and:
2569 __ andptr(l_lo, r_lo);
2570 NOT_LP64(__ andptr(l_hi, r_hi);)
2571 break;
2572 case lir_logic_or:
2573 __ orptr(l_lo, r_lo);
2574 NOT_LP64(__ orptr(l_hi, r_hi);)
2575 break;
2576 case lir_logic_xor:
2577 __ xorptr(l_lo, r_lo);
2578 NOT_LP64(__ xorptr(l_hi, r_hi);)
2579 break;
2580 default: ShouldNotReachHere();
2581 }
2582 }
2583
2584 Register dst_lo = dst->as_register_lo();
2585 Register dst_hi = dst->as_register_hi();
2586
2587 #ifdef _LP64
2588 move_regs(l_lo, dst_lo);
2589 #else
2590 if (dst_lo == l_hi) {
2591 assert(dst_hi != l_lo, "overwriting registers");
2592 move_regs(l_hi, dst_hi);
2593 move_regs(l_lo, dst_lo);
2594 } else {
2595 assert(dst_lo != l_hi, "overwriting registers");
2596 move_regs(l_lo, dst_lo);
2597 move_regs(l_hi, dst_hi);
2598 }
2599 #endif // _LP64
2600 }
2601 }
2602
2603
2604 // we assume that rax, and rdx can be overwritten
2605 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2606
2607 assert(left->is_single_cpu(), "left must be register");
2608 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2609 assert(result->is_single_cpu(), "result must be register");
2610
2611 // assert(left->destroys_register(), "check");
2612 // assert(right->destroys_register(), "check");
2613
2614 Register lreg = left->as_register();
2615 Register dreg = result->as_register();
2616
2617 if (right->is_constant()) {
2618 jint divisor = right->as_constant_ptr()->as_jint();
2619 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2620 if (code == lir_idiv) {
2621 assert(lreg == rax, "must be rax,");
2622 assert(temp->as_register() == rdx, "tmp register must be rdx");
2623 __ cdql(); // sign extend into rdx:rax
2624 if (divisor == 2) {
2625 __ subl(lreg, rdx);
2626 } else {
2627 __ andl(rdx, divisor - 1);
2628 __ addl(lreg, rdx);
2629 }
2630 __ sarl(lreg, log2_jint(divisor));
2631 move_regs(lreg, dreg);
2632 } else if (code == lir_irem) {
2633 Label done;
2634 __ mov(dreg, lreg);
2635 __ andl(dreg, 0x80000000 | (divisor - 1));
2636 __ jcc(Assembler::positive, done);
2637 __ decrement(dreg);
2638 __ orl(dreg, ~(divisor - 1));
2639 __ increment(dreg);
2640 __ bind(done);
2641 } else {
2642 ShouldNotReachHere();
2643 }
2644 } else {
2645 Register rreg = right->as_register();
2646 assert(lreg == rax, "left register must be rax,");
2647 assert(rreg != rdx, "right register must not be rdx");
2648 assert(temp->as_register() == rdx, "tmp register must be rdx");
2649
2650 move_regs(lreg, rax);
2651
2652 int idivl_offset = __ corrected_idivl(rreg);
2653 if (ImplicitDiv0Checks) {
2654 add_debug_info_for_div0(idivl_offset, info);
2655 }
2656 if (code == lir_irem) {
2657 move_regs(rdx, dreg); // result is in rdx
2658 } else {
2659 move_regs(rax, dreg);
2660 }
2661 }
2662 }
2663
2664
2665 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2666 if (opr1->is_single_cpu()) {
2667 Register reg1 = opr1->as_register();
2668 if (opr2->is_single_cpu()) {
2669 // cpu register - cpu register
2670 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2671 __ cmpoop(reg1, opr2->as_register());
2672 } else {
2673 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
2674 __ cmpl(reg1, opr2->as_register());
2675 }
2676 } else if (opr2->is_stack()) {
2677 // cpu register - stack
2678 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2679 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2680 } else {
2681 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2682 }
2683 } else if (opr2->is_constant()) {
2684 // cpu register - constant
2685 LIR_Const* c = opr2->as_constant_ptr();
2686 if (c->type() == T_INT) {
2687 __ cmpl(reg1, c->as_jint());
2688 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2689 // In 64bit oops are single register
2690 jobject o = c->as_jobject();
2691 if (o == NULL) {
2692 __ cmpptr(reg1, (int32_t)NULL_WORD);
2693 } else {
2694 __ cmpoop(reg1, o);
2695 }
2696 } else {
2697 fatal("unexpected type: %s", basictype_to_str(c->type()));
2698 }
2699 // cpu register - address
2700 } else if (opr2->is_address()) {
2701 if (op->info() != NULL) {
2702 add_debug_info_for_null_check_here(op->info());
2703 }
2704 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2705 } else {
2706 ShouldNotReachHere();
2707 }
2708
2709 } else if(opr1->is_double_cpu()) {
2710 Register xlo = opr1->as_register_lo();
2711 Register xhi = opr1->as_register_hi();
2712 if (opr2->is_double_cpu()) {
2713 #ifdef _LP64
2714 __ cmpptr(xlo, opr2->as_register_lo());
2715 #else
2716 // cpu register - cpu register
2717 Register ylo = opr2->as_register_lo();
2718 Register yhi = opr2->as_register_hi();
2719 __ subl(xlo, ylo);
2720 __ sbbl(xhi, yhi);
2721 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2722 __ orl(xhi, xlo);
2723 }
2724 #endif // _LP64
2725 } else if (opr2->is_constant()) {
2726 // cpu register - constant 0
2727 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2728 #ifdef _LP64
2729 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2730 #else
2731 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2732 __ orl(xhi, xlo);
2733 #endif // _LP64
2734 } else {
2735 ShouldNotReachHere();
2736 }
2737
2738 } else if (opr1->is_single_xmm()) {
2739 XMMRegister reg1 = opr1->as_xmm_float_reg();
2740 if (opr2->is_single_xmm()) {
2741 // xmm register - xmm register
2742 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2743 } else if (opr2->is_stack()) {
2744 // xmm register - stack
2745 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2746 } else if (opr2->is_constant()) {
2747 // xmm register - constant
2748 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2749 } else if (opr2->is_address()) {
2750 // xmm register - address
2751 if (op->info() != NULL) {
2752 add_debug_info_for_null_check_here(op->info());
2753 }
2754 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2755 } else {
2756 ShouldNotReachHere();
2757 }
2758
2759 } else if (opr1->is_double_xmm()) {
2760 XMMRegister reg1 = opr1->as_xmm_double_reg();
2761 if (opr2->is_double_xmm()) {
2762 // xmm register - xmm register
2763 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2764 } else if (opr2->is_stack()) {
2765 // xmm register - stack
2766 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2767 } else if (opr2->is_constant()) {
2768 // xmm register - constant
2769 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2770 } else if (opr2->is_address()) {
2771 // xmm register - address
2772 if (op->info() != NULL) {
2773 add_debug_info_for_null_check_here(op->info());
2774 }
2775 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2776 } else {
2777 ShouldNotReachHere();
2778 }
2779
2780 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2781 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2782 assert(opr2->is_fpu_register(), "both must be registers");
2783 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2784
2785 } else if (opr1->is_address() && opr2->is_constant()) {
2786 LIR_Const* c = opr2->as_constant_ptr();
2787 #ifdef _LP64
2788 if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2789 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2790 __ movoop(rscratch1, c->as_jobject());
2791 }
2792 #endif // LP64
2793 if (op->info() != NULL) {
2794 add_debug_info_for_null_check_here(op->info());
2795 }
2796 // special case: address - constant
2797 LIR_Address* addr = opr1->as_address_ptr();
2798 if (c->type() == T_INT) {
2799 __ cmpl(as_Address(addr), c->as_jint());
2800 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2801 #ifdef _LP64
2802 // %%% Make this explode if addr isn't reachable until we figure out a
2803 // better strategy by giving noreg as the temp for as_Address
2804 __ cmpoop(rscratch1, as_Address(addr, noreg));
2805 #else
2806 __ cmpoop(as_Address(addr), c->as_jobject());
2807 #endif // _LP64
2808 } else {
2809 ShouldNotReachHere();
2810 }
2811
2812 } else {
2813 ShouldNotReachHere();
2814 }
2815 }
2816
2817 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2818 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2819 if (left->is_single_xmm()) {
2820 assert(right->is_single_xmm(), "must match");
2821 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2822 } else if (left->is_double_xmm()) {
2823 assert(right->is_double_xmm(), "must match");
2824 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2825
2826 } else {
2827 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2828 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2829
2830 assert(left->fpu() == 0, "left must be on TOS");
2831 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2832 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2833 }
2834 } else {
2835 assert(code == lir_cmp_l2i, "check");
2836 #ifdef _LP64
2837 Label done;
2838 Register dest = dst->as_register();
2839 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2840 __ movl(dest, -1);
2841 __ jccb(Assembler::less, done);
2842 __ set_byte_if_not_zero(dest);
2843 __ movzbl(dest, dest);
2844 __ bind(done);
2845 #else
2846 __ lcmp2int(left->as_register_hi(),
2847 left->as_register_lo(),
2848 right->as_register_hi(),
2849 right->as_register_lo());
2850 move_regs(left->as_register_hi(), dst->as_register());
2851 #endif // _LP64
2852 }
2853 }
2854
2855
2856 void LIR_Assembler::align_call(LIR_Code code) {
2857 // make sure that the displacement word of the call ends up word aligned
2858 int offset = __ offset();
2859 switch (code) {
2860 case lir_static_call:
2861 case lir_optvirtual_call:
2862 case lir_dynamic_call:
2863 offset += NativeCall::displacement_offset;
2864 break;
2865 case lir_icvirtual_call:
2866 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2867 break;
2868 case lir_virtual_call: // currently, sparc-specific for niagara
2869 default: ShouldNotReachHere();
2870 }
2871 __ align(BytesPerWord, offset);
2872 }
2873
2874
2875 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2876 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2877 "must be aligned");
2878 __ call(AddressLiteral(op->addr(), rtype));
2879 add_call_info(code_offset(), op->info());
2880 }
2881
2882
2883 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2884 __ ic_call(op->addr());
2885 add_call_info(code_offset(), op->info());
2886 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2887 "must be aligned");
2888 }
2889
2890
2891 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2892 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2893 ShouldNotReachHere();
2894 }
2895
2896
2897 void LIR_Assembler::emit_static_call_stub() {
2898 address call_pc = __ pc();
2899 address stub = __ start_a_stub(call_stub_size());
2900 if (stub == NULL) {
2901 bailout("static call stub overflow");
2902 return;
2903 }
2904
2905 int start = __ offset();
2906
2907 // make sure that the displacement word of the call ends up word aligned
2908 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2909 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2910 __ mov_metadata(rbx, (Metadata*)NULL);
2911 // must be set to -1 at code generation time
2912 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2913 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2914 __ jump(RuntimeAddress(__ pc()));
2915
2916 if (UseAOT) {
2917 // Trampoline to aot code
2918 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2919 #ifdef _LP64
2920 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2921 #else
2922 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2923 #endif
2924 __ jmp(rax);
2925 }
2926 assert(__ offset() - start <= call_stub_size(), "stub too big");
2927 __ end_a_stub();
2928 }
2929
2930
2931 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2932 assert(exceptionOop->as_register() == rax, "must match");
2933 assert(exceptionPC->as_register() == rdx, "must match");
2934
2935 // exception object is not added to oop map by LinearScan
2936 // (LinearScan assumes that no oops are in fixed registers)
2937 info->add_register_oop(exceptionOop);
2938 Runtime1::StubID unwind_id;
2939
2940 // get current pc information
2941 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2942 int pc_for_athrow_offset = __ offset();
2943 InternalAddress pc_for_athrow(__ pc());
2944 __ lea(exceptionPC->as_register(), pc_for_athrow);
2945 add_call_info(pc_for_athrow_offset, info); // for exception handler
2946
2947 __ verify_not_null_oop(rax);
2948 // search an exception handler (rax: exception oop, rdx: throwing pc)
2949 if (compilation()->has_fpu_code()) {
2950 unwind_id = Runtime1::handle_exception_id;
2951 } else {
2952 unwind_id = Runtime1::handle_exception_nofpu_id;
2953 }
2954 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2955
2956 // enough room for two byte trap
2957 __ nop();
2958 }
2959
2960
2961 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2962 assert(exceptionOop->as_register() == rax, "must match");
2963
2964 __ jmp(_unwind_handler_entry);
2965 }
2966
2967
2968 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2969
2970 // optimized version for linear scan:
2971 // * count must be already in ECX (guaranteed by LinearScan)
2972 // * left and dest must be equal
2973 // * tmp must be unused
2974 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2975 assert(left == dest, "left and dest must be equal");
2976 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2977
2978 if (left->is_single_cpu()) {
2979 Register value = left->as_register();
2980 assert(value != SHIFT_count, "left cannot be ECX");
2981
2982 switch (code) {
2983 case lir_shl: __ shll(value); break;
2984 case lir_shr: __ sarl(value); break;
2985 case lir_ushr: __ shrl(value); break;
2986 default: ShouldNotReachHere();
2987 }
2988 } else if (left->is_double_cpu()) {
2989 Register lo = left->as_register_lo();
2990 Register hi = left->as_register_hi();
2991 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2992 #ifdef _LP64
2993 switch (code) {
2994 case lir_shl: __ shlptr(lo); break;
2995 case lir_shr: __ sarptr(lo); break;
2996 case lir_ushr: __ shrptr(lo); break;
2997 default: ShouldNotReachHere();
2998 }
2999 #else
3000
3001 switch (code) {
3002 case lir_shl: __ lshl(hi, lo); break;
3003 case lir_shr: __ lshr(hi, lo, true); break;
3004 case lir_ushr: __ lshr(hi, lo, false); break;
3005 default: ShouldNotReachHere();
3006 }
3007 #endif // LP64
3008 } else {
3009 ShouldNotReachHere();
3010 }
3011 }
3012
3013
3014 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3015 if (dest->is_single_cpu()) {
3016 // first move left into dest so that left is not destroyed by the shift
3017 Register value = dest->as_register();
3018 count = count & 0x1F; // Java spec
3019
3020 move_regs(left->as_register(), value);
3021 switch (code) {
3022 case lir_shl: __ shll(value, count); break;
3023 case lir_shr: __ sarl(value, count); break;
3024 case lir_ushr: __ shrl(value, count); break;
3025 default: ShouldNotReachHere();
3026 }
3027 } else if (dest->is_double_cpu()) {
3028 #ifndef _LP64
3029 Unimplemented();
3030 #else
3031 // first move left into dest so that left is not destroyed by the shift
3032 Register value = dest->as_register_lo();
3033 count = count & 0x1F; // Java spec
3034
3035 move_regs(left->as_register_lo(), value);
3036 switch (code) {
3037 case lir_shl: __ shlptr(value, count); break;
3038 case lir_shr: __ sarptr(value, count); break;
3039 case lir_ushr: __ shrptr(value, count); break;
3040 default: ShouldNotReachHere();
3041 }
3042 #endif // _LP64
3043 } else {
3044 ShouldNotReachHere();
3045 }
3046 }
3047
3048
3049 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3050 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3051 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3052 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3053 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3054 }
3055
3056
3057 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3058 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3059 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3060 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3061 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3062 }
3063
3064
3065 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3066 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3067 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3068 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3069 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3070 }
3071
3072
3073 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3074 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3075 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3076 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3077 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3078 }
3079
3080
3081 void LIR_Assembler::arraycopy_flat_check(Register obj, Register tmp, CodeStub* slow_path) {
3082 Address klass_addr = Address(obj, oopDesc::klass_offset_in_bytes());
3083 if (UseCompressedClassPointers) {
3084 __ movl(tmp, klass_addr);
3085 LP64_ONLY(__ decode_klass_not_null(tmp));
3086 } else {
3087 __ movptr(tmp, klass_addr);
3088 }
3089 __ movl(tmp, Address(tmp, Klass::layout_helper_offset()));
3090 __ sarl(tmp, Klass::_lh_array_tag_shift);
3091 __ cmpl(tmp, Klass::_lh_array_tag_vt_value);
3092 __ jcc(Assembler::equal, *slow_path->entry());
3093 }
3094
3095
3096 // This code replaces a call to arraycopy; no exception may
3097 // be thrown in this code, they must be thrown in the System.arraycopy
3098 // activation frame; we could save some checks if this would not be the case
3099 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3100 ciArrayKlass* default_type = op->expected_type();
3101 Register src = op->src()->as_register();
3102 Register dst = op->dst()->as_register();
3103 Register src_pos = op->src_pos()->as_register();
3104 Register dst_pos = op->dst_pos()->as_register();
3105 Register length = op->length()->as_register();
3106 Register tmp = op->tmp()->as_register();
3107
3108 __ resolve(ACCESS_READ, src);
3109 __ resolve(ACCESS_WRITE, dst);
3110
3111 CodeStub* stub = op->stub();
3112 int flags = op->flags();
3113 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3114 if (basic_type == T_ARRAY || basic_type == T_VALUETYPE) basic_type = T_OBJECT;
3115
3116 if (flags & LIR_OpArrayCopy::always_slow_path) {
3117 __ jmp(*stub->entry());
3118 __ bind(*stub->continuation());
3119 return;
3120 }
3121
3122 if (flags & LIR_OpArrayCopy::src_flat_check) {
3123 arraycopy_flat_check(src, tmp, stub);
3124 }
3125
3126 if (flags & LIR_OpArrayCopy::dst_flat_check) {
3127 arraycopy_flat_check(dst, tmp, stub);
3128 }
3129
3130 // if we don't know anything, just go through the generic arraycopy
3131 if (default_type == NULL) {
3132 // save outgoing arguments on stack in case call to System.arraycopy is needed
3133 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3134 // for interpreter calling conventions. Now we have to do it in new style conventions.
3135 // For the moment until C1 gets the new register allocator I just force all the
3136 // args to the right place (except the register args) and then on the back side
3137 // reload the register args properly if we go slow path. Yuck
3138
3139 // These are proper for the calling convention
3140 store_parameter(length, 2);
3141 store_parameter(dst_pos, 1);
3142 store_parameter(dst, 0);
3143
3144 // these are just temporary placements until we need to reload
3145 store_parameter(src_pos, 3);
3146 store_parameter(src, 4);
3147 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3148
3149 address copyfunc_addr = StubRoutines::generic_arraycopy();
3150 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3151
3152 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3153 #ifdef _LP64
3154 // The arguments are in java calling convention so we can trivially shift them to C
3155 // convention
3156 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3157 __ mov(c_rarg0, j_rarg0);
3158 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3159 __ mov(c_rarg1, j_rarg1);
3160 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3161 __ mov(c_rarg2, j_rarg2);
3162 assert_different_registers(c_rarg3, j_rarg4);
3163 __ mov(c_rarg3, j_rarg3);
3164 #ifdef _WIN64
3165 // Allocate abi space for args but be sure to keep stack aligned
3166 __ subptr(rsp, 6*wordSize);
3167 store_parameter(j_rarg4, 4);
3168 #ifndef PRODUCT
3169 if (PrintC1Statistics) {
3170 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3171 }
3172 #endif
3173 __ call(RuntimeAddress(copyfunc_addr));
3174 __ addptr(rsp, 6*wordSize);
3175 #else
3176 __ mov(c_rarg4, j_rarg4);
3177 #ifndef PRODUCT
3178 if (PrintC1Statistics) {
3179 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3180 }
3181 #endif
3182 __ call(RuntimeAddress(copyfunc_addr));
3183 #endif // _WIN64
3184 #else
3185 __ push(length);
3186 __ push(dst_pos);
3187 __ push(dst);
3188 __ push(src_pos);
3189 __ push(src);
3190
3191 #ifndef PRODUCT
3192 if (PrintC1Statistics) {
3193 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3194 }
3195 #endif
3196 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3197
3198 #endif // _LP64
3199
3200 __ cmpl(rax, 0);
3201 __ jcc(Assembler::equal, *stub->continuation());
3202
3203 __ mov(tmp, rax);
3204 __ xorl(tmp, -1);
3205
3206 // Reload values from the stack so they are where the stub
3207 // expects them.
3208 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3209 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3210 __ movptr (length, Address(rsp, 2*BytesPerWord));
3211 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3212 __ movptr (src, Address(rsp, 4*BytesPerWord));
3213
3214 __ subl(length, tmp);
3215 __ addl(src_pos, tmp);
3216 __ addl(dst_pos, tmp);
3217 __ jmp(*stub->entry());
3218
3219 __ bind(*stub->continuation());
3220 return;
3221 }
3222
3223 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3224
3225 int elem_size = type2aelembytes(basic_type);
3226 Address::ScaleFactor scale;
3227
3228 switch (elem_size) {
3229 case 1 :
3230 scale = Address::times_1;
3231 break;
3232 case 2 :
3233 scale = Address::times_2;
3234 break;
3235 case 4 :
3236 scale = Address::times_4;
3237 break;
3238 case 8 :
3239 scale = Address::times_8;
3240 break;
3241 default:
3242 scale = Address::no_scale;
3243 ShouldNotReachHere();
3244 }
3245
3246 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3247 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3248 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3249 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3250
3251 // length and pos's are all sign extended at this point on 64bit
3252
3253 // test for NULL
3254 if (flags & LIR_OpArrayCopy::src_null_check) {
3255 __ testptr(src, src);
3256 __ jcc(Assembler::zero, *stub->entry());
3257 }
3258 if (flags & LIR_OpArrayCopy::dst_null_check) {
3259 __ testptr(dst, dst);
3260 __ jcc(Assembler::zero, *stub->entry());
3261 }
3262
3263 // If the compiler was not able to prove that exact type of the source or the destination
3264 // of the arraycopy is an array type, check at runtime if the source or the destination is
3265 // an instance type.
3266 if (flags & LIR_OpArrayCopy::type_check) {
3267 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3268 __ load_klass(tmp, dst);
3269 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3270 __ jcc(Assembler::greaterEqual, *stub->entry());
3271 }
3272
3273 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3274 __ load_klass(tmp, src);
3275 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3276 __ jcc(Assembler::greaterEqual, *stub->entry());
3277 }
3278 }
3279
3280 // check if negative
3281 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3282 __ testl(src_pos, src_pos);
3283 __ jcc(Assembler::less, *stub->entry());
3284 }
3285 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3286 __ testl(dst_pos, dst_pos);
3287 __ jcc(Assembler::less, *stub->entry());
3288 }
3289
3290 if (flags & LIR_OpArrayCopy::src_range_check) {
3291 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3292 __ cmpl(tmp, src_length_addr);
3293 __ jcc(Assembler::above, *stub->entry());
3294 }
3295 if (flags & LIR_OpArrayCopy::dst_range_check) {
3296 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3297 __ cmpl(tmp, dst_length_addr);
3298 __ jcc(Assembler::above, *stub->entry());
3299 }
3300
3301 if (flags & LIR_OpArrayCopy::length_positive_check) {
3302 __ testl(length, length);
3303 __ jcc(Assembler::less, *stub->entry());
3304 }
3305
3306 #ifdef _LP64
3307 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3308 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3309 #endif
3310
3311 if (flags & LIR_OpArrayCopy::type_check) {
3312 // We don't know the array types are compatible
3313 if (basic_type != T_OBJECT) {
3314 // Simple test for basic type arrays
3315 if (UseCompressedClassPointers) {
3316 __ movl(tmp, src_klass_addr);
3317 __ cmpl(tmp, dst_klass_addr);
3318 } else {
3319 __ movptr(tmp, src_klass_addr);
3320 __ cmpptr(tmp, dst_klass_addr);
3321 }
3322 __ jcc(Assembler::notEqual, *stub->entry());
3323 } else {
3324 // For object arrays, if src is a sub class of dst then we can
3325 // safely do the copy.
3326 Label cont, slow;
3327
3328 __ push(src);
3329 __ push(dst);
3330
3331 __ load_klass(src, src);
3332 __ load_klass(dst, dst);
3333
3334 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3335
3336 __ push(src);
3337 __ push(dst);
3338 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3339 __ pop(dst);
3340 __ pop(src);
3341
3342 __ cmpl(src, 0);
3343 __ jcc(Assembler::notEqual, cont);
3344
3345 __ bind(slow);
3346 __ pop(dst);
3347 __ pop(src);
3348
3349 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3350 if (copyfunc_addr != NULL) { // use stub if available
3351 // src is not a sub class of dst so we have to do a
3352 // per-element check.
3353
3354 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3355 if ((flags & mask) != mask) {
3356 // Check that at least both of them object arrays.
3357 assert(flags & mask, "one of the two should be known to be an object array");
3358
3359 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3360 __ load_klass(tmp, src);
3361 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3362 __ load_klass(tmp, dst);
3363 }
3364 int lh_offset = in_bytes(Klass::layout_helper_offset());
3365 Address klass_lh_addr(tmp, lh_offset);
3366 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3367 __ cmpl(klass_lh_addr, objArray_lh);
3368 __ jcc(Assembler::notEqual, *stub->entry());
3369 }
3370
3371 // Spill because stubs can use any register they like and it's
3372 // easier to restore just those that we care about.
3373 store_parameter(dst, 0);
3374 store_parameter(dst_pos, 1);
3375 store_parameter(length, 2);
3376 store_parameter(src_pos, 3);
3377 store_parameter(src, 4);
3378
3379 #ifndef _LP64
3380 __ movptr(tmp, dst_klass_addr);
3381 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3382 __ push(tmp);
3383 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3384 __ push(tmp);
3385 __ push(length);
3386 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3387 __ push(tmp);
3388 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3389 __ push(tmp);
3390
3391 __ call_VM_leaf(copyfunc_addr, 5);
3392 #else
3393 __ movl2ptr(length, length); //higher 32bits must be null
3394
3395 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3396 assert_different_registers(c_rarg0, dst, dst_pos, length);
3397 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3398 assert_different_registers(c_rarg1, dst, length);
3399
3400 __ mov(c_rarg2, length);
3401 assert_different_registers(c_rarg2, dst);
3402
3403 #ifdef _WIN64
3404 // Allocate abi space for args but be sure to keep stack aligned
3405 __ subptr(rsp, 6*wordSize);
3406 __ load_klass(c_rarg3, dst);
3407 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3408 store_parameter(c_rarg3, 4);
3409 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3410 __ call(RuntimeAddress(copyfunc_addr));
3411 __ addptr(rsp, 6*wordSize);
3412 #else
3413 __ load_klass(c_rarg4, dst);
3414 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3415 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3416 __ call(RuntimeAddress(copyfunc_addr));
3417 #endif
3418
3419 #endif
3420
3421 #ifndef PRODUCT
3422 if (PrintC1Statistics) {
3423 Label failed;
3424 __ testl(rax, rax);
3425 __ jcc(Assembler::notZero, failed);
3426 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3427 __ bind(failed);
3428 }
3429 #endif
3430
3431 __ testl(rax, rax);
3432 __ jcc(Assembler::zero, *stub->continuation());
3433
3434 #ifndef PRODUCT
3435 if (PrintC1Statistics) {
3436 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3437 }
3438 #endif
3439
3440 __ mov(tmp, rax);
3441
3442 __ xorl(tmp, -1);
3443
3444 // Restore previously spilled arguments
3445 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3446 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3447 __ movptr (length, Address(rsp, 2*BytesPerWord));
3448 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3449 __ movptr (src, Address(rsp, 4*BytesPerWord));
3450
3451
3452 __ subl(length, tmp);
3453 __ addl(src_pos, tmp);
3454 __ addl(dst_pos, tmp);
3455 }
3456
3457 __ jmp(*stub->entry());
3458
3459 __ bind(cont);
3460 __ pop(dst);
3461 __ pop(src);
3462 }
3463 }
3464
3465 #ifdef ASSERT
3466 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3467 // Sanity check the known type with the incoming class. For the
3468 // primitive case the types must match exactly with src.klass and
3469 // dst.klass each exactly matching the default type. For the
3470 // object array case, if no type check is needed then either the
3471 // dst type is exactly the expected type and the src type is a
3472 // subtype which we can't check or src is the same array as dst
3473 // but not necessarily exactly of type default_type.
3474 Label known_ok, halt;
3475 __ mov_metadata(tmp, default_type->constant_encoding());
3476 #ifdef _LP64
3477 if (UseCompressedClassPointers) {
3478 __ encode_klass_not_null(tmp);
3479 }
3480 #endif
3481
3482 if (basic_type != T_OBJECT) {
3483
3484 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3485 else __ cmpptr(tmp, dst_klass_addr);
3486 __ jcc(Assembler::notEqual, halt);
3487 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3488 else __ cmpptr(tmp, src_klass_addr);
3489 __ jcc(Assembler::equal, known_ok);
3490 } else {
3491 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3492 else __ cmpptr(tmp, dst_klass_addr);
3493 __ jcc(Assembler::equal, known_ok);
3494 __ cmpptr(src, dst);
3495 __ jcc(Assembler::equal, known_ok);
3496 }
3497 __ bind(halt);
3498 __ stop("incorrect type information in arraycopy");
3499 __ bind(known_ok);
3500 }
3501 #endif
3502
3503 #ifndef PRODUCT
3504 if (PrintC1Statistics) {
3505 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3506 }
3507 #endif
3508
3509 #ifdef _LP64
3510 assert_different_registers(c_rarg0, dst, dst_pos, length);
3511 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3512 assert_different_registers(c_rarg1, length);
3513 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3514 __ mov(c_rarg2, length);
3515
3516 #else
3517 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3518 store_parameter(tmp, 0);
3519 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3520 store_parameter(tmp, 1);
3521 store_parameter(length, 2);
3522 #endif // _LP64
3523
3524 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3525 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3526 const char *name;
3527 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3528 __ call_VM_leaf(entry, 0);
3529
3530 __ bind(*stub->continuation());
3531 }
3532
3533 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3534 assert(op->crc()->is_single_cpu(), "crc must be register");
3535 assert(op->val()->is_single_cpu(), "byte value must be register");
3536 assert(op->result_opr()->is_single_cpu(), "result must be register");
3537 Register crc = op->crc()->as_register();
3538 Register val = op->val()->as_register();
3539 Register res = op->result_opr()->as_register();
3540
3541 assert_different_registers(val, crc, res);
3542
3543 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3544 __ notl(crc); // ~crc
3545 __ update_byte_crc32(crc, val, res);
3546 __ notl(crc); // ~crc
3547 __ mov(res, crc);
3548 }
3549
3550 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3551 Register obj = op->obj_opr()->as_register(); // may not be an oop
3552 Register hdr = op->hdr_opr()->as_register();
3553 Register lock = op->lock_opr()->as_register();
3554 if (!UseFastLocking) {
3555 __ jmp(*op->stub()->entry());
3556 } else if (op->code() == lir_lock) {
3557 Register scratch = noreg;
3558 if (UseBiasedLocking) {
3559 scratch = op->scratch_opr()->as_register();
3560 }
3561 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3562 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3563 // add debug info for NullPointerException only if one is possible
3564 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3565 if (op->info() != NULL) {
3566 add_debug_info_for_null_check(null_check_offset, op->info());
3567 }
3568 // done
3569 } else if (op->code() == lir_unlock) {
3570 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3571 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3572 } else {
3573 Unimplemented();
3574 }
3575 __ bind(*op->stub()->continuation());
3576 }
3577
3578
3579 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3580 ciMethod* method = op->profiled_method();
3581 int bci = op->profiled_bci();
3582 ciMethod* callee = op->profiled_callee();
3583
3584 // Update counter for all call types
3585 ciMethodData* md = method->method_data_or_null();
3586 assert(md != NULL, "Sanity");
3587 ciProfileData* data = md->bci_to_data(bci);
3588 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3589 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3590 Register mdo = op->mdo()->as_register();
3591 __ mov_metadata(mdo, md->constant_encoding());
3592 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3593 // Perform additional virtual call profiling for invokevirtual and
3594 // invokeinterface bytecodes
3595 if (op->should_profile_receiver_type()) {
3596 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3597 Register recv = op->recv()->as_register();
3598 assert_different_registers(mdo, recv);
3599 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3600 ciKlass* known_klass = op->known_holder();
3601 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3602 // We know the type that will be seen at this call site; we can
3603 // statically update the MethodData* rather than needing to do
3604 // dynamic tests on the receiver type
3605
3606 // NOTE: we should probably put a lock around this search to
3607 // avoid collisions by concurrent compilations
3608 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3609 uint i;
3610 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3611 ciKlass* receiver = vc_data->receiver(i);
3612 if (known_klass->equals(receiver)) {
3613 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3614 __ addptr(data_addr, DataLayout::counter_increment);
3615 return;
3616 }
3617 }
3618
3619 // Receiver type not found in profile data; select an empty slot
3620
3621 // Note that this is less efficient than it should be because it
3622 // always does a write to the receiver part of the
3623 // VirtualCallData rather than just the first time
3624 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3625 ciKlass* receiver = vc_data->receiver(i);
3626 if (receiver == NULL) {
3627 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3628 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3629 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3630 __ addptr(data_addr, DataLayout::counter_increment);
3631 return;
3632 }
3633 }
3634 } else {
3635 __ load_klass(recv, recv);
3636 Label update_done;
3637 type_profile_helper(mdo, md, data, recv, &update_done);
3638 // Receiver did not match any saved receiver and there is no empty row for it.
3639 // Increment total counter to indicate polymorphic case.
3640 __ addptr(counter_addr, DataLayout::counter_increment);
3641
3642 __ bind(update_done);
3643 }
3644 } else {
3645 // Static call
3646 __ addptr(counter_addr, DataLayout::counter_increment);
3647 }
3648 }
3649
3650 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3651 Register obj = op->obj()->as_register();
3652 Register tmp = op->tmp()->as_pointer_register();
3653 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3654 ciKlass* exact_klass = op->exact_klass();
3655 intptr_t current_klass = op->current_klass();
3656 bool not_null = op->not_null();
3657 bool no_conflict = op->no_conflict();
3658
3659 Label update, next, none;
3660
3661 bool do_null = !not_null;
3662 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3663 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3664
3665 assert(do_null || do_update, "why are we here?");
3666 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3667
3668 __ verify_oop(obj);
3669
3670 if (tmp != obj) {
3671 __ mov(tmp, obj);
3672 }
3673 if (do_null) {
3674 __ testptr(tmp, tmp);
3675 __ jccb(Assembler::notZero, update);
3676 if (!TypeEntries::was_null_seen(current_klass)) {
3677 __ orptr(mdo_addr, TypeEntries::null_seen);
3678 }
3679 if (do_update) {
3680 #ifndef ASSERT
3681 __ jmpb(next);
3682 }
3683 #else
3684 __ jmp(next);
3685 }
3686 } else {
3687 __ testptr(tmp, tmp);
3688 __ jcc(Assembler::notZero, update);
3689 __ stop("unexpect null obj");
3690 #endif
3691 }
3692
3693 __ bind(update);
3694
3695 if (do_update) {
3696 #ifdef ASSERT
3697 if (exact_klass != NULL) {
3698 Label ok;
3699 __ load_klass(tmp, tmp);
3700 __ push(tmp);
3701 __ mov_metadata(tmp, exact_klass->constant_encoding());
3702 __ cmpptr(tmp, Address(rsp, 0));
3703 __ jcc(Assembler::equal, ok);
3704 __ stop("exact klass and actual klass differ");
3705 __ bind(ok);
3706 __ pop(tmp);
3707 }
3708 #endif
3709 if (!no_conflict) {
3710 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3711 if (exact_klass != NULL) {
3712 __ mov_metadata(tmp, exact_klass->constant_encoding());
3713 } else {
3714 __ load_klass(tmp, tmp);
3715 }
3716
3717 __ xorptr(tmp, mdo_addr);
3718 __ testptr(tmp, TypeEntries::type_klass_mask);
3719 // klass seen before, nothing to do. The unknown bit may have been
3720 // set already but no need to check.
3721 __ jccb(Assembler::zero, next);
3722
3723 __ testptr(tmp, TypeEntries::type_unknown);
3724 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3725
3726 if (TypeEntries::is_type_none(current_klass)) {
3727 __ cmpptr(mdo_addr, 0);
3728 __ jccb(Assembler::equal, none);
3729 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3730 __ jccb(Assembler::equal, none);
3731 // There is a chance that the checks above (re-reading profiling
3732 // data from memory) fail if another thread has just set the
3733 // profiling to this obj's klass
3734 __ xorptr(tmp, mdo_addr);
3735 __ testptr(tmp, TypeEntries::type_klass_mask);
3736 __ jccb(Assembler::zero, next);
3737 }
3738 } else {
3739 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3740 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3741
3742 __ movptr(tmp, mdo_addr);
3743 __ testptr(tmp, TypeEntries::type_unknown);
3744 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3745 }
3746
3747 // different than before. Cannot keep accurate profile.
3748 __ orptr(mdo_addr, TypeEntries::type_unknown);
3749
3750 if (TypeEntries::is_type_none(current_klass)) {
3751 __ jmpb(next);
3752
3753 __ bind(none);
3754 // first time here. Set profile type.
3755 __ movptr(mdo_addr, tmp);
3756 }
3757 } else {
3758 // There's a single possible klass at this profile point
3759 assert(exact_klass != NULL, "should be");
3760 if (TypeEntries::is_type_none(current_klass)) {
3761 __ mov_metadata(tmp, exact_klass->constant_encoding());
3762 __ xorptr(tmp, mdo_addr);
3763 __ testptr(tmp, TypeEntries::type_klass_mask);
3764 #ifdef ASSERT
3765 __ jcc(Assembler::zero, next);
3766
3767 {
3768 Label ok;
3769 __ push(tmp);
3770 __ cmpptr(mdo_addr, 0);
3771 __ jcc(Assembler::equal, ok);
3772 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3773 __ jcc(Assembler::equal, ok);
3774 // may have been set by another thread
3775 __ mov_metadata(tmp, exact_klass->constant_encoding());
3776 __ xorptr(tmp, mdo_addr);
3777 __ testptr(tmp, TypeEntries::type_mask);
3778 __ jcc(Assembler::zero, ok);
3779
3780 __ stop("unexpected profiling mismatch");
3781 __ bind(ok);
3782 __ pop(tmp);
3783 }
3784 #else
3785 __ jccb(Assembler::zero, next);
3786 #endif
3787 // first time here. Set profile type.
3788 __ movptr(mdo_addr, tmp);
3789 } else {
3790 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3791 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3792
3793 __ movptr(tmp, mdo_addr);
3794 __ testptr(tmp, TypeEntries::type_unknown);
3795 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3796
3797 __ orptr(mdo_addr, TypeEntries::type_unknown);
3798 }
3799 }
3800
3801 __ bind(next);
3802 }
3803 }
3804
3805 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3806 Unimplemented();
3807 }
3808
3809
3810 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3811 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3812 }
3813
3814
3815 void LIR_Assembler::align_backward_branch_target() {
3816 __ align(BytesPerWord);
3817 }
3818
3819
3820 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3821 if (left->is_single_cpu()) {
3822 __ negl(left->as_register());
3823 move_regs(left->as_register(), dest->as_register());
3824
3825 } else if (left->is_double_cpu()) {
3826 Register lo = left->as_register_lo();
3827 #ifdef _LP64
3828 Register dst = dest->as_register_lo();
3829 __ movptr(dst, lo);
3830 __ negptr(dst);
3831 #else
3832 Register hi = left->as_register_hi();
3833 __ lneg(hi, lo);
3834 if (dest->as_register_lo() == hi) {
3835 assert(dest->as_register_hi() != lo, "destroying register");
3836 move_regs(hi, dest->as_register_hi());
3837 move_regs(lo, dest->as_register_lo());
3838 } else {
3839 move_regs(lo, dest->as_register_lo());
3840 move_regs(hi, dest->as_register_hi());
3841 }
3842 #endif // _LP64
3843
3844 } else if (dest->is_single_xmm()) {
3845 #ifdef _LP64
3846 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3847 assert(tmp->is_valid(), "need temporary");
3848 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3849 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3850 }
3851 else
3852 #endif
3853 {
3854 assert(!tmp->is_valid(), "do not need temporary");
3855 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3856 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3857 }
3858 __ xorps(dest->as_xmm_float_reg(),
3859 ExternalAddress((address)float_signflip_pool));
3860 }
3861 } else if (dest->is_double_xmm()) {
3862 #ifdef _LP64
3863 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3864 assert(tmp->is_valid(), "need temporary");
3865 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3866 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3867 }
3868 else
3869 #endif
3870 {
3871 assert(!tmp->is_valid(), "do not need temporary");
3872 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3873 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3874 }
3875 __ xorpd(dest->as_xmm_double_reg(),
3876 ExternalAddress((address)double_signflip_pool));
3877 }
3878 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3879 assert(left->fpu() == 0, "arg must be on TOS");
3880 assert(dest->fpu() == 0, "dest must be TOS");
3881 __ fchs();
3882
3883 } else {
3884 ShouldNotReachHere();
3885 }
3886 }
3887
3888
3889 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3890 assert(src->is_address(), "must be an address");
3891 assert(dest->is_register(), "must be a register");
3892
3893 PatchingStub* patch = NULL;
3894 if (patch_code != lir_patch_none) {
3895 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3896 }
3897
3898 Register reg = dest->as_pointer_register();
3899 LIR_Address* addr = src->as_address_ptr();
3900 __ lea(reg, as_Address(addr));
3901
3902 if (patch != NULL) {
3903 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3904 }
3905 }
3906
3907
3908
3909 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3910 assert(!tmp->is_valid(), "don't need temporary");
3911 __ call(RuntimeAddress(dest));
3912 if (info != NULL) {
3913 add_call_info_here(info);
3914 }
3915 }
3916
3917
3918 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3919 assert(type == T_LONG, "only for volatile long fields");
3920
3921 if (info != NULL) {
3922 add_debug_info_for_null_check_here(info);
3923 }
3924
3925 if (src->is_double_xmm()) {
3926 if (dest->is_double_cpu()) {
3927 #ifdef _LP64
3928 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3929 #else
3930 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3931 __ psrlq(src->as_xmm_double_reg(), 32);
3932 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3933 #endif // _LP64
3934 } else if (dest->is_double_stack()) {
3935 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3936 } else if (dest->is_address()) {
3937 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3938 } else {
3939 ShouldNotReachHere();
3940 }
3941
3942 } else if (dest->is_double_xmm()) {
3943 if (src->is_double_stack()) {
3944 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3945 } else if (src->is_address()) {
3946 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3947 } else {
3948 ShouldNotReachHere();
3949 }
3950
3951 } else if (src->is_double_fpu()) {
3952 assert(src->fpu_regnrLo() == 0, "must be TOS");
3953 if (dest->is_double_stack()) {
3954 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3955 } else if (dest->is_address()) {
3956 __ fistp_d(as_Address(dest->as_address_ptr()));
3957 } else {
3958 ShouldNotReachHere();
3959 }
3960
3961 } else if (dest->is_double_fpu()) {
3962 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3963 if (src->is_double_stack()) {
3964 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3965 } else if (src->is_address()) {
3966 __ fild_d(as_Address(src->as_address_ptr()));
3967 } else {
3968 ShouldNotReachHere();
3969 }
3970 } else {
3971 ShouldNotReachHere();
3972 }
3973 }
3974
3975 #ifdef ASSERT
3976 // emit run-time assertion
3977 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3978 assert(op->code() == lir_assert, "must be");
3979
3980 if (op->in_opr1()->is_valid()) {
3981 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3982 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3983 } else {
3984 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3985 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3986 }
3987
3988 Label ok;
3989 if (op->condition() != lir_cond_always) {
3990 Assembler::Condition acond = Assembler::zero;
3991 switch (op->condition()) {
3992 case lir_cond_equal: acond = Assembler::equal; break;
3993 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3994 case lir_cond_less: acond = Assembler::less; break;
3995 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3996 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3997 case lir_cond_greater: acond = Assembler::greater; break;
3998 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3999 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
4000 default: ShouldNotReachHere();
4001 }
4002 __ jcc(acond, ok);
4003 }
4004 if (op->halt()) {
4005 const char* str = __ code_string(op->msg());
4006 __ stop(str);
4007 } else {
4008 breakpoint();
4009 }
4010 __ bind(ok);
4011 }
4012 #endif
4013
4014 void LIR_Assembler::membar() {
4015 // QQQ sparc TSO uses this,
4016 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4017 }
4018
4019 void LIR_Assembler::membar_acquire() {
4020 // No x86 machines currently require load fences
4021 }
4022
4023 void LIR_Assembler::membar_release() {
4024 // No x86 machines currently require store fences
4025 }
4026
4027 void LIR_Assembler::membar_loadload() {
4028 // no-op
4029 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4030 }
4031
4032 void LIR_Assembler::membar_storestore() {
4033 // no-op
4034 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4035 }
4036
4037 void LIR_Assembler::membar_loadstore() {
4038 // no-op
4039 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4040 }
4041
4042 void LIR_Assembler::membar_storeload() {
4043 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4044 }
4045
4046 void LIR_Assembler::on_spin_wait() {
4047 __ pause ();
4048 }
4049
4050 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4051 assert(result_reg->is_register(), "check");
4052 #ifdef _LP64
4053 // __ get_thread(result_reg->as_register_lo());
4054 __ mov(result_reg->as_register(), r15_thread);
4055 #else
4056 __ get_thread(result_reg->as_register());
4057 #endif // _LP64
4058 }
4059
4060
4061 void LIR_Assembler::peephole(LIR_List*) {
4062 // do nothing for now
4063 }
4064
4065 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4066 assert(data == dest, "xchg/xadd uses only 2 operands");
4067
4068 if (data->type() == T_INT) {
4069 if (code == lir_xadd) {
4070 __ lock();
4071 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4072 } else {
4073 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4074 }
4075 } else if (data->is_oop()) {
4076 assert (code == lir_xchg, "xadd for oops");
4077 Register obj = data->as_register();
4078 #ifdef _LP64
4079 if (UseCompressedOops) {
4080 __ encode_heap_oop(obj);
4081 __ xchgl(obj, as_Address(src->as_address_ptr()));
4082 __ decode_heap_oop(obj);
4083 } else {
4084 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4085 }
4086 #else
4087 __ xchgl(obj, as_Address(src->as_address_ptr()));
4088 #endif
4089 } else if (data->type() == T_LONG) {
4090 #ifdef _LP64
4091 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4092 if (code == lir_xadd) {
4093 __ lock();
4094 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4095 } else {
4096 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4097 }
4098 #else
4099 ShouldNotReachHere();
4100 #endif
4101 } else {
4102 ShouldNotReachHere();
4103 }
4104 }
4105
4106 #undef __