1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31 #include "runtime/signature.hpp"
32
33 class ciValueKlass;
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42 friend class Runtime1; // as_Address()
43
44 public:
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments // the number of arguments to pop after the call
54 );
55
56 protected:
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 Address as_Address(AddressLiteral adr);
91 Address as_Address(ArrayAddress adr);
92
93 // Support for NULL-checks
94 //
95 // Generates code that causes a NULL OS exception if the content of reg is NULL.
96 // If the accessed location is M[reg + offset] and the offset is known, provide the
97 // offset. No explicit code generation is needed if the offset is within a certain
98 // range (0 <= offset <= page_size).
99
100 void null_check(Register reg, int offset = -1);
101 static bool needs_explicit_null_check(intptr_t offset);
102 static bool uses_implicit_null_check(void* address);
103
104 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
105
106 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
107 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
108 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
109
110 // Check oops array storage properties, i.e. flattened and/or null-free
111 void test_flattened_array_oop(Register oop, Register temp_reg, Label&is_flattened_array);
112 void test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array);
113
114 // Required platform-specific helpers for Label::patch_instructions.
115 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
116 void pd_patch_instruction(address branch, address target, const char* file, int line) {
117 unsigned char op = branch[0];
118 assert(op == 0xE8 /* call */ ||
119 op == 0xE9 /* jmp */ ||
120 op == 0xEB /* short jmp */ ||
121 (op & 0xF0) == 0x70 /* short jcc */ ||
122 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
123 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
124 "Invalid opcode at patch point");
125
126 if (op == 0xEB || (op & 0xF0) == 0x70) {
127 // short offset operators (jmp and jcc)
128 char* disp = (char*) &branch[1];
129 int imm8 = target - (address) &disp[1];
130 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
131 *disp = imm8;
132 } else {
133 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
134 int imm32 = target - (address) &disp[1];
135 *disp = imm32;
136 }
137 }
138
139 // The following 4 methods return the offset of the appropriate move instruction
140
141 // Support for fast byte/short loading with zero extension (depending on particular CPU)
142 int load_unsigned_byte(Register dst, Address src);
143 int load_unsigned_short(Register dst, Address src);
144
145 // Support for fast byte/short loading with sign extension (depending on particular CPU)
146 int load_signed_byte(Register dst, Address src);
147 int load_signed_short(Register dst, Address src);
148
149 // Support for sign-extension (hi:lo = extend_sign(lo))
150 void extend_sign(Register hi, Register lo);
151
152 // Load and store values by size and signed-ness
153 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
154 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
155
156 // Support for inc/dec with optimal instruction selection depending on value
157
158 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
159 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
160
161 void decrementl(Address dst, int value = 1);
162 void decrementl(Register reg, int value = 1);
163
164 void decrementq(Register reg, int value = 1);
165 void decrementq(Address dst, int value = 1);
166
167 void incrementl(Address dst, int value = 1);
168 void incrementl(Register reg, int value = 1);
169
170 void incrementq(Register reg, int value = 1);
171 void incrementq(Address dst, int value = 1);
172
173 #ifdef COMPILER2
174 // special instructions for EVEX
175 void setvectmask(Register dst, Register src);
176 void restorevectmask();
177 #endif
178
179 // Support optimal SSE move instructions.
180 void movflt(XMMRegister dst, XMMRegister src) {
181 if (dst-> encoding() == src->encoding()) return;
182 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
183 else { movss (dst, src); return; }
184 }
185 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
186 void movflt(XMMRegister dst, AddressLiteral src);
187 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
188
189 void movdbl(XMMRegister dst, XMMRegister src) {
190 if (dst-> encoding() == src->encoding()) return;
191 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
192 else { movsd (dst, src); return; }
193 }
194
195 void movdbl(XMMRegister dst, AddressLiteral src);
196
197 void movdbl(XMMRegister dst, Address src) {
198 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
199 else { movlpd(dst, src); return; }
200 }
201 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
202
203 void incrementl(AddressLiteral dst);
204 void incrementl(ArrayAddress dst);
205
206 void incrementq(AddressLiteral dst);
207
208 // Alignment
209 void align(int modulus);
210 void align(int modulus, int target);
211
212 // A 5 byte nop that is safe for patching (see patch_verified_entry)
213 void fat_nop();
214
215 // Stack frame creation/removal
216 void enter();
217 void leave();
218
219 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
220 // The pointer will be loaded into the thread register.
221 void get_thread(Register thread);
222
223
224 // Support for VM calls
225 //
226 // It is imperative that all calls into the VM are handled via the call_VM macros.
227 // They make sure that the stack linkage is setup correctly. call_VM's correspond
228 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
229
230
231 void call_VM(Register oop_result,
232 address entry_point,
233 bool check_exceptions = true);
234 void call_VM(Register oop_result,
235 address entry_point,
236 Register arg_1,
237 bool check_exceptions = true);
238 void call_VM(Register oop_result,
239 address entry_point,
240 Register arg_1, Register arg_2,
241 bool check_exceptions = true);
242 void call_VM(Register oop_result,
243 address entry_point,
244 Register arg_1, Register arg_2, Register arg_3,
245 bool check_exceptions = true);
246
247 // Overloadings with last_Java_sp
248 void call_VM(Register oop_result,
249 Register last_java_sp,
250 address entry_point,
251 int number_of_arguments = 0,
252 bool check_exceptions = true);
253 void call_VM(Register oop_result,
254 Register last_java_sp,
255 address entry_point,
256 Register arg_1, bool
257 check_exceptions = true);
258 void call_VM(Register oop_result,
259 Register last_java_sp,
260 address entry_point,
261 Register arg_1, Register arg_2,
262 bool check_exceptions = true);
263 void call_VM(Register oop_result,
264 Register last_java_sp,
265 address entry_point,
266 Register arg_1, Register arg_2, Register arg_3,
267 bool check_exceptions = true);
268
269 void get_vm_result (Register oop_result, Register thread);
270 void get_vm_result_2(Register metadata_result, Register thread);
271
272 // These always tightly bind to MacroAssembler::call_VM_base
273 // bypassing the virtual implementation
274 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
275 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
276 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
277 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
278 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
279
280 void call_VM_leaf0(address entry_point);
281 void call_VM_leaf(address entry_point,
282 int number_of_arguments = 0);
283 void call_VM_leaf(address entry_point,
284 Register arg_1);
285 void call_VM_leaf(address entry_point,
286 Register arg_1, Register arg_2);
287 void call_VM_leaf(address entry_point,
288 Register arg_1, Register arg_2, Register arg_3);
289
290 // These always tightly bind to MacroAssembler::call_VM_leaf_base
291 // bypassing the virtual implementation
292 void super_call_VM_leaf(address entry_point);
293 void super_call_VM_leaf(address entry_point, Register arg_1);
294 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
295 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
296 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
297
298 // last Java Frame (fills frame anchor)
299 void set_last_Java_frame(Register thread,
300 Register last_java_sp,
301 Register last_java_fp,
302 address last_java_pc);
303
304 // thread in the default location (r15_thread on 64bit)
305 void set_last_Java_frame(Register last_java_sp,
306 Register last_java_fp,
307 address last_java_pc);
308
309 void reset_last_Java_frame(Register thread, bool clear_fp);
310
311 // thread in the default location (r15_thread on 64bit)
312 void reset_last_Java_frame(bool clear_fp);
313
314 // jobjects
315 void clear_jweak_tag(Register possibly_jweak);
316 void resolve_jobject(Register value, Register thread, Register tmp);
317
318 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
319 void c2bool(Register x);
320
321 // C++ bool manipulation
322
323 void movbool(Register dst, Address src);
324 void movbool(Address dst, bool boolconst);
325 void movbool(Address dst, Register src);
326 void testbool(Register dst);
327
328 void resolve_oop_handle(Register result, Register tmp = rscratch2);
329 void resolve_weak_handle(Register result, Register tmp);
330 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
331 void load_method_holder_cld(Register rresult, Register rmethod);
332
333 void load_method_holder(Register holder, Register method);
334
335 // oop manipulations
336 void load_metadata(Register dst, Register src);
337 void load_storage_props(Register dst, Register src);
338 void load_klass(Register dst, Register src);
339 void store_klass(Register dst, Register src);
340
341 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
342 Register tmp1, Register thread_tmp);
343 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
344 Register tmp1, Register tmp2, Register tmp3 = noreg);
345
346 // Resolves obj access. Result is placed in the same register.
347 // All other registers are preserved.
348 void resolve(DecoratorSet decorators, Register obj);
349
350 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
351 Register thread_tmp = noreg, DecoratorSet decorators = 0);
352 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
353 Register thread_tmp = noreg, DecoratorSet decorators = 0);
354 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
355 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
356
357 // Used for storing NULL. All other oop constants should be
358 // stored using routines that take a jobject.
359 void store_heap_oop_null(Address dst);
360
361 void load_prototype_header(Register dst, Register src);
362
363 #ifdef _LP64
364 void store_klass_gap(Register dst, Register src);
365
366 // This dummy is to prevent a call to store_heap_oop from
367 // converting a zero (like NULL) into a Register by giving
368 // the compiler two choices it can't resolve
369
370 void store_heap_oop(Address dst, void* dummy);
371
372 void encode_heap_oop(Register r);
373 void decode_heap_oop(Register r);
374 void encode_heap_oop_not_null(Register r);
375 void decode_heap_oop_not_null(Register r);
376 void encode_heap_oop_not_null(Register dst, Register src);
377 void decode_heap_oop_not_null(Register dst, Register src);
378
379 void set_narrow_oop(Register dst, jobject obj);
380 void set_narrow_oop(Address dst, jobject obj);
381 void cmp_narrow_oop(Register dst, jobject obj);
382 void cmp_narrow_oop(Address dst, jobject obj);
383
384 void encode_klass_not_null(Register r);
385 void decode_klass_not_null(Register r);
386 void encode_klass_not_null(Register dst, Register src);
387 void decode_klass_not_null(Register dst, Register src);
388 void set_narrow_klass(Register dst, Klass* k);
389 void set_narrow_klass(Address dst, Klass* k);
390 void cmp_narrow_klass(Register dst, Klass* k);
391 void cmp_narrow_klass(Address dst, Klass* k);
392
393 // Returns the byte size of the instructions generated by decode_klass_not_null()
394 // when compressed klass pointers are being used.
395 static int instr_size_for_decode_klass_not_null();
396
397 // if heap base register is used - reinit it with the correct value
398 void reinit_heapbase();
399
400 DEBUG_ONLY(void verify_heapbase(const char* msg);)
401
402 #endif // _LP64
403
404 // Int division/remainder for Java
405 // (as idivl, but checks for special case as described in JVM spec.)
406 // returns idivl instruction offset for implicit exception handling
407 int corrected_idivl(Register reg);
408
409 // Long division/remainder for Java
410 // (as idivq, but checks for special case as described in JVM spec.)
411 // returns idivq instruction offset for implicit exception handling
412 int corrected_idivq(Register reg);
413
414 void int3();
415
416 // Long operation macros for a 32bit cpu
417 // Long negation for Java
418 void lneg(Register hi, Register lo);
419
420 // Long multiplication for Java
421 // (destroys contents of eax, ebx, ecx and edx)
422 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
423
424 // Long shifts for Java
425 // (semantics as described in JVM spec.)
426 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
427 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
428
429 // Long compare for Java
430 // (semantics as described in JVM spec.)
431 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
432
433
434 // misc
435
436 // Sign extension
437 void sign_extend_short(Register reg);
438 void sign_extend_byte(Register reg);
439
440 // Division by power of 2, rounding towards 0
441 void division_with_shift(Register reg, int shift_value);
442
443 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
444 //
445 // CF (corresponds to C0) if x < y
446 // PF (corresponds to C2) if unordered
447 // ZF (corresponds to C3) if x = y
448 //
449 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
450 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
451 void fcmp(Register tmp);
452 // Variant of the above which allows y to be further down the stack
453 // and which only pops x and y if specified. If pop_right is
454 // specified then pop_left must also be specified.
455 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
456
457 // Floating-point comparison for Java
458 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
459 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
460 // (semantics as described in JVM spec.)
461 void fcmp2int(Register dst, bool unordered_is_less);
462 // Variant of the above which allows y to be further down the stack
463 // and which only pops x and y if specified. If pop_right is
464 // specified then pop_left must also be specified.
465 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
466
467 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
468 // tmp is a temporary register, if none is available use noreg
469 void fremr(Register tmp);
470
471 // dst = c = a * b + c
472 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
473 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
474
475 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
476 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
477 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
478 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
479
480
481 // same as fcmp2int, but using SSE2
482 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
483 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
484
485 // branch to L if FPU flag C2 is set/not set
486 // tmp is a temporary register, if none is available use noreg
487 void jC2 (Register tmp, Label& L);
488 void jnC2(Register tmp, Label& L);
489
490 // Pop ST (ffree & fincstp combined)
491 void fpop();
492
493 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
494 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
495 void load_float(Address src);
496
497 // Store float value to 'address'. If UseSSE >= 1, the value is stored
498 // from register xmm0. Otherwise, the value is stored from the FPU stack.
499 void store_float(Address dst);
500
501 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
502 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
503 void load_double(Address src);
504
505 // Store double value to 'address'. If UseSSE >= 2, the value is stored
506 // from register xmm0. Otherwise, the value is stored from the FPU stack.
507 void store_double(Address dst);
508
509 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
510 void push_fTOS();
511
512 // pops double TOS element from CPU stack and pushes on FPU stack
513 void pop_fTOS();
514
515 void empty_FPU_stack();
516
517 void push_IU_state();
518 void pop_IU_state();
519
520 void push_FPU_state();
521 void pop_FPU_state();
522
523 void push_CPU_state();
524 void pop_CPU_state();
525
526 // Round up to a power of two
527 void round_to(Register reg, int modulus);
528
529 // Callee saved registers handling
530 void push_callee_saved_registers();
531 void pop_callee_saved_registers();
532
533 // allocation
534 void eden_allocate(
535 Register thread, // Current thread
536 Register obj, // result: pointer to object after successful allocation
537 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
538 int con_size_in_bytes, // object size in bytes if known at compile time
539 Register t1, // temp register
540 Label& slow_case // continuation point if fast allocation fails
541 );
542 void tlab_allocate(
543 Register thread, // Current thread
544 Register obj, // result: pointer to object after successful allocation
545 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
546 int con_size_in_bytes, // object size in bytes if known at compile time
547 Register t1, // temp register
548 Register t2, // temp register
549 Label& slow_case // continuation point if fast allocation fails
550 );
551 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
552
553 // interface method calling
554 void lookup_interface_method(Register recv_klass,
555 Register intf_klass,
556 RegisterOrConstant itable_index,
557 Register method_result,
558 Register scan_temp,
559 Label& no_such_interface,
560 bool return_method = true);
561
562 // virtual method calling
563 void lookup_virtual_method(Register recv_klass,
564 RegisterOrConstant vtable_index,
565 Register method_result);
566
567 // Test sub_klass against super_klass, with fast and slow paths.
568
569 // The fast path produces a tri-state answer: yes / no / maybe-slow.
570 // One of the three labels can be NULL, meaning take the fall-through.
571 // If super_check_offset is -1, the value is loaded up from super_klass.
572 // No registers are killed, except temp_reg.
573 void check_klass_subtype_fast_path(Register sub_klass,
574 Register super_klass,
575 Register temp_reg,
576 Label* L_success,
577 Label* L_failure,
578 Label* L_slow_path,
579 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
580
581 // The rest of the type check; must be wired to a corresponding fast path.
582 // It does not repeat the fast path logic, so don't use it standalone.
583 // The temp_reg and temp2_reg can be noreg, if no temps are available.
584 // Updates the sub's secondary super cache as necessary.
585 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
586 void check_klass_subtype_slow_path(Register sub_klass,
587 Register super_klass,
588 Register temp_reg,
589 Register temp2_reg,
590 Label* L_success,
591 Label* L_failure,
592 bool set_cond_codes = false);
593
594 // Simplified, combined version, good for typical uses.
595 // Falls through on failure.
596 void check_klass_subtype(Register sub_klass,
597 Register super_klass,
598 Register temp_reg,
599 Label& L_success);
600
601 void clinit_barrier(Register klass,
602 Register thread,
603 Label* L_fast_path = NULL,
604 Label* L_slow_path = NULL);
605
606 // method handles (JSR 292)
607 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
608
609 //----
610 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
611
612 // Debugging
613
614 // only if +VerifyOops
615 // TODO: Make these macros with file and line like sparc version!
616 void verify_oop(Register reg, const char* s = "broken oop");
617 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
618
619 // TODO: verify method and klass metadata (compare against vptr?)
620 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
621 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
622
623 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
624 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
625
626 // only if +VerifyFPU
627 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
628
629 // Verify or restore cpu control state after JNI call
630 void restore_cpu_control_state_after_jni();
631
632 // prints msg, dumps registers and stops execution
633 void stop(const char* msg);
634
635 // prints msg and continues
636 void warn(const char* msg);
637
638 // dumps registers and other state
639 void print_state();
640
641 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
642 static void debug64(char* msg, int64_t pc, int64_t regs[]);
643 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
644 static void print_state64(int64_t pc, int64_t regs[]);
645
646 void os_breakpoint();
647
648 void untested() { stop("untested"); }
649
650 void unimplemented(const char* what = "");
651
652 void should_not_reach_here() { stop("should not reach here"); }
653
654 void print_CPU_state();
655
656 // Stack overflow checking
657 void bang_stack_with_offset(int offset) {
658 // stack grows down, caller passes positive offset
659 assert(offset > 0, "must bang with negative offset");
660 movl(Address(rsp, (-offset)), rax);
661 }
662
663 // Writes to stack successive pages until offset reached to check for
664 // stack overflow + shadow pages. Also, clobbers tmp
665 void bang_stack_size(Register size, Register tmp);
666
667 // Check for reserved stack access in method being exited (for JIT)
668 void reserved_stack_check();
669
670 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
671 Register tmp,
672 int offset);
673
674 // If thread_reg is != noreg the code assumes the register passed contains
675 // the thread (required on 64 bit).
676 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
677
678 void verify_tlab();
679
680 // Biased locking support
681 // lock_reg and obj_reg must be loaded up with the appropriate values.
682 // swap_reg must be rax, and is killed.
683 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
684 // be killed; if not supplied, push/pop will be used internally to
685 // allocate a temporary (inefficient, avoid if possible).
686 // Optional slow case is for implementations (interpreter and C1) which branch to
687 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
688 // Returns offset of first potentially-faulting instruction for null
689 // check info (currently consumed only by C1). If
690 // swap_reg_contains_mark is true then returns -1 as it is assumed
691 // the calling code has already passed any potential faults.
692 int biased_locking_enter(Register lock_reg, Register obj_reg,
693 Register swap_reg, Register tmp_reg,
694 bool swap_reg_contains_mark,
695 Label& done, Label* slow_case = NULL,
696 BiasedLockingCounters* counters = NULL);
697 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
698 #ifdef COMPILER2
699 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
700 // See full desription in macroAssembler_x86.cpp.
701 void fast_lock(Register obj, Register box, Register tmp,
702 Register scr, Register cx1, Register cx2,
703 BiasedLockingCounters* counters,
704 RTMLockingCounters* rtm_counters,
705 RTMLockingCounters* stack_rtm_counters,
706 Metadata* method_data,
707 bool use_rtm, bool profile_rtm);
708 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
709 #if INCLUDE_RTM_OPT
710 void rtm_counters_update(Register abort_status, Register rtm_counters);
711 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
712 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
713 RTMLockingCounters* rtm_counters,
714 Metadata* method_data);
715 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
716 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
717 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
718 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
719 void rtm_stack_locking(Register obj, Register tmp, Register scr,
720 Register retry_on_abort_count,
721 RTMLockingCounters* stack_rtm_counters,
722 Metadata* method_data, bool profile_rtm,
723 Label& DONE_LABEL, Label& IsInflated);
724 void rtm_inflated_locking(Register obj, Register box, Register tmp,
725 Register scr, Register retry_on_busy_count,
726 Register retry_on_abort_count,
727 RTMLockingCounters* rtm_counters,
728 Metadata* method_data, bool profile_rtm,
729 Label& DONE_LABEL);
730 #endif
731 #endif
732
733 Condition negate_condition(Condition cond);
734
735 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
736 // operands. In general the names are modified to avoid hiding the instruction in Assembler
737 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
738 // here in MacroAssembler. The major exception to this rule is call
739
740 // Arithmetics
741
742
743 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
744 void addptr(Address dst, Register src);
745
746 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
747 void addptr(Register dst, int32_t src);
748 void addptr(Register dst, Register src);
749 void addptr(Register dst, RegisterOrConstant src) {
750 if (src.is_constant()) addptr(dst, (int) src.as_constant());
751 else addptr(dst, src.as_register());
752 }
753
754 void andptr(Register dst, int32_t src);
755 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
756
757 void cmp8(AddressLiteral src1, int imm);
758
759 // renamed to drag out the casting of address to int32_t/intptr_t
760 void cmp32(Register src1, int32_t imm);
761
762 void cmp32(AddressLiteral src1, int32_t imm);
763 // compare reg - mem, or reg - &mem
764 void cmp32(Register src1, AddressLiteral src2);
765
766 void cmp32(Register src1, Address src2);
767
768 #ifndef _LP64
769 void cmpklass(Address dst, Metadata* obj);
770 void cmpklass(Register dst, Metadata* obj);
771 void cmpoop(Address dst, jobject obj);
772 void cmpoop_raw(Address dst, jobject obj);
773 #endif // _LP64
774
775 void cmpoop(Register src1, Register src2);
776 void cmpoop(Register src1, Address src2);
777 void cmpoop(Register dst, jobject obj);
778 void cmpoop_raw(Register dst, jobject obj);
779
780 // NOTE src2 must be the lval. This is NOT an mem-mem compare
781 void cmpptr(Address src1, AddressLiteral src2);
782
783 void cmpptr(Register src1, AddressLiteral src2);
784
785 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
786 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
787 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
788
789 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
790 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
791
792 // cmp64 to avoild hiding cmpq
793 void cmp64(Register src1, AddressLiteral src);
794
795 void cmpxchgptr(Register reg, Address adr);
796
797 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
798
799
800 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
801 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
802
803
804 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
805
806 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
807
808 void shlptr(Register dst, int32_t shift);
809 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
810
811 void shrptr(Register dst, int32_t shift);
812 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
813
814 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
815 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
816
817 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
818
819 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
820 void subptr(Register dst, int32_t src);
821 // Force generation of a 4 byte immediate value even if it fits into 8bit
822 void subptr_imm32(Register dst, int32_t src);
823 void subptr(Register dst, Register src);
824 void subptr(Register dst, RegisterOrConstant src) {
825 if (src.is_constant()) subptr(dst, (int) src.as_constant());
826 else subptr(dst, src.as_register());
827 }
828
829 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
830 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
831
832 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
833 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
834
835 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
836
837
838
839 // Helper functions for statistics gathering.
840 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
841 void cond_inc32(Condition cond, AddressLiteral counter_addr);
842 // Unconditional atomic increment.
843 void atomic_incl(Address counter_addr);
844 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
845 #ifdef _LP64
846 void atomic_incq(Address counter_addr);
847 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
848 #endif
849 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
850 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
851
852 void lea(Register dst, AddressLiteral adr);
853 void lea(Address dst, AddressLiteral adr);
854 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
855
856 void leal32(Register dst, Address src) { leal(dst, src); }
857
858 // Import other testl() methods from the parent class or else
859 // they will be hidden by the following overriding declaration.
860 using Assembler::testl;
861 void testl(Register dst, AddressLiteral src);
862
863 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
864 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
865 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
866 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
867
868 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
869 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
870 void testptr(Register src1, Register src2);
871
872 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
873 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
874
875 // Calls
876
877 void call(Label& L, relocInfo::relocType rtype);
878 void call(Register entry);
879
880 // NOTE: this call transfers to the effective address of entry NOT
881 // the address contained by entry. This is because this is more natural
882 // for jumps/calls.
883 void call(AddressLiteral entry);
884
885 // Emit the CompiledIC call idiom
886 void ic_call(address entry, jint method_index = 0);
887
888 // Jumps
889
890 // NOTE: these jumps tranfer to the effective address of dst NOT
891 // the address contained by dst. This is because this is more natural
892 // for jumps/calls.
893 void jump(AddressLiteral dst);
894 void jump_cc(Condition cc, AddressLiteral dst);
895
896 // 32bit can do a case table jump in one instruction but we no longer allow the base
897 // to be installed in the Address class. This jump will tranfers to the address
898 // contained in the location described by entry (not the address of entry)
899 void jump(ArrayAddress entry);
900
901 // Floating
902
903 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
904 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
905 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
906
907 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
908 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
909 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
910
911 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
912 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
913 void comiss(XMMRegister dst, AddressLiteral src);
914
915 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
916 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
917 void comisd(XMMRegister dst, AddressLiteral src);
918
919 void fadd_s(Address src) { Assembler::fadd_s(src); }
920 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
921
922 void fldcw(Address src) { Assembler::fldcw(src); }
923 void fldcw(AddressLiteral src);
924
925 void fld_s(int index) { Assembler::fld_s(index); }
926 void fld_s(Address src) { Assembler::fld_s(src); }
927 void fld_s(AddressLiteral src);
928
929 void fld_d(Address src) { Assembler::fld_d(src); }
930 void fld_d(AddressLiteral src);
931
932 void fld_x(Address src) { Assembler::fld_x(src); }
933 void fld_x(AddressLiteral src);
934
935 void fmul_s(Address src) { Assembler::fmul_s(src); }
936 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
937
938 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
939 void ldmxcsr(AddressLiteral src);
940
941 #ifdef _LP64
942 private:
943 void sha256_AVX2_one_round_compute(
944 Register reg_old_h,
945 Register reg_a,
946 Register reg_b,
947 Register reg_c,
948 Register reg_d,
949 Register reg_e,
950 Register reg_f,
951 Register reg_g,
952 Register reg_h,
953 int iter);
954 void sha256_AVX2_four_rounds_compute_first(int start);
955 void sha256_AVX2_four_rounds_compute_last(int start);
956 void sha256_AVX2_one_round_and_sched(
957 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
958 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
959 XMMRegister xmm_2, /* ymm6 */
960 XMMRegister xmm_3, /* ymm7 */
961 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
962 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
963 Register reg_c, /* edi */
964 Register reg_d, /* esi */
965 Register reg_e, /* r8d */
966 Register reg_f, /* r9d */
967 Register reg_g, /* r10d */
968 Register reg_h, /* r11d */
969 int iter);
970
971 void addm(int disp, Register r1, Register r2);
972 void gfmul(XMMRegister tmp0, XMMRegister t);
973 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
974 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
975 void generateHtbl_one_block(Register htbl);
976 void generateHtbl_eight_blocks(Register htbl);
977 public:
978 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
979 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
980 Register buf, Register state, Register ofs, Register limit, Register rsp,
981 bool multi_block, XMMRegister shuf_mask);
982 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
983 #endif
984
985 #ifdef _LP64
986 private:
987 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
988 Register e, Register f, Register g, Register h, int iteration);
989
990 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
991 Register a, Register b, Register c, Register d, Register e, Register f,
992 Register g, Register h, int iteration);
993
994 void addmq(int disp, Register r1, Register r2);
995 public:
996 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
997 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
998 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
999 XMMRegister shuf_mask);
1000 #endif
1001
1002 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1003 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1004 Register buf, Register state, Register ofs, Register limit, Register rsp,
1005 bool multi_block);
1006
1007 #ifdef _LP64
1008 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1009 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1010 Register buf, Register state, Register ofs, Register limit, Register rsp,
1011 bool multi_block, XMMRegister shuf_mask);
1012 #else
1013 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1014 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1015 Register buf, Register state, Register ofs, Register limit, Register rsp,
1016 bool multi_block);
1017 #endif
1018
1019 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1020 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1021 Register rax, Register rcx, Register rdx, Register tmp);
1022
1023 #ifdef _LP64
1024 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1025 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1026 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1027
1028 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1029 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1030 Register rax, Register rcx, Register rdx, Register r11);
1031
1032 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1033 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1034 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1035
1036 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1037 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1038 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1039 Register tmp3, Register tmp4);
1040
1041 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1042 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1043 Register rax, Register rcx, Register rdx, Register tmp1,
1044 Register tmp2, Register tmp3, Register tmp4);
1045 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1046 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1047 Register rax, Register rcx, Register rdx, Register tmp1,
1048 Register tmp2, Register tmp3, Register tmp4);
1049 #else
1050 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1051 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1052 Register rax, Register rcx, Register rdx, Register tmp1);
1053
1054 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1055 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1056 Register rax, Register rcx, Register rdx, Register tmp);
1057
1058 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1059 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1060 Register rdx, Register tmp);
1061
1062 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1063 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1064 Register rax, Register rbx, Register rdx);
1065
1066 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1067 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1068 Register rax, Register rcx, Register rdx, Register tmp);
1069
1070 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1071 Register edx, Register ebx, Register esi, Register edi,
1072 Register ebp, Register esp);
1073
1074 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1075 Register esi, Register edi, Register ebp, Register esp);
1076
1077 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1078 Register edx, Register ebx, Register esi, Register edi,
1079 Register ebp, Register esp);
1080
1081 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1082 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1083 Register rax, Register rcx, Register rdx, Register tmp);
1084 #endif
1085
1086 void increase_precision();
1087 void restore_precision();
1088
1089 private:
1090
1091 // these are private because users should be doing movflt/movdbl
1092
1093 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1094 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1095 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1096 void movss(XMMRegister dst, AddressLiteral src);
1097
1098 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1099 void movlpd(XMMRegister dst, AddressLiteral src);
1100
1101 public:
1102
1103 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1104 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1105 void addsd(XMMRegister dst, AddressLiteral src);
1106
1107 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1108 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1109 void addss(XMMRegister dst, AddressLiteral src);
1110
1111 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1112 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1113 void addpd(XMMRegister dst, AddressLiteral src);
1114
1115 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1116 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1117 void divsd(XMMRegister dst, AddressLiteral src);
1118
1119 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1120 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1121 void divss(XMMRegister dst, AddressLiteral src);
1122
1123 // Move Unaligned Double Quadword
1124 void movdqu(Address dst, XMMRegister src);
1125 void movdqu(XMMRegister dst, Address src);
1126 void movdqu(XMMRegister dst, XMMRegister src);
1127 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1128 // AVX Unaligned forms
1129 void vmovdqu(Address dst, XMMRegister src);
1130 void vmovdqu(XMMRegister dst, Address src);
1131 void vmovdqu(XMMRegister dst, XMMRegister src);
1132 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1133 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1134 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1135 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1136 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1137
1138 // Move Aligned Double Quadword
1139 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1140 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1141 void movdqa(XMMRegister dst, AddressLiteral src);
1142
1143 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1144 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1145 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1146 void movsd(XMMRegister dst, AddressLiteral src);
1147
1148 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1149 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1150 void mulpd(XMMRegister dst, AddressLiteral src);
1151
1152 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1153 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1154 void mulsd(XMMRegister dst, AddressLiteral src);
1155
1156 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1157 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1158 void mulss(XMMRegister dst, AddressLiteral src);
1159
1160 // Carry-Less Multiplication Quadword
1161 void pclmulldq(XMMRegister dst, XMMRegister src) {
1162 // 0x00 - multiply lower 64 bits [0:63]
1163 Assembler::pclmulqdq(dst, src, 0x00);
1164 }
1165 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1166 // 0x11 - multiply upper 64 bits [64:127]
1167 Assembler::pclmulqdq(dst, src, 0x11);
1168 }
1169
1170 void pcmpeqb(XMMRegister dst, XMMRegister src);
1171 void pcmpeqw(XMMRegister dst, XMMRegister src);
1172
1173 void pcmpestri(XMMRegister dst, Address src, int imm8);
1174 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1175
1176 void pmovzxbw(XMMRegister dst, XMMRegister src);
1177 void pmovzxbw(XMMRegister dst, Address src);
1178
1179 void pmovmskb(Register dst, XMMRegister src);
1180
1181 void ptest(XMMRegister dst, XMMRegister src);
1182
1183 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1184 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1185 void sqrtsd(XMMRegister dst, AddressLiteral src);
1186
1187 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1188 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1189 void sqrtss(XMMRegister dst, AddressLiteral src);
1190
1191 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1192 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1193 void subsd(XMMRegister dst, AddressLiteral src);
1194
1195 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1196 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1197 void subss(XMMRegister dst, AddressLiteral src);
1198
1199 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1200 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1201 void ucomiss(XMMRegister dst, AddressLiteral src);
1202
1203 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1204 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1205 void ucomisd(XMMRegister dst, AddressLiteral src);
1206
1207 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1208 void xorpd(XMMRegister dst, XMMRegister src);
1209 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1210 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1211
1212 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1213 void xorps(XMMRegister dst, XMMRegister src);
1214 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1215 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1216
1217 // Shuffle Bytes
1218 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1219 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1220 void pshufb(XMMRegister dst, AddressLiteral src);
1221 // AVX 3-operands instructions
1222
1223 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1224 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1225 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1226
1227 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1228 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1229 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1230
1231 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1232 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1233
1234 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1235 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1236
1237 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1238 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1239
1240 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1241 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1242 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1243
1244 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1245 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1246
1247 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1248
1249 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1250
1251 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1252 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1253
1254 void vpmovmskb(Register dst, XMMRegister src);
1255
1256 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1257 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1258
1259 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1260 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1261
1262 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1263 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1264
1265 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1266 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1267
1268 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1269 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1270
1271 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1272 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1273
1274 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1275 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1276
1277 void vptest(XMMRegister dst, XMMRegister src);
1278
1279 void punpcklbw(XMMRegister dst, XMMRegister src);
1280 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1281
1282 void pshufd(XMMRegister dst, Address src, int mode);
1283 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1284
1285 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1286 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1287
1288 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1289 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1290 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1291
1292 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1293 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1294 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1295
1296 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1297 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1298 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1299
1300 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1301 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1302 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1303
1304 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1305 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1306 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1307
1308 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1309 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1310 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1311
1312 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1313 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1314 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1315
1316 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1317 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1318 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1319
1320 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1321 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1322
1323 // AVX Vector instructions
1324
1325 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1326 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1327 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1328
1329 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1330 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1331 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1332
1333 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1334 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1335 Assembler::vpxor(dst, nds, src, vector_len);
1336 else
1337 Assembler::vxorpd(dst, nds, src, vector_len);
1338 }
1339 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1340 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1341 Assembler::vpxor(dst, nds, src, vector_len);
1342 else
1343 Assembler::vxorpd(dst, nds, src, vector_len);
1344 }
1345 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1346
1347 // Simple version for AVX2 256bit vectors
1348 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1349 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1350
1351 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1352 if (UseAVX > 2) {
1353 Assembler::vinserti32x4(dst, dst, src, imm8);
1354 } else if (UseAVX > 1) {
1355 // vinserti128 is available only in AVX2
1356 Assembler::vinserti128(dst, nds, src, imm8);
1357 } else {
1358 Assembler::vinsertf128(dst, nds, src, imm8);
1359 }
1360 }
1361
1362 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1363 if (UseAVX > 2) {
1364 Assembler::vinserti32x4(dst, dst, src, imm8);
1365 } else if (UseAVX > 1) {
1366 // vinserti128 is available only in AVX2
1367 Assembler::vinserti128(dst, nds, src, imm8);
1368 } else {
1369 Assembler::vinsertf128(dst, nds, src, imm8);
1370 }
1371 }
1372
1373 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1374 if (UseAVX > 2) {
1375 Assembler::vextracti32x4(dst, src, imm8);
1376 } else if (UseAVX > 1) {
1377 // vextracti128 is available only in AVX2
1378 Assembler::vextracti128(dst, src, imm8);
1379 } else {
1380 Assembler::vextractf128(dst, src, imm8);
1381 }
1382 }
1383
1384 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1385 if (UseAVX > 2) {
1386 Assembler::vextracti32x4(dst, src, imm8);
1387 } else if (UseAVX > 1) {
1388 // vextracti128 is available only in AVX2
1389 Assembler::vextracti128(dst, src, imm8);
1390 } else {
1391 Assembler::vextractf128(dst, src, imm8);
1392 }
1393 }
1394
1395 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1396 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1397 vinserti128(dst, dst, src, 1);
1398 }
1399 void vinserti128_high(XMMRegister dst, Address src) {
1400 vinserti128(dst, dst, src, 1);
1401 }
1402 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1403 vextracti128(dst, src, 1);
1404 }
1405 void vextracti128_high(Address dst, XMMRegister src) {
1406 vextracti128(dst, src, 1);
1407 }
1408
1409 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1410 if (UseAVX > 2) {
1411 Assembler::vinsertf32x4(dst, dst, src, 1);
1412 } else {
1413 Assembler::vinsertf128(dst, dst, src, 1);
1414 }
1415 }
1416
1417 void vinsertf128_high(XMMRegister dst, Address src) {
1418 if (UseAVX > 2) {
1419 Assembler::vinsertf32x4(dst, dst, src, 1);
1420 } else {
1421 Assembler::vinsertf128(dst, dst, src, 1);
1422 }
1423 }
1424
1425 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1426 if (UseAVX > 2) {
1427 Assembler::vextractf32x4(dst, src, 1);
1428 } else {
1429 Assembler::vextractf128(dst, src, 1);
1430 }
1431 }
1432
1433 void vextractf128_high(Address dst, XMMRegister src) {
1434 if (UseAVX > 2) {
1435 Assembler::vextractf32x4(dst, src, 1);
1436 } else {
1437 Assembler::vextractf128(dst, src, 1);
1438 }
1439 }
1440
1441 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1442 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1443 Assembler::vinserti64x4(dst, dst, src, 1);
1444 }
1445 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1446 Assembler::vinsertf64x4(dst, dst, src, 1);
1447 }
1448 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1449 Assembler::vextracti64x4(dst, src, 1);
1450 }
1451 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1452 Assembler::vextractf64x4(dst, src, 1);
1453 }
1454 void vextractf64x4_high(Address dst, XMMRegister src) {
1455 Assembler::vextractf64x4(dst, src, 1);
1456 }
1457 void vinsertf64x4_high(XMMRegister dst, Address src) {
1458 Assembler::vinsertf64x4(dst, dst, src, 1);
1459 }
1460
1461 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1462 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1463 vinserti128(dst, dst, src, 0);
1464 }
1465 void vinserti128_low(XMMRegister dst, Address src) {
1466 vinserti128(dst, dst, src, 0);
1467 }
1468 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1469 vextracti128(dst, src, 0);
1470 }
1471 void vextracti128_low(Address dst, XMMRegister src) {
1472 vextracti128(dst, src, 0);
1473 }
1474
1475 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1476 if (UseAVX > 2) {
1477 Assembler::vinsertf32x4(dst, dst, src, 0);
1478 } else {
1479 Assembler::vinsertf128(dst, dst, src, 0);
1480 }
1481 }
1482
1483 void vinsertf128_low(XMMRegister dst, Address src) {
1484 if (UseAVX > 2) {
1485 Assembler::vinsertf32x4(dst, dst, src, 0);
1486 } else {
1487 Assembler::vinsertf128(dst, dst, src, 0);
1488 }
1489 }
1490
1491 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1492 if (UseAVX > 2) {
1493 Assembler::vextractf32x4(dst, src, 0);
1494 } else {
1495 Assembler::vextractf128(dst, src, 0);
1496 }
1497 }
1498
1499 void vextractf128_low(Address dst, XMMRegister src) {
1500 if (UseAVX > 2) {
1501 Assembler::vextractf32x4(dst, src, 0);
1502 } else {
1503 Assembler::vextractf128(dst, src, 0);
1504 }
1505 }
1506
1507 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1508 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1509 Assembler::vinserti64x4(dst, dst, src, 0);
1510 }
1511 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1512 Assembler::vinsertf64x4(dst, dst, src, 0);
1513 }
1514 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1515 Assembler::vextracti64x4(dst, src, 0);
1516 }
1517 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1518 Assembler::vextractf64x4(dst, src, 0);
1519 }
1520 void vextractf64x4_low(Address dst, XMMRegister src) {
1521 Assembler::vextractf64x4(dst, src, 0);
1522 }
1523 void vinsertf64x4_low(XMMRegister dst, Address src) {
1524 Assembler::vinsertf64x4(dst, dst, src, 0);
1525 }
1526
1527 // Carry-Less Multiplication Quadword
1528 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1529 // 0x00 - multiply lower 64 bits [0:63]
1530 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1531 }
1532 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1533 // 0x11 - multiply upper 64 bits [64:127]
1534 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1535 }
1536 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1537 // 0x10 - multiply nds[0:63] and src[64:127]
1538 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1539 }
1540 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1541 //0x01 - multiply nds[64:127] and src[0:63]
1542 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1543 }
1544
1545 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1546 // 0x00 - multiply lower 64 bits [0:63]
1547 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1548 }
1549 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1550 // 0x11 - multiply upper 64 bits [64:127]
1551 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1552 }
1553
1554 // Data
1555
1556 void cmov32( Condition cc, Register dst, Address src);
1557 void cmov32( Condition cc, Register dst, Register src);
1558
1559 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1560
1561 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1562 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1563
1564 void movoop(Register dst, jobject obj);
1565 void movoop(Address dst, jobject obj);
1566
1567 void mov_metadata(Register dst, Metadata* obj);
1568 void mov_metadata(Address dst, Metadata* obj);
1569
1570 void movptr(ArrayAddress dst, Register src);
1571 // can this do an lea?
1572 void movptr(Register dst, ArrayAddress src);
1573
1574 void movptr(Register dst, Address src);
1575
1576 #ifdef _LP64
1577 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1578 #else
1579 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1580 #endif
1581
1582 void movptr(Register dst, intptr_t src);
1583 void movptr(Register dst, Register src);
1584 void movptr(Address dst, intptr_t src);
1585
1586 void movptr(Address dst, Register src);
1587
1588 void movptr(Register dst, RegisterOrConstant src) {
1589 if (src.is_constant()) movptr(dst, src.as_constant());
1590 else movptr(dst, src.as_register());
1591 }
1592
1593 #ifdef _LP64
1594 // Generally the next two are only used for moving NULL
1595 // Although there are situations in initializing the mark word where
1596 // they could be used. They are dangerous.
1597
1598 // They only exist on LP64 so that int32_t and intptr_t are not the same
1599 // and we have ambiguous declarations.
1600
1601 void movptr(Address dst, int32_t imm32);
1602 void movptr(Register dst, int32_t imm32);
1603 #endif // _LP64
1604
1605 // to avoid hiding movl
1606 void mov32(AddressLiteral dst, Register src);
1607 void mov32(Register dst, AddressLiteral src);
1608
1609 // to avoid hiding movb
1610 void movbyte(ArrayAddress dst, int src);
1611
1612 // Import other mov() methods from the parent class or else
1613 // they will be hidden by the following overriding declaration.
1614 using Assembler::movdl;
1615 using Assembler::movq;
1616 void movdl(XMMRegister dst, AddressLiteral src);
1617 void movq(XMMRegister dst, AddressLiteral src);
1618
1619 // Can push value or effective address
1620 void pushptr(AddressLiteral src);
1621
1622 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1623 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1624
1625 void pushoop(jobject obj);
1626 void pushklass(Metadata* obj);
1627
1628 // sign extend as need a l to ptr sized element
1629 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1630 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1631
1632 #ifdef COMPILER2
1633 // Generic instructions support for use in .ad files C2 code generation
1634 void vabsnegd(int opcode, XMMRegister dst, Register scr);
1635 void vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1636 void vabsnegf(int opcode, XMMRegister dst, Register scr);
1637 void vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1638 void vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len);
1639 void vextendbw(bool sign, XMMRegister dst, XMMRegister src);
1640 void vshiftd(int opcode, XMMRegister dst, XMMRegister src);
1641 void vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1642 void vshiftw(int opcode, XMMRegister dst, XMMRegister src);
1643 void vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1644 void vshiftq(int opcode, XMMRegister dst, XMMRegister src);
1645 void vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1646 #endif
1647
1648 // C2 compiled method's prolog code.
1649 void verified_entry(Compile* C, int sp_inc = 0);
1650
1651 enum RegState {
1652 reg_readonly,
1653 reg_writable,
1654 reg_written
1655 };
1656
1657 int store_value_type_fields_to_buf(ciValueKlass* vk, bool from_interpreter = true);
1658
1659 // Unpack all value type arguments passed as oops
1660 void unpack_value_args(Compile* C, bool receiver_only);
1661 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off, int extra_stack_offset);
1662 bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index,
1663 RegState reg_state[], int ret_off, int extra_stack_offset);
1664 bool pack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1665 VMReg to, VMRegPair* regs_from, int regs_from_count, int& from_index, RegState reg_state[],
1666 int ret_off, int extra_stack_offset);
1667 void restore_stack(Compile* C);
1668
1669 int shuffle_value_args(bool is_packing, bool receiver_only, int extra_stack_offset,
1670 BasicType* sig_bt, const GrowableArray<SigEntry>* sig_cc,
1671 int args_passed, int args_on_stack, VMRegPair* regs,
1672 int args_passed_to, int args_on_stack_to, VMRegPair* regs_to);
1673 bool shuffle_value_args_spill(bool is_packing, const GrowableArray<SigEntry>* sig_cc, int sig_cc_index,
1674 VMRegPair* regs_from, int from_index, int regs_from_count,
1675 RegState* reg_state, int sp_inc, int extra_stack_offset);
1676 VMReg spill_reg_for(VMReg reg);
1677
1678 // clear memory of size 'cnt' qwords, starting at 'base';
1679 // if 'is_large' is set, do not try to produce short loop
1680 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1681
1682 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1683 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1684
1685 #ifdef COMPILER2
1686 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1687 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1688
1689 // IndexOf strings.
1690 // Small strings are loaded through stack if they cross page boundary.
1691 void string_indexof(Register str1, Register str2,
1692 Register cnt1, Register cnt2,
1693 int int_cnt2, Register result,
1694 XMMRegister vec, Register tmp,
1695 int ae);
1696
1697 // IndexOf for constant substrings with size >= 8 elements
1698 // which don't need to be loaded through stack.
1699 void string_indexofC8(Register str1, Register str2,
1700 Register cnt1, Register cnt2,
1701 int int_cnt2, Register result,
1702 XMMRegister vec, Register tmp,
1703 int ae);
1704
1705 // Smallest code: we don't need to load through stack,
1706 // check string tail.
1707
1708 // helper function for string_compare
1709 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1710 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1711 Address::ScaleFactor scale2, Register index, int ae);
1712 // Compare strings.
1713 void string_compare(Register str1, Register str2,
1714 Register cnt1, Register cnt2, Register result,
1715 XMMRegister vec1, int ae);
1716
1717 // Search for Non-ASCII character (Negative byte value) in a byte array,
1718 // return true if it has any and false otherwise.
1719 void has_negatives(Register ary1, Register len,
1720 Register result, Register tmp1,
1721 XMMRegister vec1, XMMRegister vec2);
1722
1723 // Compare char[] or byte[] arrays.
1724 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1725 Register limit, Register result, Register chr,
1726 XMMRegister vec1, XMMRegister vec2, bool is_char);
1727
1728 #endif
1729
1730 // Fill primitive arrays
1731 void generate_fill(BasicType t, bool aligned,
1732 Register to, Register value, Register count,
1733 Register rtmp, XMMRegister xtmp);
1734
1735 void encode_iso_array(Register src, Register dst, Register len,
1736 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1737 XMMRegister tmp4, Register tmp5, Register result);
1738
1739 #ifdef _LP64
1740 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1741 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1742 Register y, Register y_idx, Register z,
1743 Register carry, Register product,
1744 Register idx, Register kdx);
1745 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1746 Register yz_idx, Register idx,
1747 Register carry, Register product, int offset);
1748 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1749 Register carry, Register carry2,
1750 Register idx, Register jdx,
1751 Register yz_idx1, Register yz_idx2,
1752 Register tmp, Register tmp3, Register tmp4);
1753 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1754 Register yz_idx, Register idx, Register jdx,
1755 Register carry, Register product,
1756 Register carry2);
1757 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1758 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1759 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1760 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1761 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1762 Register tmp2);
1763 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1764 Register rdxReg, Register raxReg);
1765 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1766 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1767 Register tmp3, Register tmp4);
1768 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1769 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1770
1771 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1772 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1773 Register raxReg);
1774 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1775 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1776 Register raxReg);
1777 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1778 Register result, Register tmp1, Register tmp2,
1779 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1780 #endif
1781
1782 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1783 void update_byte_crc32(Register crc, Register val, Register table);
1784 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1785 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1786 // Note on a naming convention:
1787 // Prefix w = register only used on a Westmere+ architecture
1788 // Prefix n = register only used on a Nehalem architecture
1789 #ifdef _LP64
1790 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1791 Register tmp1, Register tmp2, Register tmp3);
1792 #else
1793 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1794 Register tmp1, Register tmp2, Register tmp3,
1795 XMMRegister xtmp1, XMMRegister xtmp2);
1796 #endif
1797 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1798 Register in_out,
1799 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1800 XMMRegister w_xtmp2,
1801 Register tmp1,
1802 Register n_tmp2, Register n_tmp3);
1803 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1804 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1805 Register tmp1, Register tmp2,
1806 Register n_tmp3);
1807 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1808 Register in_out1, Register in_out2, Register in_out3,
1809 Register tmp1, Register tmp2, Register tmp3,
1810 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1811 Register tmp4, Register tmp5,
1812 Register n_tmp6);
1813 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1814 Register tmp1, Register tmp2, Register tmp3,
1815 Register tmp4, Register tmp5, Register tmp6,
1816 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1817 bool is_pclmulqdq_supported);
1818 // Fold 128-bit data chunk
1819 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1820 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1821 // Fold 8-bit data
1822 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1823 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1824 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1825
1826 // Compress char[] array to byte[].
1827 void char_array_compress(Register src, Register dst, Register len,
1828 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1829 XMMRegister tmp4, Register tmp5, Register result);
1830
1831 // Inflate byte[] array to char[].
1832 void byte_array_inflate(Register src, Register dst, Register len,
1833 XMMRegister tmp1, Register tmp2);
1834
1835 #include "asm/macroAssembler_common.hpp"
1836
1837
1838 };
1839
1840 /**
1841 * class SkipIfEqual:
1842 *
1843 * Instantiating this class will result in assembly code being output that will
1844 * jump around any code emitted between the creation of the instance and it's
1845 * automatic destruction at the end of a scope block, depending on the value of
1846 * the flag passed to the constructor, which will be checked at run-time.
1847 */
1848 class SkipIfEqual {
1849 private:
1850 MacroAssembler* _masm;
1851 Label _label;
1852
1853 public:
1854 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1855 ~SkipIfEqual();
1856 };
1857
1858 #endif // CPU_X86_MACROASSEMBLER_X86_HPP