1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableBarrierSet.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "nativeInst_x86.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "vmreg_x86.inline.hpp"
  44 
  45 
  46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  47 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  48 // fast versions of NegF/NegD and AbsF/AbsD.
  49 
  50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  52   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  53   // of 128-bits operands for SSE instructions.
  54   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  55   // Store the value to a 128-bits operand.
  56   operand[0] = lo;
  57   operand[1] = hi;
  58   return operand;
  59 }
  60 
  61 // Buffer for 128-bits masks used by SSE instructions.
  62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  63 
  64 // Static initialization during VM startup.
  65 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  67 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  69 
  70 
  71 
  72 NEEDS_CLEANUP // remove this definitions ?
  73 const Register IC_Klass    = rax;   // where the IC klass is cached
  74 const Register SYNC_header = rax;   // synchronization header
  75 const Register SHIFT_count = rcx;   // where count for shift operations must be
  76 
  77 #define __ _masm->
  78 
  79 
  80 static void select_different_registers(Register preserve,
  81                                        Register extra,
  82                                        Register &tmp1,
  83                                        Register &tmp2) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, extra);
  89     tmp2 = extra;
  90   }
  91   assert_different_registers(preserve, tmp1, tmp2);
  92 }
  93 
  94 
  95 
  96 static void select_different_registers(Register preserve,
  97                                        Register extra,
  98                                        Register &tmp1,
  99                                        Register &tmp2,
 100                                        Register &tmp3) {
 101   if (tmp1 == preserve) {
 102     assert_different_registers(tmp1, tmp2, tmp3, extra);
 103     tmp1 = extra;
 104   } else if (tmp2 == preserve) {
 105     assert_different_registers(tmp1, tmp2, tmp3, extra);
 106     tmp2 = extra;
 107   } else if (tmp3 == preserve) {
 108     assert_different_registers(tmp1, tmp2, tmp3, extra);
 109     tmp3 = extra;
 110   }
 111   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 112 }
 113 
 114 
 115 
 116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 117   if (opr->is_constant()) {
 118     LIR_Const* constant = opr->as_constant_ptr();
 119     switch (constant->type()) {
 120       case T_INT: {
 121         return true;
 122       }
 123 
 124       default:
 125         return false;
 126     }
 127   }
 128   return false;
 129 }
 130 
 131 
 132 LIR_Opr LIR_Assembler::receiverOpr() {
 133   return FrameMap::receiver_opr;
 134 }
 135 
 136 LIR_Opr LIR_Assembler::osrBufferPointer() {
 137   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 138 }
 139 
 140 //--------------fpu register translations-----------------------
 141 
 142 
 143 address LIR_Assembler::float_constant(float f) {
 144   address const_addr = __ float_constant(f);
 145   if (const_addr == NULL) {
 146     bailout("const section overflow");
 147     return __ code()->consts()->start();
 148   } else {
 149     return const_addr;
 150   }
 151 }
 152 
 153 
 154 address LIR_Assembler::double_constant(double d) {
 155   address const_addr = __ double_constant(d);
 156   if (const_addr == NULL) {
 157     bailout("const section overflow");
 158     return __ code()->consts()->start();
 159   } else {
 160     return const_addr;
 161   }
 162 }
 163 
 164 
 165 void LIR_Assembler::set_24bit_FPU() {
 166   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 167 }
 168 
 169 void LIR_Assembler::reset_FPU() {
 170   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 171 }
 172 
 173 void LIR_Assembler::fpop() {
 174   __ fpop();
 175 }
 176 
 177 void LIR_Assembler::fxch(int i) {
 178   __ fxch(i);
 179 }
 180 
 181 void LIR_Assembler::fld(int i) {
 182   __ fld_s(i);
 183 }
 184 
 185 void LIR_Assembler::ffree(int i) {
 186   __ ffree(i);
 187 }
 188 
 189 void LIR_Assembler::breakpoint() {
 190   __ int3();
 191 }
 192 
 193 void LIR_Assembler::push(LIR_Opr opr) {
 194   if (opr->is_single_cpu()) {
 195     __ push_reg(opr->as_register());
 196   } else if (opr->is_double_cpu()) {
 197     NOT_LP64(__ push_reg(opr->as_register_hi()));
 198     __ push_reg(opr->as_register_lo());
 199   } else if (opr->is_stack()) {
 200     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 201   } else if (opr->is_constant()) {
 202     LIR_Const* const_opr = opr->as_constant_ptr();
 203     if (const_opr->type() == T_OBJECT || const_opr->type() == T_VALUETYPE) {
 204       __ push_oop(const_opr->as_jobject());
 205     } else if (const_opr->type() == T_INT) {
 206       __ push_jint(const_opr->as_jint());
 207     } else {
 208       ShouldNotReachHere();
 209     }
 210 
 211   } else {
 212     ShouldNotReachHere();
 213   }
 214 }
 215 
 216 void LIR_Assembler::pop(LIR_Opr opr) {
 217   if (opr->is_single_cpu()) {
 218     __ pop_reg(opr->as_register());
 219   } else {
 220     ShouldNotReachHere();
 221   }
 222 }
 223 
 224 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 225   return addr->base()->is_illegal() && addr->index()->is_illegal();
 226 }
 227 
 228 //-------------------------------------------
 229 
 230 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 231   return as_Address(addr, rscratch1);
 232 }
 233 
 234 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 235   if (addr->base()->is_illegal()) {
 236     assert(addr->index()->is_illegal(), "must be illegal too");
 237     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 238     if (! __ reachable(laddr)) {
 239       __ movptr(tmp, laddr.addr());
 240       Address res(tmp, 0);
 241       return res;
 242     } else {
 243       return __ as_Address(laddr);
 244     }
 245   }
 246 
 247   Register base = addr->base()->as_pointer_register();
 248 
 249   if (addr->index()->is_illegal()) {
 250     return Address( base, addr->disp());
 251   } else if (addr->index()->is_cpu_register()) {
 252     Register index = addr->index()->as_pointer_register();
 253     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 254   } else if (addr->index()->is_constant()) {
 255     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 256     assert(Assembler::is_simm32(addr_offset), "must be");
 257 
 258     return Address(base, addr_offset);
 259   } else {
 260     Unimplemented();
 261     return Address();
 262   }
 263 }
 264 
 265 
 266 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 267   Address base = as_Address(addr);
 268   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 269 }
 270 
 271 
 272 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 273   return as_Address(addr);
 274 }
 275 
 276 
 277 void LIR_Assembler::osr_entry() {
 278   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 279   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 280   ValueStack* entry_state = osr_entry->state();
 281   int number_of_locks = entry_state->locks_size();
 282 
 283   // we jump here if osr happens with the interpreter
 284   // state set up to continue at the beginning of the
 285   // loop that triggered osr - in particular, we have
 286   // the following registers setup:
 287   //
 288   // rcx: osr buffer
 289   //
 290 
 291   // build frame
 292   ciMethod* m = compilation()->method();
 293   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 294 
 295   // OSR buffer is
 296   //
 297   // locals[nlocals-1..0]
 298   // monitors[0..number_of_locks]
 299   //
 300   // locals is a direct copy of the interpreter frame so in the osr buffer
 301   // so first slot in the local array is the last local from the interpreter
 302   // and last slot is local[0] (receiver) from the interpreter
 303   //
 304   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 305   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 306   // in the interpreter frame (the method lock if a sync method)
 307 
 308   // Initialize monitors in the compiled activation.
 309   //   rcx: pointer to osr buffer
 310   //
 311   // All other registers are dead at this point and the locals will be
 312   // copied into place by code emitted in the IR.
 313 
 314   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 315   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 316     int monitor_offset = BytesPerWord * method()->max_locals() +
 317       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 318     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 319     // the OSR buffer using 2 word entries: first the lock and then
 320     // the oop.
 321     for (int i = 0; i < number_of_locks; i++) {
 322       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 323 #ifdef ASSERT
 324       // verify the interpreter's monitor has a non-null object
 325       {
 326         Label L;
 327         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 328         __ jcc(Assembler::notZero, L);
 329         __ stop("locked object is NULL");
 330         __ bind(L);
 331       }
 332 #endif
 333       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 334       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 335       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 336       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 337     }
 338   }
 339 }
 340 
 341 
 342 // inline cache check; done before the frame is built.
 343 int LIR_Assembler::check_icache() {
 344   Register receiver = FrameMap::receiver_opr->as_register();
 345   Register ic_klass = IC_Klass;
 346   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 347   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 348   if (!do_post_padding) {
 349     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 350     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 351   }
 352   int offset = __ offset();
 353   __ inline_cache_check(receiver, IC_Klass);
 354   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 355   if (do_post_padding) {
 356     // force alignment after the cache check.
 357     // It's been verified to be aligned if !VerifyOops
 358     __ align(CodeEntryAlignment);
 359   }
 360   return offset;
 361 }
 362 
 363 
 364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 365   jobject o = NULL;
 366   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 367   __ movoop(reg, o);
 368   patching_epilog(patch, lir_patch_normal, reg, info);
 369 }
 370 
 371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 372   Metadata* o = NULL;
 373   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 374   __ mov_metadata(reg, o);
 375   patching_epilog(patch, lir_patch_normal, reg, info);
 376 }
 377 
 378 // This specifies the rsp decrement needed to build the frame
 379 int LIR_Assembler::initial_frame_size_in_bytes() const {
 380   // if rounding, must let FrameMap know!
 381 
 382   // The frame_map records size in slots (32bit word)
 383 
 384   // subtract two words to account for return address and link
 385   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 386 }
 387 
 388 
 389 int LIR_Assembler::emit_exception_handler() {
 390   // if the last instruction is a call (typically to do a throw which
 391   // is coming at the end after block reordering) the return address
 392   // must still point into the code area in order to avoid assertion
 393   // failures when searching for the corresponding bci => add a nop
 394   // (was bug 5/14/1999 - gri)
 395   __ nop();
 396 
 397   // generate code for exception handler
 398   address handler_base = __ start_a_stub(exception_handler_size());
 399   if (handler_base == NULL) {
 400     // not enough space left for the handler
 401     bailout("exception handler overflow");
 402     return -1;
 403   }
 404 
 405   int offset = code_offset();
 406 
 407   // the exception oop and pc are in rax, and rdx
 408   // no other registers need to be preserved, so invalidate them
 409   __ invalidate_registers(false, true, true, false, true, true);
 410 
 411   // check that there is really an exception
 412   __ verify_not_null_oop(rax);
 413 
 414   // search an exception handler (rax: exception oop, rdx: throwing pc)
 415   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 416   __ should_not_reach_here();
 417   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 418   __ end_a_stub();
 419 
 420   return offset;
 421 }
 422 
 423 
 424 // Emit the code to remove the frame from the stack in the exception
 425 // unwind path.
 426 int LIR_Assembler::emit_unwind_handler() {
 427 #ifndef PRODUCT
 428   if (CommentedAssembly) {
 429     _masm->block_comment("Unwind handler");
 430   }
 431 #endif
 432 
 433   int offset = code_offset();
 434 
 435   // Fetch the exception from TLS and clear out exception related thread state
 436   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 437   NOT_LP64(__ get_thread(rsi));
 438   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 439   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 440   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 441 
 442   __ bind(_unwind_handler_entry);
 443   __ verify_not_null_oop(rax);
 444   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 445     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 446   }
 447 
 448   // Preform needed unlocking
 449   MonitorExitStub* stub = NULL;
 450   if (method()->is_synchronized()) {
 451     monitor_address(0, FrameMap::rax_opr);
 452     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 453     __ unlock_object(rdi, rsi, rax, *stub->entry());
 454     __ bind(*stub->continuation());
 455   }
 456 
 457   if (compilation()->env()->dtrace_method_probes()) {
 458 #ifdef _LP64
 459     __ mov(rdi, r15_thread);
 460     __ mov_metadata(rsi, method()->constant_encoding());
 461 #else
 462     __ get_thread(rax);
 463     __ movptr(Address(rsp, 0), rax);
 464     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 465 #endif
 466     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 467   }
 468 
 469   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 470     __ mov(rax, rbx);  // Restore the exception
 471   }
 472 
 473   // remove the activation and dispatch to the unwind handler
 474   __ remove_frame(initial_frame_size_in_bytes());
 475   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 476 
 477   // Emit the slow path assembly
 478   if (stub != NULL) {
 479     stub->emit_code(this);
 480   }
 481 
 482   return offset;
 483 }
 484 
 485 
 486 int LIR_Assembler::emit_deopt_handler() {
 487   // if the last instruction is a call (typically to do a throw which
 488   // is coming at the end after block reordering) the return address
 489   // must still point into the code area in order to avoid assertion
 490   // failures when searching for the corresponding bci => add a nop
 491   // (was bug 5/14/1999 - gri)
 492   __ nop();
 493 
 494   // generate code for exception handler
 495   address handler_base = __ start_a_stub(deopt_handler_size());
 496   if (handler_base == NULL) {
 497     // not enough space left for the handler
 498     bailout("deopt handler overflow");
 499     return -1;
 500   }
 501 
 502   int offset = code_offset();
 503   InternalAddress here(__ pc());
 504 
 505   __ pushptr(here.addr());
 506   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 507   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 508   __ end_a_stub();
 509 
 510   return offset;
 511 }
 512 
 513 
 514 void LIR_Assembler::return_op(LIR_Opr result) {
 515   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 516   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 517     assert(result->fpu() == 0, "result must already be on TOS");
 518   }
 519 
 520   // Pop the stack before the safepoint code
 521   __ remove_frame(initial_frame_size_in_bytes());
 522 
 523   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 524     __ reserved_stack_check();
 525   }
 526 
 527   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 528 
 529   // Note: we do not need to round double result; float result has the right precision
 530   // the poll sets the condition code, but no data registers
 531 
 532   if (SafepointMechanism::uses_thread_local_poll()) {
 533 #ifdef _LP64
 534     const Register poll_addr = rscratch1;
 535     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 536 #else
 537     const Register poll_addr = rbx;
 538     assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
 539     __ get_thread(poll_addr);
 540     __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
 541 #endif
 542     __ relocate(relocInfo::poll_return_type);
 543     __ testl(rax, Address(poll_addr, 0));
 544   } else {
 545     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
 546 
 547     if (Assembler::is_polling_page_far()) {
 548       __ lea(rscratch1, polling_page);
 549       __ relocate(relocInfo::poll_return_type);
 550       __ testl(rax, Address(rscratch1, 0));
 551     } else {
 552       __ testl(rax, polling_page);
 553     }
 554   }
 555   __ ret(0);
 556 }
 557 
 558 
 559 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 560   guarantee(info != NULL, "Shouldn't be NULL");
 561   int offset = __ offset();
 562   if (SafepointMechanism::uses_thread_local_poll()) {
 563 #ifdef _LP64
 564     const Register poll_addr = rscratch1;
 565     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 566 #else
 567     assert(tmp->is_cpu_register(), "needed");
 568     const Register poll_addr = tmp->as_register();
 569     __ get_thread(poll_addr);
 570     __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
 571 #endif
 572     add_debug_info_for_branch(info);
 573     __ relocate(relocInfo::poll_type);
 574     address pre_pc = __ pc();
 575     __ testl(rax, Address(poll_addr, 0));
 576     address post_pc = __ pc();
 577     guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 578   } else {
 579     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
 580     if (Assembler::is_polling_page_far()) {
 581       __ lea(rscratch1, polling_page);
 582       offset = __ offset();
 583       add_debug_info_for_branch(info);
 584       __ relocate(relocInfo::poll_type);
 585       __ testl(rax, Address(rscratch1, 0));
 586     } else {
 587       add_debug_info_for_branch(info);
 588       __ testl(rax, polling_page);
 589     }
 590   }
 591   return offset;
 592 }
 593 
 594 
 595 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 596   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 597 }
 598 
 599 void LIR_Assembler::swap_reg(Register a, Register b) {
 600   __ xchgptr(a, b);
 601 }
 602 
 603 
 604 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 605   assert(src->is_constant(), "should not call otherwise");
 606   assert(dest->is_register(), "should not call otherwise");
 607   LIR_Const* c = src->as_constant_ptr();
 608 
 609   switch (c->type()) {
 610     case T_INT: {
 611       assert(patch_code == lir_patch_none, "no patching handled here");
 612       __ movl(dest->as_register(), c->as_jint());
 613       break;
 614     }
 615 
 616     case T_ADDRESS: {
 617       assert(patch_code == lir_patch_none, "no patching handled here");
 618       __ movptr(dest->as_register(), c->as_jint());
 619       break;
 620     }
 621 
 622     case T_LONG: {
 623       assert(patch_code == lir_patch_none, "no patching handled here");
 624 #ifdef _LP64
 625       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 626 #else
 627       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 628       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 629 #endif // _LP64
 630       break;
 631     }
 632 
 633     case T_VALUETYPE: // Fall through
 634     case T_OBJECT: {
 635       if (patch_code != lir_patch_none) {
 636         jobject2reg_with_patching(dest->as_register(), info);
 637       } else {
 638         __ movoop(dest->as_register(), c->as_jobject());
 639       }
 640       break;
 641     }
 642 
 643     case T_METADATA: {
 644       if (patch_code != lir_patch_none) {
 645         klass2reg_with_patching(dest->as_register(), info);
 646       } else {
 647         __ mov_metadata(dest->as_register(), c->as_metadata());
 648       }
 649       break;
 650     }
 651 
 652     case T_FLOAT: {
 653       if (dest->is_single_xmm()) {
 654         if (c->is_zero_float()) {
 655           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 656         } else {
 657           __ movflt(dest->as_xmm_float_reg(),
 658                    InternalAddress(float_constant(c->as_jfloat())));
 659         }
 660       } else {
 661         assert(dest->is_single_fpu(), "must be");
 662         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 663         if (c->is_zero_float()) {
 664           __ fldz();
 665         } else if (c->is_one_float()) {
 666           __ fld1();
 667         } else {
 668           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 669         }
 670       }
 671       break;
 672     }
 673 
 674     case T_DOUBLE: {
 675       if (dest->is_double_xmm()) {
 676         if (c->is_zero_double()) {
 677           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 678         } else {
 679           __ movdbl(dest->as_xmm_double_reg(),
 680                     InternalAddress(double_constant(c->as_jdouble())));
 681         }
 682       } else {
 683         assert(dest->is_double_fpu(), "must be");
 684         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 685         if (c->is_zero_double()) {
 686           __ fldz();
 687         } else if (c->is_one_double()) {
 688           __ fld1();
 689         } else {
 690           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 691         }
 692       }
 693       break;
 694     }
 695 
 696     default:
 697       ShouldNotReachHere();
 698   }
 699 }
 700 
 701 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 702   assert(src->is_constant(), "should not call otherwise");
 703   assert(dest->is_stack(), "should not call otherwise");
 704   LIR_Const* c = src->as_constant_ptr();
 705 
 706   switch (c->type()) {
 707     case T_INT:  // fall through
 708     case T_FLOAT:
 709       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 710       break;
 711 
 712     case T_ADDRESS:
 713       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 714       break;
 715 
 716     case T_VALUETYPE: // Fall through
 717     case T_OBJECT:
 718       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 719       break;
 720 
 721     case T_LONG:  // fall through
 722     case T_DOUBLE:
 723 #ifdef _LP64
 724       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 725                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 726 #else
 727       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 728                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 729       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 730                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 731 #endif // _LP64
 732       break;
 733 
 734     default:
 735       ShouldNotReachHere();
 736   }
 737 }
 738 
 739 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 740   assert(src->is_constant(), "should not call otherwise");
 741   assert(dest->is_address(), "should not call otherwise");
 742   LIR_Const* c = src->as_constant_ptr();
 743   LIR_Address* addr = dest->as_address_ptr();
 744 
 745   int null_check_here = code_offset();
 746   switch (type) {
 747     case T_INT:    // fall through
 748     case T_FLOAT:
 749       __ movl(as_Address(addr), c->as_jint_bits());
 750       break;
 751 
 752     case T_ADDRESS:
 753       __ movptr(as_Address(addr), c->as_jint_bits());
 754       break;
 755 
 756     case T_VALUETYPE: // fall through
 757     case T_OBJECT:  // fall through
 758     case T_ARRAY:
 759       if (c->as_jobject() == NULL) {
 760         if (UseCompressedOops && !wide) {
 761           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 762         } else {
 763 #ifdef _LP64
 764           __ xorptr(rscratch1, rscratch1);
 765           null_check_here = code_offset();
 766           __ movptr(as_Address(addr), rscratch1);
 767 #else
 768           __ movptr(as_Address(addr), NULL_WORD);
 769 #endif
 770         }
 771       } else {
 772         if (is_literal_address(addr)) {
 773           ShouldNotReachHere();
 774           __ movoop(as_Address(addr, noreg), c->as_jobject());
 775         } else {
 776 #ifdef _LP64
 777           __ movoop(rscratch1, c->as_jobject());
 778           if (UseCompressedOops && !wide) {
 779             __ encode_heap_oop(rscratch1);
 780             null_check_here = code_offset();
 781             __ movl(as_Address_lo(addr), rscratch1);
 782           } else {
 783             null_check_here = code_offset();
 784             __ movptr(as_Address_lo(addr), rscratch1);
 785           }
 786 #else
 787           __ movoop(as_Address(addr), c->as_jobject());
 788 #endif
 789         }
 790       }
 791       break;
 792 
 793     case T_LONG:    // fall through
 794     case T_DOUBLE:
 795 #ifdef _LP64
 796       if (is_literal_address(addr)) {
 797         ShouldNotReachHere();
 798         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 799       } else {
 800         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 801         null_check_here = code_offset();
 802         __ movptr(as_Address_lo(addr), r10);
 803       }
 804 #else
 805       // Always reachable in 32bit so this doesn't produce useless move literal
 806       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 807       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 808 #endif // _LP64
 809       break;
 810 
 811     case T_BOOLEAN: // fall through
 812     case T_BYTE:
 813       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 814       break;
 815 
 816     case T_CHAR:    // fall through
 817     case T_SHORT:
 818       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 819       break;
 820 
 821     default:
 822       ShouldNotReachHere();
 823   };
 824 
 825   if (info != NULL) {
 826     add_debug_info_for_null_check(null_check_here, info);
 827   }
 828 }
 829 
 830 
 831 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 832   assert(src->is_register(), "should not call otherwise");
 833   assert(dest->is_register(), "should not call otherwise");
 834 
 835   // move between cpu-registers
 836   if (dest->is_single_cpu()) {
 837 #ifdef _LP64
 838     if (src->type() == T_LONG) {
 839       // Can do LONG -> OBJECT
 840       move_regs(src->as_register_lo(), dest->as_register());
 841       return;
 842     }
 843 #endif
 844     assert(src->is_single_cpu(), "must match");
 845     if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
 846       __ verify_oop(src->as_register());
 847     }
 848     move_regs(src->as_register(), dest->as_register());
 849 
 850   } else if (dest->is_double_cpu()) {
 851 #ifdef _LP64
 852     if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
 853       // Surprising to me but we can see move of a long to t_object
 854       __ verify_oop(src->as_register());
 855       move_regs(src->as_register(), dest->as_register_lo());
 856       return;
 857     }
 858 #endif
 859     assert(src->is_double_cpu(), "must match");
 860     Register f_lo = src->as_register_lo();
 861     Register f_hi = src->as_register_hi();
 862     Register t_lo = dest->as_register_lo();
 863     Register t_hi = dest->as_register_hi();
 864 #ifdef _LP64
 865     assert(f_hi == f_lo, "must be same");
 866     assert(t_hi == t_lo, "must be same");
 867     move_regs(f_lo, t_lo);
 868 #else
 869     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 870 
 871 
 872     if (f_lo == t_hi && f_hi == t_lo) {
 873       swap_reg(f_lo, f_hi);
 874     } else if (f_hi == t_lo) {
 875       assert(f_lo != t_hi, "overwriting register");
 876       move_regs(f_hi, t_hi);
 877       move_regs(f_lo, t_lo);
 878     } else {
 879       assert(f_hi != t_lo, "overwriting register");
 880       move_regs(f_lo, t_lo);
 881       move_regs(f_hi, t_hi);
 882     }
 883 #endif // LP64
 884 
 885     // special moves from fpu-register to xmm-register
 886     // necessary for method results
 887   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 888     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 889     __ fld_s(Address(rsp, 0));
 890   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 891     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 892     __ fld_d(Address(rsp, 0));
 893   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 894     __ fstp_s(Address(rsp, 0));
 895     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 896   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 897     __ fstp_d(Address(rsp, 0));
 898     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 899 
 900     // move between xmm-registers
 901   } else if (dest->is_single_xmm()) {
 902     assert(src->is_single_xmm(), "must match");
 903     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 904   } else if (dest->is_double_xmm()) {
 905     assert(src->is_double_xmm(), "must match");
 906     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 907 
 908     // move between fpu-registers (no instruction necessary because of fpu-stack)
 909   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 910     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 911     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 912   } else {
 913     ShouldNotReachHere();
 914   }
 915 }
 916 
 917 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 918   assert(src->is_register(), "should not call otherwise");
 919   assert(dest->is_stack(), "should not call otherwise");
 920 
 921   if (src->is_single_cpu()) {
 922     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 923     if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) {
 924       __ verify_oop(src->as_register());
 925       __ movptr (dst, src->as_register());
 926     } else if (type == T_METADATA) {
 927       __ movptr (dst, src->as_register());
 928     } else {
 929       __ movl (dst, src->as_register());
 930     }
 931 
 932   } else if (src->is_double_cpu()) {
 933     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 934     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 935     __ movptr (dstLO, src->as_register_lo());
 936     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 937 
 938   } else if (src->is_single_xmm()) {
 939     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 940     __ movflt(dst_addr, src->as_xmm_float_reg());
 941 
 942   } else if (src->is_double_xmm()) {
 943     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 944     __ movdbl(dst_addr, src->as_xmm_double_reg());
 945 
 946   } else if (src->is_single_fpu()) {
 947     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 948     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 949     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 950     else                   __ fst_s  (dst_addr);
 951 
 952   } else if (src->is_double_fpu()) {
 953     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 954     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 955     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 956     else                   __ fst_d  (dst_addr);
 957 
 958   } else {
 959     ShouldNotReachHere();
 960   }
 961 }
 962 
 963 
 964 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 965   LIR_Address* to_addr = dest->as_address_ptr();
 966   PatchingStub* patch = NULL;
 967   Register compressed_src = rscratch1;
 968 
 969   if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
 970     __ verify_oop(src->as_register());
 971 #ifdef _LP64
 972     if (UseCompressedOops && !wide) {
 973       __ movptr(compressed_src, src->as_register());
 974       __ encode_heap_oop(compressed_src);
 975       if (patch_code != lir_patch_none) {
 976         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 977       }
 978     }
 979 #endif
 980   }
 981 
 982   if (patch_code != lir_patch_none) {
 983     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 984     Address toa = as_Address(to_addr);
 985     assert(toa.disp() != 0, "must have");
 986   }
 987 
 988   int null_check_here = code_offset();
 989   switch (type) {
 990     case T_FLOAT: {
 991       if (src->is_single_xmm()) {
 992         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 993       } else {
 994         assert(src->is_single_fpu(), "must be");
 995         assert(src->fpu_regnr() == 0, "argument must be on TOS");
 996         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
 997         else                    __ fst_s (as_Address(to_addr));
 998       }
 999       break;
1000     }
1001 
1002     case T_DOUBLE: {
1003       if (src->is_double_xmm()) {
1004         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1005       } else {
1006         assert(src->is_double_fpu(), "must be");
1007         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1008         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1009         else                    __ fst_d (as_Address(to_addr));
1010       }
1011       break;
1012     }
1013 
1014     case T_VALUETYPE: // fall through
1015     case T_ARRAY:   // fall through
1016     case T_OBJECT:  // fall through
1017       if (UseCompressedOops && !wide) {
1018         __ movl(as_Address(to_addr), compressed_src);
1019       } else {
1020         __ movptr(as_Address(to_addr), src->as_register());
1021       }
1022       break;
1023     case T_METADATA:
1024       // We get here to store a method pointer to the stack to pass to
1025       // a dtrace runtime call. This can't work on 64 bit with
1026       // compressed klass ptrs: T_METADATA can be a compressed klass
1027       // ptr or a 64 bit method pointer.
1028       LP64_ONLY(ShouldNotReachHere());
1029       __ movptr(as_Address(to_addr), src->as_register());
1030       break;
1031     case T_ADDRESS:
1032       __ movptr(as_Address(to_addr), src->as_register());
1033       break;
1034     case T_INT:
1035       __ movl(as_Address(to_addr), src->as_register());
1036       break;
1037 
1038     case T_LONG: {
1039       Register from_lo = src->as_register_lo();
1040       Register from_hi = src->as_register_hi();
1041 #ifdef _LP64
1042       __ movptr(as_Address_lo(to_addr), from_lo);
1043 #else
1044       Register base = to_addr->base()->as_register();
1045       Register index = noreg;
1046       if (to_addr->index()->is_register()) {
1047         index = to_addr->index()->as_register();
1048       }
1049       if (base == from_lo || index == from_lo) {
1050         assert(base != from_hi, "can't be");
1051         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1052         __ movl(as_Address_hi(to_addr), from_hi);
1053         if (patch != NULL) {
1054           patching_epilog(patch, lir_patch_high, base, info);
1055           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1056           patch_code = lir_patch_low;
1057         }
1058         __ movl(as_Address_lo(to_addr), from_lo);
1059       } else {
1060         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1061         __ movl(as_Address_lo(to_addr), from_lo);
1062         if (patch != NULL) {
1063           patching_epilog(patch, lir_patch_low, base, info);
1064           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1065           patch_code = lir_patch_high;
1066         }
1067         __ movl(as_Address_hi(to_addr), from_hi);
1068       }
1069 #endif // _LP64
1070       break;
1071     }
1072 
1073     case T_BYTE:    // fall through
1074     case T_BOOLEAN: {
1075       Register src_reg = src->as_register();
1076       Address dst_addr = as_Address(to_addr);
1077       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1078       __ movb(dst_addr, src_reg);
1079       break;
1080     }
1081 
1082     case T_CHAR:    // fall through
1083     case T_SHORT:
1084       __ movw(as_Address(to_addr), src->as_register());
1085       break;
1086 
1087     default:
1088       ShouldNotReachHere();
1089   }
1090   if (info != NULL) {
1091     add_debug_info_for_null_check(null_check_here, info);
1092   }
1093 
1094   if (patch_code != lir_patch_none) {
1095     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1096   }
1097 }
1098 
1099 
1100 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1101   assert(src->is_stack(), "should not call otherwise");
1102   assert(dest->is_register(), "should not call otherwise");
1103 
1104   if (dest->is_single_cpu()) {
1105     if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1106       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1107       __ verify_oop(dest->as_register());
1108     } else if (type == T_METADATA) {
1109       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1110     } else {
1111       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1112     }
1113 
1114   } else if (dest->is_double_cpu()) {
1115     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1116     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1117     __ movptr(dest->as_register_lo(), src_addr_LO);
1118     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1119 
1120   } else if (dest->is_single_xmm()) {
1121     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1122     __ movflt(dest->as_xmm_float_reg(), src_addr);
1123 
1124   } else if (dest->is_double_xmm()) {
1125     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1126     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1127 
1128   } else if (dest->is_single_fpu()) {
1129     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1130     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1131     __ fld_s(src_addr);
1132 
1133   } else if (dest->is_double_fpu()) {
1134     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1135     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1136     __ fld_d(src_addr);
1137 
1138   } else {
1139     ShouldNotReachHere();
1140   }
1141 }
1142 
1143 
1144 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1145   if (src->is_single_stack()) {
1146     if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) {
1147       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1148       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1149     } else {
1150 #ifndef _LP64
1151       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1152       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1153 #else
1154       //no pushl on 64bits
1155       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1156       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1157 #endif
1158     }
1159 
1160   } else if (src->is_double_stack()) {
1161 #ifdef _LP64
1162     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1163     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1164 #else
1165     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1166     // push and pop the part at src + wordSize, adding wordSize for the previous push
1167     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1168     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1169     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1170 #endif // _LP64
1171 
1172   } else {
1173     ShouldNotReachHere();
1174   }
1175 }
1176 
1177 
1178 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1179   assert(src->is_address(), "should not call otherwise");
1180   assert(dest->is_register(), "should not call otherwise");
1181 
1182   LIR_Address* addr = src->as_address_ptr();
1183   Address from_addr = as_Address(addr);
1184 
1185   if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
1186     __ verify_oop(addr->base()->as_pointer_register());
1187   }
1188 
1189   switch (type) {
1190     case T_BOOLEAN: // fall through
1191     case T_BYTE:    // fall through
1192     case T_CHAR:    // fall through
1193     case T_SHORT:
1194       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1195         // on pre P6 processors we may get partial register stalls
1196         // so blow away the value of to_rinfo before loading a
1197         // partial word into it.  Do it here so that it precedes
1198         // the potential patch point below.
1199         __ xorptr(dest->as_register(), dest->as_register());
1200       }
1201       break;
1202    default:
1203      break;
1204   }
1205 
1206   PatchingStub* patch = NULL;
1207   if (patch_code != lir_patch_none) {
1208     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1209     assert(from_addr.disp() != 0, "must have");
1210   }
1211   if (info != NULL) {
1212     add_debug_info_for_null_check_here(info);
1213   }
1214 
1215   switch (type) {
1216     case T_FLOAT: {
1217       if (dest->is_single_xmm()) {
1218         __ movflt(dest->as_xmm_float_reg(), from_addr);
1219       } else {
1220         assert(dest->is_single_fpu(), "must be");
1221         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1222         __ fld_s(from_addr);
1223       }
1224       break;
1225     }
1226 
1227     case T_DOUBLE: {
1228       if (dest->is_double_xmm()) {
1229         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1230       } else {
1231         assert(dest->is_double_fpu(), "must be");
1232         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1233         __ fld_d(from_addr);
1234       }
1235       break;
1236     }
1237 
1238     case T_VALUETYPE: // fall through
1239     case T_OBJECT:  // fall through
1240     case T_ARRAY:   // fall through
1241       if (UseCompressedOops && !wide) {
1242         __ movl(dest->as_register(), from_addr);
1243       } else {
1244         __ movptr(dest->as_register(), from_addr);
1245       }
1246       break;
1247 
1248     case T_ADDRESS:
1249       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1250         __ movl(dest->as_register(), from_addr);
1251       } else {
1252         __ movptr(dest->as_register(), from_addr);
1253       }
1254       break;
1255     case T_INT:
1256       __ movl(dest->as_register(), from_addr);
1257       break;
1258 
1259     case T_LONG: {
1260       Register to_lo = dest->as_register_lo();
1261       Register to_hi = dest->as_register_hi();
1262 #ifdef _LP64
1263       __ movptr(to_lo, as_Address_lo(addr));
1264 #else
1265       Register base = addr->base()->as_register();
1266       Register index = noreg;
1267       if (addr->index()->is_register()) {
1268         index = addr->index()->as_register();
1269       }
1270       if ((base == to_lo && index == to_hi) ||
1271           (base == to_hi && index == to_lo)) {
1272         // addresses with 2 registers are only formed as a result of
1273         // array access so this code will never have to deal with
1274         // patches or null checks.
1275         assert(info == NULL && patch == NULL, "must be");
1276         __ lea(to_hi, as_Address(addr));
1277         __ movl(to_lo, Address(to_hi, 0));
1278         __ movl(to_hi, Address(to_hi, BytesPerWord));
1279       } else if (base == to_lo || index == to_lo) {
1280         assert(base != to_hi, "can't be");
1281         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1282         __ movl(to_hi, as_Address_hi(addr));
1283         if (patch != NULL) {
1284           patching_epilog(patch, lir_patch_high, base, info);
1285           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1286           patch_code = lir_patch_low;
1287         }
1288         __ movl(to_lo, as_Address_lo(addr));
1289       } else {
1290         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1291         __ movl(to_lo, as_Address_lo(addr));
1292         if (patch != NULL) {
1293           patching_epilog(patch, lir_patch_low, base, info);
1294           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1295           patch_code = lir_patch_high;
1296         }
1297         __ movl(to_hi, as_Address_hi(addr));
1298       }
1299 #endif // _LP64
1300       break;
1301     }
1302 
1303     case T_BOOLEAN: // fall through
1304     case T_BYTE: {
1305       Register dest_reg = dest->as_register();
1306       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1307       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1308         __ movsbl(dest_reg, from_addr);
1309       } else {
1310         __ movb(dest_reg, from_addr);
1311         __ shll(dest_reg, 24);
1312         __ sarl(dest_reg, 24);
1313       }
1314       break;
1315     }
1316 
1317     case T_CHAR: {
1318       Register dest_reg = dest->as_register();
1319       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1320       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1321         __ movzwl(dest_reg, from_addr);
1322       } else {
1323         __ movw(dest_reg, from_addr);
1324       }
1325       break;
1326     }
1327 
1328     case T_SHORT: {
1329       Register dest_reg = dest->as_register();
1330       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1331         __ movswl(dest_reg, from_addr);
1332       } else {
1333         __ movw(dest_reg, from_addr);
1334         __ shll(dest_reg, 16);
1335         __ sarl(dest_reg, 16);
1336       }
1337       break;
1338     }
1339 
1340     default:
1341       ShouldNotReachHere();
1342   }
1343 
1344   if (patch != NULL) {
1345     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1346   }
1347 
1348   if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1349 #ifdef _LP64
1350     if (UseCompressedOops && !wide) {
1351       __ decode_heap_oop(dest->as_register());
1352     }
1353 #endif
1354 
1355     // Load barrier has not yet been applied, so ZGC can't verify the oop here
1356     if (!UseZGC) {
1357       __ verify_oop(dest->as_register());
1358     }
1359   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1360 #ifdef _LP64
1361     if (UseCompressedClassPointers) {
1362       __ decode_klass_not_null(dest->as_register());
1363     }
1364 #endif
1365   }
1366 }
1367 
1368 
1369 NEEDS_CLEANUP; // This could be static?
1370 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1371   int elem_size = type2aelembytes(type);
1372   switch (elem_size) {
1373     case 1: return Address::times_1;
1374     case 2: return Address::times_2;
1375     case 4: return Address::times_4;
1376     case 8: return Address::times_8;
1377   }
1378   ShouldNotReachHere();
1379   return Address::no_scale;
1380 }
1381 
1382 
1383 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1384   switch (op->code()) {
1385     case lir_idiv:
1386     case lir_irem:
1387       arithmetic_idiv(op->code(),
1388                       op->in_opr1(),
1389                       op->in_opr2(),
1390                       op->in_opr3(),
1391                       op->result_opr(),
1392                       op->info());
1393       break;
1394     case lir_fmad:
1395       __ fmad(op->result_opr()->as_xmm_double_reg(),
1396               op->in_opr1()->as_xmm_double_reg(),
1397               op->in_opr2()->as_xmm_double_reg(),
1398               op->in_opr3()->as_xmm_double_reg());
1399       break;
1400     case lir_fmaf:
1401       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1402               op->in_opr1()->as_xmm_float_reg(),
1403               op->in_opr2()->as_xmm_float_reg(),
1404               op->in_opr3()->as_xmm_float_reg());
1405       break;
1406     default:      ShouldNotReachHere(); break;
1407   }
1408 }
1409 
1410 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1411 #ifdef ASSERT
1412   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1413   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1414   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1415 #endif
1416 
1417   if (op->cond() == lir_cond_always) {
1418     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1419     __ jmp (*(op->label()));
1420   } else {
1421     Assembler::Condition acond = Assembler::zero;
1422     if (op->code() == lir_cond_float_branch) {
1423       assert(op->ublock() != NULL, "must have unordered successor");
1424       __ jcc(Assembler::parity, *(op->ublock()->label()));
1425       switch(op->cond()) {
1426         case lir_cond_equal:        acond = Assembler::equal;      break;
1427         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1428         case lir_cond_less:         acond = Assembler::below;      break;
1429         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1430         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1431         case lir_cond_greater:      acond = Assembler::above;      break;
1432         default:                         ShouldNotReachHere();
1433       }
1434     } else {
1435       switch (op->cond()) {
1436         case lir_cond_equal:        acond = Assembler::equal;       break;
1437         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1438         case lir_cond_less:         acond = Assembler::less;        break;
1439         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1440         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1441         case lir_cond_greater:      acond = Assembler::greater;     break;
1442         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1443         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1444         default:                         ShouldNotReachHere();
1445       }
1446     }
1447     __ jcc(acond,*(op->label()));
1448   }
1449 }
1450 
1451 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1452   LIR_Opr src  = op->in_opr();
1453   LIR_Opr dest = op->result_opr();
1454 
1455   switch (op->bytecode()) {
1456     case Bytecodes::_i2l:
1457 #ifdef _LP64
1458       __ movl2ptr(dest->as_register_lo(), src->as_register());
1459 #else
1460       move_regs(src->as_register(), dest->as_register_lo());
1461       move_regs(src->as_register(), dest->as_register_hi());
1462       __ sarl(dest->as_register_hi(), 31);
1463 #endif // LP64
1464       break;
1465 
1466     case Bytecodes::_l2i:
1467 #ifdef _LP64
1468       __ movl(dest->as_register(), src->as_register_lo());
1469 #else
1470       move_regs(src->as_register_lo(), dest->as_register());
1471 #endif
1472       break;
1473 
1474     case Bytecodes::_i2b:
1475       move_regs(src->as_register(), dest->as_register());
1476       __ sign_extend_byte(dest->as_register());
1477       break;
1478 
1479     case Bytecodes::_i2c:
1480       move_regs(src->as_register(), dest->as_register());
1481       __ andl(dest->as_register(), 0xFFFF);
1482       break;
1483 
1484     case Bytecodes::_i2s:
1485       move_regs(src->as_register(), dest->as_register());
1486       __ sign_extend_short(dest->as_register());
1487       break;
1488 
1489 
1490     case Bytecodes::_f2d:
1491     case Bytecodes::_d2f:
1492       if (dest->is_single_xmm()) {
1493         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1494       } else if (dest->is_double_xmm()) {
1495         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1496       } else {
1497         assert(src->fpu() == dest->fpu(), "register must be equal");
1498         // do nothing (float result is rounded later through spilling)
1499       }
1500       break;
1501 
1502     case Bytecodes::_i2f:
1503     case Bytecodes::_i2d:
1504       if (dest->is_single_xmm()) {
1505         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1506       } else if (dest->is_double_xmm()) {
1507         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1508       } else {
1509         assert(dest->fpu() == 0, "result must be on TOS");
1510         __ movl(Address(rsp, 0), src->as_register());
1511         __ fild_s(Address(rsp, 0));
1512       }
1513       break;
1514 
1515     case Bytecodes::_f2i:
1516     case Bytecodes::_d2i:
1517       if (src->is_single_xmm()) {
1518         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1519       } else if (src->is_double_xmm()) {
1520         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1521       } else {
1522         assert(src->fpu() == 0, "input must be on TOS");
1523         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1524         __ fist_s(Address(rsp, 0));
1525         __ movl(dest->as_register(), Address(rsp, 0));
1526         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1527       }
1528 
1529       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1530       assert(op->stub() != NULL, "stub required");
1531       __ cmpl(dest->as_register(), 0x80000000);
1532       __ jcc(Assembler::equal, *op->stub()->entry());
1533       __ bind(*op->stub()->continuation());
1534       break;
1535 
1536     case Bytecodes::_l2f:
1537     case Bytecodes::_l2d:
1538       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1539       assert(dest->fpu() == 0, "result must be on TOS");
1540 
1541       __ movptr(Address(rsp, 0),            src->as_register_lo());
1542       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1543       __ fild_d(Address(rsp, 0));
1544       // float result is rounded later through spilling
1545       break;
1546 
1547     case Bytecodes::_f2l:
1548     case Bytecodes::_d2l:
1549       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1550       assert(src->fpu() == 0, "input must be on TOS");
1551       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1552 
1553       // instruction sequence too long to inline it here
1554       {
1555         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1556       }
1557       break;
1558 
1559     default: ShouldNotReachHere();
1560   }
1561 }
1562 
1563 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1564   if (op->init_check()) {
1565     add_debug_info_for_null_check_here(op->stub()->info());
1566     __ cmpb(Address(op->klass()->as_register(),
1567                     InstanceKlass::init_state_offset()),
1568                     InstanceKlass::fully_initialized);
1569     __ jcc(Assembler::notEqual, *op->stub()->entry());
1570   }
1571   __ allocate_object(op->obj()->as_register(),
1572                      op->tmp1()->as_register(),
1573                      op->tmp2()->as_register(),
1574                      op->header_size(),
1575                      op->object_size(),
1576                      op->klass()->as_register(),
1577                      *op->stub()->entry());
1578   __ bind(*op->stub()->continuation());
1579 }
1580 
1581 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1582   Register len =  op->len()->as_register();
1583   LP64_ONLY( __ movslq(len, len); )
1584 
1585   if (UseSlowPath || op->type() == T_VALUETYPE ||
1586       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1587       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1588     __ jmp(*op->stub()->entry());
1589   } else {
1590     Register tmp1 = op->tmp1()->as_register();
1591     Register tmp2 = op->tmp2()->as_register();
1592     Register tmp3 = op->tmp3()->as_register();
1593     if (len == tmp1) {
1594       tmp1 = tmp3;
1595     } else if (len == tmp2) {
1596       tmp2 = tmp3;
1597     } else if (len == tmp3) {
1598       // everything is ok
1599     } else {
1600       __ mov(tmp3, len);
1601     }
1602     __ allocate_array(op->obj()->as_register(),
1603                       len,
1604                       tmp1,
1605                       tmp2,
1606                       arrayOopDesc::header_size(op->type()),
1607                       array_element_size(op->type()),
1608                       op->klass()->as_register(),
1609                       *op->stub()->entry());
1610   }
1611   __ bind(*op->stub()->continuation());
1612 }
1613 
1614 void LIR_Assembler::type_profile_helper(Register mdo,
1615                                         ciMethodData *md, ciProfileData *data,
1616                                         Register recv, Label* update_done) {
1617   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1618     Label next_test;
1619     // See if the receiver is receiver[n].
1620     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1621     __ jccb(Assembler::notEqual, next_test);
1622     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1623     __ addptr(data_addr, DataLayout::counter_increment);
1624     __ jmp(*update_done);
1625     __ bind(next_test);
1626   }
1627 
1628   // Didn't find receiver; find next empty slot and fill it in
1629   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1630     Label next_test;
1631     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1632     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1633     __ jccb(Assembler::notEqual, next_test);
1634     __ movptr(recv_addr, recv);
1635     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1636     __ jmp(*update_done);
1637     __ bind(next_test);
1638   }
1639 }
1640 
1641 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1642   // we always need a stub for the failure case.
1643   CodeStub* stub = op->stub();
1644   Register obj = op->object()->as_register();
1645   Register k_RInfo = op->tmp1()->as_register();
1646   Register klass_RInfo = op->tmp2()->as_register();
1647   Register dst = op->result_opr()->as_register();
1648   ciKlass* k = op->klass();
1649   Register Rtmp1 = noreg;
1650 
1651   // check if it needs to be profiled
1652   ciMethodData* md = NULL;
1653   ciProfileData* data = NULL;
1654 
1655   if (op->should_profile()) {
1656     ciMethod* method = op->profiled_method();
1657     assert(method != NULL, "Should have method");
1658     int bci = op->profiled_bci();
1659     md = method->method_data_or_null();
1660     assert(md != NULL, "Sanity");
1661     data = md->bci_to_data(bci);
1662     assert(data != NULL,                "need data for type check");
1663     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1664   }
1665   Label profile_cast_success, profile_cast_failure;
1666   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1667   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1668 
1669   if (obj == k_RInfo) {
1670     k_RInfo = dst;
1671   } else if (obj == klass_RInfo) {
1672     klass_RInfo = dst;
1673   }
1674   if (k->is_loaded() && !UseCompressedClassPointers) {
1675     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1676   } else {
1677     Rtmp1 = op->tmp3()->as_register();
1678     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1679   }
1680 
1681   assert_different_registers(obj, k_RInfo, klass_RInfo);
1682 
1683   __ cmpptr(obj, (int32_t)NULL_WORD);
1684   if (op->should_profile()) {
1685     Label not_null;
1686     __ jccb(Assembler::notEqual, not_null);
1687     // Object is null; update MDO and exit
1688     Register mdo  = klass_RInfo;
1689     __ mov_metadata(mdo, md->constant_encoding());
1690     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1691     int header_bits = BitData::null_seen_byte_constant();
1692     __ orb(data_addr, header_bits);
1693     __ jmp(*obj_is_null);
1694     __ bind(not_null);
1695   } else {
1696     __ jcc(Assembler::equal, *obj_is_null);
1697   }
1698 
1699   if (!k->is_loaded()) {
1700     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1701   } else {
1702 #ifdef _LP64
1703     __ mov_metadata(k_RInfo, k->constant_encoding());
1704 #endif // _LP64
1705   }
1706   __ verify_oop(obj);
1707 
1708   if (op->fast_check()) {
1709     // get object class
1710     // not a safepoint as obj null check happens earlier
1711 #ifdef _LP64
1712     if (UseCompressedClassPointers) {
1713       __ load_klass(Rtmp1, obj);
1714       __ cmpptr(k_RInfo, Rtmp1);
1715     } else {
1716       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1717     }
1718 #else
1719     if (k->is_loaded()) {
1720       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1721     } else {
1722       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1723     }
1724 #endif
1725     __ jcc(Assembler::notEqual, *failure_target);
1726     // successful cast, fall through to profile or jump
1727   } else {
1728     // get object class
1729     // not a safepoint as obj null check happens earlier
1730     __ load_klass(klass_RInfo, obj);
1731     if (k->is_loaded()) {
1732       // See if we get an immediate positive hit
1733 #ifdef _LP64
1734       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1735 #else
1736       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1737 #endif // _LP64
1738       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1739         __ jcc(Assembler::notEqual, *failure_target);
1740         // successful cast, fall through to profile or jump
1741       } else {
1742         // See if we get an immediate positive hit
1743         __ jcc(Assembler::equal, *success_target);
1744         // check for self
1745 #ifdef _LP64
1746         __ cmpptr(klass_RInfo, k_RInfo);
1747 #else
1748         __ cmpklass(klass_RInfo, k->constant_encoding());
1749 #endif // _LP64
1750         __ jcc(Assembler::equal, *success_target);
1751 
1752         __ push(klass_RInfo);
1753 #ifdef _LP64
1754         __ push(k_RInfo);
1755 #else
1756         __ pushklass(k->constant_encoding());
1757 #endif // _LP64
1758         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1759         __ pop(klass_RInfo);
1760         __ pop(klass_RInfo);
1761         // result is a boolean
1762         __ cmpl(klass_RInfo, 0);
1763         __ jcc(Assembler::equal, *failure_target);
1764         // successful cast, fall through to profile or jump
1765       }
1766     } else {
1767       // perform the fast part of the checking logic
1768       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1769       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1770       __ push(klass_RInfo);
1771       __ push(k_RInfo);
1772       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1773       __ pop(klass_RInfo);
1774       __ pop(k_RInfo);
1775       // result is a boolean
1776       __ cmpl(k_RInfo, 0);
1777       __ jcc(Assembler::equal, *failure_target);
1778       // successful cast, fall through to profile or jump
1779     }
1780   }
1781   if (op->should_profile()) {
1782     Register mdo  = klass_RInfo, recv = k_RInfo;
1783     __ bind(profile_cast_success);
1784     __ mov_metadata(mdo, md->constant_encoding());
1785     __ load_klass(recv, obj);
1786     Label update_done;
1787     type_profile_helper(mdo, md, data, recv, success);
1788     __ jmp(*success);
1789 
1790     __ bind(profile_cast_failure);
1791     __ mov_metadata(mdo, md->constant_encoding());
1792     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1793     __ subptr(counter_addr, DataLayout::counter_increment);
1794     __ jmp(*failure);
1795   }
1796   __ jmp(*success);
1797 }
1798 
1799 
1800 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1801   LIR_Code code = op->code();
1802   if (code == lir_store_check) {
1803     Register value = op->object()->as_register();
1804     Register array = op->array()->as_register();
1805     Register k_RInfo = op->tmp1()->as_register();
1806     Register klass_RInfo = op->tmp2()->as_register();
1807     Register Rtmp1 = op->tmp3()->as_register();
1808 
1809     CodeStub* stub = op->stub();
1810 
1811     // check if it needs to be profiled
1812     ciMethodData* md = NULL;
1813     ciProfileData* data = NULL;
1814 
1815     if (op->should_profile()) {
1816       ciMethod* method = op->profiled_method();
1817       assert(method != NULL, "Should have method");
1818       int bci = op->profiled_bci();
1819       md = method->method_data_or_null();
1820       assert(md != NULL, "Sanity");
1821       data = md->bci_to_data(bci);
1822       assert(data != NULL,                "need data for type check");
1823       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1824     }
1825     Label profile_cast_success, profile_cast_failure, done;
1826     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1827     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1828 
1829     __ cmpptr(value, (int32_t)NULL_WORD);
1830     if (op->should_profile()) {
1831       Label not_null;
1832       __ jccb(Assembler::notEqual, not_null);
1833       // Object is null; update MDO and exit
1834       Register mdo  = klass_RInfo;
1835       __ mov_metadata(mdo, md->constant_encoding());
1836       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1837       int header_bits = BitData::null_seen_byte_constant();
1838       __ orb(data_addr, header_bits);
1839       __ jmp(done);
1840       __ bind(not_null);
1841     } else {
1842       __ jcc(Assembler::equal, done);
1843     }
1844 
1845     add_debug_info_for_null_check_here(op->info_for_exception());
1846     __ load_klass(k_RInfo, array);
1847     __ load_klass(klass_RInfo, value);
1848 
1849     // get instance klass (it's already uncompressed)
1850     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1851     // perform the fast part of the checking logic
1852     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1853     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1854     __ push(klass_RInfo);
1855     __ push(k_RInfo);
1856     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1857     __ pop(klass_RInfo);
1858     __ pop(k_RInfo);
1859     // result is a boolean
1860     __ cmpl(k_RInfo, 0);
1861     __ jcc(Assembler::equal, *failure_target);
1862     // fall through to the success case
1863 
1864     if (op->should_profile()) {
1865       Register mdo  = klass_RInfo, recv = k_RInfo;
1866       __ bind(profile_cast_success);
1867       __ mov_metadata(mdo, md->constant_encoding());
1868       __ load_klass(recv, value);
1869       Label update_done;
1870       type_profile_helper(mdo, md, data, recv, &done);
1871       __ jmpb(done);
1872 
1873       __ bind(profile_cast_failure);
1874       __ mov_metadata(mdo, md->constant_encoding());
1875       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1876       __ subptr(counter_addr, DataLayout::counter_increment);
1877       __ jmp(*stub->entry());
1878     }
1879 
1880     __ bind(done);
1881   } else
1882     if (code == lir_checkcast) {
1883       Register obj = op->object()->as_register();
1884       Register dst = op->result_opr()->as_register();
1885       Label success;
1886       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1887       __ bind(success);
1888       if (dst != obj) {
1889         __ mov(dst, obj);
1890       }
1891     } else
1892       if (code == lir_instanceof) {
1893         Register obj = op->object()->as_register();
1894         Register dst = op->result_opr()->as_register();
1895         Label success, failure, done;
1896         emit_typecheck_helper(op, &success, &failure, &failure);
1897         __ bind(failure);
1898         __ xorptr(dst, dst);
1899         __ jmpb(done);
1900         __ bind(success);
1901         __ movptr(dst, 1);
1902         __ bind(done);
1903       } else {
1904         ShouldNotReachHere();
1905       }
1906 
1907 }
1908 
1909 
1910 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1911   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1912     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1913     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1914     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1915     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1916     Register addr = op->addr()->as_register();
1917     if (os::is_MP()) {
1918       __ lock();
1919     }
1920     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1921 
1922   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1923     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1924     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1925     Register newval = op->new_value()->as_register();
1926     Register cmpval = op->cmp_value()->as_register();
1927     assert(cmpval == rax, "wrong register");
1928     assert(newval != NULL, "new val must be register");
1929     assert(cmpval != newval, "cmp and new values must be in different registers");
1930     assert(cmpval != addr, "cmp and addr must be in different registers");
1931     assert(newval != addr, "new value and addr must be in different registers");
1932 
1933     if ( op->code() == lir_cas_obj) {
1934 #ifdef _LP64
1935       if (UseCompressedOops) {
1936         __ encode_heap_oop(cmpval);
1937         __ mov(rscratch1, newval);
1938         __ encode_heap_oop(rscratch1);
1939         if (os::is_MP()) {
1940           __ lock();
1941         }
1942         // cmpval (rax) is implicitly used by this instruction
1943         __ cmpxchgl(rscratch1, Address(addr, 0));
1944       } else
1945 #endif
1946       {
1947         if (os::is_MP()) {
1948           __ lock();
1949         }
1950         __ cmpxchgptr(newval, Address(addr, 0));
1951       }
1952     } else {
1953       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1954       if (os::is_MP()) {
1955         __ lock();
1956       }
1957       __ cmpxchgl(newval, Address(addr, 0));
1958     }
1959 #ifdef _LP64
1960   } else if (op->code() == lir_cas_long) {
1961     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1962     Register newval = op->new_value()->as_register_lo();
1963     Register cmpval = op->cmp_value()->as_register_lo();
1964     assert(cmpval == rax, "wrong register");
1965     assert(newval != NULL, "new val must be register");
1966     assert(cmpval != newval, "cmp and new values must be in different registers");
1967     assert(cmpval != addr, "cmp and addr must be in different registers");
1968     assert(newval != addr, "new value and addr must be in different registers");
1969     if (os::is_MP()) {
1970       __ lock();
1971     }
1972     __ cmpxchgq(newval, Address(addr, 0));
1973 #endif // _LP64
1974   } else {
1975     Unimplemented();
1976   }
1977 }
1978 
1979 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1980   Assembler::Condition acond, ncond;
1981   switch (condition) {
1982     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1983     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1984     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
1985     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
1986     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
1987     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
1988     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
1989     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
1990     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
1991                                 ShouldNotReachHere();
1992   }
1993 
1994   if (opr1->is_cpu_register()) {
1995     reg2reg(opr1, result);
1996   } else if (opr1->is_stack()) {
1997     stack2reg(opr1, result, result->type());
1998   } else if (opr1->is_constant()) {
1999     const2reg(opr1, result, lir_patch_none, NULL);
2000   } else {
2001     ShouldNotReachHere();
2002   }
2003 
2004   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2005     // optimized version that does not require a branch
2006     if (opr2->is_single_cpu()) {
2007       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2008       __ cmov(ncond, result->as_register(), opr2->as_register());
2009     } else if (opr2->is_double_cpu()) {
2010       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2011       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2012       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2013       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2014     } else if (opr2->is_single_stack()) {
2015       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2016     } else if (opr2->is_double_stack()) {
2017       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2018       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2019     } else {
2020       ShouldNotReachHere();
2021     }
2022 
2023   } else {
2024     Label skip;
2025     __ jcc (acond, skip);
2026     if (opr2->is_cpu_register()) {
2027       reg2reg(opr2, result);
2028     } else if (opr2->is_stack()) {
2029       stack2reg(opr2, result, result->type());
2030     } else if (opr2->is_constant()) {
2031       const2reg(opr2, result, lir_patch_none, NULL);
2032     } else {
2033       ShouldNotReachHere();
2034     }
2035     __ bind(skip);
2036   }
2037 }
2038 
2039 
2040 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2041   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2042 
2043   if (left->is_single_cpu()) {
2044     assert(left == dest, "left and dest must be equal");
2045     Register lreg = left->as_register();
2046 
2047     if (right->is_single_cpu()) {
2048       // cpu register - cpu register
2049       Register rreg = right->as_register();
2050       switch (code) {
2051         case lir_add: __ addl (lreg, rreg); break;
2052         case lir_sub: __ subl (lreg, rreg); break;
2053         case lir_mul: __ imull(lreg, rreg); break;
2054         default:      ShouldNotReachHere();
2055       }
2056 
2057     } else if (right->is_stack()) {
2058       // cpu register - stack
2059       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2060       switch (code) {
2061         case lir_add: __ addl(lreg, raddr); break;
2062         case lir_sub: __ subl(lreg, raddr); break;
2063         default:      ShouldNotReachHere();
2064       }
2065 
2066     } else if (right->is_constant()) {
2067       // cpu register - constant
2068       jint c = right->as_constant_ptr()->as_jint();
2069       switch (code) {
2070         case lir_add: {
2071           __ incrementl(lreg, c);
2072           break;
2073         }
2074         case lir_sub: {
2075           __ decrementl(lreg, c);
2076           break;
2077         }
2078         default: ShouldNotReachHere();
2079       }
2080 
2081     } else {
2082       ShouldNotReachHere();
2083     }
2084 
2085   } else if (left->is_double_cpu()) {
2086     assert(left == dest, "left and dest must be equal");
2087     Register lreg_lo = left->as_register_lo();
2088     Register lreg_hi = left->as_register_hi();
2089 
2090     if (right->is_double_cpu()) {
2091       // cpu register - cpu register
2092       Register rreg_lo = right->as_register_lo();
2093       Register rreg_hi = right->as_register_hi();
2094       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2095       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2096       switch (code) {
2097         case lir_add:
2098           __ addptr(lreg_lo, rreg_lo);
2099           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2100           break;
2101         case lir_sub:
2102           __ subptr(lreg_lo, rreg_lo);
2103           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2104           break;
2105         case lir_mul:
2106 #ifdef _LP64
2107           __ imulq(lreg_lo, rreg_lo);
2108 #else
2109           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2110           __ imull(lreg_hi, rreg_lo);
2111           __ imull(rreg_hi, lreg_lo);
2112           __ addl (rreg_hi, lreg_hi);
2113           __ mull (rreg_lo);
2114           __ addl (lreg_hi, rreg_hi);
2115 #endif // _LP64
2116           break;
2117         default:
2118           ShouldNotReachHere();
2119       }
2120 
2121     } else if (right->is_constant()) {
2122       // cpu register - constant
2123 #ifdef _LP64
2124       jlong c = right->as_constant_ptr()->as_jlong_bits();
2125       __ movptr(r10, (intptr_t) c);
2126       switch (code) {
2127         case lir_add:
2128           __ addptr(lreg_lo, r10);
2129           break;
2130         case lir_sub:
2131           __ subptr(lreg_lo, r10);
2132           break;
2133         default:
2134           ShouldNotReachHere();
2135       }
2136 #else
2137       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2138       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2139       switch (code) {
2140         case lir_add:
2141           __ addptr(lreg_lo, c_lo);
2142           __ adcl(lreg_hi, c_hi);
2143           break;
2144         case lir_sub:
2145           __ subptr(lreg_lo, c_lo);
2146           __ sbbl(lreg_hi, c_hi);
2147           break;
2148         default:
2149           ShouldNotReachHere();
2150       }
2151 #endif // _LP64
2152 
2153     } else {
2154       ShouldNotReachHere();
2155     }
2156 
2157   } else if (left->is_single_xmm()) {
2158     assert(left == dest, "left and dest must be equal");
2159     XMMRegister lreg = left->as_xmm_float_reg();
2160 
2161     if (right->is_single_xmm()) {
2162       XMMRegister rreg = right->as_xmm_float_reg();
2163       switch (code) {
2164         case lir_add: __ addss(lreg, rreg);  break;
2165         case lir_sub: __ subss(lreg, rreg);  break;
2166         case lir_mul_strictfp: // fall through
2167         case lir_mul: __ mulss(lreg, rreg);  break;
2168         case lir_div_strictfp: // fall through
2169         case lir_div: __ divss(lreg, rreg);  break;
2170         default: ShouldNotReachHere();
2171       }
2172     } else {
2173       Address raddr;
2174       if (right->is_single_stack()) {
2175         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2176       } else if (right->is_constant()) {
2177         // hack for now
2178         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2179       } else {
2180         ShouldNotReachHere();
2181       }
2182       switch (code) {
2183         case lir_add: __ addss(lreg, raddr);  break;
2184         case lir_sub: __ subss(lreg, raddr);  break;
2185         case lir_mul_strictfp: // fall through
2186         case lir_mul: __ mulss(lreg, raddr);  break;
2187         case lir_div_strictfp: // fall through
2188         case lir_div: __ divss(lreg, raddr);  break;
2189         default: ShouldNotReachHere();
2190       }
2191     }
2192 
2193   } else if (left->is_double_xmm()) {
2194     assert(left == dest, "left and dest must be equal");
2195 
2196     XMMRegister lreg = left->as_xmm_double_reg();
2197     if (right->is_double_xmm()) {
2198       XMMRegister rreg = right->as_xmm_double_reg();
2199       switch (code) {
2200         case lir_add: __ addsd(lreg, rreg);  break;
2201         case lir_sub: __ subsd(lreg, rreg);  break;
2202         case lir_mul_strictfp: // fall through
2203         case lir_mul: __ mulsd(lreg, rreg);  break;
2204         case lir_div_strictfp: // fall through
2205         case lir_div: __ divsd(lreg, rreg);  break;
2206         default: ShouldNotReachHere();
2207       }
2208     } else {
2209       Address raddr;
2210       if (right->is_double_stack()) {
2211         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2212       } else if (right->is_constant()) {
2213         // hack for now
2214         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2215       } else {
2216         ShouldNotReachHere();
2217       }
2218       switch (code) {
2219         case lir_add: __ addsd(lreg, raddr);  break;
2220         case lir_sub: __ subsd(lreg, raddr);  break;
2221         case lir_mul_strictfp: // fall through
2222         case lir_mul: __ mulsd(lreg, raddr);  break;
2223         case lir_div_strictfp: // fall through
2224         case lir_div: __ divsd(lreg, raddr);  break;
2225         default: ShouldNotReachHere();
2226       }
2227     }
2228 
2229   } else if (left->is_single_fpu()) {
2230     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2231 
2232     if (right->is_single_fpu()) {
2233       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2234 
2235     } else {
2236       assert(left->fpu_regnr() == 0, "left must be on TOS");
2237       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2238 
2239       Address raddr;
2240       if (right->is_single_stack()) {
2241         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2242       } else if (right->is_constant()) {
2243         address const_addr = float_constant(right->as_jfloat());
2244         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2245         // hack for now
2246         raddr = __ as_Address(InternalAddress(const_addr));
2247       } else {
2248         ShouldNotReachHere();
2249       }
2250 
2251       switch (code) {
2252         case lir_add: __ fadd_s(raddr); break;
2253         case lir_sub: __ fsub_s(raddr); break;
2254         case lir_mul_strictfp: // fall through
2255         case lir_mul: __ fmul_s(raddr); break;
2256         case lir_div_strictfp: // fall through
2257         case lir_div: __ fdiv_s(raddr); break;
2258         default:      ShouldNotReachHere();
2259       }
2260     }
2261 
2262   } else if (left->is_double_fpu()) {
2263     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2264 
2265     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2266       // Double values require special handling for strictfp mul/div on x86
2267       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2268       __ fmulp(left->fpu_regnrLo() + 1);
2269     }
2270 
2271     if (right->is_double_fpu()) {
2272       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2273 
2274     } else {
2275       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2276       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2277 
2278       Address raddr;
2279       if (right->is_double_stack()) {
2280         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2281       } else if (right->is_constant()) {
2282         // hack for now
2283         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2284       } else {
2285         ShouldNotReachHere();
2286       }
2287 
2288       switch (code) {
2289         case lir_add: __ fadd_d(raddr); break;
2290         case lir_sub: __ fsub_d(raddr); break;
2291         case lir_mul_strictfp: // fall through
2292         case lir_mul: __ fmul_d(raddr); break;
2293         case lir_div_strictfp: // fall through
2294         case lir_div: __ fdiv_d(raddr); break;
2295         default: ShouldNotReachHere();
2296       }
2297     }
2298 
2299     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2300       // Double values require special handling for strictfp mul/div on x86
2301       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2302       __ fmulp(dest->fpu_regnrLo() + 1);
2303     }
2304 
2305   } else if (left->is_single_stack() || left->is_address()) {
2306     assert(left == dest, "left and dest must be equal");
2307 
2308     Address laddr;
2309     if (left->is_single_stack()) {
2310       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2311     } else if (left->is_address()) {
2312       laddr = as_Address(left->as_address_ptr());
2313     } else {
2314       ShouldNotReachHere();
2315     }
2316 
2317     if (right->is_single_cpu()) {
2318       Register rreg = right->as_register();
2319       switch (code) {
2320         case lir_add: __ addl(laddr, rreg); break;
2321         case lir_sub: __ subl(laddr, rreg); break;
2322         default:      ShouldNotReachHere();
2323       }
2324     } else if (right->is_constant()) {
2325       jint c = right->as_constant_ptr()->as_jint();
2326       switch (code) {
2327         case lir_add: {
2328           __ incrementl(laddr, c);
2329           break;
2330         }
2331         case lir_sub: {
2332           __ decrementl(laddr, c);
2333           break;
2334         }
2335         default: ShouldNotReachHere();
2336       }
2337     } else {
2338       ShouldNotReachHere();
2339     }
2340 
2341   } else {
2342     ShouldNotReachHere();
2343   }
2344 }
2345 
2346 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2347   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2348   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2349   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2350 
2351   bool left_is_tos = (left_index == 0);
2352   bool dest_is_tos = (dest_index == 0);
2353   int non_tos_index = (left_is_tos ? right_index : left_index);
2354 
2355   switch (code) {
2356     case lir_add:
2357       if (pop_fpu_stack)       __ faddp(non_tos_index);
2358       else if (dest_is_tos)    __ fadd (non_tos_index);
2359       else                     __ fadda(non_tos_index);
2360       break;
2361 
2362     case lir_sub:
2363       if (left_is_tos) {
2364         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2365         else if (dest_is_tos)  __ fsub  (non_tos_index);
2366         else                   __ fsubra(non_tos_index);
2367       } else {
2368         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2369         else if (dest_is_tos)  __ fsubr (non_tos_index);
2370         else                   __ fsuba (non_tos_index);
2371       }
2372       break;
2373 
2374     case lir_mul_strictfp: // fall through
2375     case lir_mul:
2376       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2377       else if (dest_is_tos)    __ fmul (non_tos_index);
2378       else                     __ fmula(non_tos_index);
2379       break;
2380 
2381     case lir_div_strictfp: // fall through
2382     case lir_div:
2383       if (left_is_tos) {
2384         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2385         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2386         else                   __ fdivra(non_tos_index);
2387       } else {
2388         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2389         else if (dest_is_tos)  __ fdivr (non_tos_index);
2390         else                   __ fdiva (non_tos_index);
2391       }
2392       break;
2393 
2394     case lir_rem:
2395       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2396       __ fremr(noreg);
2397       break;
2398 
2399     default:
2400       ShouldNotReachHere();
2401   }
2402 }
2403 
2404 
2405 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2406   if (value->is_double_xmm()) {
2407     switch(code) {
2408       case lir_abs :
2409         {
2410           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2411             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2412           }
2413           __ andpd(dest->as_xmm_double_reg(),
2414                     ExternalAddress((address)double_signmask_pool));
2415         }
2416         break;
2417 
2418       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2419       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2420       default      : ShouldNotReachHere();
2421     }
2422 
2423   } else if (value->is_double_fpu()) {
2424     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2425     switch(code) {
2426       case lir_abs   : __ fabs() ; break;
2427       case lir_sqrt  : __ fsqrt(); break;
2428       default      : ShouldNotReachHere();
2429     }
2430   } else {
2431     Unimplemented();
2432   }
2433 }
2434 
2435 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2436   // assert(left->destroys_register(), "check");
2437   if (left->is_single_cpu()) {
2438     Register reg = left->as_register();
2439     if (right->is_constant()) {
2440       int val = right->as_constant_ptr()->as_jint();
2441       switch (code) {
2442         case lir_logic_and: __ andl (reg, val); break;
2443         case lir_logic_or:  __ orl  (reg, val); break;
2444         case lir_logic_xor: __ xorl (reg, val); break;
2445         default: ShouldNotReachHere();
2446       }
2447     } else if (right->is_stack()) {
2448       // added support for stack operands
2449       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2450       switch (code) {
2451         case lir_logic_and: __ andl (reg, raddr); break;
2452         case lir_logic_or:  __ orl  (reg, raddr); break;
2453         case lir_logic_xor: __ xorl (reg, raddr); break;
2454         default: ShouldNotReachHere();
2455       }
2456     } else {
2457       Register rright = right->as_register();
2458       switch (code) {
2459         case lir_logic_and: __ andptr (reg, rright); break;
2460         case lir_logic_or : __ orptr  (reg, rright); break;
2461         case lir_logic_xor: __ xorptr (reg, rright); break;
2462         default: ShouldNotReachHere();
2463       }
2464     }
2465     move_regs(reg, dst->as_register());
2466   } else {
2467     Register l_lo = left->as_register_lo();
2468     Register l_hi = left->as_register_hi();
2469     if (right->is_constant()) {
2470 #ifdef _LP64
2471       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2472       switch (code) {
2473         case lir_logic_and:
2474           __ andq(l_lo, rscratch1);
2475           break;
2476         case lir_logic_or:
2477           __ orq(l_lo, rscratch1);
2478           break;
2479         case lir_logic_xor:
2480           __ xorq(l_lo, rscratch1);
2481           break;
2482         default: ShouldNotReachHere();
2483       }
2484 #else
2485       int r_lo = right->as_constant_ptr()->as_jint_lo();
2486       int r_hi = right->as_constant_ptr()->as_jint_hi();
2487       switch (code) {
2488         case lir_logic_and:
2489           __ andl(l_lo, r_lo);
2490           __ andl(l_hi, r_hi);
2491           break;
2492         case lir_logic_or:
2493           __ orl(l_lo, r_lo);
2494           __ orl(l_hi, r_hi);
2495           break;
2496         case lir_logic_xor:
2497           __ xorl(l_lo, r_lo);
2498           __ xorl(l_hi, r_hi);
2499           break;
2500         default: ShouldNotReachHere();
2501       }
2502 #endif // _LP64
2503     } else {
2504 #ifdef _LP64
2505       Register r_lo;
2506       if (right->type() == T_OBJECT || right->type() == T_ARRAY || right->type() == T_VALUETYPE) {
2507         r_lo = right->as_register();
2508       } else {
2509         r_lo = right->as_register_lo();
2510       }
2511 #else
2512       Register r_lo = right->as_register_lo();
2513       Register r_hi = right->as_register_hi();
2514       assert(l_lo != r_hi, "overwriting registers");
2515 #endif
2516       switch (code) {
2517         case lir_logic_and:
2518           __ andptr(l_lo, r_lo);
2519           NOT_LP64(__ andptr(l_hi, r_hi);)
2520           break;
2521         case lir_logic_or:
2522           __ orptr(l_lo, r_lo);
2523           NOT_LP64(__ orptr(l_hi, r_hi);)
2524           break;
2525         case lir_logic_xor:
2526           __ xorptr(l_lo, r_lo);
2527           NOT_LP64(__ xorptr(l_hi, r_hi);)
2528           break;
2529         default: ShouldNotReachHere();
2530       }
2531     }
2532 
2533     Register dst_lo = dst->as_register_lo();
2534     Register dst_hi = dst->as_register_hi();
2535 
2536 #ifdef _LP64
2537     move_regs(l_lo, dst_lo);
2538 #else
2539     if (dst_lo == l_hi) {
2540       assert(dst_hi != l_lo, "overwriting registers");
2541       move_regs(l_hi, dst_hi);
2542       move_regs(l_lo, dst_lo);
2543     } else {
2544       assert(dst_lo != l_hi, "overwriting registers");
2545       move_regs(l_lo, dst_lo);
2546       move_regs(l_hi, dst_hi);
2547     }
2548 #endif // _LP64
2549   }
2550 }
2551 
2552 
2553 // we assume that rax, and rdx can be overwritten
2554 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2555 
2556   assert(left->is_single_cpu(),   "left must be register");
2557   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2558   assert(result->is_single_cpu(), "result must be register");
2559 
2560   //  assert(left->destroys_register(), "check");
2561   //  assert(right->destroys_register(), "check");
2562 
2563   Register lreg = left->as_register();
2564   Register dreg = result->as_register();
2565 
2566   if (right->is_constant()) {
2567     int divisor = right->as_constant_ptr()->as_jint();
2568     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2569     if (code == lir_idiv) {
2570       assert(lreg == rax, "must be rax,");
2571       assert(temp->as_register() == rdx, "tmp register must be rdx");
2572       __ cdql(); // sign extend into rdx:rax
2573       if (divisor == 2) {
2574         __ subl(lreg, rdx);
2575       } else {
2576         __ andl(rdx, divisor - 1);
2577         __ addl(lreg, rdx);
2578       }
2579       __ sarl(lreg, log2_intptr(divisor));
2580       move_regs(lreg, dreg);
2581     } else if (code == lir_irem) {
2582       Label done;
2583       __ mov(dreg, lreg);
2584       __ andl(dreg, 0x80000000 | (divisor - 1));
2585       __ jcc(Assembler::positive, done);
2586       __ decrement(dreg);
2587       __ orl(dreg, ~(divisor - 1));
2588       __ increment(dreg);
2589       __ bind(done);
2590     } else {
2591       ShouldNotReachHere();
2592     }
2593   } else {
2594     Register rreg = right->as_register();
2595     assert(lreg == rax, "left register must be rax,");
2596     assert(rreg != rdx, "right register must not be rdx");
2597     assert(temp->as_register() == rdx, "tmp register must be rdx");
2598 
2599     move_regs(lreg, rax);
2600 
2601     int idivl_offset = __ corrected_idivl(rreg);
2602     if (ImplicitDiv0Checks) {
2603       add_debug_info_for_div0(idivl_offset, info);
2604     }
2605     if (code == lir_irem) {
2606       move_regs(rdx, dreg); // result is in rdx
2607     } else {
2608       move_regs(rax, dreg);
2609     }
2610   }
2611 }
2612 
2613 
2614 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2615   if (opr1->is_single_cpu()) {
2616     Register reg1 = opr1->as_register();
2617     if (opr2->is_single_cpu()) {
2618       // cpu register - cpu register
2619       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2620         __ cmpoop(reg1, opr2->as_register());
2621       } else {
2622         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
2623         __ cmpl(reg1, opr2->as_register());
2624       }
2625     } else if (opr2->is_stack()) {
2626       // cpu register - stack
2627       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
2628         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2629       } else {
2630         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2631       }
2632     } else if (opr2->is_constant()) {
2633       // cpu register - constant
2634       LIR_Const* c = opr2->as_constant_ptr();
2635       if (c->type() == T_INT) {
2636         __ cmpl(reg1, c->as_jint());
2637       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2638         // In 64bit oops are single register
2639         jobject o = c->as_jobject();
2640         if (o == NULL) {
2641           __ cmpptr(reg1, (int32_t)NULL_WORD);
2642         } else {
2643           __ cmpoop(reg1, o);
2644         }
2645       } else {
2646         fatal("unexpected type: %s", basictype_to_str(c->type()));
2647       }
2648       // cpu register - address
2649     } else if (opr2->is_address()) {
2650       if (op->info() != NULL) {
2651         add_debug_info_for_null_check_here(op->info());
2652       }
2653       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2654     } else {
2655       ShouldNotReachHere();
2656     }
2657 
2658   } else if(opr1->is_double_cpu()) {
2659     Register xlo = opr1->as_register_lo();
2660     Register xhi = opr1->as_register_hi();
2661     if (opr2->is_double_cpu()) {
2662 #ifdef _LP64
2663       __ cmpptr(xlo, opr2->as_register_lo());
2664 #else
2665       // cpu register - cpu register
2666       Register ylo = opr2->as_register_lo();
2667       Register yhi = opr2->as_register_hi();
2668       __ subl(xlo, ylo);
2669       __ sbbl(xhi, yhi);
2670       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2671         __ orl(xhi, xlo);
2672       }
2673 #endif // _LP64
2674     } else if (opr2->is_constant()) {
2675       // cpu register - constant 0
2676       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2677 #ifdef _LP64
2678       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2679 #else
2680       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2681       __ orl(xhi, xlo);
2682 #endif // _LP64
2683     } else {
2684       ShouldNotReachHere();
2685     }
2686 
2687   } else if (opr1->is_single_xmm()) {
2688     XMMRegister reg1 = opr1->as_xmm_float_reg();
2689     if (opr2->is_single_xmm()) {
2690       // xmm register - xmm register
2691       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2692     } else if (opr2->is_stack()) {
2693       // xmm register - stack
2694       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2695     } else if (opr2->is_constant()) {
2696       // xmm register - constant
2697       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2698     } else if (opr2->is_address()) {
2699       // xmm register - address
2700       if (op->info() != NULL) {
2701         add_debug_info_for_null_check_here(op->info());
2702       }
2703       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2704     } else {
2705       ShouldNotReachHere();
2706     }
2707 
2708   } else if (opr1->is_double_xmm()) {
2709     XMMRegister reg1 = opr1->as_xmm_double_reg();
2710     if (opr2->is_double_xmm()) {
2711       // xmm register - xmm register
2712       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2713     } else if (opr2->is_stack()) {
2714       // xmm register - stack
2715       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2716     } else if (opr2->is_constant()) {
2717       // xmm register - constant
2718       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2719     } else if (opr2->is_address()) {
2720       // xmm register - address
2721       if (op->info() != NULL) {
2722         add_debug_info_for_null_check_here(op->info());
2723       }
2724       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2725     } else {
2726       ShouldNotReachHere();
2727     }
2728 
2729   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2730     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2731     assert(opr2->is_fpu_register(), "both must be registers");
2732     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2733 
2734   } else if (opr1->is_address() && opr2->is_constant()) {
2735     LIR_Const* c = opr2->as_constant_ptr();
2736 #ifdef _LP64
2737     if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2738       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2739       __ movoop(rscratch1, c->as_jobject());
2740     }
2741 #endif // LP64
2742     if (op->info() != NULL) {
2743       add_debug_info_for_null_check_here(op->info());
2744     }
2745     // special case: address - constant
2746     LIR_Address* addr = opr1->as_address_ptr();
2747     if (c->type() == T_INT) {
2748       __ cmpl(as_Address(addr), c->as_jint());
2749     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) {
2750 #ifdef _LP64
2751       // %%% Make this explode if addr isn't reachable until we figure out a
2752       // better strategy by giving noreg as the temp for as_Address
2753       __ cmpoop(rscratch1, as_Address(addr, noreg));
2754 #else
2755       __ cmpoop(as_Address(addr), c->as_jobject());
2756 #endif // _LP64
2757     } else {
2758       ShouldNotReachHere();
2759     }
2760 
2761   } else {
2762     ShouldNotReachHere();
2763   }
2764 }
2765 
2766 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2767   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2768     if (left->is_single_xmm()) {
2769       assert(right->is_single_xmm(), "must match");
2770       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2771     } else if (left->is_double_xmm()) {
2772       assert(right->is_double_xmm(), "must match");
2773       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2774 
2775     } else {
2776       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2777       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2778 
2779       assert(left->fpu() == 0, "left must be on TOS");
2780       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2781                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2782     }
2783   } else {
2784     assert(code == lir_cmp_l2i, "check");
2785 #ifdef _LP64
2786     Label done;
2787     Register dest = dst->as_register();
2788     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2789     __ movl(dest, -1);
2790     __ jccb(Assembler::less, done);
2791     __ set_byte_if_not_zero(dest);
2792     __ movzbl(dest, dest);
2793     __ bind(done);
2794 #else
2795     __ lcmp2int(left->as_register_hi(),
2796                 left->as_register_lo(),
2797                 right->as_register_hi(),
2798                 right->as_register_lo());
2799     move_regs(left->as_register_hi(), dst->as_register());
2800 #endif // _LP64
2801   }
2802 }
2803 
2804 
2805 void LIR_Assembler::align_call(LIR_Code code) {
2806   if (os::is_MP()) {
2807     // make sure that the displacement word of the call ends up word aligned
2808     int offset = __ offset();
2809     switch (code) {
2810       case lir_static_call:
2811       case lir_optvirtual_call:
2812       case lir_dynamic_call:
2813         offset += NativeCall::displacement_offset;
2814         break;
2815       case lir_icvirtual_call:
2816         offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2817       break;
2818       case lir_virtual_call:  // currently, sparc-specific for niagara
2819       default: ShouldNotReachHere();
2820     }
2821     __ align(BytesPerWord, offset);
2822   }
2823 }
2824 
2825 
2826 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2827   assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2828          "must be aligned");
2829   __ call(AddressLiteral(op->addr(), rtype));
2830   add_call_info(code_offset(), op->info());
2831 }
2832 
2833 
2834 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2835   __ ic_call(op->addr());
2836   add_call_info(code_offset(), op->info());
2837   assert(!os::is_MP() ||
2838          (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2839          "must be aligned");
2840 }
2841 
2842 
2843 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2844 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2845   ShouldNotReachHere();
2846 }
2847 
2848 
2849 void LIR_Assembler::emit_static_call_stub() {
2850   address call_pc = __ pc();
2851   address stub = __ start_a_stub(call_stub_size());
2852   if (stub == NULL) {
2853     bailout("static call stub overflow");
2854     return;
2855   }
2856 
2857   int start = __ offset();
2858   if (os::is_MP()) {
2859     // make sure that the displacement word of the call ends up word aligned
2860     __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2861   }
2862   __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2863   __ mov_metadata(rbx, (Metadata*)NULL);
2864   // must be set to -1 at code generation time
2865   assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2866   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2867   __ jump(RuntimeAddress(__ pc()));
2868 
2869   if (UseAOT) {
2870     // Trampoline to aot code
2871     __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2872 #ifdef _LP64
2873     __ mov64(rax, CONST64(0));  // address is zapped till fixup time.
2874 #else
2875     __ movl(rax, 0xdeadffff);  // address is zapped till fixup time.
2876 #endif
2877     __ jmp(rax);
2878   }
2879   assert(__ offset() - start <= call_stub_size(), "stub too big");
2880   __ end_a_stub();
2881 }
2882 
2883 
2884 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2885   assert(exceptionOop->as_register() == rax, "must match");
2886   assert(exceptionPC->as_register() == rdx, "must match");
2887 
2888   // exception object is not added to oop map by LinearScan
2889   // (LinearScan assumes that no oops are in fixed registers)
2890   info->add_register_oop(exceptionOop);
2891   Runtime1::StubID unwind_id;
2892 
2893   // get current pc information
2894   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2895   int pc_for_athrow_offset = __ offset();
2896   InternalAddress pc_for_athrow(__ pc());
2897   __ lea(exceptionPC->as_register(), pc_for_athrow);
2898   add_call_info(pc_for_athrow_offset, info); // for exception handler
2899 
2900   __ verify_not_null_oop(rax);
2901   // search an exception handler (rax: exception oop, rdx: throwing pc)
2902   if (compilation()->has_fpu_code()) {
2903     unwind_id = Runtime1::handle_exception_id;
2904   } else {
2905     unwind_id = Runtime1::handle_exception_nofpu_id;
2906   }
2907   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2908 
2909   // enough room for two byte trap
2910   __ nop();
2911 }
2912 
2913 
2914 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2915   assert(exceptionOop->as_register() == rax, "must match");
2916 
2917   __ jmp(_unwind_handler_entry);
2918 }
2919 
2920 
2921 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2922 
2923   // optimized version for linear scan:
2924   // * count must be already in ECX (guaranteed by LinearScan)
2925   // * left and dest must be equal
2926   // * tmp must be unused
2927   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2928   assert(left == dest, "left and dest must be equal");
2929   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2930 
2931   if (left->is_single_cpu()) {
2932     Register value = left->as_register();
2933     assert(value != SHIFT_count, "left cannot be ECX");
2934 
2935     switch (code) {
2936       case lir_shl:  __ shll(value); break;
2937       case lir_shr:  __ sarl(value); break;
2938       case lir_ushr: __ shrl(value); break;
2939       default: ShouldNotReachHere();
2940     }
2941   } else if (left->is_double_cpu()) {
2942     Register lo = left->as_register_lo();
2943     Register hi = left->as_register_hi();
2944     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2945 #ifdef _LP64
2946     switch (code) {
2947       case lir_shl:  __ shlptr(lo);        break;
2948       case lir_shr:  __ sarptr(lo);        break;
2949       case lir_ushr: __ shrptr(lo);        break;
2950       default: ShouldNotReachHere();
2951     }
2952 #else
2953 
2954     switch (code) {
2955       case lir_shl:  __ lshl(hi, lo);        break;
2956       case lir_shr:  __ lshr(hi, lo, true);  break;
2957       case lir_ushr: __ lshr(hi, lo, false); break;
2958       default: ShouldNotReachHere();
2959     }
2960 #endif // LP64
2961   } else {
2962     ShouldNotReachHere();
2963   }
2964 }
2965 
2966 
2967 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2968   if (dest->is_single_cpu()) {
2969     // first move left into dest so that left is not destroyed by the shift
2970     Register value = dest->as_register();
2971     count = count & 0x1F; // Java spec
2972 
2973     move_regs(left->as_register(), value);
2974     switch (code) {
2975       case lir_shl:  __ shll(value, count); break;
2976       case lir_shr:  __ sarl(value, count); break;
2977       case lir_ushr: __ shrl(value, count); break;
2978       default: ShouldNotReachHere();
2979     }
2980   } else if (dest->is_double_cpu()) {
2981 #ifndef _LP64
2982     Unimplemented();
2983 #else
2984     // first move left into dest so that left is not destroyed by the shift
2985     Register value = dest->as_register_lo();
2986     count = count & 0x1F; // Java spec
2987 
2988     move_regs(left->as_register_lo(), value);
2989     switch (code) {
2990       case lir_shl:  __ shlptr(value, count); break;
2991       case lir_shr:  __ sarptr(value, count); break;
2992       case lir_ushr: __ shrptr(value, count); break;
2993       default: ShouldNotReachHere();
2994     }
2995 #endif // _LP64
2996   } else {
2997     ShouldNotReachHere();
2998   }
2999 }
3000 
3001 
3002 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3003   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3004   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3005   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3006   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3007 }
3008 
3009 
3010 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3011   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3012   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3013   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3014   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3015 }
3016 
3017 
3018 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
3019   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3020   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3021   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3022   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3023 }
3024 
3025 
3026 void LIR_Assembler::store_parameter(Metadata* m,  int offset_from_rsp_in_words) {
3027   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3028   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3029   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3030   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3031 }
3032 
3033 
3034 // This code replaces a call to arraycopy; no exception may
3035 // be thrown in this code, they must be thrown in the System.arraycopy
3036 // activation frame; we could save some checks if this would not be the case
3037 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3038   ciArrayKlass* default_type = op->expected_type();
3039   Register src = op->src()->as_register();
3040   Register dst = op->dst()->as_register();
3041   Register src_pos = op->src_pos()->as_register();
3042   Register dst_pos = op->dst_pos()->as_register();
3043   Register length  = op->length()->as_register();
3044   Register tmp = op->tmp()->as_register();
3045 
3046   __ resolve(ACCESS_READ, src);
3047   __ resolve(ACCESS_WRITE, dst);
3048 
3049   CodeStub* stub = op->stub();
3050   int flags = op->flags();
3051   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3052   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3053 
3054   // if we don't know anything, just go through the generic arraycopy
3055   if (default_type == NULL) {
3056     Label done;
3057     // save outgoing arguments on stack in case call to System.arraycopy is needed
3058     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3059     // for interpreter calling conventions. Now we have to do it in new style conventions.
3060     // For the moment until C1 gets the new register allocator I just force all the
3061     // args to the right place (except the register args) and then on the back side
3062     // reload the register args properly if we go slow path. Yuck
3063 
3064     // These are proper for the calling convention
3065     store_parameter(length, 2);
3066     store_parameter(dst_pos, 1);
3067     store_parameter(dst, 0);
3068 
3069     // these are just temporary placements until we need to reload
3070     store_parameter(src_pos, 3);
3071     store_parameter(src, 4);
3072     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3073 
3074     address copyfunc_addr = StubRoutines::generic_arraycopy();
3075     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3076 
3077     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3078 #ifdef _LP64
3079     // The arguments are in java calling convention so we can trivially shift them to C
3080     // convention
3081     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3082     __ mov(c_rarg0, j_rarg0);
3083     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3084     __ mov(c_rarg1, j_rarg1);
3085     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3086     __ mov(c_rarg2, j_rarg2);
3087     assert_different_registers(c_rarg3, j_rarg4);
3088     __ mov(c_rarg3, j_rarg3);
3089 #ifdef _WIN64
3090     // Allocate abi space for args but be sure to keep stack aligned
3091     __ subptr(rsp, 6*wordSize);
3092     store_parameter(j_rarg4, 4);
3093 #ifndef PRODUCT
3094     if (PrintC1Statistics) {
3095       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3096     }
3097 #endif
3098     __ call(RuntimeAddress(copyfunc_addr));
3099     __ addptr(rsp, 6*wordSize);
3100 #else
3101     __ mov(c_rarg4, j_rarg4);
3102 #ifndef PRODUCT
3103     if (PrintC1Statistics) {
3104       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3105     }
3106 #endif
3107     __ call(RuntimeAddress(copyfunc_addr));
3108 #endif // _WIN64
3109 #else
3110     __ push(length);
3111     __ push(dst_pos);
3112     __ push(dst);
3113     __ push(src_pos);
3114     __ push(src);
3115 
3116 #ifndef PRODUCT
3117     if (PrintC1Statistics) {
3118       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3119     }
3120 #endif
3121     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3122 
3123 #endif // _LP64
3124 
3125     __ cmpl(rax, 0);
3126     __ jcc(Assembler::equal, *stub->continuation());
3127 
3128     __ mov(tmp, rax);
3129     __ xorl(tmp, -1);
3130 
3131     // Reload values from the stack so they are where the stub
3132     // expects them.
3133     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3134     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3135     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3136     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3137     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3138 
3139     __ subl(length, tmp);
3140     __ addl(src_pos, tmp);
3141     __ addl(dst_pos, tmp);
3142     __ jmp(*stub->entry());
3143 
3144     __ bind(*stub->continuation());
3145     return;
3146   }
3147 
3148   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3149 
3150   int elem_size = type2aelembytes(basic_type);
3151   Address::ScaleFactor scale;
3152 
3153   switch (elem_size) {
3154     case 1 :
3155       scale = Address::times_1;
3156       break;
3157     case 2 :
3158       scale = Address::times_2;
3159       break;
3160     case 4 :
3161       scale = Address::times_4;
3162       break;
3163     case 8 :
3164       scale = Address::times_8;
3165       break;
3166     default:
3167       scale = Address::no_scale;
3168       ShouldNotReachHere();
3169   }
3170 
3171   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3172   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3173   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3174   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3175 
3176   // length and pos's are all sign extended at this point on 64bit
3177 
3178   // test for NULL
3179   if (flags & LIR_OpArrayCopy::src_null_check) {
3180     __ testptr(src, src);
3181     __ jcc(Assembler::zero, *stub->entry());
3182   }
3183   if (flags & LIR_OpArrayCopy::dst_null_check) {
3184     __ testptr(dst, dst);
3185     __ jcc(Assembler::zero, *stub->entry());
3186   }
3187 
3188   // If the compiler was not able to prove that exact type of the source or the destination
3189   // of the arraycopy is an array type, check at runtime if the source or the destination is
3190   // an instance type.
3191   if (flags & LIR_OpArrayCopy::type_check) {
3192     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3193       __ load_klass(tmp, dst);
3194       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3195       __ jcc(Assembler::greaterEqual, *stub->entry());
3196     }
3197 
3198     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3199       __ load_klass(tmp, src);
3200       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3201       __ jcc(Assembler::greaterEqual, *stub->entry());
3202     }
3203   }
3204 
3205   // check if negative
3206   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3207     __ testl(src_pos, src_pos);
3208     __ jcc(Assembler::less, *stub->entry());
3209   }
3210   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3211     __ testl(dst_pos, dst_pos);
3212     __ jcc(Assembler::less, *stub->entry());
3213   }
3214 
3215   if (flags & LIR_OpArrayCopy::src_range_check) {
3216     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3217     __ cmpl(tmp, src_length_addr);
3218     __ jcc(Assembler::above, *stub->entry());
3219   }
3220   if (flags & LIR_OpArrayCopy::dst_range_check) {
3221     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3222     __ cmpl(tmp, dst_length_addr);
3223     __ jcc(Assembler::above, *stub->entry());
3224   }
3225 
3226   if (flags & LIR_OpArrayCopy::length_positive_check) {
3227     __ testl(length, length);
3228     __ jcc(Assembler::less, *stub->entry());
3229   }
3230 
3231 #ifdef _LP64
3232   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3233   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3234 #endif
3235 
3236   if (flags & LIR_OpArrayCopy::type_check) {
3237     // We don't know the array types are compatible
3238     if (basic_type != T_OBJECT) {
3239       // Simple test for basic type arrays
3240       if (UseCompressedClassPointers) {
3241         __ movl(tmp, src_klass_addr);
3242         __ cmpl(tmp, dst_klass_addr);
3243       } else {
3244         __ movptr(tmp, src_klass_addr);
3245         __ cmpptr(tmp, dst_klass_addr);
3246       }
3247       __ jcc(Assembler::notEqual, *stub->entry());
3248     } else {
3249       // For object arrays, if src is a sub class of dst then we can
3250       // safely do the copy.
3251       Label cont, slow;
3252 
3253       __ push(src);
3254       __ push(dst);
3255 
3256       __ load_klass(src, src);
3257       __ load_klass(dst, dst);
3258 
3259       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3260 
3261       __ push(src);
3262       __ push(dst);
3263       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3264       __ pop(dst);
3265       __ pop(src);
3266 
3267       __ cmpl(src, 0);
3268       __ jcc(Assembler::notEqual, cont);
3269 
3270       __ bind(slow);
3271       __ pop(dst);
3272       __ pop(src);
3273 
3274       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3275       if (copyfunc_addr != NULL) { // use stub if available
3276         // src is not a sub class of dst so we have to do a
3277         // per-element check.
3278 
3279         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3280         if ((flags & mask) != mask) {
3281           // Check that at least both of them object arrays.
3282           assert(flags & mask, "one of the two should be known to be an object array");
3283 
3284           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3285             __ load_klass(tmp, src);
3286           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3287             __ load_klass(tmp, dst);
3288           }
3289           int lh_offset = in_bytes(Klass::layout_helper_offset());
3290           Address klass_lh_addr(tmp, lh_offset);
3291           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3292           __ cmpl(klass_lh_addr, objArray_lh);
3293           __ jcc(Assembler::notEqual, *stub->entry());
3294         }
3295 
3296        // Spill because stubs can use any register they like and it's
3297        // easier to restore just those that we care about.
3298        store_parameter(dst, 0);
3299        store_parameter(dst_pos, 1);
3300        store_parameter(length, 2);
3301        store_parameter(src_pos, 3);
3302        store_parameter(src, 4);
3303 
3304 #ifndef _LP64
3305         __ movptr(tmp, dst_klass_addr);
3306         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3307         __ push(tmp);
3308         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3309         __ push(tmp);
3310         __ push(length);
3311         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3312         __ push(tmp);
3313         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3314         __ push(tmp);
3315 
3316         __ call_VM_leaf(copyfunc_addr, 5);
3317 #else
3318         __ movl2ptr(length, length); //higher 32bits must be null
3319 
3320         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3321         assert_different_registers(c_rarg0, dst, dst_pos, length);
3322         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3323         assert_different_registers(c_rarg1, dst, length);
3324 
3325         __ mov(c_rarg2, length);
3326         assert_different_registers(c_rarg2, dst);
3327 
3328 #ifdef _WIN64
3329         // Allocate abi space for args but be sure to keep stack aligned
3330         __ subptr(rsp, 6*wordSize);
3331         __ load_klass(c_rarg3, dst);
3332         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3333         store_parameter(c_rarg3, 4);
3334         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3335         __ call(RuntimeAddress(copyfunc_addr));
3336         __ addptr(rsp, 6*wordSize);
3337 #else
3338         __ load_klass(c_rarg4, dst);
3339         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3340         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3341         __ call(RuntimeAddress(copyfunc_addr));
3342 #endif
3343 
3344 #endif
3345 
3346 #ifndef PRODUCT
3347         if (PrintC1Statistics) {
3348           Label failed;
3349           __ testl(rax, rax);
3350           __ jcc(Assembler::notZero, failed);
3351           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3352           __ bind(failed);
3353         }
3354 #endif
3355 
3356         __ testl(rax, rax);
3357         __ jcc(Assembler::zero, *stub->continuation());
3358 
3359 #ifndef PRODUCT
3360         if (PrintC1Statistics) {
3361           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3362         }
3363 #endif
3364 
3365         __ mov(tmp, rax);
3366 
3367         __ xorl(tmp, -1);
3368 
3369         // Restore previously spilled arguments
3370         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3371         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3372         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3373         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3374         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3375 
3376 
3377         __ subl(length, tmp);
3378         __ addl(src_pos, tmp);
3379         __ addl(dst_pos, tmp);
3380       }
3381 
3382       __ jmp(*stub->entry());
3383 
3384       __ bind(cont);
3385       __ pop(dst);
3386       __ pop(src);
3387     }
3388   }
3389 
3390 #ifdef ASSERT
3391   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3392     // Sanity check the known type with the incoming class.  For the
3393     // primitive case the types must match exactly with src.klass and
3394     // dst.klass each exactly matching the default type.  For the
3395     // object array case, if no type check is needed then either the
3396     // dst type is exactly the expected type and the src type is a
3397     // subtype which we can't check or src is the same array as dst
3398     // but not necessarily exactly of type default_type.
3399     Label known_ok, halt;
3400     __ mov_metadata(tmp, default_type->constant_encoding());
3401 #ifdef _LP64
3402     if (UseCompressedClassPointers) {
3403       __ encode_klass_not_null(tmp);
3404     }
3405 #endif
3406 
3407     if (basic_type != T_OBJECT) {
3408 
3409       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3410       else                   __ cmpptr(tmp, dst_klass_addr);
3411       __ jcc(Assembler::notEqual, halt);
3412       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3413       else                   __ cmpptr(tmp, src_klass_addr);
3414       __ jcc(Assembler::equal, known_ok);
3415     } else {
3416       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3417       else                   __ cmpptr(tmp, dst_klass_addr);
3418       __ jcc(Assembler::equal, known_ok);
3419       __ cmpptr(src, dst);
3420       __ jcc(Assembler::equal, known_ok);
3421     }
3422     __ bind(halt);
3423     __ stop("incorrect type information in arraycopy");
3424     __ bind(known_ok);
3425   }
3426 #endif
3427 
3428 #ifndef PRODUCT
3429   if (PrintC1Statistics) {
3430     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3431   }
3432 #endif
3433 
3434 #ifdef _LP64
3435   assert_different_registers(c_rarg0, dst, dst_pos, length);
3436   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3437   assert_different_registers(c_rarg1, length);
3438   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3439   __ mov(c_rarg2, length);
3440 
3441 #else
3442   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3443   store_parameter(tmp, 0);
3444   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3445   store_parameter(tmp, 1);
3446   store_parameter(length, 2);
3447 #endif // _LP64
3448 
3449   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3450   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3451   const char *name;
3452   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3453   __ call_VM_leaf(entry, 0);
3454 
3455   __ bind(*stub->continuation());
3456 }
3457 
3458 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3459   assert(op->crc()->is_single_cpu(),  "crc must be register");
3460   assert(op->val()->is_single_cpu(),  "byte value must be register");
3461   assert(op->result_opr()->is_single_cpu(), "result must be register");
3462   Register crc = op->crc()->as_register();
3463   Register val = op->val()->as_register();
3464   Register res = op->result_opr()->as_register();
3465 
3466   assert_different_registers(val, crc, res);
3467 
3468   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3469   __ notl(crc); // ~crc
3470   __ update_byte_crc32(crc, val, res);
3471   __ notl(crc); // ~crc
3472   __ mov(res, crc);
3473 }
3474 
3475 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3476   Register obj = op->obj_opr()->as_register();  // may not be an oop
3477   Register hdr = op->hdr_opr()->as_register();
3478   Register lock = op->lock_opr()->as_register();
3479   if (!UseFastLocking) {
3480     __ jmp(*op->stub()->entry());
3481   } else if (op->code() == lir_lock) {
3482     Register scratch = noreg;
3483     if (UseBiasedLocking) {
3484       scratch = op->scratch_opr()->as_register();
3485     }
3486     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3487     __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3488     // add debug info for NullPointerException only if one is possible
3489     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3490     if (op->info() != NULL) {
3491       add_debug_info_for_null_check(null_check_offset, op->info());
3492     }
3493     // done
3494   } else if (op->code() == lir_unlock) {
3495     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3496     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3497   } else {
3498     Unimplemented();
3499   }
3500   __ bind(*op->stub()->continuation());
3501 }
3502 
3503 
3504 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3505   ciMethod* method = op->profiled_method();
3506   int bci          = op->profiled_bci();
3507   ciMethod* callee = op->profiled_callee();
3508 
3509   // Update counter for all call types
3510   ciMethodData* md = method->method_data_or_null();
3511   assert(md != NULL, "Sanity");
3512   ciProfileData* data = md->bci_to_data(bci);
3513   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3514   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3515   Register mdo  = op->mdo()->as_register();
3516   __ mov_metadata(mdo, md->constant_encoding());
3517   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3518   // Perform additional virtual call profiling for invokevirtual and
3519   // invokeinterface bytecodes
3520   if (op->should_profile_receiver_type()) {
3521     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3522     Register recv = op->recv()->as_register();
3523     assert_different_registers(mdo, recv);
3524     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3525     ciKlass* known_klass = op->known_holder();
3526     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3527       // We know the type that will be seen at this call site; we can
3528       // statically update the MethodData* rather than needing to do
3529       // dynamic tests on the receiver type
3530 
3531       // NOTE: we should probably put a lock around this search to
3532       // avoid collisions by concurrent compilations
3533       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3534       uint i;
3535       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3536         ciKlass* receiver = vc_data->receiver(i);
3537         if (known_klass->equals(receiver)) {
3538           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3539           __ addptr(data_addr, DataLayout::counter_increment);
3540           return;
3541         }
3542       }
3543 
3544       // Receiver type not found in profile data; select an empty slot
3545 
3546       // Note that this is less efficient than it should be because it
3547       // always does a write to the receiver part of the
3548       // VirtualCallData rather than just the first time
3549       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3550         ciKlass* receiver = vc_data->receiver(i);
3551         if (receiver == NULL) {
3552           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3553           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3554           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3555           __ addptr(data_addr, DataLayout::counter_increment);
3556           return;
3557         }
3558       }
3559     } else {
3560       __ load_klass(recv, recv);
3561       Label update_done;
3562       type_profile_helper(mdo, md, data, recv, &update_done);
3563       // Receiver did not match any saved receiver and there is no empty row for it.
3564       // Increment total counter to indicate polymorphic case.
3565       __ addptr(counter_addr, DataLayout::counter_increment);
3566 
3567       __ bind(update_done);
3568     }
3569   } else {
3570     // Static call
3571     __ addptr(counter_addr, DataLayout::counter_increment);
3572   }
3573 }
3574 
3575 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3576   Register obj = op->obj()->as_register();
3577   Register tmp = op->tmp()->as_pointer_register();
3578   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3579   ciKlass* exact_klass = op->exact_klass();
3580   intptr_t current_klass = op->current_klass();
3581   bool not_null = op->not_null();
3582   bool no_conflict = op->no_conflict();
3583 
3584   Label update, next, none;
3585 
3586   bool do_null = !not_null;
3587   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3588   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3589 
3590   assert(do_null || do_update, "why are we here?");
3591   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3592 
3593   __ verify_oop(obj);
3594 
3595   if (tmp != obj) {
3596     __ mov(tmp, obj);
3597   }
3598   if (do_null) {
3599     __ testptr(tmp, tmp);
3600     __ jccb(Assembler::notZero, update);
3601     if (!TypeEntries::was_null_seen(current_klass)) {
3602       __ orptr(mdo_addr, TypeEntries::null_seen);
3603     }
3604     if (do_update) {
3605 #ifndef ASSERT
3606       __ jmpb(next);
3607     }
3608 #else
3609       __ jmp(next);
3610     }
3611   } else {
3612     __ testptr(tmp, tmp);
3613     __ jcc(Assembler::notZero, update);
3614     __ stop("unexpect null obj");
3615 #endif
3616   }
3617 
3618   __ bind(update);
3619 
3620   if (do_update) {
3621 #ifdef ASSERT
3622     if (exact_klass != NULL) {
3623       Label ok;
3624       __ load_klass(tmp, tmp);
3625       __ push(tmp);
3626       __ mov_metadata(tmp, exact_klass->constant_encoding());
3627       __ cmpptr(tmp, Address(rsp, 0));
3628       __ jcc(Assembler::equal, ok);
3629       __ stop("exact klass and actual klass differ");
3630       __ bind(ok);
3631       __ pop(tmp);
3632     }
3633 #endif
3634     if (!no_conflict) {
3635       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3636         if (exact_klass != NULL) {
3637           __ mov_metadata(tmp, exact_klass->constant_encoding());
3638         } else {
3639           __ load_klass(tmp, tmp);
3640         }
3641 
3642         __ xorptr(tmp, mdo_addr);
3643         __ testptr(tmp, TypeEntries::type_klass_mask);
3644         // klass seen before, nothing to do. The unknown bit may have been
3645         // set already but no need to check.
3646         __ jccb(Assembler::zero, next);
3647 
3648         __ testptr(tmp, TypeEntries::type_unknown);
3649         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3650 
3651         if (TypeEntries::is_type_none(current_klass)) {
3652           __ cmpptr(mdo_addr, 0);
3653           __ jccb(Assembler::equal, none);
3654           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3655           __ jccb(Assembler::equal, none);
3656           // There is a chance that the checks above (re-reading profiling
3657           // data from memory) fail if another thread has just set the
3658           // profiling to this obj's klass
3659           __ xorptr(tmp, mdo_addr);
3660           __ testptr(tmp, TypeEntries::type_klass_mask);
3661           __ jccb(Assembler::zero, next);
3662         }
3663       } else {
3664         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3665                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3666 
3667         __ movptr(tmp, mdo_addr);
3668         __ testptr(tmp, TypeEntries::type_unknown);
3669         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3670       }
3671 
3672       // different than before. Cannot keep accurate profile.
3673       __ orptr(mdo_addr, TypeEntries::type_unknown);
3674 
3675       if (TypeEntries::is_type_none(current_klass)) {
3676         __ jmpb(next);
3677 
3678         __ bind(none);
3679         // first time here. Set profile type.
3680         __ movptr(mdo_addr, tmp);
3681       }
3682     } else {
3683       // There's a single possible klass at this profile point
3684       assert(exact_klass != NULL, "should be");
3685       if (TypeEntries::is_type_none(current_klass)) {
3686         __ mov_metadata(tmp, exact_klass->constant_encoding());
3687         __ xorptr(tmp, mdo_addr);
3688         __ testptr(tmp, TypeEntries::type_klass_mask);
3689 #ifdef ASSERT
3690         __ jcc(Assembler::zero, next);
3691 
3692         {
3693           Label ok;
3694           __ push(tmp);
3695           __ cmpptr(mdo_addr, 0);
3696           __ jcc(Assembler::equal, ok);
3697           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3698           __ jcc(Assembler::equal, ok);
3699           // may have been set by another thread
3700           __ mov_metadata(tmp, exact_klass->constant_encoding());
3701           __ xorptr(tmp, mdo_addr);
3702           __ testptr(tmp, TypeEntries::type_mask);
3703           __ jcc(Assembler::zero, ok);
3704 
3705           __ stop("unexpected profiling mismatch");
3706           __ bind(ok);
3707           __ pop(tmp);
3708         }
3709 #else
3710         __ jccb(Assembler::zero, next);
3711 #endif
3712         // first time here. Set profile type.
3713         __ movptr(mdo_addr, tmp);
3714       } else {
3715         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3716                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3717 
3718         __ movptr(tmp, mdo_addr);
3719         __ testptr(tmp, TypeEntries::type_unknown);
3720         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3721 
3722         __ orptr(mdo_addr, TypeEntries::type_unknown);
3723       }
3724     }
3725 
3726     __ bind(next);
3727   }
3728 }
3729 
3730 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3731   Unimplemented();
3732 }
3733 
3734 
3735 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3736   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3737 }
3738 
3739 
3740 void LIR_Assembler::align_backward_branch_target() {
3741   __ align(BytesPerWord);
3742 }
3743 
3744 
3745 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3746   if (left->is_single_cpu()) {
3747     __ negl(left->as_register());
3748     move_regs(left->as_register(), dest->as_register());
3749 
3750   } else if (left->is_double_cpu()) {
3751     Register lo = left->as_register_lo();
3752 #ifdef _LP64
3753     Register dst = dest->as_register_lo();
3754     __ movptr(dst, lo);
3755     __ negptr(dst);
3756 #else
3757     Register hi = left->as_register_hi();
3758     __ lneg(hi, lo);
3759     if (dest->as_register_lo() == hi) {
3760       assert(dest->as_register_hi() != lo, "destroying register");
3761       move_regs(hi, dest->as_register_hi());
3762       move_regs(lo, dest->as_register_lo());
3763     } else {
3764       move_regs(lo, dest->as_register_lo());
3765       move_regs(hi, dest->as_register_hi());
3766     }
3767 #endif // _LP64
3768 
3769   } else if (dest->is_single_xmm()) {
3770     if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3771       __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3772     }
3773     if (UseAVX > 0) {
3774       __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3775                    ExternalAddress((address)float_signflip_pool));
3776     } else {
3777       __ xorps(dest->as_xmm_float_reg(),
3778                ExternalAddress((address)float_signflip_pool));
3779     }
3780   } else if (dest->is_double_xmm()) {
3781     if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3782       __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3783     }
3784     if (UseAVX > 0) {
3785       __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3786                    ExternalAddress((address)double_signflip_pool));
3787     } else {
3788       __ xorpd(dest->as_xmm_double_reg(),
3789                ExternalAddress((address)double_signflip_pool));
3790     }
3791   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3792     assert(left->fpu() == 0, "arg must be on TOS");
3793     assert(dest->fpu() == 0, "dest must be TOS");
3794     __ fchs();
3795 
3796   } else {
3797     ShouldNotReachHere();
3798   }
3799 }
3800 
3801 
3802 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3803   assert(src->is_address(), "must be an address");
3804   assert(dest->is_register(), "must be a register");
3805 
3806   PatchingStub* patch = NULL;
3807   if (patch_code != lir_patch_none) {
3808     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3809   }
3810 
3811   Register reg = dest->as_pointer_register();
3812   LIR_Address* addr = src->as_address_ptr();
3813   __ lea(reg, as_Address(addr));
3814 
3815   if (patch != NULL) {
3816     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3817   }
3818 }
3819 
3820 
3821 
3822 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3823   assert(!tmp->is_valid(), "don't need temporary");
3824   __ call(RuntimeAddress(dest));
3825   if (info != NULL) {
3826     add_call_info_here(info);
3827   }
3828 }
3829 
3830 
3831 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3832   assert(type == T_LONG, "only for volatile long fields");
3833 
3834   if (info != NULL) {
3835     add_debug_info_for_null_check_here(info);
3836   }
3837 
3838   if (src->is_double_xmm()) {
3839     if (dest->is_double_cpu()) {
3840 #ifdef _LP64
3841       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3842 #else
3843       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3844       __ psrlq(src->as_xmm_double_reg(), 32);
3845       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3846 #endif // _LP64
3847     } else if (dest->is_double_stack()) {
3848       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3849     } else if (dest->is_address()) {
3850       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3851     } else {
3852       ShouldNotReachHere();
3853     }
3854 
3855   } else if (dest->is_double_xmm()) {
3856     if (src->is_double_stack()) {
3857       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3858     } else if (src->is_address()) {
3859       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3860     } else {
3861       ShouldNotReachHere();
3862     }
3863 
3864   } else if (src->is_double_fpu()) {
3865     assert(src->fpu_regnrLo() == 0, "must be TOS");
3866     if (dest->is_double_stack()) {
3867       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3868     } else if (dest->is_address()) {
3869       __ fistp_d(as_Address(dest->as_address_ptr()));
3870     } else {
3871       ShouldNotReachHere();
3872     }
3873 
3874   } else if (dest->is_double_fpu()) {
3875     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3876     if (src->is_double_stack()) {
3877       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3878     } else if (src->is_address()) {
3879       __ fild_d(as_Address(src->as_address_ptr()));
3880     } else {
3881       ShouldNotReachHere();
3882     }
3883   } else {
3884     ShouldNotReachHere();
3885   }
3886 }
3887 
3888 #ifdef ASSERT
3889 // emit run-time assertion
3890 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3891   assert(op->code() == lir_assert, "must be");
3892 
3893   if (op->in_opr1()->is_valid()) {
3894     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3895     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3896   } else {
3897     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3898     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3899   }
3900 
3901   Label ok;
3902   if (op->condition() != lir_cond_always) {
3903     Assembler::Condition acond = Assembler::zero;
3904     switch (op->condition()) {
3905       case lir_cond_equal:        acond = Assembler::equal;       break;
3906       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3907       case lir_cond_less:         acond = Assembler::less;        break;
3908       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3909       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3910       case lir_cond_greater:      acond = Assembler::greater;     break;
3911       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3912       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3913       default:                    ShouldNotReachHere();
3914     }
3915     __ jcc(acond, ok);
3916   }
3917   if (op->halt()) {
3918     const char* str = __ code_string(op->msg());
3919     __ stop(str);
3920   } else {
3921     breakpoint();
3922   }
3923   __ bind(ok);
3924 }
3925 #endif
3926 
3927 void LIR_Assembler::membar() {
3928   // QQQ sparc TSO uses this,
3929   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3930 }
3931 
3932 void LIR_Assembler::membar_acquire() {
3933   // No x86 machines currently require load fences
3934 }
3935 
3936 void LIR_Assembler::membar_release() {
3937   // No x86 machines currently require store fences
3938 }
3939 
3940 void LIR_Assembler::membar_loadload() {
3941   // no-op
3942   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3943 }
3944 
3945 void LIR_Assembler::membar_storestore() {
3946   // no-op
3947   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3948 }
3949 
3950 void LIR_Assembler::membar_loadstore() {
3951   // no-op
3952   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3953 }
3954 
3955 void LIR_Assembler::membar_storeload() {
3956   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3957 }
3958 
3959 void LIR_Assembler::on_spin_wait() {
3960   __ pause ();
3961 }
3962 
3963 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3964   assert(result_reg->is_register(), "check");
3965 #ifdef _LP64
3966   // __ get_thread(result_reg->as_register_lo());
3967   __ mov(result_reg->as_register(), r15_thread);
3968 #else
3969   __ get_thread(result_reg->as_register());
3970 #endif // _LP64
3971 }
3972 
3973 
3974 void LIR_Assembler::peephole(LIR_List*) {
3975   // do nothing for now
3976 }
3977 
3978 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3979   assert(data == dest, "xchg/xadd uses only 2 operands");
3980 
3981   if (data->type() == T_INT) {
3982     if (code == lir_xadd) {
3983       if (os::is_MP()) {
3984         __ lock();
3985       }
3986       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3987     } else {
3988       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3989     }
3990   } else if (data->is_oop()) {
3991     assert (code == lir_xchg, "xadd for oops");
3992     Register obj = data->as_register();
3993 #ifdef _LP64
3994     if (UseCompressedOops) {
3995       __ encode_heap_oop(obj);
3996       __ xchgl(obj, as_Address(src->as_address_ptr()));
3997       __ decode_heap_oop(obj);
3998     } else {
3999       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4000     }
4001 #else
4002     __ xchgl(obj, as_Address(src->as_address_ptr()));
4003 #endif
4004   } else if (data->type() == T_LONG) {
4005 #ifdef _LP64
4006     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4007     if (code == lir_xadd) {
4008       if (os::is_MP()) {
4009         __ lock();
4010       }
4011       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4012     } else {
4013       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4014     }
4015 #else
4016     ShouldNotReachHere();
4017 #endif
4018   } else {
4019     ShouldNotReachHere();
4020   }
4021 }
4022 
4023 #undef __
--- EOF ---