src/cpu/sparc/vm/vm_version_sparc.cpp

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 339   }
 340 
 341   if (UseVIS > 2) {
 342     if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 343       FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 344     }
 345   } else if (UseAdler32Intrinsics) {
 346     warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 347     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 348   }
 349 
 350   if (UseVIS > 2) {
 351     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 352       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 353     }
 354   } else if (UseCRC32Intrinsics) {
 355     warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
 356     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 357   }
 358 






 359   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 360     (cache_line_size > ContendedPaddingWidth))
 361     ContendedPaddingWidth = cache_line_size;
 362 
 363   // This machine does not allow unaligned memory accesses
 364   if (UseUnalignedAccesses) {
 365     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 366       warning("Unaligned memory access is not available on this CPU");
 367     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 368   }
 369 
 370   if (PrintMiscellaneous && Verbose) {
 371     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 372     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 373     tty->print("Allocation");
 374     if (AllocatePrefetchStyle <= 0) {
 375       tty->print_cr(": no prefetching");
 376     } else {
 377       tty->print(" prefetching: ");
 378       if (AllocatePrefetchInstr == 0) {




 339   }
 340 
 341   if (UseVIS > 2) {
 342     if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 343       FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 344     }
 345   } else if (UseAdler32Intrinsics) {
 346     warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 347     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 348   }
 349 
 350   if (UseVIS > 2) {
 351     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 352       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 353     }
 354   } else if (UseCRC32Intrinsics) {
 355     warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
 356     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 357   }
 358 
 359   if (UseOnSpinWaitIntrinsic) {
 360     if (!FLAG_IS_DEFAULT(UseOnSpinWaitIntrinsic))
 361       warning("onSpinWait intrinsic is not available on this CPU");
 362     FLAG_SET_DEFAULT(UseOnSpinWaitIntrinsic, false);
 363   }
 364 
 365   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 366     (cache_line_size > ContendedPaddingWidth))
 367     ContendedPaddingWidth = cache_line_size;
 368 
 369   // This machine does not allow unaligned memory accesses
 370   if (UseUnalignedAccesses) {
 371     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 372       warning("Unaligned memory access is not available on this CPU");
 373     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 374   }
 375 
 376   if (PrintMiscellaneous && Verbose) {
 377     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 378     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 379     tty->print("Allocation");
 380     if (AllocatePrefetchStyle <= 0) {
 381       tty->print_cr(": no prefetching");
 382     } else {
 383       tty->print(" prefetching: ");
 384       if (AllocatePrefetchInstr == 0) {