1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version : public Abstract_VM_Version {
32 friend class VMStructs;
33 friend class JVMCIVMStructs;
34
35 public:
36 // cpuid result register layouts. These are all unions of a uint32_t
37 // (in case anyone wants access to the register as a whole) and a bitfield.
38
39 union StdCpuid1Eax {
40 uint32_t value;
41 struct {
42 uint32_t stepping : 4,
43 model : 4,
44 family : 4,
45 proc_type : 2,
46 : 2,
47 ext_model : 4,
48 ext_family : 8,
49 : 4;
50 } bits;
51 };
52
53 union StdCpuid1Ebx { // example, unused
54 uint32_t value;
55 struct {
56 uint32_t brand_id : 8,
57 clflush_size : 8,
58 threads_per_cpu : 8,
59 apic_id : 8;
60 } bits;
61 };
62
63 union StdCpuid1Ecx {
64 uint32_t value;
65 struct {
66 uint32_t sse3 : 1,
67 clmul : 1,
68 : 1,
69 monitor : 1,
70 : 1,
71 vmx : 1,
72 : 1,
73 est : 1,
74 : 1,
75 ssse3 : 1,
76 cid : 1,
77 : 2,
78 cmpxchg16: 1,
79 : 4,
80 dca : 1,
81 sse4_1 : 1,
82 sse4_2 : 1,
83 : 2,
84 popcnt : 1,
85 : 1,
86 aes : 1,
87 : 1,
88 osxsave : 1,
89 avx : 1,
90 : 3;
91 } bits;
92 };
93
94 union StdCpuid1Edx {
95 uint32_t value;
96 struct {
97 uint32_t : 4,
98 tsc : 1,
99 : 3,
100 cmpxchg8 : 1,
101 : 6,
102 cmov : 1,
103 : 3,
104 clflush : 1,
105 : 3,
106 mmx : 1,
107 fxsr : 1,
108 sse : 1,
109 sse2 : 1,
110 : 1,
111 ht : 1,
112 : 3;
113 } bits;
114 };
115
116 union DcpCpuid4Eax {
117 uint32_t value;
118 struct {
119 uint32_t cache_type : 5,
120 : 21,
121 cores_per_cpu : 6;
122 } bits;
123 };
124
125 union DcpCpuid4Ebx {
126 uint32_t value;
127 struct {
128 uint32_t L1_line_size : 12,
129 partitions : 10,
130 associativity : 10;
131 } bits;
132 };
133
134 union TplCpuidBEbx {
135 uint32_t value;
136 struct {
137 uint32_t logical_cpus : 16,
138 : 16;
139 } bits;
140 };
141
142 union ExtCpuid1Ecx {
143 uint32_t value;
144 struct {
145 uint32_t LahfSahf : 1,
146 CmpLegacy : 1,
147 : 3,
148 lzcnt_intel : 1,
149 lzcnt : 1,
150 sse4a : 1,
151 misalignsse : 1,
152 prefetchw : 1,
153 : 22;
154 } bits;
155 };
156
157 union ExtCpuid1Edx {
158 uint32_t value;
159 struct {
160 uint32_t : 22,
161 mmx_amd : 1,
162 mmx : 1,
163 fxsr : 1,
164 : 4,
165 long_mode : 1,
166 tdnow2 : 1,
167 tdnow : 1;
168 } bits;
169 };
170
171 union ExtCpuid5Ex {
172 uint32_t value;
173 struct {
174 uint32_t L1_line_size : 8,
175 L1_tag_lines : 8,
176 L1_assoc : 8,
177 L1_size : 8;
178 } bits;
179 };
180
181 union ExtCpuid7Edx {
182 uint32_t value;
183 struct {
184 uint32_t : 8,
185 tsc_invariance : 1,
186 : 23;
187 } bits;
188 };
189
190 union ExtCpuid8Ecx {
191 uint32_t value;
192 struct {
193 uint32_t cores_per_cpu : 8,
194 : 24;
195 } bits;
196 };
197
198 union SefCpuid7Eax {
199 uint32_t value;
200 };
201
202 union SefCpuid7Ebx {
203 uint32_t value;
204 struct {
205 uint32_t fsgsbase : 1,
206 : 2,
207 bmi1 : 1,
208 : 1,
209 avx2 : 1,
210 : 2,
211 bmi2 : 1,
212 erms : 1,
213 : 1,
214 rtm : 1,
215 : 4,
216 avx512f : 1,
217 avx512dq : 1,
218 : 1,
219 adx : 1,
220 : 6,
221 avx512pf : 1,
222 avx512er : 1,
223 avx512cd : 1,
224 : 1,
225 avx512bw : 1,
226 avx512vl : 1;
227 } bits;
228 };
229
230 union XemXcr0Eax {
231 uint32_t value;
232 struct {
233 uint32_t x87 : 1,
234 sse : 1,
235 ymm : 1,
236 bndregs : 1,
237 bndcsr : 1,
238 opmask : 1,
239 zmm512 : 1,
240 zmm32 : 1,
241 : 24;
242 } bits;
243 };
244
245 protected:
246 static int _cpu;
247 static int _model;
248 static int _stepping;
249
250 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
251 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
252
253 enum Feature_Flag {
254 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
255 CPU_CMOV = (1 << 1),
256 CPU_FXSR = (1 << 2),
257 CPU_HT = (1 << 3),
258 CPU_MMX = (1 << 4),
259 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
260 // may not necessarily support other 3dnow instructions
261 CPU_SSE = (1 << 6),
262 CPU_SSE2 = (1 << 7),
263 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
264 CPU_SSSE3 = (1 << 9),
265 CPU_SSE4A = (1 << 10),
266 CPU_SSE4_1 = (1 << 11),
267 CPU_SSE4_2 = (1 << 12),
268 CPU_POPCNT = (1 << 13),
269 CPU_LZCNT = (1 << 14),
270 CPU_TSC = (1 << 15),
271 CPU_TSCINV = (1 << 16),
272 CPU_AVX = (1 << 17),
273 CPU_AVX2 = (1 << 18),
274 CPU_AES = (1 << 19),
275 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
276 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
277 CPU_BMI1 = (1 << 22),
278 CPU_BMI2 = (1 << 23),
279 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
280 CPU_ADX = (1 << 25),
281 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
282 CPU_AVX512DQ = (1 << 27),
283 CPU_AVX512PF = (1 << 28),
284 CPU_AVX512ER = (1 << 29),
285 CPU_AVX512CD = (1 << 30),
286 CPU_AVX512BW = (1 << 31)
287 };
288
289 #define CPU_AVX512VL UCONST64(0x100000000) // EVEX instructions with smaller vector length : enums are limited to 32bit
290
291 enum Extended_Family {
292 // AMD
293 CPU_FAMILY_AMD_11H = 0x11,
294 // Intel
295 CPU_FAMILY_INTEL_CORE = 6,
296 CPU_MODEL_NEHALEM = 0x1e,
297 CPU_MODEL_NEHALEM_EP = 0x1a,
298 CPU_MODEL_NEHALEM_EX = 0x2e,
299 CPU_MODEL_WESTMERE = 0x25,
300 CPU_MODEL_WESTMERE_EP = 0x2c,
301 CPU_MODEL_WESTMERE_EX = 0x2f,
302 CPU_MODEL_SANDYBRIDGE = 0x2a,
303 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
304 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
305 CPU_MODEL_HASWELL_E3 = 0x3c,
306 CPU_MODEL_HASWELL_E7 = 0x3f,
307 CPU_MODEL_BROADWELL = 0x3d,
308 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
309 };
310
311 // cpuid information block. All info derived from executing cpuid with
312 // various function numbers is stored here. Intel and AMD info is
313 // merged in this block: accessor methods disentangle it.
314 //
315 // The info block is laid out in subblocks of 4 dwords corresponding to
316 // eax, ebx, ecx and edx, whether or not they contain anything useful.
317 struct CpuidInfo {
318 // cpuid function 0
319 uint32_t std_max_function;
320 uint32_t std_vendor_name_0;
321 uint32_t std_vendor_name_1;
322 uint32_t std_vendor_name_2;
323
324 // cpuid function 1
325 StdCpuid1Eax std_cpuid1_eax;
326 StdCpuid1Ebx std_cpuid1_ebx;
327 StdCpuid1Ecx std_cpuid1_ecx;
328 StdCpuid1Edx std_cpuid1_edx;
329
330 // cpuid function 4 (deterministic cache parameters)
331 DcpCpuid4Eax dcp_cpuid4_eax;
332 DcpCpuid4Ebx dcp_cpuid4_ebx;
333 uint32_t dcp_cpuid4_ecx; // unused currently
334 uint32_t dcp_cpuid4_edx; // unused currently
335
336 // cpuid function 7 (structured extended features)
337 SefCpuid7Eax sef_cpuid7_eax;
338 SefCpuid7Ebx sef_cpuid7_ebx;
339 uint32_t sef_cpuid7_ecx; // unused currently
340 uint32_t sef_cpuid7_edx; // unused currently
341
342 // cpuid function 0xB (processor topology)
343 // ecx = 0
344 uint32_t tpl_cpuidB0_eax;
345 TplCpuidBEbx tpl_cpuidB0_ebx;
346 uint32_t tpl_cpuidB0_ecx; // unused currently
347 uint32_t tpl_cpuidB0_edx; // unused currently
348
349 // ecx = 1
350 uint32_t tpl_cpuidB1_eax;
351 TplCpuidBEbx tpl_cpuidB1_ebx;
352 uint32_t tpl_cpuidB1_ecx; // unused currently
353 uint32_t tpl_cpuidB1_edx; // unused currently
354
355 // ecx = 2
356 uint32_t tpl_cpuidB2_eax;
357 TplCpuidBEbx tpl_cpuidB2_ebx;
358 uint32_t tpl_cpuidB2_ecx; // unused currently
359 uint32_t tpl_cpuidB2_edx; // unused currently
360
361 // cpuid function 0x80000000 // example, unused
362 uint32_t ext_max_function;
363 uint32_t ext_vendor_name_0;
364 uint32_t ext_vendor_name_1;
365 uint32_t ext_vendor_name_2;
366
367 // cpuid function 0x80000001
368 uint32_t ext_cpuid1_eax; // reserved
369 uint32_t ext_cpuid1_ebx; // reserved
370 ExtCpuid1Ecx ext_cpuid1_ecx;
371 ExtCpuid1Edx ext_cpuid1_edx;
372
373 // cpuid functions 0x80000002 thru 0x80000004: example, unused
374 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
375 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
376 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
377
378 // cpuid function 0x80000005 // AMD L1, Intel reserved
379 uint32_t ext_cpuid5_eax; // unused currently
380 uint32_t ext_cpuid5_ebx; // reserved
381 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
382 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
383
384 // cpuid function 0x80000007
385 uint32_t ext_cpuid7_eax; // reserved
386 uint32_t ext_cpuid7_ebx; // reserved
387 uint32_t ext_cpuid7_ecx; // reserved
388 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
389
390 // cpuid function 0x80000008
391 uint32_t ext_cpuid8_eax; // unused currently
392 uint32_t ext_cpuid8_ebx; // reserved
393 ExtCpuid8Ecx ext_cpuid8_ecx;
394 uint32_t ext_cpuid8_edx; // reserved
395
396 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
397 XemXcr0Eax xem_xcr0_eax;
398 uint32_t xem_xcr0_edx; // reserved
399
400 // Space to save ymm registers after signal handle
401 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
402
403 // Space to save zmm registers after signal handle
404 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
405 };
406
407 // The actual cpuid info block
408 static CpuidInfo _cpuid_info;
409
410 // Extractors and predicates
411 static uint32_t extended_cpu_family() {
412 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
413 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
414 return result;
415 }
416
417 static uint32_t extended_cpu_model() {
418 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
419 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
420 return result;
421 }
422
423 static uint32_t cpu_stepping() {
424 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
425 return result;
426 }
427
428 static uint logical_processor_count() {
429 uint result = threads_per_core();
430 return result;
431 }
432
433 static uint64_t feature_flags() {
434 uint64_t result = 0;
435 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
436 result |= CPU_CX8;
437 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
438 result |= CPU_CMOV;
439 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
440 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
441 result |= CPU_FXSR;
442 // HT flag is set for multi-core processors also.
443 if (threads_per_core() > 1)
444 result |= CPU_HT;
445 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
446 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
447 result |= CPU_MMX;
448 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
449 result |= CPU_SSE;
450 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
451 result |= CPU_SSE2;
452 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
453 result |= CPU_SSE3;
454 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
455 result |= CPU_SSSE3;
456 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
457 result |= CPU_SSE4_1;
458 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
459 result |= CPU_SSE4_2;
460 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
461 result |= CPU_POPCNT;
462 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
463 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
464 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
465 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
466 result |= CPU_AVX;
467 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
468 result |= CPU_AVX2;
469 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
470 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
471 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
472 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
473 result |= CPU_AVX512F;
474 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
475 result |= CPU_AVX512CD;
476 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
477 result |= CPU_AVX512DQ;
478 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
479 result |= CPU_AVX512PF;
480 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
481 result |= CPU_AVX512ER;
482 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
483 result |= CPU_AVX512BW;
484 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
485 result |= CPU_AVX512VL;
486 }
487 }
488 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
489 result |= CPU_BMI1;
490 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
491 result |= CPU_TSC;
492 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
493 result |= CPU_TSCINV;
494 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
495 result |= CPU_AES;
496 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
497 result |= CPU_ERMS;
498 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
499 result |= CPU_CLMUL;
500 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
501 result |= CPU_RTM;
502
503 // AMD features.
504 if (is_amd()) {
505 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
506 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
507 result |= CPU_3DNOW_PREFETCH;
508 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
509 result |= CPU_LZCNT;
510 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
511 result |= CPU_SSE4A;
512 }
513 // Intel features.
514 if(is_intel()) {
515 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
516 result |= CPU_ADX;
517 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
518 result |= CPU_BMI2;
519 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
520 result |= CPU_LZCNT;
521 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
522 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
523 result |= CPU_3DNOW_PREFETCH;
524 }
525 }
526
527 return result;
528 }
529
530 static bool os_supports_avx_vectors() {
531 bool retVal = false;
532 if (supports_evex()) {
533 // Verify that OS save/restore all bits of EVEX registers
534 // during signal processing.
535 int nreg = 2 LP64_ONLY(+2);
536 retVal = true;
537 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
538 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
539 retVal = false;
540 break;
541 }
542 }
543 } else if (supports_avx()) {
544 // Verify that OS save/restore all bits of AVX registers
545 // during signal processing.
546 int nreg = 2 LP64_ONLY(+2);
547 retVal = true;
548 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
549 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
550 retVal = false;
551 break;
552 }
553 }
554 // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
555 if (retVal == false) {
556 // Verify that OS save/restore all bits of EVEX registers
557 // during signal processing.
558 int nreg = 2 LP64_ONLY(+2);
559 retVal = true;
560 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
561 if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
562 retVal = false;
563 break;
564 }
565 }
566 }
567 }
568 return retVal;
569 }
570
571 static void get_processor_features();
572
573 public:
574 // Offsets for cpuid asm stub
575 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
576 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
577 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
578 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
579 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
580 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
581 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
582 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
583 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
584 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
585 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
586 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
587 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
588 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
589
590 // The value used to check ymm register after signal handle
591 static int ymm_test_value() { return 0xCAFEBABE; }
592
593 static void get_cpu_info_wrapper();
594 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
595 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
596 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
597 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
598
599 static void clean_cpuFeatures() { _features = 0; }
600 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX); }
601 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 ); }
602
603
604 // Initialization
605 static void initialize();
606
607 // Override Abstract_VM_Version implementation
608 static bool use_biased_locking();
609
610 // Asserts
611 static void assert_is_initialized() {
612 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
613 }
614
615 //
616 // Processor family:
617 // 3 - 386
618 // 4 - 486
619 // 5 - Pentium
620 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
621 // Pentium M, Core Solo, Core Duo, Core2 Duo
622 // family 6 model: 9, 13, 14, 15
623 // 0x0f - Pentium 4, Opteron
624 //
625 // Note: The cpu family should be used to select between
626 // instruction sequences which are valid on all Intel
627 // processors. Use the feature test functions below to
628 // determine whether a particular instruction is supported.
629 //
630 static int cpu_family() { return _cpu;}
631 static bool is_P6() { return cpu_family() >= 6; }
632 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
633 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
634
635 static bool supports_processor_topology() {
636 return (_cpuid_info.std_max_function >= 0xB) &&
637 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
638 // Some cpus have max cpuid >= 0xB but do not support processor topology.
639 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
640 }
641
642 static uint cores_per_cpu() {
643 uint result = 1;
644 if (is_intel()) {
645 bool supports_topology = supports_processor_topology();
646 if (supports_topology) {
647 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
648 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
649 }
650 if (!supports_topology || result == 0) {
651 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
652 }
653 } else if (is_amd()) {
654 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
655 }
656 return result;
657 }
658
659 static uint threads_per_core() {
660 uint result = 1;
661 if (is_intel() && supports_processor_topology()) {
662 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
663 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
664 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
665 cores_per_cpu();
666 }
667 return (result == 0 ? 1 : result);
668 }
669
670 static intx L1_line_size() {
671 intx result = 0;
672 if (is_intel()) {
673 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
674 } else if (is_amd()) {
675 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
676 }
677 if (result < 32) // not defined ?
678 result = 32; // 32 bytes by default on x86 and other x64
679 return result;
680 }
681
682 static intx prefetch_data_size() {
683 return L1_line_size();
684 }
685
686 //
687 // Feature identification
688 //
689 static bool supports_cpuid() { return _features != 0; }
690 static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
691 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
692 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
693 static bool supports_ht() { return (_features & CPU_HT) != 0; }
694 static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
695 static bool supports_sse() { return (_features & CPU_SSE) != 0; }
696 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
697 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
698 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
699 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
700 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
701 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
702 static bool supports_avx() { return (_features & CPU_AVX) != 0; }
703 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
704 static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
705 static bool supports_aes() { return (_features & CPU_AES) != 0; }
706 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
707 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
708 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
709 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
710 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
711 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
712 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
713 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
714 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
715 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
716 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
717 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
718 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
719 static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); }
720 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
721 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
722 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
723 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
724 // Intel features
725 static bool is_intel_family_core() { return is_intel() &&
726 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
727
728 static bool is_intel_tsc_synched_at_init() {
729 if (is_intel_family_core()) {
730 uint32_t ext_model = extended_cpu_model();
731 if (ext_model == CPU_MODEL_NEHALEM_EP ||
732 ext_model == CPU_MODEL_WESTMERE_EP ||
733 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
734 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
735 // <= 2-socket invariant tsc support. EX versions are usually used
736 // in > 2-socket systems and likely don't synchronize tscs at
737 // initialization.
738 // Code that uses tsc values must be prepared for them to arbitrarily
739 // jump forward or backward.
740 return true;
741 }
742 }
743 return false;
744 }
745
746 // AMD features
747 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
748 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
749 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
750 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
751
752 static bool is_amd_Barcelona() { return is_amd() &&
753 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
754
755 // Intel and AMD newer cores support fast timestamps well
756 static bool supports_tscinv_bit() {
757 return (_features & CPU_TSCINV) != 0;
758 }
759 static bool supports_tscinv() {
760 return supports_tscinv_bit() &&
761 ( (is_amd() && !is_amd_Barcelona()) ||
762 is_intel_tsc_synched_at_init() );
763 }
764
765 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
766 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
767 supports_sse3() && _model != 0x1C; }
768
769 static bool supports_compare_and_exchange() { return true; }
770
771 static intx allocate_prefetch_distance() {
772 // This method should be called before allocate_prefetch_style().
773 //
774 // Hardware prefetching (distance/size in bytes):
775 // Pentium 3 - 64 / 32
776 // Pentium 4 - 256 / 128
777 // Athlon - 64 / 32 ????
778 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
779 // Core - 128 / 64
780 //
781 // Software prefetching (distance in bytes / instruction with best score):
782 // Pentium 3 - 128 / prefetchnta
783 // Pentium 4 - 512 / prefetchnta
784 // Athlon - 128 / prefetchnta
785 // Opteron - 256 / prefetchnta
786 // Core - 256 / prefetchnta
787 // It will be used only when AllocatePrefetchStyle > 0
788
789 intx count = AllocatePrefetchDistance;
790 if (count < 0) { // default ?
791 if (is_amd()) { // AMD
792 if (supports_sse2())
793 count = 256; // Opteron
794 else
795 count = 128; // Athlon
796 } else { // Intel
797 if (supports_sse2())
798 if (cpu_family() == 6) {
799 count = 256; // Pentium M, Core, Core2
800 } else {
801 count = 512; // Pentium 4
802 }
803 else
804 count = 128; // Pentium 3 (and all other old CPUs)
805 }
806 }
807 return count;
808 }
809 static intx allocate_prefetch_style() {
810 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
811 // Return 0 if AllocatePrefetchDistance was not defined.
812 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
813 }
814
815 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
816 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
817 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
818 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
819
820 // gc copy/scan is disabled if prefetchw isn't supported, because
821 // Prefetch::write emits an inlined prefetchw on Linux.
822 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
823 // The used prefetcht0 instruction works for both amd64 and em64t.
824 static intx prefetch_copy_interval_in_bytes() {
825 intx interval = PrefetchCopyIntervalInBytes;
826 return interval >= 0 ? interval : 576;
827 }
828 static intx prefetch_scan_interval_in_bytes() {
829 intx interval = PrefetchScanIntervalInBytes;
830 return interval >= 0 ? interval : 576;
831 }
832 static intx prefetch_fields_ahead() {
833 intx count = PrefetchFieldsAhead;
834 return count >= 0 ? count : 1;
835 }
836 static uint32_t get_xsave_header_lower_segment() {
837 return _cpuid_info.xem_xcr0_eax.value;
838 }
839 static uint32_t get_xsave_header_upper_segment() {
840 return _cpuid_info.xem_xcr0_edx;
841 }
842
843 // SSE2 and later processors implement a 'pause' instruction
844 // that can be used for efficient implementation of
845 // the intrinsic for java.lang.Runtime.onSpinWait()
846 static bool supports_on_spin_wait() { return supports_sse2(); }
847 };
848
849 #endif // CPU_X86_VM_VM_VERSION_X86_HPP