466 reset();
467 set_op(op);
468
469 switch (op->code()) {
470
471 // LIR_Op0
472 case lir_word_align: // result and info always invalid
473 case lir_backwardbranch_target: // result and info always invalid
474 case lir_build_frame: // result and info always invalid
475 case lir_fpop_raw: // result and info always invalid
476 case lir_24bit_FPU: // result and info always invalid
477 case lir_reset_FPU: // result and info always invalid
478 case lir_breakpoint: // result and info always invalid
479 case lir_membar: // result and info always invalid
480 case lir_membar_acquire: // result and info always invalid
481 case lir_membar_release: // result and info always invalid
482 case lir_membar_loadload: // result and info always invalid
483 case lir_membar_storestore: // result and info always invalid
484 case lir_membar_loadstore: // result and info always invalid
485 case lir_membar_storeload: // result and info always invalid
486 {
487 assert(op->as_Op0() != NULL, "must be");
488 assert(op->_info == NULL, "info not used by this instruction");
489 assert(op->_result->is_illegal(), "not used");
490 break;
491 }
492
493 case lir_nop: // may have info, result always invalid
494 case lir_std_entry: // may have result, info always invalid
495 case lir_osr_entry: // may have result, info always invalid
496 case lir_get_thread: // may have result, info always invalid
497 {
498 assert(op->as_Op0() != NULL, "must be");
499 if (op->_info != NULL) do_info(op->_info);
500 if (op->_result->is_valid()) do_output(op->_result);
501 break;
502 }
503
504
505 // LIR_OpLabel
1674 if (Verbose && _file != NULL) {
1675 out->print(" (%s:%d)", _file, _line);
1676 }
1677 #endif
1678 }
1679
1680 const char * LIR_Op::name() const {
1681 const char* s = NULL;
1682 switch(code()) {
1683 // LIR_Op0
1684 case lir_membar: s = "membar"; break;
1685 case lir_membar_acquire: s = "membar_acquire"; break;
1686 case lir_membar_release: s = "membar_release"; break;
1687 case lir_membar_loadload: s = "membar_loadload"; break;
1688 case lir_membar_storestore: s = "membar_storestore"; break;
1689 case lir_membar_loadstore: s = "membar_loadstore"; break;
1690 case lir_membar_storeload: s = "membar_storeload"; break;
1691 case lir_word_align: s = "word_align"; break;
1692 case lir_label: s = "label"; break;
1693 case lir_nop: s = "nop"; break;
1694 case lir_backwardbranch_target: s = "backbranch"; break;
1695 case lir_std_entry: s = "std_entry"; break;
1696 case lir_osr_entry: s = "osr_entry"; break;
1697 case lir_build_frame: s = "build_frm"; break;
1698 case lir_fpop_raw: s = "fpop_raw"; break;
1699 case lir_24bit_FPU: s = "24bit_FPU"; break;
1700 case lir_reset_FPU: s = "reset_FPU"; break;
1701 case lir_breakpoint: s = "breakpoint"; break;
1702 case lir_get_thread: s = "get_thread"; break;
1703 // LIR_Op1
1704 case lir_fxch: s = "fxch"; break;
1705 case lir_fld: s = "fld"; break;
1706 case lir_ffree: s = "ffree"; break;
1707 case lir_push: s = "push"; break;
1708 case lir_pop: s = "pop"; break;
1709 case lir_null_check: s = "null_check"; break;
1710 case lir_return: s = "return"; break;
1711 case lir_safepoint: s = "safepoint"; break;
1712 case lir_neg: s = "neg"; break;
1713 case lir_leal: s = "leal"; break;
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466 reset();
467 set_op(op);
468
469 switch (op->code()) {
470
471 // LIR_Op0
472 case lir_word_align: // result and info always invalid
473 case lir_backwardbranch_target: // result and info always invalid
474 case lir_build_frame: // result and info always invalid
475 case lir_fpop_raw: // result and info always invalid
476 case lir_24bit_FPU: // result and info always invalid
477 case lir_reset_FPU: // result and info always invalid
478 case lir_breakpoint: // result and info always invalid
479 case lir_membar: // result and info always invalid
480 case lir_membar_acquire: // result and info always invalid
481 case lir_membar_release: // result and info always invalid
482 case lir_membar_loadload: // result and info always invalid
483 case lir_membar_storestore: // result and info always invalid
484 case lir_membar_loadstore: // result and info always invalid
485 case lir_membar_storeload: // result and info always invalid
486 case lir_on_spin_wait:
487 {
488 assert(op->as_Op0() != NULL, "must be");
489 assert(op->_info == NULL, "info not used by this instruction");
490 assert(op->_result->is_illegal(), "not used");
491 break;
492 }
493
494 case lir_nop: // may have info, result always invalid
495 case lir_std_entry: // may have result, info always invalid
496 case lir_osr_entry: // may have result, info always invalid
497 case lir_get_thread: // may have result, info always invalid
498 {
499 assert(op->as_Op0() != NULL, "must be");
500 if (op->_info != NULL) do_info(op->_info);
501 if (op->_result->is_valid()) do_output(op->_result);
502 break;
503 }
504
505
506 // LIR_OpLabel
1675 if (Verbose && _file != NULL) {
1676 out->print(" (%s:%d)", _file, _line);
1677 }
1678 #endif
1679 }
1680
1681 const char * LIR_Op::name() const {
1682 const char* s = NULL;
1683 switch(code()) {
1684 // LIR_Op0
1685 case lir_membar: s = "membar"; break;
1686 case lir_membar_acquire: s = "membar_acquire"; break;
1687 case lir_membar_release: s = "membar_release"; break;
1688 case lir_membar_loadload: s = "membar_loadload"; break;
1689 case lir_membar_storestore: s = "membar_storestore"; break;
1690 case lir_membar_loadstore: s = "membar_loadstore"; break;
1691 case lir_membar_storeload: s = "membar_storeload"; break;
1692 case lir_word_align: s = "word_align"; break;
1693 case lir_label: s = "label"; break;
1694 case lir_nop: s = "nop"; break;
1695 case lir_on_spin_wait: s = "on_spin_wait"; break;
1696 case lir_backwardbranch_target: s = "backbranch"; break;
1697 case lir_std_entry: s = "std_entry"; break;
1698 case lir_osr_entry: s = "osr_entry"; break;
1699 case lir_build_frame: s = "build_frm"; break;
1700 case lir_fpop_raw: s = "fpop_raw"; break;
1701 case lir_24bit_FPU: s = "24bit_FPU"; break;
1702 case lir_reset_FPU: s = "reset_FPU"; break;
1703 case lir_breakpoint: s = "breakpoint"; break;
1704 case lir_get_thread: s = "get_thread"; break;
1705 // LIR_Op1
1706 case lir_fxch: s = "fxch"; break;
1707 case lir_fld: s = "fld"; break;
1708 case lir_ffree: s = "ffree"; break;
1709 case lir_push: s = "push"; break;
1710 case lir_pop: s = "pop"; break;
1711 case lir_null_check: s = "null_check"; break;
1712 case lir_return: s = "return"; break;
1713 case lir_safepoint: s = "safepoint"; break;
1714 case lir_neg: s = "neg"; break;
1715 case lir_leal: s = "leal"; break;
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