hotspot Sdiff src/cpu/sparc/vm

src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

rev 10271 : 8147844: new method j.l.Runtime.onSpinWait() and the corresponding x86 hotspot instrinsic
Summary: adds c1 & c2 x86 intrinsics for j.l.Runtime.onSpinWait() that utilize the PAUSE instruction
Reviewed-by: iveresov, kvn, vlivanov
Contributed-by: Ivan Krylov <ivan@azul.com>, Yuri Gaevsky <ygaevsky@azul.com>

3296 
3297 void LIR_Assembler::membar_loadload() {
3298   // no-op
3299   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3300 }
3301 
3302 void LIR_Assembler::membar_storestore() {
3303   // no-op
3304   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3305 }
3306 
3307 void LIR_Assembler::membar_loadstore() {
3308   // no-op
3309   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3310 }
3311 
3312 void LIR_Assembler::membar_storeload() {
3313   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3314 }
3315 



3316 
3317 // Pack two sequential registers containing 32 bit values
3318 // into a single 64 bit register.
3319 // src and src->successor() are packed into dst
3320 // src and dst may be the same register.
3321 // Note: src is destroyed
3322 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3323   Register rs = src->as_register();
3324   Register rd = dst->as_register_lo();
3325   __ sllx(rs, 32, rs);
3326   __ srl(rs->successor(), 0, rs->successor());
3327   __ or3(rs, rs->successor(), rd);
3328 }
3329 
3330 // Unpack a 64 bit value in a register into
3331 // two sequential registers.
3332 // src is unpacked into dst and dst->successor()
3333 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3334   Register rs = src->as_register_lo();
3335   Register rd = dst->as_register_hi();

3296 
3297 void LIR_Assembler::membar_loadload() {
3298   // no-op
3299   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3300 }
3301 
3302 void LIR_Assembler::membar_storestore() {
3303   // no-op
3304   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3305 }
3306 
3307 void LIR_Assembler::membar_loadstore() {
3308   // no-op
3309   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3310 }
3311 
3312 void LIR_Assembler::membar_storeload() {
3313   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3314 }
3315 
3316 void LIR_Assembler::on_spin_wait() {
3317   Unimplemented();
3318 }
3319 
3320 // Pack two sequential registers containing 32 bit values
3321 // into a single 64 bit register.
3322 // src and src->successor() are packed into dst
3323 // src and dst may be the same register.
3324 // Note: src is destroyed
3325 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3326   Register rs = src->as_register();
3327   Register rd = dst->as_register_lo();
3328   __ sllx(rs, 32, rs);
3329   __ srl(rs->successor(), 0, rs->successor());
3330   __ or3(rs, rs->successor(), rd);
3331 }
3332 
3333 // Unpack a 64 bit value in a register into
3334 // two sequential registers.
3335 // src is unpacked into dst and dst->successor()
3336 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3337   Register rs = src->as_register_lo();
3338   Register rd = dst->as_register_hi();