1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_assembler_x86.cpp.incl"
27
28 // Implementation of AddressLiteral
29
30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
31 _is_lval = false;
32 _target = target;
33 switch (rtype) {
34 case relocInfo::oop_type:
35 // Oops are a special case. Normally they would be their own section
36 // but in cases like icBuffer they are literals in the code stream that
37 // we don't have a section for. We use none so that we get a literal address
38 // which is always patchable.
39 break;
40 case relocInfo::external_word_type:
41 _rspec = external_word_Relocation::spec(target);
42 break;
43 case relocInfo::internal_word_type:
44 _rspec = internal_word_Relocation::spec(target);
45 break;
46 case relocInfo::opt_virtual_call_type:
47 _rspec = opt_virtual_call_Relocation::spec();
48 break;
49 case relocInfo::static_call_type:
50 _rspec = static_call_Relocation::spec();
51 break;
52 case relocInfo::runtime_call_type:
53 _rspec = runtime_call_Relocation::spec();
54 break;
55 case relocInfo::poll_type:
56 case relocInfo::poll_return_type:
57 _rspec = Relocation::spec_simple(rtype);
58 break;
59 case relocInfo::none:
60 break;
61 default:
62 ShouldNotReachHere();
63 break;
64 }
65 }
66
67 // Implementation of Address
68
69 #ifdef _LP64
70
71 Address Address::make_array(ArrayAddress adr) {
72 // Not implementable on 64bit machines
73 // Should have been handled higher up the call chain.
74 ShouldNotReachHere();
75 return Address();
76 }
77
78 // exceedingly dangerous constructor
79 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
80 _base = noreg;
81 _index = noreg;
82 _scale = no_scale;
83 _disp = disp;
84 switch (rtype) {
85 case relocInfo::external_word_type:
86 _rspec = external_word_Relocation::spec(loc);
87 break;
88 case relocInfo::internal_word_type:
89 _rspec = internal_word_Relocation::spec(loc);
90 break;
91 case relocInfo::runtime_call_type:
92 // HMM
93 _rspec = runtime_call_Relocation::spec();
94 break;
95 case relocInfo::poll_type:
96 case relocInfo::poll_return_type:
97 _rspec = Relocation::spec_simple(rtype);
98 break;
99 case relocInfo::none:
100 break;
101 default:
102 ShouldNotReachHere();
103 }
104 }
105 #else // LP64
106
107 Address Address::make_array(ArrayAddress adr) {
108 AddressLiteral base = adr.base();
109 Address index = adr.index();
110 assert(index._disp == 0, "must not have disp"); // maybe it can?
111 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
112 array._rspec = base._rspec;
113 return array;
114 }
115
116 // exceedingly dangerous constructor
117 Address::Address(address loc, RelocationHolder spec) {
118 _base = noreg;
119 _index = noreg;
120 _scale = no_scale;
121 _disp = (intptr_t) loc;
122 _rspec = spec;
123 }
124
125 #endif // _LP64
126
127
128
129 // Convert the raw encoding form into the form expected by the constructor for
130 // Address. An index of 4 (rsp) corresponds to having no index, so convert
131 // that to noreg for the Address constructor.
132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
133 RelocationHolder rspec;
134 if (disp_is_oop) {
135 rspec = Relocation::spec_simple(relocInfo::oop_type);
136 }
137 bool valid_index = index != rsp->encoding();
138 if (valid_index) {
139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
140 madr._rspec = rspec;
141 return madr;
142 } else {
143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
144 madr._rspec = rspec;
145 return madr;
146 }
147 }
148
149 // Implementation of Assembler
150
151 int AbstractAssembler::code_fill_byte() {
152 return (u_char)'\xF4'; // hlt
153 }
154
155 // make this go away someday
156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
157 if (rtype == relocInfo::none)
158 emit_long(data);
159 else emit_data(data, Relocation::spec_simple(rtype), format);
160 }
161
162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
163 assert(imm_operand == 0, "default format must be immediate in this file");
164 assert(inst_mark() != NULL, "must be inside InstructionMark");
165 if (rspec.type() != relocInfo::none) {
166 #ifdef ASSERT
167 check_relocation(rspec, format);
168 #endif
169 // Do not use AbstractAssembler::relocate, which is not intended for
170 // embedded words. Instead, relocate to the enclosing instruction.
171
172 // hack. call32 is too wide for mask so use disp32
173 if (format == call32_operand)
174 code_section()->relocate(inst_mark(), rspec, disp32_operand);
175 else
176 code_section()->relocate(inst_mark(), rspec, format);
177 }
178 emit_long(data);
179 }
180
181 static int encode(Register r) {
182 int enc = r->encoding();
183 if (enc >= 8) {
184 enc -= 8;
185 }
186 return enc;
187 }
188
189 static int encode(XMMRegister r) {
190 int enc = r->encoding();
191 if (enc >= 8) {
192 enc -= 8;
193 }
194 return enc;
195 }
196
197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
198 assert(dst->has_byte_register(), "must have byte register");
199 assert(isByte(op1) && isByte(op2), "wrong opcode");
200 assert(isByte(imm8), "not a byte");
201 assert((op1 & 0x01) == 0, "should be 8bit operation");
202 emit_byte(op1);
203 emit_byte(op2 | encode(dst));
204 emit_byte(imm8);
205 }
206
207
208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
209 assert(isByte(op1) && isByte(op2), "wrong opcode");
210 assert((op1 & 0x01) == 1, "should be 32bit operation");
211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
212 if (is8bit(imm32)) {
213 emit_byte(op1 | 0x02); // set sign bit
214 emit_byte(op2 | encode(dst));
215 emit_byte(imm32 & 0xFF);
216 } else {
217 emit_byte(op1);
218 emit_byte(op2 | encode(dst));
219 emit_long(imm32);
220 }
221 }
222
223 // immediate-to-memory forms
224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
225 assert((op1 & 0x01) == 1, "should be 32bit operation");
226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
227 if (is8bit(imm32)) {
228 emit_byte(op1 | 0x02); // set sign bit
229 emit_operand(rm, adr, 1);
230 emit_byte(imm32 & 0xFF);
231 } else {
232 emit_byte(op1);
233 emit_operand(rm, adr, 4);
234 emit_long(imm32);
235 }
236 }
237
238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
239 LP64_ONLY(ShouldNotReachHere());
240 assert(isByte(op1) && isByte(op2), "wrong opcode");
241 assert((op1 & 0x01) == 1, "should be 32bit operation");
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
243 InstructionMark im(this);
244 emit_byte(op1);
245 emit_byte(op2 | encode(dst));
246 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
247 }
248
249
250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
251 assert(isByte(op1) && isByte(op2), "wrong opcode");
252 emit_byte(op1);
253 emit_byte(op2 | encode(dst) << 3 | encode(src));
254 }
255
256
257 void Assembler::emit_operand(Register reg, Register base, Register index,
258 Address::ScaleFactor scale, int disp,
259 RelocationHolder const& rspec,
260 int rip_relative_correction) {
261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
262
263 // Encode the registers as needed in the fields they are used in
264
265 int regenc = encode(reg) << 3;
266 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
267 int baseenc = base->is_valid() ? encode(base) : 0;
268
269 if (base->is_valid()) {
270 if (index->is_valid()) {
271 assert(scale != Address::no_scale, "inconsistent address");
272 // [base + index*scale + disp]
273 if (disp == 0 && rtype == relocInfo::none &&
274 base != rbp LP64_ONLY(&& base != r13)) {
275 // [base + index*scale]
276 // [00 reg 100][ss index base]
277 assert(index != rsp, "illegal addressing mode");
278 emit_byte(0x04 | regenc);
279 emit_byte(scale << 6 | indexenc | baseenc);
280 } else if (is8bit(disp) && rtype == relocInfo::none) {
281 // [base + index*scale + imm8]
282 // [01 reg 100][ss index base] imm8
283 assert(index != rsp, "illegal addressing mode");
284 emit_byte(0x44 | regenc);
285 emit_byte(scale << 6 | indexenc | baseenc);
286 emit_byte(disp & 0xFF);
287 } else {
288 // [base + index*scale + disp32]
289 // [10 reg 100][ss index base] disp32
290 assert(index != rsp, "illegal addressing mode");
291 emit_byte(0x84 | regenc);
292 emit_byte(scale << 6 | indexenc | baseenc);
293 emit_data(disp, rspec, disp32_operand);
294 }
295 } else if (base == rsp LP64_ONLY(|| base == r12)) {
296 // [rsp + disp]
297 if (disp == 0 && rtype == relocInfo::none) {
298 // [rsp]
299 // [00 reg 100][00 100 100]
300 emit_byte(0x04 | regenc);
301 emit_byte(0x24);
302 } else if (is8bit(disp) && rtype == relocInfo::none) {
303 // [rsp + imm8]
304 // [01 reg 100][00 100 100] disp8
305 emit_byte(0x44 | regenc);
306 emit_byte(0x24);
307 emit_byte(disp & 0xFF);
308 } else {
309 // [rsp + imm32]
310 // [10 reg 100][00 100 100] disp32
311 emit_byte(0x84 | regenc);
312 emit_byte(0x24);
313 emit_data(disp, rspec, disp32_operand);
314 }
315 } else {
316 // [base + disp]
317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
318 if (disp == 0 && rtype == relocInfo::none &&
319 base != rbp LP64_ONLY(&& base != r13)) {
320 // [base]
321 // [00 reg base]
322 emit_byte(0x00 | regenc | baseenc);
323 } else if (is8bit(disp) && rtype == relocInfo::none) {
324 // [base + disp8]
325 // [01 reg base] disp8
326 emit_byte(0x40 | regenc | baseenc);
327 emit_byte(disp & 0xFF);
328 } else {
329 // [base + disp32]
330 // [10 reg base] disp32
331 emit_byte(0x80 | regenc | baseenc);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 }
335 } else {
336 if (index->is_valid()) {
337 assert(scale != Address::no_scale, "inconsistent address");
338 // [index*scale + disp]
339 // [00 reg 100][ss index 101] disp32
340 assert(index != rsp, "illegal addressing mode");
341 emit_byte(0x04 | regenc);
342 emit_byte(scale << 6 | indexenc | 0x05);
343 emit_data(disp, rspec, disp32_operand);
344 } else if (rtype != relocInfo::none ) {
345 // [disp] (64bit) RIP-RELATIVE (32bit) abs
346 // [00 000 101] disp32
347
348 emit_byte(0x05 | regenc);
349 // Note that the RIP-rel. correction applies to the generated
350 // disp field, but _not_ to the target address in the rspec.
351
352 // disp was created by converting the target address minus the pc
353 // at the start of the instruction. That needs more correction here.
354 // intptr_t disp = target - next_ip;
355 assert(inst_mark() != NULL, "must be inside InstructionMark");
356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
357 int64_t adjusted = disp;
358 // Do rip-rel adjustment for 64bit
359 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
360 assert(is_simm32(adjusted),
361 "must be 32bit offset (RIP relative address)");
362 emit_data((int32_t) adjusted, rspec, disp32_operand);
363
364 } else {
365 // 32bit never did this, did everything as the rip-rel/disp code above
366 // [disp] ABSOLUTE
367 // [00 reg 100][00 100 101] disp32
368 emit_byte(0x04 | regenc);
369 emit_byte(0x25);
370 emit_data(disp, rspec, disp32_operand);
371 }
372 }
373 }
374
375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
376 Address::ScaleFactor scale, int disp,
377 RelocationHolder const& rspec) {
378 emit_operand((Register)reg, base, index, scale, disp, rspec);
379 }
380
381 // Secret local extension to Assembler::WhichOperand:
382 #define end_pc_operand (_WhichOperand_limit)
383
384 address Assembler::locate_operand(address inst, WhichOperand which) {
385 // Decode the given instruction, and return the address of
386 // an embedded 32-bit operand word.
387
388 // If "which" is disp32_operand, selects the displacement portion
389 // of an effective address specifier.
390 // If "which" is imm64_operand, selects the trailing immediate constant.
391 // If "which" is call32_operand, selects the displacement of a call or jump.
392 // Caller is responsible for ensuring that there is such an operand,
393 // and that it is 32/64 bits wide.
394
395 // If "which" is end_pc_operand, find the end of the instruction.
396
397 address ip = inst;
398 bool is_64bit = false;
399
400 debug_only(bool has_disp32 = false);
401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
402
403 again_after_prefix:
404 switch (0xFF & *ip++) {
405
406 // These convenience macros generate groups of "case" labels for the switch.
407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
409 case (x)+4: case (x)+5: case (x)+6: case (x)+7
410 #define REP16(x) REP8((x)+0): \
411 case REP8((x)+8)
412
413 case CS_segment:
414 case SS_segment:
415 case DS_segment:
416 case ES_segment:
417 case FS_segment:
418 case GS_segment:
419 // Seems dubious
420 LP64_ONLY(assert(false, "shouldn't have that prefix"));
421 assert(ip == inst+1, "only one prefix allowed");
422 goto again_after_prefix;
423
424 case 0x67:
425 case REX:
426 case REX_B:
427 case REX_X:
428 case REX_XB:
429 case REX_R:
430 case REX_RB:
431 case REX_RX:
432 case REX_RXB:
433 NOT_LP64(assert(false, "64bit prefixes"));
434 goto again_after_prefix;
435
436 case REX_W:
437 case REX_WB:
438 case REX_WX:
439 case REX_WXB:
440 case REX_WR:
441 case REX_WRB:
442 case REX_WRX:
443 case REX_WRXB:
444 NOT_LP64(assert(false, "64bit prefixes"));
445 is_64bit = true;
446 goto again_after_prefix;
447
448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
449 case 0x88: // movb a, r
450 case 0x89: // movl a, r
451 case 0x8A: // movb r, a
452 case 0x8B: // movl r, a
453 case 0x8F: // popl a
454 debug_only(has_disp32 = true);
455 break;
456
457 case 0x68: // pushq #32
458 if (which == end_pc_operand) {
459 return ip + 4;
460 }
461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
462 return ip; // not produced by emit_operand
463
464 case 0x66: // movw ... (size prefix)
465 again_after_size_prefix2:
466 switch (0xFF & *ip++) {
467 case REX:
468 case REX_B:
469 case REX_X:
470 case REX_XB:
471 case REX_R:
472 case REX_RB:
473 case REX_RX:
474 case REX_RXB:
475 case REX_W:
476 case REX_WB:
477 case REX_WX:
478 case REX_WXB:
479 case REX_WR:
480 case REX_WRB:
481 case REX_WRX:
482 case REX_WRXB:
483 NOT_LP64(assert(false, "64bit prefix found"));
484 goto again_after_size_prefix2;
485 case 0x8B: // movw r, a
486 case 0x89: // movw a, r
487 debug_only(has_disp32 = true);
488 break;
489 case 0xC7: // movw a, #16
490 debug_only(has_disp32 = true);
491 tail_size = 2; // the imm16
492 break;
493 case 0x0F: // several SSE/SSE2 variants
494 ip--; // reparse the 0x0F
495 goto again_after_prefix;
496 default:
497 ShouldNotReachHere();
498 }
499 break;
500
501 case REP8(0xB8): // movl/q r, #32/#64(oop?)
502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
503 // these asserts are somewhat nonsensical
504 #ifndef _LP64
505 assert(which == imm_operand || which == disp32_operand, "");
506 #else
507 assert((which == call32_operand || which == imm_operand) && is_64bit ||
508 which == narrow_oop_operand && !is_64bit, "");
509 #endif // _LP64
510 return ip;
511
512 case 0x69: // imul r, a, #32
513 case 0xC7: // movl a, #32(oop?)
514 tail_size = 4;
515 debug_only(has_disp32 = true); // has both kinds of operands!
516 break;
517
518 case 0x0F: // movx..., etc.
519 switch (0xFF & *ip++) {
520 case 0x12: // movlps
521 case 0x28: // movaps
522 case 0x2E: // ucomiss
523 case 0x2F: // comiss
524 case 0x54: // andps
525 case 0x55: // andnps
526 case 0x56: // orps
527 case 0x57: // xorps
528 case 0x6E: // movd
529 case 0x7E: // movd
530 case 0xAE: // ldmxcsr a
531 // 64bit side says it these have both operands but that doesn't
532 // appear to be true
533 debug_only(has_disp32 = true);
534 break;
535
536 case 0xAD: // shrd r, a, %cl
537 case 0xAF: // imul r, a
538 case 0xBE: // movsbl r, a (movsxb)
539 case 0xBF: // movswl r, a (movsxw)
540 case 0xB6: // movzbl r, a (movzxb)
541 case 0xB7: // movzwl r, a (movzxw)
542 case REP16(0x40): // cmovl cc, r, a
543 case 0xB0: // cmpxchgb
544 case 0xB1: // cmpxchg
545 case 0xC1: // xaddl
546 case 0xC7: // cmpxchg8
547 case REP16(0x90): // setcc a
548 debug_only(has_disp32 = true);
549 // fall out of the switch to decode the address
550 break;
551
552 case 0xAC: // shrd r, a, #8
553 debug_only(has_disp32 = true);
554 tail_size = 1; // the imm8
555 break;
556
557 case REP16(0x80): // jcc rdisp32
558 if (which == end_pc_operand) return ip + 4;
559 assert(which == call32_operand, "jcc has no disp32 or imm");
560 return ip;
561 default:
562 ShouldNotReachHere();
563 }
564 break;
565
566 case 0x81: // addl a, #32; addl r, #32
567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
568 // on 32bit in the case of cmpl, the imm might be an oop
569 tail_size = 4;
570 debug_only(has_disp32 = true); // has both kinds of operands!
571 break;
572
573 case 0x83: // addl a, #8; addl r, #8
574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
575 debug_only(has_disp32 = true); // has both kinds of operands!
576 tail_size = 1;
577 break;
578
579 case 0x9B:
580 switch (0xFF & *ip++) {
581 case 0xD9: // fnstcw a
582 debug_only(has_disp32 = true);
583 break;
584 default:
585 ShouldNotReachHere();
586 }
587 break;
588
589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
590 case REP4(0x10): // adc...
591 case REP4(0x20): // and...
592 case REP4(0x30): // xor...
593 case REP4(0x08): // or...
594 case REP4(0x18): // sbb...
595 case REP4(0x28): // sub...
596 case 0xF7: // mull a
597 case 0x8D: // lea r, a
598 case 0x87: // xchg r, a
599 case REP4(0x38): // cmp...
600 case 0x85: // test r, a
601 debug_only(has_disp32 = true); // has both kinds of operands!
602 break;
603
604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
605 case 0xC6: // movb a, #8
606 case 0x80: // cmpb a, #8
607 case 0x6B: // imul r, a, #8
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 tail_size = 1; // the imm8
610 break;
611
612 case 0xE8: // call rdisp32
613 case 0xE9: // jmp rdisp32
614 if (which == end_pc_operand) return ip + 4;
615 assert(which == call32_operand, "call has no disp32 or imm");
616 return ip;
617
618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
621 case 0xDD: // fld_d a; fst_d a; fstp_d a
622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
623 case 0xDF: // fild_d a; fistp_d a
624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
627 debug_only(has_disp32 = true);
628 break;
629
630 case 0xF0: // Lock
631 assert(os::is_MP(), "only on MP");
632 goto again_after_prefix;
633
634 case 0xF3: // For SSE
635 case 0xF2: // For SSE2
636 switch (0xFF & *ip++) {
637 case REX:
638 case REX_B:
639 case REX_X:
640 case REX_XB:
641 case REX_R:
642 case REX_RB:
643 case REX_RX:
644 case REX_RXB:
645 case REX_W:
646 case REX_WB:
647 case REX_WX:
648 case REX_WXB:
649 case REX_WR:
650 case REX_WRB:
651 case REX_WRX:
652 case REX_WRXB:
653 NOT_LP64(assert(false, "found 64bit prefix"));
654 ip++;
655 default:
656 ip++;
657 }
658 debug_only(has_disp32 = true); // has both kinds of operands!
659 break;
660
661 default:
662 ShouldNotReachHere();
663
664 #undef REP8
665 #undef REP16
666 }
667
668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
669 #ifdef _LP64
670 assert(which != imm_operand, "instruction is not a movq reg, imm64");
671 #else
672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
674 #endif // LP64
675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
676
677 // parse the output of emit_operand
678 int op2 = 0xFF & *ip++;
679 int base = op2 & 0x07;
680 int op3 = -1;
681 const int b100 = 4;
682 const int b101 = 5;
683 if (base == b100 && (op2 >> 6) != 3) {
684 op3 = 0xFF & *ip++;
685 base = op3 & 0x07; // refetch the base
686 }
687 // now ip points at the disp (if any)
688
689 switch (op2 >> 6) {
690 case 0:
691 // [00 reg 100][ss index base]
692 // [00 reg 100][00 100 esp]
693 // [00 reg base]
694 // [00 reg 100][ss index 101][disp32]
695 // [00 reg 101] [disp32]
696
697 if (base == b101) {
698 if (which == disp32_operand)
699 return ip; // caller wants the disp32
700 ip += 4; // skip the disp32
701 }
702 break;
703
704 case 1:
705 // [01 reg 100][ss index base][disp8]
706 // [01 reg 100][00 100 esp][disp8]
707 // [01 reg base] [disp8]
708 ip += 1; // skip the disp8
709 break;
710
711 case 2:
712 // [10 reg 100][ss index base][disp32]
713 // [10 reg 100][00 100 esp][disp32]
714 // [10 reg base] [disp32]
715 if (which == disp32_operand)
716 return ip; // caller wants the disp32
717 ip += 4; // skip the disp32
718 break;
719
720 case 3:
721 // [11 reg base] (not a memory addressing mode)
722 break;
723 }
724
725 if (which == end_pc_operand) {
726 return ip + tail_size;
727 }
728
729 #ifdef _LP64
730 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
731 #else
732 assert(which == imm_operand, "instruction has only an imm field");
733 #endif // LP64
734 return ip;
735 }
736
737 address Assembler::locate_next_instruction(address inst) {
738 // Secretly share code with locate_operand:
739 return locate_operand(inst, end_pc_operand);
740 }
741
742
743 #ifdef ASSERT
744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
745 address inst = inst_mark();
746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
747 address opnd;
748
749 Relocation* r = rspec.reloc();
750 if (r->type() == relocInfo::none) {
751 return;
752 } else if (r->is_call() || format == call32_operand) {
753 // assert(format == imm32_operand, "cannot specify a nonzero format");
754 opnd = locate_operand(inst, call32_operand);
755 } else if (r->is_data()) {
756 assert(format == imm_operand || format == disp32_operand
757 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
758 opnd = locate_operand(inst, (WhichOperand)format);
759 } else {
760 assert(format == imm_operand, "cannot specify a format");
761 return;
762 }
763 assert(opnd == pc(), "must put operand where relocs can find it");
764 }
765 #endif // ASSERT
766
767 void Assembler::emit_operand32(Register reg, Address adr) {
768 assert(reg->encoding() < 8, "no extended registers");
769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
771 adr._rspec);
772 }
773
774 void Assembler::emit_operand(Register reg, Address adr,
775 int rip_relative_correction) {
776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
777 adr._rspec,
778 rip_relative_correction);
779 }
780
781 void Assembler::emit_operand(XMMRegister reg, Address adr) {
782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
783 adr._rspec);
784 }
785
786 // MMX operations
787 void Assembler::emit_operand(MMXRegister reg, Address adr) {
788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
790 }
791
792 // work around gcc (3.2.1-7a) bug
793 void Assembler::emit_operand(Address adr, MMXRegister reg) {
794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
796 }
797
798
799 void Assembler::emit_farith(int b1, int b2, int i) {
800 assert(isByte(b1) && isByte(b2), "wrong opcode");
801 assert(0 <= i && i < 8, "illegal stack offset");
802 emit_byte(b1);
803 emit_byte(b2 + i);
804 }
805
806
807 // Now the Assembler instruction (identical for 32/64 bits)
808
809 void Assembler::adcl(Register dst, int32_t imm32) {
810 prefix(dst);
811 emit_arith(0x81, 0xD0, dst, imm32);
812 }
813
814 void Assembler::adcl(Register dst, Address src) {
815 InstructionMark im(this);
816 prefix(src, dst);
817 emit_byte(0x13);
818 emit_operand(dst, src);
819 }
820
821 void Assembler::adcl(Register dst, Register src) {
822 (void) prefix_and_encode(dst->encoding(), src->encoding());
823 emit_arith(0x13, 0xC0, dst, src);
824 }
825
826 void Assembler::addl(Address dst, int32_t imm32) {
827 InstructionMark im(this);
828 prefix(dst);
829 emit_arith_operand(0x81, rax, dst, imm32);
830 }
831
832 void Assembler::addl(Address dst, Register src) {
833 InstructionMark im(this);
834 prefix(dst, src);
835 emit_byte(0x01);
836 emit_operand(src, dst);
837 }
838
839 void Assembler::addl(Register dst, int32_t imm32) {
840 prefix(dst);
841 emit_arith(0x81, 0xC0, dst, imm32);
842 }
843
844 void Assembler::addl(Register dst, Address src) {
845 InstructionMark im(this);
846 prefix(src, dst);
847 emit_byte(0x03);
848 emit_operand(dst, src);
849 }
850
851 void Assembler::addl(Register dst, Register src) {
852 (void) prefix_and_encode(dst->encoding(), src->encoding());
853 emit_arith(0x03, 0xC0, dst, src);
854 }
855
856 void Assembler::addr_nop_4() {
857 // 4 bytes: NOP DWORD PTR [EAX+0]
858 emit_byte(0x0F);
859 emit_byte(0x1F);
860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
861 emit_byte(0); // 8-bits offset (1 byte)
862 }
863
864 void Assembler::addr_nop_5() {
865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
866 emit_byte(0x0F);
867 emit_byte(0x1F);
868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
870 emit_byte(0); // 8-bits offset (1 byte)
871 }
872
873 void Assembler::addr_nop_7() {
874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
875 emit_byte(0x0F);
876 emit_byte(0x1F);
877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
878 emit_long(0); // 32-bits offset (4 bytes)
879 }
880
881 void Assembler::addr_nop_8() {
882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
883 emit_byte(0x0F);
884 emit_byte(0x1F);
885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
887 emit_long(0); // 32-bits offset (4 bytes)
888 }
889
890 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
891 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
892 emit_byte(0xF2);
893 int encode = prefix_and_encode(dst->encoding(), src->encoding());
894 emit_byte(0x0F);
895 emit_byte(0x58);
896 emit_byte(0xC0 | encode);
897 }
898
899 void Assembler::addsd(XMMRegister dst, Address src) {
900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
901 InstructionMark im(this);
902 emit_byte(0xF2);
903 prefix(src, dst);
904 emit_byte(0x0F);
905 emit_byte(0x58);
906 emit_operand(dst, src);
907 }
908
909 void Assembler::addss(XMMRegister dst, XMMRegister src) {
910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
911 emit_byte(0xF3);
912 int encode = prefix_and_encode(dst->encoding(), src->encoding());
913 emit_byte(0x0F);
914 emit_byte(0x58);
915 emit_byte(0xC0 | encode);
916 }
917
918 void Assembler::addss(XMMRegister dst, Address src) {
919 NOT_LP64(assert(VM_Version::supports_sse(), ""));
920 InstructionMark im(this);
921 emit_byte(0xF3);
922 prefix(src, dst);
923 emit_byte(0x0F);
924 emit_byte(0x58);
925 emit_operand(dst, src);
926 }
927
928 void Assembler::andl(Register dst, int32_t imm32) {
929 prefix(dst);
930 emit_arith(0x81, 0xE0, dst, imm32);
931 }
932
933 void Assembler::andl(Register dst, Address src) {
934 InstructionMark im(this);
935 prefix(src, dst);
936 emit_byte(0x23);
937 emit_operand(dst, src);
938 }
939
940 void Assembler::andl(Register dst, Register src) {
941 (void) prefix_and_encode(dst->encoding(), src->encoding());
942 emit_arith(0x23, 0xC0, dst, src);
943 }
944
945 void Assembler::andpd(XMMRegister dst, Address src) {
946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
947 InstructionMark im(this);
948 emit_byte(0x66);
949 prefix(src, dst);
950 emit_byte(0x0F);
951 emit_byte(0x54);
952 emit_operand(dst, src);
953 }
954
955 void Assembler::bsfl(Register dst, Register src) {
956 int encode = prefix_and_encode(dst->encoding(), src->encoding());
957 emit_byte(0x0F);
958 emit_byte(0xBC);
959 emit_byte(0xC0 | encode);
960 }
961
962 void Assembler::bsrl(Register dst, Register src) {
963 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
964 int encode = prefix_and_encode(dst->encoding(), src->encoding());
965 emit_byte(0x0F);
966 emit_byte(0xBD);
967 emit_byte(0xC0 | encode);
968 }
969
970 void Assembler::bswapl(Register reg) { // bswap
971 int encode = prefix_and_encode(reg->encoding());
972 emit_byte(0x0F);
973 emit_byte(0xC8 | encode);
974 }
975
976 void Assembler::call(Label& L, relocInfo::relocType rtype) {
977 // suspect disp32 is always good
978 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
979
980 if (L.is_bound()) {
981 const int long_size = 5;
982 int offs = (int)( target(L) - pc() );
983 assert(offs <= 0, "assembler error");
984 InstructionMark im(this);
985 // 1110 1000 #32-bit disp
986 emit_byte(0xE8);
987 emit_data(offs - long_size, rtype, operand);
988 } else {
989 InstructionMark im(this);
990 // 1110 1000 #32-bit disp
991 L.add_patch_at(code(), locator());
992
993 emit_byte(0xE8);
994 emit_data(int(0), rtype, operand);
995 }
996 }
997
998 void Assembler::call(Register dst) {
999 // This was originally using a 32bit register encoding
1000 // and surely we want 64bit!
1001 // this is a 32bit encoding but in 64bit mode the default
1002 // operand size is 64bit so there is no need for the
1003 // wide prefix. So prefix only happens if we use the
1004 // new registers. Much like push/pop.
1005 int x = offset();
1006 // this may be true but dbx disassembles it as if it
1007 // were 32bits...
1008 // int encode = prefix_and_encode(dst->encoding());
1009 // if (offset() != x) assert(dst->encoding() >= 8, "what?");
1010 int encode = prefixq_and_encode(dst->encoding());
1011
1012 emit_byte(0xFF);
1013 emit_byte(0xD0 | encode);
1014 }
1015
1016
1017 void Assembler::call(Address adr) {
1018 InstructionMark im(this);
1019 prefix(adr);
1020 emit_byte(0xFF);
1021 emit_operand(rdx, adr);
1022 }
1023
1024 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1025 assert(entry != NULL, "call most probably wrong");
1026 InstructionMark im(this);
1027 emit_byte(0xE8);
1028 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1029 assert(is_simm32(disp), "must be 32bit offset (call2)");
1030 // Technically, should use call32_operand, but this format is
1031 // implied by the fact that we're emitting a call instruction.
1032
1033 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1034 emit_data((int) disp, rspec, operand);
1035 }
1036
1037 void Assembler::cdql() {
1038 emit_byte(0x99);
1039 }
1040
1041 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1042 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1043 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1044 emit_byte(0x0F);
1045 emit_byte(0x40 | cc);
1046 emit_byte(0xC0 | encode);
1047 }
1048
1049
1050 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1051 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1052 prefix(src, dst);
1053 emit_byte(0x0F);
1054 emit_byte(0x40 | cc);
1055 emit_operand(dst, src);
1056 }
1057
1058 void Assembler::cmpb(Address dst, int imm8) {
1059 InstructionMark im(this);
1060 prefix(dst);
1061 emit_byte(0x80);
1062 emit_operand(rdi, dst, 1);
1063 emit_byte(imm8);
1064 }
1065
1066 void Assembler::cmpl(Address dst, int32_t imm32) {
1067 InstructionMark im(this);
1068 prefix(dst);
1069 emit_byte(0x81);
1070 emit_operand(rdi, dst, 4);
1071 emit_long(imm32);
1072 }
1073
1074 void Assembler::cmpl(Register dst, int32_t imm32) {
1075 prefix(dst);
1076 emit_arith(0x81, 0xF8, dst, imm32);
1077 }
1078
1079 void Assembler::cmpl(Register dst, Register src) {
1080 (void) prefix_and_encode(dst->encoding(), src->encoding());
1081 emit_arith(0x3B, 0xC0, dst, src);
1082 }
1083
1084
1085 void Assembler::cmpl(Register dst, Address src) {
1086 InstructionMark im(this);
1087 prefix(src, dst);
1088 emit_byte(0x3B);
1089 emit_operand(dst, src);
1090 }
1091
1092 void Assembler::cmpw(Address dst, int imm16) {
1093 InstructionMark im(this);
1094 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1095 emit_byte(0x66);
1096 emit_byte(0x81);
1097 emit_operand(rdi, dst, 2);
1098 emit_word(imm16);
1099 }
1100
1101 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1102 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1103 // The ZF is set if the compared values were equal, and cleared otherwise.
1104 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1105 if (Atomics & 2) {
1106 // caveat: no instructionmark, so this isn't relocatable.
1107 // Emit a synthetic, non-atomic, CAS equivalent.
1108 // Beware. The synthetic form sets all ICCs, not just ZF.
1109 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1110 cmpl(rax, adr);
1111 movl(rax, adr);
1112 if (reg != rax) {
1113 Label L ;
1114 jcc(Assembler::notEqual, L);
1115 movl(adr, reg);
1116 bind(L);
1117 }
1118 } else {
1119 InstructionMark im(this);
1120 prefix(adr, reg);
1121 emit_byte(0x0F);
1122 emit_byte(0xB1);
1123 emit_operand(reg, adr);
1124 }
1125 }
1126
1127 void Assembler::comisd(XMMRegister dst, Address src) {
1128 // NOTE: dbx seems to decode this as comiss even though the
1129 // 0x66 is there. Strangly ucomisd comes out correct
1130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1131 emit_byte(0x66);
1132 comiss(dst, src);
1133 }
1134
1135 void Assembler::comiss(XMMRegister dst, Address src) {
1136 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1137
1138 InstructionMark im(this);
1139 prefix(src, dst);
1140 emit_byte(0x0F);
1141 emit_byte(0x2F);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1147 emit_byte(0xF3);
1148 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1149 emit_byte(0x0F);
1150 emit_byte(0xE6);
1151 emit_byte(0xC0 | encode);
1152 }
1153
1154 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1155 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1156 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1157 emit_byte(0x0F);
1158 emit_byte(0x5B);
1159 emit_byte(0xC0 | encode);
1160 }
1161
1162 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1164 emit_byte(0xF2);
1165 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1166 emit_byte(0x0F);
1167 emit_byte(0x5A);
1168 emit_byte(0xC0 | encode);
1169 }
1170
1171 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1173 emit_byte(0xF2);
1174 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1175 emit_byte(0x0F);
1176 emit_byte(0x2A);
1177 emit_byte(0xC0 | encode);
1178 }
1179
1180 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1181 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1182 emit_byte(0xF3);
1183 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1184 emit_byte(0x0F);
1185 emit_byte(0x2A);
1186 emit_byte(0xC0 | encode);
1187 }
1188
1189 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1190 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1191 emit_byte(0xF3);
1192 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1193 emit_byte(0x0F);
1194 emit_byte(0x5A);
1195 emit_byte(0xC0 | encode);
1196 }
1197
1198 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1200 emit_byte(0xF2);
1201 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1202 emit_byte(0x0F);
1203 emit_byte(0x2C);
1204 emit_byte(0xC0 | encode);
1205 }
1206
1207 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1208 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1209 emit_byte(0xF3);
1210 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1211 emit_byte(0x0F);
1212 emit_byte(0x2C);
1213 emit_byte(0xC0 | encode);
1214 }
1215
1216 void Assembler::decl(Address dst) {
1217 // Don't use it directly. Use MacroAssembler::decrement() instead.
1218 InstructionMark im(this);
1219 prefix(dst);
1220 emit_byte(0xFF);
1221 emit_operand(rcx, dst);
1222 }
1223
1224 void Assembler::divsd(XMMRegister dst, Address src) {
1225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1226 InstructionMark im(this);
1227 emit_byte(0xF2);
1228 prefix(src, dst);
1229 emit_byte(0x0F);
1230 emit_byte(0x5E);
1231 emit_operand(dst, src);
1232 }
1233
1234 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1236 emit_byte(0xF2);
1237 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1238 emit_byte(0x0F);
1239 emit_byte(0x5E);
1240 emit_byte(0xC0 | encode);
1241 }
1242
1243 void Assembler::divss(XMMRegister dst, Address src) {
1244 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1245 InstructionMark im(this);
1246 emit_byte(0xF3);
1247 prefix(src, dst);
1248 emit_byte(0x0F);
1249 emit_byte(0x5E);
1250 emit_operand(dst, src);
1251 }
1252
1253 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1254 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1255 emit_byte(0xF3);
1256 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1257 emit_byte(0x0F);
1258 emit_byte(0x5E);
1259 emit_byte(0xC0 | encode);
1260 }
1261
1262 void Assembler::emms() {
1263 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1264 emit_byte(0x0F);
1265 emit_byte(0x77);
1266 }
1267
1268 void Assembler::hlt() {
1269 emit_byte(0xF4);
1270 }
1271
1272 void Assembler::idivl(Register src) {
1273 int encode = prefix_and_encode(src->encoding());
1274 emit_byte(0xF7);
1275 emit_byte(0xF8 | encode);
1276 }
1277
1278 void Assembler::imull(Register dst, Register src) {
1279 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1280 emit_byte(0x0F);
1281 emit_byte(0xAF);
1282 emit_byte(0xC0 | encode);
1283 }
1284
1285
1286 void Assembler::imull(Register dst, Register src, int value) {
1287 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1288 if (is8bit(value)) {
1289 emit_byte(0x6B);
1290 emit_byte(0xC0 | encode);
1291 emit_byte(value);
1292 } else {
1293 emit_byte(0x69);
1294 emit_byte(0xC0 | encode);
1295 emit_long(value);
1296 }
1297 }
1298
1299 void Assembler::incl(Address dst) {
1300 // Don't use it directly. Use MacroAssembler::increment() instead.
1301 InstructionMark im(this);
1302 prefix(dst);
1303 emit_byte(0xFF);
1304 emit_operand(rax, dst);
1305 }
1306
1307 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1308 InstructionMark im(this);
1309 relocate(rtype);
1310 assert((0 <= cc) && (cc < 16), "illegal cc");
1311 if (L.is_bound()) {
1312 address dst = target(L);
1313 assert(dst != NULL, "jcc most probably wrong");
1314
1315 const int short_size = 2;
1316 const int long_size = 6;
1317 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1318 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1319 // 0111 tttn #8-bit disp
1320 emit_byte(0x70 | cc);
1321 emit_byte((offs - short_size) & 0xFF);
1322 } else {
1323 // 0000 1111 1000 tttn #32-bit disp
1324 assert(is_simm32(offs - long_size),
1325 "must be 32bit offset (call4)");
1326 emit_byte(0x0F);
1327 emit_byte(0x80 | cc);
1328 emit_long(offs - long_size);
1329 }
1330 } else {
1331 // Note: could eliminate cond. jumps to this jump if condition
1332 // is the same however, seems to be rather unlikely case.
1333 // Note: use jccb() if label to be bound is very close to get
1334 // an 8-bit displacement
1335 L.add_patch_at(code(), locator());
1336 emit_byte(0x0F);
1337 emit_byte(0x80 | cc);
1338 emit_long(0);
1339 }
1340 }
1341
1342 void Assembler::jccb(Condition cc, Label& L) {
1343 if (L.is_bound()) {
1344 const int short_size = 2;
1345 address entry = target(L);
1346 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1347 "Dispacement too large for a short jmp");
1348 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1349 // 0111 tttn #8-bit disp
1350 emit_byte(0x70 | cc);
1351 emit_byte((offs - short_size) & 0xFF);
1352 } else {
1353 InstructionMark im(this);
1354 L.add_patch_at(code(), locator());
1355 emit_byte(0x70 | cc);
1356 emit_byte(0);
1357 }
1358 }
1359
1360 void Assembler::jmp(Address adr) {
1361 InstructionMark im(this);
1362 prefix(adr);
1363 emit_byte(0xFF);
1364 emit_operand(rsp, adr);
1365 }
1366
1367 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1368 if (L.is_bound()) {
1369 address entry = target(L);
1370 assert(entry != NULL, "jmp most probably wrong");
1371 InstructionMark im(this);
1372 const int short_size = 2;
1373 const int long_size = 5;
1374 intptr_t offs = entry - _code_pos;
1375 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1376 emit_byte(0xEB);
1377 emit_byte((offs - short_size) & 0xFF);
1378 } else {
1379 emit_byte(0xE9);
1380 emit_long(offs - long_size);
1381 }
1382 } else {
1383 // By default, forward jumps are always 32-bit displacements, since
1384 // we can't yet know where the label will be bound. If you're sure that
1385 // the forward jump will not run beyond 256 bytes, use jmpb to
1386 // force an 8-bit displacement.
1387 InstructionMark im(this);
1388 relocate(rtype);
1389 L.add_patch_at(code(), locator());
1390 emit_byte(0xE9);
1391 emit_long(0);
1392 }
1393 }
1394
1395 void Assembler::jmp(Register entry) {
1396 int encode = prefix_and_encode(entry->encoding());
1397 emit_byte(0xFF);
1398 emit_byte(0xE0 | encode);
1399 }
1400
1401 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1402 InstructionMark im(this);
1403 emit_byte(0xE9);
1404 assert(dest != NULL, "must have a target");
1405 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1406 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1407 emit_data(disp, rspec.reloc(), call32_operand);
1408 }
1409
1410 void Assembler::jmpb(Label& L) {
1411 if (L.is_bound()) {
1412 const int short_size = 2;
1413 address entry = target(L);
1414 assert(is8bit((entry - _code_pos) + short_size),
1415 "Dispacement too large for a short jmp");
1416 assert(entry != NULL, "jmp most probably wrong");
1417 intptr_t offs = entry - _code_pos;
1418 emit_byte(0xEB);
1419 emit_byte((offs - short_size) & 0xFF);
1420 } else {
1421 InstructionMark im(this);
1422 L.add_patch_at(code(), locator());
1423 emit_byte(0xEB);
1424 emit_byte(0);
1425 }
1426 }
1427
1428 void Assembler::ldmxcsr( Address src) {
1429 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1430 InstructionMark im(this);
1431 prefix(src);
1432 emit_byte(0x0F);
1433 emit_byte(0xAE);
1434 emit_operand(as_Register(2), src);
1435 }
1436
1437 void Assembler::leal(Register dst, Address src) {
1438 InstructionMark im(this);
1439 #ifdef _LP64
1440 emit_byte(0x67); // addr32
1441 prefix(src, dst);
1442 #endif // LP64
1443 emit_byte(0x8D);
1444 emit_operand(dst, src);
1445 }
1446
1447 void Assembler::lock() {
1448 if (Atomics & 1) {
1449 // Emit either nothing, a NOP, or a NOP: prefix
1450 emit_byte(0x90) ;
1451 } else {
1452 emit_byte(0xF0);
1453 }
1454 }
1455
1456 void Assembler::lzcntl(Register dst, Register src) {
1457 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1458 emit_byte(0xF3);
1459 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1460 emit_byte(0x0F);
1461 emit_byte(0xBD);
1462 emit_byte(0xC0 | encode);
1463 }
1464
1465 // Emit mfence instruction
1466 void Assembler::mfence() {
1467 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1468 emit_byte( 0x0F );
1469 emit_byte( 0xAE );
1470 emit_byte( 0xF0 );
1471 }
1472
1473 void Assembler::mov(Register dst, Register src) {
1474 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1475 }
1476
1477 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1479 int dstenc = dst->encoding();
1480 int srcenc = src->encoding();
1481 emit_byte(0x66);
1482 if (dstenc < 8) {
1483 if (srcenc >= 8) {
1484 prefix(REX_B);
1485 srcenc -= 8;
1486 }
1487 } else {
1488 if (srcenc < 8) {
1489 prefix(REX_R);
1490 } else {
1491 prefix(REX_RB);
1492 srcenc -= 8;
1493 }
1494 dstenc -= 8;
1495 }
1496 emit_byte(0x0F);
1497 emit_byte(0x28);
1498 emit_byte(0xC0 | dstenc << 3 | srcenc);
1499 }
1500
1501 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1502 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1503 int dstenc = dst->encoding();
1504 int srcenc = src->encoding();
1505 if (dstenc < 8) {
1506 if (srcenc >= 8) {
1507 prefix(REX_B);
1508 srcenc -= 8;
1509 }
1510 } else {
1511 if (srcenc < 8) {
1512 prefix(REX_R);
1513 } else {
1514 prefix(REX_RB);
1515 srcenc -= 8;
1516 }
1517 dstenc -= 8;
1518 }
1519 emit_byte(0x0F);
1520 emit_byte(0x28);
1521 emit_byte(0xC0 | dstenc << 3 | srcenc);
1522 }
1523
1524 void Assembler::movb(Register dst, Address src) {
1525 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1526 InstructionMark im(this);
1527 prefix(src, dst, true);
1528 emit_byte(0x8A);
1529 emit_operand(dst, src);
1530 }
1531
1532
1533 void Assembler::movb(Address dst, int imm8) {
1534 InstructionMark im(this);
1535 prefix(dst);
1536 emit_byte(0xC6);
1537 emit_operand(rax, dst, 1);
1538 emit_byte(imm8);
1539 }
1540
1541
1542 void Assembler::movb(Address dst, Register src) {
1543 assert(src->has_byte_register(), "must have byte register");
1544 InstructionMark im(this);
1545 prefix(dst, src, true);
1546 emit_byte(0x88);
1547 emit_operand(src, dst);
1548 }
1549
1550 void Assembler::movdl(XMMRegister dst, Register src) {
1551 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1552 emit_byte(0x66);
1553 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1554 emit_byte(0x0F);
1555 emit_byte(0x6E);
1556 emit_byte(0xC0 | encode);
1557 }
1558
1559 void Assembler::movdl(Register dst, XMMRegister src) {
1560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1561 emit_byte(0x66);
1562 // swap src/dst to get correct prefix
1563 int encode = prefix_and_encode(src->encoding(), dst->encoding());
1564 emit_byte(0x0F);
1565 emit_byte(0x7E);
1566 emit_byte(0xC0 | encode);
1567 }
1568
1569 void Assembler::movdqa(XMMRegister dst, Address src) {
1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1571 InstructionMark im(this);
1572 emit_byte(0x66);
1573 prefix(src, dst);
1574 emit_byte(0x0F);
1575 emit_byte(0x6F);
1576 emit_operand(dst, src);
1577 }
1578
1579 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1580 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1581 emit_byte(0x66);
1582 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1583 emit_byte(0x0F);
1584 emit_byte(0x6F);
1585 emit_byte(0xC0 | encode);
1586 }
1587
1588 void Assembler::movdqa(Address dst, XMMRegister src) {
1589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1590 InstructionMark im(this);
1591 emit_byte(0x66);
1592 prefix(dst, src);
1593 emit_byte(0x0F);
1594 emit_byte(0x7F);
1595 emit_operand(src, dst);
1596 }
1597
1598 void Assembler::movdqu(XMMRegister dst, Address src) {
1599 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1600 InstructionMark im(this);
1601 emit_byte(0xF3);
1602 prefix(src, dst);
1603 emit_byte(0x0F);
1604 emit_byte(0x6F);
1605 emit_operand(dst, src);
1606 }
1607
1608 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1610 emit_byte(0xF3);
1611 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1612 emit_byte(0x0F);
1613 emit_byte(0x6F);
1614 emit_byte(0xC0 | encode);
1615 }
1616
1617 void Assembler::movdqu(Address dst, XMMRegister src) {
1618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1619 InstructionMark im(this);
1620 emit_byte(0xF3);
1621 prefix(dst, src);
1622 emit_byte(0x0F);
1623 emit_byte(0x7F);
1624 emit_operand(src, dst);
1625 }
1626
1627 // Uses zero extension on 64bit
1628
1629 void Assembler::movl(Register dst, int32_t imm32) {
1630 int encode = prefix_and_encode(dst->encoding());
1631 emit_byte(0xB8 | encode);
1632 emit_long(imm32);
1633 }
1634
1635 void Assembler::movl(Register dst, Register src) {
1636 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1637 emit_byte(0x8B);
1638 emit_byte(0xC0 | encode);
1639 }
1640
1641 void Assembler::movl(Register dst, Address src) {
1642 InstructionMark im(this);
1643 prefix(src, dst);
1644 emit_byte(0x8B);
1645 emit_operand(dst, src);
1646 }
1647
1648 void Assembler::movl(Address dst, int32_t imm32) {
1649 InstructionMark im(this);
1650 prefix(dst);
1651 emit_byte(0xC7);
1652 emit_operand(rax, dst, 4);
1653 emit_long(imm32);
1654 }
1655
1656 void Assembler::movl(Address dst, Register src) {
1657 InstructionMark im(this);
1658 prefix(dst, src);
1659 emit_byte(0x89);
1660 emit_operand(src, dst);
1661 }
1662
1663 // New cpus require to use movsd and movss to avoid partial register stall
1664 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1665 // The selection is done in MacroAssembler::movdbl() and movflt().
1666 void Assembler::movlpd(XMMRegister dst, Address src) {
1667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1668 InstructionMark im(this);
1669 emit_byte(0x66);
1670 prefix(src, dst);
1671 emit_byte(0x0F);
1672 emit_byte(0x12);
1673 emit_operand(dst, src);
1674 }
1675
1676 void Assembler::movq( MMXRegister dst, Address src ) {
1677 assert( VM_Version::supports_mmx(), "" );
1678 emit_byte(0x0F);
1679 emit_byte(0x6F);
1680 emit_operand(dst, src);
1681 }
1682
1683 void Assembler::movq( Address dst, MMXRegister src ) {
1684 assert( VM_Version::supports_mmx(), "" );
1685 emit_byte(0x0F);
1686 emit_byte(0x7F);
1687 // workaround gcc (3.2.1-7a) bug
1688 // In that version of gcc with only an emit_operand(MMX, Address)
1689 // gcc will tail jump and try and reverse the parameters completely
1690 // obliterating dst in the process. By having a version available
1691 // that doesn't need to swap the args at the tail jump the bug is
1692 // avoided.
1693 emit_operand(dst, src);
1694 }
1695
1696 void Assembler::movq(XMMRegister dst, Address src) {
1697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1698 InstructionMark im(this);
1699 emit_byte(0xF3);
1700 prefix(src, dst);
1701 emit_byte(0x0F);
1702 emit_byte(0x7E);
1703 emit_operand(dst, src);
1704 }
1705
1706 void Assembler::movq(Address dst, XMMRegister src) {
1707 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1708 InstructionMark im(this);
1709 emit_byte(0x66);
1710 prefix(dst, src);
1711 emit_byte(0x0F);
1712 emit_byte(0xD6);
1713 emit_operand(src, dst);
1714 }
1715
1716 void Assembler::movsbl(Register dst, Address src) { // movsxb
1717 InstructionMark im(this);
1718 prefix(src, dst);
1719 emit_byte(0x0F);
1720 emit_byte(0xBE);
1721 emit_operand(dst, src);
1722 }
1723
1724 void Assembler::movsbl(Register dst, Register src) { // movsxb
1725 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1726 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1727 emit_byte(0x0F);
1728 emit_byte(0xBE);
1729 emit_byte(0xC0 | encode);
1730 }
1731
1732 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1734 emit_byte(0xF2);
1735 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1736 emit_byte(0x0F);
1737 emit_byte(0x10);
1738 emit_byte(0xC0 | encode);
1739 }
1740
1741 void Assembler::movsd(XMMRegister dst, Address src) {
1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743 InstructionMark im(this);
1744 emit_byte(0xF2);
1745 prefix(src, dst);
1746 emit_byte(0x0F);
1747 emit_byte(0x10);
1748 emit_operand(dst, src);
1749 }
1750
1751 void Assembler::movsd(Address dst, XMMRegister src) {
1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753 InstructionMark im(this);
1754 emit_byte(0xF2);
1755 prefix(dst, src);
1756 emit_byte(0x0F);
1757 emit_byte(0x11);
1758 emit_operand(src, dst);
1759 }
1760
1761 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1762 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1763 emit_byte(0xF3);
1764 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1765 emit_byte(0x0F);
1766 emit_byte(0x10);
1767 emit_byte(0xC0 | encode);
1768 }
1769
1770 void Assembler::movss(XMMRegister dst, Address src) {
1771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1772 InstructionMark im(this);
1773 emit_byte(0xF3);
1774 prefix(src, dst);
1775 emit_byte(0x0F);
1776 emit_byte(0x10);
1777 emit_operand(dst, src);
1778 }
1779
1780 void Assembler::movss(Address dst, XMMRegister src) {
1781 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1782 InstructionMark im(this);
1783 emit_byte(0xF3);
1784 prefix(dst, src);
1785 emit_byte(0x0F);
1786 emit_byte(0x11);
1787 emit_operand(src, dst);
1788 }
1789
1790 void Assembler::movswl(Register dst, Address src) { // movsxw
1791 InstructionMark im(this);
1792 prefix(src, dst);
1793 emit_byte(0x0F);
1794 emit_byte(0xBF);
1795 emit_operand(dst, src);
1796 }
1797
1798 void Assembler::movswl(Register dst, Register src) { // movsxw
1799 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1800 emit_byte(0x0F);
1801 emit_byte(0xBF);
1802 emit_byte(0xC0 | encode);
1803 }
1804
1805 void Assembler::movw(Address dst, int imm16) {
1806 InstructionMark im(this);
1807
1808 emit_byte(0x66); // switch to 16-bit mode
1809 prefix(dst);
1810 emit_byte(0xC7);
1811 emit_operand(rax, dst, 2);
1812 emit_word(imm16);
1813 }
1814
1815 void Assembler::movw(Register dst, Address src) {
1816 InstructionMark im(this);
1817 emit_byte(0x66);
1818 prefix(src, dst);
1819 emit_byte(0x8B);
1820 emit_operand(dst, src);
1821 }
1822
1823 void Assembler::movw(Address dst, Register src) {
1824 InstructionMark im(this);
1825 emit_byte(0x66);
1826 prefix(dst, src);
1827 emit_byte(0x89);
1828 emit_operand(src, dst);
1829 }
1830
1831 void Assembler::movzbl(Register dst, Address src) { // movzxb
1832 InstructionMark im(this);
1833 prefix(src, dst);
1834 emit_byte(0x0F);
1835 emit_byte(0xB6);
1836 emit_operand(dst, src);
1837 }
1838
1839 void Assembler::movzbl(Register dst, Register src) { // movzxb
1840 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1841 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1842 emit_byte(0x0F);
1843 emit_byte(0xB6);
1844 emit_byte(0xC0 | encode);
1845 }
1846
1847 void Assembler::movzwl(Register dst, Address src) { // movzxw
1848 InstructionMark im(this);
1849 prefix(src, dst);
1850 emit_byte(0x0F);
1851 emit_byte(0xB7);
1852 emit_operand(dst, src);
1853 }
1854
1855 void Assembler::movzwl(Register dst, Register src) { // movzxw
1856 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1857 emit_byte(0x0F);
1858 emit_byte(0xB7);
1859 emit_byte(0xC0 | encode);
1860 }
1861
1862 void Assembler::mull(Address src) {
1863 InstructionMark im(this);
1864 prefix(src);
1865 emit_byte(0xF7);
1866 emit_operand(rsp, src);
1867 }
1868
1869 void Assembler::mull(Register src) {
1870 int encode = prefix_and_encode(src->encoding());
1871 emit_byte(0xF7);
1872 emit_byte(0xE0 | encode);
1873 }
1874
1875 void Assembler::mulsd(XMMRegister dst, Address src) {
1876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1877 InstructionMark im(this);
1878 emit_byte(0xF2);
1879 prefix(src, dst);
1880 emit_byte(0x0F);
1881 emit_byte(0x59);
1882 emit_operand(dst, src);
1883 }
1884
1885 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1887 emit_byte(0xF2);
1888 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1889 emit_byte(0x0F);
1890 emit_byte(0x59);
1891 emit_byte(0xC0 | encode);
1892 }
1893
1894 void Assembler::mulss(XMMRegister dst, Address src) {
1895 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1896 InstructionMark im(this);
1897 emit_byte(0xF3);
1898 prefix(src, dst);
1899 emit_byte(0x0F);
1900 emit_byte(0x59);
1901 emit_operand(dst, src);
1902 }
1903
1904 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1905 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1906 emit_byte(0xF3);
1907 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1908 emit_byte(0x0F);
1909 emit_byte(0x59);
1910 emit_byte(0xC0 | encode);
1911 }
1912
1913 void Assembler::negl(Register dst) {
1914 int encode = prefix_and_encode(dst->encoding());
1915 emit_byte(0xF7);
1916 emit_byte(0xD8 | encode);
1917 }
1918
1919 void Assembler::nop(int i) {
1920 #ifdef ASSERT
1921 assert(i > 0, " ");
1922 // The fancy nops aren't currently recognized by debuggers making it a
1923 // pain to disassemble code while debugging. If asserts are on clearly
1924 // speed is not an issue so simply use the single byte traditional nop
1925 // to do alignment.
1926
1927 for (; i > 0 ; i--) emit_byte(0x90);
1928 return;
1929
1930 #endif // ASSERT
1931
1932 if (UseAddressNop && VM_Version::is_intel()) {
1933 //
1934 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1935 // 1: 0x90
1936 // 2: 0x66 0x90
1937 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1938 // 4: 0x0F 0x1F 0x40 0x00
1939 // 5: 0x0F 0x1F 0x44 0x00 0x00
1940 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1941 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1942 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1943 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1944 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1945 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1946
1947 // The rest coding is Intel specific - don't use consecutive address nops
1948
1949 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1950 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1951 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1952 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1953
1954 while(i >= 15) {
1955 // For Intel don't generate consecutive addess nops (mix with regular nops)
1956 i -= 15;
1957 emit_byte(0x66); // size prefix
1958 emit_byte(0x66); // size prefix
1959 emit_byte(0x66); // size prefix
1960 addr_nop_8();
1961 emit_byte(0x66); // size prefix
1962 emit_byte(0x66); // size prefix
1963 emit_byte(0x66); // size prefix
1964 emit_byte(0x90); // nop
1965 }
1966 switch (i) {
1967 case 14:
1968 emit_byte(0x66); // size prefix
1969 case 13:
1970 emit_byte(0x66); // size prefix
1971 case 12:
1972 addr_nop_8();
1973 emit_byte(0x66); // size prefix
1974 emit_byte(0x66); // size prefix
1975 emit_byte(0x66); // size prefix
1976 emit_byte(0x90); // nop
1977 break;
1978 case 11:
1979 emit_byte(0x66); // size prefix
1980 case 10:
1981 emit_byte(0x66); // size prefix
1982 case 9:
1983 emit_byte(0x66); // size prefix
1984 case 8:
1985 addr_nop_8();
1986 break;
1987 case 7:
1988 addr_nop_7();
1989 break;
1990 case 6:
1991 emit_byte(0x66); // size prefix
1992 case 5:
1993 addr_nop_5();
1994 break;
1995 case 4:
1996 addr_nop_4();
1997 break;
1998 case 3:
1999 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2000 emit_byte(0x66); // size prefix
2001 case 2:
2002 emit_byte(0x66); // size prefix
2003 case 1:
2004 emit_byte(0x90); // nop
2005 break;
2006 default:
2007 assert(i == 0, " ");
2008 }
2009 return;
2010 }
2011 if (UseAddressNop && VM_Version::is_amd()) {
2012 //
2013 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2014 // 1: 0x90
2015 // 2: 0x66 0x90
2016 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2017 // 4: 0x0F 0x1F 0x40 0x00
2018 // 5: 0x0F 0x1F 0x44 0x00 0x00
2019 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2020 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2021 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2022 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2023 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2024 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2025
2026 // The rest coding is AMD specific - use consecutive address nops
2027
2028 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2029 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2030 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2031 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2032 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2033 // Size prefixes (0x66) are added for larger sizes
2034
2035 while(i >= 22) {
2036 i -= 11;
2037 emit_byte(0x66); // size prefix
2038 emit_byte(0x66); // size prefix
2039 emit_byte(0x66); // size prefix
2040 addr_nop_8();
2041 }
2042 // Generate first nop for size between 21-12
2043 switch (i) {
2044 case 21:
2045 i -= 1;
2046 emit_byte(0x66); // size prefix
2047 case 20:
2048 case 19:
2049 i -= 1;
2050 emit_byte(0x66); // size prefix
2051 case 18:
2052 case 17:
2053 i -= 1;
2054 emit_byte(0x66); // size prefix
2055 case 16:
2056 case 15:
2057 i -= 8;
2058 addr_nop_8();
2059 break;
2060 case 14:
2061 case 13:
2062 i -= 7;
2063 addr_nop_7();
2064 break;
2065 case 12:
2066 i -= 6;
2067 emit_byte(0x66); // size prefix
2068 addr_nop_5();
2069 break;
2070 default:
2071 assert(i < 12, " ");
2072 }
2073
2074 // Generate second nop for size between 11-1
2075 switch (i) {
2076 case 11:
2077 emit_byte(0x66); // size prefix
2078 case 10:
2079 emit_byte(0x66); // size prefix
2080 case 9:
2081 emit_byte(0x66); // size prefix
2082 case 8:
2083 addr_nop_8();
2084 break;
2085 case 7:
2086 addr_nop_7();
2087 break;
2088 case 6:
2089 emit_byte(0x66); // size prefix
2090 case 5:
2091 addr_nop_5();
2092 break;
2093 case 4:
2094 addr_nop_4();
2095 break;
2096 case 3:
2097 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2098 emit_byte(0x66); // size prefix
2099 case 2:
2100 emit_byte(0x66); // size prefix
2101 case 1:
2102 emit_byte(0x90); // nop
2103 break;
2104 default:
2105 assert(i == 0, " ");
2106 }
2107 return;
2108 }
2109
2110 // Using nops with size prefixes "0x66 0x90".
2111 // From AMD Optimization Guide:
2112 // 1: 0x90
2113 // 2: 0x66 0x90
2114 // 3: 0x66 0x66 0x90
2115 // 4: 0x66 0x66 0x66 0x90
2116 // 5: 0x66 0x66 0x90 0x66 0x90
2117 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2118 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2119 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2120 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2121 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2122 //
2123 while(i > 12) {
2124 i -= 4;
2125 emit_byte(0x66); // size prefix
2126 emit_byte(0x66);
2127 emit_byte(0x66);
2128 emit_byte(0x90); // nop
2129 }
2130 // 1 - 12 nops
2131 if(i > 8) {
2132 if(i > 9) {
2133 i -= 1;
2134 emit_byte(0x66);
2135 }
2136 i -= 3;
2137 emit_byte(0x66);
2138 emit_byte(0x66);
2139 emit_byte(0x90);
2140 }
2141 // 1 - 8 nops
2142 if(i > 4) {
2143 if(i > 6) {
2144 i -= 1;
2145 emit_byte(0x66);
2146 }
2147 i -= 3;
2148 emit_byte(0x66);
2149 emit_byte(0x66);
2150 emit_byte(0x90);
2151 }
2152 switch (i) {
2153 case 4:
2154 emit_byte(0x66);
2155 case 3:
2156 emit_byte(0x66);
2157 case 2:
2158 emit_byte(0x66);
2159 case 1:
2160 emit_byte(0x90);
2161 break;
2162 default:
2163 assert(i == 0, " ");
2164 }
2165 }
2166
2167 void Assembler::notl(Register dst) {
2168 int encode = prefix_and_encode(dst->encoding());
2169 emit_byte(0xF7);
2170 emit_byte(0xD0 | encode );
2171 }
2172
2173 void Assembler::orl(Address dst, int32_t imm32) {
2174 InstructionMark im(this);
2175 prefix(dst);
2176 emit_byte(0x81);
2177 emit_operand(rcx, dst, 4);
2178 emit_long(imm32);
2179 }
2180
2181 void Assembler::orl(Register dst, int32_t imm32) {
2182 prefix(dst);
2183 emit_arith(0x81, 0xC8, dst, imm32);
2184 }
2185
2186
2187 void Assembler::orl(Register dst, Address src) {
2188 InstructionMark im(this);
2189 prefix(src, dst);
2190 emit_byte(0x0B);
2191 emit_operand(dst, src);
2192 }
2193
2194
2195 void Assembler::orl(Register dst, Register src) {
2196 (void) prefix_and_encode(dst->encoding(), src->encoding());
2197 emit_arith(0x0B, 0xC0, dst, src);
2198 }
2199
2200 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2201 assert(VM_Version::supports_sse4_2(), "");
2202
2203 InstructionMark im(this);
2204 emit_byte(0x66);
2205 prefix(src, dst);
2206 emit_byte(0x0F);
2207 emit_byte(0x3A);
2208 emit_byte(0x61);
2209 emit_operand(dst, src);
2210 emit_byte(imm8);
2211 }
2212
2213 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2214 assert(VM_Version::supports_sse4_2(), "");
2215
2216 emit_byte(0x66);
2217 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2218 emit_byte(0x0F);
2219 emit_byte(0x3A);
2220 emit_byte(0x61);
2221 emit_byte(0xC0 | encode);
2222 emit_byte(imm8);
2223 }
2224
2225 // generic
2226 void Assembler::pop(Register dst) {
2227 int encode = prefix_and_encode(dst->encoding());
2228 emit_byte(0x58 | encode);
2229 }
2230
2231 void Assembler::popcntl(Register dst, Address src) {
2232 assert(VM_Version::supports_popcnt(), "must support");
2233 InstructionMark im(this);
2234 emit_byte(0xF3);
2235 prefix(src, dst);
2236 emit_byte(0x0F);
2237 emit_byte(0xB8);
2238 emit_operand(dst, src);
2239 }
2240
2241 void Assembler::popcntl(Register dst, Register src) {
2242 assert(VM_Version::supports_popcnt(), "must support");
2243 emit_byte(0xF3);
2244 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2245 emit_byte(0x0F);
2246 emit_byte(0xB8);
2247 emit_byte(0xC0 | encode);
2248 }
2249
2250 void Assembler::popf() {
2251 emit_byte(0x9D);
2252 }
2253
2254 #ifndef _LP64 // no 32bit push/pop on amd64
2255 void Assembler::popl(Address dst) {
2256 // NOTE: this will adjust stack by 8byte on 64bits
2257 InstructionMark im(this);
2258 prefix(dst);
2259 emit_byte(0x8F);
2260 emit_operand(rax, dst);
2261 }
2262 #endif
2263
2264 void Assembler::prefetch_prefix(Address src) {
2265 prefix(src);
2266 emit_byte(0x0F);
2267 }
2268
2269 void Assembler::prefetchnta(Address src) {
2270 NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
2271 InstructionMark im(this);
2272 prefetch_prefix(src);
2273 emit_byte(0x18);
2274 emit_operand(rax, src); // 0, src
2275 }
2276
2277 void Assembler::prefetchr(Address src) {
2278 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2279 InstructionMark im(this);
2280 prefetch_prefix(src);
2281 emit_byte(0x0D);
2282 emit_operand(rax, src); // 0, src
2283 }
2284
2285 void Assembler::prefetcht0(Address src) {
2286 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2287 InstructionMark im(this);
2288 prefetch_prefix(src);
2289 emit_byte(0x18);
2290 emit_operand(rcx, src); // 1, src
2291 }
2292
2293 void Assembler::prefetcht1(Address src) {
2294 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2295 InstructionMark im(this);
2296 prefetch_prefix(src);
2297 emit_byte(0x18);
2298 emit_operand(rdx, src); // 2, src
2299 }
2300
2301 void Assembler::prefetcht2(Address src) {
2302 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2303 InstructionMark im(this);
2304 prefetch_prefix(src);
2305 emit_byte(0x18);
2306 emit_operand(rbx, src); // 3, src
2307 }
2308
2309 void Assembler::prefetchw(Address src) {
2310 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2311 InstructionMark im(this);
2312 prefetch_prefix(src);
2313 emit_byte(0x0D);
2314 emit_operand(rcx, src); // 1, src
2315 }
2316
2317 void Assembler::prefix(Prefix p) {
2318 a_byte(p);
2319 }
2320
2321 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2322 assert(isByte(mode), "invalid value");
2323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2324
2325 emit_byte(0x66);
2326 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2327 emit_byte(0x0F);
2328 emit_byte(0x70);
2329 emit_byte(0xC0 | encode);
2330 emit_byte(mode & 0xFF);
2331
2332 }
2333
2334 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2335 assert(isByte(mode), "invalid value");
2336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2337
2338 InstructionMark im(this);
2339 emit_byte(0x66);
2340 prefix(src, dst);
2341 emit_byte(0x0F);
2342 emit_byte(0x70);
2343 emit_operand(dst, src);
2344 emit_byte(mode & 0xFF);
2345 }
2346
2347 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2348 assert(isByte(mode), "invalid value");
2349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2350
2351 emit_byte(0xF2);
2352 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2353 emit_byte(0x0F);
2354 emit_byte(0x70);
2355 emit_byte(0xC0 | encode);
2356 emit_byte(mode & 0xFF);
2357 }
2358
2359 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2360 assert(isByte(mode), "invalid value");
2361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2362
2363 InstructionMark im(this);
2364 emit_byte(0xF2);
2365 prefix(src, dst); // QQ new
2366 emit_byte(0x0F);
2367 emit_byte(0x70);
2368 emit_operand(dst, src);
2369 emit_byte(mode & 0xFF);
2370 }
2371
2372 void Assembler::psrlq(XMMRegister dst, int shift) {
2373 // HMM Table D-1 says sse2 or mmx
2374 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2375
2376 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
2377 emit_byte(0x66);
2378 emit_byte(0x0F);
2379 emit_byte(0x73);
2380 emit_byte(0xC0 | encode);
2381 emit_byte(shift);
2382 }
2383
2384 void Assembler::ptest(XMMRegister dst, Address src) {
2385 assert(VM_Version::supports_sse4_1(), "");
2386
2387 InstructionMark im(this);
2388 emit_byte(0x66);
2389 prefix(src, dst);
2390 emit_byte(0x0F);
2391 emit_byte(0x38);
2392 emit_byte(0x17);
2393 emit_operand(dst, src);
2394 }
2395
2396 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2397 assert(VM_Version::supports_sse4_1(), "");
2398
2399 emit_byte(0x66);
2400 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2401 emit_byte(0x0F);
2402 emit_byte(0x38);
2403 emit_byte(0x17);
2404 emit_byte(0xC0 | encode);
2405 }
2406
2407 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2409 emit_byte(0x66);
2410 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2411 emit_byte(0x0F);
2412 emit_byte(0x60);
2413 emit_byte(0xC0 | encode);
2414 }
2415
2416 void Assembler::push(int32_t imm32) {
2417 // in 64bits we push 64bits onto the stack but only
2418 // take a 32bit immediate
2419 emit_byte(0x68);
2420 emit_long(imm32);
2421 }
2422
2423 void Assembler::push(Register src) {
2424 int encode = prefix_and_encode(src->encoding());
2425
2426 emit_byte(0x50 | encode);
2427 }
2428
2429 void Assembler::pushf() {
2430 emit_byte(0x9C);
2431 }
2432
2433 #ifndef _LP64 // no 32bit push/pop on amd64
2434 void Assembler::pushl(Address src) {
2435 // Note this will push 64bit on 64bit
2436 InstructionMark im(this);
2437 prefix(src);
2438 emit_byte(0xFF);
2439 emit_operand(rsi, src);
2440 }
2441 #endif
2442
2443 void Assembler::pxor(XMMRegister dst, Address src) {
2444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2445 InstructionMark im(this);
2446 emit_byte(0x66);
2447 prefix(src, dst);
2448 emit_byte(0x0F);
2449 emit_byte(0xEF);
2450 emit_operand(dst, src);
2451 }
2452
2453 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2454 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2455 InstructionMark im(this);
2456 emit_byte(0x66);
2457 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2458 emit_byte(0x0F);
2459 emit_byte(0xEF);
2460 emit_byte(0xC0 | encode);
2461 }
2462
2463 void Assembler::rcll(Register dst, int imm8) {
2464 assert(isShiftCount(imm8), "illegal shift count");
2465 int encode = prefix_and_encode(dst->encoding());
2466 if (imm8 == 1) {
2467 emit_byte(0xD1);
2468 emit_byte(0xD0 | encode);
2469 } else {
2470 emit_byte(0xC1);
2471 emit_byte(0xD0 | encode);
2472 emit_byte(imm8);
2473 }
2474 }
2475
2476 // copies data from [esi] to [edi] using rcx pointer sized words
2477 // generic
2478 void Assembler::rep_mov() {
2479 emit_byte(0xF3);
2480 // MOVSQ
2481 LP64_ONLY(prefix(REX_W));
2482 emit_byte(0xA5);
2483 }
2484
2485 // sets rcx pointer sized words with rax, value at [edi]
2486 // generic
2487 void Assembler::rep_set() { // rep_set
2488 emit_byte(0xF3);
2489 // STOSQ
2490 LP64_ONLY(prefix(REX_W));
2491 emit_byte(0xAB);
2492 }
2493
2494 // scans rcx pointer sized words at [edi] for occurance of rax,
2495 // generic
2496 void Assembler::repne_scan() { // repne_scan
2497 emit_byte(0xF2);
2498 // SCASQ
2499 LP64_ONLY(prefix(REX_W));
2500 emit_byte(0xAF);
2501 }
2502
2503 #ifdef _LP64
2504 // scans rcx 4 byte words at [edi] for occurance of rax,
2505 // generic
2506 void Assembler::repne_scanl() { // repne_scan
2507 emit_byte(0xF2);
2508 // SCASL
2509 emit_byte(0xAF);
2510 }
2511 #endif
2512
2513 void Assembler::ret(int imm16) {
2514 if (imm16 == 0) {
2515 emit_byte(0xC3);
2516 } else {
2517 emit_byte(0xC2);
2518 emit_word(imm16);
2519 }
2520 }
2521
2522 void Assembler::sahf() {
2523 #ifdef _LP64
2524 // Not supported in 64bit mode
2525 ShouldNotReachHere();
2526 #endif
2527 emit_byte(0x9E);
2528 }
2529
2530 void Assembler::sarl(Register dst, int imm8) {
2531 int encode = prefix_and_encode(dst->encoding());
2532 assert(isShiftCount(imm8), "illegal shift count");
2533 if (imm8 == 1) {
2534 emit_byte(0xD1);
2535 emit_byte(0xF8 | encode);
2536 } else {
2537 emit_byte(0xC1);
2538 emit_byte(0xF8 | encode);
2539 emit_byte(imm8);
2540 }
2541 }
2542
2543 void Assembler::sarl(Register dst) {
2544 int encode = prefix_and_encode(dst->encoding());
2545 emit_byte(0xD3);
2546 emit_byte(0xF8 | encode);
2547 }
2548
2549 void Assembler::sbbl(Address dst, int32_t imm32) {
2550 InstructionMark im(this);
2551 prefix(dst);
2552 emit_arith_operand(0x81, rbx, dst, imm32);
2553 }
2554
2555 void Assembler::sbbl(Register dst, int32_t imm32) {
2556 prefix(dst);
2557 emit_arith(0x81, 0xD8, dst, imm32);
2558 }
2559
2560
2561 void Assembler::sbbl(Register dst, Address src) {
2562 InstructionMark im(this);
2563 prefix(src, dst);
2564 emit_byte(0x1B);
2565 emit_operand(dst, src);
2566 }
2567
2568 void Assembler::sbbl(Register dst, Register src) {
2569 (void) prefix_and_encode(dst->encoding(), src->encoding());
2570 emit_arith(0x1B, 0xC0, dst, src);
2571 }
2572
2573 void Assembler::setb(Condition cc, Register dst) {
2574 assert(0 <= cc && cc < 16, "illegal cc");
2575 int encode = prefix_and_encode(dst->encoding(), true);
2576 emit_byte(0x0F);
2577 emit_byte(0x90 | cc);
2578 emit_byte(0xC0 | encode);
2579 }
2580
2581 void Assembler::shll(Register dst, int imm8) {
2582 assert(isShiftCount(imm8), "illegal shift count");
2583 int encode = prefix_and_encode(dst->encoding());
2584 if (imm8 == 1 ) {
2585 emit_byte(0xD1);
2586 emit_byte(0xE0 | encode);
2587 } else {
2588 emit_byte(0xC1);
2589 emit_byte(0xE0 | encode);
2590 emit_byte(imm8);
2591 }
2592 }
2593
2594 void Assembler::shll(Register dst) {
2595 int encode = prefix_and_encode(dst->encoding());
2596 emit_byte(0xD3);
2597 emit_byte(0xE0 | encode);
2598 }
2599
2600 void Assembler::shrl(Register dst, int imm8) {
2601 assert(isShiftCount(imm8), "illegal shift count");
2602 int encode = prefix_and_encode(dst->encoding());
2603 emit_byte(0xC1);
2604 emit_byte(0xE8 | encode);
2605 emit_byte(imm8);
2606 }
2607
2608 void Assembler::shrl(Register dst) {
2609 int encode = prefix_and_encode(dst->encoding());
2610 emit_byte(0xD3);
2611 emit_byte(0xE8 | encode);
2612 }
2613
2614 // copies a single word from [esi] to [edi]
2615 void Assembler::smovl() {
2616 emit_byte(0xA5);
2617 }
2618
2619 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2620 // HMM Table D-1 says sse2
2621 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2622 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2623 emit_byte(0xF2);
2624 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2625 emit_byte(0x0F);
2626 emit_byte(0x51);
2627 emit_byte(0xC0 | encode);
2628 }
2629
2630 void Assembler::stmxcsr( Address dst) {
2631 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2632 InstructionMark im(this);
2633 prefix(dst);
2634 emit_byte(0x0F);
2635 emit_byte(0xAE);
2636 emit_operand(as_Register(3), dst);
2637 }
2638
2639 void Assembler::subl(Address dst, int32_t imm32) {
2640 InstructionMark im(this);
2641 prefix(dst);
2642 if (is8bit(imm32)) {
2643 emit_byte(0x83);
2644 emit_operand(rbp, dst, 1);
2645 emit_byte(imm32 & 0xFF);
2646 } else {
2647 emit_byte(0x81);
2648 emit_operand(rbp, dst, 4);
2649 emit_long(imm32);
2650 }
2651 }
2652
2653 void Assembler::subl(Register dst, int32_t imm32) {
2654 prefix(dst);
2655 emit_arith(0x81, 0xE8, dst, imm32);
2656 }
2657
2658 void Assembler::subl(Address dst, Register src) {
2659 InstructionMark im(this);
2660 prefix(dst, src);
2661 emit_byte(0x29);
2662 emit_operand(src, dst);
2663 }
2664
2665 void Assembler::subl(Register dst, Address src) {
2666 InstructionMark im(this);
2667 prefix(src, dst);
2668 emit_byte(0x2B);
2669 emit_operand(dst, src);
2670 }
2671
2672 void Assembler::subl(Register dst, Register src) {
2673 (void) prefix_and_encode(dst->encoding(), src->encoding());
2674 emit_arith(0x2B, 0xC0, dst, src);
2675 }
2676
2677 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2679 emit_byte(0xF2);
2680 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2681 emit_byte(0x0F);
2682 emit_byte(0x5C);
2683 emit_byte(0xC0 | encode);
2684 }
2685
2686 void Assembler::subsd(XMMRegister dst, Address src) {
2687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2688 InstructionMark im(this);
2689 emit_byte(0xF2);
2690 prefix(src, dst);
2691 emit_byte(0x0F);
2692 emit_byte(0x5C);
2693 emit_operand(dst, src);
2694 }
2695
2696 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2697 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2698 emit_byte(0xF3);
2699 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2700 emit_byte(0x0F);
2701 emit_byte(0x5C);
2702 emit_byte(0xC0 | encode);
2703 }
2704
2705 void Assembler::subss(XMMRegister dst, Address src) {
2706 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2707 InstructionMark im(this);
2708 emit_byte(0xF3);
2709 prefix(src, dst);
2710 emit_byte(0x0F);
2711 emit_byte(0x5C);
2712 emit_operand(dst, src);
2713 }
2714
2715 void Assembler::testb(Register dst, int imm8) {
2716 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2717 (void) prefix_and_encode(dst->encoding(), true);
2718 emit_arith_b(0xF6, 0xC0, dst, imm8);
2719 }
2720
2721 void Assembler::testl(Register dst, int32_t imm32) {
2722 // not using emit_arith because test
2723 // doesn't support sign-extension of
2724 // 8bit operands
2725 int encode = dst->encoding();
2726 if (encode == 0) {
2727 emit_byte(0xA9);
2728 } else {
2729 encode = prefix_and_encode(encode);
2730 emit_byte(0xF7);
2731 emit_byte(0xC0 | encode);
2732 }
2733 emit_long(imm32);
2734 }
2735
2736 void Assembler::testl(Register dst, Register src) {
2737 (void) prefix_and_encode(dst->encoding(), src->encoding());
2738 emit_arith(0x85, 0xC0, dst, src);
2739 }
2740
2741 void Assembler::testl(Register dst, Address src) {
2742 InstructionMark im(this);
2743 prefix(src, dst);
2744 emit_byte(0x85);
2745 emit_operand(dst, src);
2746 }
2747
2748 void Assembler::ucomisd(XMMRegister dst, Address src) {
2749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2750 emit_byte(0x66);
2751 ucomiss(dst, src);
2752 }
2753
2754 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2756 emit_byte(0x66);
2757 ucomiss(dst, src);
2758 }
2759
2760 void Assembler::ucomiss(XMMRegister dst, Address src) {
2761 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2762
2763 InstructionMark im(this);
2764 prefix(src, dst);
2765 emit_byte(0x0F);
2766 emit_byte(0x2E);
2767 emit_operand(dst, src);
2768 }
2769
2770 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2772 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2773 emit_byte(0x0F);
2774 emit_byte(0x2E);
2775 emit_byte(0xC0 | encode);
2776 }
2777
2778
2779 void Assembler::xaddl(Address dst, Register src) {
2780 InstructionMark im(this);
2781 prefix(dst, src);
2782 emit_byte(0x0F);
2783 emit_byte(0xC1);
2784 emit_operand(src, dst);
2785 }
2786
2787 void Assembler::xchgl(Register dst, Address src) { // xchg
2788 InstructionMark im(this);
2789 prefix(src, dst);
2790 emit_byte(0x87);
2791 emit_operand(dst, src);
2792 }
2793
2794 void Assembler::xchgl(Register dst, Register src) {
2795 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2796 emit_byte(0x87);
2797 emit_byte(0xc0 | encode);
2798 }
2799
2800 void Assembler::xorl(Register dst, int32_t imm32) {
2801 prefix(dst);
2802 emit_arith(0x81, 0xF0, dst, imm32);
2803 }
2804
2805 void Assembler::xorl(Register dst, Address src) {
2806 InstructionMark im(this);
2807 prefix(src, dst);
2808 emit_byte(0x33);
2809 emit_operand(dst, src);
2810 }
2811
2812 void Assembler::xorl(Register dst, Register src) {
2813 (void) prefix_and_encode(dst->encoding(), src->encoding());
2814 emit_arith(0x33, 0xC0, dst, src);
2815 }
2816
2817 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2819 emit_byte(0x66);
2820 xorps(dst, src);
2821 }
2822
2823 void Assembler::xorpd(XMMRegister dst, Address src) {
2824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2825 InstructionMark im(this);
2826 emit_byte(0x66);
2827 prefix(src, dst);
2828 emit_byte(0x0F);
2829 emit_byte(0x57);
2830 emit_operand(dst, src);
2831 }
2832
2833
2834 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2836 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2837 emit_byte(0x0F);
2838 emit_byte(0x57);
2839 emit_byte(0xC0 | encode);
2840 }
2841
2842 void Assembler::xorps(XMMRegister dst, Address src) {
2843 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2844 InstructionMark im(this);
2845 prefix(src, dst);
2846 emit_byte(0x0F);
2847 emit_byte(0x57);
2848 emit_operand(dst, src);
2849 }
2850
2851 #ifndef _LP64
2852 // 32bit only pieces of the assembler
2853
2854 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2855 // NO PREFIX AS NEVER 64BIT
2856 InstructionMark im(this);
2857 emit_byte(0x81);
2858 emit_byte(0xF8 | src1->encoding());
2859 emit_data(imm32, rspec, 0);
2860 }
2861
2862 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2863 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2864 InstructionMark im(this);
2865 emit_byte(0x81);
2866 emit_operand(rdi, src1);
2867 emit_data(imm32, rspec, 0);
2868 }
2869
2870 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
2871 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
2872 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
2873 void Assembler::cmpxchg8(Address adr) {
2874 InstructionMark im(this);
2875 emit_byte(0x0F);
2876 emit_byte(0xc7);
2877 emit_operand(rcx, adr);
2878 }
2879
2880 void Assembler::decl(Register dst) {
2881 // Don't use it directly. Use MacroAssembler::decrementl() instead.
2882 emit_byte(0x48 | dst->encoding());
2883 }
2884
2885 #endif // _LP64
2886
2887 // 64bit typically doesn't use the x87 but needs to for the trig funcs
2888
2889 void Assembler::fabs() {
2890 emit_byte(0xD9);
2891 emit_byte(0xE1);
2892 }
2893
2894 void Assembler::fadd(int i) {
2895 emit_farith(0xD8, 0xC0, i);
2896 }
2897
2898 void Assembler::fadd_d(Address src) {
2899 InstructionMark im(this);
2900 emit_byte(0xDC);
2901 emit_operand32(rax, src);
2902 }
2903
2904 void Assembler::fadd_s(Address src) {
2905 InstructionMark im(this);
2906 emit_byte(0xD8);
2907 emit_operand32(rax, src);
2908 }
2909
2910 void Assembler::fadda(int i) {
2911 emit_farith(0xDC, 0xC0, i);
2912 }
2913
2914 void Assembler::faddp(int i) {
2915 emit_farith(0xDE, 0xC0, i);
2916 }
2917
2918 void Assembler::fchs() {
2919 emit_byte(0xD9);
2920 emit_byte(0xE0);
2921 }
2922
2923 void Assembler::fcom(int i) {
2924 emit_farith(0xD8, 0xD0, i);
2925 }
2926
2927 void Assembler::fcomp(int i) {
2928 emit_farith(0xD8, 0xD8, i);
2929 }
2930
2931 void Assembler::fcomp_d(Address src) {
2932 InstructionMark im(this);
2933 emit_byte(0xDC);
2934 emit_operand32(rbx, src);
2935 }
2936
2937 void Assembler::fcomp_s(Address src) {
2938 InstructionMark im(this);
2939 emit_byte(0xD8);
2940 emit_operand32(rbx, src);
2941 }
2942
2943 void Assembler::fcompp() {
2944 emit_byte(0xDE);
2945 emit_byte(0xD9);
2946 }
2947
2948 void Assembler::fcos() {
2949 emit_byte(0xD9);
2950 emit_byte(0xFF);
2951 }
2952
2953 void Assembler::fdecstp() {
2954 emit_byte(0xD9);
2955 emit_byte(0xF6);
2956 }
2957
2958 void Assembler::fdiv(int i) {
2959 emit_farith(0xD8, 0xF0, i);
2960 }
2961
2962 void Assembler::fdiv_d(Address src) {
2963 InstructionMark im(this);
2964 emit_byte(0xDC);
2965 emit_operand32(rsi, src);
2966 }
2967
2968 void Assembler::fdiv_s(Address src) {
2969 InstructionMark im(this);
2970 emit_byte(0xD8);
2971 emit_operand32(rsi, src);
2972 }
2973
2974 void Assembler::fdiva(int i) {
2975 emit_farith(0xDC, 0xF8, i);
2976 }
2977
2978 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
2979 // is erroneous for some of the floating-point instructions below.
2980
2981 void Assembler::fdivp(int i) {
2982 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
2983 }
2984
2985 void Assembler::fdivr(int i) {
2986 emit_farith(0xD8, 0xF8, i);
2987 }
2988
2989 void Assembler::fdivr_d(Address src) {
2990 InstructionMark im(this);
2991 emit_byte(0xDC);
2992 emit_operand32(rdi, src);
2993 }
2994
2995 void Assembler::fdivr_s(Address src) {
2996 InstructionMark im(this);
2997 emit_byte(0xD8);
2998 emit_operand32(rdi, src);
2999 }
3000
3001 void Assembler::fdivra(int i) {
3002 emit_farith(0xDC, 0xF0, i);
3003 }
3004
3005 void Assembler::fdivrp(int i) {
3006 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3007 }
3008
3009 void Assembler::ffree(int i) {
3010 emit_farith(0xDD, 0xC0, i);
3011 }
3012
3013 void Assembler::fild_d(Address adr) {
3014 InstructionMark im(this);
3015 emit_byte(0xDF);
3016 emit_operand32(rbp, adr);
3017 }
3018
3019 void Assembler::fild_s(Address adr) {
3020 InstructionMark im(this);
3021 emit_byte(0xDB);
3022 emit_operand32(rax, adr);
3023 }
3024
3025 void Assembler::fincstp() {
3026 emit_byte(0xD9);
3027 emit_byte(0xF7);
3028 }
3029
3030 void Assembler::finit() {
3031 emit_byte(0x9B);
3032 emit_byte(0xDB);
3033 emit_byte(0xE3);
3034 }
3035
3036 void Assembler::fist_s(Address adr) {
3037 InstructionMark im(this);
3038 emit_byte(0xDB);
3039 emit_operand32(rdx, adr);
3040 }
3041
3042 void Assembler::fistp_d(Address adr) {
3043 InstructionMark im(this);
3044 emit_byte(0xDF);
3045 emit_operand32(rdi, adr);
3046 }
3047
3048 void Assembler::fistp_s(Address adr) {
3049 InstructionMark im(this);
3050 emit_byte(0xDB);
3051 emit_operand32(rbx, adr);
3052 }
3053
3054 void Assembler::fld1() {
3055 emit_byte(0xD9);
3056 emit_byte(0xE8);
3057 }
3058
3059 void Assembler::fld_d(Address adr) {
3060 InstructionMark im(this);
3061 emit_byte(0xDD);
3062 emit_operand32(rax, adr);
3063 }
3064
3065 void Assembler::fld_s(Address adr) {
3066 InstructionMark im(this);
3067 emit_byte(0xD9);
3068 emit_operand32(rax, adr);
3069 }
3070
3071
3072 void Assembler::fld_s(int index) {
3073 emit_farith(0xD9, 0xC0, index);
3074 }
3075
3076 void Assembler::fld_x(Address adr) {
3077 InstructionMark im(this);
3078 emit_byte(0xDB);
3079 emit_operand32(rbp, adr);
3080 }
3081
3082 void Assembler::fldcw(Address src) {
3083 InstructionMark im(this);
3084 emit_byte(0xd9);
3085 emit_operand32(rbp, src);
3086 }
3087
3088 void Assembler::fldenv(Address src) {
3089 InstructionMark im(this);
3090 emit_byte(0xD9);
3091 emit_operand32(rsp, src);
3092 }
3093
3094 void Assembler::fldlg2() {
3095 emit_byte(0xD9);
3096 emit_byte(0xEC);
3097 }
3098
3099 void Assembler::fldln2() {
3100 emit_byte(0xD9);
3101 emit_byte(0xED);
3102 }
3103
3104 void Assembler::fldz() {
3105 emit_byte(0xD9);
3106 emit_byte(0xEE);
3107 }
3108
3109 void Assembler::flog() {
3110 fldln2();
3111 fxch();
3112 fyl2x();
3113 }
3114
3115 void Assembler::flog10() {
3116 fldlg2();
3117 fxch();
3118 fyl2x();
3119 }
3120
3121 void Assembler::fmul(int i) {
3122 emit_farith(0xD8, 0xC8, i);
3123 }
3124
3125 void Assembler::fmul_d(Address src) {
3126 InstructionMark im(this);
3127 emit_byte(0xDC);
3128 emit_operand32(rcx, src);
3129 }
3130
3131 void Assembler::fmul_s(Address src) {
3132 InstructionMark im(this);
3133 emit_byte(0xD8);
3134 emit_operand32(rcx, src);
3135 }
3136
3137 void Assembler::fmula(int i) {
3138 emit_farith(0xDC, 0xC8, i);
3139 }
3140
3141 void Assembler::fmulp(int i) {
3142 emit_farith(0xDE, 0xC8, i);
3143 }
3144
3145 void Assembler::fnsave(Address dst) {
3146 InstructionMark im(this);
3147 emit_byte(0xDD);
3148 emit_operand32(rsi, dst);
3149 }
3150
3151 void Assembler::fnstcw(Address src) {
3152 InstructionMark im(this);
3153 emit_byte(0x9B);
3154 emit_byte(0xD9);
3155 emit_operand32(rdi, src);
3156 }
3157
3158 void Assembler::fnstsw_ax() {
3159 emit_byte(0xdF);
3160 emit_byte(0xE0);
3161 }
3162
3163 void Assembler::fprem() {
3164 emit_byte(0xD9);
3165 emit_byte(0xF8);
3166 }
3167
3168 void Assembler::fprem1() {
3169 emit_byte(0xD9);
3170 emit_byte(0xF5);
3171 }
3172
3173 void Assembler::frstor(Address src) {
3174 InstructionMark im(this);
3175 emit_byte(0xDD);
3176 emit_operand32(rsp, src);
3177 }
3178
3179 void Assembler::fsin() {
3180 emit_byte(0xD9);
3181 emit_byte(0xFE);
3182 }
3183
3184 void Assembler::fsqrt() {
3185 emit_byte(0xD9);
3186 emit_byte(0xFA);
3187 }
3188
3189 void Assembler::fst_d(Address adr) {
3190 InstructionMark im(this);
3191 emit_byte(0xDD);
3192 emit_operand32(rdx, adr);
3193 }
3194
3195 void Assembler::fst_s(Address adr) {
3196 InstructionMark im(this);
3197 emit_byte(0xD9);
3198 emit_operand32(rdx, adr);
3199 }
3200
3201 void Assembler::fstp_d(Address adr) {
3202 InstructionMark im(this);
3203 emit_byte(0xDD);
3204 emit_operand32(rbx, adr);
3205 }
3206
3207 void Assembler::fstp_d(int index) {
3208 emit_farith(0xDD, 0xD8, index);
3209 }
3210
3211 void Assembler::fstp_s(Address adr) {
3212 InstructionMark im(this);
3213 emit_byte(0xD9);
3214 emit_operand32(rbx, adr);
3215 }
3216
3217 void Assembler::fstp_x(Address adr) {
3218 InstructionMark im(this);
3219 emit_byte(0xDB);
3220 emit_operand32(rdi, adr);
3221 }
3222
3223 void Assembler::fsub(int i) {
3224 emit_farith(0xD8, 0xE0, i);
3225 }
3226
3227 void Assembler::fsub_d(Address src) {
3228 InstructionMark im(this);
3229 emit_byte(0xDC);
3230 emit_operand32(rsp, src);
3231 }
3232
3233 void Assembler::fsub_s(Address src) {
3234 InstructionMark im(this);
3235 emit_byte(0xD8);
3236 emit_operand32(rsp, src);
3237 }
3238
3239 void Assembler::fsuba(int i) {
3240 emit_farith(0xDC, 0xE8, i);
3241 }
3242
3243 void Assembler::fsubp(int i) {
3244 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3245 }
3246
3247 void Assembler::fsubr(int i) {
3248 emit_farith(0xD8, 0xE8, i);
3249 }
3250
3251 void Assembler::fsubr_d(Address src) {
3252 InstructionMark im(this);
3253 emit_byte(0xDC);
3254 emit_operand32(rbp, src);
3255 }
3256
3257 void Assembler::fsubr_s(Address src) {
3258 InstructionMark im(this);
3259 emit_byte(0xD8);
3260 emit_operand32(rbp, src);
3261 }
3262
3263 void Assembler::fsubra(int i) {
3264 emit_farith(0xDC, 0xE0, i);
3265 }
3266
3267 void Assembler::fsubrp(int i) {
3268 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3269 }
3270
3271 void Assembler::ftan() {
3272 emit_byte(0xD9);
3273 emit_byte(0xF2);
3274 emit_byte(0xDD);
3275 emit_byte(0xD8);
3276 }
3277
3278 void Assembler::ftst() {
3279 emit_byte(0xD9);
3280 emit_byte(0xE4);
3281 }
3282
3283 void Assembler::fucomi(int i) {
3284 // make sure the instruction is supported (introduced for P6, together with cmov)
3285 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3286 emit_farith(0xDB, 0xE8, i);
3287 }
3288
3289 void Assembler::fucomip(int i) {
3290 // make sure the instruction is supported (introduced for P6, together with cmov)
3291 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3292 emit_farith(0xDF, 0xE8, i);
3293 }
3294
3295 void Assembler::fwait() {
3296 emit_byte(0x9B);
3297 }
3298
3299 void Assembler::fxch(int i) {
3300 emit_farith(0xD9, 0xC8, i);
3301 }
3302
3303 void Assembler::fyl2x() {
3304 emit_byte(0xD9);
3305 emit_byte(0xF1);
3306 }
3307
3308
3309 #ifndef _LP64
3310
3311 void Assembler::incl(Register dst) {
3312 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3313 emit_byte(0x40 | dst->encoding());
3314 }
3315
3316 void Assembler::lea(Register dst, Address src) {
3317 leal(dst, src);
3318 }
3319
3320 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3321 InstructionMark im(this);
3322 emit_byte(0xC7);
3323 emit_operand(rax, dst);
3324 emit_data((int)imm32, rspec, 0);
3325 }
3326
3327 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3328 InstructionMark im(this);
3329 int encode = prefix_and_encode(dst->encoding());
3330 emit_byte(0xB8 | encode);
3331 emit_data((int)imm32, rspec, 0);
3332 }
3333
3334 void Assembler::popa() { // 32bit
3335 emit_byte(0x61);
3336 }
3337
3338 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3339 InstructionMark im(this);
3340 emit_byte(0x68);
3341 emit_data(imm32, rspec, 0);
3342 }
3343
3344 void Assembler::pusha() { // 32bit
3345 emit_byte(0x60);
3346 }
3347
3348 void Assembler::set_byte_if_not_zero(Register dst) {
3349 emit_byte(0x0F);
3350 emit_byte(0x95);
3351 emit_byte(0xE0 | dst->encoding());
3352 }
3353
3354 void Assembler::shldl(Register dst, Register src) {
3355 emit_byte(0x0F);
3356 emit_byte(0xA5);
3357 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3358 }
3359
3360 void Assembler::shrdl(Register dst, Register src) {
3361 emit_byte(0x0F);
3362 emit_byte(0xAD);
3363 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3364 }
3365
3366 #else // LP64
3367
3368 // 64bit only pieces of the assembler
3369 // This should only be used by 64bit instructions that can use rip-relative
3370 // it cannot be used by instructions that want an immediate value.
3371
3372 bool Assembler::reachable(AddressLiteral adr) {
3373 int64_t disp;
3374 // None will force a 64bit literal to the code stream. Likely a placeholder
3375 // for something that will be patched later and we need to certain it will
3376 // always be reachable.
3377 if (adr.reloc() == relocInfo::none) {
3378 return false;
3379 }
3380 if (adr.reloc() == relocInfo::internal_word_type) {
3381 // This should be rip relative and easily reachable.
3382 return true;
3383 }
3384 if (adr.reloc() == relocInfo::virtual_call_type ||
3385 adr.reloc() == relocInfo::opt_virtual_call_type ||
3386 adr.reloc() == relocInfo::static_call_type ||
3387 adr.reloc() == relocInfo::static_stub_type ) {
3388 // This should be rip relative within the code cache and easily
3389 // reachable until we get huge code caches. (At which point
3390 // ic code is going to have issues).
3391 return true;
3392 }
3393 if (adr.reloc() != relocInfo::external_word_type &&
3394 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3395 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3396 adr.reloc() != relocInfo::runtime_call_type ) {
3397 return false;
3398 }
3399
3400 // Stress the correction code
3401 if (ForceUnreachable) {
3402 // Must be runtimecall reloc, see if it is in the codecache
3403 // Flipping stuff in the codecache to be unreachable causes issues
3404 // with things like inline caches where the additional instructions
3405 // are not handled.
3406 if (CodeCache::find_blob(adr._target) == NULL) {
3407 return false;
3408 }
3409 }
3410 // For external_word_type/runtime_call_type if it is reachable from where we
3411 // are now (possibly a temp buffer) and where we might end up
3412 // anywhere in the codeCache then we are always reachable.
3413 // This would have to change if we ever save/restore shared code
3414 // to be more pessimistic.
3415
3416 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3417 if (!is_simm32(disp)) return false;
3418 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3419 if (!is_simm32(disp)) return false;
3420
3421 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3422
3423 // Because rip relative is a disp + address_of_next_instruction and we
3424 // don't know the value of address_of_next_instruction we apply a fudge factor
3425 // to make sure we will be ok no matter the size of the instruction we get placed into.
3426 // We don't have to fudge the checks above here because they are already worst case.
3427
3428 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3429 // + 4 because better safe than sorry.
3430 const int fudge = 12 + 4;
3431 if (disp < 0) {
3432 disp -= fudge;
3433 } else {
3434 disp += fudge;
3435 }
3436 return is_simm32(disp);
3437 }
3438
3439 void Assembler::emit_data64(jlong data,
3440 relocInfo::relocType rtype,
3441 int format) {
3442 if (rtype == relocInfo::none) {
3443 emit_long64(data);
3444 } else {
3445 emit_data64(data, Relocation::spec_simple(rtype), format);
3446 }
3447 }
3448
3449 void Assembler::emit_data64(jlong data,
3450 RelocationHolder const& rspec,
3451 int format) {
3452 assert(imm_operand == 0, "default format must be immediate in this file");
3453 assert(imm_operand == format, "must be immediate");
3454 assert(inst_mark() != NULL, "must be inside InstructionMark");
3455 // Do not use AbstractAssembler::relocate, which is not intended for
3456 // embedded words. Instead, relocate to the enclosing instruction.
3457 code_section()->relocate(inst_mark(), rspec, format);
3458 #ifdef ASSERT
3459 check_relocation(rspec, format);
3460 #endif
3461 emit_long64(data);
3462 }
3463
3464 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3465 if (reg_enc >= 8) {
3466 prefix(REX_B);
3467 reg_enc -= 8;
3468 } else if (byteinst && reg_enc >= 4) {
3469 prefix(REX);
3470 }
3471 return reg_enc;
3472 }
3473
3474 int Assembler::prefixq_and_encode(int reg_enc) {
3475 if (reg_enc < 8) {
3476 prefix(REX_W);
3477 } else {
3478 prefix(REX_WB);
3479 reg_enc -= 8;
3480 }
3481 return reg_enc;
3482 }
3483
3484 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3485 if (dst_enc < 8) {
3486 if (src_enc >= 8) {
3487 prefix(REX_B);
3488 src_enc -= 8;
3489 } else if (byteinst && src_enc >= 4) {
3490 prefix(REX);
3491 }
3492 } else {
3493 if (src_enc < 8) {
3494 prefix(REX_R);
3495 } else {
3496 prefix(REX_RB);
3497 src_enc -= 8;
3498 }
3499 dst_enc -= 8;
3500 }
3501 return dst_enc << 3 | src_enc;
3502 }
3503
3504 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
3505 if (dst_enc < 8) {
3506 if (src_enc < 8) {
3507 prefix(REX_W);
3508 } else {
3509 prefix(REX_WB);
3510 src_enc -= 8;
3511 }
3512 } else {
3513 if (src_enc < 8) {
3514 prefix(REX_WR);
3515 } else {
3516 prefix(REX_WRB);
3517 src_enc -= 8;
3518 }
3519 dst_enc -= 8;
3520 }
3521 return dst_enc << 3 | src_enc;
3522 }
3523
3524 void Assembler::prefix(Register reg) {
3525 if (reg->encoding() >= 8) {
3526 prefix(REX_B);
3527 }
3528 }
3529
3530 void Assembler::prefix(Address adr) {
3531 if (adr.base_needs_rex()) {
3532 if (adr.index_needs_rex()) {
3533 prefix(REX_XB);
3534 } else {
3535 prefix(REX_B);
3536 }
3537 } else {
3538 if (adr.index_needs_rex()) {
3539 prefix(REX_X);
3540 }
3541 }
3542 }
3543
3544 void Assembler::prefixq(Address adr) {
3545 if (adr.base_needs_rex()) {
3546 if (adr.index_needs_rex()) {
3547 prefix(REX_WXB);
3548 } else {
3549 prefix(REX_WB);
3550 }
3551 } else {
3552 if (adr.index_needs_rex()) {
3553 prefix(REX_WX);
3554 } else {
3555 prefix(REX_W);
3556 }
3557 }
3558 }
3559
3560
3561 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
3562 if (reg->encoding() < 8) {
3563 if (adr.base_needs_rex()) {
3564 if (adr.index_needs_rex()) {
3565 prefix(REX_XB);
3566 } else {
3567 prefix(REX_B);
3568 }
3569 } else {
3570 if (adr.index_needs_rex()) {
3571 prefix(REX_X);
3572 } else if (reg->encoding() >= 4 ) {
3573 prefix(REX);
3574 }
3575 }
3576 } else {
3577 if (adr.base_needs_rex()) {
3578 if (adr.index_needs_rex()) {
3579 prefix(REX_RXB);
3580 } else {
3581 prefix(REX_RB);
3582 }
3583 } else {
3584 if (adr.index_needs_rex()) {
3585 prefix(REX_RX);
3586 } else {
3587 prefix(REX_R);
3588 }
3589 }
3590 }
3591 }
3592
3593 void Assembler::prefixq(Address adr, Register src) {
3594 if (src->encoding() < 8) {
3595 if (adr.base_needs_rex()) {
3596 if (adr.index_needs_rex()) {
3597 prefix(REX_WXB);
3598 } else {
3599 prefix(REX_WB);
3600 }
3601 } else {
3602 if (adr.index_needs_rex()) {
3603 prefix(REX_WX);
3604 } else {
3605 prefix(REX_W);
3606 }
3607 }
3608 } else {
3609 if (adr.base_needs_rex()) {
3610 if (adr.index_needs_rex()) {
3611 prefix(REX_WRXB);
3612 } else {
3613 prefix(REX_WRB);
3614 }
3615 } else {
3616 if (adr.index_needs_rex()) {
3617 prefix(REX_WRX);
3618 } else {
3619 prefix(REX_WR);
3620 }
3621 }
3622 }
3623 }
3624
3625 void Assembler::prefix(Address adr, XMMRegister reg) {
3626 if (reg->encoding() < 8) {
3627 if (adr.base_needs_rex()) {
3628 if (adr.index_needs_rex()) {
3629 prefix(REX_XB);
3630 } else {
3631 prefix(REX_B);
3632 }
3633 } else {
3634 if (adr.index_needs_rex()) {
3635 prefix(REX_X);
3636 }
3637 }
3638 } else {
3639 if (adr.base_needs_rex()) {
3640 if (adr.index_needs_rex()) {
3641 prefix(REX_RXB);
3642 } else {
3643 prefix(REX_RB);
3644 }
3645 } else {
3646 if (adr.index_needs_rex()) {
3647 prefix(REX_RX);
3648 } else {
3649 prefix(REX_R);
3650 }
3651 }
3652 }
3653 }
3654
3655 void Assembler::adcq(Register dst, int32_t imm32) {
3656 (void) prefixq_and_encode(dst->encoding());
3657 emit_arith(0x81, 0xD0, dst, imm32);
3658 }
3659
3660 void Assembler::adcq(Register dst, Address src) {
3661 InstructionMark im(this);
3662 prefixq(src, dst);
3663 emit_byte(0x13);
3664 emit_operand(dst, src);
3665 }
3666
3667 void Assembler::adcq(Register dst, Register src) {
3668 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3669 emit_arith(0x13, 0xC0, dst, src);
3670 }
3671
3672 void Assembler::addq(Address dst, int32_t imm32) {
3673 InstructionMark im(this);
3674 prefixq(dst);
3675 emit_arith_operand(0x81, rax, dst,imm32);
3676 }
3677
3678 void Assembler::addq(Address dst, Register src) {
3679 InstructionMark im(this);
3680 prefixq(dst, src);
3681 emit_byte(0x01);
3682 emit_operand(src, dst);
3683 }
3684
3685 void Assembler::addq(Register dst, int32_t imm32) {
3686 (void) prefixq_and_encode(dst->encoding());
3687 emit_arith(0x81, 0xC0, dst, imm32);
3688 }
3689
3690 void Assembler::addq(Register dst, Address src) {
3691 InstructionMark im(this);
3692 prefixq(src, dst);
3693 emit_byte(0x03);
3694 emit_operand(dst, src);
3695 }
3696
3697 void Assembler::addq(Register dst, Register src) {
3698 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3699 emit_arith(0x03, 0xC0, dst, src);
3700 }
3701
3702 void Assembler::andq(Register dst, int32_t imm32) {
3703 (void) prefixq_and_encode(dst->encoding());
3704 emit_arith(0x81, 0xE0, dst, imm32);
3705 }
3706
3707 void Assembler::andq(Register dst, Address src) {
3708 InstructionMark im(this);
3709 prefixq(src, dst);
3710 emit_byte(0x23);
3711 emit_operand(dst, src);
3712 }
3713
3714 void Assembler::andq(Register dst, Register src) {
3715 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3716 emit_arith(0x23, 0xC0, dst, src);
3717 }
3718
3719 void Assembler::bsfq(Register dst, Register src) {
3720 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3721 emit_byte(0x0F);
3722 emit_byte(0xBC);
3723 emit_byte(0xC0 | encode);
3724 }
3725
3726 void Assembler::bsrq(Register dst, Register src) {
3727 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
3728 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3729 emit_byte(0x0F);
3730 emit_byte(0xBD);
3731 emit_byte(0xC0 | encode);
3732 }
3733
3734 void Assembler::bswapq(Register reg) {
3735 int encode = prefixq_and_encode(reg->encoding());
3736 emit_byte(0x0F);
3737 emit_byte(0xC8 | encode);
3738 }
3739
3740 void Assembler::cdqq() {
3741 prefix(REX_W);
3742 emit_byte(0x99);
3743 }
3744
3745 void Assembler::clflush(Address adr) {
3746 prefix(adr);
3747 emit_byte(0x0F);
3748 emit_byte(0xAE);
3749 emit_operand(rdi, adr);
3750 }
3751
3752 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3753 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3754 emit_byte(0x0F);
3755 emit_byte(0x40 | cc);
3756 emit_byte(0xC0 | encode);
3757 }
3758
3759 void Assembler::cmovq(Condition cc, Register dst, Address src) {
3760 InstructionMark im(this);
3761 prefixq(src, dst);
3762 emit_byte(0x0F);
3763 emit_byte(0x40 | cc);
3764 emit_operand(dst, src);
3765 }
3766
3767 void Assembler::cmpq(Address dst, int32_t imm32) {
3768 InstructionMark im(this);
3769 prefixq(dst);
3770 emit_byte(0x81);
3771 emit_operand(rdi, dst, 4);
3772 emit_long(imm32);
3773 }
3774
3775 void Assembler::cmpq(Register dst, int32_t imm32) {
3776 (void) prefixq_and_encode(dst->encoding());
3777 emit_arith(0x81, 0xF8, dst, imm32);
3778 }
3779
3780 void Assembler::cmpq(Address dst, Register src) {
3781 InstructionMark im(this);
3782 prefixq(dst, src);
3783 emit_byte(0x3B);
3784 emit_operand(src, dst);
3785 }
3786
3787 void Assembler::cmpq(Register dst, Register src) {
3788 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3789 emit_arith(0x3B, 0xC0, dst, src);
3790 }
3791
3792 void Assembler::cmpq(Register dst, Address src) {
3793 InstructionMark im(this);
3794 prefixq(src, dst);
3795 emit_byte(0x3B);
3796 emit_operand(dst, src);
3797 }
3798
3799 void Assembler::cmpxchgq(Register reg, Address adr) {
3800 InstructionMark im(this);
3801 prefixq(adr, reg);
3802 emit_byte(0x0F);
3803 emit_byte(0xB1);
3804 emit_operand(reg, adr);
3805 }
3806
3807 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
3808 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3809 emit_byte(0xF2);
3810 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3811 emit_byte(0x0F);
3812 emit_byte(0x2A);
3813 emit_byte(0xC0 | encode);
3814 }
3815
3816 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
3817 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3818 emit_byte(0xF3);
3819 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3820 emit_byte(0x0F);
3821 emit_byte(0x2A);
3822 emit_byte(0xC0 | encode);
3823 }
3824
3825 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3826 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3827 emit_byte(0xF2);
3828 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3829 emit_byte(0x0F);
3830 emit_byte(0x2C);
3831 emit_byte(0xC0 | encode);
3832 }
3833
3834 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
3835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3836 emit_byte(0xF3);
3837 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3838 emit_byte(0x0F);
3839 emit_byte(0x2C);
3840 emit_byte(0xC0 | encode);
3841 }
3842
3843 void Assembler::decl(Register dst) {
3844 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3845 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
3846 int encode = prefix_and_encode(dst->encoding());
3847 emit_byte(0xFF);
3848 emit_byte(0xC8 | encode);
3849 }
3850
3851 void Assembler::decq(Register dst) {
3852 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3853 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3854 int encode = prefixq_and_encode(dst->encoding());
3855 emit_byte(0xFF);
3856 emit_byte(0xC8 | encode);
3857 }
3858
3859 void Assembler::decq(Address dst) {
3860 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3861 InstructionMark im(this);
3862 prefixq(dst);
3863 emit_byte(0xFF);
3864 emit_operand(rcx, dst);
3865 }
3866
3867 void Assembler::fxrstor(Address src) {
3868 prefixq(src);
3869 emit_byte(0x0F);
3870 emit_byte(0xAE);
3871 emit_operand(as_Register(1), src);
3872 }
3873
3874 void Assembler::fxsave(Address dst) {
3875 prefixq(dst);
3876 emit_byte(0x0F);
3877 emit_byte(0xAE);
3878 emit_operand(as_Register(0), dst);
3879 }
3880
3881 void Assembler::idivq(Register src) {
3882 int encode = prefixq_and_encode(src->encoding());
3883 emit_byte(0xF7);
3884 emit_byte(0xF8 | encode);
3885 }
3886
3887 void Assembler::imulq(Register dst, Register src) {
3888 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3889 emit_byte(0x0F);
3890 emit_byte(0xAF);
3891 emit_byte(0xC0 | encode);
3892 }
3893
3894 void Assembler::imulq(Register dst, Register src, int value) {
3895 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3896 if (is8bit(value)) {
3897 emit_byte(0x6B);
3898 emit_byte(0xC0 | encode);
3899 emit_byte(value);
3900 } else {
3901 emit_byte(0x69);
3902 emit_byte(0xC0 | encode);
3903 emit_long(value);
3904 }
3905 }
3906
3907 void Assembler::incl(Register dst) {
3908 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3909 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3910 int encode = prefix_and_encode(dst->encoding());
3911 emit_byte(0xFF);
3912 emit_byte(0xC0 | encode);
3913 }
3914
3915 void Assembler::incq(Register dst) {
3916 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3917 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3918 int encode = prefixq_and_encode(dst->encoding());
3919 emit_byte(0xFF);
3920 emit_byte(0xC0 | encode);
3921 }
3922
3923 void Assembler::incq(Address dst) {
3924 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3925 InstructionMark im(this);
3926 prefixq(dst);
3927 emit_byte(0xFF);
3928 emit_operand(rax, dst);
3929 }
3930
3931 void Assembler::lea(Register dst, Address src) {
3932 leaq(dst, src);
3933 }
3934
3935 void Assembler::leaq(Register dst, Address src) {
3936 InstructionMark im(this);
3937 prefixq(src, dst);
3938 emit_byte(0x8D);
3939 emit_operand(dst, src);
3940 }
3941
3942 void Assembler::mov64(Register dst, int64_t imm64) {
3943 InstructionMark im(this);
3944 int encode = prefixq_and_encode(dst->encoding());
3945 emit_byte(0xB8 | encode);
3946 emit_long64(imm64);
3947 }
3948
3949 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
3950 InstructionMark im(this);
3951 int encode = prefixq_and_encode(dst->encoding());
3952 emit_byte(0xB8 | encode);
3953 emit_data64(imm64, rspec);
3954 }
3955
3956 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3957 InstructionMark im(this);
3958 int encode = prefix_and_encode(dst->encoding());
3959 emit_byte(0xB8 | encode);
3960 emit_data((int)imm32, rspec, narrow_oop_operand);
3961 }
3962
3963 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3964 InstructionMark im(this);
3965 prefix(dst);
3966 emit_byte(0xC7);
3967 emit_operand(rax, dst, 4);
3968 emit_data((int)imm32, rspec, narrow_oop_operand);
3969 }
3970
3971 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3972 InstructionMark im(this);
3973 int encode = prefix_and_encode(src1->encoding());
3974 emit_byte(0x81);
3975 emit_byte(0xF8 | encode);
3976 emit_data((int)imm32, rspec, narrow_oop_operand);
3977 }
3978
3979 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3980 InstructionMark im(this);
3981 prefix(src1);
3982 emit_byte(0x81);
3983 emit_operand(rax, src1, 4);
3984 emit_data((int)imm32, rspec, narrow_oop_operand);
3985 }
3986
3987 void Assembler::lzcntq(Register dst, Register src) {
3988 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
3989 emit_byte(0xF3);
3990 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3991 emit_byte(0x0F);
3992 emit_byte(0xBD);
3993 emit_byte(0xC0 | encode);
3994 }
3995
3996 void Assembler::movdq(XMMRegister dst, Register src) {
3997 // table D-1 says MMX/SSE2
3998 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
3999 emit_byte(0x66);
4000 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4001 emit_byte(0x0F);
4002 emit_byte(0x6E);
4003 emit_byte(0xC0 | encode);
4004 }
4005
4006 void Assembler::movdq(Register dst, XMMRegister src) {
4007 // table D-1 says MMX/SSE2
4008 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4009 emit_byte(0x66);
4010 // swap src/dst to get correct prefix
4011 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4012 emit_byte(0x0F);
4013 emit_byte(0x7E);
4014 emit_byte(0xC0 | encode);
4015 }
4016
4017 void Assembler::movq(Register dst, Register src) {
4018 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4019 emit_byte(0x8B);
4020 emit_byte(0xC0 | encode);
4021 }
4022
4023 void Assembler::movq(Register dst, Address src) {
4024 InstructionMark im(this);
4025 prefixq(src, dst);
4026 emit_byte(0x8B);
4027 emit_operand(dst, src);
4028 }
4029
4030 void Assembler::movq(Address dst, Register src) {
4031 InstructionMark im(this);
4032 prefixq(dst, src);
4033 emit_byte(0x89);
4034 emit_operand(src, dst);
4035 }
4036
4037 void Assembler::movsbq(Register dst, Address src) {
4038 InstructionMark im(this);
4039 prefixq(src, dst);
4040 emit_byte(0x0F);
4041 emit_byte(0xBE);
4042 emit_operand(dst, src);
4043 }
4044
4045 void Assembler::movsbq(Register dst, Register src) {
4046 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4047 emit_byte(0x0F);
4048 emit_byte(0xBE);
4049 emit_byte(0xC0 | encode);
4050 }
4051
4052 void Assembler::movslq(Register dst, int32_t imm32) {
4053 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4054 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4055 // as a result we shouldn't use until tested at runtime...
4056 ShouldNotReachHere();
4057 InstructionMark im(this);
4058 int encode = prefixq_and_encode(dst->encoding());
4059 emit_byte(0xC7 | encode);
4060 emit_long(imm32);
4061 }
4062
4063 void Assembler::movslq(Address dst, int32_t imm32) {
4064 assert(is_simm32(imm32), "lost bits");
4065 InstructionMark im(this);
4066 prefixq(dst);
4067 emit_byte(0xC7);
4068 emit_operand(rax, dst, 4);
4069 emit_long(imm32);
4070 }
4071
4072 void Assembler::movslq(Register dst, Address src) {
4073 InstructionMark im(this);
4074 prefixq(src, dst);
4075 emit_byte(0x63);
4076 emit_operand(dst, src);
4077 }
4078
4079 void Assembler::movslq(Register dst, Register src) {
4080 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4081 emit_byte(0x63);
4082 emit_byte(0xC0 | encode);
4083 }
4084
4085 void Assembler::movswq(Register dst, Address src) {
4086 InstructionMark im(this);
4087 prefixq(src, dst);
4088 emit_byte(0x0F);
4089 emit_byte(0xBF);
4090 emit_operand(dst, src);
4091 }
4092
4093 void Assembler::movswq(Register dst, Register src) {
4094 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4095 emit_byte(0x0F);
4096 emit_byte(0xBF);
4097 emit_byte(0xC0 | encode);
4098 }
4099
4100 void Assembler::movzbq(Register dst, Address src) {
4101 InstructionMark im(this);
4102 prefixq(src, dst);
4103 emit_byte(0x0F);
4104 emit_byte(0xB6);
4105 emit_operand(dst, src);
4106 }
4107
4108 void Assembler::movzbq(Register dst, Register src) {
4109 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4110 emit_byte(0x0F);
4111 emit_byte(0xB6);
4112 emit_byte(0xC0 | encode);
4113 }
4114
4115 void Assembler::movzwq(Register dst, Address src) {
4116 InstructionMark im(this);
4117 prefixq(src, dst);
4118 emit_byte(0x0F);
4119 emit_byte(0xB7);
4120 emit_operand(dst, src);
4121 }
4122
4123 void Assembler::movzwq(Register dst, Register src) {
4124 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4125 emit_byte(0x0F);
4126 emit_byte(0xB7);
4127 emit_byte(0xC0 | encode);
4128 }
4129
4130 void Assembler::negq(Register dst) {
4131 int encode = prefixq_and_encode(dst->encoding());
4132 emit_byte(0xF7);
4133 emit_byte(0xD8 | encode);
4134 }
4135
4136 void Assembler::notq(Register dst) {
4137 int encode = prefixq_and_encode(dst->encoding());
4138 emit_byte(0xF7);
4139 emit_byte(0xD0 | encode);
4140 }
4141
4142 void Assembler::orq(Address dst, int32_t imm32) {
4143 InstructionMark im(this);
4144 prefixq(dst);
4145 emit_byte(0x81);
4146 emit_operand(rcx, dst, 4);
4147 emit_long(imm32);
4148 }
4149
4150 void Assembler::orq(Register dst, int32_t imm32) {
4151 (void) prefixq_and_encode(dst->encoding());
4152 emit_arith(0x81, 0xC8, dst, imm32);
4153 }
4154
4155 void Assembler::orq(Register dst, Address src) {
4156 InstructionMark im(this);
4157 prefixq(src, dst);
4158 emit_byte(0x0B);
4159 emit_operand(dst, src);
4160 }
4161
4162 void Assembler::orq(Register dst, Register src) {
4163 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4164 emit_arith(0x0B, 0xC0, dst, src);
4165 }
4166
4167 void Assembler::popa() { // 64bit
4168 movq(r15, Address(rsp, 0));
4169 movq(r14, Address(rsp, wordSize));
4170 movq(r13, Address(rsp, 2 * wordSize));
4171 movq(r12, Address(rsp, 3 * wordSize));
4172 movq(r11, Address(rsp, 4 * wordSize));
4173 movq(r10, Address(rsp, 5 * wordSize));
4174 movq(r9, Address(rsp, 6 * wordSize));
4175 movq(r8, Address(rsp, 7 * wordSize));
4176 movq(rdi, Address(rsp, 8 * wordSize));
4177 movq(rsi, Address(rsp, 9 * wordSize));
4178 movq(rbp, Address(rsp, 10 * wordSize));
4179 // skip rsp
4180 movq(rbx, Address(rsp, 12 * wordSize));
4181 movq(rdx, Address(rsp, 13 * wordSize));
4182 movq(rcx, Address(rsp, 14 * wordSize));
4183 movq(rax, Address(rsp, 15 * wordSize));
4184
4185 addq(rsp, 16 * wordSize);
4186 }
4187
4188 void Assembler::popcntq(Register dst, Address src) {
4189 assert(VM_Version::supports_popcnt(), "must support");
4190 InstructionMark im(this);
4191 emit_byte(0xF3);
4192 prefixq(src, dst);
4193 emit_byte(0x0F);
4194 emit_byte(0xB8);
4195 emit_operand(dst, src);
4196 }
4197
4198 void Assembler::popcntq(Register dst, Register src) {
4199 assert(VM_Version::supports_popcnt(), "must support");
4200 emit_byte(0xF3);
4201 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4202 emit_byte(0x0F);
4203 emit_byte(0xB8);
4204 emit_byte(0xC0 | encode);
4205 }
4206
4207 void Assembler::popq(Address dst) {
4208 InstructionMark im(this);
4209 prefixq(dst);
4210 emit_byte(0x8F);
4211 emit_operand(rax, dst);
4212 }
4213
4214 void Assembler::pusha() { // 64bit
4215 // we have to store original rsp. ABI says that 128 bytes
4216 // below rsp are local scratch.
4217 movq(Address(rsp, -5 * wordSize), rsp);
4218
4219 subq(rsp, 16 * wordSize);
4220
4221 movq(Address(rsp, 15 * wordSize), rax);
4222 movq(Address(rsp, 14 * wordSize), rcx);
4223 movq(Address(rsp, 13 * wordSize), rdx);
4224 movq(Address(rsp, 12 * wordSize), rbx);
4225 // skip rsp
4226 movq(Address(rsp, 10 * wordSize), rbp);
4227 movq(Address(rsp, 9 * wordSize), rsi);
4228 movq(Address(rsp, 8 * wordSize), rdi);
4229 movq(Address(rsp, 7 * wordSize), r8);
4230 movq(Address(rsp, 6 * wordSize), r9);
4231 movq(Address(rsp, 5 * wordSize), r10);
4232 movq(Address(rsp, 4 * wordSize), r11);
4233 movq(Address(rsp, 3 * wordSize), r12);
4234 movq(Address(rsp, 2 * wordSize), r13);
4235 movq(Address(rsp, wordSize), r14);
4236 movq(Address(rsp, 0), r15);
4237 }
4238
4239 void Assembler::pushq(Address src) {
4240 InstructionMark im(this);
4241 prefixq(src);
4242 emit_byte(0xFF);
4243 emit_operand(rsi, src);
4244 }
4245
4246 void Assembler::rclq(Register dst, int imm8) {
4247 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4248 int encode = prefixq_and_encode(dst->encoding());
4249 if (imm8 == 1) {
4250 emit_byte(0xD1);
4251 emit_byte(0xD0 | encode);
4252 } else {
4253 emit_byte(0xC1);
4254 emit_byte(0xD0 | encode);
4255 emit_byte(imm8);
4256 }
4257 }
4258 void Assembler::sarq(Register dst, int imm8) {
4259 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4260 int encode = prefixq_and_encode(dst->encoding());
4261 if (imm8 == 1) {
4262 emit_byte(0xD1);
4263 emit_byte(0xF8 | encode);
4264 } else {
4265 emit_byte(0xC1);
4266 emit_byte(0xF8 | encode);
4267 emit_byte(imm8);
4268 }
4269 }
4270
4271 void Assembler::sarq(Register dst) {
4272 int encode = prefixq_and_encode(dst->encoding());
4273 emit_byte(0xD3);
4274 emit_byte(0xF8 | encode);
4275 }
4276 void Assembler::sbbq(Address dst, int32_t imm32) {
4277 InstructionMark im(this);
4278 prefixq(dst);
4279 emit_arith_operand(0x81, rbx, dst, imm32);
4280 }
4281
4282 void Assembler::sbbq(Register dst, int32_t imm32) {
4283 (void) prefixq_and_encode(dst->encoding());
4284 emit_arith(0x81, 0xD8, dst, imm32);
4285 }
4286
4287 void Assembler::sbbq(Register dst, Address src) {
4288 InstructionMark im(this);
4289 prefixq(src, dst);
4290 emit_byte(0x1B);
4291 emit_operand(dst, src);
4292 }
4293
4294 void Assembler::sbbq(Register dst, Register src) {
4295 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4296 emit_arith(0x1B, 0xC0, dst, src);
4297 }
4298
4299 void Assembler::shlq(Register dst, int imm8) {
4300 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4301 int encode = prefixq_and_encode(dst->encoding());
4302 if (imm8 == 1) {
4303 emit_byte(0xD1);
4304 emit_byte(0xE0 | encode);
4305 } else {
4306 emit_byte(0xC1);
4307 emit_byte(0xE0 | encode);
4308 emit_byte(imm8);
4309 }
4310 }
4311
4312 void Assembler::shlq(Register dst) {
4313 int encode = prefixq_and_encode(dst->encoding());
4314 emit_byte(0xD3);
4315 emit_byte(0xE0 | encode);
4316 }
4317
4318 void Assembler::shrq(Register dst, int imm8) {
4319 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4320 int encode = prefixq_and_encode(dst->encoding());
4321 emit_byte(0xC1);
4322 emit_byte(0xE8 | encode);
4323 emit_byte(imm8);
4324 }
4325
4326 void Assembler::shrq(Register dst) {
4327 int encode = prefixq_and_encode(dst->encoding());
4328 emit_byte(0xD3);
4329 emit_byte(0xE8 | encode);
4330 }
4331
4332 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4334 InstructionMark im(this);
4335 emit_byte(0xF2);
4336 prefix(src, dst);
4337 emit_byte(0x0F);
4338 emit_byte(0x51);
4339 emit_operand(dst, src);
4340 }
4341
4342 void Assembler::subq(Address dst, int32_t imm32) {
4343 InstructionMark im(this);
4344 prefixq(dst);
4345 if (is8bit(imm32)) {
4346 emit_byte(0x83);
4347 emit_operand(rbp, dst, 1);
4348 emit_byte(imm32 & 0xFF);
4349 } else {
4350 emit_byte(0x81);
4351 emit_operand(rbp, dst, 4);
4352 emit_long(imm32);
4353 }
4354 }
4355
4356 void Assembler::subq(Register dst, int32_t imm32) {
4357 (void) prefixq_and_encode(dst->encoding());
4358 emit_arith(0x81, 0xE8, dst, imm32);
4359 }
4360
4361 void Assembler::subq(Address dst, Register src) {
4362 InstructionMark im(this);
4363 prefixq(dst, src);
4364 emit_byte(0x29);
4365 emit_operand(src, dst);
4366 }
4367
4368 void Assembler::subq(Register dst, Address src) {
4369 InstructionMark im(this);
4370 prefixq(src, dst);
4371 emit_byte(0x2B);
4372 emit_operand(dst, src);
4373 }
4374
4375 void Assembler::subq(Register dst, Register src) {
4376 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4377 emit_arith(0x2B, 0xC0, dst, src);
4378 }
4379
4380 void Assembler::testq(Register dst, int32_t imm32) {
4381 // not using emit_arith because test
4382 // doesn't support sign-extension of
4383 // 8bit operands
4384 int encode = dst->encoding();
4385 if (encode == 0) {
4386 prefix(REX_W);
4387 emit_byte(0xA9);
4388 } else {
4389 encode = prefixq_and_encode(encode);
4390 emit_byte(0xF7);
4391 emit_byte(0xC0 | encode);
4392 }
4393 emit_long(imm32);
4394 }
4395
4396 void Assembler::testq(Register dst, Register src) {
4397 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4398 emit_arith(0x85, 0xC0, dst, src);
4399 }
4400
4401 void Assembler::xaddq(Address dst, Register src) {
4402 InstructionMark im(this);
4403 prefixq(dst, src);
4404 emit_byte(0x0F);
4405 emit_byte(0xC1);
4406 emit_operand(src, dst);
4407 }
4408
4409 void Assembler::xchgq(Register dst, Address src) {
4410 InstructionMark im(this);
4411 prefixq(src, dst);
4412 emit_byte(0x87);
4413 emit_operand(dst, src);
4414 }
4415
4416 void Assembler::xchgq(Register dst, Register src) {
4417 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4418 emit_byte(0x87);
4419 emit_byte(0xc0 | encode);
4420 }
4421
4422 void Assembler::xorq(Register dst, Register src) {
4423 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4424 emit_arith(0x33, 0xC0, dst, src);
4425 }
4426
4427 void Assembler::xorq(Register dst, Address src) {
4428 InstructionMark im(this);
4429 prefixq(src, dst);
4430 emit_byte(0x33);
4431 emit_operand(dst, src);
4432 }
4433
4434 #endif // !LP64
4435
4436 static Assembler::Condition reverse[] = {
4437 Assembler::noOverflow /* overflow = 0x0 */ ,
4438 Assembler::overflow /* noOverflow = 0x1 */ ,
4439 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4440 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4441 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4442 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4443 Assembler::above /* belowEqual = 0x6 */ ,
4444 Assembler::belowEqual /* above = 0x7 */ ,
4445 Assembler::positive /* negative = 0x8 */ ,
4446 Assembler::negative /* positive = 0x9 */ ,
4447 Assembler::noParity /* parity = 0xa */ ,
4448 Assembler::parity /* noParity = 0xb */ ,
4449 Assembler::greaterEqual /* less = 0xc */ ,
4450 Assembler::less /* greaterEqual = 0xd */ ,
4451 Assembler::greater /* lessEqual = 0xe */ ,
4452 Assembler::lessEqual /* greater = 0xf, */
4453
4454 };
4455
4456
4457 // Implementation of MacroAssembler
4458
4459 // First all the versions that have distinct versions depending on 32/64 bit
4460 // Unless the difference is trivial (1 line or so).
4461
4462 #ifndef _LP64
4463
4464 // 32bit versions
4465
4466 Address MacroAssembler::as_Address(AddressLiteral adr) {
4467 return Address(adr.target(), adr.rspec());
4468 }
4469
4470 Address MacroAssembler::as_Address(ArrayAddress adr) {
4471 return Address::make_array(adr);
4472 }
4473
4474 int MacroAssembler::biased_locking_enter(Register lock_reg,
4475 Register obj_reg,
4476 Register swap_reg,
4477 Register tmp_reg,
4478 bool swap_reg_contains_mark,
4479 Label& done,
4480 Label* slow_case,
4481 BiasedLockingCounters* counters) {
4482 assert(UseBiasedLocking, "why call this otherwise?");
4483 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4484 assert_different_registers(lock_reg, obj_reg, swap_reg);
4485
4486 if (PrintBiasedLockingStatistics && counters == NULL)
4487 counters = BiasedLocking::counters();
4488
4489 bool need_tmp_reg = false;
4490 if (tmp_reg == noreg) {
4491 need_tmp_reg = true;
4492 tmp_reg = lock_reg;
4493 } else {
4494 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4495 }
4496 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4497 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4498 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4499 Address saved_mark_addr(lock_reg, 0);
4500
4501 // Biased locking
4502 // See whether the lock is currently biased toward our thread and
4503 // whether the epoch is still valid
4504 // Note that the runtime guarantees sufficient alignment of JavaThread
4505 // pointers to allow age to be placed into low bits
4506 // First check to see whether biasing is even enabled for this object
4507 Label cas_label;
4508 int null_check_offset = -1;
4509 if (!swap_reg_contains_mark) {
4510 null_check_offset = offset();
4511 movl(swap_reg, mark_addr);
4512 }
4513 if (need_tmp_reg) {
4514 push(tmp_reg);
4515 }
4516 movl(tmp_reg, swap_reg);
4517 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4518 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4519 if (need_tmp_reg) {
4520 pop(tmp_reg);
4521 }
4522 jcc(Assembler::notEqual, cas_label);
4523 // The bias pattern is present in the object's header. Need to check
4524 // whether the bias owner and the epoch are both still current.
4525 // Note that because there is no current thread register on x86 we
4526 // need to store off the mark word we read out of the object to
4527 // avoid reloading it and needing to recheck invariants below. This
4528 // store is unfortunate but it makes the overall code shorter and
4529 // simpler.
4530 movl(saved_mark_addr, swap_reg);
4531 if (need_tmp_reg) {
4532 push(tmp_reg);
4533 }
4534 get_thread(tmp_reg);
4535 xorl(swap_reg, tmp_reg);
4536 if (swap_reg_contains_mark) {
4537 null_check_offset = offset();
4538 }
4539 movl(tmp_reg, klass_addr);
4540 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4541 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4542 if (need_tmp_reg) {
4543 pop(tmp_reg);
4544 }
4545 if (counters != NULL) {
4546 cond_inc32(Assembler::zero,
4547 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4548 }
4549 jcc(Assembler::equal, done);
4550
4551 Label try_revoke_bias;
4552 Label try_rebias;
4553
4554 // At this point we know that the header has the bias pattern and
4555 // that we are not the bias owner in the current epoch. We need to
4556 // figure out more details about the state of the header in order to
4557 // know what operations can be legally performed on the object's
4558 // header.
4559
4560 // If the low three bits in the xor result aren't clear, that means
4561 // the prototype header is no longer biased and we have to revoke
4562 // the bias on this object.
4563 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4564 jcc(Assembler::notZero, try_revoke_bias);
4565
4566 // Biasing is still enabled for this data type. See whether the
4567 // epoch of the current bias is still valid, meaning that the epoch
4568 // bits of the mark word are equal to the epoch bits of the
4569 // prototype header. (Note that the prototype header's epoch bits
4570 // only change at a safepoint.) If not, attempt to rebias the object
4571 // toward the current thread. Note that we must be absolutely sure
4572 // that the current epoch is invalid in order to do this because
4573 // otherwise the manipulations it performs on the mark word are
4574 // illegal.
4575 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4576 jcc(Assembler::notZero, try_rebias);
4577
4578 // The epoch of the current bias is still valid but we know nothing
4579 // about the owner; it might be set or it might be clear. Try to
4580 // acquire the bias of the object using an atomic operation. If this
4581 // fails we will go in to the runtime to revoke the object's bias.
4582 // Note that we first construct the presumed unbiased header so we
4583 // don't accidentally blow away another thread's valid bias.
4584 movl(swap_reg, saved_mark_addr);
4585 andl(swap_reg,
4586 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4587 if (need_tmp_reg) {
4588 push(tmp_reg);
4589 }
4590 get_thread(tmp_reg);
4591 orl(tmp_reg, swap_reg);
4592 if (os::is_MP()) {
4593 lock();
4594 }
4595 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4596 if (need_tmp_reg) {
4597 pop(tmp_reg);
4598 }
4599 // If the biasing toward our thread failed, this means that
4600 // another thread succeeded in biasing it toward itself and we
4601 // need to revoke that bias. The revocation will occur in the
4602 // interpreter runtime in the slow case.
4603 if (counters != NULL) {
4604 cond_inc32(Assembler::zero,
4605 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4606 }
4607 if (slow_case != NULL) {
4608 jcc(Assembler::notZero, *slow_case);
4609 }
4610 jmp(done);
4611
4612 bind(try_rebias);
4613 // At this point we know the epoch has expired, meaning that the
4614 // current "bias owner", if any, is actually invalid. Under these
4615 // circumstances _only_, we are allowed to use the current header's
4616 // value as the comparison value when doing the cas to acquire the
4617 // bias in the current epoch. In other words, we allow transfer of
4618 // the bias from one thread to another directly in this situation.
4619 //
4620 // FIXME: due to a lack of registers we currently blow away the age
4621 // bits in this situation. Should attempt to preserve them.
4622 if (need_tmp_reg) {
4623 push(tmp_reg);
4624 }
4625 get_thread(tmp_reg);
4626 movl(swap_reg, klass_addr);
4627 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4628 movl(swap_reg, saved_mark_addr);
4629 if (os::is_MP()) {
4630 lock();
4631 }
4632 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4633 if (need_tmp_reg) {
4634 pop(tmp_reg);
4635 }
4636 // If the biasing toward our thread failed, then another thread
4637 // succeeded in biasing it toward itself and we need to revoke that
4638 // bias. The revocation will occur in the runtime in the slow case.
4639 if (counters != NULL) {
4640 cond_inc32(Assembler::zero,
4641 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4642 }
4643 if (slow_case != NULL) {
4644 jcc(Assembler::notZero, *slow_case);
4645 }
4646 jmp(done);
4647
4648 bind(try_revoke_bias);
4649 // The prototype mark in the klass doesn't have the bias bit set any
4650 // more, indicating that objects of this data type are not supposed
4651 // to be biased any more. We are going to try to reset the mark of
4652 // this object to the prototype value and fall through to the
4653 // CAS-based locking scheme. Note that if our CAS fails, it means
4654 // that another thread raced us for the privilege of revoking the
4655 // bias of this particular object, so it's okay to continue in the
4656 // normal locking code.
4657 //
4658 // FIXME: due to a lack of registers we currently blow away the age
4659 // bits in this situation. Should attempt to preserve them.
4660 movl(swap_reg, saved_mark_addr);
4661 if (need_tmp_reg) {
4662 push(tmp_reg);
4663 }
4664 movl(tmp_reg, klass_addr);
4665 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4666 if (os::is_MP()) {
4667 lock();
4668 }
4669 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4670 if (need_tmp_reg) {
4671 pop(tmp_reg);
4672 }
4673 // Fall through to the normal CAS-based lock, because no matter what
4674 // the result of the above CAS, some thread must have succeeded in
4675 // removing the bias bit from the object's header.
4676 if (counters != NULL) {
4677 cond_inc32(Assembler::zero,
4678 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4679 }
4680
4681 bind(cas_label);
4682
4683 return null_check_offset;
4684 }
4685 void MacroAssembler::call_VM_leaf_base(address entry_point,
4686 int number_of_arguments) {
4687 call(RuntimeAddress(entry_point));
4688 increment(rsp, number_of_arguments * wordSize);
4689 }
4690
4691 void MacroAssembler::cmpoop(Address src1, jobject obj) {
4692 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4693 }
4694
4695 void MacroAssembler::cmpoop(Register src1, jobject obj) {
4696 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4697 }
4698
4699 void MacroAssembler::extend_sign(Register hi, Register lo) {
4700 // According to Intel Doc. AP-526, "Integer Divide", p.18.
4701 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
4702 cdql();
4703 } else {
4704 movl(hi, lo);
4705 sarl(hi, 31);
4706 }
4707 }
4708
4709 void MacroAssembler::fat_nop() {
4710 // A 5 byte nop that is safe for patching (see patch_verified_entry)
4711 emit_byte(0x26); // es:
4712 emit_byte(0x2e); // cs:
4713 emit_byte(0x64); // fs:
4714 emit_byte(0x65); // gs:
4715 emit_byte(0x90);
4716 }
4717
4718 void MacroAssembler::jC2(Register tmp, Label& L) {
4719 // set parity bit if FPU flag C2 is set (via rax)
4720 save_rax(tmp);
4721 fwait(); fnstsw_ax();
4722 sahf();
4723 restore_rax(tmp);
4724 // branch
4725 jcc(Assembler::parity, L);
4726 }
4727
4728 void MacroAssembler::jnC2(Register tmp, Label& L) {
4729 // set parity bit if FPU flag C2 is set (via rax)
4730 save_rax(tmp);
4731 fwait(); fnstsw_ax();
4732 sahf();
4733 restore_rax(tmp);
4734 // branch
4735 jcc(Assembler::noParity, L);
4736 }
4737
4738 // 32bit can do a case table jump in one instruction but we no longer allow the base
4739 // to be installed in the Address class
4740 void MacroAssembler::jump(ArrayAddress entry) {
4741 jmp(as_Address(entry));
4742 }
4743
4744 // Note: y_lo will be destroyed
4745 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
4746 // Long compare for Java (semantics as described in JVM spec.)
4747 Label high, low, done;
4748
4749 cmpl(x_hi, y_hi);
4750 jcc(Assembler::less, low);
4751 jcc(Assembler::greater, high);
4752 // x_hi is the return register
4753 xorl(x_hi, x_hi);
4754 cmpl(x_lo, y_lo);
4755 jcc(Assembler::below, low);
4756 jcc(Assembler::equal, done);
4757
4758 bind(high);
4759 xorl(x_hi, x_hi);
4760 increment(x_hi);
4761 jmp(done);
4762
4763 bind(low);
4764 xorl(x_hi, x_hi);
4765 decrementl(x_hi);
4766
4767 bind(done);
4768 }
4769
4770 void MacroAssembler::lea(Register dst, AddressLiteral src) {
4771 mov_literal32(dst, (int32_t)src.target(), src.rspec());
4772 }
4773
4774 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
4775 // leal(dst, as_Address(adr));
4776 // see note in movl as to why we must use a move
4777 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
4778 }
4779
4780 void MacroAssembler::leave() {
4781 mov(rsp, rbp);
4782 pop(rbp);
4783 }
4784
4785 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
4786 // Multiplication of two Java long values stored on the stack
4787 // as illustrated below. Result is in rdx:rax.
4788 //
4789 // rsp ---> [ ?? ] \ \
4790 // .... | y_rsp_offset |
4791 // [ y_lo ] / (in bytes) | x_rsp_offset
4792 // [ y_hi ] | (in bytes)
4793 // .... |
4794 // [ x_lo ] /
4795 // [ x_hi ]
4796 // ....
4797 //
4798 // Basic idea: lo(result) = lo(x_lo * y_lo)
4799 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
4800 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
4801 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
4802 Label quick;
4803 // load x_hi, y_hi and check if quick
4804 // multiplication is possible
4805 movl(rbx, x_hi);
4806 movl(rcx, y_hi);
4807 movl(rax, rbx);
4808 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
4809 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
4810 // do full multiplication
4811 // 1st step
4812 mull(y_lo); // x_hi * y_lo
4813 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
4814 // 2nd step
4815 movl(rax, x_lo);
4816 mull(rcx); // x_lo * y_hi
4817 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
4818 // 3rd step
4819 bind(quick); // note: rbx, = 0 if quick multiply!
4820 movl(rax, x_lo);
4821 mull(y_lo); // x_lo * y_lo
4822 addl(rdx, rbx); // correct hi(x_lo * y_lo)
4823 }
4824
4825 void MacroAssembler::lneg(Register hi, Register lo) {
4826 negl(lo);
4827 adcl(hi, 0);
4828 negl(hi);
4829 }
4830
4831 void MacroAssembler::lshl(Register hi, Register lo) {
4832 // Java shift left long support (semantics as described in JVM spec., p.305)
4833 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
4834 // shift value is in rcx !
4835 assert(hi != rcx, "must not use rcx");
4836 assert(lo != rcx, "must not use rcx");
4837 const Register s = rcx; // shift count
4838 const int n = BitsPerWord;
4839 Label L;
4840 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4841 cmpl(s, n); // if (s < n)
4842 jcc(Assembler::less, L); // else (s >= n)
4843 movl(hi, lo); // x := x << n
4844 xorl(lo, lo);
4845 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4846 bind(L); // s (mod n) < n
4847 shldl(hi, lo); // x := x << s
4848 shll(lo);
4849 }
4850
4851
4852 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
4853 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
4854 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
4855 assert(hi != rcx, "must not use rcx");
4856 assert(lo != rcx, "must not use rcx");
4857 const Register s = rcx; // shift count
4858 const int n = BitsPerWord;
4859 Label L;
4860 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4861 cmpl(s, n); // if (s < n)
4862 jcc(Assembler::less, L); // else (s >= n)
4863 movl(lo, hi); // x := x >> n
4864 if (sign_extension) sarl(hi, 31);
4865 else xorl(hi, hi);
4866 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4867 bind(L); // s (mod n) < n
4868 shrdl(lo, hi); // x := x >> s
4869 if (sign_extension) sarl(hi);
4870 else shrl(hi);
4871 }
4872
4873 void MacroAssembler::movoop(Register dst, jobject obj) {
4874 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4875 }
4876
4877 void MacroAssembler::movoop(Address dst, jobject obj) {
4878 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4879 }
4880
4881 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
4882 if (src.is_lval()) {
4883 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
4884 } else {
4885 movl(dst, as_Address(src));
4886 }
4887 }
4888
4889 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
4890 movl(as_Address(dst), src);
4891 }
4892
4893 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
4894 movl(dst, as_Address(src));
4895 }
4896
4897 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
4898 void MacroAssembler::movptr(Address dst, intptr_t src) {
4899 movl(dst, src);
4900 }
4901
4902
4903 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
4904 movsd(dst, as_Address(src));
4905 }
4906
4907 void MacroAssembler::pop_callee_saved_registers() {
4908 pop(rcx);
4909 pop(rdx);
4910 pop(rdi);
4911 pop(rsi);
4912 }
4913
4914 void MacroAssembler::pop_fTOS() {
4915 fld_d(Address(rsp, 0));
4916 addl(rsp, 2 * wordSize);
4917 }
4918
4919 void MacroAssembler::push_callee_saved_registers() {
4920 push(rsi);
4921 push(rdi);
4922 push(rdx);
4923 push(rcx);
4924 }
4925
4926 void MacroAssembler::push_fTOS() {
4927 subl(rsp, 2 * wordSize);
4928 fstp_d(Address(rsp, 0));
4929 }
4930
4931
4932 void MacroAssembler::pushoop(jobject obj) {
4933 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
4934 }
4935
4936
4937 void MacroAssembler::pushptr(AddressLiteral src) {
4938 if (src.is_lval()) {
4939 push_literal32((int32_t)src.target(), src.rspec());
4940 } else {
4941 pushl(as_Address(src));
4942 }
4943 }
4944
4945 void MacroAssembler::set_word_if_not_zero(Register dst) {
4946 xorl(dst, dst);
4947 set_byte_if_not_zero(dst);
4948 }
4949
4950 static void pass_arg0(MacroAssembler* masm, Register arg) {
4951 masm->push(arg);
4952 }
4953
4954 static void pass_arg1(MacroAssembler* masm, Register arg) {
4955 masm->push(arg);
4956 }
4957
4958 static void pass_arg2(MacroAssembler* masm, Register arg) {
4959 masm->push(arg);
4960 }
4961
4962 static void pass_arg3(MacroAssembler* masm, Register arg) {
4963 masm->push(arg);
4964 }
4965
4966 #ifndef PRODUCT
4967 extern "C" void findpc(intptr_t x);
4968 #endif
4969
4970 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
4971 // In order to get locks to work, we need to fake a in_VM state
4972 JavaThread* thread = JavaThread::current();
4973 JavaThreadState saved_state = thread->thread_state();
4974 thread->set_thread_state(_thread_in_vm);
4975 if (ShowMessageBoxOnError) {
4976 JavaThread* thread = JavaThread::current();
4977 JavaThreadState saved_state = thread->thread_state();
4978 thread->set_thread_state(_thread_in_vm);
4979 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
4980 ttyLocker ttyl;
4981 BytecodeCounter::print();
4982 }
4983 // To see where a verify_oop failed, get $ebx+40/X for this frame.
4984 // This is the value of eip which points to where verify_oop will return.
4985 if (os::message_box(msg, "Execution stopped, print registers?")) {
4986 ttyLocker ttyl;
4987 tty->print_cr("eip = 0x%08x", eip);
4988 #ifndef PRODUCT
4989 tty->cr();
4990 findpc(eip);
4991 tty->cr();
4992 #endif
4993 tty->print_cr("rax, = 0x%08x", rax);
4994 tty->print_cr("rbx, = 0x%08x", rbx);
4995 tty->print_cr("rcx = 0x%08x", rcx);
4996 tty->print_cr("rdx = 0x%08x", rdx);
4997 tty->print_cr("rdi = 0x%08x", rdi);
4998 tty->print_cr("rsi = 0x%08x", rsi);
4999 tty->print_cr("rbp, = 0x%08x", rbp);
5000 tty->print_cr("rsp = 0x%08x", rsp);
5001 BREAKPOINT;
5002 }
5003 } else {
5004 ttyLocker ttyl;
5005 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5006 assert(false, "DEBUG MESSAGE");
5007 }
5008 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5009 }
5010
5011 void MacroAssembler::stop(const char* msg) {
5012 ExternalAddress message((address)msg);
5013 // push address of message
5014 pushptr(message.addr());
5015 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5016 pusha(); // push registers
5017 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5018 hlt();
5019 }
5020
5021 void MacroAssembler::warn(const char* msg) {
5022 push_CPU_state();
5023
5024 ExternalAddress message((address) msg);
5025 // push address of message
5026 pushptr(message.addr());
5027
5028 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5029 addl(rsp, wordSize); // discard argument
5030 pop_CPU_state();
5031 }
5032
5033 #else // _LP64
5034
5035 // 64 bit versions
5036
5037 Address MacroAssembler::as_Address(AddressLiteral adr) {
5038 // amd64 always does this as a pc-rel
5039 // we can be absolute or disp based on the instruction type
5040 // jmp/call are displacements others are absolute
5041 assert(!adr.is_lval(), "must be rval");
5042 assert(reachable(adr), "must be");
5043 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5044
5045 }
5046
5047 Address MacroAssembler::as_Address(ArrayAddress adr) {
5048 AddressLiteral base = adr.base();
5049 lea(rscratch1, base);
5050 Address index = adr.index();
5051 assert(index._disp == 0, "must not have disp"); // maybe it can?
5052 Address array(rscratch1, index._index, index._scale, index._disp);
5053 return array;
5054 }
5055
5056 int MacroAssembler::biased_locking_enter(Register lock_reg,
5057 Register obj_reg,
5058 Register swap_reg,
5059 Register tmp_reg,
5060 bool swap_reg_contains_mark,
5061 Label& done,
5062 Label* slow_case,
5063 BiasedLockingCounters* counters) {
5064 assert(UseBiasedLocking, "why call this otherwise?");
5065 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5066 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5067 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5068 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5069 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5070 Address saved_mark_addr(lock_reg, 0);
5071
5072 if (PrintBiasedLockingStatistics && counters == NULL)
5073 counters = BiasedLocking::counters();
5074
5075 // Biased locking
5076 // See whether the lock is currently biased toward our thread and
5077 // whether the epoch is still valid
5078 // Note that the runtime guarantees sufficient alignment of JavaThread
5079 // pointers to allow age to be placed into low bits
5080 // First check to see whether biasing is even enabled for this object
5081 Label cas_label;
5082 int null_check_offset = -1;
5083 if (!swap_reg_contains_mark) {
5084 null_check_offset = offset();
5085 movq(swap_reg, mark_addr);
5086 }
5087 movq(tmp_reg, swap_reg);
5088 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5089 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5090 jcc(Assembler::notEqual, cas_label);
5091 // The bias pattern is present in the object's header. Need to check
5092 // whether the bias owner and the epoch are both still current.
5093 load_prototype_header(tmp_reg, obj_reg);
5094 orq(tmp_reg, r15_thread);
5095 xorq(tmp_reg, swap_reg);
5096 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5097 if (counters != NULL) {
5098 cond_inc32(Assembler::zero,
5099 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5100 }
5101 jcc(Assembler::equal, done);
5102
5103 Label try_revoke_bias;
5104 Label try_rebias;
5105
5106 // At this point we know that the header has the bias pattern and
5107 // that we are not the bias owner in the current epoch. We need to
5108 // figure out more details about the state of the header in order to
5109 // know what operations can be legally performed on the object's
5110 // header.
5111
5112 // If the low three bits in the xor result aren't clear, that means
5113 // the prototype header is no longer biased and we have to revoke
5114 // the bias on this object.
5115 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5116 jcc(Assembler::notZero, try_revoke_bias);
5117
5118 // Biasing is still enabled for this data type. See whether the
5119 // epoch of the current bias is still valid, meaning that the epoch
5120 // bits of the mark word are equal to the epoch bits of the
5121 // prototype header. (Note that the prototype header's epoch bits
5122 // only change at a safepoint.) If not, attempt to rebias the object
5123 // toward the current thread. Note that we must be absolutely sure
5124 // that the current epoch is invalid in order to do this because
5125 // otherwise the manipulations it performs on the mark word are
5126 // illegal.
5127 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5128 jcc(Assembler::notZero, try_rebias);
5129
5130 // The epoch of the current bias is still valid but we know nothing
5131 // about the owner; it might be set or it might be clear. Try to
5132 // acquire the bias of the object using an atomic operation. If this
5133 // fails we will go in to the runtime to revoke the object's bias.
5134 // Note that we first construct the presumed unbiased header so we
5135 // don't accidentally blow away another thread's valid bias.
5136 andq(swap_reg,
5137 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5138 movq(tmp_reg, swap_reg);
5139 orq(tmp_reg, r15_thread);
5140 if (os::is_MP()) {
5141 lock();
5142 }
5143 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5144 // If the biasing toward our thread failed, this means that
5145 // another thread succeeded in biasing it toward itself and we
5146 // need to revoke that bias. The revocation will occur in the
5147 // interpreter runtime in the slow case.
5148 if (counters != NULL) {
5149 cond_inc32(Assembler::zero,
5150 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5151 }
5152 if (slow_case != NULL) {
5153 jcc(Assembler::notZero, *slow_case);
5154 }
5155 jmp(done);
5156
5157 bind(try_rebias);
5158 // At this point we know the epoch has expired, meaning that the
5159 // current "bias owner", if any, is actually invalid. Under these
5160 // circumstances _only_, we are allowed to use the current header's
5161 // value as the comparison value when doing the cas to acquire the
5162 // bias in the current epoch. In other words, we allow transfer of
5163 // the bias from one thread to another directly in this situation.
5164 //
5165 // FIXME: due to a lack of registers we currently blow away the age
5166 // bits in this situation. Should attempt to preserve them.
5167 load_prototype_header(tmp_reg, obj_reg);
5168 orq(tmp_reg, r15_thread);
5169 if (os::is_MP()) {
5170 lock();
5171 }
5172 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5173 // If the biasing toward our thread failed, then another thread
5174 // succeeded in biasing it toward itself and we need to revoke that
5175 // bias. The revocation will occur in the runtime in the slow case.
5176 if (counters != NULL) {
5177 cond_inc32(Assembler::zero,
5178 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5179 }
5180 if (slow_case != NULL) {
5181 jcc(Assembler::notZero, *slow_case);
5182 }
5183 jmp(done);
5184
5185 bind(try_revoke_bias);
5186 // The prototype mark in the klass doesn't have the bias bit set any
5187 // more, indicating that objects of this data type are not supposed
5188 // to be biased any more. We are going to try to reset the mark of
5189 // this object to the prototype value and fall through to the
5190 // CAS-based locking scheme. Note that if our CAS fails, it means
5191 // that another thread raced us for the privilege of revoking the
5192 // bias of this particular object, so it's okay to continue in the
5193 // normal locking code.
5194 //
5195 // FIXME: due to a lack of registers we currently blow away the age
5196 // bits in this situation. Should attempt to preserve them.
5197 load_prototype_header(tmp_reg, obj_reg);
5198 if (os::is_MP()) {
5199 lock();
5200 }
5201 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5202 // Fall through to the normal CAS-based lock, because no matter what
5203 // the result of the above CAS, some thread must have succeeded in
5204 // removing the bias bit from the object's header.
5205 if (counters != NULL) {
5206 cond_inc32(Assembler::zero,
5207 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5208 }
5209
5210 bind(cas_label);
5211
5212 return null_check_offset;
5213 }
5214
5215 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5216 Label L, E;
5217
5218 #ifdef _WIN64
5219 // Windows always allocates space for it's register args
5220 assert(num_args <= 4, "only register arguments supported");
5221 subq(rsp, frame::arg_reg_save_area_bytes);
5222 #endif
5223
5224 // Align stack if necessary
5225 testl(rsp, 15);
5226 jcc(Assembler::zero, L);
5227
5228 subq(rsp, 8);
5229 {
5230 call(RuntimeAddress(entry_point));
5231 }
5232 addq(rsp, 8);
5233 jmp(E);
5234
5235 bind(L);
5236 {
5237 call(RuntimeAddress(entry_point));
5238 }
5239
5240 bind(E);
5241
5242 #ifdef _WIN64
5243 // restore stack pointer
5244 addq(rsp, frame::arg_reg_save_area_bytes);
5245 #endif
5246
5247 }
5248
5249 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5250 assert(!src2.is_lval(), "should use cmpptr");
5251
5252 if (reachable(src2)) {
5253 cmpq(src1, as_Address(src2));
5254 } else {
5255 lea(rscratch1, src2);
5256 Assembler::cmpq(src1, Address(rscratch1, 0));
5257 }
5258 }
5259
5260 int MacroAssembler::corrected_idivq(Register reg) {
5261 // Full implementation of Java ldiv and lrem; checks for special
5262 // case as described in JVM spec., p.243 & p.271. The function
5263 // returns the (pc) offset of the idivl instruction - may be needed
5264 // for implicit exceptions.
5265 //
5266 // normal case special case
5267 //
5268 // input : rax: dividend min_long
5269 // reg: divisor (may not be eax/edx) -1
5270 //
5271 // output: rax: quotient (= rax idiv reg) min_long
5272 // rdx: remainder (= rax irem reg) 0
5273 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5274 static const int64_t min_long = 0x8000000000000000;
5275 Label normal_case, special_case;
5276
5277 // check for special case
5278 cmp64(rax, ExternalAddress((address) &min_long));
5279 jcc(Assembler::notEqual, normal_case);
5280 xorl(rdx, rdx); // prepare rdx for possible special case (where
5281 // remainder = 0)
5282 cmpq(reg, -1);
5283 jcc(Assembler::equal, special_case);
5284
5285 // handle normal case
5286 bind(normal_case);
5287 cdqq();
5288 int idivq_offset = offset();
5289 idivq(reg);
5290
5291 // normal and special case exit
5292 bind(special_case);
5293
5294 return idivq_offset;
5295 }
5296
5297 void MacroAssembler::decrementq(Register reg, int value) {
5298 if (value == min_jint) { subq(reg, value); return; }
5299 if (value < 0) { incrementq(reg, -value); return; }
5300 if (value == 0) { ; return; }
5301 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5302 /* else */ { subq(reg, value) ; return; }
5303 }
5304
5305 void MacroAssembler::decrementq(Address dst, int value) {
5306 if (value == min_jint) { subq(dst, value); return; }
5307 if (value < 0) { incrementq(dst, -value); return; }
5308 if (value == 0) { ; return; }
5309 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5310 /* else */ { subq(dst, value) ; return; }
5311 }
5312
5313 void MacroAssembler::fat_nop() {
5314 // A 5 byte nop that is safe for patching (see patch_verified_entry)
5315 // Recommened sequence from 'Software Optimization Guide for the AMD
5316 // Hammer Processor'
5317 emit_byte(0x66);
5318 emit_byte(0x66);
5319 emit_byte(0x90);
5320 emit_byte(0x66);
5321 emit_byte(0x90);
5322 }
5323
5324 void MacroAssembler::incrementq(Register reg, int value) {
5325 if (value == min_jint) { addq(reg, value); return; }
5326 if (value < 0) { decrementq(reg, -value); return; }
5327 if (value == 0) { ; return; }
5328 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5329 /* else */ { addq(reg, value) ; return; }
5330 }
5331
5332 void MacroAssembler::incrementq(Address dst, int value) {
5333 if (value == min_jint) { addq(dst, value); return; }
5334 if (value < 0) { decrementq(dst, -value); return; }
5335 if (value == 0) { ; return; }
5336 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5337 /* else */ { addq(dst, value) ; return; }
5338 }
5339
5340 // 32bit can do a case table jump in one instruction but we no longer allow the base
5341 // to be installed in the Address class
5342 void MacroAssembler::jump(ArrayAddress entry) {
5343 lea(rscratch1, entry.base());
5344 Address dispatch = entry.index();
5345 assert(dispatch._base == noreg, "must be");
5346 dispatch._base = rscratch1;
5347 jmp(dispatch);
5348 }
5349
5350 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5351 ShouldNotReachHere(); // 64bit doesn't use two regs
5352 cmpq(x_lo, y_lo);
5353 }
5354
5355 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5356 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5357 }
5358
5359 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5360 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5361 movptr(dst, rscratch1);
5362 }
5363
5364 void MacroAssembler::leave() {
5365 // %%% is this really better? Why not on 32bit too?
5366 emit_byte(0xC9); // LEAVE
5367 }
5368
5369 void MacroAssembler::lneg(Register hi, Register lo) {
5370 ShouldNotReachHere(); // 64bit doesn't use two regs
5371 negq(lo);
5372 }
5373
5374 void MacroAssembler::movoop(Register dst, jobject obj) {
5375 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5376 }
5377
5378 void MacroAssembler::movoop(Address dst, jobject obj) {
5379 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5380 movq(dst, rscratch1);
5381 }
5382
5383 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5384 if (src.is_lval()) {
5385 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5386 } else {
5387 if (reachable(src)) {
5388 movq(dst, as_Address(src));
5389 } else {
5390 lea(rscratch1, src);
5391 movq(dst, Address(rscratch1,0));
5392 }
5393 }
5394 }
5395
5396 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5397 movq(as_Address(dst), src);
5398 }
5399
5400 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5401 movq(dst, as_Address(src));
5402 }
5403
5404 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5405 void MacroAssembler::movptr(Address dst, intptr_t src) {
5406 mov64(rscratch1, src);
5407 movq(dst, rscratch1);
5408 }
5409
5410 // These are mostly for initializing NULL
5411 void MacroAssembler::movptr(Address dst, int32_t src) {
5412 movslq(dst, src);
5413 }
5414
5415 void MacroAssembler::movptr(Register dst, int32_t src) {
5416 mov64(dst, (intptr_t)src);
5417 }
5418
5419 void MacroAssembler::pushoop(jobject obj) {
5420 movoop(rscratch1, obj);
5421 push(rscratch1);
5422 }
5423
5424 void MacroAssembler::pushptr(AddressLiteral src) {
5425 lea(rscratch1, src);
5426 if (src.is_lval()) {
5427 push(rscratch1);
5428 } else {
5429 pushq(Address(rscratch1, 0));
5430 }
5431 }
5432
5433 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5434 bool clear_pc) {
5435 // we must set sp to zero to clear frame
5436 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
5437 // must clear fp, so that compiled frames are not confused; it is
5438 // possible that we need it only for debugging
5439 if (clear_fp) {
5440 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
5441 }
5442
5443 if (clear_pc) {
5444 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
5445 }
5446 }
5447
5448 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
5449 Register last_java_fp,
5450 address last_java_pc) {
5451 // determine last_java_sp register
5452 if (!last_java_sp->is_valid()) {
5453 last_java_sp = rsp;
5454 }
5455
5456 // last_java_fp is optional
5457 if (last_java_fp->is_valid()) {
5458 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
5459 last_java_fp);
5460 }
5461
5462 // last_java_pc is optional
5463 if (last_java_pc != NULL) {
5464 Address java_pc(r15_thread,
5465 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
5466 lea(rscratch1, InternalAddress(last_java_pc));
5467 movptr(java_pc, rscratch1);
5468 }
5469
5470 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
5471 }
5472
5473 static void pass_arg0(MacroAssembler* masm, Register arg) {
5474 if (c_rarg0 != arg ) {
5475 masm->mov(c_rarg0, arg);
5476 }
5477 }
5478
5479 static void pass_arg1(MacroAssembler* masm, Register arg) {
5480 if (c_rarg1 != arg ) {
5481 masm->mov(c_rarg1, arg);
5482 }
5483 }
5484
5485 static void pass_arg2(MacroAssembler* masm, Register arg) {
5486 if (c_rarg2 != arg ) {
5487 masm->mov(c_rarg2, arg);
5488 }
5489 }
5490
5491 static void pass_arg3(MacroAssembler* masm, Register arg) {
5492 if (c_rarg3 != arg ) {
5493 masm->mov(c_rarg3, arg);
5494 }
5495 }
5496
5497 void MacroAssembler::stop(const char* msg) {
5498 address rip = pc();
5499 pusha(); // get regs on stack
5500 lea(c_rarg0, ExternalAddress((address) msg));
5501 lea(c_rarg1, InternalAddress(rip));
5502 movq(c_rarg2, rsp); // pass pointer to regs array
5503 andq(rsp, -16); // align stack as required by ABI
5504 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
5505 hlt();
5506 }
5507
5508 void MacroAssembler::warn(const char* msg) {
5509 push(r12);
5510 movq(r12, rsp);
5511 andq(rsp, -16); // align stack as required by push_CPU_state and call
5512
5513 push_CPU_state(); // keeps alignment at 16 bytes
5514 lea(c_rarg0, ExternalAddress((address) msg));
5515 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
5516 pop_CPU_state();
5517
5518 movq(rsp, r12);
5519 pop(r12);
5520 }
5521
5522 #ifndef PRODUCT
5523 extern "C" void findpc(intptr_t x);
5524 #endif
5525
5526 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
5527 // In order to get locks to work, we need to fake a in_VM state
5528 if (ShowMessageBoxOnError ) {
5529 JavaThread* thread = JavaThread::current();
5530 JavaThreadState saved_state = thread->thread_state();
5531 thread->set_thread_state(_thread_in_vm);
5532 #ifndef PRODUCT
5533 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5534 ttyLocker ttyl;
5535 BytecodeCounter::print();
5536 }
5537 #endif
5538 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5539 // XXX correct this offset for amd64
5540 // This is the value of eip which points to where verify_oop will return.
5541 if (os::message_box(msg, "Execution stopped, print registers?")) {
5542 ttyLocker ttyl;
5543 tty->print_cr("rip = 0x%016lx", pc);
5544 #ifndef PRODUCT
5545 tty->cr();
5546 findpc(pc);
5547 tty->cr();
5548 #endif
5549 tty->print_cr("rax = 0x%016lx", regs[15]);
5550 tty->print_cr("rbx = 0x%016lx", regs[12]);
5551 tty->print_cr("rcx = 0x%016lx", regs[14]);
5552 tty->print_cr("rdx = 0x%016lx", regs[13]);
5553 tty->print_cr("rdi = 0x%016lx", regs[8]);
5554 tty->print_cr("rsi = 0x%016lx", regs[9]);
5555 tty->print_cr("rbp = 0x%016lx", regs[10]);
5556 tty->print_cr("rsp = 0x%016lx", regs[11]);
5557 tty->print_cr("r8 = 0x%016lx", regs[7]);
5558 tty->print_cr("r9 = 0x%016lx", regs[6]);
5559 tty->print_cr("r10 = 0x%016lx", regs[5]);
5560 tty->print_cr("r11 = 0x%016lx", regs[4]);
5561 tty->print_cr("r12 = 0x%016lx", regs[3]);
5562 tty->print_cr("r13 = 0x%016lx", regs[2]);
5563 tty->print_cr("r14 = 0x%016lx", regs[1]);
5564 tty->print_cr("r15 = 0x%016lx", regs[0]);
5565 BREAKPOINT;
5566 }
5567 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5568 } else {
5569 ttyLocker ttyl;
5570 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
5571 msg);
5572 }
5573 }
5574
5575 #endif // _LP64
5576
5577 // Now versions that are common to 32/64 bit
5578
5579 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5580 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5581 }
5582
5583 void MacroAssembler::addptr(Register dst, Register src) {
5584 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5585 }
5586
5587 void MacroAssembler::addptr(Address dst, Register src) {
5588 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5589 }
5590
5591 void MacroAssembler::align(int modulus) {
5592 if (offset() % modulus != 0) {
5593 nop(modulus - (offset() % modulus));
5594 }
5595 }
5596
5597 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5598 if (reachable(src)) {
5599 andpd(dst, as_Address(src));
5600 } else {
5601 lea(rscratch1, src);
5602 andpd(dst, Address(rscratch1, 0));
5603 }
5604 }
5605
5606 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5607 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5608 }
5609
5610 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5611 pushf();
5612 if (os::is_MP())
5613 lock();
5614 incrementl(counter_addr);
5615 popf();
5616 }
5617
5618 // Writes to stack successive pages until offset reached to check for
5619 // stack overflow + shadow pages. This clobbers tmp.
5620 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5621 movptr(tmp, rsp);
5622 // Bang stack for total size given plus shadow page size.
5623 // Bang one page at a time because large size can bang beyond yellow and
5624 // red zones.
5625 Label loop;
5626 bind(loop);
5627 movl(Address(tmp, (-os::vm_page_size())), size );
5628 subptr(tmp, os::vm_page_size());
5629 subl(size, os::vm_page_size());
5630 jcc(Assembler::greater, loop);
5631
5632 // Bang down shadow pages too.
5633 // The -1 because we already subtracted 1 page.
5634 for (int i = 0; i< StackShadowPages-1; i++) {
5635 // this could be any sized move but this is can be a debugging crumb
5636 // so the bigger the better.
5637 movptr(Address(tmp, (-i*os::vm_page_size())), size );
5638 }
5639 }
5640
5641 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
5642 assert(UseBiasedLocking, "why call this otherwise?");
5643
5644 // Check for biased locking unlock case, which is a no-op
5645 // Note: we do not have to check the thread ID for two reasons.
5646 // First, the interpreter checks for IllegalMonitorStateException at
5647 // a higher level. Second, if the bias was revoked while we held the
5648 // lock, the object could not be rebiased toward another thread, so
5649 // the bias bit would be clear.
5650 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
5651 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
5652 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
5653 jcc(Assembler::equal, done);
5654 }
5655
5656 void MacroAssembler::c2bool(Register x) {
5657 // implements x == 0 ? 0 : 1
5658 // note: must only look at least-significant byte of x
5659 // since C-style booleans are stored in one byte
5660 // only! (was bug)
5661 andl(x, 0xFF);
5662 setb(Assembler::notZero, x);
5663 }
5664
5665 // Wouldn't need if AddressLiteral version had new name
5666 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
5667 Assembler::call(L, rtype);
5668 }
5669
5670 void MacroAssembler::call(Register entry) {
5671 Assembler::call(entry);
5672 }
5673
5674 void MacroAssembler::call(AddressLiteral entry) {
5675 if (reachable(entry)) {
5676 Assembler::call_literal(entry.target(), entry.rspec());
5677 } else {
5678 lea(rscratch1, entry);
5679 Assembler::call(rscratch1);
5680 }
5681 }
5682
5683 // Implementation of call_VM versions
5684
5685 void MacroAssembler::call_VM(Register oop_result,
5686 address entry_point,
5687 bool check_exceptions) {
5688 Label C, E;
5689 call(C, relocInfo::none);
5690 jmp(E);
5691
5692 bind(C);
5693 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
5694 ret(0);
5695
5696 bind(E);
5697 }
5698
5699 void MacroAssembler::call_VM(Register oop_result,
5700 address entry_point,
5701 Register arg_1,
5702 bool check_exceptions) {
5703 Label C, E;
5704 call(C, relocInfo::none);
5705 jmp(E);
5706
5707 bind(C);
5708 pass_arg1(this, arg_1);
5709 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
5710 ret(0);
5711
5712 bind(E);
5713 }
5714
5715 void MacroAssembler::call_VM(Register oop_result,
5716 address entry_point,
5717 Register arg_1,
5718 Register arg_2,
5719 bool check_exceptions) {
5720 Label C, E;
5721 call(C, relocInfo::none);
5722 jmp(E);
5723
5724 bind(C);
5725
5726 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5727
5728 pass_arg2(this, arg_2);
5729 pass_arg1(this, arg_1);
5730 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
5731 ret(0);
5732
5733 bind(E);
5734 }
5735
5736 void MacroAssembler::call_VM(Register oop_result,
5737 address entry_point,
5738 Register arg_1,
5739 Register arg_2,
5740 Register arg_3,
5741 bool check_exceptions) {
5742 Label C, E;
5743 call(C, relocInfo::none);
5744 jmp(E);
5745
5746 bind(C);
5747
5748 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5749 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5750 pass_arg3(this, arg_3);
5751
5752 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5753 pass_arg2(this, arg_2);
5754
5755 pass_arg1(this, arg_1);
5756 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
5757 ret(0);
5758
5759 bind(E);
5760 }
5761
5762 void MacroAssembler::call_VM(Register oop_result,
5763 Register last_java_sp,
5764 address entry_point,
5765 int number_of_arguments,
5766 bool check_exceptions) {
5767 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
5768 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
5769 }
5770
5771 void MacroAssembler::call_VM(Register oop_result,
5772 Register last_java_sp,
5773 address entry_point,
5774 Register arg_1,
5775 bool check_exceptions) {
5776 pass_arg1(this, arg_1);
5777 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
5778 }
5779
5780 void MacroAssembler::call_VM(Register oop_result,
5781 Register last_java_sp,
5782 address entry_point,
5783 Register arg_1,
5784 Register arg_2,
5785 bool check_exceptions) {
5786
5787 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5788 pass_arg2(this, arg_2);
5789 pass_arg1(this, arg_1);
5790 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
5791 }
5792
5793 void MacroAssembler::call_VM(Register oop_result,
5794 Register last_java_sp,
5795 address entry_point,
5796 Register arg_1,
5797 Register arg_2,
5798 Register arg_3,
5799 bool check_exceptions) {
5800 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5801 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5802 pass_arg3(this, arg_3);
5803 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5804 pass_arg2(this, arg_2);
5805 pass_arg1(this, arg_1);
5806 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
5807 }
5808
5809 void MacroAssembler::call_VM_base(Register oop_result,
5810 Register java_thread,
5811 Register last_java_sp,
5812 address entry_point,
5813 int number_of_arguments,
5814 bool check_exceptions) {
5815 // determine java_thread register
5816 if (!java_thread->is_valid()) {
5817 #ifdef _LP64
5818 java_thread = r15_thread;
5819 #else
5820 java_thread = rdi;
5821 get_thread(java_thread);
5822 #endif // LP64
5823 }
5824 // determine last_java_sp register
5825 if (!last_java_sp->is_valid()) {
5826 last_java_sp = rsp;
5827 }
5828 // debugging support
5829 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
5830 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
5831 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
5832 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
5833
5834 // push java thread (becomes first argument of C function)
5835
5836 NOT_LP64(push(java_thread); number_of_arguments++);
5837 LP64_ONLY(mov(c_rarg0, r15_thread));
5838
5839 // set last Java frame before call
5840 assert(last_java_sp != rbp, "can't use ebp/rbp");
5841
5842 // Only interpreter should have to set fp
5843 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
5844
5845 // do the call, remove parameters
5846 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
5847
5848 // restore the thread (cannot use the pushed argument since arguments
5849 // may be overwritten by C code generated by an optimizing compiler);
5850 // however can use the register value directly if it is callee saved.
5851 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
5852 // rdi & rsi (also r15) are callee saved -> nothing to do
5853 #ifdef ASSERT
5854 guarantee(java_thread != rax, "change this code");
5855 push(rax);
5856 { Label L;
5857 get_thread(rax);
5858 cmpptr(java_thread, rax);
5859 jcc(Assembler::equal, L);
5860 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
5861 bind(L);
5862 }
5863 pop(rax);
5864 #endif
5865 } else {
5866 get_thread(java_thread);
5867 }
5868 // reset last Java frame
5869 // Only interpreter should have to clear fp
5870 reset_last_Java_frame(java_thread, true, false);
5871
5872 #ifndef CC_INTERP
5873 // C++ interp handles this in the interpreter
5874 check_and_handle_popframe(java_thread);
5875 check_and_handle_earlyret(java_thread);
5876 #endif /* CC_INTERP */
5877
5878 if (check_exceptions) {
5879 // check for pending exceptions (java_thread is set upon return)
5880 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
5881 #ifndef _LP64
5882 jump_cc(Assembler::notEqual,
5883 RuntimeAddress(StubRoutines::forward_exception_entry()));
5884 #else
5885 // This used to conditionally jump to forward_exception however it is
5886 // possible if we relocate that the branch will not reach. So we must jump
5887 // around so we can always reach
5888
5889 Label ok;
5890 jcc(Assembler::equal, ok);
5891 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
5892 bind(ok);
5893 #endif // LP64
5894 }
5895
5896 // get oop result if there is one and reset the value in the thread
5897 if (oop_result->is_valid()) {
5898 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
5899 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
5900 verify_oop(oop_result, "broken oop in call_VM_base");
5901 }
5902 }
5903
5904 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
5905
5906 // Calculate the value for last_Java_sp
5907 // somewhat subtle. call_VM does an intermediate call
5908 // which places a return address on the stack just under the
5909 // stack pointer as the user finsihed with it. This allows
5910 // use to retrieve last_Java_pc from last_Java_sp[-1].
5911 // On 32bit we then have to push additional args on the stack to accomplish
5912 // the actual requested call. On 64bit call_VM only can use register args
5913 // so the only extra space is the return address that call_VM created.
5914 // This hopefully explains the calculations here.
5915
5916 #ifdef _LP64
5917 // We've pushed one address, correct last_Java_sp
5918 lea(rax, Address(rsp, wordSize));
5919 #else
5920 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
5921 #endif // LP64
5922
5923 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
5924
5925 }
5926
5927 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
5928 call_VM_leaf_base(entry_point, number_of_arguments);
5929 }
5930
5931 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
5932 pass_arg0(this, arg_0);
5933 call_VM_leaf(entry_point, 1);
5934 }
5935
5936 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
5937
5938 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5939 pass_arg1(this, arg_1);
5940 pass_arg0(this, arg_0);
5941 call_VM_leaf(entry_point, 2);
5942 }
5943
5944 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
5945 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
5946 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5947 pass_arg2(this, arg_2);
5948 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5949 pass_arg1(this, arg_1);
5950 pass_arg0(this, arg_0);
5951 call_VM_leaf(entry_point, 3);
5952 }
5953
5954 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
5955 }
5956
5957 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
5958 }
5959
5960 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
5961 if (reachable(src1)) {
5962 cmpl(as_Address(src1), imm);
5963 } else {
5964 lea(rscratch1, src1);
5965 cmpl(Address(rscratch1, 0), imm);
5966 }
5967 }
5968
5969 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
5970 assert(!src2.is_lval(), "use cmpptr");
5971 if (reachable(src2)) {
5972 cmpl(src1, as_Address(src2));
5973 } else {
5974 lea(rscratch1, src2);
5975 cmpl(src1, Address(rscratch1, 0));
5976 }
5977 }
5978
5979 void MacroAssembler::cmp32(Register src1, int32_t imm) {
5980 Assembler::cmpl(src1, imm);
5981 }
5982
5983 void MacroAssembler::cmp32(Register src1, Address src2) {
5984 Assembler::cmpl(src1, src2);
5985 }
5986
5987 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
5988 ucomisd(opr1, opr2);
5989
5990 Label L;
5991 if (unordered_is_less) {
5992 movl(dst, -1);
5993 jcc(Assembler::parity, L);
5994 jcc(Assembler::below , L);
5995 movl(dst, 0);
5996 jcc(Assembler::equal , L);
5997 increment(dst);
5998 } else { // unordered is greater
5999 movl(dst, 1);
6000 jcc(Assembler::parity, L);
6001 jcc(Assembler::above , L);
6002 movl(dst, 0);
6003 jcc(Assembler::equal , L);
6004 decrementl(dst);
6005 }
6006 bind(L);
6007 }
6008
6009 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6010 ucomiss(opr1, opr2);
6011
6012 Label L;
6013 if (unordered_is_less) {
6014 movl(dst, -1);
6015 jcc(Assembler::parity, L);
6016 jcc(Assembler::below , L);
6017 movl(dst, 0);
6018 jcc(Assembler::equal , L);
6019 increment(dst);
6020 } else { // unordered is greater
6021 movl(dst, 1);
6022 jcc(Assembler::parity, L);
6023 jcc(Assembler::above , L);
6024 movl(dst, 0);
6025 jcc(Assembler::equal , L);
6026 decrementl(dst);
6027 }
6028 bind(L);
6029 }
6030
6031
6032 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6033 if (reachable(src1)) {
6034 cmpb(as_Address(src1), imm);
6035 } else {
6036 lea(rscratch1, src1);
6037 cmpb(Address(rscratch1, 0), imm);
6038 }
6039 }
6040
6041 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6042 #ifdef _LP64
6043 if (src2.is_lval()) {
6044 movptr(rscratch1, src2);
6045 Assembler::cmpq(src1, rscratch1);
6046 } else if (reachable(src2)) {
6047 cmpq(src1, as_Address(src2));
6048 } else {
6049 lea(rscratch1, src2);
6050 Assembler::cmpq(src1, Address(rscratch1, 0));
6051 }
6052 #else
6053 if (src2.is_lval()) {
6054 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6055 } else {
6056 cmpl(src1, as_Address(src2));
6057 }
6058 #endif // _LP64
6059 }
6060
6061 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6062 assert(src2.is_lval(), "not a mem-mem compare");
6063 #ifdef _LP64
6064 // moves src2's literal address
6065 movptr(rscratch1, src2);
6066 Assembler::cmpq(src1, rscratch1);
6067 #else
6068 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6069 #endif // _LP64
6070 }
6071
6072 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6073 if (reachable(adr)) {
6074 if (os::is_MP())
6075 lock();
6076 cmpxchgptr(reg, as_Address(adr));
6077 } else {
6078 lea(rscratch1, adr);
6079 if (os::is_MP())
6080 lock();
6081 cmpxchgptr(reg, Address(rscratch1, 0));
6082 }
6083 }
6084
6085 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6086 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6087 }
6088
6089 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6090 if (reachable(src)) {
6091 comisd(dst, as_Address(src));
6092 } else {
6093 lea(rscratch1, src);
6094 comisd(dst, Address(rscratch1, 0));
6095 }
6096 }
6097
6098 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6099 if (reachable(src)) {
6100 comiss(dst, as_Address(src));
6101 } else {
6102 lea(rscratch1, src);
6103 comiss(dst, Address(rscratch1, 0));
6104 }
6105 }
6106
6107
6108 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6109 Condition negated_cond = negate_condition(cond);
6110 Label L;
6111 jcc(negated_cond, L);
6112 atomic_incl(counter_addr);
6113 bind(L);
6114 }
6115
6116 int MacroAssembler::corrected_idivl(Register reg) {
6117 // Full implementation of Java idiv and irem; checks for
6118 // special case as described in JVM spec., p.243 & p.271.
6119 // The function returns the (pc) offset of the idivl
6120 // instruction - may be needed for implicit exceptions.
6121 //
6122 // normal case special case
6123 //
6124 // input : rax,: dividend min_int
6125 // reg: divisor (may not be rax,/rdx) -1
6126 //
6127 // output: rax,: quotient (= rax, idiv reg) min_int
6128 // rdx: remainder (= rax, irem reg) 0
6129 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6130 const int min_int = 0x80000000;
6131 Label normal_case, special_case;
6132
6133 // check for special case
6134 cmpl(rax, min_int);
6135 jcc(Assembler::notEqual, normal_case);
6136 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6137 cmpl(reg, -1);
6138 jcc(Assembler::equal, special_case);
6139
6140 // handle normal case
6141 bind(normal_case);
6142 cdql();
6143 int idivl_offset = offset();
6144 idivl(reg);
6145
6146 // normal and special case exit
6147 bind(special_case);
6148
6149 return idivl_offset;
6150 }
6151
6152
6153
6154 void MacroAssembler::decrementl(Register reg, int value) {
6155 if (value == min_jint) {subl(reg, value) ; return; }
6156 if (value < 0) { incrementl(reg, -value); return; }
6157 if (value == 0) { ; return; }
6158 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6159 /* else */ { subl(reg, value) ; return; }
6160 }
6161
6162 void MacroAssembler::decrementl(Address dst, int value) {
6163 if (value == min_jint) {subl(dst, value) ; return; }
6164 if (value < 0) { incrementl(dst, -value); return; }
6165 if (value == 0) { ; return; }
6166 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6167 /* else */ { subl(dst, value) ; return; }
6168 }
6169
6170 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6171 assert (shift_value > 0, "illegal shift value");
6172 Label _is_positive;
6173 testl (reg, reg);
6174 jcc (Assembler::positive, _is_positive);
6175 int offset = (1 << shift_value) - 1 ;
6176
6177 if (offset == 1) {
6178 incrementl(reg);
6179 } else {
6180 addl(reg, offset);
6181 }
6182
6183 bind (_is_positive);
6184 sarl(reg, shift_value);
6185 }
6186
6187 // !defined(COMPILER2) is because of stupid core builds
6188 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6189 void MacroAssembler::empty_FPU_stack() {
6190 if (VM_Version::supports_mmx()) {
6191 emms();
6192 } else {
6193 for (int i = 8; i-- > 0; ) ffree(i);
6194 }
6195 }
6196 #endif // !LP64 || C1 || !C2
6197
6198
6199 // Defines obj, preserves var_size_in_bytes
6200 void MacroAssembler::eden_allocate(Register obj,
6201 Register var_size_in_bytes,
6202 int con_size_in_bytes,
6203 Register t1,
6204 Label& slow_case) {
6205 assert(obj == rax, "obj must be in rax, for cmpxchg");
6206 assert_different_registers(obj, var_size_in_bytes, t1);
6207 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6208 jmp(slow_case);
6209 } else {
6210 Register end = t1;
6211 Label retry;
6212 bind(retry);
6213 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6214 movptr(obj, heap_top);
6215 if (var_size_in_bytes == noreg) {
6216 lea(end, Address(obj, con_size_in_bytes));
6217 } else {
6218 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6219 }
6220 // if end < obj then we wrapped around => object too long => slow case
6221 cmpptr(end, obj);
6222 jcc(Assembler::below, slow_case);
6223 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6224 jcc(Assembler::above, slow_case);
6225 // Compare obj with the top addr, and if still equal, store the new top addr in
6226 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6227 // it otherwise. Use lock prefix for atomicity on MPs.
6228 locked_cmpxchgptr(end, heap_top);
6229 jcc(Assembler::notEqual, retry);
6230 }
6231 }
6232
6233 void MacroAssembler::enter() {
6234 push(rbp);
6235 mov(rbp, rsp);
6236 }
6237
6238 void MacroAssembler::fcmp(Register tmp) {
6239 fcmp(tmp, 1, true, true);
6240 }
6241
6242 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
6243 assert(!pop_right || pop_left, "usage error");
6244 if (VM_Version::supports_cmov()) {
6245 assert(tmp == noreg, "unneeded temp");
6246 if (pop_left) {
6247 fucomip(index);
6248 } else {
6249 fucomi(index);
6250 }
6251 if (pop_right) {
6252 fpop();
6253 }
6254 } else {
6255 assert(tmp != noreg, "need temp");
6256 if (pop_left) {
6257 if (pop_right) {
6258 fcompp();
6259 } else {
6260 fcomp(index);
6261 }
6262 } else {
6263 fcom(index);
6264 }
6265 // convert FPU condition into eflags condition via rax,
6266 save_rax(tmp);
6267 fwait(); fnstsw_ax();
6268 sahf();
6269 restore_rax(tmp);
6270 }
6271 // condition codes set as follows:
6272 //
6273 // CF (corresponds to C0) if x < y
6274 // PF (corresponds to C2) if unordered
6275 // ZF (corresponds to C3) if x = y
6276 }
6277
6278 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
6279 fcmp2int(dst, unordered_is_less, 1, true, true);
6280 }
6281
6282 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
6283 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
6284 Label L;
6285 if (unordered_is_less) {
6286 movl(dst, -1);
6287 jcc(Assembler::parity, L);
6288 jcc(Assembler::below , L);
6289 movl(dst, 0);
6290 jcc(Assembler::equal , L);
6291 increment(dst);
6292 } else { // unordered is greater
6293 movl(dst, 1);
6294 jcc(Assembler::parity, L);
6295 jcc(Assembler::above , L);
6296 movl(dst, 0);
6297 jcc(Assembler::equal , L);
6298 decrementl(dst);
6299 }
6300 bind(L);
6301 }
6302
6303 void MacroAssembler::fld_d(AddressLiteral src) {
6304 fld_d(as_Address(src));
6305 }
6306
6307 void MacroAssembler::fld_s(AddressLiteral src) {
6308 fld_s(as_Address(src));
6309 }
6310
6311 void MacroAssembler::fld_x(AddressLiteral src) {
6312 Assembler::fld_x(as_Address(src));
6313 }
6314
6315 void MacroAssembler::fldcw(AddressLiteral src) {
6316 Assembler::fldcw(as_Address(src));
6317 }
6318
6319 void MacroAssembler::fpop() {
6320 ffree();
6321 fincstp();
6322 }
6323
6324 void MacroAssembler::fremr(Register tmp) {
6325 save_rax(tmp);
6326 { Label L;
6327 bind(L);
6328 fprem();
6329 fwait(); fnstsw_ax();
6330 #ifdef _LP64
6331 testl(rax, 0x400);
6332 jcc(Assembler::notEqual, L);
6333 #else
6334 sahf();
6335 jcc(Assembler::parity, L);
6336 #endif // _LP64
6337 }
6338 restore_rax(tmp);
6339 // Result is in ST0.
6340 // Note: fxch & fpop to get rid of ST1
6341 // (otherwise FPU stack could overflow eventually)
6342 fxch(1);
6343 fpop();
6344 }
6345
6346
6347 void MacroAssembler::incrementl(AddressLiteral dst) {
6348 if (reachable(dst)) {
6349 incrementl(as_Address(dst));
6350 } else {
6351 lea(rscratch1, dst);
6352 incrementl(Address(rscratch1, 0));
6353 }
6354 }
6355
6356 void MacroAssembler::incrementl(ArrayAddress dst) {
6357 incrementl(as_Address(dst));
6358 }
6359
6360 void MacroAssembler::incrementl(Register reg, int value) {
6361 if (value == min_jint) {addl(reg, value) ; return; }
6362 if (value < 0) { decrementl(reg, -value); return; }
6363 if (value == 0) { ; return; }
6364 if (value == 1 && UseIncDec) { incl(reg) ; return; }
6365 /* else */ { addl(reg, value) ; return; }
6366 }
6367
6368 void MacroAssembler::incrementl(Address dst, int value) {
6369 if (value == min_jint) {addl(dst, value) ; return; }
6370 if (value < 0) { decrementl(dst, -value); return; }
6371 if (value == 0) { ; return; }
6372 if (value == 1 && UseIncDec) { incl(dst) ; return; }
6373 /* else */ { addl(dst, value) ; return; }
6374 }
6375
6376 void MacroAssembler::jump(AddressLiteral dst) {
6377 if (reachable(dst)) {
6378 jmp_literal(dst.target(), dst.rspec());
6379 } else {
6380 lea(rscratch1, dst);
6381 jmp(rscratch1);
6382 }
6383 }
6384
6385 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
6386 if (reachable(dst)) {
6387 InstructionMark im(this);
6388 relocate(dst.reloc());
6389 const int short_size = 2;
6390 const int long_size = 6;
6391 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
6392 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
6393 // 0111 tttn #8-bit disp
6394 emit_byte(0x70 | cc);
6395 emit_byte((offs - short_size) & 0xFF);
6396 } else {
6397 // 0000 1111 1000 tttn #32-bit disp
6398 emit_byte(0x0F);
6399 emit_byte(0x80 | cc);
6400 emit_long(offs - long_size);
6401 }
6402 } else {
6403 #ifdef ASSERT
6404 warning("reversing conditional branch");
6405 #endif /* ASSERT */
6406 Label skip;
6407 jccb(reverse[cc], skip);
6408 lea(rscratch1, dst);
6409 Assembler::jmp(rscratch1);
6410 bind(skip);
6411 }
6412 }
6413
6414 void MacroAssembler::ldmxcsr(AddressLiteral src) {
6415 if (reachable(src)) {
6416 Assembler::ldmxcsr(as_Address(src));
6417 } else {
6418 lea(rscratch1, src);
6419 Assembler::ldmxcsr(Address(rscratch1, 0));
6420 }
6421 }
6422
6423 int MacroAssembler::load_signed_byte(Register dst, Address src) {
6424 int off;
6425 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6426 off = offset();
6427 movsbl(dst, src); // movsxb
6428 } else {
6429 off = load_unsigned_byte(dst, src);
6430 shll(dst, 24);
6431 sarl(dst, 24);
6432 }
6433 return off;
6434 }
6435
6436 // Note: load_signed_short used to be called load_signed_word.
6437 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
6438 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
6439 // The term "word" in HotSpot means a 32- or 64-bit machine word.
6440 int MacroAssembler::load_signed_short(Register dst, Address src) {
6441 int off;
6442 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6443 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
6444 // version but this is what 64bit has always done. This seems to imply
6445 // that users are only using 32bits worth.
6446 off = offset();
6447 movswl(dst, src); // movsxw
6448 } else {
6449 off = load_unsigned_short(dst, src);
6450 shll(dst, 16);
6451 sarl(dst, 16);
6452 }
6453 return off;
6454 }
6455
6456 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
6457 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6458 // and "3.9 Partial Register Penalties", p. 22).
6459 int off;
6460 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
6461 off = offset();
6462 movzbl(dst, src); // movzxb
6463 } else {
6464 xorl(dst, dst);
6465 off = offset();
6466 movb(dst, src);
6467 }
6468 return off;
6469 }
6470
6471 // Note: load_unsigned_short used to be called load_unsigned_word.
6472 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
6473 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6474 // and "3.9 Partial Register Penalties", p. 22).
6475 int off;
6476 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
6477 off = offset();
6478 movzwl(dst, src); // movzxw
6479 } else {
6480 xorl(dst, dst);
6481 off = offset();
6482 movw(dst, src);
6483 }
6484 return off;
6485 }
6486
6487 void MacroAssembler::load_sized_value(Register dst, Address src,
6488 int size_in_bytes, bool is_signed) {
6489 switch (size_in_bytes ^ (is_signed ? -1 : 0)) {
6490 #ifndef _LP64
6491 // For case 8, caller is responsible for manually loading
6492 // the second word into another register.
6493 case ~8: // fall through:
6494 case 8: movl( dst, src ); break;
6495 #else
6496 case ~8: // fall through:
6497 case 8: movq( dst, src ); break;
6498 #endif
6499 case ~4: // fall through:
6500 case 4: movl( dst, src ); break;
6501 case ~2: load_signed_short( dst, src ); break;
6502 case 2: load_unsigned_short( dst, src ); break;
6503 case ~1: load_signed_byte( dst, src ); break;
6504 case 1: load_unsigned_byte( dst, src ); break;
6505 default: ShouldNotReachHere();
6506 }
6507 }
6508
6509 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
6510 if (reachable(dst)) {
6511 movl(as_Address(dst), src);
6512 } else {
6513 lea(rscratch1, dst);
6514 movl(Address(rscratch1, 0), src);
6515 }
6516 }
6517
6518 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
6519 if (reachable(src)) {
6520 movl(dst, as_Address(src));
6521 } else {
6522 lea(rscratch1, src);
6523 movl(dst, Address(rscratch1, 0));
6524 }
6525 }
6526
6527 // C++ bool manipulation
6528
6529 void MacroAssembler::movbool(Register dst, Address src) {
6530 if(sizeof(bool) == 1)
6531 movb(dst, src);
6532 else if(sizeof(bool) == 2)
6533 movw(dst, src);
6534 else if(sizeof(bool) == 4)
6535 movl(dst, src);
6536 else
6537 // unsupported
6538 ShouldNotReachHere();
6539 }
6540
6541 void MacroAssembler::movbool(Address dst, bool boolconst) {
6542 if(sizeof(bool) == 1)
6543 movb(dst, (int) boolconst);
6544 else if(sizeof(bool) == 2)
6545 movw(dst, (int) boolconst);
6546 else if(sizeof(bool) == 4)
6547 movl(dst, (int) boolconst);
6548 else
6549 // unsupported
6550 ShouldNotReachHere();
6551 }
6552
6553 void MacroAssembler::movbool(Address dst, Register src) {
6554 if(sizeof(bool) == 1)
6555 movb(dst, src);
6556 else if(sizeof(bool) == 2)
6557 movw(dst, src);
6558 else if(sizeof(bool) == 4)
6559 movl(dst, src);
6560 else
6561 // unsupported
6562 ShouldNotReachHere();
6563 }
6564
6565 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
6566 movb(as_Address(dst), src);
6567 }
6568
6569 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
6570 if (reachable(src)) {
6571 if (UseXmmLoadAndClearUpper) {
6572 movsd (dst, as_Address(src));
6573 } else {
6574 movlpd(dst, as_Address(src));
6575 }
6576 } else {
6577 lea(rscratch1, src);
6578 if (UseXmmLoadAndClearUpper) {
6579 movsd (dst, Address(rscratch1, 0));
6580 } else {
6581 movlpd(dst, Address(rscratch1, 0));
6582 }
6583 }
6584 }
6585
6586 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
6587 if (reachable(src)) {
6588 movss(dst, as_Address(src));
6589 } else {
6590 lea(rscratch1, src);
6591 movss(dst, Address(rscratch1, 0));
6592 }
6593 }
6594
6595 void MacroAssembler::movptr(Register dst, Register src) {
6596 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6597 }
6598
6599 void MacroAssembler::movptr(Register dst, Address src) {
6600 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6601 }
6602
6603 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6604 void MacroAssembler::movptr(Register dst, intptr_t src) {
6605 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6606 }
6607
6608 void MacroAssembler::movptr(Address dst, Register src) {
6609 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6610 }
6611
6612 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
6613 if (reachable(src)) {
6614 movss(dst, as_Address(src));
6615 } else {
6616 lea(rscratch1, src);
6617 movss(dst, Address(rscratch1, 0));
6618 }
6619 }
6620
6621 void MacroAssembler::null_check(Register reg, int offset) {
6622 if (needs_explicit_null_check(offset)) {
6623 // provoke OS NULL exception if reg = NULL by
6624 // accessing M[reg] w/o changing any (non-CC) registers
6625 // NOTE: cmpl is plenty here to provoke a segv
6626 cmpptr(rax, Address(reg, 0));
6627 // Note: should probably use testl(rax, Address(reg, 0));
6628 // may be shorter code (however, this version of
6629 // testl needs to be implemented first)
6630 } else {
6631 // nothing to do, (later) access of M[reg + offset]
6632 // will provoke OS NULL exception if reg = NULL
6633 }
6634 }
6635
6636 void MacroAssembler::os_breakpoint() {
6637 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
6638 // (e.g., MSVC can't call ps() otherwise)
6639 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
6640 }
6641
6642 void MacroAssembler::pop_CPU_state() {
6643 pop_FPU_state();
6644 pop_IU_state();
6645 }
6646
6647 void MacroAssembler::pop_FPU_state() {
6648 NOT_LP64(frstor(Address(rsp, 0));)
6649 LP64_ONLY(fxrstor(Address(rsp, 0));)
6650 addptr(rsp, FPUStateSizeInWords * wordSize);
6651 }
6652
6653 void MacroAssembler::pop_IU_state() {
6654 popa();
6655 LP64_ONLY(addq(rsp, 8));
6656 popf();
6657 }
6658
6659 // Save Integer and Float state
6660 // Warning: Stack must be 16 byte aligned (64bit)
6661 void MacroAssembler::push_CPU_state() {
6662 push_IU_state();
6663 push_FPU_state();
6664 }
6665
6666 void MacroAssembler::push_FPU_state() {
6667 subptr(rsp, FPUStateSizeInWords * wordSize);
6668 #ifndef _LP64
6669 fnsave(Address(rsp, 0));
6670 fwait();
6671 #else
6672 fxsave(Address(rsp, 0));
6673 #endif // LP64
6674 }
6675
6676 void MacroAssembler::push_IU_state() {
6677 // Push flags first because pusha kills them
6678 pushf();
6679 // Make sure rsp stays 16-byte aligned
6680 LP64_ONLY(subq(rsp, 8));
6681 pusha();
6682 }
6683
6684 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
6685 // determine java_thread register
6686 if (!java_thread->is_valid()) {
6687 java_thread = rdi;
6688 get_thread(java_thread);
6689 }
6690 // we must set sp to zero to clear frame
6691 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
6692 if (clear_fp) {
6693 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
6694 }
6695
6696 if (clear_pc)
6697 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
6698
6699 }
6700
6701 void MacroAssembler::restore_rax(Register tmp) {
6702 if (tmp == noreg) pop(rax);
6703 else if (tmp != rax) mov(rax, tmp);
6704 }
6705
6706 void MacroAssembler::round_to(Register reg, int modulus) {
6707 addptr(reg, modulus - 1);
6708 andptr(reg, -modulus);
6709 }
6710
6711 void MacroAssembler::save_rax(Register tmp) {
6712 if (tmp == noreg) push(rax);
6713 else if (tmp != rax) mov(tmp, rax);
6714 }
6715
6716 // Write serialization page so VM thread can do a pseudo remote membar.
6717 // We use the current thread pointer to calculate a thread specific
6718 // offset to write to within the page. This minimizes bus traffic
6719 // due to cache line collision.
6720 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
6721 movl(tmp, thread);
6722 shrl(tmp, os::get_serialize_page_shift_count());
6723 andl(tmp, (os::vm_page_size() - sizeof(int)));
6724
6725 Address index(noreg, tmp, Address::times_1);
6726 ExternalAddress page(os::get_memory_serialize_page());
6727
6728 // Size of store must match masking code above
6729 movl(as_Address(ArrayAddress(page, index)), tmp);
6730 }
6731
6732 // Calls to C land
6733 //
6734 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
6735 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
6736 // has to be reset to 0. This is required to allow proper stack traversal.
6737 void MacroAssembler::set_last_Java_frame(Register java_thread,
6738 Register last_java_sp,
6739 Register last_java_fp,
6740 address last_java_pc) {
6741 // determine java_thread register
6742 if (!java_thread->is_valid()) {
6743 java_thread = rdi;
6744 get_thread(java_thread);
6745 }
6746 // determine last_java_sp register
6747 if (!last_java_sp->is_valid()) {
6748 last_java_sp = rsp;
6749 }
6750
6751 // last_java_fp is optional
6752
6753 if (last_java_fp->is_valid()) {
6754 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
6755 }
6756
6757 // last_java_pc is optional
6758
6759 if (last_java_pc != NULL) {
6760 lea(Address(java_thread,
6761 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
6762 InternalAddress(last_java_pc));
6763
6764 }
6765 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
6766 }
6767
6768 void MacroAssembler::shlptr(Register dst, int imm8) {
6769 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
6770 }
6771
6772 void MacroAssembler::shrptr(Register dst, int imm8) {
6773 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
6774 }
6775
6776 void MacroAssembler::sign_extend_byte(Register reg) {
6777 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
6778 movsbl(reg, reg); // movsxb
6779 } else {
6780 shll(reg, 24);
6781 sarl(reg, 24);
6782 }
6783 }
6784
6785 void MacroAssembler::sign_extend_short(Register reg) {
6786 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6787 movswl(reg, reg); // movsxw
6788 } else {
6789 shll(reg, 16);
6790 sarl(reg, 16);
6791 }
6792 }
6793
6794 //////////////////////////////////////////////////////////////////////////////////
6795 #ifndef SERIALGC
6796
6797 void MacroAssembler::g1_write_barrier_pre(Register obj,
6798 #ifndef _LP64
6799 Register thread,
6800 #endif
6801 Register tmp,
6802 Register tmp2,
6803 bool tosca_live) {
6804 LP64_ONLY(Register thread = r15_thread;)
6805 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6806 PtrQueue::byte_offset_of_active()));
6807
6808 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6809 PtrQueue::byte_offset_of_index()));
6810 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6811 PtrQueue::byte_offset_of_buf()));
6812
6813
6814 Label done;
6815 Label runtime;
6816
6817 // if (!marking_in_progress) goto done;
6818 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
6819 cmpl(in_progress, 0);
6820 } else {
6821 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
6822 cmpb(in_progress, 0);
6823 }
6824 jcc(Assembler::equal, done);
6825
6826 // if (x.f == NULL) goto done;
6827 #ifdef _LP64
6828 load_heap_oop(tmp2, Address(obj, 0));
6829 #else
6830 movptr(tmp2, Address(obj, 0));
6831 #endif
6832 cmpptr(tmp2, (int32_t) NULL_WORD);
6833 jcc(Assembler::equal, done);
6834
6835 // Can we store original value in the thread's buffer?
6836
6837 #ifdef _LP64
6838 movslq(tmp, index);
6839 cmpq(tmp, 0);
6840 #else
6841 cmpl(index, 0);
6842 #endif
6843 jcc(Assembler::equal, runtime);
6844 #ifdef _LP64
6845 subq(tmp, wordSize);
6846 movl(index, tmp);
6847 addq(tmp, buffer);
6848 #else
6849 subl(index, wordSize);
6850 movl(tmp, buffer);
6851 addl(tmp, index);
6852 #endif
6853 movptr(Address(tmp, 0), tmp2);
6854 jmp(done);
6855 bind(runtime);
6856 // save the live input values
6857 if(tosca_live) push(rax);
6858 push(obj);
6859 #ifdef _LP64
6860 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread);
6861 #else
6862 push(thread);
6863 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread);
6864 pop(thread);
6865 #endif
6866 pop(obj);
6867 if(tosca_live) pop(rax);
6868 bind(done);
6869
6870 }
6871
6872 void MacroAssembler::g1_write_barrier_post(Register store_addr,
6873 Register new_val,
6874 #ifndef _LP64
6875 Register thread,
6876 #endif
6877 Register tmp,
6878 Register tmp2) {
6879
6880 LP64_ONLY(Register thread = r15_thread;)
6881 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6882 PtrQueue::byte_offset_of_index()));
6883 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6884 PtrQueue::byte_offset_of_buf()));
6885 BarrierSet* bs = Universe::heap()->barrier_set();
6886 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
6887 Label done;
6888 Label runtime;
6889
6890 // Does store cross heap regions?
6891
6892 movptr(tmp, store_addr);
6893 xorptr(tmp, new_val);
6894 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
6895 jcc(Assembler::equal, done);
6896
6897 // crosses regions, storing NULL?
6898
6899 cmpptr(new_val, (int32_t) NULL_WORD);
6900 jcc(Assembler::equal, done);
6901
6902 // storing region crossing non-NULL, is card already dirty?
6903
6904 ExternalAddress cardtable((address) ct->byte_map_base);
6905 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
6906 #ifdef _LP64
6907 const Register card_addr = tmp;
6908
6909 movq(card_addr, store_addr);
6910 shrq(card_addr, CardTableModRefBS::card_shift);
6911
6912 lea(tmp2, cardtable);
6913
6914 // get the address of the card
6915 addq(card_addr, tmp2);
6916 #else
6917 const Register card_index = tmp;
6918
6919 movl(card_index, store_addr);
6920 shrl(card_index, CardTableModRefBS::card_shift);
6921
6922 Address index(noreg, card_index, Address::times_1);
6923 const Register card_addr = tmp;
6924 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
6925 #endif
6926 cmpb(Address(card_addr, 0), 0);
6927 jcc(Assembler::equal, done);
6928
6929 // storing a region crossing, non-NULL oop, card is clean.
6930 // dirty card and log.
6931
6932 movb(Address(card_addr, 0), 0);
6933
6934 cmpl(queue_index, 0);
6935 jcc(Assembler::equal, runtime);
6936 subl(queue_index, wordSize);
6937 movptr(tmp2, buffer);
6938 #ifdef _LP64
6939 movslq(rscratch1, queue_index);
6940 addq(tmp2, rscratch1);
6941 movq(Address(tmp2, 0), card_addr);
6942 #else
6943 addl(tmp2, queue_index);
6944 movl(Address(tmp2, 0), card_index);
6945 #endif
6946 jmp(done);
6947
6948 bind(runtime);
6949 // save the live input values
6950 push(store_addr);
6951 push(new_val);
6952 #ifdef _LP64
6953 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
6954 #else
6955 push(thread);
6956 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
6957 pop(thread);
6958 #endif
6959 pop(new_val);
6960 pop(store_addr);
6961
6962 bind(done);
6963
6964 }
6965
6966 #endif // SERIALGC
6967 //////////////////////////////////////////////////////////////////////////////////
6968
6969
6970 void MacroAssembler::store_check(Register obj) {
6971 // Does a store check for the oop in register obj. The content of
6972 // register obj is destroyed afterwards.
6973 store_check_part_1(obj);
6974 store_check_part_2(obj);
6975 }
6976
6977 void MacroAssembler::store_check(Register obj, Address dst) {
6978 store_check(obj);
6979 }
6980
6981
6982 // split the store check operation so that other instructions can be scheduled inbetween
6983 void MacroAssembler::store_check_part_1(Register obj) {
6984 BarrierSet* bs = Universe::heap()->barrier_set();
6985 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
6986 shrptr(obj, CardTableModRefBS::card_shift);
6987 }
6988
6989 void MacroAssembler::store_check_part_2(Register obj) {
6990 BarrierSet* bs = Universe::heap()->barrier_set();
6991 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
6992 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
6993 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
6994
6995 // The calculation for byte_map_base is as follows:
6996 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
6997 // So this essentially converts an address to a displacement and
6998 // it will never need to be relocated. On 64bit however the value may be too
6999 // large for a 32bit displacement
7000
7001 intptr_t disp = (intptr_t) ct->byte_map_base;
7002 if (is_simm32(disp)) {
7003 Address cardtable(noreg, obj, Address::times_1, disp);
7004 movb(cardtable, 0);
7005 } else {
7006 // By doing it as an ExternalAddress disp could be converted to a rip-relative
7007 // displacement and done in a single instruction given favorable mapping and
7008 // a smarter version of as_Address. Worst case it is two instructions which
7009 // is no worse off then loading disp into a register and doing as a simple
7010 // Address() as above.
7011 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
7012 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
7013 // in some cases we'll get a single instruction version.
7014
7015 ExternalAddress cardtable((address)disp);
7016 Address index(noreg, obj, Address::times_1);
7017 movb(as_Address(ArrayAddress(cardtable, index)), 0);
7018 }
7019 }
7020
7021 void MacroAssembler::subptr(Register dst, int32_t imm32) {
7022 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
7023 }
7024
7025 void MacroAssembler::subptr(Register dst, Register src) {
7026 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
7027 }
7028
7029 void MacroAssembler::test32(Register src1, AddressLiteral src2) {
7030 // src2 must be rval
7031
7032 if (reachable(src2)) {
7033 testl(src1, as_Address(src2));
7034 } else {
7035 lea(rscratch1, src2);
7036 testl(src1, Address(rscratch1, 0));
7037 }
7038 }
7039
7040 // C++ bool manipulation
7041 void MacroAssembler::testbool(Register dst) {
7042 if(sizeof(bool) == 1)
7043 testb(dst, 0xff);
7044 else if(sizeof(bool) == 2) {
7045 // testw implementation needed for two byte bools
7046 ShouldNotReachHere();
7047 } else if(sizeof(bool) == 4)
7048 testl(dst, dst);
7049 else
7050 // unsupported
7051 ShouldNotReachHere();
7052 }
7053
7054 void MacroAssembler::testptr(Register dst, Register src) {
7055 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
7056 }
7057
7058 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
7059 void MacroAssembler::tlab_allocate(Register obj,
7060 Register var_size_in_bytes,
7061 int con_size_in_bytes,
7062 Register t1,
7063 Register t2,
7064 Label& slow_case) {
7065 assert_different_registers(obj, t1, t2);
7066 assert_different_registers(obj, var_size_in_bytes, t1);
7067 Register end = t2;
7068 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
7069
7070 verify_tlab();
7071
7072 NOT_LP64(get_thread(thread));
7073
7074 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
7075 if (var_size_in_bytes == noreg) {
7076 lea(end, Address(obj, con_size_in_bytes));
7077 } else {
7078 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
7079 }
7080 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
7081 jcc(Assembler::above, slow_case);
7082
7083 // update the tlab top pointer
7084 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
7085
7086 // recover var_size_in_bytes if necessary
7087 if (var_size_in_bytes == end) {
7088 subptr(var_size_in_bytes, obj);
7089 }
7090 verify_tlab();
7091 }
7092
7093 // Preserves rbx, and rdx.
7094 void MacroAssembler::tlab_refill(Label& retry,
7095 Label& try_eden,
7096 Label& slow_case) {
7097 Register top = rax;
7098 Register t1 = rcx;
7099 Register t2 = rsi;
7100 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
7101 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
7102 Label do_refill, discard_tlab;
7103
7104 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
7105 // No allocation in the shared eden.
7106 jmp(slow_case);
7107 }
7108
7109 NOT_LP64(get_thread(thread_reg));
7110
7111 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7112 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7113
7114 // calculate amount of free space
7115 subptr(t1, top);
7116 shrptr(t1, LogHeapWordSize);
7117
7118 // Retain tlab and allocate object in shared space if
7119 // the amount free in the tlab is too large to discard.
7120 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
7121 jcc(Assembler::lessEqual, discard_tlab);
7122
7123 // Retain
7124 // %%% yuck as movptr...
7125 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
7126 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
7127 if (TLABStats) {
7128 // increment number of slow_allocations
7129 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
7130 }
7131 jmp(try_eden);
7132
7133 bind(discard_tlab);
7134 if (TLABStats) {
7135 // increment number of refills
7136 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
7137 // accumulate wastage -- t1 is amount free in tlab
7138 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
7139 }
7140
7141 // if tlab is currently allocated (top or end != null) then
7142 // fill [top, end + alignment_reserve) with array object
7143 testptr (top, top);
7144 jcc(Assembler::zero, do_refill);
7145
7146 // set up the mark word
7147 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
7148 // set the length to the remaining space
7149 subptr(t1, typeArrayOopDesc::header_size(T_INT));
7150 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
7151 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
7152 movptr(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
7153 // set klass to intArrayKlass
7154 // dubious reloc why not an oop reloc?
7155 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
7156 // store klass last. concurrent gcs assumes klass length is valid if
7157 // klass field is not null.
7158 store_klass(top, t1);
7159
7160 // refill the tlab with an eden allocation
7161 bind(do_refill);
7162 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7163 shlptr(t1, LogHeapWordSize);
7164 // add object_size ??
7165 eden_allocate(top, t1, 0, t2, slow_case);
7166
7167 // Check that t1 was preserved in eden_allocate.
7168 #ifdef ASSERT
7169 if (UseTLAB) {
7170 Label ok;
7171 Register tsize = rsi;
7172 assert_different_registers(tsize, thread_reg, t1);
7173 push(tsize);
7174 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7175 shlptr(tsize, LogHeapWordSize);
7176 cmpptr(t1, tsize);
7177 jcc(Assembler::equal, ok);
7178 stop("assert(t1 != tlab size)");
7179 should_not_reach_here();
7180
7181 bind(ok);
7182 pop(tsize);
7183 }
7184 #endif
7185 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
7186 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
7187 addptr(top, t1);
7188 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
7189 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
7190 verify_tlab();
7191 jmp(retry);
7192 }
7193
7194 static const double pi_4 = 0.7853981633974483;
7195
7196 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
7197 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
7198 // was attempted in this code; unfortunately it appears that the
7199 // switch to 80-bit precision and back causes this to be
7200 // unprofitable compared with simply performing a runtime call if
7201 // the argument is out of the (-pi/4, pi/4) range.
7202
7203 Register tmp = noreg;
7204 if (!VM_Version::supports_cmov()) {
7205 // fcmp needs a temporary so preserve rbx,
7206 tmp = rbx;
7207 push(tmp);
7208 }
7209
7210 Label slow_case, done;
7211
7212 ExternalAddress pi4_adr = (address)&pi_4;
7213 if (reachable(pi4_adr)) {
7214 // x ?<= pi/4
7215 fld_d(pi4_adr);
7216 fld_s(1); // Stack: X PI/4 X
7217 fabs(); // Stack: |X| PI/4 X
7218 fcmp(tmp);
7219 jcc(Assembler::above, slow_case);
7220
7221 // fastest case: -pi/4 <= x <= pi/4
7222 switch(trig) {
7223 case 's':
7224 fsin();
7225 break;
7226 case 'c':
7227 fcos();
7228 break;
7229 case 't':
7230 ftan();
7231 break;
7232 default:
7233 assert(false, "bad intrinsic");
7234 break;
7235 }
7236 jmp(done);
7237 }
7238
7239 // slow case: runtime call
7240 bind(slow_case);
7241 // Preserve registers across runtime call
7242 pusha();
7243 int incoming_argument_and_return_value_offset = -1;
7244 if (num_fpu_regs_in_use > 1) {
7245 // Must preserve all other FPU regs (could alternatively convert
7246 // SharedRuntime::dsin and dcos into assembly routines known not to trash
7247 // FPU state, but can not trust C compiler)
7248 NEEDS_CLEANUP;
7249 // NOTE that in this case we also push the incoming argument to
7250 // the stack and restore it later; we also use this stack slot to
7251 // hold the return value from dsin or dcos.
7252 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7253 subptr(rsp, sizeof(jdouble));
7254 fstp_d(Address(rsp, 0));
7255 }
7256 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
7257 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
7258 }
7259 subptr(rsp, sizeof(jdouble));
7260 fstp_d(Address(rsp, 0));
7261 #ifdef _LP64
7262 movdbl(xmm0, Address(rsp, 0));
7263 #endif // _LP64
7264
7265 // NOTE: we must not use call_VM_leaf here because that requires a
7266 // complete interpreter frame in debug mode -- same bug as 4387334
7267 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
7268 // do proper 64bit abi
7269
7270 NEEDS_CLEANUP;
7271 // Need to add stack banging before this runtime call if it needs to
7272 // be taken; however, there is no generic stack banging routine at
7273 // the MacroAssembler level
7274 switch(trig) {
7275 case 's':
7276 {
7277 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
7278 }
7279 break;
7280 case 'c':
7281 {
7282 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
7283 }
7284 break;
7285 case 't':
7286 {
7287 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
7288 }
7289 break;
7290 default:
7291 assert(false, "bad intrinsic");
7292 break;
7293 }
7294 #ifdef _LP64
7295 movsd(Address(rsp, 0), xmm0);
7296 fld_d(Address(rsp, 0));
7297 #endif // _LP64
7298 addptr(rsp, sizeof(jdouble));
7299 if (num_fpu_regs_in_use > 1) {
7300 // Must save return value to stack and then restore entire FPU stack
7301 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
7302 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7303 fld_d(Address(rsp, 0));
7304 addptr(rsp, sizeof(jdouble));
7305 }
7306 }
7307 popa();
7308
7309 // Come here with result in F-TOS
7310 bind(done);
7311
7312 if (tmp != noreg) {
7313 pop(tmp);
7314 }
7315 }
7316
7317
7318 // Look up the method for a megamorphic invokeinterface call.
7319 // The target method is determined by <intf_klass, itable_index>.
7320 // The receiver klass is in recv_klass.
7321 // On success, the result will be in method_result, and execution falls through.
7322 // On failure, execution transfers to the given label.
7323 void MacroAssembler::lookup_interface_method(Register recv_klass,
7324 Register intf_klass,
7325 RegisterOrConstant itable_index,
7326 Register method_result,
7327 Register scan_temp,
7328 Label& L_no_such_interface) {
7329 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
7330 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
7331 "caller must use same register for non-constant itable index as for method");
7332
7333 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
7334 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
7335 int itentry_off = itableMethodEntry::method_offset_in_bytes();
7336 int scan_step = itableOffsetEntry::size() * wordSize;
7337 int vte_size = vtableEntry::size() * wordSize;
7338 Address::ScaleFactor times_vte_scale = Address::times_ptr;
7339 assert(vte_size == wordSize, "else adjust times_vte_scale");
7340
7341 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
7342
7343 // %%% Could store the aligned, prescaled offset in the klassoop.
7344 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
7345 if (HeapWordsPerLong > 1) {
7346 // Round up to align_object_offset boundary
7347 // see code for instanceKlass::start_of_itable!
7348 round_to(scan_temp, BytesPerLong);
7349 }
7350
7351 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
7352 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
7353 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
7354
7355 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
7356 // if (scan->interface() == intf) {
7357 // result = (klass + scan->offset() + itable_index);
7358 // }
7359 // }
7360 Label search, found_method;
7361
7362 for (int peel = 1; peel >= 0; peel--) {
7363 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
7364 cmpptr(intf_klass, method_result);
7365
7366 if (peel) {
7367 jccb(Assembler::equal, found_method);
7368 } else {
7369 jccb(Assembler::notEqual, search);
7370 // (invert the test to fall through to found_method...)
7371 }
7372
7373 if (!peel) break;
7374
7375 bind(search);
7376
7377 // Check that the previous entry is non-null. A null entry means that
7378 // the receiver class doesn't implement the interface, and wasn't the
7379 // same as when the caller was compiled.
7380 testptr(method_result, method_result);
7381 jcc(Assembler::zero, L_no_such_interface);
7382 addptr(scan_temp, scan_step);
7383 }
7384
7385 bind(found_method);
7386
7387 // Got a hit.
7388 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
7389 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
7390 }
7391
7392
7393 void MacroAssembler::check_klass_subtype(Register sub_klass,
7394 Register super_klass,
7395 Register temp_reg,
7396 Label& L_success) {
7397 Label L_failure;
7398 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
7399 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
7400 bind(L_failure);
7401 }
7402
7403
7404 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
7405 Register super_klass,
7406 Register temp_reg,
7407 Label* L_success,
7408 Label* L_failure,
7409 Label* L_slow_path,
7410 RegisterOrConstant super_check_offset) {
7411 assert_different_registers(sub_klass, super_klass, temp_reg);
7412 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
7413 if (super_check_offset.is_register()) {
7414 assert_different_registers(sub_klass, super_klass,
7415 super_check_offset.as_register());
7416 } else if (must_load_sco) {
7417 assert(temp_reg != noreg, "supply either a temp or a register offset");
7418 }
7419
7420 Label L_fallthrough;
7421 int label_nulls = 0;
7422 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7423 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7424 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
7425 assert(label_nulls <= 1, "at most one NULL in the batch");
7426
7427 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7428 Klass::secondary_super_cache_offset_in_bytes());
7429 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
7430 Klass::super_check_offset_offset_in_bytes());
7431 Address super_check_offset_addr(super_klass, sco_offset);
7432
7433 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
7434 // range of a jccb. If this routine grows larger, reconsider at
7435 // least some of these.
7436 #define local_jcc(assembler_cond, label) \
7437 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
7438 else jcc( assembler_cond, label) /*omit semi*/
7439
7440 // Hacked jmp, which may only be used just before L_fallthrough.
7441 #define final_jmp(label) \
7442 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
7443 else jmp(label) /*omit semi*/
7444
7445 // If the pointers are equal, we are done (e.g., String[] elements).
7446 // This self-check enables sharing of secondary supertype arrays among
7447 // non-primary types such as array-of-interface. Otherwise, each such
7448 // type would need its own customized SSA.
7449 // We move this check to the front of the fast path because many
7450 // type checks are in fact trivially successful in this manner,
7451 // so we get a nicely predicted branch right at the start of the check.
7452 cmpptr(sub_klass, super_klass);
7453 local_jcc(Assembler::equal, *L_success);
7454
7455 // Check the supertype display:
7456 if (must_load_sco) {
7457 // Positive movl does right thing on LP64.
7458 movl(temp_reg, super_check_offset_addr);
7459 super_check_offset = RegisterOrConstant(temp_reg);
7460 }
7461 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
7462 cmpptr(super_klass, super_check_addr); // load displayed supertype
7463
7464 // This check has worked decisively for primary supers.
7465 // Secondary supers are sought in the super_cache ('super_cache_addr').
7466 // (Secondary supers are interfaces and very deeply nested subtypes.)
7467 // This works in the same check above because of a tricky aliasing
7468 // between the super_cache and the primary super display elements.
7469 // (The 'super_check_addr' can address either, as the case requires.)
7470 // Note that the cache is updated below if it does not help us find
7471 // what we need immediately.
7472 // So if it was a primary super, we can just fail immediately.
7473 // Otherwise, it's the slow path for us (no success at this point).
7474
7475 if (super_check_offset.is_register()) {
7476 local_jcc(Assembler::equal, *L_success);
7477 cmpl(super_check_offset.as_register(), sc_offset);
7478 if (L_failure == &L_fallthrough) {
7479 local_jcc(Assembler::equal, *L_slow_path);
7480 } else {
7481 local_jcc(Assembler::notEqual, *L_failure);
7482 final_jmp(*L_slow_path);
7483 }
7484 } else if (super_check_offset.as_constant() == sc_offset) {
7485 // Need a slow path; fast failure is impossible.
7486 if (L_slow_path == &L_fallthrough) {
7487 local_jcc(Assembler::equal, *L_success);
7488 } else {
7489 local_jcc(Assembler::notEqual, *L_slow_path);
7490 final_jmp(*L_success);
7491 }
7492 } else {
7493 // No slow path; it's a fast decision.
7494 if (L_failure == &L_fallthrough) {
7495 local_jcc(Assembler::equal, *L_success);
7496 } else {
7497 local_jcc(Assembler::notEqual, *L_failure);
7498 final_jmp(*L_success);
7499 }
7500 }
7501
7502 bind(L_fallthrough);
7503
7504 #undef local_jcc
7505 #undef final_jmp
7506 }
7507
7508
7509 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
7510 Register super_klass,
7511 Register temp_reg,
7512 Register temp2_reg,
7513 Label* L_success,
7514 Label* L_failure,
7515 bool set_cond_codes) {
7516 assert_different_registers(sub_klass, super_klass, temp_reg);
7517 if (temp2_reg != noreg)
7518 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
7519 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
7520
7521 Label L_fallthrough;
7522 int label_nulls = 0;
7523 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7524 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7525 assert(label_nulls <= 1, "at most one NULL in the batch");
7526
7527 // a couple of useful fields in sub_klass:
7528 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
7529 Klass::secondary_supers_offset_in_bytes());
7530 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7531 Klass::secondary_super_cache_offset_in_bytes());
7532 Address secondary_supers_addr(sub_klass, ss_offset);
7533 Address super_cache_addr( sub_klass, sc_offset);
7534
7535 // Do a linear scan of the secondary super-klass chain.
7536 // This code is rarely used, so simplicity is a virtue here.
7537 // The repne_scan instruction uses fixed registers, which we must spill.
7538 // Don't worry too much about pre-existing connections with the input regs.
7539
7540 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
7541 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
7542
7543 // Get super_klass value into rax (even if it was in rdi or rcx).
7544 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
7545 if (super_klass != rax || UseCompressedOops) {
7546 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
7547 mov(rax, super_klass);
7548 }
7549 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
7550 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
7551
7552 #ifndef PRODUCT
7553 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
7554 ExternalAddress pst_counter_addr((address) pst_counter);
7555 NOT_LP64( incrementl(pst_counter_addr) );
7556 LP64_ONLY( lea(rcx, pst_counter_addr) );
7557 LP64_ONLY( incrementl(Address(rcx, 0)) );
7558 #endif //PRODUCT
7559
7560 // We will consult the secondary-super array.
7561 movptr(rdi, secondary_supers_addr);
7562 // Load the array length. (Positive movl does right thing on LP64.)
7563 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
7564 // Skip to start of data.
7565 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7566
7567 // Scan RCX words at [RDI] for an occurrence of RAX.
7568 // Set NZ/Z based on last compare.
7569 #ifdef _LP64
7570 // This part is tricky, as values in supers array could be 32 or 64 bit wide
7571 // and we store values in objArrays always encoded, thus we need to encode
7572 // the value of rax before repne. Note that rax is dead after the repne.
7573 if (UseCompressedOops) {
7574 encode_heap_oop_not_null(rax);
7575 // The superclass is never null; it would be a basic system error if a null
7576 // pointer were to sneak in here. Note that we have already loaded the
7577 // Klass::super_check_offset from the super_klass in the fast path,
7578 // so if there is a null in that register, we are already in the afterlife.
7579 repne_scanl();
7580 } else
7581 #endif // _LP64
7582 repne_scan();
7583
7584 // Unspill the temp. registers:
7585 if (pushed_rdi) pop(rdi);
7586 if (pushed_rcx) pop(rcx);
7587 if (pushed_rax) pop(rax);
7588
7589 if (set_cond_codes) {
7590 // Special hack for the AD files: rdi is guaranteed non-zero.
7591 assert(!pushed_rdi, "rdi must be left non-NULL");
7592 // Also, the condition codes are properly set Z/NZ on succeed/failure.
7593 }
7594
7595 if (L_failure == &L_fallthrough)
7596 jccb(Assembler::notEqual, *L_failure);
7597 else jcc(Assembler::notEqual, *L_failure);
7598
7599 // Success. Cache the super we found and proceed in triumph.
7600 movptr(super_cache_addr, super_klass);
7601
7602 if (L_success != &L_fallthrough) {
7603 jmp(*L_success);
7604 }
7605
7606 #undef IS_A_TEMP
7607
7608 bind(L_fallthrough);
7609 }
7610
7611
7612 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7613 ucomisd(dst, as_Address(src));
7614 }
7615
7616 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7617 ucomiss(dst, as_Address(src));
7618 }
7619
7620 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7621 if (reachable(src)) {
7622 xorpd(dst, as_Address(src));
7623 } else {
7624 lea(rscratch1, src);
7625 xorpd(dst, Address(rscratch1, 0));
7626 }
7627 }
7628
7629 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7630 if (reachable(src)) {
7631 xorps(dst, as_Address(src));
7632 } else {
7633 lea(rscratch1, src);
7634 xorps(dst, Address(rscratch1, 0));
7635 }
7636 }
7637
7638 void MacroAssembler::verify_oop(Register reg, const char* s) {
7639 if (!VerifyOops) return;
7640
7641 // Pass register number to verify_oop_subroutine
7642 char* b = new char[strlen(s) + 50];
7643 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
7644 push(rax); // save rax,
7645 push(reg); // pass register argument
7646 ExternalAddress buffer((address) b);
7647 // avoid using pushptr, as it modifies scratch registers
7648 // and our contract is not to modify anything
7649 movptr(rax, buffer.addr());
7650 push(rax);
7651 // call indirectly to solve generation ordering problem
7652 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7653 call(rax);
7654 }
7655
7656
7657 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
7658 Register tmp,
7659 int offset) {
7660 intptr_t value = *delayed_value_addr;
7661 if (value != 0)
7662 return RegisterOrConstant(value + offset);
7663
7664 // load indirectly to solve generation ordering problem
7665 movptr(tmp, ExternalAddress((address) delayed_value_addr));
7666
7667 #ifdef ASSERT
7668 Label L;
7669 testptr(tmp, tmp);
7670 jccb(Assembler::notZero, L);
7671 hlt();
7672 bind(L);
7673 #endif
7674
7675 if (offset != 0)
7676 addptr(tmp, offset);
7677
7678 return RegisterOrConstant(tmp);
7679 }
7680
7681
7682 // registers on entry:
7683 // - rax ('check' register): required MethodType
7684 // - rcx: method handle
7685 // - rdx, rsi, or ?: killable temp
7686 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
7687 Register temp_reg,
7688 Label& wrong_method_type) {
7689 if (UseCompressedOops) unimplemented(); // field accesses must decode
7690 // compare method type against that of the receiver
7691 cmpptr(mtype_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)));
7692 jcc(Assembler::notEqual, wrong_method_type);
7693 }
7694
7695
7696 // A method handle has a "vmslots" field which gives the size of its
7697 // argument list in JVM stack slots. This field is either located directly
7698 // in every method handle, or else is indirectly accessed through the
7699 // method handle's MethodType. This macro hides the distinction.
7700 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
7701 Register temp_reg) {
7702 if (UseCompressedOops) unimplemented(); // field accesses must decode
7703 // load mh.type.form.vmslots
7704 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) {
7705 // hoist vmslots into every mh to avoid dependent load chain
7706 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)));
7707 } else {
7708 Register temp2_reg = vmslots_reg;
7709 movptr(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)));
7710 movptr(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)));
7711 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)));
7712 }
7713 }
7714
7715
7716 // registers on entry:
7717 // - rcx: method handle
7718 // - rdx: killable temp (interpreted only)
7719 // - rax: killable temp (compiled only)
7720 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
7721 assert(mh_reg == rcx, "caller must put MH object in rcx");
7722 assert_different_registers(mh_reg, temp_reg);
7723
7724 if (UseCompressedOops) unimplemented(); // field accesses must decode
7725
7726 // pick out the interpreted side of the handler
7727 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg)));
7728
7729 // off we go...
7730 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes()));
7731
7732 // for the various stubs which take control at this point,
7733 // see MethodHandles::generate_method_handle_stub
7734 }
7735
7736
7737 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
7738 int extra_slot_offset) {
7739 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
7740 int stackElementSize = Interpreter::stackElementSize();
7741 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
7742 #ifdef ASSERT
7743 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
7744 assert(offset1 - offset == stackElementSize, "correct arithmetic");
7745 #endif
7746 Register scale_reg = noreg;
7747 Address::ScaleFactor scale_factor = Address::no_scale;
7748 if (arg_slot.is_constant()) {
7749 offset += arg_slot.as_constant() * stackElementSize;
7750 } else {
7751 scale_reg = arg_slot.as_register();
7752 scale_factor = Address::times(stackElementSize);
7753 }
7754 offset += wordSize; // return PC is on stack
7755 return Address(rsp, scale_reg, scale_factor, offset);
7756 }
7757
7758
7759 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
7760 if (!VerifyOops) return;
7761
7762 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
7763 // Pass register number to verify_oop_subroutine
7764 char* b = new char[strlen(s) + 50];
7765 sprintf(b, "verify_oop_addr: %s", s);
7766
7767 push(rax); // save rax,
7768 // addr may contain rsp so we will have to adjust it based on the push
7769 // we just did
7770 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
7771 // stores rax into addr which is backwards of what was intended.
7772 if (addr.uses(rsp)) {
7773 lea(rax, addr);
7774 pushptr(Address(rax, BytesPerWord));
7775 } else {
7776 pushptr(addr);
7777 }
7778
7779 ExternalAddress buffer((address) b);
7780 // pass msg argument
7781 // avoid using pushptr, as it modifies scratch registers
7782 // and our contract is not to modify anything
7783 movptr(rax, buffer.addr());
7784 push(rax);
7785
7786 // call indirectly to solve generation ordering problem
7787 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7788 call(rax);
7789 // Caller pops the arguments and restores rax, from the stack
7790 }
7791
7792 void MacroAssembler::verify_tlab() {
7793 #ifdef ASSERT
7794 if (UseTLAB && VerifyOops) {
7795 Label next, ok;
7796 Register t1 = rsi;
7797 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
7798
7799 push(t1);
7800 NOT_LP64(push(thread_reg));
7801 NOT_LP64(get_thread(thread_reg));
7802
7803 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7804 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
7805 jcc(Assembler::aboveEqual, next);
7806 stop("assert(top >= start)");
7807 should_not_reach_here();
7808
7809 bind(next);
7810 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7811 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7812 jcc(Assembler::aboveEqual, ok);
7813 stop("assert(top <= end)");
7814 should_not_reach_here();
7815
7816 bind(ok);
7817 NOT_LP64(pop(thread_reg));
7818 pop(t1);
7819 }
7820 #endif
7821 }
7822
7823 class ControlWord {
7824 public:
7825 int32_t _value;
7826
7827 int rounding_control() const { return (_value >> 10) & 3 ; }
7828 int precision_control() const { return (_value >> 8) & 3 ; }
7829 bool precision() const { return ((_value >> 5) & 1) != 0; }
7830 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7831 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7832 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7833 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7834 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7835
7836 void print() const {
7837 // rounding control
7838 const char* rc;
7839 switch (rounding_control()) {
7840 case 0: rc = "round near"; break;
7841 case 1: rc = "round down"; break;
7842 case 2: rc = "round up "; break;
7843 case 3: rc = "chop "; break;
7844 };
7845 // precision control
7846 const char* pc;
7847 switch (precision_control()) {
7848 case 0: pc = "24 bits "; break;
7849 case 1: pc = "reserved"; break;
7850 case 2: pc = "53 bits "; break;
7851 case 3: pc = "64 bits "; break;
7852 };
7853 // flags
7854 char f[9];
7855 f[0] = ' ';
7856 f[1] = ' ';
7857 f[2] = (precision ()) ? 'P' : 'p';
7858 f[3] = (underflow ()) ? 'U' : 'u';
7859 f[4] = (overflow ()) ? 'O' : 'o';
7860 f[5] = (zero_divide ()) ? 'Z' : 'z';
7861 f[6] = (denormalized()) ? 'D' : 'd';
7862 f[7] = (invalid ()) ? 'I' : 'i';
7863 f[8] = '\x0';
7864 // output
7865 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
7866 }
7867
7868 };
7869
7870 class StatusWord {
7871 public:
7872 int32_t _value;
7873
7874 bool busy() const { return ((_value >> 15) & 1) != 0; }
7875 bool C3() const { return ((_value >> 14) & 1) != 0; }
7876 bool C2() const { return ((_value >> 10) & 1) != 0; }
7877 bool C1() const { return ((_value >> 9) & 1) != 0; }
7878 bool C0() const { return ((_value >> 8) & 1) != 0; }
7879 int top() const { return (_value >> 11) & 7 ; }
7880 bool error_status() const { return ((_value >> 7) & 1) != 0; }
7881 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
7882 bool precision() const { return ((_value >> 5) & 1) != 0; }
7883 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7884 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7885 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7886 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7887 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7888
7889 void print() const {
7890 // condition codes
7891 char c[5];
7892 c[0] = (C3()) ? '3' : '-';
7893 c[1] = (C2()) ? '2' : '-';
7894 c[2] = (C1()) ? '1' : '-';
7895 c[3] = (C0()) ? '0' : '-';
7896 c[4] = '\x0';
7897 // flags
7898 char f[9];
7899 f[0] = (error_status()) ? 'E' : '-';
7900 f[1] = (stack_fault ()) ? 'S' : '-';
7901 f[2] = (precision ()) ? 'P' : '-';
7902 f[3] = (underflow ()) ? 'U' : '-';
7903 f[4] = (overflow ()) ? 'O' : '-';
7904 f[5] = (zero_divide ()) ? 'Z' : '-';
7905 f[6] = (denormalized()) ? 'D' : '-';
7906 f[7] = (invalid ()) ? 'I' : '-';
7907 f[8] = '\x0';
7908 // output
7909 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
7910 }
7911
7912 };
7913
7914 class TagWord {
7915 public:
7916 int32_t _value;
7917
7918 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
7919
7920 void print() const {
7921 printf("%04x", _value & 0xFFFF);
7922 }
7923
7924 };
7925
7926 class FPU_Register {
7927 public:
7928 int32_t _m0;
7929 int32_t _m1;
7930 int16_t _ex;
7931
7932 bool is_indefinite() const {
7933 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
7934 }
7935
7936 void print() const {
7937 char sign = (_ex < 0) ? '-' : '+';
7938 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
7939 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
7940 };
7941
7942 };
7943
7944 class FPU_State {
7945 public:
7946 enum {
7947 register_size = 10,
7948 number_of_registers = 8,
7949 register_mask = 7
7950 };
7951
7952 ControlWord _control_word;
7953 StatusWord _status_word;
7954 TagWord _tag_word;
7955 int32_t _error_offset;
7956 int32_t _error_selector;
7957 int32_t _data_offset;
7958 int32_t _data_selector;
7959 int8_t _register[register_size * number_of_registers];
7960
7961 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
7962 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
7963
7964 const char* tag_as_string(int tag) const {
7965 switch (tag) {
7966 case 0: return "valid";
7967 case 1: return "zero";
7968 case 2: return "special";
7969 case 3: return "empty";
7970 }
7971 ShouldNotReachHere()
7972 return NULL;
7973 }
7974
7975 void print() const {
7976 // print computation registers
7977 { int t = _status_word.top();
7978 for (int i = 0; i < number_of_registers; i++) {
7979 int j = (i - t) & register_mask;
7980 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
7981 st(j)->print();
7982 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
7983 }
7984 }
7985 printf("\n");
7986 // print control registers
7987 printf("ctrl = "); _control_word.print(); printf("\n");
7988 printf("stat = "); _status_word .print(); printf("\n");
7989 printf("tags = "); _tag_word .print(); printf("\n");
7990 }
7991
7992 };
7993
7994 class Flag_Register {
7995 public:
7996 int32_t _value;
7997
7998 bool overflow() const { return ((_value >> 11) & 1) != 0; }
7999 bool direction() const { return ((_value >> 10) & 1) != 0; }
8000 bool sign() const { return ((_value >> 7) & 1) != 0; }
8001 bool zero() const { return ((_value >> 6) & 1) != 0; }
8002 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
8003 bool parity() const { return ((_value >> 2) & 1) != 0; }
8004 bool carry() const { return ((_value >> 0) & 1) != 0; }
8005
8006 void print() const {
8007 // flags
8008 char f[8];
8009 f[0] = (overflow ()) ? 'O' : '-';
8010 f[1] = (direction ()) ? 'D' : '-';
8011 f[2] = (sign ()) ? 'S' : '-';
8012 f[3] = (zero ()) ? 'Z' : '-';
8013 f[4] = (auxiliary_carry()) ? 'A' : '-';
8014 f[5] = (parity ()) ? 'P' : '-';
8015 f[6] = (carry ()) ? 'C' : '-';
8016 f[7] = '\x0';
8017 // output
8018 printf("%08x flags = %s", _value, f);
8019 }
8020
8021 };
8022
8023 class IU_Register {
8024 public:
8025 int32_t _value;
8026
8027 void print() const {
8028 printf("%08x %11d", _value, _value);
8029 }
8030
8031 };
8032
8033 class IU_State {
8034 public:
8035 Flag_Register _eflags;
8036 IU_Register _rdi;
8037 IU_Register _rsi;
8038 IU_Register _rbp;
8039 IU_Register _rsp;
8040 IU_Register _rbx;
8041 IU_Register _rdx;
8042 IU_Register _rcx;
8043 IU_Register _rax;
8044
8045 void print() const {
8046 // computation registers
8047 printf("rax, = "); _rax.print(); printf("\n");
8048 printf("rbx, = "); _rbx.print(); printf("\n");
8049 printf("rcx = "); _rcx.print(); printf("\n");
8050 printf("rdx = "); _rdx.print(); printf("\n");
8051 printf("rdi = "); _rdi.print(); printf("\n");
8052 printf("rsi = "); _rsi.print(); printf("\n");
8053 printf("rbp, = "); _rbp.print(); printf("\n");
8054 printf("rsp = "); _rsp.print(); printf("\n");
8055 printf("\n");
8056 // control registers
8057 printf("flgs = "); _eflags.print(); printf("\n");
8058 }
8059 };
8060
8061
8062 class CPU_State {
8063 public:
8064 FPU_State _fpu_state;
8065 IU_State _iu_state;
8066
8067 void print() const {
8068 printf("--------------------------------------------------\n");
8069 _iu_state .print();
8070 printf("\n");
8071 _fpu_state.print();
8072 printf("--------------------------------------------------\n");
8073 }
8074
8075 };
8076
8077
8078 static void _print_CPU_state(CPU_State* state) {
8079 state->print();
8080 };
8081
8082
8083 void MacroAssembler::print_CPU_state() {
8084 push_CPU_state();
8085 push(rsp); // pass CPU state
8086 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
8087 addptr(rsp, wordSize); // discard argument
8088 pop_CPU_state();
8089 }
8090
8091
8092 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
8093 static int counter = 0;
8094 FPU_State* fs = &state->_fpu_state;
8095 counter++;
8096 // For leaf calls, only verify that the top few elements remain empty.
8097 // We only need 1 empty at the top for C2 code.
8098 if( stack_depth < 0 ) {
8099 if( fs->tag_for_st(7) != 3 ) {
8100 printf("FPR7 not empty\n");
8101 state->print();
8102 assert(false, "error");
8103 return false;
8104 }
8105 return true; // All other stack states do not matter
8106 }
8107
8108 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
8109 "bad FPU control word");
8110
8111 // compute stack depth
8112 int i = 0;
8113 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
8114 int d = i;
8115 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
8116 // verify findings
8117 if (i != FPU_State::number_of_registers) {
8118 // stack not contiguous
8119 printf("%s: stack not contiguous at ST%d\n", s, i);
8120 state->print();
8121 assert(false, "error");
8122 return false;
8123 }
8124 // check if computed stack depth corresponds to expected stack depth
8125 if (stack_depth < 0) {
8126 // expected stack depth is -stack_depth or less
8127 if (d > -stack_depth) {
8128 // too many elements on the stack
8129 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
8130 state->print();
8131 assert(false, "error");
8132 return false;
8133 }
8134 } else {
8135 // expected stack depth is stack_depth
8136 if (d != stack_depth) {
8137 // wrong stack depth
8138 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
8139 state->print();
8140 assert(false, "error");
8141 return false;
8142 }
8143 }
8144 // everything is cool
8145 return true;
8146 }
8147
8148
8149 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
8150 if (!VerifyFPU) return;
8151 push_CPU_state();
8152 push(rsp); // pass CPU state
8153 ExternalAddress msg((address) s);
8154 // pass message string s
8155 pushptr(msg.addr());
8156 push(stack_depth); // pass stack depth
8157 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
8158 addptr(rsp, 3 * wordSize); // discard arguments
8159 // check for error
8160 { Label L;
8161 testl(rax, rax);
8162 jcc(Assembler::notZero, L);
8163 int3(); // break if error condition
8164 bind(L);
8165 }
8166 pop_CPU_state();
8167 }
8168
8169 void MacroAssembler::load_klass(Register dst, Register src) {
8170 #ifdef _LP64
8171 if (UseCompressedOops) {
8172 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8173 decode_heap_oop_not_null(dst);
8174 } else
8175 #endif
8176 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8177 }
8178
8179 void MacroAssembler::load_prototype_header(Register dst, Register src) {
8180 #ifdef _LP64
8181 if (UseCompressedOops) {
8182 assert (Universe::heap() != NULL, "java heap should be initialized");
8183 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8184 if (Universe::narrow_oop_shift() != 0) {
8185 assert(Address::times_8 == LogMinObjAlignmentInBytes &&
8186 Address::times_8 == Universe::narrow_oop_shift(), "decode alg wrong");
8187 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8188 } else {
8189 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8190 }
8191 } else
8192 #endif
8193 {
8194 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8195 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8196 }
8197 }
8198
8199 void MacroAssembler::store_klass(Register dst, Register src) {
8200 #ifdef _LP64
8201 if (UseCompressedOops) {
8202 encode_heap_oop_not_null(src);
8203 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8204 } else
8205 #endif
8206 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8207 }
8208
8209 #ifdef _LP64
8210 void MacroAssembler::store_klass_gap(Register dst, Register src) {
8211 if (UseCompressedOops) {
8212 // Store to klass gap in destination
8213 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
8214 }
8215 }
8216
8217 void MacroAssembler::load_heap_oop(Register dst, Address src) {
8218 if (UseCompressedOops) {
8219 movl(dst, src);
8220 decode_heap_oop(dst);
8221 } else {
8222 movq(dst, src);
8223 }
8224 }
8225
8226 void MacroAssembler::store_heap_oop(Address dst, Register src) {
8227 if (UseCompressedOops) {
8228 assert(!dst.uses(src), "not enough registers");
8229 encode_heap_oop(src);
8230 movl(dst, src);
8231 } else {
8232 movq(dst, src);
8233 }
8234 }
8235
8236 // Used for storing NULLs.
8237 void MacroAssembler::store_heap_oop_null(Address dst) {
8238 if (UseCompressedOops) {
8239 movl(dst, (int32_t)NULL_WORD);
8240 } else {
8241 movslq(dst, (int32_t)NULL_WORD);
8242 }
8243 }
8244
8245 // Algorithm must match oop.inline.hpp encode_heap_oop.
8246 void MacroAssembler::encode_heap_oop(Register r) {
8247 assert (UseCompressedOops, "should be compressed");
8248 assert (Universe::heap() != NULL, "java heap should be initialized");
8249 if (Universe::narrow_oop_base() == NULL) {
8250 verify_oop(r, "broken oop in encode_heap_oop");
8251 if (Universe::narrow_oop_shift() != 0) {
8252 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8253 shrq(r, LogMinObjAlignmentInBytes);
8254 }
8255 return;
8256 }
8257 #ifdef ASSERT
8258 if (CheckCompressedOops) {
8259 Label ok;
8260 push(rscratch1); // cmpptr trashes rscratch1
8261 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8262 jcc(Assembler::equal, ok);
8263 stop("MacroAssembler::encode_heap_oop: heap base corrupted?");
8264 bind(ok);
8265 pop(rscratch1);
8266 }
8267 #endif
8268 verify_oop(r, "broken oop in encode_heap_oop");
8269 testq(r, r);
8270 cmovq(Assembler::equal, r, r12_heapbase);
8271 subq(r, r12_heapbase);
8272 shrq(r, LogMinObjAlignmentInBytes);
8273 }
8274
8275 void MacroAssembler::encode_heap_oop_not_null(Register r) {
8276 assert (UseCompressedOops, "should be compressed");
8277 assert (Universe::heap() != NULL, "java heap should be initialized");
8278 #ifdef ASSERT
8279 if (CheckCompressedOops) {
8280 Label ok;
8281 testq(r, r);
8282 jcc(Assembler::notEqual, ok);
8283 stop("null oop passed to encode_heap_oop_not_null");
8284 bind(ok);
8285 }
8286 #endif
8287 verify_oop(r, "broken oop in encode_heap_oop_not_null");
8288 if (Universe::narrow_oop_base() != NULL) {
8289 subq(r, r12_heapbase);
8290 }
8291 if (Universe::narrow_oop_shift() != 0) {
8292 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8293 shrq(r, LogMinObjAlignmentInBytes);
8294 }
8295 }
8296
8297 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
8298 assert (UseCompressedOops, "should be compressed");
8299 assert (Universe::heap() != NULL, "java heap should be initialized");
8300 #ifdef ASSERT
8301 if (CheckCompressedOops) {
8302 Label ok;
8303 testq(src, src);
8304 jcc(Assembler::notEqual, ok);
8305 stop("null oop passed to encode_heap_oop_not_null2");
8306 bind(ok);
8307 }
8308 #endif
8309 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
8310 if (dst != src) {
8311 movq(dst, src);
8312 }
8313 if (Universe::narrow_oop_base() != NULL) {
8314 subq(dst, r12_heapbase);
8315 }
8316 if (Universe::narrow_oop_shift() != 0) {
8317 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8318 shrq(dst, LogMinObjAlignmentInBytes);
8319 }
8320 }
8321
8322 void MacroAssembler::decode_heap_oop(Register r) {
8323 assert (UseCompressedOops, "should be compressed");
8324 assert (Universe::heap() != NULL, "java heap should be initialized");
8325 if (Universe::narrow_oop_base() == NULL) {
8326 if (Universe::narrow_oop_shift() != 0) {
8327 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8328 shlq(r, LogMinObjAlignmentInBytes);
8329 }
8330 verify_oop(r, "broken oop in decode_heap_oop");
8331 return;
8332 }
8333 #ifdef ASSERT
8334 if (CheckCompressedOops) {
8335 Label ok;
8336 push(rscratch1);
8337 cmpptr(r12_heapbase,
8338 ExternalAddress((address)Universe::narrow_oop_base_addr()));
8339 jcc(Assembler::equal, ok);
8340 stop("MacroAssembler::decode_heap_oop: heap base corrupted?");
8341 bind(ok);
8342 pop(rscratch1);
8343 }
8344 #endif
8345
8346 Label done;
8347 shlq(r, LogMinObjAlignmentInBytes);
8348 jccb(Assembler::equal, done);
8349 addq(r, r12_heapbase);
8350 #if 0
8351 // alternate decoding probably a wash.
8352 testq(r, r);
8353 jccb(Assembler::equal, done);
8354 leaq(r, Address(r12_heapbase, r, Address::times_8, 0));
8355 #endif
8356 bind(done);
8357 verify_oop(r, "broken oop in decode_heap_oop");
8358 }
8359
8360 void MacroAssembler::decode_heap_oop_not_null(Register r) {
8361 assert (UseCompressedOops, "should only be used for compressed headers");
8362 assert (Universe::heap() != NULL, "java heap should be initialized");
8363 // Cannot assert, unverified entry point counts instructions (see .ad file)
8364 // vtableStubs also counts instructions in pd_code_size_limit.
8365 // Also do not verify_oop as this is called by verify_oop.
8366 if (Universe::narrow_oop_shift() != 0) {
8367 assert (Address::times_8 == LogMinObjAlignmentInBytes &&
8368 Address::times_8 == Universe::narrow_oop_shift(), "decode alg wrong");
8369 // Don't use Shift since it modifies flags.
8370 leaq(r, Address(r12_heapbase, r, Address::times_8, 0));
8371 } else {
8372 assert (Universe::narrow_oop_base() == NULL, "sanity");
8373 }
8374 }
8375
8376 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
8377 assert (UseCompressedOops, "should only be used for compressed headers");
8378 assert (Universe::heap() != NULL, "java heap should be initialized");
8379 // Cannot assert, unverified entry point counts instructions (see .ad file)
8380 // vtableStubs also counts instructions in pd_code_size_limit.
8381 // Also do not verify_oop as this is called by verify_oop.
8382 if (Universe::narrow_oop_shift() != 0) {
8383 assert (Address::times_8 == LogMinObjAlignmentInBytes &&
8384 Address::times_8 == Universe::narrow_oop_shift(), "decode alg wrong");
8385 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
8386 } else if (dst != src) {
8387 assert (Universe::narrow_oop_base() == NULL, "sanity");
8388 movq(dst, src);
8389 }
8390 }
8391
8392 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
8393 assert (UseCompressedOops, "should only be used for compressed headers");
8394 assert (Universe::heap() != NULL, "java heap should be initialized");
8395 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8396 int oop_index = oop_recorder()->find_index(obj);
8397 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8398 mov_narrow_oop(dst, oop_index, rspec);
8399 }
8400
8401 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
8402 assert (UseCompressedOops, "should only be used for compressed headers");
8403 assert (Universe::heap() != NULL, "java heap should be initialized");
8404 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8405 int oop_index = oop_recorder()->find_index(obj);
8406 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8407 mov_narrow_oop(dst, oop_index, rspec);
8408 }
8409
8410 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
8411 assert (UseCompressedOops, "should only be used for compressed headers");
8412 assert (Universe::heap() != NULL, "java heap should be initialized");
8413 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8414 int oop_index = oop_recorder()->find_index(obj);
8415 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8416 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8417 }
8418
8419 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
8420 assert (UseCompressedOops, "should only be used for compressed headers");
8421 assert (Universe::heap() != NULL, "java heap should be initialized");
8422 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8423 int oop_index = oop_recorder()->find_index(obj);
8424 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8425 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8426 }
8427
8428 void MacroAssembler::reinit_heapbase() {
8429 if (UseCompressedOops) {
8430 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8431 }
8432 }
8433 #endif // _LP64
8434
8435 // IndexOf substring.
8436 void MacroAssembler::string_indexof(Register str1, Register str2,
8437 Register cnt1, Register cnt2, Register result,
8438 XMMRegister vec, Register tmp) {
8439 assert(UseSSE42Intrinsics, "SSE4.2 is required");
8440
8441 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
8442 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP;
8443
8444 push(str1); // string addr
8445 push(str2); // substr addr
8446 push(cnt2); // substr count
8447 jmpb(PREP_FOR_SCAN);
8448
8449 // Substr count saved at sp
8450 // Substr saved at sp+1*wordSize
8451 // String saved at sp+2*wordSize
8452
8453 // Reload substr for rescan
8454 bind(RELOAD_SUBSTR);
8455 movl(cnt2, Address(rsp, 0));
8456 movptr(str2, Address(rsp, wordSize));
8457 // We came here after the beginninig of the substring was
8458 // matched but the rest of it was not so we need to search
8459 // again. Start from the next element after the previous match.
8460 subptr(str1, result); // Restore counter
8461 shrl(str1, 1);
8462 addl(cnt1, str1);
8463 decrementl(cnt1);
8464 lea(str1, Address(result, 2)); // Reload string
8465
8466 // Load substr
8467 bind(PREP_FOR_SCAN);
8468 movdqu(vec, Address(str2, 0));
8469 addl(cnt1, 8); // prime the loop
8470 subptr(str1, 16);
8471
8472 // Scan string for substr in 16-byte vectors
8473 bind(SCAN_TO_SUBSTR);
8474 subl(cnt1, 8);
8475 addptr(str1, 16);
8476
8477 // pcmpestri
8478 // inputs:
8479 // xmm - substring
8480 // rax - substring length (elements count)
8481 // mem - scaned string
8482 // rdx - string length (elements count)
8483 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
8484 // outputs:
8485 // rcx - matched index in string
8486 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
8487
8488 pcmpestri(vec, Address(str1, 0), 0x0d);
8489 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
8490 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
8491
8492 // Fallthrough: found a potential substr
8493
8494 // Make sure string is still long enough
8495 subl(cnt1, tmp);
8496 cmpl(cnt1, cnt2);
8497 jccb(Assembler::negative, RET_NOT_FOUND);
8498 // Compute start addr of substr
8499 lea(str1, Address(str1, tmp, Address::times_2));
8500 movptr(result, str1); // save
8501
8502 // Compare potential substr
8503 addl(cnt1, 8); // prime the loop
8504 addl(cnt2, 8);
8505 subptr(str1, 16);
8506 subptr(str2, 16);
8507
8508 // Scan 16-byte vectors of string and substr
8509 bind(SCAN_SUBSTR);
8510 subl(cnt1, 8);
8511 subl(cnt2, 8);
8512 addptr(str1, 16);
8513 addptr(str2, 16);
8514 movdqu(vec, Address(str2, 0));
8515 pcmpestri(vec, Address(str1, 0), 0x0d);
8516 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
8517 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
8518
8519 // Compute substr offset
8520 subptr(result, Address(rsp, 2*wordSize));
8521 shrl(result, 1); // index
8522 jmpb(CLEANUP);
8523
8524 bind(RET_NOT_FOUND);
8525 movl(result, -1);
8526
8527 bind(CLEANUP);
8528 addptr(rsp, 3*wordSize);
8529 }
8530
8531 // Compare strings.
8532 void MacroAssembler::string_compare(Register str1, Register str2,
8533 Register cnt1, Register cnt2, Register result,
8534 XMMRegister vec1, XMMRegister vec2) {
8535 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
8536
8537 // Compute the minimum of the string lengths and the
8538 // difference of the string lengths (stack).
8539 // Do the conditional move stuff
8540 movl(result, cnt1);
8541 subl(cnt1, cnt2);
8542 push(cnt1);
8543 if (VM_Version::supports_cmov()) {
8544 cmovl(Assembler::lessEqual, cnt2, result);
8545 } else {
8546 Label GT_LABEL;
8547 jccb(Assembler::greater, GT_LABEL);
8548 movl(cnt2, result);
8549 bind(GT_LABEL);
8550 }
8551
8552 // Is the minimum length zero?
8553 testl(cnt2, cnt2);
8554 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8555
8556 // Load first characters
8557 load_unsigned_short(result, Address(str1, 0));
8558 load_unsigned_short(cnt1, Address(str2, 0));
8559
8560 // Compare first characters
8561 subl(result, cnt1);
8562 jcc(Assembler::notZero, POP_LABEL);
8563 decrementl(cnt2);
8564 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8565
8566 {
8567 // Check after comparing first character to see if strings are equivalent
8568 Label LSkip2;
8569 // Check if the strings start at same location
8570 cmpptr(str1, str2);
8571 jccb(Assembler::notEqual, LSkip2);
8572
8573 // Check if the length difference is zero (from stack)
8574 cmpl(Address(rsp, 0), 0x0);
8575 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
8576
8577 // Strings might not be equivalent
8578 bind(LSkip2);
8579 }
8580
8581 // Advance to next character
8582 addptr(str1, 2);
8583 addptr(str2, 2);
8584
8585 if (UseSSE42Intrinsics) {
8586 // With SSE4.2, use double quad vector compare
8587 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8588 // Setup to compare 16-byte vectors
8589 movl(cnt1, cnt2);
8590 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count
8591 andl(cnt1, 0x00000007); // cnt1 holds the tail count
8592 testl(cnt2, cnt2);
8593 jccb(Assembler::zero, COMPARE_TAIL);
8594
8595 lea(str2, Address(str2, cnt2, Address::times_2));
8596 lea(str1, Address(str1, cnt2, Address::times_2));
8597 negptr(cnt2);
8598
8599 bind(COMPARE_VECTORS);
8600 movdqu(vec1, Address(str1, cnt2, Address::times_2));
8601 movdqu(vec2, Address(str2, cnt2, Address::times_2));
8602 pxor(vec1, vec2);
8603 ptest(vec1, vec1);
8604 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
8605 addptr(cnt2, 8);
8606 jcc(Assembler::notZero, COMPARE_VECTORS);
8607 jmpb(COMPARE_TAIL);
8608
8609 // Mismatched characters in the vectors
8610 bind(VECTOR_NOT_EQUAL);
8611 lea(str1, Address(str1, cnt2, Address::times_2));
8612 lea(str2, Address(str2, cnt2, Address::times_2));
8613 movl(cnt1, 8);
8614
8615 // Compare tail (< 8 chars), or rescan last vectors to
8616 // find 1st mismatched characters
8617 bind(COMPARE_TAIL);
8618 testl(cnt1, cnt1);
8619 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8620 movl(cnt2, cnt1);
8621 // Fallthru to tail compare
8622 }
8623
8624 // Shift str2 and str1 to the end of the arrays, negate min
8625 lea(str1, Address(str1, cnt2, Address::times_2, 0));
8626 lea(str2, Address(str2, cnt2, Address::times_2, 0));
8627 negptr(cnt2);
8628
8629 // Compare the rest of the characters
8630 bind(WHILE_HEAD_LABEL);
8631 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0));
8632 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0));
8633 subl(result, cnt1);
8634 jccb(Assembler::notZero, POP_LABEL);
8635 increment(cnt2);
8636 jcc(Assembler::notZero, WHILE_HEAD_LABEL);
8637
8638 // Strings are equal up to min length. Return the length difference.
8639 bind(LENGTH_DIFF_LABEL);
8640 pop(result);
8641 jmpb(DONE_LABEL);
8642
8643 // Discard the stored length difference
8644 bind(POP_LABEL);
8645 addptr(rsp, wordSize);
8646
8647 // That's it
8648 bind(DONE_LABEL);
8649 }
8650
8651 // Compare char[] arrays aligned to 4 bytes or substrings.
8652 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8653 Register limit, Register result, Register chr,
8654 XMMRegister vec1, XMMRegister vec2) {
8655 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
8656
8657 int length_offset = arrayOopDesc::length_offset_in_bytes();
8658 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
8659
8660 // Check the input args
8661 cmpptr(ary1, ary2);
8662 jcc(Assembler::equal, TRUE_LABEL);
8663
8664 if (is_array_equ) {
8665 // Need additional checks for arrays_equals.
8666 testptr(ary1, ary1);
8667 jcc(Assembler::zero, FALSE_LABEL);
8668 testptr(ary2, ary2);
8669 jcc(Assembler::zero, FALSE_LABEL);
8670
8671 // Check the lengths
8672 movl(limit, Address(ary1, length_offset));
8673 cmpl(limit, Address(ary2, length_offset));
8674 jcc(Assembler::notEqual, FALSE_LABEL);
8675 }
8676
8677 // count == 0
8678 testl(limit, limit);
8679 jcc(Assembler::zero, TRUE_LABEL);
8680
8681 if (is_array_equ) {
8682 // Load array address
8683 lea(ary1, Address(ary1, base_offset));
8684 lea(ary2, Address(ary2, base_offset));
8685 }
8686
8687 shll(limit, 1); // byte count != 0
8688 movl(result, limit); // copy
8689
8690 if (UseSSE42Intrinsics) {
8691 // With SSE4.2, use double quad vector compare
8692 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8693 // Compare 16-byte vectors
8694 andl(result, 0x0000000e); // tail count (in bytes)
8695 andl(limit, 0xfffffff0); // vector count (in bytes)
8696 jccb(Assembler::zero, COMPARE_TAIL);
8697
8698 lea(ary1, Address(ary1, limit, Address::times_1));
8699 lea(ary2, Address(ary2, limit, Address::times_1));
8700 negptr(limit);
8701
8702 bind(COMPARE_WIDE_VECTORS);
8703 movdqu(vec1, Address(ary1, limit, Address::times_1));
8704 movdqu(vec2, Address(ary2, limit, Address::times_1));
8705 pxor(vec1, vec2);
8706 ptest(vec1, vec1);
8707 jccb(Assembler::notZero, FALSE_LABEL);
8708 addptr(limit, 16);
8709 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8710
8711 bind(COMPARE_TAIL); // limit is zero
8712 movl(limit, result);
8713 // Fallthru to tail compare
8714 }
8715
8716 // Compare 4-byte vectors
8717 andl(limit, 0xfffffffc); // vector count (in bytes)
8718 jccb(Assembler::zero, COMPARE_CHAR);
8719
8720 lea(ary1, Address(ary1, limit, Address::times_1));
8721 lea(ary2, Address(ary2, limit, Address::times_1));
8722 negptr(limit);
8723
8724 bind(COMPARE_VECTORS);
8725 movl(chr, Address(ary1, limit, Address::times_1));
8726 cmpl(chr, Address(ary2, limit, Address::times_1));
8727 jccb(Assembler::notEqual, FALSE_LABEL);
8728 addptr(limit, 4);
8729 jcc(Assembler::notZero, COMPARE_VECTORS);
8730
8731 // Compare trailing char (final 2 bytes), if any
8732 bind(COMPARE_CHAR);
8733 testl(result, 0x2); // tail char
8734 jccb(Assembler::zero, TRUE_LABEL);
8735 load_unsigned_short(chr, Address(ary1, 0));
8736 load_unsigned_short(limit, Address(ary2, 0));
8737 cmpl(chr, limit);
8738 jccb(Assembler::notEqual, FALSE_LABEL);
8739
8740 bind(TRUE_LABEL);
8741 movl(result, 1); // return true
8742 jmpb(DONE);
8743
8744 bind(FALSE_LABEL);
8745 xorl(result, result); // return false
8746
8747 // That's it
8748 bind(DONE);
8749 }
8750
8751 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8752 switch (cond) {
8753 // Note some conditions are synonyms for others
8754 case Assembler::zero: return Assembler::notZero;
8755 case Assembler::notZero: return Assembler::zero;
8756 case Assembler::less: return Assembler::greaterEqual;
8757 case Assembler::lessEqual: return Assembler::greater;
8758 case Assembler::greater: return Assembler::lessEqual;
8759 case Assembler::greaterEqual: return Assembler::less;
8760 case Assembler::below: return Assembler::aboveEqual;
8761 case Assembler::belowEqual: return Assembler::above;
8762 case Assembler::above: return Assembler::belowEqual;
8763 case Assembler::aboveEqual: return Assembler::below;
8764 case Assembler::overflow: return Assembler::noOverflow;
8765 case Assembler::noOverflow: return Assembler::overflow;
8766 case Assembler::negative: return Assembler::positive;
8767 case Assembler::positive: return Assembler::negative;
8768 case Assembler::parity: return Assembler::noParity;
8769 case Assembler::noParity: return Assembler::parity;
8770 }
8771 ShouldNotReachHere(); return Assembler::overflow;
8772 }
8773
8774 SkipIfEqual::SkipIfEqual(
8775 MacroAssembler* masm, const bool* flag_addr, bool value) {
8776 _masm = masm;
8777 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8778 _masm->jcc(Assembler::equal, _label);
8779 }
8780
8781 SkipIfEqual::~SkipIfEqual() {
8782 _masm->bind(_label);
8783 }