1 /* 2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25 # include "incls/_precompiled.incl" 26 # include "incls/_c1_LIRAssembler_x86.cpp.incl" 27 28 29 // These masks are used to provide 128-bit aligned bitmasks to the XMM 30 // instructions, to allow sign-masking or sign-bit flipping. They allow 31 // fast versions of NegF/NegD and AbsF/AbsD. 32 33 // Note: 'double' and 'long long' have 32-bits alignment on x86. 34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 36 // of 128-bits operands for SSE instructions. 37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); 38 // Store the value to a 128-bits operand. 39 operand[0] = lo; 40 operand[1] = hi; 41 return operand; 42 } 43 44 // Buffer for 128-bits masks used by SSE instructions. 45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 46 47 // Static initialization during VM startup. 48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 52 53 54 55 NEEDS_CLEANUP // remove this definitions ? 56 const Register IC_Klass = rax; // where the IC klass is cached 57 const Register SYNC_header = rax; // synchronization header 58 const Register SHIFT_count = rcx; // where count for shift operations must be 59 60 #define __ _masm-> 61 62 63 static void select_different_registers(Register preserve, 64 Register extra, 65 Register &tmp1, 66 Register &tmp2) { 67 if (tmp1 == preserve) { 68 assert_different_registers(tmp1, tmp2, extra); 69 tmp1 = extra; 70 } else if (tmp2 == preserve) { 71 assert_different_registers(tmp1, tmp2, extra); 72 tmp2 = extra; 73 } 74 assert_different_registers(preserve, tmp1, tmp2); 75 } 76 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2, 83 Register &tmp3) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, tmp3, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, tmp3, extra); 89 tmp2 = extra; 90 } else if (tmp3 == preserve) { 91 assert_different_registers(tmp1, tmp2, tmp3, extra); 92 tmp3 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); 95 } 96 97 98 99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 100 if (opr->is_constant()) { 101 LIR_Const* constant = opr->as_constant_ptr(); 102 switch (constant->type()) { 103 case T_INT: { 104 return true; 105 } 106 107 default: 108 return false; 109 } 110 } 111 return false; 112 } 113 114 115 LIR_Opr LIR_Assembler::receiverOpr() { 116 return FrameMap::receiver_opr; 117 } 118 119 LIR_Opr LIR_Assembler::incomingReceiverOpr() { 120 return receiverOpr(); 121 } 122 123 LIR_Opr LIR_Assembler::osrBufferPointer() { 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 125 } 126 127 //--------------fpu register translations----------------------- 128 129 130 address LIR_Assembler::float_constant(float f) { 131 address const_addr = __ float_constant(f); 132 if (const_addr == NULL) { 133 bailout("const section overflow"); 134 return __ code()->consts()->start(); 135 } else { 136 return const_addr; 137 } 138 } 139 140 141 address LIR_Assembler::double_constant(double d) { 142 address const_addr = __ double_constant(d); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 void LIR_Assembler::set_24bit_FPU() { 153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 154 } 155 156 void LIR_Assembler::reset_FPU() { 157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 158 } 159 160 void LIR_Assembler::fpop() { 161 __ fpop(); 162 } 163 164 void LIR_Assembler::fxch(int i) { 165 __ fxch(i); 166 } 167 168 void LIR_Assembler::fld(int i) { 169 __ fld_s(i); 170 } 171 172 void LIR_Assembler::ffree(int i) { 173 __ ffree(i); 174 } 175 176 void LIR_Assembler::breakpoint() { 177 __ int3(); 178 } 179 180 void LIR_Assembler::push(LIR_Opr opr) { 181 if (opr->is_single_cpu()) { 182 __ push_reg(opr->as_register()); 183 } else if (opr->is_double_cpu()) { 184 NOT_LP64(__ push_reg(opr->as_register_hi())); 185 __ push_reg(opr->as_register_lo()); 186 } else if (opr->is_stack()) { 187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 188 } else if (opr->is_constant()) { 189 LIR_Const* const_opr = opr->as_constant_ptr(); 190 if (const_opr->type() == T_OBJECT) { 191 __ push_oop(const_opr->as_jobject()); 192 } else if (const_opr->type() == T_INT) { 193 __ push_jint(const_opr->as_jint()); 194 } else { 195 ShouldNotReachHere(); 196 } 197 198 } else { 199 ShouldNotReachHere(); 200 } 201 } 202 203 void LIR_Assembler::pop(LIR_Opr opr) { 204 if (opr->is_single_cpu()) { 205 __ pop_reg(opr->as_register()); 206 } else { 207 ShouldNotReachHere(); 208 } 209 } 210 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 212 return addr->base()->is_illegal() && addr->index()->is_illegal(); 213 } 214 215 //------------------------------------------- 216 217 Address LIR_Assembler::as_Address(LIR_Address* addr) { 218 return as_Address(addr, rscratch1); 219 } 220 221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 222 if (addr->base()->is_illegal()) { 223 assert(addr->index()->is_illegal(), "must be illegal too"); 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 225 if (! __ reachable(laddr)) { 226 __ movptr(tmp, laddr.addr()); 227 Address res(tmp, 0); 228 return res; 229 } else { 230 return __ as_Address(laddr); 231 } 232 } 233 234 Register base = addr->base()->as_pointer_register(); 235 236 if (addr->index()->is_illegal()) { 237 return Address( base, addr->disp()); 238 } else if (addr->index()->is_cpu_register()) { 239 Register index = addr->index()->as_pointer_register(); 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 241 } else if (addr->index()->is_constant()) { 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 243 assert(Assembler::is_simm32(addr_offset), "must be"); 244 245 return Address(base, addr_offset); 246 } else { 247 Unimplemented(); 248 return Address(); 249 } 250 } 251 252 253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 254 Address base = as_Address(addr); 255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 256 } 257 258 259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 260 return as_Address(addr); 261 } 262 263 264 void LIR_Assembler::osr_entry() { 265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 266 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 267 ValueStack* entry_state = osr_entry->state(); 268 int number_of_locks = entry_state->locks_size(); 269 270 // we jump here if osr happens with the interpreter 271 // state set up to continue at the beginning of the 272 // loop that triggered osr - in particular, we have 273 // the following registers setup: 274 // 275 // rcx: osr buffer 276 // 277 278 // build frame 279 ciMethod* m = compilation()->method(); 280 __ build_frame(initial_frame_size_in_bytes()); 281 282 // OSR buffer is 283 // 284 // locals[nlocals-1..0] 285 // monitors[0..number_of_locks] 286 // 287 // locals is a direct copy of the interpreter frame so in the osr buffer 288 // so first slot in the local array is the last local from the interpreter 289 // and last slot is local[0] (receiver) from the interpreter 290 // 291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 293 // in the interpreter frame (the method lock if a sync method) 294 295 // Initialize monitors in the compiled activation. 296 // rcx: pointer to osr buffer 297 // 298 // All other registers are dead at this point and the locals will be 299 // copied into place by code emitted in the IR. 300 301 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 303 int monitor_offset = BytesPerWord * method()->max_locals() + 304 (2 * BytesPerWord) * (number_of_locks - 1); 305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 306 // the OSR buffer using 2 word entries: first the lock and then 307 // the oop. 308 for (int i = 0; i < number_of_locks; i++) { 309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 310 #ifdef ASSERT 311 // verify the interpreter's monitor has a non-null object 312 { 313 Label L; 314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 315 __ jcc(Assembler::notZero, L); 316 __ stop("locked object is NULL"); 317 __ bind(L); 318 } 319 #endif 320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 323 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 324 } 325 } 326 } 327 328 329 // inline cache check; done before the frame is built. 330 int LIR_Assembler::check_icache() { 331 Register receiver = FrameMap::receiver_opr->as_register(); 332 Register ic_klass = IC_Klass; 333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 334 335 if (!VerifyOops) { 336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 338 __ nop(); 339 } 340 } 341 int offset = __ offset(); 342 __ inline_cache_check(receiver, IC_Klass); 343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); 344 if (VerifyOops) { 345 // force alignment after the cache check. 346 // It's been verified to be aligned if !VerifyOops 347 __ align(CodeEntryAlignment); 348 } 349 return offset; 350 } 351 352 353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 354 jobject o = NULL; 355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 356 __ movoop(reg, o); 357 patching_epilog(patch, lir_patch_normal, reg, info); 358 } 359 360 361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { 362 if (exception->is_valid()) { 363 // preserve exception 364 // note: the monitor_exit runtime call is a leaf routine 365 // and cannot block => no GC can happen 366 // The slow case (MonitorAccessStub) uses the first two stack slots 367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] 368 __ movptr (Address(rsp, 2*wordSize), exception); 369 } 370 371 Register obj_reg = obj_opr->as_register(); 372 Register lock_reg = lock_opr->as_register(); 373 374 // setup registers (lock_reg must be rax, for lock_object) 375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); 376 Register hdr = lock_reg; 377 assert(new_hdr == SYNC_header, "wrong register"); 378 lock_reg = new_hdr; 379 // compute pointer to BasicLock 380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); 381 __ lea(lock_reg, lock_addr); 382 // unlock object 383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); 384 // _slow_case_stubs->append(slow_case); 385 // temporary fix: must be created after exceptionhandler, therefore as call stub 386 _slow_case_stubs->append(slow_case); 387 if (UseFastLocking) { 388 // try inlined fast unlocking first, revert to slow locking if it fails 389 // note: lock_reg points to the displaced header since the displaced header offset is 0! 390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 392 } else { 393 // always do slow unlocking 394 // note: the slow unlocking code could be inlined here, however if we use 395 // slow unlocking, speed doesn't matter anyway and this solution is 396 // simpler and requires less duplicated code - additionally, the 397 // slow unlocking code is the same in either case which simplifies 398 // debugging 399 __ jmp(*slow_case->entry()); 400 } 401 // done 402 __ bind(*slow_case->continuation()); 403 404 if (exception->is_valid()) { 405 // restore exception 406 __ movptr (exception, Address(rsp, 2 * wordSize)); 407 } 408 } 409 410 // This specifies the rsp decrement needed to build the frame 411 int LIR_Assembler::initial_frame_size_in_bytes() { 412 // if rounding, must let FrameMap know! 413 414 // The frame_map records size in slots (32bit word) 415 416 // subtract two words to account for return address and link 417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 418 } 419 420 421 int LIR_Assembler::emit_exception_handler() { 422 // if the last instruction is a call (typically to do a throw which 423 // is coming at the end after block reordering) the return address 424 // must still point into the code area in order to avoid assertion 425 // failures when searching for the corresponding bci => add a nop 426 // (was bug 5/14/1999 - gri) 427 __ nop(); 428 429 // generate code for exception handler 430 address handler_base = __ start_a_stub(exception_handler_size); 431 if (handler_base == NULL) { 432 // not enough space left for the handler 433 bailout("exception handler overflow"); 434 return -1; 435 } 436 437 int offset = code_offset(); 438 439 // the exception oop and pc are in rax, and rdx 440 // no other registers need to be preserved, so invalidate them 441 __ invalidate_registers(false, true, true, false, true, true); 442 443 // check that there is really an exception 444 __ verify_not_null_oop(rax); 445 446 // search an exception handler (rax: exception oop, rdx: throwing pc) 447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); 448 449 __ stop("should not reach here"); 450 451 assert(code_offset() - offset <= exception_handler_size, "overflow"); 452 __ end_a_stub(); 453 454 return offset; 455 } 456 457 458 // Emit the code to remove the frame from the stack in the exception 459 // unwind path. 460 int LIR_Assembler::emit_unwind_handler() { 461 #ifndef PRODUCT 462 if (CommentedAssembly) { 463 _masm->block_comment("Unwind handler"); 464 } 465 #endif 466 467 int offset = code_offset(); 468 469 // Fetch the exception from TLS and clear out exception related thread state 470 __ get_thread(rsi); 471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); 472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); 473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 474 475 __ bind(_unwind_handler_entry); 476 __ verify_not_null_oop(rax); 477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 478 __ mov(rsi, rax); // Preserve the exception 479 } 480 481 // Preform needed unlocking 482 MonitorExitStub* stub = NULL; 483 if (method()->is_synchronized()) { 484 monitor_address(0, FrameMap::rax_opr); 485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 486 __ unlock_object(rdi, rbx, rax, *stub->entry()); 487 __ bind(*stub->continuation()); 488 } 489 490 if (compilation()->env()->dtrace_method_probes()) { 491 __ movoop(Address(rsp, 0), method()->constant_encoding()); 492 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 493 } 494 495 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 496 __ mov(rax, rsi); // Restore the exception 497 } 498 499 // remove the activation and dispatch to the unwind handler 500 __ remove_frame(initial_frame_size_in_bytes()); 501 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 502 503 // Emit the slow path assembly 504 if (stub != NULL) { 505 stub->emit_code(this); 506 } 507 508 return offset; 509 } 510 511 512 int LIR_Assembler::emit_deopt_handler() { 513 // if the last instruction is a call (typically to do a throw which 514 // is coming at the end after block reordering) the return address 515 // must still point into the code area in order to avoid assertion 516 // failures when searching for the corresponding bci => add a nop 517 // (was bug 5/14/1999 - gri) 518 __ nop(); 519 520 // generate code for exception handler 521 address handler_base = __ start_a_stub(deopt_handler_size); 522 if (handler_base == NULL) { 523 // not enough space left for the handler 524 bailout("deopt handler overflow"); 525 return -1; 526 } 527 528 int offset = code_offset(); 529 InternalAddress here(__ pc()); 530 531 __ pushptr(here.addr()); 532 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 533 534 assert(code_offset() - offset <= deopt_handler_size, "overflow"); 535 __ end_a_stub(); 536 537 return offset; 538 } 539 540 541 // This is the fast version of java.lang.String.compare; it has not 542 // OSR-entry and therefore, we generate a slow version for OSR's 543 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 544 __ movptr (rbx, rcx); // receiver is in rcx 545 __ movptr (rax, arg1->as_register()); 546 547 // Get addresses of first characters from both Strings 548 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 549 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 550 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 551 552 553 // rbx, may be NULL 554 add_debug_info_for_null_check_here(info); 555 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 556 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 557 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 558 559 // compute minimum length (in rax) and difference of lengths (on top of stack) 560 if (VM_Version::supports_cmov()) { 561 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 562 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 563 __ mov (rcx, rbx); 564 __ subptr (rbx, rax); // subtract lengths 565 __ push (rbx); // result 566 __ cmov (Assembler::lessEqual, rax, rcx); 567 } else { 568 Label L; 569 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 570 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); 571 __ mov (rax, rbx); 572 __ subptr (rbx, rcx); 573 __ push (rbx); 574 __ jcc (Assembler::lessEqual, L); 575 __ mov (rax, rcx); 576 __ bind (L); 577 } 578 // is minimum length 0? 579 Label noLoop, haveResult; 580 __ testptr (rax, rax); 581 __ jcc (Assembler::zero, noLoop); 582 583 // compare first characters 584 __ load_unsigned_short(rcx, Address(rdi, 0)); 585 __ load_unsigned_short(rbx, Address(rsi, 0)); 586 __ subl(rcx, rbx); 587 __ jcc(Assembler::notZero, haveResult); 588 // starting loop 589 __ decrement(rax); // we already tested index: skip one 590 __ jcc(Assembler::zero, noLoop); 591 592 // set rsi.edi to the end of the arrays (arrays have same length) 593 // negate the index 594 595 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 596 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 597 __ negptr(rax); 598 599 // compare the strings in a loop 600 601 Label loop; 602 __ align(wordSize); 603 __ bind(loop); 604 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); 605 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); 606 __ subl(rcx, rbx); 607 __ jcc(Assembler::notZero, haveResult); 608 __ increment(rax); 609 __ jcc(Assembler::notZero, loop); 610 611 // strings are equal up to min length 612 613 __ bind(noLoop); 614 __ pop(rax); 615 return_op(LIR_OprFact::illegalOpr); 616 617 __ bind(haveResult); 618 // leave instruction is going to discard the TOS value 619 __ mov (rax, rcx); // result of call is in rax, 620 } 621 622 623 void LIR_Assembler::return_op(LIR_Opr result) { 624 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 625 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 626 assert(result->fpu() == 0, "result must already be on TOS"); 627 } 628 629 // Pop the stack before the safepoint code 630 __ remove_frame(initial_frame_size_in_bytes()); 631 632 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 633 634 // Note: we do not need to round double result; float result has the right precision 635 // the poll sets the condition code, but no data registers 636 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 637 relocInfo::poll_return_type); 638 639 // NOTE: the requires that the polling page be reachable else the reloc 640 // goes to the movq that loads the address and not the faulting instruction 641 // which breaks the signal handler code 642 643 __ test32(rax, polling_page); 644 645 __ ret(0); 646 } 647 648 649 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 650 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 651 relocInfo::poll_type); 652 653 if (info != NULL) { 654 add_debug_info_for_branch(info); 655 } else { 656 ShouldNotReachHere(); 657 } 658 659 int offset = __ offset(); 660 661 // NOTE: the requires that the polling page be reachable else the reloc 662 // goes to the movq that loads the address and not the faulting instruction 663 // which breaks the signal handler code 664 665 __ test32(rax, polling_page); 666 return offset; 667 } 668 669 670 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 671 if (from_reg != to_reg) __ mov(to_reg, from_reg); 672 } 673 674 void LIR_Assembler::swap_reg(Register a, Register b) { 675 __ xchgptr(a, b); 676 } 677 678 679 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 680 assert(src->is_constant(), "should not call otherwise"); 681 assert(dest->is_register(), "should not call otherwise"); 682 LIR_Const* c = src->as_constant_ptr(); 683 684 switch (c->type()) { 685 case T_INT: 686 case T_ADDRESS: { 687 assert(patch_code == lir_patch_none, "no patching handled here"); 688 __ movl(dest->as_register(), c->as_jint()); 689 break; 690 } 691 692 case T_LONG: { 693 assert(patch_code == lir_patch_none, "no patching handled here"); 694 #ifdef _LP64 695 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 696 #else 697 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 698 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 699 #endif // _LP64 700 break; 701 } 702 703 case T_OBJECT: { 704 if (patch_code != lir_patch_none) { 705 jobject2reg_with_patching(dest->as_register(), info); 706 } else { 707 __ movoop(dest->as_register(), c->as_jobject()); 708 } 709 break; 710 } 711 712 case T_FLOAT: { 713 if (dest->is_single_xmm()) { 714 if (c->is_zero_float()) { 715 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 716 } else { 717 __ movflt(dest->as_xmm_float_reg(), 718 InternalAddress(float_constant(c->as_jfloat()))); 719 } 720 } else { 721 assert(dest->is_single_fpu(), "must be"); 722 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 723 if (c->is_zero_float()) { 724 __ fldz(); 725 } else if (c->is_one_float()) { 726 __ fld1(); 727 } else { 728 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 729 } 730 } 731 break; 732 } 733 734 case T_DOUBLE: { 735 if (dest->is_double_xmm()) { 736 if (c->is_zero_double()) { 737 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 738 } else { 739 __ movdbl(dest->as_xmm_double_reg(), 740 InternalAddress(double_constant(c->as_jdouble()))); 741 } 742 } else { 743 assert(dest->is_double_fpu(), "must be"); 744 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 745 if (c->is_zero_double()) { 746 __ fldz(); 747 } else if (c->is_one_double()) { 748 __ fld1(); 749 } else { 750 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 751 } 752 } 753 break; 754 } 755 756 default: 757 ShouldNotReachHere(); 758 } 759 } 760 761 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 762 assert(src->is_constant(), "should not call otherwise"); 763 assert(dest->is_stack(), "should not call otherwise"); 764 LIR_Const* c = src->as_constant_ptr(); 765 766 switch (c->type()) { 767 case T_INT: // fall through 768 case T_FLOAT: 769 case T_ADDRESS: 770 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 771 break; 772 773 case T_OBJECT: 774 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 775 break; 776 777 case T_LONG: // fall through 778 case T_DOUBLE: 779 #ifdef _LP64 780 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 781 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 782 #else 783 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 784 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 785 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 786 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 787 #endif // _LP64 788 break; 789 790 default: 791 ShouldNotReachHere(); 792 } 793 } 794 795 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { 796 assert(src->is_constant(), "should not call otherwise"); 797 assert(dest->is_address(), "should not call otherwise"); 798 LIR_Const* c = src->as_constant_ptr(); 799 LIR_Address* addr = dest->as_address_ptr(); 800 801 int null_check_here = code_offset(); 802 switch (type) { 803 case T_INT: // fall through 804 case T_FLOAT: 805 case T_ADDRESS: 806 __ movl(as_Address(addr), c->as_jint_bits()); 807 break; 808 809 case T_OBJECT: // fall through 810 case T_ARRAY: 811 if (c->as_jobject() == NULL) { 812 __ movptr(as_Address(addr), NULL_WORD); 813 } else { 814 if (is_literal_address(addr)) { 815 ShouldNotReachHere(); 816 __ movoop(as_Address(addr, noreg), c->as_jobject()); 817 } else { 818 #ifdef _LP64 819 __ movoop(rscratch1, c->as_jobject()); 820 null_check_here = code_offset(); 821 __ movptr(as_Address_lo(addr), rscratch1); 822 #else 823 __ movoop(as_Address(addr), c->as_jobject()); 824 #endif 825 } 826 } 827 break; 828 829 case T_LONG: // fall through 830 case T_DOUBLE: 831 #ifdef _LP64 832 if (is_literal_address(addr)) { 833 ShouldNotReachHere(); 834 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 835 } else { 836 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 837 null_check_here = code_offset(); 838 __ movptr(as_Address_lo(addr), r10); 839 } 840 #else 841 // Always reachable in 32bit so this doesn't produce useless move literal 842 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 843 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 844 #endif // _LP64 845 break; 846 847 case T_BOOLEAN: // fall through 848 case T_BYTE: 849 __ movb(as_Address(addr), c->as_jint() & 0xFF); 850 break; 851 852 case T_CHAR: // fall through 853 case T_SHORT: 854 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 855 break; 856 857 default: 858 ShouldNotReachHere(); 859 }; 860 861 if (info != NULL) { 862 add_debug_info_for_null_check(null_check_here, info); 863 } 864 } 865 866 867 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 868 assert(src->is_register(), "should not call otherwise"); 869 assert(dest->is_register(), "should not call otherwise"); 870 871 // move between cpu-registers 872 if (dest->is_single_cpu()) { 873 #ifdef _LP64 874 if (src->type() == T_LONG) { 875 // Can do LONG -> OBJECT 876 move_regs(src->as_register_lo(), dest->as_register()); 877 return; 878 } 879 #endif 880 assert(src->is_single_cpu(), "must match"); 881 if (src->type() == T_OBJECT) { 882 __ verify_oop(src->as_register()); 883 } 884 move_regs(src->as_register(), dest->as_register()); 885 886 } else if (dest->is_double_cpu()) { 887 #ifdef _LP64 888 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 889 // Surprising to me but we can see move of a long to t_object 890 __ verify_oop(src->as_register()); 891 move_regs(src->as_register(), dest->as_register_lo()); 892 return; 893 } 894 #endif 895 assert(src->is_double_cpu(), "must match"); 896 Register f_lo = src->as_register_lo(); 897 Register f_hi = src->as_register_hi(); 898 Register t_lo = dest->as_register_lo(); 899 Register t_hi = dest->as_register_hi(); 900 #ifdef _LP64 901 assert(f_hi == f_lo, "must be same"); 902 assert(t_hi == t_lo, "must be same"); 903 move_regs(f_lo, t_lo); 904 #else 905 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 906 907 908 if (f_lo == t_hi && f_hi == t_lo) { 909 swap_reg(f_lo, f_hi); 910 } else if (f_hi == t_lo) { 911 assert(f_lo != t_hi, "overwriting register"); 912 move_regs(f_hi, t_hi); 913 move_regs(f_lo, t_lo); 914 } else { 915 assert(f_hi != t_lo, "overwriting register"); 916 move_regs(f_lo, t_lo); 917 move_regs(f_hi, t_hi); 918 } 919 #endif // LP64 920 921 // special moves from fpu-register to xmm-register 922 // necessary for method results 923 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 924 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 925 __ fld_s(Address(rsp, 0)); 926 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 927 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 928 __ fld_d(Address(rsp, 0)); 929 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 930 __ fstp_s(Address(rsp, 0)); 931 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 932 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 933 __ fstp_d(Address(rsp, 0)); 934 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 935 936 // move between xmm-registers 937 } else if (dest->is_single_xmm()) { 938 assert(src->is_single_xmm(), "must match"); 939 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 940 } else if (dest->is_double_xmm()) { 941 assert(src->is_double_xmm(), "must match"); 942 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 943 944 // move between fpu-registers (no instruction necessary because of fpu-stack) 945 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 946 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 947 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 948 } else { 949 ShouldNotReachHere(); 950 } 951 } 952 953 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 954 assert(src->is_register(), "should not call otherwise"); 955 assert(dest->is_stack(), "should not call otherwise"); 956 957 if (src->is_single_cpu()) { 958 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 959 if (type == T_OBJECT || type == T_ARRAY) { 960 __ verify_oop(src->as_register()); 961 __ movptr (dst, src->as_register()); 962 } else { 963 __ movl (dst, src->as_register()); 964 } 965 966 } else if (src->is_double_cpu()) { 967 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 968 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 969 __ movptr (dstLO, src->as_register_lo()); 970 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 971 972 } else if (src->is_single_xmm()) { 973 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 974 __ movflt(dst_addr, src->as_xmm_float_reg()); 975 976 } else if (src->is_double_xmm()) { 977 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 978 __ movdbl(dst_addr, src->as_xmm_double_reg()); 979 980 } else if (src->is_single_fpu()) { 981 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 982 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 983 if (pop_fpu_stack) __ fstp_s (dst_addr); 984 else __ fst_s (dst_addr); 985 986 } else if (src->is_double_fpu()) { 987 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 988 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 989 if (pop_fpu_stack) __ fstp_d (dst_addr); 990 else __ fst_d (dst_addr); 991 992 } else { 993 ShouldNotReachHere(); 994 } 995 } 996 997 998 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { 999 LIR_Address* to_addr = dest->as_address_ptr(); 1000 PatchingStub* patch = NULL; 1001 1002 if (type == T_ARRAY || type == T_OBJECT) { 1003 __ verify_oop(src->as_register()); 1004 } 1005 if (patch_code != lir_patch_none) { 1006 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1007 Address toa = as_Address(to_addr); 1008 assert(toa.disp() != 0, "must have"); 1009 } 1010 if (info != NULL) { 1011 add_debug_info_for_null_check_here(info); 1012 } 1013 1014 switch (type) { 1015 case T_FLOAT: { 1016 if (src->is_single_xmm()) { 1017 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 1018 } else { 1019 assert(src->is_single_fpu(), "must be"); 1020 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 1021 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 1022 else __ fst_s (as_Address(to_addr)); 1023 } 1024 break; 1025 } 1026 1027 case T_DOUBLE: { 1028 if (src->is_double_xmm()) { 1029 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1030 } else { 1031 assert(src->is_double_fpu(), "must be"); 1032 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1033 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1034 else __ fst_d (as_Address(to_addr)); 1035 } 1036 break; 1037 } 1038 1039 case T_ADDRESS: // fall through 1040 case T_ARRAY: // fall through 1041 case T_OBJECT: // fall through 1042 #ifdef _LP64 1043 __ movptr(as_Address(to_addr), src->as_register()); 1044 break; 1045 #endif // _LP64 1046 case T_INT: 1047 __ movl(as_Address(to_addr), src->as_register()); 1048 break; 1049 1050 case T_LONG: { 1051 Register from_lo = src->as_register_lo(); 1052 Register from_hi = src->as_register_hi(); 1053 #ifdef _LP64 1054 __ movptr(as_Address_lo(to_addr), from_lo); 1055 #else 1056 Register base = to_addr->base()->as_register(); 1057 Register index = noreg; 1058 if (to_addr->index()->is_register()) { 1059 index = to_addr->index()->as_register(); 1060 } 1061 if (base == from_lo || index == from_lo) { 1062 assert(base != from_hi, "can't be"); 1063 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1064 __ movl(as_Address_hi(to_addr), from_hi); 1065 if (patch != NULL) { 1066 patching_epilog(patch, lir_patch_high, base, info); 1067 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1068 patch_code = lir_patch_low; 1069 } 1070 __ movl(as_Address_lo(to_addr), from_lo); 1071 } else { 1072 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1073 __ movl(as_Address_lo(to_addr), from_lo); 1074 if (patch != NULL) { 1075 patching_epilog(patch, lir_patch_low, base, info); 1076 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1077 patch_code = lir_patch_high; 1078 } 1079 __ movl(as_Address_hi(to_addr), from_hi); 1080 } 1081 #endif // _LP64 1082 break; 1083 } 1084 1085 case T_BYTE: // fall through 1086 case T_BOOLEAN: { 1087 Register src_reg = src->as_register(); 1088 Address dst_addr = as_Address(to_addr); 1089 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1090 __ movb(dst_addr, src_reg); 1091 break; 1092 } 1093 1094 case T_CHAR: // fall through 1095 case T_SHORT: 1096 __ movw(as_Address(to_addr), src->as_register()); 1097 break; 1098 1099 default: 1100 ShouldNotReachHere(); 1101 } 1102 1103 if (patch_code != lir_patch_none) { 1104 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1105 } 1106 } 1107 1108 1109 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1110 assert(src->is_stack(), "should not call otherwise"); 1111 assert(dest->is_register(), "should not call otherwise"); 1112 1113 if (dest->is_single_cpu()) { 1114 if (type == T_ARRAY || type == T_OBJECT) { 1115 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1116 __ verify_oop(dest->as_register()); 1117 } else { 1118 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1119 } 1120 1121 } else if (dest->is_double_cpu()) { 1122 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1123 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1124 __ movptr(dest->as_register_lo(), src_addr_LO); 1125 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1126 1127 } else if (dest->is_single_xmm()) { 1128 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1129 __ movflt(dest->as_xmm_float_reg(), src_addr); 1130 1131 } else if (dest->is_double_xmm()) { 1132 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1133 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1134 1135 } else if (dest->is_single_fpu()) { 1136 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1137 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1138 __ fld_s(src_addr); 1139 1140 } else if (dest->is_double_fpu()) { 1141 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1142 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1143 __ fld_d(src_addr); 1144 1145 } else { 1146 ShouldNotReachHere(); 1147 } 1148 } 1149 1150 1151 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1152 if (src->is_single_stack()) { 1153 if (type == T_OBJECT || type == T_ARRAY) { 1154 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1155 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1156 } else { 1157 #ifndef _LP64 1158 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1159 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1160 #else 1161 //no pushl on 64bits 1162 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1163 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1164 #endif 1165 } 1166 1167 } else if (src->is_double_stack()) { 1168 #ifdef _LP64 1169 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1170 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1171 #else 1172 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1173 // push and pop the part at src + wordSize, adding wordSize for the previous push 1174 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1175 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1176 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1177 #endif // _LP64 1178 1179 } else { 1180 ShouldNotReachHere(); 1181 } 1182 } 1183 1184 1185 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { 1186 assert(src->is_address(), "should not call otherwise"); 1187 assert(dest->is_register(), "should not call otherwise"); 1188 1189 LIR_Address* addr = src->as_address_ptr(); 1190 Address from_addr = as_Address(addr); 1191 1192 switch (type) { 1193 case T_BOOLEAN: // fall through 1194 case T_BYTE: // fall through 1195 case T_CHAR: // fall through 1196 case T_SHORT: 1197 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1198 // on pre P6 processors we may get partial register stalls 1199 // so blow away the value of to_rinfo before loading a 1200 // partial word into it. Do it here so that it precedes 1201 // the potential patch point below. 1202 __ xorptr(dest->as_register(), dest->as_register()); 1203 } 1204 break; 1205 } 1206 1207 PatchingStub* patch = NULL; 1208 if (patch_code != lir_patch_none) { 1209 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1210 assert(from_addr.disp() != 0, "must have"); 1211 } 1212 if (info != NULL) { 1213 add_debug_info_for_null_check_here(info); 1214 } 1215 1216 switch (type) { 1217 case T_FLOAT: { 1218 if (dest->is_single_xmm()) { 1219 __ movflt(dest->as_xmm_float_reg(), from_addr); 1220 } else { 1221 assert(dest->is_single_fpu(), "must be"); 1222 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1223 __ fld_s(from_addr); 1224 } 1225 break; 1226 } 1227 1228 case T_DOUBLE: { 1229 if (dest->is_double_xmm()) { 1230 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1231 } else { 1232 assert(dest->is_double_fpu(), "must be"); 1233 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1234 __ fld_d(from_addr); 1235 } 1236 break; 1237 } 1238 1239 case T_ADDRESS: // fall through 1240 case T_OBJECT: // fall through 1241 case T_ARRAY: // fall through 1242 #ifdef _LP64 1243 __ movptr(dest->as_register(), from_addr); 1244 break; 1245 #endif // _L64 1246 case T_INT: 1247 __ movl(dest->as_register(), from_addr); 1248 break; 1249 1250 case T_LONG: { 1251 Register to_lo = dest->as_register_lo(); 1252 Register to_hi = dest->as_register_hi(); 1253 #ifdef _LP64 1254 __ movptr(to_lo, as_Address_lo(addr)); 1255 #else 1256 Register base = addr->base()->as_register(); 1257 Register index = noreg; 1258 if (addr->index()->is_register()) { 1259 index = addr->index()->as_register(); 1260 } 1261 if ((base == to_lo && index == to_hi) || 1262 (base == to_hi && index == to_lo)) { 1263 // addresses with 2 registers are only formed as a result of 1264 // array access so this code will never have to deal with 1265 // patches or null checks. 1266 assert(info == NULL && patch == NULL, "must be"); 1267 __ lea(to_hi, as_Address(addr)); 1268 __ movl(to_lo, Address(to_hi, 0)); 1269 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1270 } else if (base == to_lo || index == to_lo) { 1271 assert(base != to_hi, "can't be"); 1272 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1273 __ movl(to_hi, as_Address_hi(addr)); 1274 if (patch != NULL) { 1275 patching_epilog(patch, lir_patch_high, base, info); 1276 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1277 patch_code = lir_patch_low; 1278 } 1279 __ movl(to_lo, as_Address_lo(addr)); 1280 } else { 1281 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1282 __ movl(to_lo, as_Address_lo(addr)); 1283 if (patch != NULL) { 1284 patching_epilog(patch, lir_patch_low, base, info); 1285 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1286 patch_code = lir_patch_high; 1287 } 1288 __ movl(to_hi, as_Address_hi(addr)); 1289 } 1290 #endif // _LP64 1291 break; 1292 } 1293 1294 case T_BOOLEAN: // fall through 1295 case T_BYTE: { 1296 Register dest_reg = dest->as_register(); 1297 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1298 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1299 __ movsbl(dest_reg, from_addr); 1300 } else { 1301 __ movb(dest_reg, from_addr); 1302 __ shll(dest_reg, 24); 1303 __ sarl(dest_reg, 24); 1304 } 1305 break; 1306 } 1307 1308 case T_CHAR: { 1309 Register dest_reg = dest->as_register(); 1310 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1311 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1312 __ movzwl(dest_reg, from_addr); 1313 } else { 1314 __ movw(dest_reg, from_addr); 1315 } 1316 break; 1317 } 1318 1319 case T_SHORT: { 1320 Register dest_reg = dest->as_register(); 1321 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1322 __ movswl(dest_reg, from_addr); 1323 } else { 1324 __ movw(dest_reg, from_addr); 1325 __ shll(dest_reg, 16); 1326 __ sarl(dest_reg, 16); 1327 } 1328 break; 1329 } 1330 1331 default: 1332 ShouldNotReachHere(); 1333 } 1334 1335 if (patch != NULL) { 1336 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1337 } 1338 1339 if (type == T_ARRAY || type == T_OBJECT) { 1340 __ verify_oop(dest->as_register()); 1341 } 1342 } 1343 1344 1345 void LIR_Assembler::prefetchr(LIR_Opr src) { 1346 LIR_Address* addr = src->as_address_ptr(); 1347 Address from_addr = as_Address(addr); 1348 1349 if (VM_Version::supports_sse()) { 1350 switch (ReadPrefetchInstr) { 1351 case 0: 1352 __ prefetchnta(from_addr); break; 1353 case 1: 1354 __ prefetcht0(from_addr); break; 1355 case 2: 1356 __ prefetcht2(from_addr); break; 1357 default: 1358 ShouldNotReachHere(); break; 1359 } 1360 } else if (VM_Version::supports_3dnow()) { 1361 __ prefetchr(from_addr); 1362 } 1363 } 1364 1365 1366 void LIR_Assembler::prefetchw(LIR_Opr src) { 1367 LIR_Address* addr = src->as_address_ptr(); 1368 Address from_addr = as_Address(addr); 1369 1370 if (VM_Version::supports_sse()) { 1371 switch (AllocatePrefetchInstr) { 1372 case 0: 1373 __ prefetchnta(from_addr); break; 1374 case 1: 1375 __ prefetcht0(from_addr); break; 1376 case 2: 1377 __ prefetcht2(from_addr); break; 1378 case 3: 1379 __ prefetchw(from_addr); break; 1380 default: 1381 ShouldNotReachHere(); break; 1382 } 1383 } else if (VM_Version::supports_3dnow()) { 1384 __ prefetchw(from_addr); 1385 } 1386 } 1387 1388 1389 NEEDS_CLEANUP; // This could be static? 1390 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1391 int elem_size = type2aelembytes(type); 1392 switch (elem_size) { 1393 case 1: return Address::times_1; 1394 case 2: return Address::times_2; 1395 case 4: return Address::times_4; 1396 case 8: return Address::times_8; 1397 } 1398 ShouldNotReachHere(); 1399 return Address::no_scale; 1400 } 1401 1402 1403 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1404 switch (op->code()) { 1405 case lir_idiv: 1406 case lir_irem: 1407 arithmetic_idiv(op->code(), 1408 op->in_opr1(), 1409 op->in_opr2(), 1410 op->in_opr3(), 1411 op->result_opr(), 1412 op->info()); 1413 break; 1414 default: ShouldNotReachHere(); break; 1415 } 1416 } 1417 1418 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1419 #ifdef ASSERT 1420 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1421 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1422 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1423 #endif 1424 1425 if (op->cond() == lir_cond_always) { 1426 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1427 __ jmp (*(op->label())); 1428 } else { 1429 Assembler::Condition acond = Assembler::zero; 1430 if (op->code() == lir_cond_float_branch) { 1431 assert(op->ublock() != NULL, "must have unordered successor"); 1432 __ jcc(Assembler::parity, *(op->ublock()->label())); 1433 switch(op->cond()) { 1434 case lir_cond_equal: acond = Assembler::equal; break; 1435 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1436 case lir_cond_less: acond = Assembler::below; break; 1437 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1438 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1439 case lir_cond_greater: acond = Assembler::above; break; 1440 default: ShouldNotReachHere(); 1441 } 1442 } else { 1443 switch (op->cond()) { 1444 case lir_cond_equal: acond = Assembler::equal; break; 1445 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1446 case lir_cond_less: acond = Assembler::less; break; 1447 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1448 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1449 case lir_cond_greater: acond = Assembler::greater; break; 1450 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1451 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1452 default: ShouldNotReachHere(); 1453 } 1454 } 1455 __ jcc(acond,*(op->label())); 1456 } 1457 } 1458 1459 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1460 LIR_Opr src = op->in_opr(); 1461 LIR_Opr dest = op->result_opr(); 1462 1463 switch (op->bytecode()) { 1464 case Bytecodes::_i2l: 1465 #ifdef _LP64 1466 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1467 #else 1468 move_regs(src->as_register(), dest->as_register_lo()); 1469 move_regs(src->as_register(), dest->as_register_hi()); 1470 __ sarl(dest->as_register_hi(), 31); 1471 #endif // LP64 1472 break; 1473 1474 case Bytecodes::_l2i: 1475 move_regs(src->as_register_lo(), dest->as_register()); 1476 break; 1477 1478 case Bytecodes::_i2b: 1479 move_regs(src->as_register(), dest->as_register()); 1480 __ sign_extend_byte(dest->as_register()); 1481 break; 1482 1483 case Bytecodes::_i2c: 1484 move_regs(src->as_register(), dest->as_register()); 1485 __ andl(dest->as_register(), 0xFFFF); 1486 break; 1487 1488 case Bytecodes::_i2s: 1489 move_regs(src->as_register(), dest->as_register()); 1490 __ sign_extend_short(dest->as_register()); 1491 break; 1492 1493 1494 case Bytecodes::_f2d: 1495 case Bytecodes::_d2f: 1496 if (dest->is_single_xmm()) { 1497 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1498 } else if (dest->is_double_xmm()) { 1499 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1500 } else { 1501 assert(src->fpu() == dest->fpu(), "register must be equal"); 1502 // do nothing (float result is rounded later through spilling) 1503 } 1504 break; 1505 1506 case Bytecodes::_i2f: 1507 case Bytecodes::_i2d: 1508 if (dest->is_single_xmm()) { 1509 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1510 } else if (dest->is_double_xmm()) { 1511 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1512 } else { 1513 assert(dest->fpu() == 0, "result must be on TOS"); 1514 __ movl(Address(rsp, 0), src->as_register()); 1515 __ fild_s(Address(rsp, 0)); 1516 } 1517 break; 1518 1519 case Bytecodes::_f2i: 1520 case Bytecodes::_d2i: 1521 if (src->is_single_xmm()) { 1522 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1523 } else if (src->is_double_xmm()) { 1524 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1525 } else { 1526 assert(src->fpu() == 0, "input must be on TOS"); 1527 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1528 __ fist_s(Address(rsp, 0)); 1529 __ movl(dest->as_register(), Address(rsp, 0)); 1530 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1531 } 1532 1533 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1534 assert(op->stub() != NULL, "stub required"); 1535 __ cmpl(dest->as_register(), 0x80000000); 1536 __ jcc(Assembler::equal, *op->stub()->entry()); 1537 __ bind(*op->stub()->continuation()); 1538 break; 1539 1540 case Bytecodes::_l2f: 1541 case Bytecodes::_l2d: 1542 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1543 assert(dest->fpu() == 0, "result must be on TOS"); 1544 1545 __ movptr(Address(rsp, 0), src->as_register_lo()); 1546 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1547 __ fild_d(Address(rsp, 0)); 1548 // float result is rounded later through spilling 1549 break; 1550 1551 case Bytecodes::_f2l: 1552 case Bytecodes::_d2l: 1553 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1554 assert(src->fpu() == 0, "input must be on TOS"); 1555 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1556 1557 // instruction sequence too long to inline it here 1558 { 1559 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1560 } 1561 break; 1562 1563 default: ShouldNotReachHere(); 1564 } 1565 } 1566 1567 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1568 if (op->init_check()) { 1569 __ cmpl(Address(op->klass()->as_register(), 1570 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), 1571 instanceKlass::fully_initialized); 1572 add_debug_info_for_null_check_here(op->stub()->info()); 1573 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1574 } 1575 __ allocate_object(op->obj()->as_register(), 1576 op->tmp1()->as_register(), 1577 op->tmp2()->as_register(), 1578 op->header_size(), 1579 op->object_size(), 1580 op->klass()->as_register(), 1581 *op->stub()->entry()); 1582 __ bind(*op->stub()->continuation()); 1583 } 1584 1585 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1586 if (UseSlowPath || 1587 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1588 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1589 __ jmp(*op->stub()->entry()); 1590 } else { 1591 Register len = op->len()->as_register(); 1592 Register tmp1 = op->tmp1()->as_register(); 1593 Register tmp2 = op->tmp2()->as_register(); 1594 Register tmp3 = op->tmp3()->as_register(); 1595 if (len == tmp1) { 1596 tmp1 = tmp3; 1597 } else if (len == tmp2) { 1598 tmp2 = tmp3; 1599 } else if (len == tmp3) { 1600 // everything is ok 1601 } else { 1602 __ mov(tmp3, len); 1603 } 1604 __ allocate_array(op->obj()->as_register(), 1605 len, 1606 tmp1, 1607 tmp2, 1608 arrayOopDesc::header_size(op->type()), 1609 array_element_size(op->type()), 1610 op->klass()->as_register(), 1611 *op->stub()->entry()); 1612 } 1613 __ bind(*op->stub()->continuation()); 1614 } 1615 1616 1617 1618 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1619 LIR_Code code = op->code(); 1620 if (code == lir_store_check) { 1621 Register value = op->object()->as_register(); 1622 Register array = op->array()->as_register(); 1623 Register k_RInfo = op->tmp1()->as_register(); 1624 Register klass_RInfo = op->tmp2()->as_register(); 1625 Register Rtmp1 = op->tmp3()->as_register(); 1626 1627 CodeStub* stub = op->stub(); 1628 Label done; 1629 __ cmpptr(value, (int32_t)NULL_WORD); 1630 __ jcc(Assembler::equal, done); 1631 add_debug_info_for_null_check_here(op->info_for_exception()); 1632 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); 1633 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); 1634 1635 // get instance klass 1636 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); 1637 // perform the fast part of the checking logic 1638 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); 1639 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1640 __ push(klass_RInfo); 1641 __ push(k_RInfo); 1642 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1643 __ pop(klass_RInfo); 1644 __ pop(k_RInfo); 1645 // result is a boolean 1646 __ cmpl(k_RInfo, 0); 1647 __ jcc(Assembler::equal, *stub->entry()); 1648 __ bind(done); 1649 } else if (op->code() == lir_checkcast) { 1650 // we always need a stub for the failure case. 1651 CodeStub* stub = op->stub(); 1652 Register obj = op->object()->as_register(); 1653 Register k_RInfo = op->tmp1()->as_register(); 1654 Register klass_RInfo = op->tmp2()->as_register(); 1655 Register dst = op->result_opr()->as_register(); 1656 ciKlass* k = op->klass(); 1657 Register Rtmp1 = noreg; 1658 1659 Label done; 1660 if (obj == k_RInfo) { 1661 k_RInfo = dst; 1662 } else if (obj == klass_RInfo) { 1663 klass_RInfo = dst; 1664 } 1665 if (k->is_loaded()) { 1666 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1667 } else { 1668 Rtmp1 = op->tmp3()->as_register(); 1669 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1670 } 1671 1672 assert_different_registers(obj, k_RInfo, klass_RInfo); 1673 if (!k->is_loaded()) { 1674 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1675 } else { 1676 #ifdef _LP64 1677 __ movoop(k_RInfo, k->constant_encoding()); 1678 #else 1679 k_RInfo = noreg; 1680 #endif // _LP64 1681 } 1682 assert(obj != k_RInfo, "must be different"); 1683 __ cmpptr(obj, (int32_t)NULL_WORD); 1684 if (op->profiled_method() != NULL) { 1685 ciMethod* method = op->profiled_method(); 1686 int bci = op->profiled_bci(); 1687 1688 Label profile_done; 1689 __ jcc(Assembler::notEqual, profile_done); 1690 // Object is null; update methodDataOop 1691 ciMethodData* md = method->method_data(); 1692 if (md == NULL) { 1693 bailout("out of memory building methodDataOop"); 1694 return; 1695 } 1696 ciProfileData* data = md->bci_to_data(bci); 1697 assert(data != NULL, "need data for checkcast"); 1698 assert(data->is_BitData(), "need BitData for checkcast"); 1699 Register mdo = klass_RInfo; 1700 __ movoop(mdo, md->constant_encoding()); 1701 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1702 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1703 __ orl(data_addr, header_bits); 1704 __ jmp(done); 1705 __ bind(profile_done); 1706 } else { 1707 __ jcc(Assembler::equal, done); 1708 } 1709 __ verify_oop(obj); 1710 1711 if (op->fast_check()) { 1712 // get object classo 1713 // not a safepoint as obj null check happens earlier 1714 if (k->is_loaded()) { 1715 #ifdef _LP64 1716 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1717 #else 1718 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1719 #endif // _LP64 1720 } else { 1721 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1722 1723 } 1724 __ jcc(Assembler::notEqual, *stub->entry()); 1725 __ bind(done); 1726 } else { 1727 // get object class 1728 // not a safepoint as obj null check happens earlier 1729 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1730 if (k->is_loaded()) { 1731 // See if we get an immediate positive hit 1732 #ifdef _LP64 1733 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1734 #else 1735 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1736 #endif // _LP64 1737 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { 1738 __ jcc(Assembler::notEqual, *stub->entry()); 1739 } else { 1740 // See if we get an immediate positive hit 1741 __ jcc(Assembler::equal, done); 1742 // check for self 1743 #ifdef _LP64 1744 __ cmpptr(klass_RInfo, k_RInfo); 1745 #else 1746 __ cmpoop(klass_RInfo, k->constant_encoding()); 1747 #endif // _LP64 1748 __ jcc(Assembler::equal, done); 1749 1750 __ push(klass_RInfo); 1751 #ifdef _LP64 1752 __ push(k_RInfo); 1753 #else 1754 __ pushoop(k->constant_encoding()); 1755 #endif // _LP64 1756 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1757 __ pop(klass_RInfo); 1758 __ pop(klass_RInfo); 1759 // result is a boolean 1760 __ cmpl(klass_RInfo, 0); 1761 __ jcc(Assembler::equal, *stub->entry()); 1762 } 1763 __ bind(done); 1764 } else { 1765 // perform the fast part of the checking logic 1766 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); 1767 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1768 __ push(klass_RInfo); 1769 __ push(k_RInfo); 1770 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1771 __ pop(klass_RInfo); 1772 __ pop(k_RInfo); 1773 // result is a boolean 1774 __ cmpl(k_RInfo, 0); 1775 __ jcc(Assembler::equal, *stub->entry()); 1776 __ bind(done); 1777 } 1778 1779 } 1780 if (dst != obj) { 1781 __ mov(dst, obj); 1782 } 1783 } else if (code == lir_instanceof) { 1784 Register obj = op->object()->as_register(); 1785 Register k_RInfo = op->tmp1()->as_register(); 1786 Register klass_RInfo = op->tmp2()->as_register(); 1787 Register dst = op->result_opr()->as_register(); 1788 ciKlass* k = op->klass(); 1789 1790 Label done; 1791 Label zero; 1792 Label one; 1793 if (obj == k_RInfo) { 1794 k_RInfo = klass_RInfo; 1795 klass_RInfo = obj; 1796 } 1797 // patching may screw with our temporaries on sparc, 1798 // so let's do it before loading the class 1799 if (!k->is_loaded()) { 1800 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1801 } else { 1802 LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding())); 1803 } 1804 assert(obj != k_RInfo, "must be different"); 1805 1806 __ verify_oop(obj); 1807 if (op->fast_check()) { 1808 __ cmpptr(obj, (int32_t)NULL_WORD); 1809 __ jcc(Assembler::equal, zero); 1810 // get object class 1811 // not a safepoint as obj null check happens earlier 1812 if (LP64_ONLY(false &&) k->is_loaded()) { 1813 NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding())); 1814 k_RInfo = noreg; 1815 } else { 1816 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1817 1818 } 1819 __ jcc(Assembler::equal, one); 1820 } else { 1821 // get object class 1822 // not a safepoint as obj null check happens earlier 1823 __ cmpptr(obj, (int32_t)NULL_WORD); 1824 __ jcc(Assembler::equal, zero); 1825 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1826 1827 #ifndef _LP64 1828 if (k->is_loaded()) { 1829 // See if we get an immediate positive hit 1830 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1831 __ jcc(Assembler::equal, one); 1832 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { 1833 // check for self 1834 __ cmpoop(klass_RInfo, k->constant_encoding()); 1835 __ jcc(Assembler::equal, one); 1836 __ push(klass_RInfo); 1837 __ pushoop(k->constant_encoding()); 1838 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1839 __ pop(klass_RInfo); 1840 __ pop(dst); 1841 __ jmp(done); 1842 } 1843 } 1844 else // next block is unconditional if LP64: 1845 #endif // LP64 1846 { 1847 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); 1848 1849 // perform the fast part of the checking logic 1850 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL); 1851 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1852 __ push(klass_RInfo); 1853 __ push(k_RInfo); 1854 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1855 __ pop(klass_RInfo); 1856 __ pop(dst); 1857 __ jmp(done); 1858 } 1859 } 1860 __ bind(zero); 1861 __ xorptr(dst, dst); 1862 __ jmp(done); 1863 __ bind(one); 1864 __ movptr(dst, 1); 1865 __ bind(done); 1866 } else { 1867 ShouldNotReachHere(); 1868 } 1869 1870 } 1871 1872 1873 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1874 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1875 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1876 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1877 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1878 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1879 Register addr = op->addr()->as_register(); 1880 if (os::is_MP()) { 1881 __ lock(); 1882 } 1883 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1884 1885 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1886 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1887 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1888 Register newval = op->new_value()->as_register(); 1889 Register cmpval = op->cmp_value()->as_register(); 1890 assert(cmpval == rax, "wrong register"); 1891 assert(newval != NULL, "new val must be register"); 1892 assert(cmpval != newval, "cmp and new values must be in different registers"); 1893 assert(cmpval != addr, "cmp and addr must be in different registers"); 1894 assert(newval != addr, "new value and addr must be in different registers"); 1895 if (os::is_MP()) { 1896 __ lock(); 1897 } 1898 if ( op->code() == lir_cas_obj) { 1899 __ cmpxchgptr(newval, Address(addr, 0)); 1900 } else if (op->code() == lir_cas_int) { 1901 __ cmpxchgl(newval, Address(addr, 0)); 1902 } else { 1903 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); 1904 } 1905 #ifdef _LP64 1906 } else if (op->code() == lir_cas_long) { 1907 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1908 Register newval = op->new_value()->as_register_lo(); 1909 Register cmpval = op->cmp_value()->as_register_lo(); 1910 assert(cmpval == rax, "wrong register"); 1911 assert(newval != NULL, "new val must be register"); 1912 assert(cmpval != newval, "cmp and new values must be in different registers"); 1913 assert(cmpval != addr, "cmp and addr must be in different registers"); 1914 assert(newval != addr, "new value and addr must be in different registers"); 1915 if (os::is_MP()) { 1916 __ lock(); 1917 } 1918 __ cmpxchgq(newval, Address(addr, 0)); 1919 #endif // _LP64 1920 } else { 1921 Unimplemented(); 1922 } 1923 } 1924 1925 1926 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1927 Assembler::Condition acond, ncond; 1928 switch (condition) { 1929 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1930 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1931 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1932 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1933 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1934 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1935 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1936 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1937 default: ShouldNotReachHere(); 1938 } 1939 1940 if (opr1->is_cpu_register()) { 1941 reg2reg(opr1, result); 1942 } else if (opr1->is_stack()) { 1943 stack2reg(opr1, result, result->type()); 1944 } else if (opr1->is_constant()) { 1945 const2reg(opr1, result, lir_patch_none, NULL); 1946 } else { 1947 ShouldNotReachHere(); 1948 } 1949 1950 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1951 // optimized version that does not require a branch 1952 if (opr2->is_single_cpu()) { 1953 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1954 __ cmov(ncond, result->as_register(), opr2->as_register()); 1955 } else if (opr2->is_double_cpu()) { 1956 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1957 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1958 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 1959 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 1960 } else if (opr2->is_single_stack()) { 1961 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 1962 } else if (opr2->is_double_stack()) { 1963 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 1964 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 1965 } else { 1966 ShouldNotReachHere(); 1967 } 1968 1969 } else { 1970 Label skip; 1971 __ jcc (acond, skip); 1972 if (opr2->is_cpu_register()) { 1973 reg2reg(opr2, result); 1974 } else if (opr2->is_stack()) { 1975 stack2reg(opr2, result, result->type()); 1976 } else if (opr2->is_constant()) { 1977 const2reg(opr2, result, lir_patch_none, NULL); 1978 } else { 1979 ShouldNotReachHere(); 1980 } 1981 __ bind(skip); 1982 } 1983 } 1984 1985 1986 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1987 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1988 1989 if (left->is_single_cpu()) { 1990 assert(left == dest, "left and dest must be equal"); 1991 Register lreg = left->as_register(); 1992 1993 if (right->is_single_cpu()) { 1994 // cpu register - cpu register 1995 Register rreg = right->as_register(); 1996 switch (code) { 1997 case lir_add: __ addl (lreg, rreg); break; 1998 case lir_sub: __ subl (lreg, rreg); break; 1999 case lir_mul: __ imull(lreg, rreg); break; 2000 default: ShouldNotReachHere(); 2001 } 2002 2003 } else if (right->is_stack()) { 2004 // cpu register - stack 2005 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2006 switch (code) { 2007 case lir_add: __ addl(lreg, raddr); break; 2008 case lir_sub: __ subl(lreg, raddr); break; 2009 default: ShouldNotReachHere(); 2010 } 2011 2012 } else if (right->is_constant()) { 2013 // cpu register - constant 2014 jint c = right->as_constant_ptr()->as_jint(); 2015 switch (code) { 2016 case lir_add: { 2017 __ increment(lreg, c); 2018 break; 2019 } 2020 case lir_sub: { 2021 __ decrement(lreg, c); 2022 break; 2023 } 2024 default: ShouldNotReachHere(); 2025 } 2026 2027 } else { 2028 ShouldNotReachHere(); 2029 } 2030 2031 } else if (left->is_double_cpu()) { 2032 assert(left == dest, "left and dest must be equal"); 2033 Register lreg_lo = left->as_register_lo(); 2034 Register lreg_hi = left->as_register_hi(); 2035 2036 if (right->is_double_cpu()) { 2037 // cpu register - cpu register 2038 Register rreg_lo = right->as_register_lo(); 2039 Register rreg_hi = right->as_register_hi(); 2040 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2041 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2042 switch (code) { 2043 case lir_add: 2044 __ addptr(lreg_lo, rreg_lo); 2045 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2046 break; 2047 case lir_sub: 2048 __ subptr(lreg_lo, rreg_lo); 2049 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2050 break; 2051 case lir_mul: 2052 #ifdef _LP64 2053 __ imulq(lreg_lo, rreg_lo); 2054 #else 2055 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2056 __ imull(lreg_hi, rreg_lo); 2057 __ imull(rreg_hi, lreg_lo); 2058 __ addl (rreg_hi, lreg_hi); 2059 __ mull (rreg_lo); 2060 __ addl (lreg_hi, rreg_hi); 2061 #endif // _LP64 2062 break; 2063 default: 2064 ShouldNotReachHere(); 2065 } 2066 2067 } else if (right->is_constant()) { 2068 // cpu register - constant 2069 #ifdef _LP64 2070 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2071 __ movptr(r10, (intptr_t) c); 2072 switch (code) { 2073 case lir_add: 2074 __ addptr(lreg_lo, r10); 2075 break; 2076 case lir_sub: 2077 __ subptr(lreg_lo, r10); 2078 break; 2079 default: 2080 ShouldNotReachHere(); 2081 } 2082 #else 2083 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2084 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2085 switch (code) { 2086 case lir_add: 2087 __ addptr(lreg_lo, c_lo); 2088 __ adcl(lreg_hi, c_hi); 2089 break; 2090 case lir_sub: 2091 __ subptr(lreg_lo, c_lo); 2092 __ sbbl(lreg_hi, c_hi); 2093 break; 2094 default: 2095 ShouldNotReachHere(); 2096 } 2097 #endif // _LP64 2098 2099 } else { 2100 ShouldNotReachHere(); 2101 } 2102 2103 } else if (left->is_single_xmm()) { 2104 assert(left == dest, "left and dest must be equal"); 2105 XMMRegister lreg = left->as_xmm_float_reg(); 2106 2107 if (right->is_single_xmm()) { 2108 XMMRegister rreg = right->as_xmm_float_reg(); 2109 switch (code) { 2110 case lir_add: __ addss(lreg, rreg); break; 2111 case lir_sub: __ subss(lreg, rreg); break; 2112 case lir_mul_strictfp: // fall through 2113 case lir_mul: __ mulss(lreg, rreg); break; 2114 case lir_div_strictfp: // fall through 2115 case lir_div: __ divss(lreg, rreg); break; 2116 default: ShouldNotReachHere(); 2117 } 2118 } else { 2119 Address raddr; 2120 if (right->is_single_stack()) { 2121 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2122 } else if (right->is_constant()) { 2123 // hack for now 2124 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2125 } else { 2126 ShouldNotReachHere(); 2127 } 2128 switch (code) { 2129 case lir_add: __ addss(lreg, raddr); break; 2130 case lir_sub: __ subss(lreg, raddr); break; 2131 case lir_mul_strictfp: // fall through 2132 case lir_mul: __ mulss(lreg, raddr); break; 2133 case lir_div_strictfp: // fall through 2134 case lir_div: __ divss(lreg, raddr); break; 2135 default: ShouldNotReachHere(); 2136 } 2137 } 2138 2139 } else if (left->is_double_xmm()) { 2140 assert(left == dest, "left and dest must be equal"); 2141 2142 XMMRegister lreg = left->as_xmm_double_reg(); 2143 if (right->is_double_xmm()) { 2144 XMMRegister rreg = right->as_xmm_double_reg(); 2145 switch (code) { 2146 case lir_add: __ addsd(lreg, rreg); break; 2147 case lir_sub: __ subsd(lreg, rreg); break; 2148 case lir_mul_strictfp: // fall through 2149 case lir_mul: __ mulsd(lreg, rreg); break; 2150 case lir_div_strictfp: // fall through 2151 case lir_div: __ divsd(lreg, rreg); break; 2152 default: ShouldNotReachHere(); 2153 } 2154 } else { 2155 Address raddr; 2156 if (right->is_double_stack()) { 2157 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2158 } else if (right->is_constant()) { 2159 // hack for now 2160 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2161 } else { 2162 ShouldNotReachHere(); 2163 } 2164 switch (code) { 2165 case lir_add: __ addsd(lreg, raddr); break; 2166 case lir_sub: __ subsd(lreg, raddr); break; 2167 case lir_mul_strictfp: // fall through 2168 case lir_mul: __ mulsd(lreg, raddr); break; 2169 case lir_div_strictfp: // fall through 2170 case lir_div: __ divsd(lreg, raddr); break; 2171 default: ShouldNotReachHere(); 2172 } 2173 } 2174 2175 } else if (left->is_single_fpu()) { 2176 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2177 2178 if (right->is_single_fpu()) { 2179 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2180 2181 } else { 2182 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2183 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2184 2185 Address raddr; 2186 if (right->is_single_stack()) { 2187 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2188 } else if (right->is_constant()) { 2189 address const_addr = float_constant(right->as_jfloat()); 2190 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2191 // hack for now 2192 raddr = __ as_Address(InternalAddress(const_addr)); 2193 } else { 2194 ShouldNotReachHere(); 2195 } 2196 2197 switch (code) { 2198 case lir_add: __ fadd_s(raddr); break; 2199 case lir_sub: __ fsub_s(raddr); break; 2200 case lir_mul_strictfp: // fall through 2201 case lir_mul: __ fmul_s(raddr); break; 2202 case lir_div_strictfp: // fall through 2203 case lir_div: __ fdiv_s(raddr); break; 2204 default: ShouldNotReachHere(); 2205 } 2206 } 2207 2208 } else if (left->is_double_fpu()) { 2209 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2210 2211 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2212 // Double values require special handling for strictfp mul/div on x86 2213 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2214 __ fmulp(left->fpu_regnrLo() + 1); 2215 } 2216 2217 if (right->is_double_fpu()) { 2218 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2219 2220 } else { 2221 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2222 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2223 2224 Address raddr; 2225 if (right->is_double_stack()) { 2226 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2227 } else if (right->is_constant()) { 2228 // hack for now 2229 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2230 } else { 2231 ShouldNotReachHere(); 2232 } 2233 2234 switch (code) { 2235 case lir_add: __ fadd_d(raddr); break; 2236 case lir_sub: __ fsub_d(raddr); break; 2237 case lir_mul_strictfp: // fall through 2238 case lir_mul: __ fmul_d(raddr); break; 2239 case lir_div_strictfp: // fall through 2240 case lir_div: __ fdiv_d(raddr); break; 2241 default: ShouldNotReachHere(); 2242 } 2243 } 2244 2245 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2246 // Double values require special handling for strictfp mul/div on x86 2247 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2248 __ fmulp(dest->fpu_regnrLo() + 1); 2249 } 2250 2251 } else if (left->is_single_stack() || left->is_address()) { 2252 assert(left == dest, "left and dest must be equal"); 2253 2254 Address laddr; 2255 if (left->is_single_stack()) { 2256 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2257 } else if (left->is_address()) { 2258 laddr = as_Address(left->as_address_ptr()); 2259 } else { 2260 ShouldNotReachHere(); 2261 } 2262 2263 if (right->is_single_cpu()) { 2264 Register rreg = right->as_register(); 2265 switch (code) { 2266 case lir_add: __ addl(laddr, rreg); break; 2267 case lir_sub: __ subl(laddr, rreg); break; 2268 default: ShouldNotReachHere(); 2269 } 2270 } else if (right->is_constant()) { 2271 jint c = right->as_constant_ptr()->as_jint(); 2272 switch (code) { 2273 case lir_add: { 2274 __ incrementl(laddr, c); 2275 break; 2276 } 2277 case lir_sub: { 2278 __ decrementl(laddr, c); 2279 break; 2280 } 2281 default: ShouldNotReachHere(); 2282 } 2283 } else { 2284 ShouldNotReachHere(); 2285 } 2286 2287 } else { 2288 ShouldNotReachHere(); 2289 } 2290 } 2291 2292 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2293 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2294 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2295 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2296 2297 bool left_is_tos = (left_index == 0); 2298 bool dest_is_tos = (dest_index == 0); 2299 int non_tos_index = (left_is_tos ? right_index : left_index); 2300 2301 switch (code) { 2302 case lir_add: 2303 if (pop_fpu_stack) __ faddp(non_tos_index); 2304 else if (dest_is_tos) __ fadd (non_tos_index); 2305 else __ fadda(non_tos_index); 2306 break; 2307 2308 case lir_sub: 2309 if (left_is_tos) { 2310 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2311 else if (dest_is_tos) __ fsub (non_tos_index); 2312 else __ fsubra(non_tos_index); 2313 } else { 2314 if (pop_fpu_stack) __ fsubp (non_tos_index); 2315 else if (dest_is_tos) __ fsubr (non_tos_index); 2316 else __ fsuba (non_tos_index); 2317 } 2318 break; 2319 2320 case lir_mul_strictfp: // fall through 2321 case lir_mul: 2322 if (pop_fpu_stack) __ fmulp(non_tos_index); 2323 else if (dest_is_tos) __ fmul (non_tos_index); 2324 else __ fmula(non_tos_index); 2325 break; 2326 2327 case lir_div_strictfp: // fall through 2328 case lir_div: 2329 if (left_is_tos) { 2330 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2331 else if (dest_is_tos) __ fdiv (non_tos_index); 2332 else __ fdivra(non_tos_index); 2333 } else { 2334 if (pop_fpu_stack) __ fdivp (non_tos_index); 2335 else if (dest_is_tos) __ fdivr (non_tos_index); 2336 else __ fdiva (non_tos_index); 2337 } 2338 break; 2339 2340 case lir_rem: 2341 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2342 __ fremr(noreg); 2343 break; 2344 2345 default: 2346 ShouldNotReachHere(); 2347 } 2348 } 2349 2350 2351 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2352 if (value->is_double_xmm()) { 2353 switch(code) { 2354 case lir_abs : 2355 { 2356 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2357 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2358 } 2359 __ andpd(dest->as_xmm_double_reg(), 2360 ExternalAddress((address)double_signmask_pool)); 2361 } 2362 break; 2363 2364 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2365 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2366 default : ShouldNotReachHere(); 2367 } 2368 2369 } else if (value->is_double_fpu()) { 2370 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2371 switch(code) { 2372 case lir_log : __ flog() ; break; 2373 case lir_log10 : __ flog10() ; break; 2374 case lir_abs : __ fabs() ; break; 2375 case lir_sqrt : __ fsqrt(); break; 2376 case lir_sin : 2377 // Should consider not saving rbx, if not necessary 2378 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2379 break; 2380 case lir_cos : 2381 // Should consider not saving rbx, if not necessary 2382 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2383 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2384 break; 2385 case lir_tan : 2386 // Should consider not saving rbx, if not necessary 2387 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2388 break; 2389 default : ShouldNotReachHere(); 2390 } 2391 } else { 2392 Unimplemented(); 2393 } 2394 } 2395 2396 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2397 // assert(left->destroys_register(), "check"); 2398 if (left->is_single_cpu()) { 2399 Register reg = left->as_register(); 2400 if (right->is_constant()) { 2401 int val = right->as_constant_ptr()->as_jint(); 2402 switch (code) { 2403 case lir_logic_and: __ andl (reg, val); break; 2404 case lir_logic_or: __ orl (reg, val); break; 2405 case lir_logic_xor: __ xorl (reg, val); break; 2406 default: ShouldNotReachHere(); 2407 } 2408 } else if (right->is_stack()) { 2409 // added support for stack operands 2410 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2411 switch (code) { 2412 case lir_logic_and: __ andl (reg, raddr); break; 2413 case lir_logic_or: __ orl (reg, raddr); break; 2414 case lir_logic_xor: __ xorl (reg, raddr); break; 2415 default: ShouldNotReachHere(); 2416 } 2417 } else { 2418 Register rright = right->as_register(); 2419 switch (code) { 2420 case lir_logic_and: __ andptr (reg, rright); break; 2421 case lir_logic_or : __ orptr (reg, rright); break; 2422 case lir_logic_xor: __ xorptr (reg, rright); break; 2423 default: ShouldNotReachHere(); 2424 } 2425 } 2426 move_regs(reg, dst->as_register()); 2427 } else { 2428 Register l_lo = left->as_register_lo(); 2429 Register l_hi = left->as_register_hi(); 2430 if (right->is_constant()) { 2431 #ifdef _LP64 2432 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2433 switch (code) { 2434 case lir_logic_and: 2435 __ andq(l_lo, rscratch1); 2436 break; 2437 case lir_logic_or: 2438 __ orq(l_lo, rscratch1); 2439 break; 2440 case lir_logic_xor: 2441 __ xorq(l_lo, rscratch1); 2442 break; 2443 default: ShouldNotReachHere(); 2444 } 2445 #else 2446 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2447 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2448 switch (code) { 2449 case lir_logic_and: 2450 __ andl(l_lo, r_lo); 2451 __ andl(l_hi, r_hi); 2452 break; 2453 case lir_logic_or: 2454 __ orl(l_lo, r_lo); 2455 __ orl(l_hi, r_hi); 2456 break; 2457 case lir_logic_xor: 2458 __ xorl(l_lo, r_lo); 2459 __ xorl(l_hi, r_hi); 2460 break; 2461 default: ShouldNotReachHere(); 2462 } 2463 #endif // _LP64 2464 } else { 2465 Register r_lo = right->as_register_lo(); 2466 Register r_hi = right->as_register_hi(); 2467 assert(l_lo != r_hi, "overwriting registers"); 2468 switch (code) { 2469 case lir_logic_and: 2470 __ andptr(l_lo, r_lo); 2471 NOT_LP64(__ andptr(l_hi, r_hi);) 2472 break; 2473 case lir_logic_or: 2474 __ orptr(l_lo, r_lo); 2475 NOT_LP64(__ orptr(l_hi, r_hi);) 2476 break; 2477 case lir_logic_xor: 2478 __ xorptr(l_lo, r_lo); 2479 NOT_LP64(__ xorptr(l_hi, r_hi);) 2480 break; 2481 default: ShouldNotReachHere(); 2482 } 2483 } 2484 2485 Register dst_lo = dst->as_register_lo(); 2486 Register dst_hi = dst->as_register_hi(); 2487 2488 #ifdef _LP64 2489 move_regs(l_lo, dst_lo); 2490 #else 2491 if (dst_lo == l_hi) { 2492 assert(dst_hi != l_lo, "overwriting registers"); 2493 move_regs(l_hi, dst_hi); 2494 move_regs(l_lo, dst_lo); 2495 } else { 2496 assert(dst_lo != l_hi, "overwriting registers"); 2497 move_regs(l_lo, dst_lo); 2498 move_regs(l_hi, dst_hi); 2499 } 2500 #endif // _LP64 2501 } 2502 } 2503 2504 2505 // we assume that rax, and rdx can be overwritten 2506 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2507 2508 assert(left->is_single_cpu(), "left must be register"); 2509 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2510 assert(result->is_single_cpu(), "result must be register"); 2511 2512 // assert(left->destroys_register(), "check"); 2513 // assert(right->destroys_register(), "check"); 2514 2515 Register lreg = left->as_register(); 2516 Register dreg = result->as_register(); 2517 2518 if (right->is_constant()) { 2519 int divisor = right->as_constant_ptr()->as_jint(); 2520 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2521 if (code == lir_idiv) { 2522 assert(lreg == rax, "must be rax,"); 2523 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2524 __ cdql(); // sign extend into rdx:rax 2525 if (divisor == 2) { 2526 __ subl(lreg, rdx); 2527 } else { 2528 __ andl(rdx, divisor - 1); 2529 __ addl(lreg, rdx); 2530 } 2531 __ sarl(lreg, log2_intptr(divisor)); 2532 move_regs(lreg, dreg); 2533 } else if (code == lir_irem) { 2534 Label done; 2535 __ mov(dreg, lreg); 2536 __ andl(dreg, 0x80000000 | (divisor - 1)); 2537 __ jcc(Assembler::positive, done); 2538 __ decrement(dreg); 2539 __ orl(dreg, ~(divisor - 1)); 2540 __ increment(dreg); 2541 __ bind(done); 2542 } else { 2543 ShouldNotReachHere(); 2544 } 2545 } else { 2546 Register rreg = right->as_register(); 2547 assert(lreg == rax, "left register must be rax,"); 2548 assert(rreg != rdx, "right register must not be rdx"); 2549 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2550 2551 move_regs(lreg, rax); 2552 2553 int idivl_offset = __ corrected_idivl(rreg); 2554 add_debug_info_for_div0(idivl_offset, info); 2555 if (code == lir_irem) { 2556 move_regs(rdx, dreg); // result is in rdx 2557 } else { 2558 move_regs(rax, dreg); 2559 } 2560 } 2561 } 2562 2563 2564 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2565 if (opr1->is_single_cpu()) { 2566 Register reg1 = opr1->as_register(); 2567 if (opr2->is_single_cpu()) { 2568 // cpu register - cpu register 2569 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2570 __ cmpptr(reg1, opr2->as_register()); 2571 } else { 2572 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2573 __ cmpl(reg1, opr2->as_register()); 2574 } 2575 } else if (opr2->is_stack()) { 2576 // cpu register - stack 2577 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2578 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2579 } else { 2580 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2581 } 2582 } else if (opr2->is_constant()) { 2583 // cpu register - constant 2584 LIR_Const* c = opr2->as_constant_ptr(); 2585 if (c->type() == T_INT) { 2586 __ cmpl(reg1, c->as_jint()); 2587 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2588 // In 64bit oops are single register 2589 jobject o = c->as_jobject(); 2590 if (o == NULL) { 2591 __ cmpptr(reg1, (int32_t)NULL_WORD); 2592 } else { 2593 #ifdef _LP64 2594 __ movoop(rscratch1, o); 2595 __ cmpptr(reg1, rscratch1); 2596 #else 2597 __ cmpoop(reg1, c->as_jobject()); 2598 #endif // _LP64 2599 } 2600 } else { 2601 ShouldNotReachHere(); 2602 } 2603 // cpu register - address 2604 } else if (opr2->is_address()) { 2605 if (op->info() != NULL) { 2606 add_debug_info_for_null_check_here(op->info()); 2607 } 2608 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2609 } else { 2610 ShouldNotReachHere(); 2611 } 2612 2613 } else if(opr1->is_double_cpu()) { 2614 Register xlo = opr1->as_register_lo(); 2615 Register xhi = opr1->as_register_hi(); 2616 if (opr2->is_double_cpu()) { 2617 #ifdef _LP64 2618 __ cmpptr(xlo, opr2->as_register_lo()); 2619 #else 2620 // cpu register - cpu register 2621 Register ylo = opr2->as_register_lo(); 2622 Register yhi = opr2->as_register_hi(); 2623 __ subl(xlo, ylo); 2624 __ sbbl(xhi, yhi); 2625 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2626 __ orl(xhi, xlo); 2627 } 2628 #endif // _LP64 2629 } else if (opr2->is_constant()) { 2630 // cpu register - constant 0 2631 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2632 #ifdef _LP64 2633 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2634 #else 2635 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2636 __ orl(xhi, xlo); 2637 #endif // _LP64 2638 } else { 2639 ShouldNotReachHere(); 2640 } 2641 2642 } else if (opr1->is_single_xmm()) { 2643 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2644 if (opr2->is_single_xmm()) { 2645 // xmm register - xmm register 2646 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2647 } else if (opr2->is_stack()) { 2648 // xmm register - stack 2649 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2650 } else if (opr2->is_constant()) { 2651 // xmm register - constant 2652 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2653 } else if (opr2->is_address()) { 2654 // xmm register - address 2655 if (op->info() != NULL) { 2656 add_debug_info_for_null_check_here(op->info()); 2657 } 2658 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2659 } else { 2660 ShouldNotReachHere(); 2661 } 2662 2663 } else if (opr1->is_double_xmm()) { 2664 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2665 if (opr2->is_double_xmm()) { 2666 // xmm register - xmm register 2667 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2668 } else if (opr2->is_stack()) { 2669 // xmm register - stack 2670 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2671 } else if (opr2->is_constant()) { 2672 // xmm register - constant 2673 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2674 } else if (opr2->is_address()) { 2675 // xmm register - address 2676 if (op->info() != NULL) { 2677 add_debug_info_for_null_check_here(op->info()); 2678 } 2679 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2680 } else { 2681 ShouldNotReachHere(); 2682 } 2683 2684 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2685 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2686 assert(opr2->is_fpu_register(), "both must be registers"); 2687 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2688 2689 } else if (opr1->is_address() && opr2->is_constant()) { 2690 LIR_Const* c = opr2->as_constant_ptr(); 2691 #ifdef _LP64 2692 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2693 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2694 __ movoop(rscratch1, c->as_jobject()); 2695 } 2696 #endif // LP64 2697 if (op->info() != NULL) { 2698 add_debug_info_for_null_check_here(op->info()); 2699 } 2700 // special case: address - constant 2701 LIR_Address* addr = opr1->as_address_ptr(); 2702 if (c->type() == T_INT) { 2703 __ cmpl(as_Address(addr), c->as_jint()); 2704 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2705 #ifdef _LP64 2706 // %%% Make this explode if addr isn't reachable until we figure out a 2707 // better strategy by giving noreg as the temp for as_Address 2708 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2709 #else 2710 __ cmpoop(as_Address(addr), c->as_jobject()); 2711 #endif // _LP64 2712 } else { 2713 ShouldNotReachHere(); 2714 } 2715 2716 } else { 2717 ShouldNotReachHere(); 2718 } 2719 } 2720 2721 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2722 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2723 if (left->is_single_xmm()) { 2724 assert(right->is_single_xmm(), "must match"); 2725 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2726 } else if (left->is_double_xmm()) { 2727 assert(right->is_double_xmm(), "must match"); 2728 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2729 2730 } else { 2731 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2732 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2733 2734 assert(left->fpu() == 0, "left must be on TOS"); 2735 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2736 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2737 } 2738 } else { 2739 assert(code == lir_cmp_l2i, "check"); 2740 #ifdef _LP64 2741 Label done; 2742 Register dest = dst->as_register(); 2743 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2744 __ movl(dest, -1); 2745 __ jccb(Assembler::less, done); 2746 __ set_byte_if_not_zero(dest); 2747 __ movzbl(dest, dest); 2748 __ bind(done); 2749 #else 2750 __ lcmp2int(left->as_register_hi(), 2751 left->as_register_lo(), 2752 right->as_register_hi(), 2753 right->as_register_lo()); 2754 move_regs(left->as_register_hi(), dst->as_register()); 2755 #endif // _LP64 2756 } 2757 } 2758 2759 2760 void LIR_Assembler::align_call(LIR_Code code) { 2761 if (os::is_MP()) { 2762 // make sure that the displacement word of the call ends up word aligned 2763 int offset = __ offset(); 2764 switch (code) { 2765 case lir_static_call: 2766 case lir_optvirtual_call: 2767 case lir_dynamic_call: 2768 offset += NativeCall::displacement_offset; 2769 break; 2770 case lir_icvirtual_call: 2771 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2772 break; 2773 case lir_virtual_call: // currently, sparc-specific for niagara 2774 default: ShouldNotReachHere(); 2775 } 2776 while (offset++ % BytesPerWord != 0) { 2777 __ nop(); 2778 } 2779 } 2780 } 2781 2782 2783 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2784 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2785 "must be aligned"); 2786 __ call(AddressLiteral(op->addr(), rtype)); 2787 add_call_info(code_offset(), op->info()); 2788 } 2789 2790 2791 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2792 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2793 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); 2794 assert(!os::is_MP() || 2795 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2796 "must be aligned"); 2797 __ call(AddressLiteral(op->addr(), rh)); 2798 add_call_info(code_offset(), op->info()); 2799 } 2800 2801 2802 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2803 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2804 ShouldNotReachHere(); 2805 } 2806 2807 2808 void LIR_Assembler::emit_static_call_stub() { 2809 address call_pc = __ pc(); 2810 address stub = __ start_a_stub(call_stub_size); 2811 if (stub == NULL) { 2812 bailout("static call stub overflow"); 2813 return; 2814 } 2815 2816 int start = __ offset(); 2817 if (os::is_MP()) { 2818 // make sure that the displacement word of the call ends up word aligned 2819 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2820 while (offset++ % BytesPerWord != 0) { 2821 __ nop(); 2822 } 2823 } 2824 __ relocate(static_stub_Relocation::spec(call_pc)); 2825 __ movoop(rbx, (jobject)NULL); 2826 // must be set to -1 at code generation time 2827 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2828 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2829 __ jump(RuntimeAddress(__ pc())); 2830 2831 assert(__ offset() - start <= call_stub_size, "stub too big"); 2832 __ end_a_stub(); 2833 } 2834 2835 2836 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2837 assert(exceptionOop->as_register() == rax, "must match"); 2838 assert(exceptionPC->as_register() == rdx, "must match"); 2839 2840 // exception object is not added to oop map by LinearScan 2841 // (LinearScan assumes that no oops are in fixed registers) 2842 info->add_register_oop(exceptionOop); 2843 Runtime1::StubID unwind_id; 2844 2845 // get current pc information 2846 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2847 int pc_for_athrow_offset = __ offset(); 2848 InternalAddress pc_for_athrow(__ pc()); 2849 __ lea(exceptionPC->as_register(), pc_for_athrow); 2850 add_call_info(pc_for_athrow_offset, info); // for exception handler 2851 2852 __ verify_not_null_oop(rax); 2853 // search an exception handler (rax: exception oop, rdx: throwing pc) 2854 if (compilation()->has_fpu_code()) { 2855 unwind_id = Runtime1::handle_exception_id; 2856 } else { 2857 unwind_id = Runtime1::handle_exception_nofpu_id; 2858 } 2859 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2860 2861 // enough room for two byte trap 2862 __ nop(); 2863 } 2864 2865 2866 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2867 assert(exceptionOop->as_register() == rax, "must match"); 2868 2869 __ jmp(_unwind_handler_entry); 2870 } 2871 2872 2873 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2874 2875 // optimized version for linear scan: 2876 // * count must be already in ECX (guaranteed by LinearScan) 2877 // * left and dest must be equal 2878 // * tmp must be unused 2879 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2880 assert(left == dest, "left and dest must be equal"); 2881 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2882 2883 if (left->is_single_cpu()) { 2884 Register value = left->as_register(); 2885 assert(value != SHIFT_count, "left cannot be ECX"); 2886 2887 switch (code) { 2888 case lir_shl: __ shll(value); break; 2889 case lir_shr: __ sarl(value); break; 2890 case lir_ushr: __ shrl(value); break; 2891 default: ShouldNotReachHere(); 2892 } 2893 } else if (left->is_double_cpu()) { 2894 Register lo = left->as_register_lo(); 2895 Register hi = left->as_register_hi(); 2896 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2897 #ifdef _LP64 2898 switch (code) { 2899 case lir_shl: __ shlptr(lo); break; 2900 case lir_shr: __ sarptr(lo); break; 2901 case lir_ushr: __ shrptr(lo); break; 2902 default: ShouldNotReachHere(); 2903 } 2904 #else 2905 2906 switch (code) { 2907 case lir_shl: __ lshl(hi, lo); break; 2908 case lir_shr: __ lshr(hi, lo, true); break; 2909 case lir_ushr: __ lshr(hi, lo, false); break; 2910 default: ShouldNotReachHere(); 2911 } 2912 #endif // LP64 2913 } else { 2914 ShouldNotReachHere(); 2915 } 2916 } 2917 2918 2919 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2920 if (dest->is_single_cpu()) { 2921 // first move left into dest so that left is not destroyed by the shift 2922 Register value = dest->as_register(); 2923 count = count & 0x1F; // Java spec 2924 2925 move_regs(left->as_register(), value); 2926 switch (code) { 2927 case lir_shl: __ shll(value, count); break; 2928 case lir_shr: __ sarl(value, count); break; 2929 case lir_ushr: __ shrl(value, count); break; 2930 default: ShouldNotReachHere(); 2931 } 2932 } else if (dest->is_double_cpu()) { 2933 #ifndef _LP64 2934 Unimplemented(); 2935 #else 2936 // first move left into dest so that left is not destroyed by the shift 2937 Register value = dest->as_register_lo(); 2938 count = count & 0x1F; // Java spec 2939 2940 move_regs(left->as_register_lo(), value); 2941 switch (code) { 2942 case lir_shl: __ shlptr(value, count); break; 2943 case lir_shr: __ sarptr(value, count); break; 2944 case lir_ushr: __ shrptr(value, count); break; 2945 default: ShouldNotReachHere(); 2946 } 2947 #endif // _LP64 2948 } else { 2949 ShouldNotReachHere(); 2950 } 2951 } 2952 2953 2954 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2955 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2956 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2957 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2958 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2959 } 2960 2961 2962 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2963 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2964 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2965 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2966 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 2967 } 2968 2969 2970 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2971 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2972 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2973 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2974 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 2975 } 2976 2977 2978 // This code replaces a call to arraycopy; no exception may 2979 // be thrown in this code, they must be thrown in the System.arraycopy 2980 // activation frame; we could save some checks if this would not be the case 2981 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2982 ciArrayKlass* default_type = op->expected_type(); 2983 Register src = op->src()->as_register(); 2984 Register dst = op->dst()->as_register(); 2985 Register src_pos = op->src_pos()->as_register(); 2986 Register dst_pos = op->dst_pos()->as_register(); 2987 Register length = op->length()->as_register(); 2988 Register tmp = op->tmp()->as_register(); 2989 2990 CodeStub* stub = op->stub(); 2991 int flags = op->flags(); 2992 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2993 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 2994 2995 // if we don't know anything or it's an object array, just go through the generic arraycopy 2996 if (default_type == NULL) { 2997 Label done; 2998 // save outgoing arguments on stack in case call to System.arraycopy is needed 2999 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3000 // for interpreter calling conventions. Now we have to do it in new style conventions. 3001 // For the moment until C1 gets the new register allocator I just force all the 3002 // args to the right place (except the register args) and then on the back side 3003 // reload the register args properly if we go slow path. Yuck 3004 3005 // These are proper for the calling convention 3006 3007 store_parameter(length, 2); 3008 store_parameter(dst_pos, 1); 3009 store_parameter(dst, 0); 3010 3011 // these are just temporary placements until we need to reload 3012 store_parameter(src_pos, 3); 3013 store_parameter(src, 4); 3014 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3015 3016 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3017 3018 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3019 #ifdef _LP64 3020 // The arguments are in java calling convention so we can trivially shift them to C 3021 // convention 3022 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3023 __ mov(c_rarg0, j_rarg0); 3024 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3025 __ mov(c_rarg1, j_rarg1); 3026 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3027 __ mov(c_rarg2, j_rarg2); 3028 assert_different_registers(c_rarg3, j_rarg4); 3029 __ mov(c_rarg3, j_rarg3); 3030 #ifdef _WIN64 3031 // Allocate abi space for args but be sure to keep stack aligned 3032 __ subptr(rsp, 6*wordSize); 3033 store_parameter(j_rarg4, 4); 3034 __ call(RuntimeAddress(entry)); 3035 __ addptr(rsp, 6*wordSize); 3036 #else 3037 __ mov(c_rarg4, j_rarg4); 3038 __ call(RuntimeAddress(entry)); 3039 #endif // _WIN64 3040 #else 3041 __ push(length); 3042 __ push(dst_pos); 3043 __ push(dst); 3044 __ push(src_pos); 3045 __ push(src); 3046 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack 3047 3048 #endif // _LP64 3049 3050 __ cmpl(rax, 0); 3051 __ jcc(Assembler::equal, *stub->continuation()); 3052 3053 // Reload values from the stack so they are where the stub 3054 // expects them. 3055 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3056 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3057 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3058 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3059 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3060 __ jmp(*stub->entry()); 3061 3062 __ bind(*stub->continuation()); 3063 return; 3064 } 3065 3066 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3067 3068 int elem_size = type2aelembytes(basic_type); 3069 int shift_amount; 3070 Address::ScaleFactor scale; 3071 3072 switch (elem_size) { 3073 case 1 : 3074 shift_amount = 0; 3075 scale = Address::times_1; 3076 break; 3077 case 2 : 3078 shift_amount = 1; 3079 scale = Address::times_2; 3080 break; 3081 case 4 : 3082 shift_amount = 2; 3083 scale = Address::times_4; 3084 break; 3085 case 8 : 3086 shift_amount = 3; 3087 scale = Address::times_8; 3088 break; 3089 default: 3090 ShouldNotReachHere(); 3091 } 3092 3093 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3094 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3095 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3096 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3097 3098 // length and pos's are all sign extended at this point on 64bit 3099 3100 // test for NULL 3101 if (flags & LIR_OpArrayCopy::src_null_check) { 3102 __ testptr(src, src); 3103 __ jcc(Assembler::zero, *stub->entry()); 3104 } 3105 if (flags & LIR_OpArrayCopy::dst_null_check) { 3106 __ testptr(dst, dst); 3107 __ jcc(Assembler::zero, *stub->entry()); 3108 } 3109 3110 // check if negative 3111 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3112 __ testl(src_pos, src_pos); 3113 __ jcc(Assembler::less, *stub->entry()); 3114 } 3115 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3116 __ testl(dst_pos, dst_pos); 3117 __ jcc(Assembler::less, *stub->entry()); 3118 } 3119 if (flags & LIR_OpArrayCopy::length_positive_check) { 3120 __ testl(length, length); 3121 __ jcc(Assembler::less, *stub->entry()); 3122 } 3123 3124 if (flags & LIR_OpArrayCopy::src_range_check) { 3125 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3126 __ cmpl(tmp, src_length_addr); 3127 __ jcc(Assembler::above, *stub->entry()); 3128 } 3129 if (flags & LIR_OpArrayCopy::dst_range_check) { 3130 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3131 __ cmpl(tmp, dst_length_addr); 3132 __ jcc(Assembler::above, *stub->entry()); 3133 } 3134 3135 if (flags & LIR_OpArrayCopy::type_check) { 3136 __ movptr(tmp, src_klass_addr); 3137 __ cmpptr(tmp, dst_klass_addr); 3138 __ jcc(Assembler::notEqual, *stub->entry()); 3139 } 3140 3141 #ifdef ASSERT 3142 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3143 // Sanity check the known type with the incoming class. For the 3144 // primitive case the types must match exactly with src.klass and 3145 // dst.klass each exactly matching the default type. For the 3146 // object array case, if no type check is needed then either the 3147 // dst type is exactly the expected type and the src type is a 3148 // subtype which we can't check or src is the same array as dst 3149 // but not necessarily exactly of type default_type. 3150 Label known_ok, halt; 3151 __ movoop(tmp, default_type->constant_encoding()); 3152 if (basic_type != T_OBJECT) { 3153 __ cmpptr(tmp, dst_klass_addr); 3154 __ jcc(Assembler::notEqual, halt); 3155 __ cmpptr(tmp, src_klass_addr); 3156 __ jcc(Assembler::equal, known_ok); 3157 } else { 3158 __ cmpptr(tmp, dst_klass_addr); 3159 __ jcc(Assembler::equal, known_ok); 3160 __ cmpptr(src, dst); 3161 __ jcc(Assembler::equal, known_ok); 3162 } 3163 __ bind(halt); 3164 __ stop("incorrect type information in arraycopy"); 3165 __ bind(known_ok); 3166 } 3167 #endif 3168 3169 if (shift_amount > 0 && basic_type != T_OBJECT) { 3170 __ shlptr(length, shift_amount); 3171 } 3172 3173 #ifdef _LP64 3174 assert_different_registers(c_rarg0, dst, dst_pos, length); 3175 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3176 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3177 assert_different_registers(c_rarg1, length); 3178 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3179 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3180 __ mov(c_rarg2, length); 3181 3182 #else 3183 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3184 store_parameter(tmp, 0); 3185 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3186 store_parameter(tmp, 1); 3187 store_parameter(length, 2); 3188 #endif // _LP64 3189 if (basic_type == T_OBJECT) { 3190 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); 3191 } else { 3192 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); 3193 } 3194 3195 __ bind(*stub->continuation()); 3196 } 3197 3198 3199 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3200 Register obj = op->obj_opr()->as_register(); // may not be an oop 3201 Register hdr = op->hdr_opr()->as_register(); 3202 Register lock = op->lock_opr()->as_register(); 3203 if (!UseFastLocking) { 3204 __ jmp(*op->stub()->entry()); 3205 } else if (op->code() == lir_lock) { 3206 Register scratch = noreg; 3207 if (UseBiasedLocking) { 3208 scratch = op->scratch_opr()->as_register(); 3209 } 3210 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3211 // add debug info for NullPointerException only if one is possible 3212 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3213 if (op->info() != NULL) { 3214 add_debug_info_for_null_check(null_check_offset, op->info()); 3215 } 3216 // done 3217 } else if (op->code() == lir_unlock) { 3218 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3219 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3220 } else { 3221 Unimplemented(); 3222 } 3223 __ bind(*op->stub()->continuation()); 3224 } 3225 3226 3227 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3228 ciMethod* method = op->profiled_method(); 3229 int bci = op->profiled_bci(); 3230 3231 // Update counter for all call types 3232 ciMethodData* md = method->method_data(); 3233 if (md == NULL) { 3234 bailout("out of memory building methodDataOop"); 3235 return; 3236 } 3237 ciProfileData* data = md->bci_to_data(bci); 3238 assert(data->is_CounterData(), "need CounterData for calls"); 3239 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3240 Register mdo = op->mdo()->as_register(); 3241 __ movoop(mdo, md->constant_encoding()); 3242 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3243 Bytecodes::Code bc = method->java_code_at_bci(bci); 3244 // Perform additional virtual call profiling for invokevirtual and 3245 // invokeinterface bytecodes 3246 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3247 Tier1ProfileVirtualCalls) { 3248 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3249 Register recv = op->recv()->as_register(); 3250 assert_different_registers(mdo, recv); 3251 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3252 ciKlass* known_klass = op->known_holder(); 3253 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { 3254 // We know the type that will be seen at this call site; we can 3255 // statically update the methodDataOop rather than needing to do 3256 // dynamic tests on the receiver type 3257 3258 // NOTE: we should probably put a lock around this search to 3259 // avoid collisions by concurrent compilations 3260 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3261 uint i; 3262 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3263 ciKlass* receiver = vc_data->receiver(i); 3264 if (known_klass->equals(receiver)) { 3265 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3266 __ addl(data_addr, DataLayout::counter_increment); 3267 return; 3268 } 3269 } 3270 3271 // Receiver type not found in profile data; select an empty slot 3272 3273 // Note that this is less efficient than it should be because it 3274 // always does a write to the receiver part of the 3275 // VirtualCallData rather than just the first time 3276 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3277 ciKlass* receiver = vc_data->receiver(i); 3278 if (receiver == NULL) { 3279 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3280 __ movoop(recv_addr, known_klass->constant_encoding()); 3281 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3282 __ addl(data_addr, DataLayout::counter_increment); 3283 return; 3284 } 3285 } 3286 } else { 3287 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); 3288 Label update_done; 3289 uint i; 3290 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3291 Label next_test; 3292 // See if the receiver is receiver[n]. 3293 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); 3294 __ jcc(Assembler::notEqual, next_test); 3295 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3296 __ addl(data_addr, DataLayout::counter_increment); 3297 __ jmp(update_done); 3298 __ bind(next_test); 3299 } 3300 3301 // Didn't find receiver; find next empty slot and fill it in 3302 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3303 Label next_test; 3304 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3305 __ cmpptr(recv_addr, (int32_t)NULL_WORD); 3306 __ jcc(Assembler::notEqual, next_test); 3307 __ movptr(recv_addr, recv); 3308 __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); 3309 __ jmp(update_done); 3310 __ bind(next_test); 3311 } 3312 // Receiver did not match any saved receiver and there is no empty row for it. 3313 // Increment total counter to indicate polymorphic case. 3314 __ addl(counter_addr, DataLayout::counter_increment); 3315 3316 __ bind(update_done); 3317 } 3318 } else { 3319 // Static call 3320 __ addl(counter_addr, DataLayout::counter_increment); 3321 } 3322 } 3323 3324 3325 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3326 Unimplemented(); 3327 } 3328 3329 3330 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3331 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3332 } 3333 3334 3335 void LIR_Assembler::align_backward_branch_target() { 3336 __ align(BytesPerWord); 3337 } 3338 3339 3340 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3341 if (left->is_single_cpu()) { 3342 __ negl(left->as_register()); 3343 move_regs(left->as_register(), dest->as_register()); 3344 3345 } else if (left->is_double_cpu()) { 3346 Register lo = left->as_register_lo(); 3347 #ifdef _LP64 3348 Register dst = dest->as_register_lo(); 3349 __ movptr(dst, lo); 3350 __ negptr(dst); 3351 #else 3352 Register hi = left->as_register_hi(); 3353 __ lneg(hi, lo); 3354 if (dest->as_register_lo() == hi) { 3355 assert(dest->as_register_hi() != lo, "destroying register"); 3356 move_regs(hi, dest->as_register_hi()); 3357 move_regs(lo, dest->as_register_lo()); 3358 } else { 3359 move_regs(lo, dest->as_register_lo()); 3360 move_regs(hi, dest->as_register_hi()); 3361 } 3362 #endif // _LP64 3363 3364 } else if (dest->is_single_xmm()) { 3365 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3366 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3367 } 3368 __ xorps(dest->as_xmm_float_reg(), 3369 ExternalAddress((address)float_signflip_pool)); 3370 3371 } else if (dest->is_double_xmm()) { 3372 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3373 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3374 } 3375 __ xorpd(dest->as_xmm_double_reg(), 3376 ExternalAddress((address)double_signflip_pool)); 3377 3378 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3379 assert(left->fpu() == 0, "arg must be on TOS"); 3380 assert(dest->fpu() == 0, "dest must be TOS"); 3381 __ fchs(); 3382 3383 } else { 3384 ShouldNotReachHere(); 3385 } 3386 } 3387 3388 3389 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3390 assert(addr->is_address() && dest->is_register(), "check"); 3391 Register reg; 3392 reg = dest->as_pointer_register(); 3393 __ lea(reg, as_Address(addr->as_address_ptr())); 3394 } 3395 3396 3397 3398 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3399 assert(!tmp->is_valid(), "don't need temporary"); 3400 __ call(RuntimeAddress(dest)); 3401 if (info != NULL) { 3402 add_call_info_here(info); 3403 } 3404 } 3405 3406 3407 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3408 assert(type == T_LONG, "only for volatile long fields"); 3409 3410 if (info != NULL) { 3411 add_debug_info_for_null_check_here(info); 3412 } 3413 3414 if (src->is_double_xmm()) { 3415 if (dest->is_double_cpu()) { 3416 #ifdef _LP64 3417 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3418 #else 3419 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3420 __ psrlq(src->as_xmm_double_reg(), 32); 3421 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3422 #endif // _LP64 3423 } else if (dest->is_double_stack()) { 3424 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3425 } else if (dest->is_address()) { 3426 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3427 } else { 3428 ShouldNotReachHere(); 3429 } 3430 3431 } else if (dest->is_double_xmm()) { 3432 if (src->is_double_stack()) { 3433 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3434 } else if (src->is_address()) { 3435 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3436 } else { 3437 ShouldNotReachHere(); 3438 } 3439 3440 } else if (src->is_double_fpu()) { 3441 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3442 if (dest->is_double_stack()) { 3443 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3444 } else if (dest->is_address()) { 3445 __ fistp_d(as_Address(dest->as_address_ptr())); 3446 } else { 3447 ShouldNotReachHere(); 3448 } 3449 3450 } else if (dest->is_double_fpu()) { 3451 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3452 if (src->is_double_stack()) { 3453 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3454 } else if (src->is_address()) { 3455 __ fild_d(as_Address(src->as_address_ptr())); 3456 } else { 3457 ShouldNotReachHere(); 3458 } 3459 } else { 3460 ShouldNotReachHere(); 3461 } 3462 } 3463 3464 3465 void LIR_Assembler::membar() { 3466 // QQQ sparc TSO uses this, 3467 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3468 } 3469 3470 void LIR_Assembler::membar_acquire() { 3471 // No x86 machines currently require load fences 3472 // __ load_fence(); 3473 } 3474 3475 void LIR_Assembler::membar_release() { 3476 // No x86 machines currently require store fences 3477 // __ store_fence(); 3478 } 3479 3480 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3481 assert(result_reg->is_register(), "check"); 3482 #ifdef _LP64 3483 // __ get_thread(result_reg->as_register_lo()); 3484 __ mov(result_reg->as_register(), r15_thread); 3485 #else 3486 __ get_thread(result_reg->as_register()); 3487 #endif // _LP64 3488 } 3489 3490 3491 void LIR_Assembler::peephole(LIR_List*) { 3492 // do nothing for now 3493 } 3494 3495 3496 #undef __