1 /*
2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_x86.cpp.incl"
27
28
29 // These masks are used to provide 128-bit aligned bitmasks to the XMM
30 // instructions, to allow sign-masking or sign-bit flipping. They allow
31 // fast versions of NegF/NegD and AbsF/AbsD.
32
33 // Note: 'double' and 'long long' have 32-bits alignment on x86.
34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
36 // of 128-bits operands for SSE instructions.
37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
38 // Store the value to a 128-bits operand.
39 operand[0] = lo;
40 operand[1] = hi;
41 return operand;
42 }
43
44 // Buffer for 128-bits masks used by SSE instructions.
45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
46
47 // Static initialization during VM startup.
48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
52
53
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rax; // where the IC klass is cached
57 const Register SYNC_header = rax; // synchronization header
58 const Register SHIFT_count = rcx; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
100 if (opr->is_constant()) {
101 LIR_Const* constant = opr->as_constant_ptr();
102 switch (constant->type()) {
103 case T_INT: {
104 return true;
105 }
106
107 default:
108 return false;
109 }
110 }
111 return false;
112 }
113
114
115 LIR_Opr LIR_Assembler::receiverOpr() {
116 return FrameMap::receiver_opr;
117 }
118
119 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
120 return receiverOpr();
121 }
122
123 LIR_Opr LIR_Assembler::osrBufferPointer() {
124 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
125 }
126
127 //--------------fpu register translations-----------------------
128
129
130 address LIR_Assembler::float_constant(float f) {
131 address const_addr = __ float_constant(f);
132 if (const_addr == NULL) {
133 bailout("const section overflow");
134 return __ code()->consts()->start();
135 } else {
136 return const_addr;
137 }
138 }
139
140
141 address LIR_Assembler::double_constant(double d) {
142 address const_addr = __ double_constant(d);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 void LIR_Assembler::set_24bit_FPU() {
153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
154 }
155
156 void LIR_Assembler::reset_FPU() {
157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
158 }
159
160 void LIR_Assembler::fpop() {
161 __ fpop();
162 }
163
164 void LIR_Assembler::fxch(int i) {
165 __ fxch(i);
166 }
167
168 void LIR_Assembler::fld(int i) {
169 __ fld_s(i);
170 }
171
172 void LIR_Assembler::ffree(int i) {
173 __ ffree(i);
174 }
175
176 void LIR_Assembler::breakpoint() {
177 __ int3();
178 }
179
180 void LIR_Assembler::push(LIR_Opr opr) {
181 if (opr->is_single_cpu()) {
182 __ push_reg(opr->as_register());
183 } else if (opr->is_double_cpu()) {
184 NOT_LP64(__ push_reg(opr->as_register_hi()));
185 __ push_reg(opr->as_register_lo());
186 } else if (opr->is_stack()) {
187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
188 } else if (opr->is_constant()) {
189 LIR_Const* const_opr = opr->as_constant_ptr();
190 if (const_opr->type() == T_OBJECT) {
191 __ push_oop(const_opr->as_jobject());
192 } else if (const_opr->type() == T_INT) {
193 __ push_jint(const_opr->as_jint());
194 } else {
195 ShouldNotReachHere();
196 }
197
198 } else {
199 ShouldNotReachHere();
200 }
201 }
202
203 void LIR_Assembler::pop(LIR_Opr opr) {
204 if (opr->is_single_cpu()) {
205 __ pop_reg(opr->as_register());
206 } else {
207 ShouldNotReachHere();
208 }
209 }
210
211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
212 return addr->base()->is_illegal() && addr->index()->is_illegal();
213 }
214
215 //-------------------------------------------
216
217 Address LIR_Assembler::as_Address(LIR_Address* addr) {
218 return as_Address(addr, rscratch1);
219 }
220
221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
222 if (addr->base()->is_illegal()) {
223 assert(addr->index()->is_illegal(), "must be illegal too");
224 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
225 if (! __ reachable(laddr)) {
226 __ movptr(tmp, laddr.addr());
227 Address res(tmp, 0);
228 return res;
229 } else {
230 return __ as_Address(laddr);
231 }
232 }
233
234 Register base = addr->base()->as_pointer_register();
235
236 if (addr->index()->is_illegal()) {
237 return Address( base, addr->disp());
238 } else if (addr->index()->is_cpu_register()) {
239 Register index = addr->index()->as_pointer_register();
240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
241 } else if (addr->index()->is_constant()) {
242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
243 assert(Assembler::is_simm32(addr_offset), "must be");
244
245 return Address(base, addr_offset);
246 } else {
247 Unimplemented();
248 return Address();
249 }
250 }
251
252
253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
254 Address base = as_Address(addr);
255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
256 }
257
258
259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
260 return as_Address(addr);
261 }
262
263
264 void LIR_Assembler::osr_entry() {
265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
266 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
267 ValueStack* entry_state = osr_entry->state();
268 int number_of_locks = entry_state->locks_size();
269
270 // we jump here if osr happens with the interpreter
271 // state set up to continue at the beginning of the
272 // loop that triggered osr - in particular, we have
273 // the following registers setup:
274 //
275 // rcx: osr buffer
276 //
277
278 // build frame
279 ciMethod* m = compilation()->method();
280 __ build_frame(initial_frame_size_in_bytes());
281
282 // OSR buffer is
283 //
284 // locals[nlocals-1..0]
285 // monitors[0..number_of_locks]
286 //
287 // locals is a direct copy of the interpreter frame so in the osr buffer
288 // so first slot in the local array is the last local from the interpreter
289 // and last slot is local[0] (receiver) from the interpreter
290 //
291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
293 // in the interpreter frame (the method lock if a sync method)
294
295 // Initialize monitors in the compiled activation.
296 // rcx: pointer to osr buffer
297 //
298 // All other registers are dead at this point and the locals will be
299 // copied into place by code emitted in the IR.
300
301 Register OSR_buf = osrBufferPointer()->as_pointer_register();
302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
303 int monitor_offset = BytesPerWord * method()->max_locals() +
304 (2 * BytesPerWord) * (number_of_locks - 1);
305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
306 // the OSR buffer using 2 word entries: first the lock and then
307 // the oop.
308 for (int i = 0; i < number_of_locks; i++) {
309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
310 #ifdef ASSERT
311 // verify the interpreter's monitor has a non-null object
312 {
313 Label L;
314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
315 __ jcc(Assembler::notZero, L);
316 __ stop("locked object is NULL");
317 __ bind(L);
318 }
319 #endif
320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
323 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
324 }
325 }
326 }
327
328
329 // inline cache check; done before the frame is built.
330 int LIR_Assembler::check_icache() {
331 Register receiver = FrameMap::receiver_opr->as_register();
332 Register ic_klass = IC_Klass;
333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
334
335 if (!VerifyOops) {
336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
338 __ nop();
339 }
340 }
341 int offset = __ offset();
342 __ inline_cache_check(receiver, IC_Klass);
343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
344 if (VerifyOops) {
345 // force alignment after the cache check.
346 // It's been verified to be aligned if !VerifyOops
347 __ align(CodeEntryAlignment);
348 }
349 return offset;
350 }
351
352
353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
354 jobject o = NULL;
355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
356 __ movoop(reg, o);
357 patching_epilog(patch, lir_patch_normal, reg, info);
358 }
359
360
361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
362 if (exception->is_valid()) {
363 // preserve exception
364 // note: the monitor_exit runtime call is a leaf routine
365 // and cannot block => no GC can happen
366 // The slow case (MonitorAccessStub) uses the first two stack slots
367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
368 __ movptr (Address(rsp, 2*wordSize), exception);
369 }
370
371 Register obj_reg = obj_opr->as_register();
372 Register lock_reg = lock_opr->as_register();
373
374 // setup registers (lock_reg must be rax, for lock_object)
375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
376 Register hdr = lock_reg;
377 assert(new_hdr == SYNC_header, "wrong register");
378 lock_reg = new_hdr;
379 // compute pointer to BasicLock
380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
381 __ lea(lock_reg, lock_addr);
382 // unlock object
383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
384 // _slow_case_stubs->append(slow_case);
385 // temporary fix: must be created after exceptionhandler, therefore as call stub
386 _slow_case_stubs->append(slow_case);
387 if (UseFastLocking) {
388 // try inlined fast unlocking first, revert to slow locking if it fails
389 // note: lock_reg points to the displaced header since the displaced header offset is 0!
390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
392 } else {
393 // always do slow unlocking
394 // note: the slow unlocking code could be inlined here, however if we use
395 // slow unlocking, speed doesn't matter anyway and this solution is
396 // simpler and requires less duplicated code - additionally, the
397 // slow unlocking code is the same in either case which simplifies
398 // debugging
399 __ jmp(*slow_case->entry());
400 }
401 // done
402 __ bind(*slow_case->continuation());
403
404 if (exception->is_valid()) {
405 // restore exception
406 __ movptr (exception, Address(rsp, 2 * wordSize));
407 }
408 }
409
410 // This specifies the rsp decrement needed to build the frame
411 int LIR_Assembler::initial_frame_size_in_bytes() {
412 // if rounding, must let FrameMap know!
413
414 // The frame_map records size in slots (32bit word)
415
416 // subtract two words to account for return address and link
417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
418 }
419
420
421 int LIR_Assembler::emit_exception_handler() {
422 // if the last instruction is a call (typically to do a throw which
423 // is coming at the end after block reordering) the return address
424 // must still point into the code area in order to avoid assertion
425 // failures when searching for the corresponding bci => add a nop
426 // (was bug 5/14/1999 - gri)
427 __ nop();
428
429 // generate code for exception handler
430 address handler_base = __ start_a_stub(exception_handler_size);
431 if (handler_base == NULL) {
432 // not enough space left for the handler
433 bailout("exception handler overflow");
434 return -1;
435 }
436
437 int offset = code_offset();
438
439 // the exception oop and pc are in rax, and rdx
440 // no other registers need to be preserved, so invalidate them
441 __ invalidate_registers(false, true, true, false, true, true);
442
443 // check that there is really an exception
444 __ verify_not_null_oop(rax);
445
446 // search an exception handler (rax: exception oop, rdx: throwing pc)
447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
448
449 __ stop("should not reach here");
450
451 assert(code_offset() - offset <= exception_handler_size, "overflow");
452 __ end_a_stub();
453
454 return offset;
455 }
456
457
458 // Emit the code to remove the frame from the stack in the exception
459 // unwind path.
460 int LIR_Assembler::emit_unwind_handler() {
461 #ifndef PRODUCT
462 if (CommentedAssembly) {
463 _masm->block_comment("Unwind handler");
464 }
465 #endif
466
467 int offset = code_offset();
468
469 // Fetch the exception from TLS and clear out exception related thread state
470 __ get_thread(rsi);
471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
474
475 __ bind(_unwind_handler_entry);
476 __ verify_not_null_oop(rax);
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rsi, rax); // Preserve the exception
479 }
480
481 // Preform needed unlocking
482 MonitorExitStub* stub = NULL;
483 if (method()->is_synchronized()) {
484 monitor_address(0, FrameMap::rax_opr);
485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
486 __ unlock_object(rdi, rbx, rax, *stub->entry());
487 __ bind(*stub->continuation());
488 }
489
490 if (compilation()->env()->dtrace_method_probes()) {
491 __ movoop(Address(rsp, 0), method()->constant_encoding());
492 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
493 }
494
495 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
496 __ mov(rax, rsi); // Restore the exception
497 }
498
499 // remove the activation and dispatch to the unwind handler
500 __ remove_frame(initial_frame_size_in_bytes());
501 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
502
503 // Emit the slow path assembly
504 if (stub != NULL) {
505 stub->emit_code(this);
506 }
507
508 return offset;
509 }
510
511
512 int LIR_Assembler::emit_deopt_handler() {
513 // if the last instruction is a call (typically to do a throw which
514 // is coming at the end after block reordering) the return address
515 // must still point into the code area in order to avoid assertion
516 // failures when searching for the corresponding bci => add a nop
517 // (was bug 5/14/1999 - gri)
518 __ nop();
519
520 // generate code for exception handler
521 address handler_base = __ start_a_stub(deopt_handler_size);
522 if (handler_base == NULL) {
523 // not enough space left for the handler
524 bailout("deopt handler overflow");
525 return -1;
526 }
527
528 int offset = code_offset();
529 InternalAddress here(__ pc());
530
531 __ pushptr(here.addr());
532 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
533
534 assert(code_offset() - offset <= deopt_handler_size, "overflow");
535 __ end_a_stub();
536
537 return offset;
538 }
539
540
541 // This is the fast version of java.lang.String.compare; it has not
542 // OSR-entry and therefore, we generate a slow version for OSR's
543 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
544 __ movptr (rbx, rcx); // receiver is in rcx
545 __ movptr (rax, arg1->as_register());
546
547 // Get addresses of first characters from both Strings
548 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
549 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
550 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
551
552
553 // rbx, may be NULL
554 add_debug_info_for_null_check_here(info);
555 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
556 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
557 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
558
559 // compute minimum length (in rax) and difference of lengths (on top of stack)
560 if (VM_Version::supports_cmov()) {
561 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
562 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
563 __ mov (rcx, rbx);
564 __ subptr (rbx, rax); // subtract lengths
565 __ push (rbx); // result
566 __ cmov (Assembler::lessEqual, rax, rcx);
567 } else {
568 Label L;
569 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
570 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
571 __ mov (rax, rbx);
572 __ subptr (rbx, rcx);
573 __ push (rbx);
574 __ jcc (Assembler::lessEqual, L);
575 __ mov (rax, rcx);
576 __ bind (L);
577 }
578 // is minimum length 0?
579 Label noLoop, haveResult;
580 __ testptr (rax, rax);
581 __ jcc (Assembler::zero, noLoop);
582
583 // compare first characters
584 __ load_unsigned_short(rcx, Address(rdi, 0));
585 __ load_unsigned_short(rbx, Address(rsi, 0));
586 __ subl(rcx, rbx);
587 __ jcc(Assembler::notZero, haveResult);
588 // starting loop
589 __ decrement(rax); // we already tested index: skip one
590 __ jcc(Assembler::zero, noLoop);
591
592 // set rsi.edi to the end of the arrays (arrays have same length)
593 // negate the index
594
595 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
596 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
597 __ negptr(rax);
598
599 // compare the strings in a loop
600
601 Label loop;
602 __ align(wordSize);
603 __ bind(loop);
604 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
605 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
606 __ subl(rcx, rbx);
607 __ jcc(Assembler::notZero, haveResult);
608 __ increment(rax);
609 __ jcc(Assembler::notZero, loop);
610
611 // strings are equal up to min length
612
613 __ bind(noLoop);
614 __ pop(rax);
615 return_op(LIR_OprFact::illegalOpr);
616
617 __ bind(haveResult);
618 // leave instruction is going to discard the TOS value
619 __ mov (rax, rcx); // result of call is in rax,
620 }
621
622
623 void LIR_Assembler::return_op(LIR_Opr result) {
624 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
625 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
626 assert(result->fpu() == 0, "result must already be on TOS");
627 }
628
629 // Pop the stack before the safepoint code
630 __ remove_frame(initial_frame_size_in_bytes());
631
632 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
633
634 // Note: we do not need to round double result; float result has the right precision
635 // the poll sets the condition code, but no data registers
636 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
637 relocInfo::poll_return_type);
638
639 // NOTE: the requires that the polling page be reachable else the reloc
640 // goes to the movq that loads the address and not the faulting instruction
641 // which breaks the signal handler code
642
643 __ test32(rax, polling_page);
644
645 __ ret(0);
646 }
647
648
649 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
650 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
651 relocInfo::poll_type);
652
653 if (info != NULL) {
654 add_debug_info_for_branch(info);
655 } else {
656 ShouldNotReachHere();
657 }
658
659 int offset = __ offset();
660
661 // NOTE: the requires that the polling page be reachable else the reloc
662 // goes to the movq that loads the address and not the faulting instruction
663 // which breaks the signal handler code
664
665 __ test32(rax, polling_page);
666 return offset;
667 }
668
669
670 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
671 if (from_reg != to_reg) __ mov(to_reg, from_reg);
672 }
673
674 void LIR_Assembler::swap_reg(Register a, Register b) {
675 __ xchgptr(a, b);
676 }
677
678
679 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
680 assert(src->is_constant(), "should not call otherwise");
681 assert(dest->is_register(), "should not call otherwise");
682 LIR_Const* c = src->as_constant_ptr();
683
684 switch (c->type()) {
685 case T_INT:
686 case T_ADDRESS: {
687 assert(patch_code == lir_patch_none, "no patching handled here");
688 __ movl(dest->as_register(), c->as_jint());
689 break;
690 }
691
692 case T_LONG: {
693 assert(patch_code == lir_patch_none, "no patching handled here");
694 #ifdef _LP64
695 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
696 #else
697 __ movptr(dest->as_register_lo(), c->as_jint_lo());
698 __ movptr(dest->as_register_hi(), c->as_jint_hi());
699 #endif // _LP64
700 break;
701 }
702
703 case T_OBJECT: {
704 if (patch_code != lir_patch_none) {
705 jobject2reg_with_patching(dest->as_register(), info);
706 } else {
707 __ movoop(dest->as_register(), c->as_jobject());
708 }
709 break;
710 }
711
712 case T_FLOAT: {
713 if (dest->is_single_xmm()) {
714 if (c->is_zero_float()) {
715 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
716 } else {
717 __ movflt(dest->as_xmm_float_reg(),
718 InternalAddress(float_constant(c->as_jfloat())));
719 }
720 } else {
721 assert(dest->is_single_fpu(), "must be");
722 assert(dest->fpu_regnr() == 0, "dest must be TOS");
723 if (c->is_zero_float()) {
724 __ fldz();
725 } else if (c->is_one_float()) {
726 __ fld1();
727 } else {
728 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
729 }
730 }
731 break;
732 }
733
734 case T_DOUBLE: {
735 if (dest->is_double_xmm()) {
736 if (c->is_zero_double()) {
737 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
738 } else {
739 __ movdbl(dest->as_xmm_double_reg(),
740 InternalAddress(double_constant(c->as_jdouble())));
741 }
742 } else {
743 assert(dest->is_double_fpu(), "must be");
744 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
745 if (c->is_zero_double()) {
746 __ fldz();
747 } else if (c->is_one_double()) {
748 __ fld1();
749 } else {
750 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
751 }
752 }
753 break;
754 }
755
756 default:
757 ShouldNotReachHere();
758 }
759 }
760
761 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
762 assert(src->is_constant(), "should not call otherwise");
763 assert(dest->is_stack(), "should not call otherwise");
764 LIR_Const* c = src->as_constant_ptr();
765
766 switch (c->type()) {
767 case T_INT: // fall through
768 case T_FLOAT:
769 case T_ADDRESS:
770 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
771 break;
772
773 case T_OBJECT:
774 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
775 break;
776
777 case T_LONG: // fall through
778 case T_DOUBLE:
779 #ifdef _LP64
780 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
781 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
782 #else
783 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
784 lo_word_offset_in_bytes), c->as_jint_lo_bits());
785 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
786 hi_word_offset_in_bytes), c->as_jint_hi_bits());
787 #endif // _LP64
788 break;
789
790 default:
791 ShouldNotReachHere();
792 }
793 }
794
795 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
796 assert(src->is_constant(), "should not call otherwise");
797 assert(dest->is_address(), "should not call otherwise");
798 LIR_Const* c = src->as_constant_ptr();
799 LIR_Address* addr = dest->as_address_ptr();
800
801 int null_check_here = code_offset();
802 switch (type) {
803 case T_INT: // fall through
804 case T_FLOAT:
805 case T_ADDRESS:
806 __ movl(as_Address(addr), c->as_jint_bits());
807 break;
808
809 case T_OBJECT: // fall through
810 case T_ARRAY:
811 if (c->as_jobject() == NULL) {
812 __ movptr(as_Address(addr), NULL_WORD);
813 } else {
814 if (is_literal_address(addr)) {
815 ShouldNotReachHere();
816 __ movoop(as_Address(addr, noreg), c->as_jobject());
817 } else {
818 #ifdef _LP64
819 __ movoop(rscratch1, c->as_jobject());
820 null_check_here = code_offset();
821 __ movptr(as_Address_lo(addr), rscratch1);
822 #else
823 __ movoop(as_Address(addr), c->as_jobject());
824 #endif
825 }
826 }
827 break;
828
829 case T_LONG: // fall through
830 case T_DOUBLE:
831 #ifdef _LP64
832 if (is_literal_address(addr)) {
833 ShouldNotReachHere();
834 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
835 } else {
836 __ movptr(r10, (intptr_t)c->as_jlong_bits());
837 null_check_here = code_offset();
838 __ movptr(as_Address_lo(addr), r10);
839 }
840 #else
841 // Always reachable in 32bit so this doesn't produce useless move literal
842 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
843 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
844 #endif // _LP64
845 break;
846
847 case T_BOOLEAN: // fall through
848 case T_BYTE:
849 __ movb(as_Address(addr), c->as_jint() & 0xFF);
850 break;
851
852 case T_CHAR: // fall through
853 case T_SHORT:
854 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
855 break;
856
857 default:
858 ShouldNotReachHere();
859 };
860
861 if (info != NULL) {
862 add_debug_info_for_null_check(null_check_here, info);
863 }
864 }
865
866
867 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
868 assert(src->is_register(), "should not call otherwise");
869 assert(dest->is_register(), "should not call otherwise");
870
871 // move between cpu-registers
872 if (dest->is_single_cpu()) {
873 #ifdef _LP64
874 if (src->type() == T_LONG) {
875 // Can do LONG -> OBJECT
876 move_regs(src->as_register_lo(), dest->as_register());
877 return;
878 }
879 #endif
880 assert(src->is_single_cpu(), "must match");
881 if (src->type() == T_OBJECT) {
882 __ verify_oop(src->as_register());
883 }
884 move_regs(src->as_register(), dest->as_register());
885
886 } else if (dest->is_double_cpu()) {
887 #ifdef _LP64
888 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
889 // Surprising to me but we can see move of a long to t_object
890 __ verify_oop(src->as_register());
891 move_regs(src->as_register(), dest->as_register_lo());
892 return;
893 }
894 #endif
895 assert(src->is_double_cpu(), "must match");
896 Register f_lo = src->as_register_lo();
897 Register f_hi = src->as_register_hi();
898 Register t_lo = dest->as_register_lo();
899 Register t_hi = dest->as_register_hi();
900 #ifdef _LP64
901 assert(f_hi == f_lo, "must be same");
902 assert(t_hi == t_lo, "must be same");
903 move_regs(f_lo, t_lo);
904 #else
905 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
906
907
908 if (f_lo == t_hi && f_hi == t_lo) {
909 swap_reg(f_lo, f_hi);
910 } else if (f_hi == t_lo) {
911 assert(f_lo != t_hi, "overwriting register");
912 move_regs(f_hi, t_hi);
913 move_regs(f_lo, t_lo);
914 } else {
915 assert(f_hi != t_lo, "overwriting register");
916 move_regs(f_lo, t_lo);
917 move_regs(f_hi, t_hi);
918 }
919 #endif // LP64
920
921 // special moves from fpu-register to xmm-register
922 // necessary for method results
923 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
924 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
925 __ fld_s(Address(rsp, 0));
926 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
927 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
928 __ fld_d(Address(rsp, 0));
929 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
930 __ fstp_s(Address(rsp, 0));
931 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
932 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
933 __ fstp_d(Address(rsp, 0));
934 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
935
936 // move between xmm-registers
937 } else if (dest->is_single_xmm()) {
938 assert(src->is_single_xmm(), "must match");
939 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
940 } else if (dest->is_double_xmm()) {
941 assert(src->is_double_xmm(), "must match");
942 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
943
944 // move between fpu-registers (no instruction necessary because of fpu-stack)
945 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
946 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
947 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
948 } else {
949 ShouldNotReachHere();
950 }
951 }
952
953 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
954 assert(src->is_register(), "should not call otherwise");
955 assert(dest->is_stack(), "should not call otherwise");
956
957 if (src->is_single_cpu()) {
958 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
959 if (type == T_OBJECT || type == T_ARRAY) {
960 __ verify_oop(src->as_register());
961 __ movptr (dst, src->as_register());
962 } else {
963 __ movl (dst, src->as_register());
964 }
965
966 } else if (src->is_double_cpu()) {
967 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
968 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
969 __ movptr (dstLO, src->as_register_lo());
970 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
971
972 } else if (src->is_single_xmm()) {
973 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
974 __ movflt(dst_addr, src->as_xmm_float_reg());
975
976 } else if (src->is_double_xmm()) {
977 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
978 __ movdbl(dst_addr, src->as_xmm_double_reg());
979
980 } else if (src->is_single_fpu()) {
981 assert(src->fpu_regnr() == 0, "argument must be on TOS");
982 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
983 if (pop_fpu_stack) __ fstp_s (dst_addr);
984 else __ fst_s (dst_addr);
985
986 } else if (src->is_double_fpu()) {
987 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
988 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
989 if (pop_fpu_stack) __ fstp_d (dst_addr);
990 else __ fst_d (dst_addr);
991
992 } else {
993 ShouldNotReachHere();
994 }
995 }
996
997
998 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
999 LIR_Address* to_addr = dest->as_address_ptr();
1000 PatchingStub* patch = NULL;
1001
1002 if (type == T_ARRAY || type == T_OBJECT) {
1003 __ verify_oop(src->as_register());
1004 }
1005 if (patch_code != lir_patch_none) {
1006 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1007 Address toa = as_Address(to_addr);
1008 assert(toa.disp() != 0, "must have");
1009 }
1010 if (info != NULL) {
1011 add_debug_info_for_null_check_here(info);
1012 }
1013
1014 switch (type) {
1015 case T_FLOAT: {
1016 if (src->is_single_xmm()) {
1017 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1018 } else {
1019 assert(src->is_single_fpu(), "must be");
1020 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1021 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1022 else __ fst_s (as_Address(to_addr));
1023 }
1024 break;
1025 }
1026
1027 case T_DOUBLE: {
1028 if (src->is_double_xmm()) {
1029 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1030 } else {
1031 assert(src->is_double_fpu(), "must be");
1032 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1033 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1034 else __ fst_d (as_Address(to_addr));
1035 }
1036 break;
1037 }
1038
1039 case T_ADDRESS: // fall through
1040 case T_ARRAY: // fall through
1041 case T_OBJECT: // fall through
1042 #ifdef _LP64
1043 __ movptr(as_Address(to_addr), src->as_register());
1044 break;
1045 #endif // _LP64
1046 case T_INT:
1047 __ movl(as_Address(to_addr), src->as_register());
1048 break;
1049
1050 case T_LONG: {
1051 Register from_lo = src->as_register_lo();
1052 Register from_hi = src->as_register_hi();
1053 #ifdef _LP64
1054 __ movptr(as_Address_lo(to_addr), from_lo);
1055 #else
1056 Register base = to_addr->base()->as_register();
1057 Register index = noreg;
1058 if (to_addr->index()->is_register()) {
1059 index = to_addr->index()->as_register();
1060 }
1061 if (base == from_lo || index == from_lo) {
1062 assert(base != from_hi, "can't be");
1063 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1064 __ movl(as_Address_hi(to_addr), from_hi);
1065 if (patch != NULL) {
1066 patching_epilog(patch, lir_patch_high, base, info);
1067 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1068 patch_code = lir_patch_low;
1069 }
1070 __ movl(as_Address_lo(to_addr), from_lo);
1071 } else {
1072 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1073 __ movl(as_Address_lo(to_addr), from_lo);
1074 if (patch != NULL) {
1075 patching_epilog(patch, lir_patch_low, base, info);
1076 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1077 patch_code = lir_patch_high;
1078 }
1079 __ movl(as_Address_hi(to_addr), from_hi);
1080 }
1081 #endif // _LP64
1082 break;
1083 }
1084
1085 case T_BYTE: // fall through
1086 case T_BOOLEAN: {
1087 Register src_reg = src->as_register();
1088 Address dst_addr = as_Address(to_addr);
1089 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1090 __ movb(dst_addr, src_reg);
1091 break;
1092 }
1093
1094 case T_CHAR: // fall through
1095 case T_SHORT:
1096 __ movw(as_Address(to_addr), src->as_register());
1097 break;
1098
1099 default:
1100 ShouldNotReachHere();
1101 }
1102
1103 if (patch_code != lir_patch_none) {
1104 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1105 }
1106 }
1107
1108
1109 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1110 assert(src->is_stack(), "should not call otherwise");
1111 assert(dest->is_register(), "should not call otherwise");
1112
1113 if (dest->is_single_cpu()) {
1114 if (type == T_ARRAY || type == T_OBJECT) {
1115 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1116 __ verify_oop(dest->as_register());
1117 } else {
1118 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1119 }
1120
1121 } else if (dest->is_double_cpu()) {
1122 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1123 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1124 __ movptr(dest->as_register_lo(), src_addr_LO);
1125 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1126
1127 } else if (dest->is_single_xmm()) {
1128 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1129 __ movflt(dest->as_xmm_float_reg(), src_addr);
1130
1131 } else if (dest->is_double_xmm()) {
1132 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1133 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1134
1135 } else if (dest->is_single_fpu()) {
1136 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1137 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1138 __ fld_s(src_addr);
1139
1140 } else if (dest->is_double_fpu()) {
1141 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1142 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1143 __ fld_d(src_addr);
1144
1145 } else {
1146 ShouldNotReachHere();
1147 }
1148 }
1149
1150
1151 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1152 if (src->is_single_stack()) {
1153 if (type == T_OBJECT || type == T_ARRAY) {
1154 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1155 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1156 } else {
1157 #ifndef _LP64
1158 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1159 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1160 #else
1161 //no pushl on 64bits
1162 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1163 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1164 #endif
1165 }
1166
1167 } else if (src->is_double_stack()) {
1168 #ifdef _LP64
1169 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1170 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1171 #else
1172 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1173 // push and pop the part at src + wordSize, adding wordSize for the previous push
1174 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1175 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1176 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1177 #endif // _LP64
1178
1179 } else {
1180 ShouldNotReachHere();
1181 }
1182 }
1183
1184
1185 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1186 assert(src->is_address(), "should not call otherwise");
1187 assert(dest->is_register(), "should not call otherwise");
1188
1189 LIR_Address* addr = src->as_address_ptr();
1190 Address from_addr = as_Address(addr);
1191
1192 switch (type) {
1193 case T_BOOLEAN: // fall through
1194 case T_BYTE: // fall through
1195 case T_CHAR: // fall through
1196 case T_SHORT:
1197 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1198 // on pre P6 processors we may get partial register stalls
1199 // so blow away the value of to_rinfo before loading a
1200 // partial word into it. Do it here so that it precedes
1201 // the potential patch point below.
1202 __ xorptr(dest->as_register(), dest->as_register());
1203 }
1204 break;
1205 }
1206
1207 PatchingStub* patch = NULL;
1208 if (patch_code != lir_patch_none) {
1209 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1210 assert(from_addr.disp() != 0, "must have");
1211 }
1212 if (info != NULL) {
1213 add_debug_info_for_null_check_here(info);
1214 }
1215
1216 switch (type) {
1217 case T_FLOAT: {
1218 if (dest->is_single_xmm()) {
1219 __ movflt(dest->as_xmm_float_reg(), from_addr);
1220 } else {
1221 assert(dest->is_single_fpu(), "must be");
1222 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1223 __ fld_s(from_addr);
1224 }
1225 break;
1226 }
1227
1228 case T_DOUBLE: {
1229 if (dest->is_double_xmm()) {
1230 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1231 } else {
1232 assert(dest->is_double_fpu(), "must be");
1233 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1234 __ fld_d(from_addr);
1235 }
1236 break;
1237 }
1238
1239 case T_ADDRESS: // fall through
1240 case T_OBJECT: // fall through
1241 case T_ARRAY: // fall through
1242 #ifdef _LP64
1243 __ movptr(dest->as_register(), from_addr);
1244 break;
1245 #endif // _L64
1246 case T_INT:
1247 __ movl(dest->as_register(), from_addr);
1248 break;
1249
1250 case T_LONG: {
1251 Register to_lo = dest->as_register_lo();
1252 Register to_hi = dest->as_register_hi();
1253 #ifdef _LP64
1254 __ movptr(to_lo, as_Address_lo(addr));
1255 #else
1256 Register base = addr->base()->as_register();
1257 Register index = noreg;
1258 if (addr->index()->is_register()) {
1259 index = addr->index()->as_register();
1260 }
1261 if ((base == to_lo && index == to_hi) ||
1262 (base == to_hi && index == to_lo)) {
1263 // addresses with 2 registers are only formed as a result of
1264 // array access so this code will never have to deal with
1265 // patches or null checks.
1266 assert(info == NULL && patch == NULL, "must be");
1267 __ lea(to_hi, as_Address(addr));
1268 __ movl(to_lo, Address(to_hi, 0));
1269 __ movl(to_hi, Address(to_hi, BytesPerWord));
1270 } else if (base == to_lo || index == to_lo) {
1271 assert(base != to_hi, "can't be");
1272 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1273 __ movl(to_hi, as_Address_hi(addr));
1274 if (patch != NULL) {
1275 patching_epilog(patch, lir_patch_high, base, info);
1276 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1277 patch_code = lir_patch_low;
1278 }
1279 __ movl(to_lo, as_Address_lo(addr));
1280 } else {
1281 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1282 __ movl(to_lo, as_Address_lo(addr));
1283 if (patch != NULL) {
1284 patching_epilog(patch, lir_patch_low, base, info);
1285 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1286 patch_code = lir_patch_high;
1287 }
1288 __ movl(to_hi, as_Address_hi(addr));
1289 }
1290 #endif // _LP64
1291 break;
1292 }
1293
1294 case T_BOOLEAN: // fall through
1295 case T_BYTE: {
1296 Register dest_reg = dest->as_register();
1297 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1298 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1299 __ movsbl(dest_reg, from_addr);
1300 } else {
1301 __ movb(dest_reg, from_addr);
1302 __ shll(dest_reg, 24);
1303 __ sarl(dest_reg, 24);
1304 }
1305 break;
1306 }
1307
1308 case T_CHAR: {
1309 Register dest_reg = dest->as_register();
1310 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1311 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1312 __ movzwl(dest_reg, from_addr);
1313 } else {
1314 __ movw(dest_reg, from_addr);
1315 }
1316 break;
1317 }
1318
1319 case T_SHORT: {
1320 Register dest_reg = dest->as_register();
1321 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1322 __ movswl(dest_reg, from_addr);
1323 } else {
1324 __ movw(dest_reg, from_addr);
1325 __ shll(dest_reg, 16);
1326 __ sarl(dest_reg, 16);
1327 }
1328 break;
1329 }
1330
1331 default:
1332 ShouldNotReachHere();
1333 }
1334
1335 if (patch != NULL) {
1336 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1337 }
1338
1339 if (type == T_ARRAY || type == T_OBJECT) {
1340 __ verify_oop(dest->as_register());
1341 }
1342 }
1343
1344
1345 void LIR_Assembler::prefetchr(LIR_Opr src) {
1346 LIR_Address* addr = src->as_address_ptr();
1347 Address from_addr = as_Address(addr);
1348
1349 if (VM_Version::supports_sse()) {
1350 switch (ReadPrefetchInstr) {
1351 case 0:
1352 __ prefetchnta(from_addr); break;
1353 case 1:
1354 __ prefetcht0(from_addr); break;
1355 case 2:
1356 __ prefetcht2(from_addr); break;
1357 default:
1358 ShouldNotReachHere(); break;
1359 }
1360 } else if (VM_Version::supports_3dnow()) {
1361 __ prefetchr(from_addr);
1362 }
1363 }
1364
1365
1366 void LIR_Assembler::prefetchw(LIR_Opr src) {
1367 LIR_Address* addr = src->as_address_ptr();
1368 Address from_addr = as_Address(addr);
1369
1370 if (VM_Version::supports_sse()) {
1371 switch (AllocatePrefetchInstr) {
1372 case 0:
1373 __ prefetchnta(from_addr); break;
1374 case 1:
1375 __ prefetcht0(from_addr); break;
1376 case 2:
1377 __ prefetcht2(from_addr); break;
1378 case 3:
1379 __ prefetchw(from_addr); break;
1380 default:
1381 ShouldNotReachHere(); break;
1382 }
1383 } else if (VM_Version::supports_3dnow()) {
1384 __ prefetchw(from_addr);
1385 }
1386 }
1387
1388
1389 NEEDS_CLEANUP; // This could be static?
1390 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1391 int elem_size = type2aelembytes(type);
1392 switch (elem_size) {
1393 case 1: return Address::times_1;
1394 case 2: return Address::times_2;
1395 case 4: return Address::times_4;
1396 case 8: return Address::times_8;
1397 }
1398 ShouldNotReachHere();
1399 return Address::no_scale;
1400 }
1401
1402
1403 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1404 switch (op->code()) {
1405 case lir_idiv:
1406 case lir_irem:
1407 arithmetic_idiv(op->code(),
1408 op->in_opr1(),
1409 op->in_opr2(),
1410 op->in_opr3(),
1411 op->result_opr(),
1412 op->info());
1413 break;
1414 default: ShouldNotReachHere(); break;
1415 }
1416 }
1417
1418 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1419 #ifdef ASSERT
1420 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1421 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1422 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1423 #endif
1424
1425 if (op->cond() == lir_cond_always) {
1426 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1427 __ jmp (*(op->label()));
1428 } else {
1429 Assembler::Condition acond = Assembler::zero;
1430 if (op->code() == lir_cond_float_branch) {
1431 assert(op->ublock() != NULL, "must have unordered successor");
1432 __ jcc(Assembler::parity, *(op->ublock()->label()));
1433 switch(op->cond()) {
1434 case lir_cond_equal: acond = Assembler::equal; break;
1435 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1436 case lir_cond_less: acond = Assembler::below; break;
1437 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1438 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1439 case lir_cond_greater: acond = Assembler::above; break;
1440 default: ShouldNotReachHere();
1441 }
1442 } else {
1443 switch (op->cond()) {
1444 case lir_cond_equal: acond = Assembler::equal; break;
1445 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1446 case lir_cond_less: acond = Assembler::less; break;
1447 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1448 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1449 case lir_cond_greater: acond = Assembler::greater; break;
1450 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1451 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1452 default: ShouldNotReachHere();
1453 }
1454 }
1455 __ jcc(acond,*(op->label()));
1456 }
1457 }
1458
1459 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1460 LIR_Opr src = op->in_opr();
1461 LIR_Opr dest = op->result_opr();
1462
1463 switch (op->bytecode()) {
1464 case Bytecodes::_i2l:
1465 #ifdef _LP64
1466 __ movl2ptr(dest->as_register_lo(), src->as_register());
1467 #else
1468 move_regs(src->as_register(), dest->as_register_lo());
1469 move_regs(src->as_register(), dest->as_register_hi());
1470 __ sarl(dest->as_register_hi(), 31);
1471 #endif // LP64
1472 break;
1473
1474 case Bytecodes::_l2i:
1475 move_regs(src->as_register_lo(), dest->as_register());
1476 break;
1477
1478 case Bytecodes::_i2b:
1479 move_regs(src->as_register(), dest->as_register());
1480 __ sign_extend_byte(dest->as_register());
1481 break;
1482
1483 case Bytecodes::_i2c:
1484 move_regs(src->as_register(), dest->as_register());
1485 __ andl(dest->as_register(), 0xFFFF);
1486 break;
1487
1488 case Bytecodes::_i2s:
1489 move_regs(src->as_register(), dest->as_register());
1490 __ sign_extend_short(dest->as_register());
1491 break;
1492
1493
1494 case Bytecodes::_f2d:
1495 case Bytecodes::_d2f:
1496 if (dest->is_single_xmm()) {
1497 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1498 } else if (dest->is_double_xmm()) {
1499 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1500 } else {
1501 assert(src->fpu() == dest->fpu(), "register must be equal");
1502 // do nothing (float result is rounded later through spilling)
1503 }
1504 break;
1505
1506 case Bytecodes::_i2f:
1507 case Bytecodes::_i2d:
1508 if (dest->is_single_xmm()) {
1509 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1510 } else if (dest->is_double_xmm()) {
1511 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1512 } else {
1513 assert(dest->fpu() == 0, "result must be on TOS");
1514 __ movl(Address(rsp, 0), src->as_register());
1515 __ fild_s(Address(rsp, 0));
1516 }
1517 break;
1518
1519 case Bytecodes::_f2i:
1520 case Bytecodes::_d2i:
1521 if (src->is_single_xmm()) {
1522 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1523 } else if (src->is_double_xmm()) {
1524 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1525 } else {
1526 assert(src->fpu() == 0, "input must be on TOS");
1527 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1528 __ fist_s(Address(rsp, 0));
1529 __ movl(dest->as_register(), Address(rsp, 0));
1530 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1531 }
1532
1533 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1534 assert(op->stub() != NULL, "stub required");
1535 __ cmpl(dest->as_register(), 0x80000000);
1536 __ jcc(Assembler::equal, *op->stub()->entry());
1537 __ bind(*op->stub()->continuation());
1538 break;
1539
1540 case Bytecodes::_l2f:
1541 case Bytecodes::_l2d:
1542 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1543 assert(dest->fpu() == 0, "result must be on TOS");
1544
1545 __ movptr(Address(rsp, 0), src->as_register_lo());
1546 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1547 __ fild_d(Address(rsp, 0));
1548 // float result is rounded later through spilling
1549 break;
1550
1551 case Bytecodes::_f2l:
1552 case Bytecodes::_d2l:
1553 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1554 assert(src->fpu() == 0, "input must be on TOS");
1555 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1556
1557 // instruction sequence too long to inline it here
1558 {
1559 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1560 }
1561 break;
1562
1563 default: ShouldNotReachHere();
1564 }
1565 }
1566
1567 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1568 if (op->init_check()) {
1569 __ cmpl(Address(op->klass()->as_register(),
1570 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1571 instanceKlass::fully_initialized);
1572 add_debug_info_for_null_check_here(op->stub()->info());
1573 __ jcc(Assembler::notEqual, *op->stub()->entry());
1574 }
1575 __ allocate_object(op->obj()->as_register(),
1576 op->tmp1()->as_register(),
1577 op->tmp2()->as_register(),
1578 op->header_size(),
1579 op->object_size(),
1580 op->klass()->as_register(),
1581 *op->stub()->entry());
1582 __ bind(*op->stub()->continuation());
1583 }
1584
1585 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1586 if (UseSlowPath ||
1587 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1588 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1589 __ jmp(*op->stub()->entry());
1590 } else {
1591 Register len = op->len()->as_register();
1592 Register tmp1 = op->tmp1()->as_register();
1593 Register tmp2 = op->tmp2()->as_register();
1594 Register tmp3 = op->tmp3()->as_register();
1595 if (len == tmp1) {
1596 tmp1 = tmp3;
1597 } else if (len == tmp2) {
1598 tmp2 = tmp3;
1599 } else if (len == tmp3) {
1600 // everything is ok
1601 } else {
1602 __ mov(tmp3, len);
1603 }
1604 __ allocate_array(op->obj()->as_register(),
1605 len,
1606 tmp1,
1607 tmp2,
1608 arrayOopDesc::header_size(op->type()),
1609 array_element_size(op->type()),
1610 op->klass()->as_register(),
1611 *op->stub()->entry());
1612 }
1613 __ bind(*op->stub()->continuation());
1614 }
1615
1616
1617
1618 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1619 LIR_Code code = op->code();
1620 if (code == lir_store_check) {
1621 Register value = op->object()->as_register();
1622 Register array = op->array()->as_register();
1623 Register k_RInfo = op->tmp1()->as_register();
1624 Register klass_RInfo = op->tmp2()->as_register();
1625 Register Rtmp1 = op->tmp3()->as_register();
1626
1627 CodeStub* stub = op->stub();
1628 Label done;
1629 __ cmpptr(value, (int32_t)NULL_WORD);
1630 __ jcc(Assembler::equal, done);
1631 add_debug_info_for_null_check_here(op->info_for_exception());
1632 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1633 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1634
1635 // get instance klass
1636 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1637 // perform the fast part of the checking logic
1638 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL);
1639 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1640 __ push(klass_RInfo);
1641 __ push(k_RInfo);
1642 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1643 __ pop(klass_RInfo);
1644 __ pop(k_RInfo);
1645 // result is a boolean
1646 __ cmpl(k_RInfo, 0);
1647 __ jcc(Assembler::equal, *stub->entry());
1648 __ bind(done);
1649 } else if (op->code() == lir_checkcast) {
1650 // we always need a stub for the failure case.
1651 CodeStub* stub = op->stub();
1652 Register obj = op->object()->as_register();
1653 Register k_RInfo = op->tmp1()->as_register();
1654 Register klass_RInfo = op->tmp2()->as_register();
1655 Register dst = op->result_opr()->as_register();
1656 ciKlass* k = op->klass();
1657 Register Rtmp1 = noreg;
1658
1659 Label done;
1660 if (obj == k_RInfo) {
1661 k_RInfo = dst;
1662 } else if (obj == klass_RInfo) {
1663 klass_RInfo = dst;
1664 }
1665 if (k->is_loaded()) {
1666 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1667 } else {
1668 Rtmp1 = op->tmp3()->as_register();
1669 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1670 }
1671
1672 assert_different_registers(obj, k_RInfo, klass_RInfo);
1673 if (!k->is_loaded()) {
1674 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1675 } else {
1676 #ifdef _LP64
1677 __ movoop(k_RInfo, k->constant_encoding());
1678 #else
1679 k_RInfo = noreg;
1680 #endif // _LP64
1681 }
1682 assert(obj != k_RInfo, "must be different");
1683 __ cmpptr(obj, (int32_t)NULL_WORD);
1684 if (op->profiled_method() != NULL) {
1685 ciMethod* method = op->profiled_method();
1686 int bci = op->profiled_bci();
1687
1688 Label profile_done;
1689 __ jcc(Assembler::notEqual, profile_done);
1690 // Object is null; update methodDataOop
1691 ciMethodData* md = method->method_data();
1692 if (md == NULL) {
1693 bailout("out of memory building methodDataOop");
1694 return;
1695 }
1696 ciProfileData* data = md->bci_to_data(bci);
1697 assert(data != NULL, "need data for checkcast");
1698 assert(data->is_BitData(), "need BitData for checkcast");
1699 Register mdo = klass_RInfo;
1700 __ movoop(mdo, md->constant_encoding());
1701 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1702 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1703 __ orl(data_addr, header_bits);
1704 __ jmp(done);
1705 __ bind(profile_done);
1706 } else {
1707 __ jcc(Assembler::equal, done);
1708 }
1709 __ verify_oop(obj);
1710
1711 if (op->fast_check()) {
1712 // get object classo
1713 // not a safepoint as obj null check happens earlier
1714 if (k->is_loaded()) {
1715 #ifdef _LP64
1716 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1717 #else
1718 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1719 #endif // _LP64
1720 } else {
1721 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1722
1723 }
1724 __ jcc(Assembler::notEqual, *stub->entry());
1725 __ bind(done);
1726 } else {
1727 // get object class
1728 // not a safepoint as obj null check happens earlier
1729 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1730 if (k->is_loaded()) {
1731 // See if we get an immediate positive hit
1732 #ifdef _LP64
1733 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1734 #else
1735 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1736 #endif // _LP64
1737 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1738 __ jcc(Assembler::notEqual, *stub->entry());
1739 } else {
1740 // See if we get an immediate positive hit
1741 __ jcc(Assembler::equal, done);
1742 // check for self
1743 #ifdef _LP64
1744 __ cmpptr(klass_RInfo, k_RInfo);
1745 #else
1746 __ cmpoop(klass_RInfo, k->constant_encoding());
1747 #endif // _LP64
1748 __ jcc(Assembler::equal, done);
1749
1750 __ push(klass_RInfo);
1751 #ifdef _LP64
1752 __ push(k_RInfo);
1753 #else
1754 __ pushoop(k->constant_encoding());
1755 #endif // _LP64
1756 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1757 __ pop(klass_RInfo);
1758 __ pop(klass_RInfo);
1759 // result is a boolean
1760 __ cmpl(klass_RInfo, 0);
1761 __ jcc(Assembler::equal, *stub->entry());
1762 }
1763 __ bind(done);
1764 } else {
1765 // perform the fast part of the checking logic
1766 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL);
1767 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1768 __ push(klass_RInfo);
1769 __ push(k_RInfo);
1770 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1771 __ pop(klass_RInfo);
1772 __ pop(k_RInfo);
1773 // result is a boolean
1774 __ cmpl(k_RInfo, 0);
1775 __ jcc(Assembler::equal, *stub->entry());
1776 __ bind(done);
1777 }
1778
1779 }
1780 if (dst != obj) {
1781 __ mov(dst, obj);
1782 }
1783 } else if (code == lir_instanceof) {
1784 Register obj = op->object()->as_register();
1785 Register k_RInfo = op->tmp1()->as_register();
1786 Register klass_RInfo = op->tmp2()->as_register();
1787 Register dst = op->result_opr()->as_register();
1788 ciKlass* k = op->klass();
1789
1790 Label done;
1791 Label zero;
1792 Label one;
1793 if (obj == k_RInfo) {
1794 k_RInfo = klass_RInfo;
1795 klass_RInfo = obj;
1796 }
1797 // patching may screw with our temporaries on sparc,
1798 // so let's do it before loading the class
1799 if (!k->is_loaded()) {
1800 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1801 } else {
1802 LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding()));
1803 }
1804 assert(obj != k_RInfo, "must be different");
1805
1806 __ verify_oop(obj);
1807 if (op->fast_check()) {
1808 __ cmpptr(obj, (int32_t)NULL_WORD);
1809 __ jcc(Assembler::equal, zero);
1810 // get object class
1811 // not a safepoint as obj null check happens earlier
1812 if (LP64_ONLY(false &&) k->is_loaded()) {
1813 NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()));
1814 k_RInfo = noreg;
1815 } else {
1816 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1817
1818 }
1819 __ jcc(Assembler::equal, one);
1820 } else {
1821 // get object class
1822 // not a safepoint as obj null check happens earlier
1823 __ cmpptr(obj, (int32_t)NULL_WORD);
1824 __ jcc(Assembler::equal, zero);
1825 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1826
1827 #ifndef _LP64
1828 if (k->is_loaded()) {
1829 // See if we get an immediate positive hit
1830 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1831 __ jcc(Assembler::equal, one);
1832 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) {
1833 // check for self
1834 __ cmpoop(klass_RInfo, k->constant_encoding());
1835 __ jcc(Assembler::equal, one);
1836 __ push(klass_RInfo);
1837 __ pushoop(k->constant_encoding());
1838 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1839 __ pop(klass_RInfo);
1840 __ pop(dst);
1841 __ jmp(done);
1842 }
1843 }
1844 else // next block is unconditional if LP64:
1845 #endif // LP64
1846 {
1847 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
1848
1849 // perform the fast part of the checking logic
1850 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL);
1851 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1852 __ push(klass_RInfo);
1853 __ push(k_RInfo);
1854 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1855 __ pop(klass_RInfo);
1856 __ pop(dst);
1857 __ jmp(done);
1858 }
1859 }
1860 __ bind(zero);
1861 __ xorptr(dst, dst);
1862 __ jmp(done);
1863 __ bind(one);
1864 __ movptr(dst, 1);
1865 __ bind(done);
1866 } else {
1867 ShouldNotReachHere();
1868 }
1869
1870 }
1871
1872
1873 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1874 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1875 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1876 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1877 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1878 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1879 Register addr = op->addr()->as_register();
1880 if (os::is_MP()) {
1881 __ lock();
1882 }
1883 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1884
1885 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1886 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1887 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1888 Register newval = op->new_value()->as_register();
1889 Register cmpval = op->cmp_value()->as_register();
1890 assert(cmpval == rax, "wrong register");
1891 assert(newval != NULL, "new val must be register");
1892 assert(cmpval != newval, "cmp and new values must be in different registers");
1893 assert(cmpval != addr, "cmp and addr must be in different registers");
1894 assert(newval != addr, "new value and addr must be in different registers");
1895 if (os::is_MP()) {
1896 __ lock();
1897 }
1898 if ( op->code() == lir_cas_obj) {
1899 __ cmpxchgptr(newval, Address(addr, 0));
1900 } else if (op->code() == lir_cas_int) {
1901 __ cmpxchgl(newval, Address(addr, 0));
1902 } else {
1903 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1904 }
1905 #ifdef _LP64
1906 } else if (op->code() == lir_cas_long) {
1907 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1908 Register newval = op->new_value()->as_register_lo();
1909 Register cmpval = op->cmp_value()->as_register_lo();
1910 assert(cmpval == rax, "wrong register");
1911 assert(newval != NULL, "new val must be register");
1912 assert(cmpval != newval, "cmp and new values must be in different registers");
1913 assert(cmpval != addr, "cmp and addr must be in different registers");
1914 assert(newval != addr, "new value and addr must be in different registers");
1915 if (os::is_MP()) {
1916 __ lock();
1917 }
1918 __ cmpxchgq(newval, Address(addr, 0));
1919 #endif // _LP64
1920 } else {
1921 Unimplemented();
1922 }
1923 }
1924
1925
1926 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1927 Assembler::Condition acond, ncond;
1928 switch (condition) {
1929 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1930 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1931 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1932 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1933 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1934 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1935 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1936 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1937 default: ShouldNotReachHere();
1938 }
1939
1940 if (opr1->is_cpu_register()) {
1941 reg2reg(opr1, result);
1942 } else if (opr1->is_stack()) {
1943 stack2reg(opr1, result, result->type());
1944 } else if (opr1->is_constant()) {
1945 const2reg(opr1, result, lir_patch_none, NULL);
1946 } else {
1947 ShouldNotReachHere();
1948 }
1949
1950 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1951 // optimized version that does not require a branch
1952 if (opr2->is_single_cpu()) {
1953 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1954 __ cmov(ncond, result->as_register(), opr2->as_register());
1955 } else if (opr2->is_double_cpu()) {
1956 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1957 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1958 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1959 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
1960 } else if (opr2->is_single_stack()) {
1961 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1962 } else if (opr2->is_double_stack()) {
1963 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1964 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
1965 } else {
1966 ShouldNotReachHere();
1967 }
1968
1969 } else {
1970 Label skip;
1971 __ jcc (acond, skip);
1972 if (opr2->is_cpu_register()) {
1973 reg2reg(opr2, result);
1974 } else if (opr2->is_stack()) {
1975 stack2reg(opr2, result, result->type());
1976 } else if (opr2->is_constant()) {
1977 const2reg(opr2, result, lir_patch_none, NULL);
1978 } else {
1979 ShouldNotReachHere();
1980 }
1981 __ bind(skip);
1982 }
1983 }
1984
1985
1986 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1987 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1988
1989 if (left->is_single_cpu()) {
1990 assert(left == dest, "left and dest must be equal");
1991 Register lreg = left->as_register();
1992
1993 if (right->is_single_cpu()) {
1994 // cpu register - cpu register
1995 Register rreg = right->as_register();
1996 switch (code) {
1997 case lir_add: __ addl (lreg, rreg); break;
1998 case lir_sub: __ subl (lreg, rreg); break;
1999 case lir_mul: __ imull(lreg, rreg); break;
2000 default: ShouldNotReachHere();
2001 }
2002
2003 } else if (right->is_stack()) {
2004 // cpu register - stack
2005 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2006 switch (code) {
2007 case lir_add: __ addl(lreg, raddr); break;
2008 case lir_sub: __ subl(lreg, raddr); break;
2009 default: ShouldNotReachHere();
2010 }
2011
2012 } else if (right->is_constant()) {
2013 // cpu register - constant
2014 jint c = right->as_constant_ptr()->as_jint();
2015 switch (code) {
2016 case lir_add: {
2017 __ increment(lreg, c);
2018 break;
2019 }
2020 case lir_sub: {
2021 __ decrement(lreg, c);
2022 break;
2023 }
2024 default: ShouldNotReachHere();
2025 }
2026
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030
2031 } else if (left->is_double_cpu()) {
2032 assert(left == dest, "left and dest must be equal");
2033 Register lreg_lo = left->as_register_lo();
2034 Register lreg_hi = left->as_register_hi();
2035
2036 if (right->is_double_cpu()) {
2037 // cpu register - cpu register
2038 Register rreg_lo = right->as_register_lo();
2039 Register rreg_hi = right->as_register_hi();
2040 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2041 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2042 switch (code) {
2043 case lir_add:
2044 __ addptr(lreg_lo, rreg_lo);
2045 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2046 break;
2047 case lir_sub:
2048 __ subptr(lreg_lo, rreg_lo);
2049 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2050 break;
2051 case lir_mul:
2052 #ifdef _LP64
2053 __ imulq(lreg_lo, rreg_lo);
2054 #else
2055 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2056 __ imull(lreg_hi, rreg_lo);
2057 __ imull(rreg_hi, lreg_lo);
2058 __ addl (rreg_hi, lreg_hi);
2059 __ mull (rreg_lo);
2060 __ addl (lreg_hi, rreg_hi);
2061 #endif // _LP64
2062 break;
2063 default:
2064 ShouldNotReachHere();
2065 }
2066
2067 } else if (right->is_constant()) {
2068 // cpu register - constant
2069 #ifdef _LP64
2070 jlong c = right->as_constant_ptr()->as_jlong_bits();
2071 __ movptr(r10, (intptr_t) c);
2072 switch (code) {
2073 case lir_add:
2074 __ addptr(lreg_lo, r10);
2075 break;
2076 case lir_sub:
2077 __ subptr(lreg_lo, r10);
2078 break;
2079 default:
2080 ShouldNotReachHere();
2081 }
2082 #else
2083 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2084 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2085 switch (code) {
2086 case lir_add:
2087 __ addptr(lreg_lo, c_lo);
2088 __ adcl(lreg_hi, c_hi);
2089 break;
2090 case lir_sub:
2091 __ subptr(lreg_lo, c_lo);
2092 __ sbbl(lreg_hi, c_hi);
2093 break;
2094 default:
2095 ShouldNotReachHere();
2096 }
2097 #endif // _LP64
2098
2099 } else {
2100 ShouldNotReachHere();
2101 }
2102
2103 } else if (left->is_single_xmm()) {
2104 assert(left == dest, "left and dest must be equal");
2105 XMMRegister lreg = left->as_xmm_float_reg();
2106
2107 if (right->is_single_xmm()) {
2108 XMMRegister rreg = right->as_xmm_float_reg();
2109 switch (code) {
2110 case lir_add: __ addss(lreg, rreg); break;
2111 case lir_sub: __ subss(lreg, rreg); break;
2112 case lir_mul_strictfp: // fall through
2113 case lir_mul: __ mulss(lreg, rreg); break;
2114 case lir_div_strictfp: // fall through
2115 case lir_div: __ divss(lreg, rreg); break;
2116 default: ShouldNotReachHere();
2117 }
2118 } else {
2119 Address raddr;
2120 if (right->is_single_stack()) {
2121 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2122 } else if (right->is_constant()) {
2123 // hack for now
2124 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2125 } else {
2126 ShouldNotReachHere();
2127 }
2128 switch (code) {
2129 case lir_add: __ addss(lreg, raddr); break;
2130 case lir_sub: __ subss(lreg, raddr); break;
2131 case lir_mul_strictfp: // fall through
2132 case lir_mul: __ mulss(lreg, raddr); break;
2133 case lir_div_strictfp: // fall through
2134 case lir_div: __ divss(lreg, raddr); break;
2135 default: ShouldNotReachHere();
2136 }
2137 }
2138
2139 } else if (left->is_double_xmm()) {
2140 assert(left == dest, "left and dest must be equal");
2141
2142 XMMRegister lreg = left->as_xmm_double_reg();
2143 if (right->is_double_xmm()) {
2144 XMMRegister rreg = right->as_xmm_double_reg();
2145 switch (code) {
2146 case lir_add: __ addsd(lreg, rreg); break;
2147 case lir_sub: __ subsd(lreg, rreg); break;
2148 case lir_mul_strictfp: // fall through
2149 case lir_mul: __ mulsd(lreg, rreg); break;
2150 case lir_div_strictfp: // fall through
2151 case lir_div: __ divsd(lreg, rreg); break;
2152 default: ShouldNotReachHere();
2153 }
2154 } else {
2155 Address raddr;
2156 if (right->is_double_stack()) {
2157 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2158 } else if (right->is_constant()) {
2159 // hack for now
2160 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2161 } else {
2162 ShouldNotReachHere();
2163 }
2164 switch (code) {
2165 case lir_add: __ addsd(lreg, raddr); break;
2166 case lir_sub: __ subsd(lreg, raddr); break;
2167 case lir_mul_strictfp: // fall through
2168 case lir_mul: __ mulsd(lreg, raddr); break;
2169 case lir_div_strictfp: // fall through
2170 case lir_div: __ divsd(lreg, raddr); break;
2171 default: ShouldNotReachHere();
2172 }
2173 }
2174
2175 } else if (left->is_single_fpu()) {
2176 assert(dest->is_single_fpu(), "fpu stack allocation required");
2177
2178 if (right->is_single_fpu()) {
2179 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2180
2181 } else {
2182 assert(left->fpu_regnr() == 0, "left must be on TOS");
2183 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2184
2185 Address raddr;
2186 if (right->is_single_stack()) {
2187 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2188 } else if (right->is_constant()) {
2189 address const_addr = float_constant(right->as_jfloat());
2190 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2191 // hack for now
2192 raddr = __ as_Address(InternalAddress(const_addr));
2193 } else {
2194 ShouldNotReachHere();
2195 }
2196
2197 switch (code) {
2198 case lir_add: __ fadd_s(raddr); break;
2199 case lir_sub: __ fsub_s(raddr); break;
2200 case lir_mul_strictfp: // fall through
2201 case lir_mul: __ fmul_s(raddr); break;
2202 case lir_div_strictfp: // fall through
2203 case lir_div: __ fdiv_s(raddr); break;
2204 default: ShouldNotReachHere();
2205 }
2206 }
2207
2208 } else if (left->is_double_fpu()) {
2209 assert(dest->is_double_fpu(), "fpu stack allocation required");
2210
2211 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2212 // Double values require special handling for strictfp mul/div on x86
2213 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2214 __ fmulp(left->fpu_regnrLo() + 1);
2215 }
2216
2217 if (right->is_double_fpu()) {
2218 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2219
2220 } else {
2221 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2222 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2223
2224 Address raddr;
2225 if (right->is_double_stack()) {
2226 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2227 } else if (right->is_constant()) {
2228 // hack for now
2229 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2230 } else {
2231 ShouldNotReachHere();
2232 }
2233
2234 switch (code) {
2235 case lir_add: __ fadd_d(raddr); break;
2236 case lir_sub: __ fsub_d(raddr); break;
2237 case lir_mul_strictfp: // fall through
2238 case lir_mul: __ fmul_d(raddr); break;
2239 case lir_div_strictfp: // fall through
2240 case lir_div: __ fdiv_d(raddr); break;
2241 default: ShouldNotReachHere();
2242 }
2243 }
2244
2245 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2246 // Double values require special handling for strictfp mul/div on x86
2247 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2248 __ fmulp(dest->fpu_regnrLo() + 1);
2249 }
2250
2251 } else if (left->is_single_stack() || left->is_address()) {
2252 assert(left == dest, "left and dest must be equal");
2253
2254 Address laddr;
2255 if (left->is_single_stack()) {
2256 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2257 } else if (left->is_address()) {
2258 laddr = as_Address(left->as_address_ptr());
2259 } else {
2260 ShouldNotReachHere();
2261 }
2262
2263 if (right->is_single_cpu()) {
2264 Register rreg = right->as_register();
2265 switch (code) {
2266 case lir_add: __ addl(laddr, rreg); break;
2267 case lir_sub: __ subl(laddr, rreg); break;
2268 default: ShouldNotReachHere();
2269 }
2270 } else if (right->is_constant()) {
2271 jint c = right->as_constant_ptr()->as_jint();
2272 switch (code) {
2273 case lir_add: {
2274 __ incrementl(laddr, c);
2275 break;
2276 }
2277 case lir_sub: {
2278 __ decrementl(laddr, c);
2279 break;
2280 }
2281 default: ShouldNotReachHere();
2282 }
2283 } else {
2284 ShouldNotReachHere();
2285 }
2286
2287 } else {
2288 ShouldNotReachHere();
2289 }
2290 }
2291
2292 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2293 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2294 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2295 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2296
2297 bool left_is_tos = (left_index == 0);
2298 bool dest_is_tos = (dest_index == 0);
2299 int non_tos_index = (left_is_tos ? right_index : left_index);
2300
2301 switch (code) {
2302 case lir_add:
2303 if (pop_fpu_stack) __ faddp(non_tos_index);
2304 else if (dest_is_tos) __ fadd (non_tos_index);
2305 else __ fadda(non_tos_index);
2306 break;
2307
2308 case lir_sub:
2309 if (left_is_tos) {
2310 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2311 else if (dest_is_tos) __ fsub (non_tos_index);
2312 else __ fsubra(non_tos_index);
2313 } else {
2314 if (pop_fpu_stack) __ fsubp (non_tos_index);
2315 else if (dest_is_tos) __ fsubr (non_tos_index);
2316 else __ fsuba (non_tos_index);
2317 }
2318 break;
2319
2320 case lir_mul_strictfp: // fall through
2321 case lir_mul:
2322 if (pop_fpu_stack) __ fmulp(non_tos_index);
2323 else if (dest_is_tos) __ fmul (non_tos_index);
2324 else __ fmula(non_tos_index);
2325 break;
2326
2327 case lir_div_strictfp: // fall through
2328 case lir_div:
2329 if (left_is_tos) {
2330 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2331 else if (dest_is_tos) __ fdiv (non_tos_index);
2332 else __ fdivra(non_tos_index);
2333 } else {
2334 if (pop_fpu_stack) __ fdivp (non_tos_index);
2335 else if (dest_is_tos) __ fdivr (non_tos_index);
2336 else __ fdiva (non_tos_index);
2337 }
2338 break;
2339
2340 case lir_rem:
2341 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2342 __ fremr(noreg);
2343 break;
2344
2345 default:
2346 ShouldNotReachHere();
2347 }
2348 }
2349
2350
2351 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2352 if (value->is_double_xmm()) {
2353 switch(code) {
2354 case lir_abs :
2355 {
2356 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2357 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2358 }
2359 __ andpd(dest->as_xmm_double_reg(),
2360 ExternalAddress((address)double_signmask_pool));
2361 }
2362 break;
2363
2364 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2365 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2366 default : ShouldNotReachHere();
2367 }
2368
2369 } else if (value->is_double_fpu()) {
2370 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2371 switch(code) {
2372 case lir_log : __ flog() ; break;
2373 case lir_log10 : __ flog10() ; break;
2374 case lir_abs : __ fabs() ; break;
2375 case lir_sqrt : __ fsqrt(); break;
2376 case lir_sin :
2377 // Should consider not saving rbx, if not necessary
2378 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2379 break;
2380 case lir_cos :
2381 // Should consider not saving rbx, if not necessary
2382 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2383 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2384 break;
2385 case lir_tan :
2386 // Should consider not saving rbx, if not necessary
2387 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2388 break;
2389 default : ShouldNotReachHere();
2390 }
2391 } else {
2392 Unimplemented();
2393 }
2394 }
2395
2396 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2397 // assert(left->destroys_register(), "check");
2398 if (left->is_single_cpu()) {
2399 Register reg = left->as_register();
2400 if (right->is_constant()) {
2401 int val = right->as_constant_ptr()->as_jint();
2402 switch (code) {
2403 case lir_logic_and: __ andl (reg, val); break;
2404 case lir_logic_or: __ orl (reg, val); break;
2405 case lir_logic_xor: __ xorl (reg, val); break;
2406 default: ShouldNotReachHere();
2407 }
2408 } else if (right->is_stack()) {
2409 // added support for stack operands
2410 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2411 switch (code) {
2412 case lir_logic_and: __ andl (reg, raddr); break;
2413 case lir_logic_or: __ orl (reg, raddr); break;
2414 case lir_logic_xor: __ xorl (reg, raddr); break;
2415 default: ShouldNotReachHere();
2416 }
2417 } else {
2418 Register rright = right->as_register();
2419 switch (code) {
2420 case lir_logic_and: __ andptr (reg, rright); break;
2421 case lir_logic_or : __ orptr (reg, rright); break;
2422 case lir_logic_xor: __ xorptr (reg, rright); break;
2423 default: ShouldNotReachHere();
2424 }
2425 }
2426 move_regs(reg, dst->as_register());
2427 } else {
2428 Register l_lo = left->as_register_lo();
2429 Register l_hi = left->as_register_hi();
2430 if (right->is_constant()) {
2431 #ifdef _LP64
2432 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2433 switch (code) {
2434 case lir_logic_and:
2435 __ andq(l_lo, rscratch1);
2436 break;
2437 case lir_logic_or:
2438 __ orq(l_lo, rscratch1);
2439 break;
2440 case lir_logic_xor:
2441 __ xorq(l_lo, rscratch1);
2442 break;
2443 default: ShouldNotReachHere();
2444 }
2445 #else
2446 int r_lo = right->as_constant_ptr()->as_jint_lo();
2447 int r_hi = right->as_constant_ptr()->as_jint_hi();
2448 switch (code) {
2449 case lir_logic_and:
2450 __ andl(l_lo, r_lo);
2451 __ andl(l_hi, r_hi);
2452 break;
2453 case lir_logic_or:
2454 __ orl(l_lo, r_lo);
2455 __ orl(l_hi, r_hi);
2456 break;
2457 case lir_logic_xor:
2458 __ xorl(l_lo, r_lo);
2459 __ xorl(l_hi, r_hi);
2460 break;
2461 default: ShouldNotReachHere();
2462 }
2463 #endif // _LP64
2464 } else {
2465 #ifdef _LP64
2466 Register r_lo;
2467 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2468 r_lo = right->as_register();
2469 } else {
2470 r_lo = right->as_register_lo();
2471 }
2472 #else
2473 Register r_lo = right->as_register_lo();
2474 Register r_hi = right->as_register_hi();
2475 assert(l_lo != r_hi, "overwriting registers");
2476 #endif
2477 switch (code) {
2478 case lir_logic_and:
2479 __ andptr(l_lo, r_lo);
2480 NOT_LP64(__ andptr(l_hi, r_hi);)
2481 break;
2482 case lir_logic_or:
2483 __ orptr(l_lo, r_lo);
2484 NOT_LP64(__ orptr(l_hi, r_hi);)
2485 break;
2486 case lir_logic_xor:
2487 __ xorptr(l_lo, r_lo);
2488 NOT_LP64(__ xorptr(l_hi, r_hi);)
2489 break;
2490 default: ShouldNotReachHere();
2491 }
2492 }
2493
2494 Register dst_lo = dst->as_register_lo();
2495 Register dst_hi = dst->as_register_hi();
2496
2497 #ifdef _LP64
2498 move_regs(l_lo, dst_lo);
2499 #else
2500 if (dst_lo == l_hi) {
2501 assert(dst_hi != l_lo, "overwriting registers");
2502 move_regs(l_hi, dst_hi);
2503 move_regs(l_lo, dst_lo);
2504 } else {
2505 assert(dst_lo != l_hi, "overwriting registers");
2506 move_regs(l_lo, dst_lo);
2507 move_regs(l_hi, dst_hi);
2508 }
2509 #endif // _LP64
2510 }
2511 }
2512
2513
2514 // we assume that rax, and rdx can be overwritten
2515 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2516
2517 assert(left->is_single_cpu(), "left must be register");
2518 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2519 assert(result->is_single_cpu(), "result must be register");
2520
2521 // assert(left->destroys_register(), "check");
2522 // assert(right->destroys_register(), "check");
2523
2524 Register lreg = left->as_register();
2525 Register dreg = result->as_register();
2526
2527 if (right->is_constant()) {
2528 int divisor = right->as_constant_ptr()->as_jint();
2529 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2530 if (code == lir_idiv) {
2531 assert(lreg == rax, "must be rax,");
2532 assert(temp->as_register() == rdx, "tmp register must be rdx");
2533 __ cdql(); // sign extend into rdx:rax
2534 if (divisor == 2) {
2535 __ subl(lreg, rdx);
2536 } else {
2537 __ andl(rdx, divisor - 1);
2538 __ addl(lreg, rdx);
2539 }
2540 __ sarl(lreg, log2_intptr(divisor));
2541 move_regs(lreg, dreg);
2542 } else if (code == lir_irem) {
2543 Label done;
2544 __ mov(dreg, lreg);
2545 __ andl(dreg, 0x80000000 | (divisor - 1));
2546 __ jcc(Assembler::positive, done);
2547 __ decrement(dreg);
2548 __ orl(dreg, ~(divisor - 1));
2549 __ increment(dreg);
2550 __ bind(done);
2551 } else {
2552 ShouldNotReachHere();
2553 }
2554 } else {
2555 Register rreg = right->as_register();
2556 assert(lreg == rax, "left register must be rax,");
2557 assert(rreg != rdx, "right register must not be rdx");
2558 assert(temp->as_register() == rdx, "tmp register must be rdx");
2559
2560 move_regs(lreg, rax);
2561
2562 int idivl_offset = __ corrected_idivl(rreg);
2563 add_debug_info_for_div0(idivl_offset, info);
2564 if (code == lir_irem) {
2565 move_regs(rdx, dreg); // result is in rdx
2566 } else {
2567 move_regs(rax, dreg);
2568 }
2569 }
2570 }
2571
2572
2573 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2574 if (opr1->is_single_cpu()) {
2575 Register reg1 = opr1->as_register();
2576 if (opr2->is_single_cpu()) {
2577 // cpu register - cpu register
2578 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2579 __ cmpptr(reg1, opr2->as_register());
2580 } else {
2581 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2582 __ cmpl(reg1, opr2->as_register());
2583 }
2584 } else if (opr2->is_stack()) {
2585 // cpu register - stack
2586 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2587 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2588 } else {
2589 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2590 }
2591 } else if (opr2->is_constant()) {
2592 // cpu register - constant
2593 LIR_Const* c = opr2->as_constant_ptr();
2594 if (c->type() == T_INT) {
2595 __ cmpl(reg1, c->as_jint());
2596 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2597 // In 64bit oops are single register
2598 jobject o = c->as_jobject();
2599 if (o == NULL) {
2600 __ cmpptr(reg1, (int32_t)NULL_WORD);
2601 } else {
2602 #ifdef _LP64
2603 __ movoop(rscratch1, o);
2604 __ cmpptr(reg1, rscratch1);
2605 #else
2606 __ cmpoop(reg1, c->as_jobject());
2607 #endif // _LP64
2608 }
2609 } else {
2610 ShouldNotReachHere();
2611 }
2612 // cpu register - address
2613 } else if (opr2->is_address()) {
2614 if (op->info() != NULL) {
2615 add_debug_info_for_null_check_here(op->info());
2616 }
2617 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2618 } else {
2619 ShouldNotReachHere();
2620 }
2621
2622 } else if(opr1->is_double_cpu()) {
2623 Register xlo = opr1->as_register_lo();
2624 Register xhi = opr1->as_register_hi();
2625 if (opr2->is_double_cpu()) {
2626 #ifdef _LP64
2627 __ cmpptr(xlo, opr2->as_register_lo());
2628 #else
2629 // cpu register - cpu register
2630 Register ylo = opr2->as_register_lo();
2631 Register yhi = opr2->as_register_hi();
2632 __ subl(xlo, ylo);
2633 __ sbbl(xhi, yhi);
2634 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2635 __ orl(xhi, xlo);
2636 }
2637 #endif // _LP64
2638 } else if (opr2->is_constant()) {
2639 // cpu register - constant 0
2640 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2641 #ifdef _LP64
2642 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2643 #else
2644 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2645 __ orl(xhi, xlo);
2646 #endif // _LP64
2647 } else {
2648 ShouldNotReachHere();
2649 }
2650
2651 } else if (opr1->is_single_xmm()) {
2652 XMMRegister reg1 = opr1->as_xmm_float_reg();
2653 if (opr2->is_single_xmm()) {
2654 // xmm register - xmm register
2655 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2656 } else if (opr2->is_stack()) {
2657 // xmm register - stack
2658 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2659 } else if (opr2->is_constant()) {
2660 // xmm register - constant
2661 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2662 } else if (opr2->is_address()) {
2663 // xmm register - address
2664 if (op->info() != NULL) {
2665 add_debug_info_for_null_check_here(op->info());
2666 }
2667 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2668 } else {
2669 ShouldNotReachHere();
2670 }
2671
2672 } else if (opr1->is_double_xmm()) {
2673 XMMRegister reg1 = opr1->as_xmm_double_reg();
2674 if (opr2->is_double_xmm()) {
2675 // xmm register - xmm register
2676 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2677 } else if (opr2->is_stack()) {
2678 // xmm register - stack
2679 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2680 } else if (opr2->is_constant()) {
2681 // xmm register - constant
2682 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2683 } else if (opr2->is_address()) {
2684 // xmm register - address
2685 if (op->info() != NULL) {
2686 add_debug_info_for_null_check_here(op->info());
2687 }
2688 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2689 } else {
2690 ShouldNotReachHere();
2691 }
2692
2693 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2694 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2695 assert(opr2->is_fpu_register(), "both must be registers");
2696 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2697
2698 } else if (opr1->is_address() && opr2->is_constant()) {
2699 LIR_Const* c = opr2->as_constant_ptr();
2700 #ifdef _LP64
2701 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2702 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2703 __ movoop(rscratch1, c->as_jobject());
2704 }
2705 #endif // LP64
2706 if (op->info() != NULL) {
2707 add_debug_info_for_null_check_here(op->info());
2708 }
2709 // special case: address - constant
2710 LIR_Address* addr = opr1->as_address_ptr();
2711 if (c->type() == T_INT) {
2712 __ cmpl(as_Address(addr), c->as_jint());
2713 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2714 #ifdef _LP64
2715 // %%% Make this explode if addr isn't reachable until we figure out a
2716 // better strategy by giving noreg as the temp for as_Address
2717 __ cmpptr(rscratch1, as_Address(addr, noreg));
2718 #else
2719 __ cmpoop(as_Address(addr), c->as_jobject());
2720 #endif // _LP64
2721 } else {
2722 ShouldNotReachHere();
2723 }
2724
2725 } else {
2726 ShouldNotReachHere();
2727 }
2728 }
2729
2730 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2731 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2732 if (left->is_single_xmm()) {
2733 assert(right->is_single_xmm(), "must match");
2734 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2735 } else if (left->is_double_xmm()) {
2736 assert(right->is_double_xmm(), "must match");
2737 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2738
2739 } else {
2740 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2741 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2742
2743 assert(left->fpu() == 0, "left must be on TOS");
2744 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2745 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2746 }
2747 } else {
2748 assert(code == lir_cmp_l2i, "check");
2749 #ifdef _LP64
2750 Label done;
2751 Register dest = dst->as_register();
2752 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2753 __ movl(dest, -1);
2754 __ jccb(Assembler::less, done);
2755 __ set_byte_if_not_zero(dest);
2756 __ movzbl(dest, dest);
2757 __ bind(done);
2758 #else
2759 __ lcmp2int(left->as_register_hi(),
2760 left->as_register_lo(),
2761 right->as_register_hi(),
2762 right->as_register_lo());
2763 move_regs(left->as_register_hi(), dst->as_register());
2764 #endif // _LP64
2765 }
2766 }
2767
2768
2769 void LIR_Assembler::align_call(LIR_Code code) {
2770 if (os::is_MP()) {
2771 // make sure that the displacement word of the call ends up word aligned
2772 int offset = __ offset();
2773 switch (code) {
2774 case lir_static_call:
2775 case lir_optvirtual_call:
2776 case lir_dynamic_call:
2777 offset += NativeCall::displacement_offset;
2778 break;
2779 case lir_icvirtual_call:
2780 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2781 break;
2782 case lir_virtual_call: // currently, sparc-specific for niagara
2783 default: ShouldNotReachHere();
2784 }
2785 while (offset++ % BytesPerWord != 0) {
2786 __ nop();
2787 }
2788 }
2789 }
2790
2791
2792 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2793 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2794 "must be aligned");
2795 __ call(AddressLiteral(op->addr(), rtype));
2796 add_call_info(code_offset(), op->info());
2797 }
2798
2799
2800 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2801 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2802 __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2803 assert(!os::is_MP() ||
2804 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2805 "must be aligned");
2806 __ call(AddressLiteral(op->addr(), rh));
2807 add_call_info(code_offset(), op->info());
2808 }
2809
2810
2811 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2812 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2813 ShouldNotReachHere();
2814 }
2815
2816
2817 void LIR_Assembler::emit_static_call_stub() {
2818 address call_pc = __ pc();
2819 address stub = __ start_a_stub(call_stub_size);
2820 if (stub == NULL) {
2821 bailout("static call stub overflow");
2822 return;
2823 }
2824
2825 int start = __ offset();
2826 if (os::is_MP()) {
2827 // make sure that the displacement word of the call ends up word aligned
2828 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2829 while (offset++ % BytesPerWord != 0) {
2830 __ nop();
2831 }
2832 }
2833 __ relocate(static_stub_Relocation::spec(call_pc));
2834 __ movoop(rbx, (jobject)NULL);
2835 // must be set to -1 at code generation time
2836 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2837 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2838 __ jump(RuntimeAddress(__ pc()));
2839
2840 assert(__ offset() - start <= call_stub_size, "stub too big");
2841 __ end_a_stub();
2842 }
2843
2844
2845 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2846 assert(exceptionOop->as_register() == rax, "must match");
2847 assert(exceptionPC->as_register() == rdx, "must match");
2848
2849 // exception object is not added to oop map by LinearScan
2850 // (LinearScan assumes that no oops are in fixed registers)
2851 info->add_register_oop(exceptionOop);
2852 Runtime1::StubID unwind_id;
2853
2854 // get current pc information
2855 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2856 int pc_for_athrow_offset = __ offset();
2857 InternalAddress pc_for_athrow(__ pc());
2858 __ lea(exceptionPC->as_register(), pc_for_athrow);
2859 add_call_info(pc_for_athrow_offset, info); // for exception handler
2860
2861 __ verify_not_null_oop(rax);
2862 // search an exception handler (rax: exception oop, rdx: throwing pc)
2863 if (compilation()->has_fpu_code()) {
2864 unwind_id = Runtime1::handle_exception_id;
2865 } else {
2866 unwind_id = Runtime1::handle_exception_nofpu_id;
2867 }
2868 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2869
2870 // enough room for two byte trap
2871 __ nop();
2872 }
2873
2874
2875 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2876 assert(exceptionOop->as_register() == rax, "must match");
2877
2878 __ jmp(_unwind_handler_entry);
2879 }
2880
2881
2882 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2883
2884 // optimized version for linear scan:
2885 // * count must be already in ECX (guaranteed by LinearScan)
2886 // * left and dest must be equal
2887 // * tmp must be unused
2888 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2889 assert(left == dest, "left and dest must be equal");
2890 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2891
2892 if (left->is_single_cpu()) {
2893 Register value = left->as_register();
2894 assert(value != SHIFT_count, "left cannot be ECX");
2895
2896 switch (code) {
2897 case lir_shl: __ shll(value); break;
2898 case lir_shr: __ sarl(value); break;
2899 case lir_ushr: __ shrl(value); break;
2900 default: ShouldNotReachHere();
2901 }
2902 } else if (left->is_double_cpu()) {
2903 Register lo = left->as_register_lo();
2904 Register hi = left->as_register_hi();
2905 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2906 #ifdef _LP64
2907 switch (code) {
2908 case lir_shl: __ shlptr(lo); break;
2909 case lir_shr: __ sarptr(lo); break;
2910 case lir_ushr: __ shrptr(lo); break;
2911 default: ShouldNotReachHere();
2912 }
2913 #else
2914
2915 switch (code) {
2916 case lir_shl: __ lshl(hi, lo); break;
2917 case lir_shr: __ lshr(hi, lo, true); break;
2918 case lir_ushr: __ lshr(hi, lo, false); break;
2919 default: ShouldNotReachHere();
2920 }
2921 #endif // LP64
2922 } else {
2923 ShouldNotReachHere();
2924 }
2925 }
2926
2927
2928 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2929 if (dest->is_single_cpu()) {
2930 // first move left into dest so that left is not destroyed by the shift
2931 Register value = dest->as_register();
2932 count = count & 0x1F; // Java spec
2933
2934 move_regs(left->as_register(), value);
2935 switch (code) {
2936 case lir_shl: __ shll(value, count); break;
2937 case lir_shr: __ sarl(value, count); break;
2938 case lir_ushr: __ shrl(value, count); break;
2939 default: ShouldNotReachHere();
2940 }
2941 } else if (dest->is_double_cpu()) {
2942 #ifndef _LP64
2943 Unimplemented();
2944 #else
2945 // first move left into dest so that left is not destroyed by the shift
2946 Register value = dest->as_register_lo();
2947 count = count & 0x1F; // Java spec
2948
2949 move_regs(left->as_register_lo(), value);
2950 switch (code) {
2951 case lir_shl: __ shlptr(value, count); break;
2952 case lir_shr: __ sarptr(value, count); break;
2953 case lir_ushr: __ shrptr(value, count); break;
2954 default: ShouldNotReachHere();
2955 }
2956 #endif // _LP64
2957 } else {
2958 ShouldNotReachHere();
2959 }
2960 }
2961
2962
2963 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2964 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2965 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2966 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2967 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2968 }
2969
2970
2971 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2972 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2973 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2974 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2975 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2976 }
2977
2978
2979 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2980 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2981 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2982 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2983 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
2984 }
2985
2986
2987 // This code replaces a call to arraycopy; no exception may
2988 // be thrown in this code, they must be thrown in the System.arraycopy
2989 // activation frame; we could save some checks if this would not be the case
2990 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2991 ciArrayKlass* default_type = op->expected_type();
2992 Register src = op->src()->as_register();
2993 Register dst = op->dst()->as_register();
2994 Register src_pos = op->src_pos()->as_register();
2995 Register dst_pos = op->dst_pos()->as_register();
2996 Register length = op->length()->as_register();
2997 Register tmp = op->tmp()->as_register();
2998
2999 CodeStub* stub = op->stub();
3000 int flags = op->flags();
3001 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3002 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3003
3004 // if we don't know anything or it's an object array, just go through the generic arraycopy
3005 if (default_type == NULL) {
3006 Label done;
3007 // save outgoing arguments on stack in case call to System.arraycopy is needed
3008 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3009 // for interpreter calling conventions. Now we have to do it in new style conventions.
3010 // For the moment until C1 gets the new register allocator I just force all the
3011 // args to the right place (except the register args) and then on the back side
3012 // reload the register args properly if we go slow path. Yuck
3013
3014 // These are proper for the calling convention
3015
3016 store_parameter(length, 2);
3017 store_parameter(dst_pos, 1);
3018 store_parameter(dst, 0);
3019
3020 // these are just temporary placements until we need to reload
3021 store_parameter(src_pos, 3);
3022 store_parameter(src, 4);
3023 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3024
3025 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3026
3027 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3028 #ifdef _LP64
3029 // The arguments are in java calling convention so we can trivially shift them to C
3030 // convention
3031 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3032 __ mov(c_rarg0, j_rarg0);
3033 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3034 __ mov(c_rarg1, j_rarg1);
3035 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3036 __ mov(c_rarg2, j_rarg2);
3037 assert_different_registers(c_rarg3, j_rarg4);
3038 __ mov(c_rarg3, j_rarg3);
3039 #ifdef _WIN64
3040 // Allocate abi space for args but be sure to keep stack aligned
3041 __ subptr(rsp, 6*wordSize);
3042 store_parameter(j_rarg4, 4);
3043 __ call(RuntimeAddress(entry));
3044 __ addptr(rsp, 6*wordSize);
3045 #else
3046 __ mov(c_rarg4, j_rarg4);
3047 __ call(RuntimeAddress(entry));
3048 #endif // _WIN64
3049 #else
3050 __ push(length);
3051 __ push(dst_pos);
3052 __ push(dst);
3053 __ push(src_pos);
3054 __ push(src);
3055 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3056
3057 #endif // _LP64
3058
3059 __ cmpl(rax, 0);
3060 __ jcc(Assembler::equal, *stub->continuation());
3061
3062 // Reload values from the stack so they are where the stub
3063 // expects them.
3064 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3065 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3066 __ movptr (length, Address(rsp, 2*BytesPerWord));
3067 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3068 __ movptr (src, Address(rsp, 4*BytesPerWord));
3069 __ jmp(*stub->entry());
3070
3071 __ bind(*stub->continuation());
3072 return;
3073 }
3074
3075 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3076
3077 int elem_size = type2aelembytes(basic_type);
3078 int shift_amount;
3079 Address::ScaleFactor scale;
3080
3081 switch (elem_size) {
3082 case 1 :
3083 shift_amount = 0;
3084 scale = Address::times_1;
3085 break;
3086 case 2 :
3087 shift_amount = 1;
3088 scale = Address::times_2;
3089 break;
3090 case 4 :
3091 shift_amount = 2;
3092 scale = Address::times_4;
3093 break;
3094 case 8 :
3095 shift_amount = 3;
3096 scale = Address::times_8;
3097 break;
3098 default:
3099 ShouldNotReachHere();
3100 }
3101
3102 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3103 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3104 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3105 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3106
3107 // length and pos's are all sign extended at this point on 64bit
3108
3109 // test for NULL
3110 if (flags & LIR_OpArrayCopy::src_null_check) {
3111 __ testptr(src, src);
3112 __ jcc(Assembler::zero, *stub->entry());
3113 }
3114 if (flags & LIR_OpArrayCopy::dst_null_check) {
3115 __ testptr(dst, dst);
3116 __ jcc(Assembler::zero, *stub->entry());
3117 }
3118
3119 // check if negative
3120 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3121 __ testl(src_pos, src_pos);
3122 __ jcc(Assembler::less, *stub->entry());
3123 }
3124 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3125 __ testl(dst_pos, dst_pos);
3126 __ jcc(Assembler::less, *stub->entry());
3127 }
3128 if (flags & LIR_OpArrayCopy::length_positive_check) {
3129 __ testl(length, length);
3130 __ jcc(Assembler::less, *stub->entry());
3131 }
3132
3133 if (flags & LIR_OpArrayCopy::src_range_check) {
3134 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3135 __ cmpl(tmp, src_length_addr);
3136 __ jcc(Assembler::above, *stub->entry());
3137 }
3138 if (flags & LIR_OpArrayCopy::dst_range_check) {
3139 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3140 __ cmpl(tmp, dst_length_addr);
3141 __ jcc(Assembler::above, *stub->entry());
3142 }
3143
3144 if (flags & LIR_OpArrayCopy::type_check) {
3145 __ movptr(tmp, src_klass_addr);
3146 __ cmpptr(tmp, dst_klass_addr);
3147 __ jcc(Assembler::notEqual, *stub->entry());
3148 }
3149
3150 #ifdef ASSERT
3151 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3152 // Sanity check the known type with the incoming class. For the
3153 // primitive case the types must match exactly with src.klass and
3154 // dst.klass each exactly matching the default type. For the
3155 // object array case, if no type check is needed then either the
3156 // dst type is exactly the expected type and the src type is a
3157 // subtype which we can't check or src is the same array as dst
3158 // but not necessarily exactly of type default_type.
3159 Label known_ok, halt;
3160 __ movoop(tmp, default_type->constant_encoding());
3161 if (basic_type != T_OBJECT) {
3162 __ cmpptr(tmp, dst_klass_addr);
3163 __ jcc(Assembler::notEqual, halt);
3164 __ cmpptr(tmp, src_klass_addr);
3165 __ jcc(Assembler::equal, known_ok);
3166 } else {
3167 __ cmpptr(tmp, dst_klass_addr);
3168 __ jcc(Assembler::equal, known_ok);
3169 __ cmpptr(src, dst);
3170 __ jcc(Assembler::equal, known_ok);
3171 }
3172 __ bind(halt);
3173 __ stop("incorrect type information in arraycopy");
3174 __ bind(known_ok);
3175 }
3176 #endif
3177
3178 if (shift_amount > 0 && basic_type != T_OBJECT) {
3179 __ shlptr(length, shift_amount);
3180 }
3181
3182 #ifdef _LP64
3183 assert_different_registers(c_rarg0, dst, dst_pos, length);
3184 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3185 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3186 assert_different_registers(c_rarg1, length);
3187 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3188 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3189 __ mov(c_rarg2, length);
3190
3191 #else
3192 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3193 store_parameter(tmp, 0);
3194 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3195 store_parameter(tmp, 1);
3196 store_parameter(length, 2);
3197 #endif // _LP64
3198 if (basic_type == T_OBJECT) {
3199 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3200 } else {
3201 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3202 }
3203
3204 __ bind(*stub->continuation());
3205 }
3206
3207
3208 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3209 Register obj = op->obj_opr()->as_register(); // may not be an oop
3210 Register hdr = op->hdr_opr()->as_register();
3211 Register lock = op->lock_opr()->as_register();
3212 if (!UseFastLocking) {
3213 __ jmp(*op->stub()->entry());
3214 } else if (op->code() == lir_lock) {
3215 Register scratch = noreg;
3216 if (UseBiasedLocking) {
3217 scratch = op->scratch_opr()->as_register();
3218 }
3219 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3220 // add debug info for NullPointerException only if one is possible
3221 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3222 if (op->info() != NULL) {
3223 add_debug_info_for_null_check(null_check_offset, op->info());
3224 }
3225 // done
3226 } else if (op->code() == lir_unlock) {
3227 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3228 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3229 } else {
3230 Unimplemented();
3231 }
3232 __ bind(*op->stub()->continuation());
3233 }
3234
3235
3236 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3237 ciMethod* method = op->profiled_method();
3238 int bci = op->profiled_bci();
3239
3240 // Update counter for all call types
3241 ciMethodData* md = method->method_data();
3242 if (md == NULL) {
3243 bailout("out of memory building methodDataOop");
3244 return;
3245 }
3246 ciProfileData* data = md->bci_to_data(bci);
3247 assert(data->is_CounterData(), "need CounterData for calls");
3248 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3249 Register mdo = op->mdo()->as_register();
3250 __ movoop(mdo, md->constant_encoding());
3251 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3252 Bytecodes::Code bc = method->java_code_at_bci(bci);
3253 // Perform additional virtual call profiling for invokevirtual and
3254 // invokeinterface bytecodes
3255 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3256 Tier1ProfileVirtualCalls) {
3257 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3258 Register recv = op->recv()->as_register();
3259 assert_different_registers(mdo, recv);
3260 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3261 ciKlass* known_klass = op->known_holder();
3262 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
3263 // We know the type that will be seen at this call site; we can
3264 // statically update the methodDataOop rather than needing to do
3265 // dynamic tests on the receiver type
3266
3267 // NOTE: we should probably put a lock around this search to
3268 // avoid collisions by concurrent compilations
3269 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3270 uint i;
3271 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3272 ciKlass* receiver = vc_data->receiver(i);
3273 if (known_klass->equals(receiver)) {
3274 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3275 __ addl(data_addr, DataLayout::counter_increment);
3276 return;
3277 }
3278 }
3279
3280 // Receiver type not found in profile data; select an empty slot
3281
3282 // Note that this is less efficient than it should be because it
3283 // always does a write to the receiver part of the
3284 // VirtualCallData rather than just the first time
3285 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3286 ciKlass* receiver = vc_data->receiver(i);
3287 if (receiver == NULL) {
3288 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3289 __ movoop(recv_addr, known_klass->constant_encoding());
3290 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3291 __ addl(data_addr, DataLayout::counter_increment);
3292 return;
3293 }
3294 }
3295 } else {
3296 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3297 Label update_done;
3298 uint i;
3299 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3300 Label next_test;
3301 // See if the receiver is receiver[n].
3302 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
3303 __ jcc(Assembler::notEqual, next_test);
3304 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3305 __ addl(data_addr, DataLayout::counter_increment);
3306 __ jmp(update_done);
3307 __ bind(next_test);
3308 }
3309
3310 // Didn't find receiver; find next empty slot and fill it in
3311 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3312 Label next_test;
3313 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3314 __ cmpptr(recv_addr, (int32_t)NULL_WORD);
3315 __ jcc(Assembler::notEqual, next_test);
3316 __ movptr(recv_addr, recv);
3317 __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment);
3318 __ jmp(update_done);
3319 __ bind(next_test);
3320 }
3321 // Receiver did not match any saved receiver and there is no empty row for it.
3322 // Increment total counter to indicate polymorphic case.
3323 __ addl(counter_addr, DataLayout::counter_increment);
3324
3325 __ bind(update_done);
3326 }
3327 } else {
3328 // Static call
3329 __ addl(counter_addr, DataLayout::counter_increment);
3330 }
3331 }
3332
3333
3334 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3335 Unimplemented();
3336 }
3337
3338
3339 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3340 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3341 }
3342
3343
3344 void LIR_Assembler::align_backward_branch_target() {
3345 __ align(BytesPerWord);
3346 }
3347
3348
3349 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3350 if (left->is_single_cpu()) {
3351 __ negl(left->as_register());
3352 move_regs(left->as_register(), dest->as_register());
3353
3354 } else if (left->is_double_cpu()) {
3355 Register lo = left->as_register_lo();
3356 #ifdef _LP64
3357 Register dst = dest->as_register_lo();
3358 __ movptr(dst, lo);
3359 __ negptr(dst);
3360 #else
3361 Register hi = left->as_register_hi();
3362 __ lneg(hi, lo);
3363 if (dest->as_register_lo() == hi) {
3364 assert(dest->as_register_hi() != lo, "destroying register");
3365 move_regs(hi, dest->as_register_hi());
3366 move_regs(lo, dest->as_register_lo());
3367 } else {
3368 move_regs(lo, dest->as_register_lo());
3369 move_regs(hi, dest->as_register_hi());
3370 }
3371 #endif // _LP64
3372
3373 } else if (dest->is_single_xmm()) {
3374 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3375 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3376 }
3377 __ xorps(dest->as_xmm_float_reg(),
3378 ExternalAddress((address)float_signflip_pool));
3379
3380 } else if (dest->is_double_xmm()) {
3381 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3382 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3383 }
3384 __ xorpd(dest->as_xmm_double_reg(),
3385 ExternalAddress((address)double_signflip_pool));
3386
3387 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3388 assert(left->fpu() == 0, "arg must be on TOS");
3389 assert(dest->fpu() == 0, "dest must be TOS");
3390 __ fchs();
3391
3392 } else {
3393 ShouldNotReachHere();
3394 }
3395 }
3396
3397
3398 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3399 assert(addr->is_address() && dest->is_register(), "check");
3400 Register reg;
3401 reg = dest->as_pointer_register();
3402 __ lea(reg, as_Address(addr->as_address_ptr()));
3403 }
3404
3405
3406
3407 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3408 assert(!tmp->is_valid(), "don't need temporary");
3409 __ call(RuntimeAddress(dest));
3410 if (info != NULL) {
3411 add_call_info_here(info);
3412 }
3413 }
3414
3415
3416 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3417 assert(type == T_LONG, "only for volatile long fields");
3418
3419 if (info != NULL) {
3420 add_debug_info_for_null_check_here(info);
3421 }
3422
3423 if (src->is_double_xmm()) {
3424 if (dest->is_double_cpu()) {
3425 #ifdef _LP64
3426 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3427 #else
3428 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3429 __ psrlq(src->as_xmm_double_reg(), 32);
3430 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3431 #endif // _LP64
3432 } else if (dest->is_double_stack()) {
3433 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3434 } else if (dest->is_address()) {
3435 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3436 } else {
3437 ShouldNotReachHere();
3438 }
3439
3440 } else if (dest->is_double_xmm()) {
3441 if (src->is_double_stack()) {
3442 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3443 } else if (src->is_address()) {
3444 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3445 } else {
3446 ShouldNotReachHere();
3447 }
3448
3449 } else if (src->is_double_fpu()) {
3450 assert(src->fpu_regnrLo() == 0, "must be TOS");
3451 if (dest->is_double_stack()) {
3452 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3453 } else if (dest->is_address()) {
3454 __ fistp_d(as_Address(dest->as_address_ptr()));
3455 } else {
3456 ShouldNotReachHere();
3457 }
3458
3459 } else if (dest->is_double_fpu()) {
3460 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3461 if (src->is_double_stack()) {
3462 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3463 } else if (src->is_address()) {
3464 __ fild_d(as_Address(src->as_address_ptr()));
3465 } else {
3466 ShouldNotReachHere();
3467 }
3468 } else {
3469 ShouldNotReachHere();
3470 }
3471 }
3472
3473
3474 void LIR_Assembler::membar() {
3475 // QQQ sparc TSO uses this,
3476 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3477 }
3478
3479 void LIR_Assembler::membar_acquire() {
3480 // No x86 machines currently require load fences
3481 // __ load_fence();
3482 }
3483
3484 void LIR_Assembler::membar_release() {
3485 // No x86 machines currently require store fences
3486 // __ store_fence();
3487 }
3488
3489 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3490 assert(result_reg->is_register(), "check");
3491 #ifdef _LP64
3492 // __ get_thread(result_reg->as_register_lo());
3493 __ mov(result_reg->as_register(), r15_thread);
3494 #else
3495 __ get_thread(result_reg->as_register());
3496 #endif // _LP64
3497 }
3498
3499
3500 void LIR_Assembler::peephole(LIR_List*) {
3501 // do nothing for now
3502 }
3503
3504
3505 #undef __