1 /* 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP 27 28 class BiasedLockingCounters; 29 30 // Contains all the definitions needed for x86 assembly code generation. 31 32 // Calling convention 33 class Argument VALUE_OBJ_CLASS_SPEC { 34 public: 35 enum { 36 #ifdef _LP64 37 #ifdef _WIN64 38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 40 #else 41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 43 #endif // _WIN64 44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 46 #else 47 n_register_parameters = 0 // 0 registers used to pass arguments 48 #endif // _LP64 49 }; 50 }; 51 52 53 #ifdef _LP64 54 // Symbolically name the register arguments used by the c calling convention. 55 // Windows is different from linux/solaris. So much for standards... 56 57 #ifdef _WIN64 58 59 REGISTER_DECLARATION(Register, c_rarg0, rcx); 60 REGISTER_DECLARATION(Register, c_rarg1, rdx); 61 REGISTER_DECLARATION(Register, c_rarg2, r8); 62 REGISTER_DECLARATION(Register, c_rarg3, r9); 63 64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 68 69 #else 70 71 REGISTER_DECLARATION(Register, c_rarg0, rdi); 72 REGISTER_DECLARATION(Register, c_rarg1, rsi); 73 REGISTER_DECLARATION(Register, c_rarg2, rdx); 74 REGISTER_DECLARATION(Register, c_rarg3, rcx); 75 REGISTER_DECLARATION(Register, c_rarg4, r8); 76 REGISTER_DECLARATION(Register, c_rarg5, r9); 77 78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 86 87 #endif // _WIN64 88 89 // Symbolically name the register arguments used by the Java calling convention. 90 // We have control over the convention for java so we can do what we please. 91 // What pleases us is to offset the java calling convention so that when 92 // we call a suitable jni method the arguments are lined up and we don't 93 // have to do little shuffling. A suitable jni method is non-static and a 94 // small number of arguments (two fewer args on windows) 95 // 96 // |-------------------------------------------------------| 97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 98 // |-------------------------------------------------------| 99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 100 // | rdi rsi rdx rcx r8 r9 | solaris/linux 101 // |-------------------------------------------------------| 102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 103 // |-------------------------------------------------------| 104 105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 108 // Windows runs out of register args here 109 #ifdef _WIN64 110 REGISTER_DECLARATION(Register, j_rarg3, rdi); 111 REGISTER_DECLARATION(Register, j_rarg4, rsi); 112 #else 113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 115 #endif /* _WIN64 */ 116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 117 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 126 127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 129 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 132 133 #else 134 // rscratch1 will apear in 32bit code that is dead but of course must compile 135 // Using noreg ensures if the dead code is incorrectly live and executed it 136 // will cause an assertion failure 137 #define rscratch1 noreg 138 #define rscratch2 noreg 139 140 #endif // _LP64 141 142 // JSR 292 fixed register usages: 143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); 144 145 // Address is an abstraction used to represent a memory location 146 // using any of the amd64 addressing modes with one object. 147 // 148 // Note: A register location is represented via a Register, not 149 // via an address for efficiency & simplicity reasons. 150 151 class ArrayAddress; 152 153 class Address VALUE_OBJ_CLASS_SPEC { 154 public: 155 enum ScaleFactor { 156 no_scale = -1, 157 times_1 = 0, 158 times_2 = 1, 159 times_4 = 2, 160 times_8 = 3, 161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 162 }; 163 static ScaleFactor times(int size) { 164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 165 if (size == 8) return times_8; 166 if (size == 4) return times_4; 167 if (size == 2) return times_2; 168 return times_1; 169 } 170 static int scale_size(ScaleFactor scale) { 171 assert(scale != no_scale, ""); 172 assert(((1 << (int)times_1) == 1 && 173 (1 << (int)times_2) == 2 && 174 (1 << (int)times_4) == 4 && 175 (1 << (int)times_8) == 8), ""); 176 return (1 << (int)scale); 177 } 178 179 private: 180 Register _base; 181 Register _index; 182 ScaleFactor _scale; 183 int _disp; 184 RelocationHolder _rspec; 185 186 // Easily misused constructors make them private 187 // %%% can we make these go away? 188 NOT_LP64(Address(address loc, RelocationHolder spec);) 189 Address(int disp, address loc, relocInfo::relocType rtype); 190 Address(int disp, address loc, RelocationHolder spec); 191 192 public: 193 194 int disp() { return _disp; } 195 // creation 196 Address() 197 : _base(noreg), 198 _index(noreg), 199 _scale(no_scale), 200 _disp(0) { 201 } 202 203 // No default displacement otherwise Register can be implicitly 204 // converted to 0(Register) which is quite a different animal. 205 206 Address(Register base, int disp) 207 : _base(base), 208 _index(noreg), 209 _scale(no_scale), 210 _disp(disp) { 211 } 212 213 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 214 : _base (base), 215 _index(index), 216 _scale(scale), 217 _disp (disp) { 218 assert(!index->is_valid() == (scale == Address::no_scale), 219 "inconsistent address"); 220 } 221 222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) 223 : _base (base), 224 _index(index.register_or_noreg()), 225 _scale(scale), 226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { 227 if (!index.is_register()) scale = Address::no_scale; 228 assert(!_index->is_valid() == (scale == Address::no_scale), 229 "inconsistent address"); 230 } 231 232 Address plus_disp(int disp) const { 233 Address a = (*this); 234 a._disp += disp; 235 return a; 236 } 237 238 // The following two overloads are used in connection with the 239 // ByteSize type (see sizes.hpp). They simplify the use of 240 // ByteSize'd arguments in assembly code. Note that their equivalent 241 // for the optimized build are the member functions with int disp 242 // argument since ByteSize is mapped to an int type in that case. 243 // 244 // Note: DO NOT introduce similar overloaded functions for WordSize 245 // arguments as in the optimized mode, both ByteSize and WordSize 246 // are mapped to the same type and thus the compiler cannot make a 247 // distinction anymore (=> compiler errors). 248 249 #ifdef ASSERT 250 Address(Register base, ByteSize disp) 251 : _base(base), 252 _index(noreg), 253 _scale(no_scale), 254 _disp(in_bytes(disp)) { 255 } 256 257 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 258 : _base(base), 259 _index(index), 260 _scale(scale), 261 _disp(in_bytes(disp)) { 262 assert(!index->is_valid() == (scale == Address::no_scale), 263 "inconsistent address"); 264 } 265 266 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) 267 : _base (base), 268 _index(index.register_or_noreg()), 269 _scale(scale), 270 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { 271 if (!index.is_register()) scale = Address::no_scale; 272 assert(!_index->is_valid() == (scale == Address::no_scale), 273 "inconsistent address"); 274 } 275 276 #endif // ASSERT 277 278 // accessors 279 bool uses(Register reg) const { return _base == reg || _index == reg; } 280 Register base() const { return _base; } 281 Register index() const { return _index; } 282 ScaleFactor scale() const { return _scale; } 283 int disp() const { return _disp; } 284 285 // Convert the raw encoding form into the form expected by the constructor for 286 // Address. An index of 4 (rsp) corresponds to having no index, so convert 287 // that to noreg for the Address constructor. 288 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); 289 290 static Address make_array(ArrayAddress); 291 292 private: 293 bool base_needs_rex() const { 294 return _base != noreg && _base->encoding() >= 8; 295 } 296 297 bool index_needs_rex() const { 298 return _index != noreg &&_index->encoding() >= 8; 299 } 300 301 relocInfo::relocType reloc() const { return _rspec.type(); } 302 303 friend class Assembler; 304 friend class MacroAssembler; 305 friend class LIR_Assembler; // base/index/scale/disp 306 }; 307 308 // 309 // AddressLiteral has been split out from Address because operands of this type 310 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 311 // the few instructions that need to deal with address literals are unique and the 312 // MacroAssembler does not have to implement every instruction in the Assembler 313 // in order to search for address literals that may need special handling depending 314 // on the instruction and the platform. As small step on the way to merging i486/amd64 315 // directories. 316 // 317 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 318 friend class ArrayAddress; 319 RelocationHolder _rspec; 320 // Typically we use AddressLiterals we want to use their rval 321 // However in some situations we want the lval (effect address) of the item. 322 // We provide a special factory for making those lvals. 323 bool _is_lval; 324 325 // If the target is far we'll need to load the ea of this to 326 // a register to reach it. Otherwise if near we can do rip 327 // relative addressing. 328 329 address _target; 330 331 protected: 332 // creation 333 AddressLiteral() 334 : _is_lval(false), 335 _target(NULL) 336 {} 337 338 public: 339 340 341 AddressLiteral(address target, relocInfo::relocType rtype); 342 343 AddressLiteral(address target, RelocationHolder const& rspec) 344 : _rspec(rspec), 345 _is_lval(false), 346 _target(target) 347 {} 348 349 AddressLiteral addr() { 350 AddressLiteral ret = *this; 351 ret._is_lval = true; 352 return ret; 353 } 354 355 356 private: 357 358 address target() { return _target; } 359 bool is_lval() { return _is_lval; } 360 361 relocInfo::relocType reloc() const { return _rspec.type(); } 362 const RelocationHolder& rspec() const { return _rspec; } 363 364 friend class Assembler; 365 friend class MacroAssembler; 366 friend class Address; 367 friend class LIR_Assembler; 368 }; 369 370 // Convience classes 371 class RuntimeAddress: public AddressLiteral { 372 373 public: 374 375 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 376 377 }; 378 379 class OopAddress: public AddressLiteral { 380 381 public: 382 383 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} 384 385 }; 386 387 class ExternalAddress: public AddressLiteral { 388 389 public: 390 391 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} 392 393 }; 394 395 class InternalAddress: public AddressLiteral { 396 397 public: 398 399 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 400 401 }; 402 403 // x86 can do array addressing as a single operation since disp can be an absolute 404 // address amd64 can't. We create a class that expresses the concept but does extra 405 // magic on amd64 to get the final result 406 407 class ArrayAddress VALUE_OBJ_CLASS_SPEC { 408 private: 409 410 AddressLiteral _base; 411 Address _index; 412 413 public: 414 415 ArrayAddress() {}; 416 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 417 AddressLiteral base() { return _base; } 418 Address index() { return _index; } 419 420 }; 421 422 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 423 424 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 425 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 426 // is what you get. The Assembler is generating code into a CodeBuffer. 427 428 class Assembler : public AbstractAssembler { 429 friend class AbstractAssembler; // for the non-virtual hack 430 friend class LIR_Assembler; // as_Address() 431 friend class StubGenerator; 432 433 public: 434 enum Condition { // The x86 condition codes used for conditional jumps/moves. 435 zero = 0x4, 436 notZero = 0x5, 437 equal = 0x4, 438 notEqual = 0x5, 439 less = 0xc, 440 lessEqual = 0xe, 441 greater = 0xf, 442 greaterEqual = 0xd, 443 below = 0x2, 444 belowEqual = 0x6, 445 above = 0x7, 446 aboveEqual = 0x3, 447 overflow = 0x0, 448 noOverflow = 0x1, 449 carrySet = 0x2, 450 carryClear = 0x3, 451 negative = 0x8, 452 positive = 0x9, 453 parity = 0xa, 454 noParity = 0xb 455 }; 456 457 enum Prefix { 458 // segment overrides 459 CS_segment = 0x2e, 460 SS_segment = 0x36, 461 DS_segment = 0x3e, 462 ES_segment = 0x26, 463 FS_segment = 0x64, 464 GS_segment = 0x65, 465 466 REX = 0x40, 467 468 REX_B = 0x41, 469 REX_X = 0x42, 470 REX_XB = 0x43, 471 REX_R = 0x44, 472 REX_RB = 0x45, 473 REX_RX = 0x46, 474 REX_RXB = 0x47, 475 476 REX_W = 0x48, 477 478 REX_WB = 0x49, 479 REX_WX = 0x4A, 480 REX_WXB = 0x4B, 481 REX_WR = 0x4C, 482 REX_WRB = 0x4D, 483 REX_WRX = 0x4E, 484 REX_WRXB = 0x4F 485 }; 486 487 enum WhichOperand { 488 // input to locate_operand, and format code for relocations 489 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 490 disp32_operand = 1, // embedded 32-bit displacement or address 491 call32_operand = 2, // embedded 32-bit self-relative displacement 492 #ifndef _LP64 493 _WhichOperand_limit = 3 494 #else 495 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 496 _WhichOperand_limit = 4 497 #endif 498 }; 499 500 501 502 // NOTE: The general philopsophy of the declarations here is that 64bit versions 503 // of instructions are freely declared without the need for wrapping them an ifdef. 504 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 505 // In the .cpp file the implementations are wrapped so that they are dropped out 506 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL 507 // to the size it was prior to merging up the 32bit and 64bit assemblers. 508 // 509 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 510 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 511 512 private: 513 514 515 // 64bit prefixes 516 int prefix_and_encode(int reg_enc, bool byteinst = false); 517 int prefixq_and_encode(int reg_enc); 518 519 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); 520 int prefixq_and_encode(int dst_enc, int src_enc); 521 522 void prefix(Register reg); 523 void prefix(Address adr); 524 void prefixq(Address adr); 525 526 void prefix(Address adr, Register reg, bool byteinst = false); 527 void prefixq(Address adr, Register reg); 528 529 void prefix(Address adr, XMMRegister reg); 530 531 void prefetch_prefix(Address src); 532 533 // Helper functions for groups of instructions 534 void emit_arith_b(int op1, int op2, Register dst, int imm8); 535 536 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 537 // only 32bit?? 538 void emit_arith(int op1, int op2, Register dst, jobject obj); 539 void emit_arith(int op1, int op2, Register dst, Register src); 540 541 void emit_operand(Register reg, 542 Register base, Register index, Address::ScaleFactor scale, 543 int disp, 544 RelocationHolder const& rspec, 545 int rip_relative_correction = 0); 546 547 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); 548 549 // operands that only take the original 32bit registers 550 void emit_operand32(Register reg, Address adr); 551 552 void emit_operand(XMMRegister reg, 553 Register base, Register index, Address::ScaleFactor scale, 554 int disp, 555 RelocationHolder const& rspec); 556 557 void emit_operand(XMMRegister reg, Address adr); 558 559 void emit_operand(MMXRegister reg, Address adr); 560 561 // workaround gcc (3.2.1-7) bug 562 void emit_operand(Address adr, MMXRegister reg); 563 564 565 // Immediate-to-memory forms 566 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 567 568 void emit_farith(int b1, int b2, int i); 569 570 571 protected: 572 #ifdef ASSERT 573 void check_relocation(RelocationHolder const& rspec, int format); 574 #endif 575 576 inline void emit_long64(jlong x); 577 578 void emit_data(jint data, relocInfo::relocType rtype, int format); 579 void emit_data(jint data, RelocationHolder const& rspec, int format); 580 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 581 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 582 583 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 584 585 // These are all easily abused and hence protected 586 587 // 32BIT ONLY SECTION 588 #ifndef _LP64 589 // Make these disappear in 64bit mode since they would never be correct 590 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 591 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 592 593 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 594 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 595 596 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 597 #else 598 // 64BIT ONLY SECTION 599 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 600 601 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); 602 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); 603 604 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); 605 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); 606 #endif // _LP64 607 608 // These are unique in that we are ensured by the caller that the 32bit 609 // relative in these instructions will always be able to reach the potentially 610 // 64bit address described by entry. Since they can take a 64bit address they 611 // don't have the 32 suffix like the other instructions in this class. 612 613 void call_literal(address entry, RelocationHolder const& rspec); 614 void jmp_literal(address entry, RelocationHolder const& rspec); 615 616 // Avoid using directly section 617 // Instructions in this section are actually usable by anyone without danger 618 // of failure but have performance issues that are addressed my enhanced 619 // instructions which will do the proper thing base on the particular cpu. 620 // We protect them because we don't trust you... 621 622 // Don't use next inc() and dec() methods directly. INC & DEC instructions 623 // could cause a partial flag stall since they don't set CF flag. 624 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 625 // which call inc() & dec() or add() & sub() in accordance with 626 // the product flag UseIncDec value. 627 628 void decl(Register dst); 629 void decl(Address dst); 630 void decq(Register dst); 631 void decq(Address dst); 632 633 void incl(Register dst); 634 void incl(Address dst); 635 void incq(Register dst); 636 void incq(Address dst); 637 638 // New cpus require use of movsd and movss to avoid partial register stall 639 // when loading from memory. But for old Opteron use movlpd instead of movsd. 640 // The selection is done in MacroAssembler::movdbl() and movflt(). 641 642 // Move Scalar Single-Precision Floating-Point Values 643 void movss(XMMRegister dst, Address src); 644 void movss(XMMRegister dst, XMMRegister src); 645 void movss(Address dst, XMMRegister src); 646 647 // Move Scalar Double-Precision Floating-Point Values 648 void movsd(XMMRegister dst, Address src); 649 void movsd(XMMRegister dst, XMMRegister src); 650 void movsd(Address dst, XMMRegister src); 651 void movlpd(XMMRegister dst, Address src); 652 653 // New cpus require use of movaps and movapd to avoid partial register stall 654 // when moving between registers. 655 void movaps(XMMRegister dst, XMMRegister src); 656 void movapd(XMMRegister dst, XMMRegister src); 657 658 // End avoid using directly 659 660 661 // Instruction prefixes 662 void prefix(Prefix p); 663 664 public: 665 666 // Creation 667 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} 668 669 // Decoding 670 static address locate_operand(address inst, WhichOperand which); 671 static address locate_next_instruction(address inst); 672 673 // Utilities 674 675 #ifdef _LP64 676 static bool is_simm(int64_t x, int nbits) { return -(CONST64(1) << (nbits-1)) <= x && 677 x < (CONST64(1) << (nbits-1)); } 678 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } 679 #else 680 static bool is_simm(int32_t x, int nbits) { return -(1 << (nbits-1)) <= x && 681 x < (1 << (nbits-1)); } 682 static bool is_simm32(int32_t x) { return true; } 683 #endif // _LP64 684 685 static bool is_polling_page_far() NOT_LP64({ return false;}); 686 687 // Generic instructions 688 // Does 32bit or 64bit as needed for the platform. In some sense these 689 // belong in macro assembler but there is no need for both varieties to exist 690 691 void lea(Register dst, Address src); 692 693 void mov(Register dst, Register src); 694 695 void pusha(); 696 void popa(); 697 698 void pushf(); 699 void popf(); 700 701 void push(int32_t imm32); 702 703 void push(Register src); 704 705 void pop(Register dst); 706 707 // These are dummies to prevent surprise implicit conversions to Register 708 void push(void* v); 709 void pop(void* v); 710 711 // These do register sized moves/scans 712 void rep_mov(); 713 void rep_set(); 714 void repne_scan(); 715 #ifdef _LP64 716 void repne_scanl(); 717 #endif 718 719 // Vanilla instructions in lexical order 720 721 void adcl(Address dst, int32_t imm32); 722 void adcl(Address dst, Register src); 723 void adcl(Register dst, int32_t imm32); 724 void adcl(Register dst, Address src); 725 void adcl(Register dst, Register src); 726 727 void adcq(Register dst, int32_t imm32); 728 void adcq(Register dst, Address src); 729 void adcq(Register dst, Register src); 730 731 void addl(Address dst, int32_t imm32); 732 void addl(Address dst, Register src); 733 void addl(Register dst, int32_t imm32); 734 void addl(Register dst, Address src); 735 void addl(Register dst, Register src); 736 737 void addq(Address dst, int32_t imm32); 738 void addq(Address dst, Register src); 739 void addq(Register dst, int32_t imm32); 740 void addq(Register dst, Address src); 741 void addq(Register dst, Register src); 742 743 void addr_nop_4(); 744 void addr_nop_5(); 745 void addr_nop_7(); 746 void addr_nop_8(); 747 748 // Add Scalar Double-Precision Floating-Point Values 749 void addsd(XMMRegister dst, Address src); 750 void addsd(XMMRegister dst, XMMRegister src); 751 752 // Add Scalar Single-Precision Floating-Point Values 753 void addss(XMMRegister dst, Address src); 754 void addss(XMMRegister dst, XMMRegister src); 755 756 void andl(Register dst, int32_t imm32); 757 void andl(Register dst, Address src); 758 void andl(Register dst, Register src); 759 760 void andq(Register dst, int32_t imm32); 761 void andq(Register dst, Address src); 762 void andq(Register dst, Register src); 763 764 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values 765 void andpd(XMMRegister dst, Address src); 766 void andpd(XMMRegister dst, XMMRegister src); 767 768 void bsfl(Register dst, Register src); 769 void bsrl(Register dst, Register src); 770 771 #ifdef _LP64 772 void bsfq(Register dst, Register src); 773 void bsrq(Register dst, Register src); 774 #endif 775 776 void bswapl(Register reg); 777 778 void bswapq(Register reg); 779 780 void call(Label& L, relocInfo::relocType rtype); 781 void call(Register reg); // push pc; pc <- reg 782 void call(Address adr); // push pc; pc <- adr 783 784 void cdql(); 785 786 void cdqq(); 787 788 void cld() { emit_byte(0xfc); } 789 790 void clflush(Address adr); 791 792 void cmovl(Condition cc, Register dst, Register src); 793 void cmovl(Condition cc, Register dst, Address src); 794 795 void cmovq(Condition cc, Register dst, Register src); 796 void cmovq(Condition cc, Register dst, Address src); 797 798 799 void cmpb(Address dst, int imm8); 800 801 void cmpl(Address dst, int32_t imm32); 802 803 void cmpl(Register dst, int32_t imm32); 804 void cmpl(Register dst, Register src); 805 void cmpl(Register dst, Address src); 806 807 void cmpq(Address dst, int32_t imm32); 808 void cmpq(Address dst, Register src); 809 810 void cmpq(Register dst, int32_t imm32); 811 void cmpq(Register dst, Register src); 812 void cmpq(Register dst, Address src); 813 814 // these are dummies used to catch attempting to convert NULL to Register 815 void cmpl(Register dst, void* junk); // dummy 816 void cmpq(Register dst, void* junk); // dummy 817 818 void cmpw(Address dst, int imm16); 819 820 void cmpxchg8 (Address adr); 821 822 void cmpxchgl(Register reg, Address adr); 823 824 void cmpxchgq(Register reg, Address adr); 825 826 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 827 void comisd(XMMRegister dst, Address src); 828 829 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 830 void comiss(XMMRegister dst, Address src); 831 832 // Identify processor type and features 833 void cpuid() { 834 emit_byte(0x0F); 835 emit_byte(0xA2); 836 } 837 838 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 839 void cvtsd2ss(XMMRegister dst, XMMRegister src); 840 841 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 842 void cvtsi2sdl(XMMRegister dst, Register src); 843 void cvtsi2sdq(XMMRegister dst, Register src); 844 845 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 846 void cvtsi2ssl(XMMRegister dst, Register src); 847 void cvtsi2ssq(XMMRegister dst, Register src); 848 849 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 850 void cvtdq2pd(XMMRegister dst, XMMRegister src); 851 852 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 853 void cvtdq2ps(XMMRegister dst, XMMRegister src); 854 855 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 856 void cvtss2sd(XMMRegister dst, XMMRegister src); 857 858 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 859 void cvttsd2sil(Register dst, Address src); 860 void cvttsd2sil(Register dst, XMMRegister src); 861 void cvttsd2siq(Register dst, XMMRegister src); 862 863 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 864 void cvttss2sil(Register dst, XMMRegister src); 865 void cvttss2siq(Register dst, XMMRegister src); 866 867 // Divide Scalar Double-Precision Floating-Point Values 868 void divsd(XMMRegister dst, Address src); 869 void divsd(XMMRegister dst, XMMRegister src); 870 871 // Divide Scalar Single-Precision Floating-Point Values 872 void divss(XMMRegister dst, Address src); 873 void divss(XMMRegister dst, XMMRegister src); 874 875 void emms(); 876 877 void fabs(); 878 879 void fadd(int i); 880 881 void fadd_d(Address src); 882 void fadd_s(Address src); 883 884 // "Alternate" versions of x87 instructions place result down in FPU 885 // stack instead of on TOS 886 887 void fadda(int i); // "alternate" fadd 888 void faddp(int i = 1); 889 890 void fchs(); 891 892 void fcom(int i); 893 894 void fcomp(int i = 1); 895 void fcomp_d(Address src); 896 void fcomp_s(Address src); 897 898 void fcompp(); 899 900 void fcos(); 901 902 void fdecstp(); 903 904 void fdiv(int i); 905 void fdiv_d(Address src); 906 void fdivr_s(Address src); 907 void fdiva(int i); // "alternate" fdiv 908 void fdivp(int i = 1); 909 910 void fdivr(int i); 911 void fdivr_d(Address src); 912 void fdiv_s(Address src); 913 914 void fdivra(int i); // "alternate" reversed fdiv 915 916 void fdivrp(int i = 1); 917 918 void ffree(int i = 0); 919 920 void fild_d(Address adr); 921 void fild_s(Address adr); 922 923 void fincstp(); 924 925 void finit(); 926 927 void fist_s (Address adr); 928 void fistp_d(Address adr); 929 void fistp_s(Address adr); 930 931 void fld1(); 932 933 void fld_d(Address adr); 934 void fld_s(Address adr); 935 void fld_s(int index); 936 void fld_x(Address adr); // extended-precision (80-bit) format 937 938 void fldcw(Address src); 939 940 void fldenv(Address src); 941 942 void fldlg2(); 943 944 void fldln2(); 945 946 void fldz(); 947 948 void flog(); 949 void flog10(); 950 951 void fmul(int i); 952 953 void fmul_d(Address src); 954 void fmul_s(Address src); 955 956 void fmula(int i); // "alternate" fmul 957 958 void fmulp(int i = 1); 959 960 void fnsave(Address dst); 961 962 void fnstcw(Address src); 963 964 void fnstsw_ax(); 965 966 void fprem(); 967 void fprem1(); 968 969 void frstor(Address src); 970 971 void fsin(); 972 973 void fsqrt(); 974 975 void fst_d(Address adr); 976 void fst_s(Address adr); 977 978 void fstp_d(Address adr); 979 void fstp_d(int index); 980 void fstp_s(Address adr); 981 void fstp_x(Address adr); // extended-precision (80-bit) format 982 983 void fsub(int i); 984 void fsub_d(Address src); 985 void fsub_s(Address src); 986 987 void fsuba(int i); // "alternate" fsub 988 989 void fsubp(int i = 1); 990 991 void fsubr(int i); 992 void fsubr_d(Address src); 993 void fsubr_s(Address src); 994 995 void fsubra(int i); // "alternate" reversed fsub 996 997 void fsubrp(int i = 1); 998 999 void ftan(); 1000 1001 void ftst(); 1002 1003 void fucomi(int i = 1); 1004 void fucomip(int i = 1); 1005 1006 void fwait(); 1007 1008 void fxch(int i = 1); 1009 1010 void fxrstor(Address src); 1011 1012 void fxsave(Address dst); 1013 1014 void fyl2x(); 1015 1016 void hlt(); 1017 1018 void idivl(Register src); 1019 void divl(Register src); // Unsigned division 1020 1021 void idivq(Register src); 1022 1023 void imull(Register dst, Register src); 1024 void imull(Register dst, Register src, int value); 1025 1026 void imulq(Register dst, Register src); 1027 void imulq(Register dst, Register src, int value); 1028 1029 1030 // jcc is the generic conditional branch generator to run- 1031 // time routines, jcc is used for branches to labels. jcc 1032 // takes a branch opcode (cc) and a label (L) and generates 1033 // either a backward branch or a forward branch and links it 1034 // to the label fixup chain. Usage: 1035 // 1036 // Label L; // unbound label 1037 // jcc(cc, L); // forward branch to unbound label 1038 // bind(L); // bind label to the current pc 1039 // jcc(cc, L); // backward branch to bound label 1040 // bind(L); // illegal: a label may be bound only once 1041 // 1042 // Note: The same Label can be used for forward and backward branches 1043 // but it may be bound only once. 1044 1045 void jcc(Condition cc, Label& L, 1046 relocInfo::relocType rtype = relocInfo::none); 1047 1048 // Conditional jump to a 8-bit offset to L. 1049 // WARNING: be very careful using this for forward jumps. If the label is 1050 // not bound within an 8-bit offset of this instruction, a run-time error 1051 // will occur. 1052 void jccb(Condition cc, Label& L); 1053 1054 void jmp(Address entry); // pc <- entry 1055 1056 // Label operations & relative jumps (PPUM Appendix D) 1057 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L 1058 1059 void jmp(Register entry); // pc <- entry 1060 1061 // Unconditional 8-bit offset jump to L. 1062 // WARNING: be very careful using this for forward jumps. If the label is 1063 // not bound within an 8-bit offset of this instruction, a run-time error 1064 // will occur. 1065 void jmpb(Label& L); 1066 1067 void ldmxcsr( Address src ); 1068 1069 void leal(Register dst, Address src); 1070 1071 void leaq(Register dst, Address src); 1072 1073 void lfence() { 1074 emit_byte(0x0F); 1075 emit_byte(0xAE); 1076 emit_byte(0xE8); 1077 } 1078 1079 void lock(); 1080 1081 void lzcntl(Register dst, Register src); 1082 1083 #ifdef _LP64 1084 void lzcntq(Register dst, Register src); 1085 #endif 1086 1087 enum Membar_mask_bits { 1088 StoreStore = 1 << 3, 1089 LoadStore = 1 << 2, 1090 StoreLoad = 1 << 1, 1091 LoadLoad = 1 << 0 1092 }; 1093 1094 // Serializes memory and blows flags 1095 void membar(Membar_mask_bits order_constraint) { 1096 if (os::is_MP()) { 1097 // We only have to handle StoreLoad 1098 if (order_constraint & StoreLoad) { 1099 // All usable chips support "locked" instructions which suffice 1100 // as barriers, and are much faster than the alternative of 1101 // using cpuid instruction. We use here a locked add [esp],0. 1102 // This is conveniently otherwise a no-op except for blowing 1103 // flags. 1104 // Any change to this code may need to revisit other places in 1105 // the code where this idiom is used, in particular the 1106 // orderAccess code. 1107 lock(); 1108 addl(Address(rsp, 0), 0);// Assert the lock# signal here 1109 } 1110 } 1111 } 1112 1113 void mfence(); 1114 1115 // Moves 1116 1117 void mov64(Register dst, int64_t imm64); 1118 1119 void movb(Address dst, Register src); 1120 void movb(Address dst, int imm8); 1121 void movb(Register dst, Address src); 1122 1123 void movdl(XMMRegister dst, Register src); 1124 void movdl(Register dst, XMMRegister src); 1125 void movdl(XMMRegister dst, Address src); 1126 1127 // Move Double Quadword 1128 void movdq(XMMRegister dst, Register src); 1129 void movdq(Register dst, XMMRegister src); 1130 1131 // Move Aligned Double Quadword 1132 void movdqa(Address dst, XMMRegister src); 1133 void movdqa(XMMRegister dst, Address src); 1134 void movdqa(XMMRegister dst, XMMRegister src); 1135 1136 // Move Unaligned Double Quadword 1137 void movdqu(Address dst, XMMRegister src); 1138 void movdqu(XMMRegister dst, Address src); 1139 void movdqu(XMMRegister dst, XMMRegister src); 1140 1141 void movl(Register dst, int32_t imm32); 1142 void movl(Address dst, int32_t imm32); 1143 void movl(Register dst, Register src); 1144 void movl(Register dst, Address src); 1145 void movl(Address dst, Register src); 1146 1147 // These dummies prevent using movl from converting a zero (like NULL) into Register 1148 // by giving the compiler two choices it can't resolve 1149 1150 void movl(Address dst, void* junk); 1151 void movl(Register dst, void* junk); 1152 1153 #ifdef _LP64 1154 void movq(Register dst, Register src); 1155 void movq(Register dst, Address src); 1156 void movq(Address dst, Register src); 1157 #endif 1158 1159 void movq(Address dst, MMXRegister src ); 1160 void movq(MMXRegister dst, Address src ); 1161 1162 #ifdef _LP64 1163 // These dummies prevent using movq from converting a zero (like NULL) into Register 1164 // by giving the compiler two choices it can't resolve 1165 1166 void movq(Address dst, void* dummy); 1167 void movq(Register dst, void* dummy); 1168 #endif 1169 1170 // Move Quadword 1171 void movq(Address dst, XMMRegister src); 1172 void movq(XMMRegister dst, Address src); 1173 1174 void movsbl(Register dst, Address src); 1175 void movsbl(Register dst, Register src); 1176 1177 #ifdef _LP64 1178 void movsbq(Register dst, Address src); 1179 void movsbq(Register dst, Register src); 1180 1181 // Move signed 32bit immediate to 64bit extending sign 1182 void movslq(Address dst, int32_t imm64); 1183 void movslq(Register dst, int32_t imm64); 1184 1185 void movslq(Register dst, Address src); 1186 void movslq(Register dst, Register src); 1187 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1188 #endif 1189 1190 void movswl(Register dst, Address src); 1191 void movswl(Register dst, Register src); 1192 1193 #ifdef _LP64 1194 void movswq(Register dst, Address src); 1195 void movswq(Register dst, Register src); 1196 #endif 1197 1198 void movw(Address dst, int imm16); 1199 void movw(Register dst, Address src); 1200 void movw(Address dst, Register src); 1201 1202 void movzbl(Register dst, Address src); 1203 void movzbl(Register dst, Register src); 1204 1205 #ifdef _LP64 1206 void movzbq(Register dst, Address src); 1207 void movzbq(Register dst, Register src); 1208 #endif 1209 1210 void movzwl(Register dst, Address src); 1211 void movzwl(Register dst, Register src); 1212 1213 #ifdef _LP64 1214 void movzwq(Register dst, Address src); 1215 void movzwq(Register dst, Register src); 1216 #endif 1217 1218 void mull(Address src); 1219 void mull(Register src); 1220 1221 // Multiply Scalar Double-Precision Floating-Point Values 1222 void mulsd(XMMRegister dst, Address src); 1223 void mulsd(XMMRegister dst, XMMRegister src); 1224 1225 // Multiply Scalar Single-Precision Floating-Point Values 1226 void mulss(XMMRegister dst, Address src); 1227 void mulss(XMMRegister dst, XMMRegister src); 1228 1229 void negl(Register dst); 1230 1231 #ifdef _LP64 1232 void negq(Register dst); 1233 #endif 1234 1235 void nop(int i = 1); 1236 1237 void notl(Register dst); 1238 1239 #ifdef _LP64 1240 void notq(Register dst); 1241 #endif 1242 1243 void orl(Address dst, int32_t imm32); 1244 void orl(Register dst, int32_t imm32); 1245 void orl(Register dst, Address src); 1246 void orl(Register dst, Register src); 1247 1248 void orq(Address dst, int32_t imm32); 1249 void orq(Register dst, int32_t imm32); 1250 void orq(Register dst, Address src); 1251 void orq(Register dst, Register src); 1252 1253 // SSE4.2 string instructions 1254 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); 1255 void pcmpestri(XMMRegister xmm1, Address src, int imm8); 1256 1257 #ifndef _LP64 // no 32bit push/pop on amd64 1258 void popl(Address dst); 1259 #endif 1260 1261 #ifdef _LP64 1262 void popq(Address dst); 1263 #endif 1264 1265 void popcntl(Register dst, Address src); 1266 void popcntl(Register dst, Register src); 1267 1268 #ifdef _LP64 1269 void popcntq(Register dst, Address src); 1270 void popcntq(Register dst, Register src); 1271 #endif 1272 1273 // Prefetches (SSE, SSE2, 3DNOW only) 1274 1275 void prefetchnta(Address src); 1276 void prefetchr(Address src); 1277 void prefetcht0(Address src); 1278 void prefetcht1(Address src); 1279 void prefetcht2(Address src); 1280 void prefetchw(Address src); 1281 1282 // POR - Bitwise logical OR 1283 void por(XMMRegister dst, XMMRegister src); 1284 1285 // Shuffle Packed Doublewords 1286 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1287 void pshufd(XMMRegister dst, Address src, int mode); 1288 1289 // Shuffle Packed Low Words 1290 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1291 void pshuflw(XMMRegister dst, Address src, int mode); 1292 1293 // Shift Right by bits Logical Quadword Immediate 1294 void psrlq(XMMRegister dst, int shift); 1295 1296 // Shift Right by bytes Logical DoubleQuadword Immediate 1297 void psrldq(XMMRegister dst, int shift); 1298 1299 // Logical Compare Double Quadword 1300 void ptest(XMMRegister dst, XMMRegister src); 1301 void ptest(XMMRegister dst, Address src); 1302 1303 // Interleave Low Bytes 1304 void punpcklbw(XMMRegister dst, XMMRegister src); 1305 1306 #ifndef _LP64 // no 32bit push/pop on amd64 1307 void pushl(Address src); 1308 #endif 1309 1310 void pushq(Address src); 1311 1312 // Xor Packed Byte Integer Values 1313 void pxor(XMMRegister dst, Address src); 1314 void pxor(XMMRegister dst, XMMRegister src); 1315 1316 void rcll(Register dst, int imm8); 1317 1318 void rclq(Register dst, int imm8); 1319 1320 void ret(int imm16); 1321 1322 void sahf(); 1323 1324 void sarl(Register dst, int imm8); 1325 void sarl(Register dst); 1326 1327 void sarq(Register dst, int imm8); 1328 void sarq(Register dst); 1329 1330 void sbbl(Address dst, int32_t imm32); 1331 void sbbl(Register dst, int32_t imm32); 1332 void sbbl(Register dst, Address src); 1333 void sbbl(Register dst, Register src); 1334 1335 void sbbq(Address dst, int32_t imm32); 1336 void sbbq(Register dst, int32_t imm32); 1337 void sbbq(Register dst, Address src); 1338 void sbbq(Register dst, Register src); 1339 1340 void setb(Condition cc, Register dst); 1341 1342 void shldl(Register dst, Register src); 1343 1344 void shll(Register dst, int imm8); 1345 void shll(Register dst); 1346 1347 void shlq(Register dst, int imm8); 1348 void shlq(Register dst); 1349 1350 void shrdl(Register dst, Register src); 1351 1352 void shrl(Register dst, int imm8); 1353 void shrl(Register dst); 1354 1355 void shrq(Register dst, int imm8); 1356 void shrq(Register dst); 1357 1358 void smovl(); // QQQ generic? 1359 1360 // Compute Square Root of Scalar Double-Precision Floating-Point Value 1361 void sqrtsd(XMMRegister dst, Address src); 1362 void sqrtsd(XMMRegister dst, XMMRegister src); 1363 1364 // Compute Square Root of Scalar Single-Precision Floating-Point Value 1365 void sqrtss(XMMRegister dst, Address src); 1366 void sqrtss(XMMRegister dst, XMMRegister src); 1367 1368 void std() { emit_byte(0xfd); } 1369 1370 void stmxcsr( Address dst ); 1371 1372 void subl(Address dst, int32_t imm32); 1373 void subl(Address dst, Register src); 1374 void subl(Register dst, int32_t imm32); 1375 void subl(Register dst, Address src); 1376 void subl(Register dst, Register src); 1377 1378 void subq(Address dst, int32_t imm32); 1379 void subq(Address dst, Register src); 1380 void subq(Register dst, int32_t imm32); 1381 void subq(Register dst, Address src); 1382 void subq(Register dst, Register src); 1383 1384 1385 // Subtract Scalar Double-Precision Floating-Point Values 1386 void subsd(XMMRegister dst, Address src); 1387 void subsd(XMMRegister dst, XMMRegister src); 1388 1389 // Subtract Scalar Single-Precision Floating-Point Values 1390 void subss(XMMRegister dst, Address src); 1391 void subss(XMMRegister dst, XMMRegister src); 1392 1393 void testb(Register dst, int imm8); 1394 1395 void testl(Register dst, int32_t imm32); 1396 void testl(Register dst, Register src); 1397 void testl(Register dst, Address src); 1398 1399 void testq(Register dst, int32_t imm32); 1400 void testq(Register dst, Register src); 1401 1402 1403 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1404 void ucomisd(XMMRegister dst, Address src); 1405 void ucomisd(XMMRegister dst, XMMRegister src); 1406 1407 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1408 void ucomiss(XMMRegister dst, Address src); 1409 void ucomiss(XMMRegister dst, XMMRegister src); 1410 1411 void xaddl(Address dst, Register src); 1412 1413 void xaddq(Address dst, Register src); 1414 1415 void xchgl(Register reg, Address adr); 1416 void xchgl(Register dst, Register src); 1417 1418 void xchgq(Register reg, Address adr); 1419 void xchgq(Register dst, Register src); 1420 1421 void xorl(Register dst, int32_t imm32); 1422 void xorl(Register dst, Address src); 1423 void xorl(Register dst, Register src); 1424 1425 void xorq(Register dst, Address src); 1426 void xorq(Register dst, Register src); 1427 1428 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 1429 void xorpd(XMMRegister dst, Address src); 1430 void xorpd(XMMRegister dst, XMMRegister src); 1431 1432 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 1433 void xorps(XMMRegister dst, Address src); 1434 void xorps(XMMRegister dst, XMMRegister src); 1435 1436 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 1437 }; 1438 1439 1440 // MacroAssembler extends Assembler by frequently used macros. 1441 // 1442 // Instructions for which a 'better' code sequence exists depending 1443 // on arguments should also go in here. 1444 1445 class MacroAssembler: public Assembler { 1446 friend class LIR_Assembler; 1447 friend class Runtime1; // as_Address() 1448 protected: 1449 1450 Address as_Address(AddressLiteral adr); 1451 Address as_Address(ArrayAddress adr); 1452 1453 // Support for VM calls 1454 // 1455 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 1456 // may customize this version by overriding it for its purposes (e.g., to save/restore 1457 // additional registers when doing a VM call). 1458 #ifdef CC_INTERP 1459 // c++ interpreter never wants to use interp_masm version of call_VM 1460 #define VIRTUAL 1461 #else 1462 #define VIRTUAL virtual 1463 #endif 1464 1465 VIRTUAL void call_VM_leaf_base( 1466 address entry_point, // the entry point 1467 int number_of_arguments // the number of arguments to pop after the call 1468 ); 1469 1470 // This is the base routine called by the different versions of call_VM. The interpreter 1471 // may customize this version by overriding it for its purposes (e.g., to save/restore 1472 // additional registers when doing a VM call). 1473 // 1474 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 1475 // returns the register which contains the thread upon return. If a thread register has been 1476 // specified, the return value will correspond to that register. If no last_java_sp is specified 1477 // (noreg) than rsp will be used instead. 1478 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 1479 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 1480 Register java_thread, // the thread if computed before ; use noreg otherwise 1481 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 1482 address entry_point, // the entry point 1483 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 1484 bool check_exceptions // whether to check for pending exceptions after return 1485 ); 1486 1487 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 1488 // The implementation is only non-empty for the InterpreterMacroAssembler, 1489 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 1490 virtual void check_and_handle_popframe(Register java_thread); 1491 virtual void check_and_handle_earlyret(Register java_thread); 1492 1493 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 1494 1495 // helpers for FPU flag access 1496 // tmp is a temporary register, if none is available use noreg 1497 void save_rax (Register tmp); 1498 void restore_rax(Register tmp); 1499 1500 public: 1501 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 1502 1503 // Support for NULL-checks 1504 // 1505 // Generates code that causes a NULL OS exception if the content of reg is NULL. 1506 // If the accessed location is M[reg + offset] and the offset is known, provide the 1507 // offset. No explicit code generation is needed if the offset is within a certain 1508 // range (0 <= offset <= page_size). 1509 1510 void null_check(Register reg, int offset = -1); 1511 static bool needs_explicit_null_check(intptr_t offset); 1512 1513 // Required platform-specific helpers for Label::patch_instructions. 1514 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 1515 void pd_patch_instruction(address branch, address target); 1516 #ifndef PRODUCT 1517 static void pd_print_patched_instruction(address branch); 1518 #endif 1519 1520 // The following 4 methods return the offset of the appropriate move instruction 1521 1522 // Support for fast byte/short loading with zero extension (depending on particular CPU) 1523 int load_unsigned_byte(Register dst, Address src); 1524 int load_unsigned_short(Register dst, Address src); 1525 1526 // Support for fast byte/short loading with sign extension (depending on particular CPU) 1527 int load_signed_byte(Register dst, Address src); 1528 int load_signed_short(Register dst, Address src); 1529 1530 // Support for sign-extension (hi:lo = extend_sign(lo)) 1531 void extend_sign(Register hi, Register lo); 1532 1533 // Load and store values by size and signed-ness 1534 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 1535 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 1536 1537 // Support for inc/dec with optimal instruction selection depending on value 1538 1539 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 1540 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 1541 1542 void decrementl(Address dst, int value = 1); 1543 void decrementl(Register reg, int value = 1); 1544 1545 void decrementq(Register reg, int value = 1); 1546 void decrementq(Address dst, int value = 1); 1547 1548 void incrementl(Address dst, int value = 1); 1549 void incrementl(Register reg, int value = 1); 1550 1551 void incrementq(Register reg, int value = 1); 1552 void incrementq(Address dst, int value = 1); 1553 1554 1555 // Support optimal SSE move instructions. 1556 void movflt(XMMRegister dst, XMMRegister src) { 1557 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 1558 else { movss (dst, src); return; } 1559 } 1560 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 1561 void movflt(XMMRegister dst, AddressLiteral src); 1562 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 1563 1564 void movdbl(XMMRegister dst, XMMRegister src) { 1565 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 1566 else { movsd (dst, src); return; } 1567 } 1568 1569 void movdbl(XMMRegister dst, AddressLiteral src); 1570 1571 void movdbl(XMMRegister dst, Address src) { 1572 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 1573 else { movlpd(dst, src); return; } 1574 } 1575 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 1576 1577 void incrementl(AddressLiteral dst); 1578 void incrementl(ArrayAddress dst); 1579 1580 // Alignment 1581 void align(int modulus); 1582 1583 // Misc 1584 void fat_nop(); // 5 byte nop 1585 1586 // Stack frame creation/removal 1587 void enter(); 1588 void leave(); 1589 1590 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 1591 // The pointer will be loaded into the thread register. 1592 void get_thread(Register thread); 1593 1594 1595 // Support for VM calls 1596 // 1597 // It is imperative that all calls into the VM are handled via the call_VM macros. 1598 // They make sure that the stack linkage is setup correctly. call_VM's correspond 1599 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 1600 1601 1602 void call_VM(Register oop_result, 1603 address entry_point, 1604 bool check_exceptions = true); 1605 void call_VM(Register oop_result, 1606 address entry_point, 1607 Register arg_1, 1608 bool check_exceptions = true); 1609 void call_VM(Register oop_result, 1610 address entry_point, 1611 Register arg_1, Register arg_2, 1612 bool check_exceptions = true); 1613 void call_VM(Register oop_result, 1614 address entry_point, 1615 Register arg_1, Register arg_2, Register arg_3, 1616 bool check_exceptions = true); 1617 1618 // Overloadings with last_Java_sp 1619 void call_VM(Register oop_result, 1620 Register last_java_sp, 1621 address entry_point, 1622 int number_of_arguments = 0, 1623 bool check_exceptions = true); 1624 void call_VM(Register oop_result, 1625 Register last_java_sp, 1626 address entry_point, 1627 Register arg_1, bool 1628 check_exceptions = true); 1629 void call_VM(Register oop_result, 1630 Register last_java_sp, 1631 address entry_point, 1632 Register arg_1, Register arg_2, 1633 bool check_exceptions = true); 1634 void call_VM(Register oop_result, 1635 Register last_java_sp, 1636 address entry_point, 1637 Register arg_1, Register arg_2, Register arg_3, 1638 bool check_exceptions = true); 1639 1640 void call_VM_leaf(address entry_point, 1641 int number_of_arguments = 0); 1642 void call_VM_leaf(address entry_point, 1643 Register arg_1); 1644 void call_VM_leaf(address entry_point, 1645 Register arg_1, Register arg_2); 1646 void call_VM_leaf(address entry_point, 1647 Register arg_1, Register arg_2, Register arg_3); 1648 1649 // last Java Frame (fills frame anchor) 1650 void set_last_Java_frame(Register thread, 1651 Register last_java_sp, 1652 Register last_java_fp, 1653 address last_java_pc); 1654 1655 // thread in the default location (r15_thread on 64bit) 1656 void set_last_Java_frame(Register last_java_sp, 1657 Register last_java_fp, 1658 address last_java_pc); 1659 1660 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); 1661 1662 // thread in the default location (r15_thread on 64bit) 1663 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 1664 1665 // Stores 1666 void store_check(Register obj); // store check for obj - register is destroyed afterwards 1667 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 1668 1669 void g1_write_barrier_pre(Register obj, 1670 #ifndef _LP64 1671 Register thread, 1672 #endif 1673 Register tmp, 1674 Register tmp2, 1675 bool tosca_live); 1676 void g1_write_barrier_post(Register store_addr, 1677 Register new_val, 1678 #ifndef _LP64 1679 Register thread, 1680 #endif 1681 Register tmp, 1682 Register tmp2); 1683 1684 1685 // split store_check(Register obj) to enhance instruction interleaving 1686 void store_check_part_1(Register obj); 1687 void store_check_part_2(Register obj); 1688 1689 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 1690 void c2bool(Register x); 1691 1692 // C++ bool manipulation 1693 1694 void movbool(Register dst, Address src); 1695 void movbool(Address dst, bool boolconst); 1696 void movbool(Address dst, Register src); 1697 void testbool(Register dst); 1698 1699 // oop manipulations 1700 void load_klass(Register dst, Register src); 1701 void store_klass(Register dst, Register src); 1702 1703 void load_heap_oop(Register dst, Address src); 1704 void store_heap_oop(Address dst, Register src); 1705 1706 // Used for storing NULL. All other oop constants should be 1707 // stored using routines that take a jobject. 1708 void store_heap_oop_null(Address dst); 1709 1710 void load_prototype_header(Register dst, Register src); 1711 1712 #ifdef _LP64 1713 void store_klass_gap(Register dst, Register src); 1714 1715 // This dummy is to prevent a call to store_heap_oop from 1716 // converting a zero (like NULL) into a Register by giving 1717 // the compiler two choices it can't resolve 1718 1719 void store_heap_oop(Address dst, void* dummy); 1720 1721 void encode_heap_oop(Register r); 1722 void decode_heap_oop(Register r); 1723 void encode_heap_oop_not_null(Register r); 1724 void decode_heap_oop_not_null(Register r); 1725 void encode_heap_oop_not_null(Register dst, Register src); 1726 void decode_heap_oop_not_null(Register dst, Register src); 1727 1728 void set_narrow_oop(Register dst, jobject obj); 1729 void set_narrow_oop(Address dst, jobject obj); 1730 void cmp_narrow_oop(Register dst, jobject obj); 1731 void cmp_narrow_oop(Address dst, jobject obj); 1732 1733 // if heap base register is used - reinit it with the correct value 1734 void reinit_heapbase(); 1735 1736 DEBUG_ONLY(void verify_heapbase(const char* msg);) 1737 1738 #endif // _LP64 1739 1740 // Int division/remainder for Java 1741 // (as idivl, but checks for special case as described in JVM spec.) 1742 // returns idivl instruction offset for implicit exception handling 1743 int corrected_idivl(Register reg); 1744 1745 // Long division/remainder for Java 1746 // (as idivq, but checks for special case as described in JVM spec.) 1747 // returns idivq instruction offset for implicit exception handling 1748 int corrected_idivq(Register reg); 1749 1750 void int3(); 1751 1752 // Long operation macros for a 32bit cpu 1753 // Long negation for Java 1754 void lneg(Register hi, Register lo); 1755 1756 // Long multiplication for Java 1757 // (destroys contents of eax, ebx, ecx and edx) 1758 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 1759 1760 // Long shifts for Java 1761 // (semantics as described in JVM spec.) 1762 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 1763 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 1764 1765 // Long compare for Java 1766 // (semantics as described in JVM spec.) 1767 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 1768 1769 1770 // misc 1771 1772 // Sign extension 1773 void sign_extend_short(Register reg); 1774 void sign_extend_byte(Register reg); 1775 1776 // Division by power of 2, rounding towards 0 1777 void division_with_shift(Register reg, int shift_value); 1778 1779 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 1780 // 1781 // CF (corresponds to C0) if x < y 1782 // PF (corresponds to C2) if unordered 1783 // ZF (corresponds to C3) if x = y 1784 // 1785 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 1786 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 1787 void fcmp(Register tmp); 1788 // Variant of the above which allows y to be further down the stack 1789 // and which only pops x and y if specified. If pop_right is 1790 // specified then pop_left must also be specified. 1791 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 1792 1793 // Floating-point comparison for Java 1794 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 1795 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 1796 // (semantics as described in JVM spec.) 1797 void fcmp2int(Register dst, bool unordered_is_less); 1798 // Variant of the above which allows y to be further down the stack 1799 // and which only pops x and y if specified. If pop_right is 1800 // specified then pop_left must also be specified. 1801 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 1802 1803 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 1804 // tmp is a temporary register, if none is available use noreg 1805 void fremr(Register tmp); 1806 1807 1808 // same as fcmp2int, but using SSE2 1809 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 1810 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 1811 1812 // Inlined sin/cos generator for Java; must not use CPU instruction 1813 // directly on Intel as it does not have high enough precision 1814 // outside of the range [-pi/4, pi/4]. Extra argument indicate the 1815 // number of FPU stack slots in use; all but the topmost will 1816 // require saving if a slow case is necessary. Assumes argument is 1817 // on FP TOS; result is on FP TOS. No cpu registers are changed by 1818 // this code. 1819 void trigfunc(char trig, int num_fpu_regs_in_use = 1); 1820 1821 // branch to L if FPU flag C2 is set/not set 1822 // tmp is a temporary register, if none is available use noreg 1823 void jC2 (Register tmp, Label& L); 1824 void jnC2(Register tmp, Label& L); 1825 1826 // Pop ST (ffree & fincstp combined) 1827 void fpop(); 1828 1829 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 1830 void push_fTOS(); 1831 1832 // pops double TOS element from CPU stack and pushes on FPU stack 1833 void pop_fTOS(); 1834 1835 void empty_FPU_stack(); 1836 1837 void push_IU_state(); 1838 void pop_IU_state(); 1839 1840 void push_FPU_state(); 1841 void pop_FPU_state(); 1842 1843 void push_CPU_state(); 1844 void pop_CPU_state(); 1845 1846 // Round up to a power of two 1847 void round_to(Register reg, int modulus); 1848 1849 // Callee saved registers handling 1850 void push_callee_saved_registers(); 1851 void pop_callee_saved_registers(); 1852 1853 // allocation 1854 void eden_allocate( 1855 Register obj, // result: pointer to object after successful allocation 1856 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1857 int con_size_in_bytes, // object size in bytes if known at compile time 1858 Register t1, // temp register 1859 Label& slow_case // continuation point if fast allocation fails 1860 ); 1861 void tlab_allocate( 1862 Register obj, // result: pointer to object after successful allocation 1863 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1864 int con_size_in_bytes, // object size in bytes if known at compile time 1865 Register t1, // temp register 1866 Register t2, // temp register 1867 Label& slow_case // continuation point if fast allocation fails 1868 ); 1869 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 1870 void incr_allocated_bytes(Register thread, 1871 Register var_size_in_bytes, int con_size_in_bytes, 1872 Register t1 = noreg); 1873 1874 // interface method calling 1875 void lookup_interface_method(Register recv_klass, 1876 Register intf_klass, 1877 RegisterOrConstant itable_index, 1878 Register method_result, 1879 Register scan_temp, 1880 Label& no_such_interface); 1881 1882 // Test sub_klass against super_klass, with fast and slow paths. 1883 1884 // The fast path produces a tri-state answer: yes / no / maybe-slow. 1885 // One of the three labels can be NULL, meaning take the fall-through. 1886 // If super_check_offset is -1, the value is loaded up from super_klass. 1887 // No registers are killed, except temp_reg. 1888 void check_klass_subtype_fast_path(Register sub_klass, 1889 Register super_klass, 1890 Register temp_reg, 1891 Label* L_success, 1892 Label* L_failure, 1893 Label* L_slow_path, 1894 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 1895 1896 // The rest of the type check; must be wired to a corresponding fast path. 1897 // It does not repeat the fast path logic, so don't use it standalone. 1898 // The temp_reg and temp2_reg can be noreg, if no temps are available. 1899 // Updates the sub's secondary super cache as necessary. 1900 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 1901 void check_klass_subtype_slow_path(Register sub_klass, 1902 Register super_klass, 1903 Register temp_reg, 1904 Register temp2_reg, 1905 Label* L_success, 1906 Label* L_failure, 1907 bool set_cond_codes = false); 1908 1909 // Simplified, combined version, good for typical uses. 1910 // Falls through on failure. 1911 void check_klass_subtype(Register sub_klass, 1912 Register super_klass, 1913 Register temp_reg, 1914 Label& L_success); 1915 1916 // method handles (JSR 292) 1917 void check_method_handle_type(Register mtype_reg, Register mh_reg, 1918 Register temp_reg, 1919 Label& wrong_method_type); 1920 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, 1921 Register temp_reg); 1922 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); 1923 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 1924 1925 1926 //---- 1927 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 1928 1929 // Debugging 1930 1931 // only if +VerifyOops 1932 void verify_oop(Register reg, const char* s = "broken oop"); 1933 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 1934 1935 // only if +VerifyFPU 1936 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 1937 1938 // prints msg, dumps registers and stops execution 1939 void stop(const char* msg); 1940 1941 // prints msg and continues 1942 void warn(const char* msg); 1943 1944 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 1945 static void debug64(char* msg, int64_t pc, int64_t regs[]); 1946 1947 void os_breakpoint(); 1948 1949 void untested() { stop("untested"); } 1950 1951 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 1952 1953 void should_not_reach_here() { stop("should not reach here"); } 1954 1955 void print_CPU_state(); 1956 1957 // Stack overflow checking 1958 void bang_stack_with_offset(int offset) { 1959 // stack grows down, caller passes positive offset 1960 assert(offset > 0, "must bang with negative offset"); 1961 movl(Address(rsp, (-offset)), rax); 1962 } 1963 1964 // Writes to stack successive pages until offset reached to check for 1965 // stack overflow + shadow pages. Also, clobbers tmp 1966 void bang_stack_size(Register size, Register tmp); 1967 1968 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 1969 Register tmp, 1970 int offset); 1971 1972 // Support for serializing memory accesses between threads 1973 void serialize_memory(Register thread, Register tmp); 1974 1975 void verify_tlab(); 1976 1977 // Biased locking support 1978 // lock_reg and obj_reg must be loaded up with the appropriate values. 1979 // swap_reg must be rax, and is killed. 1980 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 1981 // be killed; if not supplied, push/pop will be used internally to 1982 // allocate a temporary (inefficient, avoid if possible). 1983 // Optional slow case is for implementations (interpreter and C1) which branch to 1984 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 1985 // Returns offset of first potentially-faulting instruction for null 1986 // check info (currently consumed only by C1). If 1987 // swap_reg_contains_mark is true then returns -1 as it is assumed 1988 // the calling code has already passed any potential faults. 1989 int biased_locking_enter(Register lock_reg, Register obj_reg, 1990 Register swap_reg, Register tmp_reg, 1991 bool swap_reg_contains_mark, 1992 Label& done, Label* slow_case = NULL, 1993 BiasedLockingCounters* counters = NULL); 1994 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 1995 1996 1997 Condition negate_condition(Condition cond); 1998 1999 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 2000 // operands. In general the names are modified to avoid hiding the instruction in Assembler 2001 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 2002 // here in MacroAssembler. The major exception to this rule is call 2003 2004 // Arithmetics 2005 2006 2007 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 2008 void addptr(Address dst, Register src); 2009 2010 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 2011 void addptr(Register dst, int32_t src); 2012 void addptr(Register dst, Register src); 2013 2014 void andptr(Register dst, int32_t src); 2015 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 2016 2017 void cmp8(AddressLiteral src1, int imm); 2018 2019 // renamed to drag out the casting of address to int32_t/intptr_t 2020 void cmp32(Register src1, int32_t imm); 2021 2022 void cmp32(AddressLiteral src1, int32_t imm); 2023 // compare reg - mem, or reg - &mem 2024 void cmp32(Register src1, AddressLiteral src2); 2025 2026 void cmp32(Register src1, Address src2); 2027 2028 #ifndef _LP64 2029 void cmpoop(Address dst, jobject obj); 2030 void cmpoop(Register dst, jobject obj); 2031 #endif // _LP64 2032 2033 // NOTE src2 must be the lval. This is NOT an mem-mem compare 2034 void cmpptr(Address src1, AddressLiteral src2); 2035 2036 void cmpptr(Register src1, AddressLiteral src2); 2037 2038 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2039 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2040 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2041 2042 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2043 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2044 2045 // cmp64 to avoild hiding cmpq 2046 void cmp64(Register src1, AddressLiteral src); 2047 2048 void cmpxchgptr(Register reg, Address adr); 2049 2050 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 2051 2052 2053 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 2054 2055 2056 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 2057 2058 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 2059 2060 void shlptr(Register dst, int32_t shift); 2061 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 2062 2063 void shrptr(Register dst, int32_t shift); 2064 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 2065 2066 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 2067 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 2068 2069 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 2070 2071 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 2072 void subptr(Register dst, int32_t src); 2073 void subptr(Register dst, Register src); 2074 2075 2076 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 2077 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 2078 2079 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 2080 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 2081 2082 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 2083 2084 2085 2086 // Helper functions for statistics gathering. 2087 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 2088 void cond_inc32(Condition cond, AddressLiteral counter_addr); 2089 // Unconditional atomic increment. 2090 void atomic_incl(AddressLiteral counter_addr); 2091 2092 void lea(Register dst, AddressLiteral adr); 2093 void lea(Address dst, AddressLiteral adr); 2094 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 2095 2096 void leal32(Register dst, Address src) { leal(dst, src); } 2097 2098 // Import other testl() methods from the parent class or else 2099 // they will be hidden by the following overriding declaration. 2100 using Assembler::testl; 2101 void testl(Register dst, AddressLiteral src); 2102 2103 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 2104 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 2105 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 2106 2107 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 2108 void testptr(Register src1, Register src2); 2109 2110 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 2111 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 2112 2113 // Calls 2114 2115 void call(Label& L, relocInfo::relocType rtype); 2116 void call(Register entry); 2117 2118 // NOTE: this call tranfers to the effective address of entry NOT 2119 // the address contained by entry. This is because this is more natural 2120 // for jumps/calls. 2121 void call(AddressLiteral entry); 2122 2123 // Jumps 2124 2125 // NOTE: these jumps tranfer to the effective address of dst NOT 2126 // the address contained by dst. This is because this is more natural 2127 // for jumps/calls. 2128 void jump(AddressLiteral dst); 2129 void jump_cc(Condition cc, AddressLiteral dst); 2130 2131 // 32bit can do a case table jump in one instruction but we no longer allow the base 2132 // to be installed in the Address class. This jump will tranfers to the address 2133 // contained in the location described by entry (not the address of entry) 2134 void jump(ArrayAddress entry); 2135 2136 // Floating 2137 2138 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 2139 void andpd(XMMRegister dst, AddressLiteral src); 2140 2141 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 2142 void comiss(XMMRegister dst, AddressLiteral src); 2143 2144 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 2145 void comisd(XMMRegister dst, AddressLiteral src); 2146 2147 void fadd_s(Address src) { Assembler::fadd_s(src); } 2148 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 2149 2150 void fldcw(Address src) { Assembler::fldcw(src); } 2151 void fldcw(AddressLiteral src); 2152 2153 void fld_s(int index) { Assembler::fld_s(index); } 2154 void fld_s(Address src) { Assembler::fld_s(src); } 2155 void fld_s(AddressLiteral src); 2156 2157 void fld_d(Address src) { Assembler::fld_d(src); } 2158 void fld_d(AddressLiteral src); 2159 2160 void fld_x(Address src) { Assembler::fld_x(src); } 2161 void fld_x(AddressLiteral src); 2162 2163 void fmul_s(Address src) { Assembler::fmul_s(src); } 2164 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 2165 2166 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 2167 void ldmxcsr(AddressLiteral src); 2168 2169 private: 2170 // these are private because users should be doing movflt/movdbl 2171 2172 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 2173 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 2174 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 2175 void movss(XMMRegister dst, AddressLiteral src); 2176 2177 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 2178 void movlpd(XMMRegister dst, AddressLiteral src); 2179 2180 public: 2181 2182 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } 2183 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 2184 void addsd(XMMRegister dst, AddressLiteral src) { Assembler::addsd(dst, as_Address(src)); } 2185 2186 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } 2187 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 2188 void addss(XMMRegister dst, AddressLiteral src) { Assembler::addss(dst, as_Address(src)); } 2189 2190 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } 2191 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 2192 void divsd(XMMRegister dst, AddressLiteral src) { Assembler::divsd(dst, as_Address(src)); } 2193 2194 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } 2195 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 2196 void divss(XMMRegister dst, AddressLiteral src) { Assembler::divss(dst, as_Address(src)); } 2197 2198 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 2199 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 2200 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 2201 void movsd(XMMRegister dst, AddressLiteral src) { Assembler::movsd(dst, as_Address(src)); } 2202 2203 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } 2204 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 2205 void mulsd(XMMRegister dst, AddressLiteral src) { Assembler::mulsd(dst, as_Address(src)); } 2206 2207 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } 2208 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 2209 void mulss(XMMRegister dst, AddressLiteral src) { Assembler::mulss(dst, as_Address(src)); } 2210 2211 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } 2212 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 2213 void sqrtsd(XMMRegister dst, AddressLiteral src) { Assembler::sqrtsd(dst, as_Address(src)); } 2214 2215 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } 2216 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 2217 void sqrtss(XMMRegister dst, AddressLiteral src) { Assembler::sqrtss(dst, as_Address(src)); } 2218 2219 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } 2220 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 2221 void subsd(XMMRegister dst, AddressLiteral src) { Assembler::subsd(dst, as_Address(src)); } 2222 2223 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } 2224 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 2225 void subss(XMMRegister dst, AddressLiteral src) { Assembler::subss(dst, as_Address(src)); } 2226 2227 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 2228 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 2229 void ucomiss(XMMRegister dst, AddressLiteral src); 2230 2231 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 2232 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 2233 void ucomisd(XMMRegister dst, AddressLiteral src); 2234 2235 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 2236 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } 2237 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 2238 void xorpd(XMMRegister dst, AddressLiteral src); 2239 2240 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 2241 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } 2242 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 2243 void xorps(XMMRegister dst, AddressLiteral src); 2244 2245 // Data 2246 2247 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } 2248 2249 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } 2250 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } 2251 2252 void movoop(Register dst, jobject obj); 2253 void movoop(Address dst, jobject obj); 2254 2255 void movptr(ArrayAddress dst, Register src); 2256 // can this do an lea? 2257 void movptr(Register dst, ArrayAddress src); 2258 2259 void movptr(Register dst, Address src); 2260 2261 void movptr(Register dst, AddressLiteral src); 2262 2263 void movptr(Register dst, intptr_t src); 2264 void movptr(Register dst, Register src); 2265 void movptr(Address dst, intptr_t src); 2266 2267 void movptr(Address dst, Register src); 2268 2269 #ifdef _LP64 2270 // Generally the next two are only used for moving NULL 2271 // Although there are situations in initializing the mark word where 2272 // they could be used. They are dangerous. 2273 2274 // They only exist on LP64 so that int32_t and intptr_t are not the same 2275 // and we have ambiguous declarations. 2276 2277 void movptr(Address dst, int32_t imm32); 2278 void movptr(Register dst, int32_t imm32); 2279 #endif // _LP64 2280 2281 // to avoid hiding movl 2282 void mov32(AddressLiteral dst, Register src); 2283 void mov32(Register dst, AddressLiteral src); 2284 2285 // to avoid hiding movb 2286 void movbyte(ArrayAddress dst, int src); 2287 2288 // Can push value or effective address 2289 void pushptr(AddressLiteral src); 2290 2291 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 2292 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 2293 2294 void pushoop(jobject obj); 2295 2296 // sign extend as need a l to ptr sized element 2297 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 2298 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 2299 2300 // IndexOf strings. 2301 // Small strings are loaded through stack if they cross page boundary. 2302 void string_indexof(Register str1, Register str2, 2303 Register cnt1, Register cnt2, 2304 int int_cnt2, Register result, 2305 XMMRegister vec, Register tmp); 2306 2307 // IndexOf for constant substrings with size >= 8 elements 2308 // which don't need to be loaded through stack. 2309 void string_indexofC8(Register str1, Register str2, 2310 Register cnt1, Register cnt2, 2311 int int_cnt2, Register result, 2312 XMMRegister vec, Register tmp); 2313 2314 // Smallest code: we don't need to load through stack, 2315 // check string tail. 2316 2317 // Compare strings. 2318 void string_compare(Register str1, Register str2, 2319 Register cnt1, Register cnt2, Register result, 2320 XMMRegister vec1); 2321 2322 // Compare char[] arrays. 2323 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 2324 Register limit, Register result, Register chr, 2325 XMMRegister vec1, XMMRegister vec2); 2326 2327 // Fill primitive arrays 2328 void generate_fill(BasicType t, bool aligned, 2329 Register to, Register value, Register count, 2330 Register rtmp, XMMRegister xtmp); 2331 2332 #undef VIRTUAL 2333 2334 }; 2335 2336 /** 2337 * class SkipIfEqual: 2338 * 2339 * Instantiating this class will result in assembly code being output that will 2340 * jump around any code emitted between the creation of the instance and it's 2341 * automatic destruction at the end of a scope block, depending on the value of 2342 * the flag passed to the constructor, which will be checked at run-time. 2343 */ 2344 class SkipIfEqual { 2345 private: 2346 MacroAssembler* _masm; 2347 Label _label; 2348 2349 public: 2350 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 2351 ~SkipIfEqual(); 2352 }; 2353 2354 #ifdef ASSERT 2355 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } 2356 #endif 2357 2358 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP