138
139 void FrameMap::initialize() {
140 assert(!_init_done, "once");
141
142 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
143 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
144 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
145 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
146 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
147 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
148 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
149
150 #ifndef _LP64
151 // The unallocatable registers are at the end
152 map_register(6, rsp);
153 map_register(7, rbp);
154 #else
155 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
156 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
157 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
158 map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
159 map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
160 map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
161 // The unallocatable registers are at the end
162 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
163 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
164 map_register(14, rsp);
165 map_register(15, rbp);
166 #endif // _LP64
167
168 #ifdef _LP64
169 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
170 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
171 #else
172 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
173 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
174 #endif // _LP64
175 fpu0_float_opr = LIR_OprFact::single_fpu(0);
176 fpu0_double_opr = LIR_OprFact::double_fpu(0);
177 xmm0_float_opr = LIR_OprFact::single_xmm(0);
178 xmm0_double_opr = LIR_OprFact::double_xmm(0);
179
180 _caller_save_cpu_regs[0] = rsi_opr;
181 _caller_save_cpu_regs[1] = rdi_opr;
182 _caller_save_cpu_regs[2] = rbx_opr;
183 _caller_save_cpu_regs[3] = rax_opr;
184 _caller_save_cpu_regs[4] = rdx_opr;
185 _caller_save_cpu_regs[5] = rcx_opr;
186
187 #ifdef _LP64
188 _caller_save_cpu_regs[6] = r8_opr;
189 _caller_save_cpu_regs[7] = r9_opr;
190 _caller_save_cpu_regs[8] = r11_opr;
191 _caller_save_cpu_regs[9] = r12_opr;
192 _caller_save_cpu_regs[10] = r13_opr;
193 _caller_save_cpu_regs[11] = r14_opr;
194 #endif // _LP64
195
196
197 _xmm_regs[0] = xmm0;
198 _xmm_regs[1] = xmm1;
199 _xmm_regs[2] = xmm2;
200 _xmm_regs[3] = xmm3;
201 _xmm_regs[4] = xmm4;
202 _xmm_regs[5] = xmm5;
203 _xmm_regs[6] = xmm6;
204 _xmm_regs[7] = xmm7;
205
206 #ifdef _LP64
207 _xmm_regs[8] = xmm8;
208 _xmm_regs[9] = xmm9;
209 _xmm_regs[10] = xmm10;
210 _xmm_regs[11] = xmm11;
211 _xmm_regs[12] = xmm12;
212 _xmm_regs[13] = xmm13;
213 _xmm_regs[14] = xmm14;
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138
139 void FrameMap::initialize() {
140 assert(!_init_done, "once");
141
142 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
143 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
144 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
145 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
146 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
147 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
148 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
149
150 #ifndef _LP64
151 // The unallocatable registers are at the end
152 map_register(6, rsp);
153 map_register(7, rbp);
154 #else
155 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
156 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
157 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
158 map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9);
159 map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10);
160 // r12 is allocated conditionally. With compressed oops it holds
161 // the heapbase value and is not visible to the allocator.
162 map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11);
163 // The unallocatable registers are at the end
164 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
165 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
166 map_register(14, rsp);
167 map_register(15, rbp);
168 #endif // _LP64
169
170 #ifdef _LP64
171 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
172 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
173 #else
174 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
175 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
176 #endif // _LP64
177 fpu0_float_opr = LIR_OprFact::single_fpu(0);
178 fpu0_double_opr = LIR_OprFact::double_fpu(0);
179 xmm0_float_opr = LIR_OprFact::single_xmm(0);
180 xmm0_double_opr = LIR_OprFact::double_xmm(0);
181
182 _caller_save_cpu_regs[0] = rsi_opr;
183 _caller_save_cpu_regs[1] = rdi_opr;
184 _caller_save_cpu_regs[2] = rbx_opr;
185 _caller_save_cpu_regs[3] = rax_opr;
186 _caller_save_cpu_regs[4] = rdx_opr;
187 _caller_save_cpu_regs[5] = rcx_opr;
188
189 #ifdef _LP64
190 _caller_save_cpu_regs[6] = r8_opr;
191 _caller_save_cpu_regs[7] = r9_opr;
192 _caller_save_cpu_regs[8] = r11_opr;
193 _caller_save_cpu_regs[9] = r13_opr;
194 _caller_save_cpu_regs[10] = r14_opr;
195 _caller_save_cpu_regs[11] = r12_opr;
196 #endif // _LP64
197
198
199 _xmm_regs[0] = xmm0;
200 _xmm_regs[1] = xmm1;
201 _xmm_regs[2] = xmm2;
202 _xmm_regs[3] = xmm3;
203 _xmm_regs[4] = xmm4;
204 _xmm_regs[5] = xmm5;
205 _xmm_regs[6] = xmm6;
206 _xmm_regs[7] = xmm7;
207
208 #ifdef _LP64
209 _xmm_regs[8] = xmm8;
210 _xmm_regs[9] = xmm9;
211 _xmm_regs[10] = xmm10;
212 _xmm_regs[11] = xmm11;
213 _xmm_regs[12] = xmm12;
214 _xmm_regs[13] = xmm13;
215 _xmm_regs[14] = xmm14;
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