1 /* 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 # include "incls/_precompiled.incl" 26 # include "incls/_c1_LIRAssembler_x86.cpp.incl" 27 28 29 // These masks are used to provide 128-bit aligned bitmasks to the XMM 30 // instructions, to allow sign-masking or sign-bit flipping. They allow 31 // fast versions of NegF/NegD and AbsF/AbsD. 32 33 // Note: 'double' and 'long long' have 32-bits alignment on x86. 34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 36 // of 128-bits operands for SSE instructions. 37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); 38 // Store the value to a 128-bits operand. 39 operand[0] = lo; 40 operand[1] = hi; 41 return operand; 42 } 43 44 // Buffer for 128-bits masks used by SSE instructions. 45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 46 47 // Static initialization during VM startup. 48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 52 53 54 55 NEEDS_CLEANUP // remove this definitions ? 56 const Register IC_Klass = rax; // where the IC klass is cached 57 const Register SYNC_header = rax; // synchronization header 58 const Register SHIFT_count = rcx; // where count for shift operations must be 59 60 #define __ _masm-> 61 62 63 static void select_different_registers(Register preserve, 64 Register extra, 65 Register &tmp1, 66 Register &tmp2) { 67 if (tmp1 == preserve) { 68 assert_different_registers(tmp1, tmp2, extra); 69 tmp1 = extra; 70 } else if (tmp2 == preserve) { 71 assert_different_registers(tmp1, tmp2, extra); 72 tmp2 = extra; 73 } 74 assert_different_registers(preserve, tmp1, tmp2); 75 } 76 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2, 83 Register &tmp3) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, tmp3, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, tmp3, extra); 89 tmp2 = extra; 90 } else if (tmp3 == preserve) { 91 assert_different_registers(tmp1, tmp2, tmp3, extra); 92 tmp3 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); 95 } 96 97 98 99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 100 if (opr->is_constant()) { 101 LIR_Const* constant = opr->as_constant_ptr(); 102 switch (constant->type()) { 103 case T_INT: { 104 return true; 105 } 106 107 default: 108 return false; 109 } 110 } 111 return false; 112 } 113 114 115 LIR_Opr LIR_Assembler::receiverOpr() { 116 return FrameMap::receiver_opr; 117 } 118 119 LIR_Opr LIR_Assembler::incomingReceiverOpr() { 120 return receiverOpr(); 121 } 122 123 LIR_Opr LIR_Assembler::osrBufferPointer() { 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 125 } 126 127 //--------------fpu register translations----------------------- 128 129 130 address LIR_Assembler::float_constant(float f) { 131 address const_addr = __ float_constant(f); 132 if (const_addr == NULL) { 133 bailout("const section overflow"); 134 return __ code()->consts()->start(); 135 } else { 136 return const_addr; 137 } 138 } 139 140 141 address LIR_Assembler::double_constant(double d) { 142 address const_addr = __ double_constant(d); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149 } 150 151 152 void LIR_Assembler::set_24bit_FPU() { 153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 154 } 155 156 void LIR_Assembler::reset_FPU() { 157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 158 } 159 160 void LIR_Assembler::fpop() { 161 __ fpop(); 162 } 163 164 void LIR_Assembler::fxch(int i) { 165 __ fxch(i); 166 } 167 168 void LIR_Assembler::fld(int i) { 169 __ fld_s(i); 170 } 171 172 void LIR_Assembler::ffree(int i) { 173 __ ffree(i); 174 } 175 176 void LIR_Assembler::breakpoint() { 177 __ int3(); 178 } 179 180 void LIR_Assembler::push(LIR_Opr opr) { 181 if (opr->is_single_cpu()) { 182 __ push_reg(opr->as_register()); 183 } else if (opr->is_double_cpu()) { 184 NOT_LP64(__ push_reg(opr->as_register_hi())); 185 __ push_reg(opr->as_register_lo()); 186 } else if (opr->is_stack()) { 187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 188 } else if (opr->is_constant()) { 189 LIR_Const* const_opr = opr->as_constant_ptr(); 190 if (const_opr->type() == T_OBJECT) { 191 __ push_oop(const_opr->as_jobject()); 192 } else if (const_opr->type() == T_INT) { 193 __ push_jint(const_opr->as_jint()); 194 } else { 195 ShouldNotReachHere(); 196 } 197 198 } else { 199 ShouldNotReachHere(); 200 } 201 } 202 203 void LIR_Assembler::pop(LIR_Opr opr) { 204 if (opr->is_single_cpu()) { 205 __ pop_reg(opr->as_register()); 206 } else { 207 ShouldNotReachHere(); 208 } 209 } 210 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 212 return addr->base()->is_illegal() && addr->index()->is_illegal(); 213 } 214 215 //------------------------------------------- 216 217 Address LIR_Assembler::as_Address(LIR_Address* addr) { 218 return as_Address(addr, rscratch1); 219 } 220 221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 222 if (addr->base()->is_illegal()) { 223 assert(addr->index()->is_illegal(), "must be illegal too"); 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 225 if (! __ reachable(laddr)) { 226 __ movptr(tmp, laddr.addr()); 227 Address res(tmp, 0); 228 return res; 229 } else { 230 return __ as_Address(laddr); 231 } 232 } 233 234 Register base = addr->base()->as_pointer_register(); 235 236 if (addr->index()->is_illegal()) { 237 return Address( base, addr->disp()); 238 } else if (addr->index()->is_cpu_register()) { 239 Register index = addr->index()->as_pointer_register(); 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 241 } else if (addr->index()->is_constant()) { 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 243 assert(Assembler::is_simm32(addr_offset), "must be"); 244 245 return Address(base, addr_offset); 246 } else { 247 Unimplemented(); 248 return Address(); 249 } 250 } 251 252 253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 254 Address base = as_Address(addr); 255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 256 } 257 258 259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 260 return as_Address(addr); 261 } 262 263 264 void LIR_Assembler::osr_entry() { 265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 266 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 267 ValueStack* entry_state = osr_entry->state(); 268 int number_of_locks = entry_state->locks_size(); 269 270 // we jump here if osr happens with the interpreter 271 // state set up to continue at the beginning of the 272 // loop that triggered osr - in particular, we have 273 // the following registers setup: 274 // 275 // rcx: osr buffer 276 // 277 278 // build frame 279 ciMethod* m = compilation()->method(); 280 __ build_frame(initial_frame_size_in_bytes()); 281 282 // OSR buffer is 283 // 284 // locals[nlocals-1..0] 285 // monitors[0..number_of_locks] 286 // 287 // locals is a direct copy of the interpreter frame so in the osr buffer 288 // so first slot in the local array is the last local from the interpreter 289 // and last slot is local[0] (receiver) from the interpreter 290 // 291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 293 // in the interpreter frame (the method lock if a sync method) 294 295 // Initialize monitors in the compiled activation. 296 // rcx: pointer to osr buffer 297 // 298 // All other registers are dead at this point and the locals will be 299 // copied into place by code emitted in the IR. 300 301 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 303 int monitor_offset = BytesPerWord * method()->max_locals() + 304 (2 * BytesPerWord) * (number_of_locks - 1); 305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 306 // the OSR buffer using 2 word entries: first the lock and then 307 // the oop. 308 for (int i = 0; i < number_of_locks; i++) { 309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 310 #ifdef ASSERT 311 // verify the interpreter's monitor has a non-null object 312 { 313 Label L; 314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 315 __ jcc(Assembler::notZero, L); 316 __ stop("locked object is NULL"); 317 __ bind(L); 318 } 319 #endif 320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 323 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 324 } 325 } 326 } 327 328 329 // inline cache check; done before the frame is built. 330 int LIR_Assembler::check_icache() { 331 Register receiver = FrameMap::receiver_opr->as_register(); 332 Register ic_klass = IC_Klass; 333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 334 335 if (!VerifyOops) { 336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 338 __ nop(); 339 } 340 } 341 int offset = __ offset(); 342 __ inline_cache_check(receiver, IC_Klass); 343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); 344 if (VerifyOops) { 345 // force alignment after the cache check. 346 // It's been verified to be aligned if !VerifyOops 347 __ align(CodeEntryAlignment); 348 } 349 return offset; 350 } 351 352 353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 354 jobject o = NULL; 355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 356 __ movoop(reg, o); 357 patching_epilog(patch, lir_patch_normal, reg, info); 358 } 359 360 361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { 362 if (exception->is_valid()) { 363 // preserve exception 364 // note: the monitor_exit runtime call is a leaf routine 365 // and cannot block => no GC can happen 366 // The slow case (MonitorAccessStub) uses the first two stack slots 367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] 368 __ movptr (Address(rsp, 2*wordSize), exception); 369 } 370 371 Register obj_reg = obj_opr->as_register(); 372 Register lock_reg = lock_opr->as_register(); 373 374 // setup registers (lock_reg must be rax, for lock_object) 375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); 376 Register hdr = lock_reg; 377 assert(new_hdr == SYNC_header, "wrong register"); 378 lock_reg = new_hdr; 379 // compute pointer to BasicLock 380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); 381 __ lea(lock_reg, lock_addr); 382 // unlock object 383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); 384 // _slow_case_stubs->append(slow_case); 385 // temporary fix: must be created after exceptionhandler, therefore as call stub 386 _slow_case_stubs->append(slow_case); 387 if (UseFastLocking) { 388 // try inlined fast unlocking first, revert to slow locking if it fails 389 // note: lock_reg points to the displaced header since the displaced header offset is 0! 390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 392 } else { 393 // always do slow unlocking 394 // note: the slow unlocking code could be inlined here, however if we use 395 // slow unlocking, speed doesn't matter anyway and this solution is 396 // simpler and requires less duplicated code - additionally, the 397 // slow unlocking code is the same in either case which simplifies 398 // debugging 399 __ jmp(*slow_case->entry()); 400 } 401 // done 402 __ bind(*slow_case->continuation()); 403 404 if (exception->is_valid()) { 405 // restore exception 406 __ movptr (exception, Address(rsp, 2 * wordSize)); 407 } 408 } 409 410 // This specifies the rsp decrement needed to build the frame 411 int LIR_Assembler::initial_frame_size_in_bytes() { 412 // if rounding, must let FrameMap know! 413 414 // The frame_map records size in slots (32bit word) 415 416 // subtract two words to account for return address and link 417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 418 } 419 420 421 int LIR_Assembler::emit_exception_handler() { 422 // if the last instruction is a call (typically to do a throw which 423 // is coming at the end after block reordering) the return address 424 // must still point into the code area in order to avoid assertion 425 // failures when searching for the corresponding bci => add a nop 426 // (was bug 5/14/1999 - gri) 427 __ nop(); 428 429 // generate code for exception handler 430 address handler_base = __ start_a_stub(exception_handler_size); 431 if (handler_base == NULL) { 432 // not enough space left for the handler 433 bailout("exception handler overflow"); 434 return -1; 435 } 436 437 int offset = code_offset(); 438 439 // the exception oop and pc are in rax, and rdx 440 // no other registers need to be preserved, so invalidate them 441 __ invalidate_registers(false, true, true, false, true, true); 442 443 // check that there is really an exception 444 __ verify_not_null_oop(rax); 445 446 // search an exception handler (rax: exception oop, rdx: throwing pc) 447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); 448 449 __ stop("should not reach here"); 450 451 assert(code_offset() - offset <= exception_handler_size, "overflow"); 452 __ end_a_stub(); 453 454 return offset; 455 } 456 457 458 // Emit the code to remove the frame from the stack in the exception 459 // unwind path. 460 int LIR_Assembler::emit_unwind_handler() { 461 #ifndef PRODUCT 462 if (CommentedAssembly) { 463 _masm->block_comment("Unwind handler"); 464 } 465 #endif 466 467 int offset = code_offset(); 468 469 // Fetch the exception from TLS and clear out exception related thread state 470 __ get_thread(rsi); 471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); 472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); 473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 474 475 __ bind(_unwind_handler_entry); 476 __ verify_not_null_oop(rax); 477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 478 __ mov(rsi, rax); // Preserve the exception 479 } 480 481 // Preform needed unlocking 482 MonitorExitStub* stub = NULL; 483 if (method()->is_synchronized()) { 484 monitor_address(0, FrameMap::rax_opr); 485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 486 __ unlock_object(rdi, rbx, rax, *stub->entry()); 487 __ bind(*stub->continuation()); 488 } 489 490 if (compilation()->env()->dtrace_method_probes()) { 491 __ get_thread(rax); 492 __ movptr(Address(rsp, 0), rax); 493 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); 494 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 495 } 496 497 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 498 __ mov(rax, rsi); // Restore the exception 499 } 500 501 // remove the activation and dispatch to the unwind handler 502 __ remove_frame(initial_frame_size_in_bytes()); 503 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 504 505 // Emit the slow path assembly 506 if (stub != NULL) { 507 stub->emit_code(this); 508 } 509 510 return offset; 511 } 512 513 514 int LIR_Assembler::emit_deopt_handler() { 515 // if the last instruction is a call (typically to do a throw which 516 // is coming at the end after block reordering) the return address 517 // must still point into the code area in order to avoid assertion 518 // failures when searching for the corresponding bci => add a nop 519 // (was bug 5/14/1999 - gri) 520 __ nop(); 521 522 // generate code for exception handler 523 address handler_base = __ start_a_stub(deopt_handler_size); 524 if (handler_base == NULL) { 525 // not enough space left for the handler 526 bailout("deopt handler overflow"); 527 return -1; 528 } 529 530 int offset = code_offset(); 531 InternalAddress here(__ pc()); 532 533 __ pushptr(here.addr()); 534 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 535 536 assert(code_offset() - offset <= deopt_handler_size, "overflow"); 537 __ end_a_stub(); 538 539 return offset; 540 } 541 542 543 // This is the fast version of java.lang.String.compare; it has not 544 // OSR-entry and therefore, we generate a slow version for OSR's 545 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 546 __ movptr (rbx, rcx); // receiver is in rcx 547 __ movptr (rax, arg1->as_register()); 548 549 // Get addresses of first characters from both Strings 550 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 551 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 552 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 553 554 555 // rbx, may be NULL 556 add_debug_info_for_null_check_here(info); 557 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 558 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 559 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 560 561 // compute minimum length (in rax) and difference of lengths (on top of stack) 562 if (VM_Version::supports_cmov()) { 563 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 564 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 565 __ mov (rcx, rbx); 566 __ subptr (rbx, rax); // subtract lengths 567 __ push (rbx); // result 568 __ cmov (Assembler::lessEqual, rax, rcx); 569 } else { 570 Label L; 571 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 572 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); 573 __ mov (rax, rbx); 574 __ subptr (rbx, rcx); 575 __ push (rbx); 576 __ jcc (Assembler::lessEqual, L); 577 __ mov (rax, rcx); 578 __ bind (L); 579 } 580 // is minimum length 0? 581 Label noLoop, haveResult; 582 __ testptr (rax, rax); 583 __ jcc (Assembler::zero, noLoop); 584 585 // compare first characters 586 __ load_unsigned_short(rcx, Address(rdi, 0)); 587 __ load_unsigned_short(rbx, Address(rsi, 0)); 588 __ subl(rcx, rbx); 589 __ jcc(Assembler::notZero, haveResult); 590 // starting loop 591 __ decrement(rax); // we already tested index: skip one 592 __ jcc(Assembler::zero, noLoop); 593 594 // set rsi.edi to the end of the arrays (arrays have same length) 595 // negate the index 596 597 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 598 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 599 __ negptr(rax); 600 601 // compare the strings in a loop 602 603 Label loop; 604 __ align(wordSize); 605 __ bind(loop); 606 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); 607 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); 608 __ subl(rcx, rbx); 609 __ jcc(Assembler::notZero, haveResult); 610 __ increment(rax); 611 __ jcc(Assembler::notZero, loop); 612 613 // strings are equal up to min length 614 615 __ bind(noLoop); 616 __ pop(rax); 617 return_op(LIR_OprFact::illegalOpr); 618 619 __ bind(haveResult); 620 // leave instruction is going to discard the TOS value 621 __ mov (rax, rcx); // result of call is in rax, 622 } 623 624 625 void LIR_Assembler::return_op(LIR_Opr result) { 626 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 627 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 628 assert(result->fpu() == 0, "result must already be on TOS"); 629 } 630 631 // Pop the stack before the safepoint code 632 __ remove_frame(initial_frame_size_in_bytes()); 633 634 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 635 636 // Note: we do not need to round double result; float result has the right precision 637 // the poll sets the condition code, but no data registers 638 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 639 relocInfo::poll_return_type); 640 641 // NOTE: the requires that the polling page be reachable else the reloc 642 // goes to the movq that loads the address and not the faulting instruction 643 // which breaks the signal handler code 644 645 __ test32(rax, polling_page); 646 647 __ ret(0); 648 } 649 650 651 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 652 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 653 relocInfo::poll_type); 654 655 if (info != NULL) { 656 add_debug_info_for_branch(info); 657 } else { 658 ShouldNotReachHere(); 659 } 660 661 int offset = __ offset(); 662 663 // NOTE: the requires that the polling page be reachable else the reloc 664 // goes to the movq that loads the address and not the faulting instruction 665 // which breaks the signal handler code 666 667 __ test32(rax, polling_page); 668 return offset; 669 } 670 671 672 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 673 if (from_reg != to_reg) __ mov(to_reg, from_reg); 674 } 675 676 void LIR_Assembler::swap_reg(Register a, Register b) { 677 __ xchgptr(a, b); 678 } 679 680 681 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 682 assert(src->is_constant(), "should not call otherwise"); 683 assert(dest->is_register(), "should not call otherwise"); 684 LIR_Const* c = src->as_constant_ptr(); 685 686 switch (c->type()) { 687 case T_INT: 688 case T_ADDRESS: { 689 assert(patch_code == lir_patch_none, "no patching handled here"); 690 __ movl(dest->as_register(), c->as_jint()); 691 break; 692 } 693 694 case T_LONG: { 695 assert(patch_code == lir_patch_none, "no patching handled here"); 696 #ifdef _LP64 697 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 698 #else 699 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 700 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 701 #endif // _LP64 702 break; 703 } 704 705 case T_OBJECT: { 706 if (patch_code != lir_patch_none) { 707 jobject2reg_with_patching(dest->as_register(), info); 708 } else { 709 __ movoop(dest->as_register(), c->as_jobject()); 710 } 711 break; 712 } 713 714 case T_FLOAT: { 715 if (dest->is_single_xmm()) { 716 if (c->is_zero_float()) { 717 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 718 } else { 719 __ movflt(dest->as_xmm_float_reg(), 720 InternalAddress(float_constant(c->as_jfloat()))); 721 } 722 } else { 723 assert(dest->is_single_fpu(), "must be"); 724 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 725 if (c->is_zero_float()) { 726 __ fldz(); 727 } else if (c->is_one_float()) { 728 __ fld1(); 729 } else { 730 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 731 } 732 } 733 break; 734 } 735 736 case T_DOUBLE: { 737 if (dest->is_double_xmm()) { 738 if (c->is_zero_double()) { 739 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 740 } else { 741 __ movdbl(dest->as_xmm_double_reg(), 742 InternalAddress(double_constant(c->as_jdouble()))); 743 } 744 } else { 745 assert(dest->is_double_fpu(), "must be"); 746 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 747 if (c->is_zero_double()) { 748 __ fldz(); 749 } else if (c->is_one_double()) { 750 __ fld1(); 751 } else { 752 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 753 } 754 } 755 break; 756 } 757 758 default: 759 ShouldNotReachHere(); 760 } 761 } 762 763 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 764 assert(src->is_constant(), "should not call otherwise"); 765 assert(dest->is_stack(), "should not call otherwise"); 766 LIR_Const* c = src->as_constant_ptr(); 767 768 switch (c->type()) { 769 case T_INT: // fall through 770 case T_FLOAT: 771 case T_ADDRESS: 772 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 773 break; 774 775 case T_OBJECT: 776 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 777 break; 778 779 case T_LONG: // fall through 780 case T_DOUBLE: 781 #ifdef _LP64 782 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 783 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 784 #else 785 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 786 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 787 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 788 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 789 #endif // _LP64 790 break; 791 792 default: 793 ShouldNotReachHere(); 794 } 795 } 796 797 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { 798 assert(src->is_constant(), "should not call otherwise"); 799 assert(dest->is_address(), "should not call otherwise"); 800 LIR_Const* c = src->as_constant_ptr(); 801 LIR_Address* addr = dest->as_address_ptr(); 802 803 int null_check_here = code_offset(); 804 switch (type) { 805 case T_INT: // fall through 806 case T_FLOAT: 807 case T_ADDRESS: 808 __ movl(as_Address(addr), c->as_jint_bits()); 809 break; 810 811 case T_OBJECT: // fall through 812 case T_ARRAY: 813 if (c->as_jobject() == NULL) { 814 __ movptr(as_Address(addr), NULL_WORD); 815 } else { 816 if (is_literal_address(addr)) { 817 ShouldNotReachHere(); 818 __ movoop(as_Address(addr, noreg), c->as_jobject()); 819 } else { 820 #ifdef _LP64 821 __ movoop(rscratch1, c->as_jobject()); 822 null_check_here = code_offset(); 823 __ movptr(as_Address_lo(addr), rscratch1); 824 #else 825 __ movoop(as_Address(addr), c->as_jobject()); 826 #endif 827 } 828 } 829 break; 830 831 case T_LONG: // fall through 832 case T_DOUBLE: 833 #ifdef _LP64 834 if (is_literal_address(addr)) { 835 ShouldNotReachHere(); 836 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 837 } else { 838 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 839 null_check_here = code_offset(); 840 __ movptr(as_Address_lo(addr), r10); 841 } 842 #else 843 // Always reachable in 32bit so this doesn't produce useless move literal 844 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 845 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 846 #endif // _LP64 847 break; 848 849 case T_BOOLEAN: // fall through 850 case T_BYTE: 851 __ movb(as_Address(addr), c->as_jint() & 0xFF); 852 break; 853 854 case T_CHAR: // fall through 855 case T_SHORT: 856 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 857 break; 858 859 default: 860 ShouldNotReachHere(); 861 }; 862 863 if (info != NULL) { 864 add_debug_info_for_null_check(null_check_here, info); 865 } 866 } 867 868 869 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 870 assert(src->is_register(), "should not call otherwise"); 871 assert(dest->is_register(), "should not call otherwise"); 872 873 // move between cpu-registers 874 if (dest->is_single_cpu()) { 875 #ifdef _LP64 876 if (src->type() == T_LONG) { 877 // Can do LONG -> OBJECT 878 move_regs(src->as_register_lo(), dest->as_register()); 879 return; 880 } 881 #endif 882 assert(src->is_single_cpu(), "must match"); 883 if (src->type() == T_OBJECT) { 884 __ verify_oop(src->as_register()); 885 } 886 move_regs(src->as_register(), dest->as_register()); 887 888 } else if (dest->is_double_cpu()) { 889 #ifdef _LP64 890 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 891 // Surprising to me but we can see move of a long to t_object 892 __ verify_oop(src->as_register()); 893 move_regs(src->as_register(), dest->as_register_lo()); 894 return; 895 } 896 #endif 897 assert(src->is_double_cpu(), "must match"); 898 Register f_lo = src->as_register_lo(); 899 Register f_hi = src->as_register_hi(); 900 Register t_lo = dest->as_register_lo(); 901 Register t_hi = dest->as_register_hi(); 902 #ifdef _LP64 903 assert(f_hi == f_lo, "must be same"); 904 assert(t_hi == t_lo, "must be same"); 905 move_regs(f_lo, t_lo); 906 #else 907 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 908 909 910 if (f_lo == t_hi && f_hi == t_lo) { 911 swap_reg(f_lo, f_hi); 912 } else if (f_hi == t_lo) { 913 assert(f_lo != t_hi, "overwriting register"); 914 move_regs(f_hi, t_hi); 915 move_regs(f_lo, t_lo); 916 } else { 917 assert(f_hi != t_lo, "overwriting register"); 918 move_regs(f_lo, t_lo); 919 move_regs(f_hi, t_hi); 920 } 921 #endif // LP64 922 923 // special moves from fpu-register to xmm-register 924 // necessary for method results 925 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 926 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 927 __ fld_s(Address(rsp, 0)); 928 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 929 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 930 __ fld_d(Address(rsp, 0)); 931 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 932 __ fstp_s(Address(rsp, 0)); 933 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 934 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 935 __ fstp_d(Address(rsp, 0)); 936 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 937 938 // move between xmm-registers 939 } else if (dest->is_single_xmm()) { 940 assert(src->is_single_xmm(), "must match"); 941 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 942 } else if (dest->is_double_xmm()) { 943 assert(src->is_double_xmm(), "must match"); 944 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 945 946 // move between fpu-registers (no instruction necessary because of fpu-stack) 947 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 948 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 949 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 950 } else { 951 ShouldNotReachHere(); 952 } 953 } 954 955 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 956 assert(src->is_register(), "should not call otherwise"); 957 assert(dest->is_stack(), "should not call otherwise"); 958 959 if (src->is_single_cpu()) { 960 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 961 if (type == T_OBJECT || type == T_ARRAY) { 962 __ verify_oop(src->as_register()); 963 __ movptr (dst, src->as_register()); 964 } else { 965 __ movl (dst, src->as_register()); 966 } 967 968 } else if (src->is_double_cpu()) { 969 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 970 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 971 __ movptr (dstLO, src->as_register_lo()); 972 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 973 974 } else if (src->is_single_xmm()) { 975 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 976 __ movflt(dst_addr, src->as_xmm_float_reg()); 977 978 } else if (src->is_double_xmm()) { 979 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 980 __ movdbl(dst_addr, src->as_xmm_double_reg()); 981 982 } else if (src->is_single_fpu()) { 983 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 984 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 985 if (pop_fpu_stack) __ fstp_s (dst_addr); 986 else __ fst_s (dst_addr); 987 988 } else if (src->is_double_fpu()) { 989 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 990 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 991 if (pop_fpu_stack) __ fstp_d (dst_addr); 992 else __ fst_d (dst_addr); 993 994 } else { 995 ShouldNotReachHere(); 996 } 997 } 998 999 1000 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { 1001 LIR_Address* to_addr = dest->as_address_ptr(); 1002 PatchingStub* patch = NULL; 1003 1004 if (type == T_ARRAY || type == T_OBJECT) { 1005 __ verify_oop(src->as_register()); 1006 } 1007 if (patch_code != lir_patch_none) { 1008 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1009 Address toa = as_Address(to_addr); 1010 assert(toa.disp() != 0, "must have"); 1011 } 1012 if (info != NULL) { 1013 add_debug_info_for_null_check_here(info); 1014 } 1015 1016 switch (type) { 1017 case T_FLOAT: { 1018 if (src->is_single_xmm()) { 1019 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 1020 } else { 1021 assert(src->is_single_fpu(), "must be"); 1022 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 1023 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 1024 else __ fst_s (as_Address(to_addr)); 1025 } 1026 break; 1027 } 1028 1029 case T_DOUBLE: { 1030 if (src->is_double_xmm()) { 1031 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1032 } else { 1033 assert(src->is_double_fpu(), "must be"); 1034 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1035 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1036 else __ fst_d (as_Address(to_addr)); 1037 } 1038 break; 1039 } 1040 1041 case T_ADDRESS: // fall through 1042 case T_ARRAY: // fall through 1043 case T_OBJECT: // fall through 1044 #ifdef _LP64 1045 __ movptr(as_Address(to_addr), src->as_register()); 1046 break; 1047 #endif // _LP64 1048 case T_INT: 1049 __ movl(as_Address(to_addr), src->as_register()); 1050 break; 1051 1052 case T_LONG: { 1053 Register from_lo = src->as_register_lo(); 1054 Register from_hi = src->as_register_hi(); 1055 #ifdef _LP64 1056 __ movptr(as_Address_lo(to_addr), from_lo); 1057 #else 1058 Register base = to_addr->base()->as_register(); 1059 Register index = noreg; 1060 if (to_addr->index()->is_register()) { 1061 index = to_addr->index()->as_register(); 1062 } 1063 if (base == from_lo || index == from_lo) { 1064 assert(base != from_hi, "can't be"); 1065 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1066 __ movl(as_Address_hi(to_addr), from_hi); 1067 if (patch != NULL) { 1068 patching_epilog(patch, lir_patch_high, base, info); 1069 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1070 patch_code = lir_patch_low; 1071 } 1072 __ movl(as_Address_lo(to_addr), from_lo); 1073 } else { 1074 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1075 __ movl(as_Address_lo(to_addr), from_lo); 1076 if (patch != NULL) { 1077 patching_epilog(patch, lir_patch_low, base, info); 1078 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1079 patch_code = lir_patch_high; 1080 } 1081 __ movl(as_Address_hi(to_addr), from_hi); 1082 } 1083 #endif // _LP64 1084 break; 1085 } 1086 1087 case T_BYTE: // fall through 1088 case T_BOOLEAN: { 1089 Register src_reg = src->as_register(); 1090 Address dst_addr = as_Address(to_addr); 1091 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1092 __ movb(dst_addr, src_reg); 1093 break; 1094 } 1095 1096 case T_CHAR: // fall through 1097 case T_SHORT: 1098 __ movw(as_Address(to_addr), src->as_register()); 1099 break; 1100 1101 default: 1102 ShouldNotReachHere(); 1103 } 1104 1105 if (patch_code != lir_patch_none) { 1106 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1107 } 1108 } 1109 1110 1111 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1112 assert(src->is_stack(), "should not call otherwise"); 1113 assert(dest->is_register(), "should not call otherwise"); 1114 1115 if (dest->is_single_cpu()) { 1116 if (type == T_ARRAY || type == T_OBJECT) { 1117 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1118 __ verify_oop(dest->as_register()); 1119 } else { 1120 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1121 } 1122 1123 } else if (dest->is_double_cpu()) { 1124 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1125 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1126 __ movptr(dest->as_register_lo(), src_addr_LO); 1127 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1128 1129 } else if (dest->is_single_xmm()) { 1130 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1131 __ movflt(dest->as_xmm_float_reg(), src_addr); 1132 1133 } else if (dest->is_double_xmm()) { 1134 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1135 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1136 1137 } else if (dest->is_single_fpu()) { 1138 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1139 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1140 __ fld_s(src_addr); 1141 1142 } else if (dest->is_double_fpu()) { 1143 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1144 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1145 __ fld_d(src_addr); 1146 1147 } else { 1148 ShouldNotReachHere(); 1149 } 1150 } 1151 1152 1153 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1154 if (src->is_single_stack()) { 1155 if (type == T_OBJECT || type == T_ARRAY) { 1156 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1157 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1158 } else { 1159 #ifndef _LP64 1160 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1161 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1162 #else 1163 //no pushl on 64bits 1164 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1165 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1166 #endif 1167 } 1168 1169 } else if (src->is_double_stack()) { 1170 #ifdef _LP64 1171 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1172 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1173 #else 1174 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1175 // push and pop the part at src + wordSize, adding wordSize for the previous push 1176 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1177 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1178 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1179 #endif // _LP64 1180 1181 } else { 1182 ShouldNotReachHere(); 1183 } 1184 } 1185 1186 1187 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { 1188 assert(src->is_address(), "should not call otherwise"); 1189 assert(dest->is_register(), "should not call otherwise"); 1190 1191 LIR_Address* addr = src->as_address_ptr(); 1192 Address from_addr = as_Address(addr); 1193 1194 switch (type) { 1195 case T_BOOLEAN: // fall through 1196 case T_BYTE: // fall through 1197 case T_CHAR: // fall through 1198 case T_SHORT: 1199 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1200 // on pre P6 processors we may get partial register stalls 1201 // so blow away the value of to_rinfo before loading a 1202 // partial word into it. Do it here so that it precedes 1203 // the potential patch point below. 1204 __ xorptr(dest->as_register(), dest->as_register()); 1205 } 1206 break; 1207 } 1208 1209 PatchingStub* patch = NULL; 1210 if (patch_code != lir_patch_none) { 1211 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1212 assert(from_addr.disp() != 0, "must have"); 1213 } 1214 if (info != NULL) { 1215 add_debug_info_for_null_check_here(info); 1216 } 1217 1218 switch (type) { 1219 case T_FLOAT: { 1220 if (dest->is_single_xmm()) { 1221 __ movflt(dest->as_xmm_float_reg(), from_addr); 1222 } else { 1223 assert(dest->is_single_fpu(), "must be"); 1224 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1225 __ fld_s(from_addr); 1226 } 1227 break; 1228 } 1229 1230 case T_DOUBLE: { 1231 if (dest->is_double_xmm()) { 1232 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1233 } else { 1234 assert(dest->is_double_fpu(), "must be"); 1235 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1236 __ fld_d(from_addr); 1237 } 1238 break; 1239 } 1240 1241 case T_ADDRESS: // fall through 1242 case T_OBJECT: // fall through 1243 case T_ARRAY: // fall through 1244 #ifdef _LP64 1245 __ movptr(dest->as_register(), from_addr); 1246 break; 1247 #endif // _L64 1248 case T_INT: 1249 __ movl(dest->as_register(), from_addr); 1250 break; 1251 1252 case T_LONG: { 1253 Register to_lo = dest->as_register_lo(); 1254 Register to_hi = dest->as_register_hi(); 1255 #ifdef _LP64 1256 __ movptr(to_lo, as_Address_lo(addr)); 1257 #else 1258 Register base = addr->base()->as_register(); 1259 Register index = noreg; 1260 if (addr->index()->is_register()) { 1261 index = addr->index()->as_register(); 1262 } 1263 if ((base == to_lo && index == to_hi) || 1264 (base == to_hi && index == to_lo)) { 1265 // addresses with 2 registers are only formed as a result of 1266 // array access so this code will never have to deal with 1267 // patches or null checks. 1268 assert(info == NULL && patch == NULL, "must be"); 1269 __ lea(to_hi, as_Address(addr)); 1270 __ movl(to_lo, Address(to_hi, 0)); 1271 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1272 } else if (base == to_lo || index == to_lo) { 1273 assert(base != to_hi, "can't be"); 1274 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1275 __ movl(to_hi, as_Address_hi(addr)); 1276 if (patch != NULL) { 1277 patching_epilog(patch, lir_patch_high, base, info); 1278 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1279 patch_code = lir_patch_low; 1280 } 1281 __ movl(to_lo, as_Address_lo(addr)); 1282 } else { 1283 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1284 __ movl(to_lo, as_Address_lo(addr)); 1285 if (patch != NULL) { 1286 patching_epilog(patch, lir_patch_low, base, info); 1287 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1288 patch_code = lir_patch_high; 1289 } 1290 __ movl(to_hi, as_Address_hi(addr)); 1291 } 1292 #endif // _LP64 1293 break; 1294 } 1295 1296 case T_BOOLEAN: // fall through 1297 case T_BYTE: { 1298 Register dest_reg = dest->as_register(); 1299 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1300 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1301 __ movsbl(dest_reg, from_addr); 1302 } else { 1303 __ movb(dest_reg, from_addr); 1304 __ shll(dest_reg, 24); 1305 __ sarl(dest_reg, 24); 1306 } 1307 break; 1308 } 1309 1310 case T_CHAR: { 1311 Register dest_reg = dest->as_register(); 1312 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1313 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1314 __ movzwl(dest_reg, from_addr); 1315 } else { 1316 __ movw(dest_reg, from_addr); 1317 } 1318 break; 1319 } 1320 1321 case T_SHORT: { 1322 Register dest_reg = dest->as_register(); 1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1324 __ movswl(dest_reg, from_addr); 1325 } else { 1326 __ movw(dest_reg, from_addr); 1327 __ shll(dest_reg, 16); 1328 __ sarl(dest_reg, 16); 1329 } 1330 break; 1331 } 1332 1333 default: 1334 ShouldNotReachHere(); 1335 } 1336 1337 if (patch != NULL) { 1338 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1339 } 1340 1341 if (type == T_ARRAY || type == T_OBJECT) { 1342 __ verify_oop(dest->as_register()); 1343 } 1344 } 1345 1346 1347 void LIR_Assembler::prefetchr(LIR_Opr src) { 1348 LIR_Address* addr = src->as_address_ptr(); 1349 Address from_addr = as_Address(addr); 1350 1351 if (VM_Version::supports_sse()) { 1352 switch (ReadPrefetchInstr) { 1353 case 0: 1354 __ prefetchnta(from_addr); break; 1355 case 1: 1356 __ prefetcht0(from_addr); break; 1357 case 2: 1358 __ prefetcht2(from_addr); break; 1359 default: 1360 ShouldNotReachHere(); break; 1361 } 1362 } else if (VM_Version::supports_3dnow()) { 1363 __ prefetchr(from_addr); 1364 } 1365 } 1366 1367 1368 void LIR_Assembler::prefetchw(LIR_Opr src) { 1369 LIR_Address* addr = src->as_address_ptr(); 1370 Address from_addr = as_Address(addr); 1371 1372 if (VM_Version::supports_sse()) { 1373 switch (AllocatePrefetchInstr) { 1374 case 0: 1375 __ prefetchnta(from_addr); break; 1376 case 1: 1377 __ prefetcht0(from_addr); break; 1378 case 2: 1379 __ prefetcht2(from_addr); break; 1380 case 3: 1381 __ prefetchw(from_addr); break; 1382 default: 1383 ShouldNotReachHere(); break; 1384 } 1385 } else if (VM_Version::supports_3dnow()) { 1386 __ prefetchw(from_addr); 1387 } 1388 } 1389 1390 1391 NEEDS_CLEANUP; // This could be static? 1392 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1393 int elem_size = type2aelembytes(type); 1394 switch (elem_size) { 1395 case 1: return Address::times_1; 1396 case 2: return Address::times_2; 1397 case 4: return Address::times_4; 1398 case 8: return Address::times_8; 1399 } 1400 ShouldNotReachHere(); 1401 return Address::no_scale; 1402 } 1403 1404 1405 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1406 switch (op->code()) { 1407 case lir_idiv: 1408 case lir_irem: 1409 arithmetic_idiv(op->code(), 1410 op->in_opr1(), 1411 op->in_opr2(), 1412 op->in_opr3(), 1413 op->result_opr(), 1414 op->info()); 1415 break; 1416 default: ShouldNotReachHere(); break; 1417 } 1418 } 1419 1420 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1421 #ifdef ASSERT 1422 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1423 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1424 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1425 #endif 1426 1427 if (op->cond() == lir_cond_always) { 1428 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1429 __ jmp (*(op->label())); 1430 } else { 1431 Assembler::Condition acond = Assembler::zero; 1432 if (op->code() == lir_cond_float_branch) { 1433 assert(op->ublock() != NULL, "must have unordered successor"); 1434 __ jcc(Assembler::parity, *(op->ublock()->label())); 1435 switch(op->cond()) { 1436 case lir_cond_equal: acond = Assembler::equal; break; 1437 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1438 case lir_cond_less: acond = Assembler::below; break; 1439 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1440 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1441 case lir_cond_greater: acond = Assembler::above; break; 1442 default: ShouldNotReachHere(); 1443 } 1444 } else { 1445 switch (op->cond()) { 1446 case lir_cond_equal: acond = Assembler::equal; break; 1447 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1448 case lir_cond_less: acond = Assembler::less; break; 1449 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1450 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1451 case lir_cond_greater: acond = Assembler::greater; break; 1452 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1453 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1454 default: ShouldNotReachHere(); 1455 } 1456 } 1457 __ jcc(acond,*(op->label())); 1458 } 1459 } 1460 1461 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1462 LIR_Opr src = op->in_opr(); 1463 LIR_Opr dest = op->result_opr(); 1464 1465 switch (op->bytecode()) { 1466 case Bytecodes::_i2l: 1467 #ifdef _LP64 1468 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1469 #else 1470 move_regs(src->as_register(), dest->as_register_lo()); 1471 move_regs(src->as_register(), dest->as_register_hi()); 1472 __ sarl(dest->as_register_hi(), 31); 1473 #endif // LP64 1474 break; 1475 1476 case Bytecodes::_l2i: 1477 move_regs(src->as_register_lo(), dest->as_register()); 1478 break; 1479 1480 case Bytecodes::_i2b: 1481 move_regs(src->as_register(), dest->as_register()); 1482 __ sign_extend_byte(dest->as_register()); 1483 break; 1484 1485 case Bytecodes::_i2c: 1486 move_regs(src->as_register(), dest->as_register()); 1487 __ andl(dest->as_register(), 0xFFFF); 1488 break; 1489 1490 case Bytecodes::_i2s: 1491 move_regs(src->as_register(), dest->as_register()); 1492 __ sign_extend_short(dest->as_register()); 1493 break; 1494 1495 1496 case Bytecodes::_f2d: 1497 case Bytecodes::_d2f: 1498 if (dest->is_single_xmm()) { 1499 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1500 } else if (dest->is_double_xmm()) { 1501 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1502 } else { 1503 assert(src->fpu() == dest->fpu(), "register must be equal"); 1504 // do nothing (float result is rounded later through spilling) 1505 } 1506 break; 1507 1508 case Bytecodes::_i2f: 1509 case Bytecodes::_i2d: 1510 if (dest->is_single_xmm()) { 1511 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1512 } else if (dest->is_double_xmm()) { 1513 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1514 } else { 1515 assert(dest->fpu() == 0, "result must be on TOS"); 1516 __ movl(Address(rsp, 0), src->as_register()); 1517 __ fild_s(Address(rsp, 0)); 1518 } 1519 break; 1520 1521 case Bytecodes::_f2i: 1522 case Bytecodes::_d2i: 1523 if (src->is_single_xmm()) { 1524 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1525 } else if (src->is_double_xmm()) { 1526 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1527 } else { 1528 assert(src->fpu() == 0, "input must be on TOS"); 1529 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1530 __ fist_s(Address(rsp, 0)); 1531 __ movl(dest->as_register(), Address(rsp, 0)); 1532 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1533 } 1534 1535 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1536 assert(op->stub() != NULL, "stub required"); 1537 __ cmpl(dest->as_register(), 0x80000000); 1538 __ jcc(Assembler::equal, *op->stub()->entry()); 1539 __ bind(*op->stub()->continuation()); 1540 break; 1541 1542 case Bytecodes::_l2f: 1543 case Bytecodes::_l2d: 1544 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1545 assert(dest->fpu() == 0, "result must be on TOS"); 1546 1547 __ movptr(Address(rsp, 0), src->as_register_lo()); 1548 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1549 __ fild_d(Address(rsp, 0)); 1550 // float result is rounded later through spilling 1551 break; 1552 1553 case Bytecodes::_f2l: 1554 case Bytecodes::_d2l: 1555 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1556 assert(src->fpu() == 0, "input must be on TOS"); 1557 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1558 1559 // instruction sequence too long to inline it here 1560 { 1561 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1562 } 1563 break; 1564 1565 default: ShouldNotReachHere(); 1566 } 1567 } 1568 1569 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1570 if (op->init_check()) { 1571 __ cmpl(Address(op->klass()->as_register(), 1572 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), 1573 instanceKlass::fully_initialized); 1574 add_debug_info_for_null_check_here(op->stub()->info()); 1575 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1576 } 1577 __ allocate_object(op->obj()->as_register(), 1578 op->tmp1()->as_register(), 1579 op->tmp2()->as_register(), 1580 op->header_size(), 1581 op->object_size(), 1582 op->klass()->as_register(), 1583 *op->stub()->entry()); 1584 __ bind(*op->stub()->continuation()); 1585 } 1586 1587 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1588 if (UseSlowPath || 1589 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1590 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1591 __ jmp(*op->stub()->entry()); 1592 } else { 1593 Register len = op->len()->as_register(); 1594 Register tmp1 = op->tmp1()->as_register(); 1595 Register tmp2 = op->tmp2()->as_register(); 1596 Register tmp3 = op->tmp3()->as_register(); 1597 if (len == tmp1) { 1598 tmp1 = tmp3; 1599 } else if (len == tmp2) { 1600 tmp2 = tmp3; 1601 } else if (len == tmp3) { 1602 // everything is ok 1603 } else { 1604 __ mov(tmp3, len); 1605 } 1606 __ allocate_array(op->obj()->as_register(), 1607 len, 1608 tmp1, 1609 tmp2, 1610 arrayOopDesc::header_size(op->type()), 1611 array_element_size(op->type()), 1612 op->klass()->as_register(), 1613 *op->stub()->entry()); 1614 } 1615 __ bind(*op->stub()->continuation()); 1616 } 1617 1618 void LIR_Assembler::type_profile_helper(Register mdo, 1619 ciMethodData *md, ciProfileData *data, 1620 Register recv, Label* update_done) { 1621 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1622 Label next_test; 1623 // See if the receiver is receiver[n]. 1624 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1625 __ jccb(Assembler::notEqual, next_test); 1626 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1627 __ addptr(data_addr, DataLayout::counter_increment); 1628 __ jmp(*update_done); 1629 __ bind(next_test); 1630 } 1631 1632 // Didn't find receiver; find next empty slot and fill it in 1633 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1634 Label next_test; 1635 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1636 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1637 __ jccb(Assembler::notEqual, next_test); 1638 __ movptr(recv_addr, recv); 1639 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1640 __ jmp(*update_done); 1641 __ bind(next_test); 1642 } 1643 } 1644 1645 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1646 // we always need a stub for the failure case. 1647 CodeStub* stub = op->stub(); 1648 Register obj = op->object()->as_register(); 1649 Register k_RInfo = op->tmp1()->as_register(); 1650 Register klass_RInfo = op->tmp2()->as_register(); 1651 Register dst = op->result_opr()->as_register(); 1652 ciKlass* k = op->klass(); 1653 Register Rtmp1 = noreg; 1654 1655 // check if it needs to be profiled 1656 ciMethodData* md; 1657 ciProfileData* data; 1658 1659 if (op->should_profile()) { 1660 ciMethod* method = op->profiled_method(); 1661 assert(method != NULL, "Should have method"); 1662 int bci = op->profiled_bci(); 1663 md = method->method_data(); 1664 if (md == NULL) { 1665 bailout("out of memory building methodDataOop"); 1666 return; 1667 } 1668 data = md->bci_to_data(bci); 1669 assert(data != NULL, "need data for type check"); 1670 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1671 } 1672 Label profile_cast_success, profile_cast_failure; 1673 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1674 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1675 1676 if (obj == k_RInfo) { 1677 k_RInfo = dst; 1678 } else if (obj == klass_RInfo) { 1679 klass_RInfo = dst; 1680 } 1681 if (k->is_loaded()) { 1682 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1683 } else { 1684 Rtmp1 = op->tmp3()->as_register(); 1685 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1686 } 1687 1688 assert_different_registers(obj, k_RInfo, klass_RInfo); 1689 if (!k->is_loaded()) { 1690 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1691 } else { 1692 #ifdef _LP64 1693 __ movoop(k_RInfo, k->constant_encoding()); 1694 #endif // _LP64 1695 } 1696 assert(obj != k_RInfo, "must be different"); 1697 1698 __ cmpptr(obj, (int32_t)NULL_WORD); 1699 if (op->should_profile()) { 1700 Label not_null; 1701 __ jccb(Assembler::notEqual, not_null); 1702 // Object is null; update MDO and exit 1703 Register mdo = klass_RInfo; 1704 __ movoop(mdo, md->constant_encoding()); 1705 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1706 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1707 __ orl(data_addr, header_bits); 1708 __ jmp(*obj_is_null); 1709 __ bind(not_null); 1710 } else { 1711 __ jcc(Assembler::equal, *obj_is_null); 1712 } 1713 __ verify_oop(obj); 1714 1715 if (op->fast_check()) { 1716 // get object class 1717 // not a safepoint as obj null check happens earlier 1718 if (k->is_loaded()) { 1719 #ifdef _LP64 1720 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1721 #else 1722 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1723 #endif // _LP64 1724 } else { 1725 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1726 } 1727 __ jcc(Assembler::notEqual, *failure_target); 1728 // successful cast, fall through to profile or jump 1729 } else { 1730 // get object class 1731 // not a safepoint as obj null check happens earlier 1732 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1733 if (k->is_loaded()) { 1734 // See if we get an immediate positive hit 1735 #ifdef _LP64 1736 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1737 #else 1738 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1739 #endif // _LP64 1740 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { 1741 __ jcc(Assembler::notEqual, *failure_target); 1742 // successful cast, fall through to profile or jump 1743 } else { 1744 // See if we get an immediate positive hit 1745 __ jcc(Assembler::equal, *success_target); 1746 // check for self 1747 #ifdef _LP64 1748 __ cmpptr(klass_RInfo, k_RInfo); 1749 #else 1750 __ cmpoop(klass_RInfo, k->constant_encoding()); 1751 #endif // _LP64 1752 __ jcc(Assembler::equal, *success_target); 1753 1754 __ push(klass_RInfo); 1755 #ifdef _LP64 1756 __ push(k_RInfo); 1757 #else 1758 __ pushoop(k->constant_encoding()); 1759 #endif // _LP64 1760 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1761 __ pop(klass_RInfo); 1762 __ pop(klass_RInfo); 1763 // result is a boolean 1764 __ cmpl(klass_RInfo, 0); 1765 __ jcc(Assembler::equal, *failure_target); 1766 // successful cast, fall through to profile or jump 1767 } 1768 } else { 1769 // perform the fast part of the checking logic 1770 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1771 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1772 __ push(klass_RInfo); 1773 __ push(k_RInfo); 1774 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1775 __ pop(klass_RInfo); 1776 __ pop(k_RInfo); 1777 // result is a boolean 1778 __ cmpl(k_RInfo, 0); 1779 __ jcc(Assembler::equal, *failure_target); 1780 // successful cast, fall through to profile or jump 1781 } 1782 } 1783 if (op->should_profile()) { 1784 Register mdo = klass_RInfo, recv = k_RInfo; 1785 __ bind(profile_cast_success); 1786 __ movoop(mdo, md->constant_encoding()); 1787 __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes())); 1788 Label update_done; 1789 type_profile_helper(mdo, md, data, recv, success); 1790 __ jmp(*success); 1791 1792 __ bind(profile_cast_failure); 1793 __ movoop(mdo, md->constant_encoding()); 1794 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1795 __ subptr(counter_addr, DataLayout::counter_increment); 1796 __ jmp(*failure); 1797 } 1798 __ jmp(*success); 1799 } 1800 1801 1802 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1803 LIR_Code code = op->code(); 1804 if (code == lir_store_check) { 1805 Register value = op->object()->as_register(); 1806 Register array = op->array()->as_register(); 1807 Register k_RInfo = op->tmp1()->as_register(); 1808 Register klass_RInfo = op->tmp2()->as_register(); 1809 Register Rtmp1 = op->tmp3()->as_register(); 1810 1811 CodeStub* stub = op->stub(); 1812 1813 // check if it needs to be profiled 1814 ciMethodData* md; 1815 ciProfileData* data; 1816 1817 if (op->should_profile()) { 1818 ciMethod* method = op->profiled_method(); 1819 assert(method != NULL, "Should have method"); 1820 int bci = op->profiled_bci(); 1821 md = method->method_data(); 1822 if (md == NULL) { 1823 bailout("out of memory building methodDataOop"); 1824 return; 1825 } 1826 data = md->bci_to_data(bci); 1827 assert(data != NULL, "need data for type check"); 1828 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1829 } 1830 Label profile_cast_success, profile_cast_failure, done; 1831 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1832 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1833 1834 __ cmpptr(value, (int32_t)NULL_WORD); 1835 if (op->should_profile()) { 1836 Label not_null; 1837 __ jccb(Assembler::notEqual, not_null); 1838 // Object is null; update MDO and exit 1839 Register mdo = klass_RInfo; 1840 __ movoop(mdo, md->constant_encoding()); 1841 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1842 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1843 __ orl(data_addr, header_bits); 1844 __ jmp(done); 1845 __ bind(not_null); 1846 } else { 1847 __ jcc(Assembler::equal, done); 1848 } 1849 1850 add_debug_info_for_null_check_here(op->info_for_exception()); 1851 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); 1852 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); 1853 1854 // get instance klass 1855 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); 1856 // perform the fast part of the checking logic 1857 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1858 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1859 __ push(klass_RInfo); 1860 __ push(k_RInfo); 1861 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1862 __ pop(klass_RInfo); 1863 __ pop(k_RInfo); 1864 // result is a boolean 1865 __ cmpl(k_RInfo, 0); 1866 __ jcc(Assembler::equal, *failure_target); 1867 // fall through to the success case 1868 1869 if (op->should_profile()) { 1870 Register mdo = klass_RInfo, recv = k_RInfo; 1871 __ bind(profile_cast_success); 1872 __ movoop(mdo, md->constant_encoding()); 1873 __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes())); 1874 Label update_done; 1875 type_profile_helper(mdo, md, data, recv, &done); 1876 __ jmpb(done); 1877 1878 __ bind(profile_cast_failure); 1879 __ movoop(mdo, md->constant_encoding()); 1880 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1881 __ subptr(counter_addr, DataLayout::counter_increment); 1882 __ jmp(*stub->entry()); 1883 } 1884 1885 __ bind(done); 1886 } else 1887 if (code == lir_checkcast) { 1888 Register obj = op->object()->as_register(); 1889 Register dst = op->result_opr()->as_register(); 1890 Label success; 1891 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1892 __ bind(success); 1893 if (dst != obj) { 1894 __ mov(dst, obj); 1895 } 1896 } else 1897 if (code == lir_instanceof) { 1898 Register obj = op->object()->as_register(); 1899 Register dst = op->result_opr()->as_register(); 1900 Label success, failure, done; 1901 emit_typecheck_helper(op, &success, &failure, &failure); 1902 __ bind(failure); 1903 __ xorptr(dst, dst); 1904 __ jmpb(done); 1905 __ bind(success); 1906 __ movptr(dst, 1); 1907 __ bind(done); 1908 } else { 1909 ShouldNotReachHere(); 1910 } 1911 1912 } 1913 1914 1915 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1916 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1917 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1918 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1919 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1920 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1921 Register addr = op->addr()->as_register(); 1922 if (os::is_MP()) { 1923 __ lock(); 1924 } 1925 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1926 1927 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1928 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1929 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1930 Register newval = op->new_value()->as_register(); 1931 Register cmpval = op->cmp_value()->as_register(); 1932 assert(cmpval == rax, "wrong register"); 1933 assert(newval != NULL, "new val must be register"); 1934 assert(cmpval != newval, "cmp and new values must be in different registers"); 1935 assert(cmpval != addr, "cmp and addr must be in different registers"); 1936 assert(newval != addr, "new value and addr must be in different registers"); 1937 if (os::is_MP()) { 1938 __ lock(); 1939 } 1940 if ( op->code() == lir_cas_obj) { 1941 __ cmpxchgptr(newval, Address(addr, 0)); 1942 } else if (op->code() == lir_cas_int) { 1943 __ cmpxchgl(newval, Address(addr, 0)); 1944 } 1945 #ifdef _LP64 1946 } else if (op->code() == lir_cas_long) { 1947 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1948 Register newval = op->new_value()->as_register_lo(); 1949 Register cmpval = op->cmp_value()->as_register_lo(); 1950 assert(cmpval == rax, "wrong register"); 1951 assert(newval != NULL, "new val must be register"); 1952 assert(cmpval != newval, "cmp and new values must be in different registers"); 1953 assert(cmpval != addr, "cmp and addr must be in different registers"); 1954 assert(newval != addr, "new value and addr must be in different registers"); 1955 if (os::is_MP()) { 1956 __ lock(); 1957 } 1958 __ cmpxchgq(newval, Address(addr, 0)); 1959 #endif // _LP64 1960 } else { 1961 Unimplemented(); 1962 } 1963 } 1964 1965 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1966 Assembler::Condition acond, ncond; 1967 switch (condition) { 1968 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1969 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1970 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1971 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1972 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1973 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1974 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1975 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1976 default: ShouldNotReachHere(); 1977 } 1978 1979 if (opr1->is_cpu_register()) { 1980 reg2reg(opr1, result); 1981 } else if (opr1->is_stack()) { 1982 stack2reg(opr1, result, result->type()); 1983 } else if (opr1->is_constant()) { 1984 const2reg(opr1, result, lir_patch_none, NULL); 1985 } else { 1986 ShouldNotReachHere(); 1987 } 1988 1989 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1990 // optimized version that does not require a branch 1991 if (opr2->is_single_cpu()) { 1992 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1993 __ cmov(ncond, result->as_register(), opr2->as_register()); 1994 } else if (opr2->is_double_cpu()) { 1995 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1996 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1997 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 1998 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 1999 } else if (opr2->is_single_stack()) { 2000 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2001 } else if (opr2->is_double_stack()) { 2002 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2003 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2004 } else { 2005 ShouldNotReachHere(); 2006 } 2007 2008 } else { 2009 Label skip; 2010 __ jcc (acond, skip); 2011 if (opr2->is_cpu_register()) { 2012 reg2reg(opr2, result); 2013 } else if (opr2->is_stack()) { 2014 stack2reg(opr2, result, result->type()); 2015 } else if (opr2->is_constant()) { 2016 const2reg(opr2, result, lir_patch_none, NULL); 2017 } else { 2018 ShouldNotReachHere(); 2019 } 2020 __ bind(skip); 2021 } 2022 } 2023 2024 2025 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2026 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2027 2028 if (left->is_single_cpu()) { 2029 assert(left == dest, "left and dest must be equal"); 2030 Register lreg = left->as_register(); 2031 2032 if (right->is_single_cpu()) { 2033 // cpu register - cpu register 2034 Register rreg = right->as_register(); 2035 switch (code) { 2036 case lir_add: __ addl (lreg, rreg); break; 2037 case lir_sub: __ subl (lreg, rreg); break; 2038 case lir_mul: __ imull(lreg, rreg); break; 2039 default: ShouldNotReachHere(); 2040 } 2041 2042 } else if (right->is_stack()) { 2043 // cpu register - stack 2044 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2045 switch (code) { 2046 case lir_add: __ addl(lreg, raddr); break; 2047 case lir_sub: __ subl(lreg, raddr); break; 2048 default: ShouldNotReachHere(); 2049 } 2050 2051 } else if (right->is_constant()) { 2052 // cpu register - constant 2053 jint c = right->as_constant_ptr()->as_jint(); 2054 switch (code) { 2055 case lir_add: { 2056 __ incrementl(lreg, c); 2057 break; 2058 } 2059 case lir_sub: { 2060 __ decrementl(lreg, c); 2061 break; 2062 } 2063 default: ShouldNotReachHere(); 2064 } 2065 2066 } else { 2067 ShouldNotReachHere(); 2068 } 2069 2070 } else if (left->is_double_cpu()) { 2071 assert(left == dest, "left and dest must be equal"); 2072 Register lreg_lo = left->as_register_lo(); 2073 Register lreg_hi = left->as_register_hi(); 2074 2075 if (right->is_double_cpu()) { 2076 // cpu register - cpu register 2077 Register rreg_lo = right->as_register_lo(); 2078 Register rreg_hi = right->as_register_hi(); 2079 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2080 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2081 switch (code) { 2082 case lir_add: 2083 __ addptr(lreg_lo, rreg_lo); 2084 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2085 break; 2086 case lir_sub: 2087 __ subptr(lreg_lo, rreg_lo); 2088 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2089 break; 2090 case lir_mul: 2091 #ifdef _LP64 2092 __ imulq(lreg_lo, rreg_lo); 2093 #else 2094 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2095 __ imull(lreg_hi, rreg_lo); 2096 __ imull(rreg_hi, lreg_lo); 2097 __ addl (rreg_hi, lreg_hi); 2098 __ mull (rreg_lo); 2099 __ addl (lreg_hi, rreg_hi); 2100 #endif // _LP64 2101 break; 2102 default: 2103 ShouldNotReachHere(); 2104 } 2105 2106 } else if (right->is_constant()) { 2107 // cpu register - constant 2108 #ifdef _LP64 2109 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2110 __ movptr(r10, (intptr_t) c); 2111 switch (code) { 2112 case lir_add: 2113 __ addptr(lreg_lo, r10); 2114 break; 2115 case lir_sub: 2116 __ subptr(lreg_lo, r10); 2117 break; 2118 default: 2119 ShouldNotReachHere(); 2120 } 2121 #else 2122 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2123 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2124 switch (code) { 2125 case lir_add: 2126 __ addptr(lreg_lo, c_lo); 2127 __ adcl(lreg_hi, c_hi); 2128 break; 2129 case lir_sub: 2130 __ subptr(lreg_lo, c_lo); 2131 __ sbbl(lreg_hi, c_hi); 2132 break; 2133 default: 2134 ShouldNotReachHere(); 2135 } 2136 #endif // _LP64 2137 2138 } else { 2139 ShouldNotReachHere(); 2140 } 2141 2142 } else if (left->is_single_xmm()) { 2143 assert(left == dest, "left and dest must be equal"); 2144 XMMRegister lreg = left->as_xmm_float_reg(); 2145 2146 if (right->is_single_xmm()) { 2147 XMMRegister rreg = right->as_xmm_float_reg(); 2148 switch (code) { 2149 case lir_add: __ addss(lreg, rreg); break; 2150 case lir_sub: __ subss(lreg, rreg); break; 2151 case lir_mul_strictfp: // fall through 2152 case lir_mul: __ mulss(lreg, rreg); break; 2153 case lir_div_strictfp: // fall through 2154 case lir_div: __ divss(lreg, rreg); break; 2155 default: ShouldNotReachHere(); 2156 } 2157 } else { 2158 Address raddr; 2159 if (right->is_single_stack()) { 2160 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2161 } else if (right->is_constant()) { 2162 // hack for now 2163 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2164 } else { 2165 ShouldNotReachHere(); 2166 } 2167 switch (code) { 2168 case lir_add: __ addss(lreg, raddr); break; 2169 case lir_sub: __ subss(lreg, raddr); break; 2170 case lir_mul_strictfp: // fall through 2171 case lir_mul: __ mulss(lreg, raddr); break; 2172 case lir_div_strictfp: // fall through 2173 case lir_div: __ divss(lreg, raddr); break; 2174 default: ShouldNotReachHere(); 2175 } 2176 } 2177 2178 } else if (left->is_double_xmm()) { 2179 assert(left == dest, "left and dest must be equal"); 2180 2181 XMMRegister lreg = left->as_xmm_double_reg(); 2182 if (right->is_double_xmm()) { 2183 XMMRegister rreg = right->as_xmm_double_reg(); 2184 switch (code) { 2185 case lir_add: __ addsd(lreg, rreg); break; 2186 case lir_sub: __ subsd(lreg, rreg); break; 2187 case lir_mul_strictfp: // fall through 2188 case lir_mul: __ mulsd(lreg, rreg); break; 2189 case lir_div_strictfp: // fall through 2190 case lir_div: __ divsd(lreg, rreg); break; 2191 default: ShouldNotReachHere(); 2192 } 2193 } else { 2194 Address raddr; 2195 if (right->is_double_stack()) { 2196 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2197 } else if (right->is_constant()) { 2198 // hack for now 2199 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2200 } else { 2201 ShouldNotReachHere(); 2202 } 2203 switch (code) { 2204 case lir_add: __ addsd(lreg, raddr); break; 2205 case lir_sub: __ subsd(lreg, raddr); break; 2206 case lir_mul_strictfp: // fall through 2207 case lir_mul: __ mulsd(lreg, raddr); break; 2208 case lir_div_strictfp: // fall through 2209 case lir_div: __ divsd(lreg, raddr); break; 2210 default: ShouldNotReachHere(); 2211 } 2212 } 2213 2214 } else if (left->is_single_fpu()) { 2215 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2216 2217 if (right->is_single_fpu()) { 2218 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2219 2220 } else { 2221 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2222 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2223 2224 Address raddr; 2225 if (right->is_single_stack()) { 2226 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2227 } else if (right->is_constant()) { 2228 address const_addr = float_constant(right->as_jfloat()); 2229 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2230 // hack for now 2231 raddr = __ as_Address(InternalAddress(const_addr)); 2232 } else { 2233 ShouldNotReachHere(); 2234 } 2235 2236 switch (code) { 2237 case lir_add: __ fadd_s(raddr); break; 2238 case lir_sub: __ fsub_s(raddr); break; 2239 case lir_mul_strictfp: // fall through 2240 case lir_mul: __ fmul_s(raddr); break; 2241 case lir_div_strictfp: // fall through 2242 case lir_div: __ fdiv_s(raddr); break; 2243 default: ShouldNotReachHere(); 2244 } 2245 } 2246 2247 } else if (left->is_double_fpu()) { 2248 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2249 2250 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2251 // Double values require special handling for strictfp mul/div on x86 2252 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2253 __ fmulp(left->fpu_regnrLo() + 1); 2254 } 2255 2256 if (right->is_double_fpu()) { 2257 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2258 2259 } else { 2260 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2261 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2262 2263 Address raddr; 2264 if (right->is_double_stack()) { 2265 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2266 } else if (right->is_constant()) { 2267 // hack for now 2268 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2269 } else { 2270 ShouldNotReachHere(); 2271 } 2272 2273 switch (code) { 2274 case lir_add: __ fadd_d(raddr); break; 2275 case lir_sub: __ fsub_d(raddr); break; 2276 case lir_mul_strictfp: // fall through 2277 case lir_mul: __ fmul_d(raddr); break; 2278 case lir_div_strictfp: // fall through 2279 case lir_div: __ fdiv_d(raddr); break; 2280 default: ShouldNotReachHere(); 2281 } 2282 } 2283 2284 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2285 // Double values require special handling for strictfp mul/div on x86 2286 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2287 __ fmulp(dest->fpu_regnrLo() + 1); 2288 } 2289 2290 } else if (left->is_single_stack() || left->is_address()) { 2291 assert(left == dest, "left and dest must be equal"); 2292 2293 Address laddr; 2294 if (left->is_single_stack()) { 2295 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2296 } else if (left->is_address()) { 2297 laddr = as_Address(left->as_address_ptr()); 2298 } else { 2299 ShouldNotReachHere(); 2300 } 2301 2302 if (right->is_single_cpu()) { 2303 Register rreg = right->as_register(); 2304 switch (code) { 2305 case lir_add: __ addl(laddr, rreg); break; 2306 case lir_sub: __ subl(laddr, rreg); break; 2307 default: ShouldNotReachHere(); 2308 } 2309 } else if (right->is_constant()) { 2310 jint c = right->as_constant_ptr()->as_jint(); 2311 switch (code) { 2312 case lir_add: { 2313 __ incrementl(laddr, c); 2314 break; 2315 } 2316 case lir_sub: { 2317 __ decrementl(laddr, c); 2318 break; 2319 } 2320 default: ShouldNotReachHere(); 2321 } 2322 } else { 2323 ShouldNotReachHere(); 2324 } 2325 2326 } else { 2327 ShouldNotReachHere(); 2328 } 2329 } 2330 2331 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2332 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2333 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2334 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2335 2336 bool left_is_tos = (left_index == 0); 2337 bool dest_is_tos = (dest_index == 0); 2338 int non_tos_index = (left_is_tos ? right_index : left_index); 2339 2340 switch (code) { 2341 case lir_add: 2342 if (pop_fpu_stack) __ faddp(non_tos_index); 2343 else if (dest_is_tos) __ fadd (non_tos_index); 2344 else __ fadda(non_tos_index); 2345 break; 2346 2347 case lir_sub: 2348 if (left_is_tos) { 2349 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2350 else if (dest_is_tos) __ fsub (non_tos_index); 2351 else __ fsubra(non_tos_index); 2352 } else { 2353 if (pop_fpu_stack) __ fsubp (non_tos_index); 2354 else if (dest_is_tos) __ fsubr (non_tos_index); 2355 else __ fsuba (non_tos_index); 2356 } 2357 break; 2358 2359 case lir_mul_strictfp: // fall through 2360 case lir_mul: 2361 if (pop_fpu_stack) __ fmulp(non_tos_index); 2362 else if (dest_is_tos) __ fmul (non_tos_index); 2363 else __ fmula(non_tos_index); 2364 break; 2365 2366 case lir_div_strictfp: // fall through 2367 case lir_div: 2368 if (left_is_tos) { 2369 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2370 else if (dest_is_tos) __ fdiv (non_tos_index); 2371 else __ fdivra(non_tos_index); 2372 } else { 2373 if (pop_fpu_stack) __ fdivp (non_tos_index); 2374 else if (dest_is_tos) __ fdivr (non_tos_index); 2375 else __ fdiva (non_tos_index); 2376 } 2377 break; 2378 2379 case lir_rem: 2380 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2381 __ fremr(noreg); 2382 break; 2383 2384 default: 2385 ShouldNotReachHere(); 2386 } 2387 } 2388 2389 2390 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2391 if (value->is_double_xmm()) { 2392 switch(code) { 2393 case lir_abs : 2394 { 2395 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2396 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2397 } 2398 __ andpd(dest->as_xmm_double_reg(), 2399 ExternalAddress((address)double_signmask_pool)); 2400 } 2401 break; 2402 2403 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2404 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2405 default : ShouldNotReachHere(); 2406 } 2407 2408 } else if (value->is_double_fpu()) { 2409 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2410 switch(code) { 2411 case lir_log : __ flog() ; break; 2412 case lir_log10 : __ flog10() ; break; 2413 case lir_abs : __ fabs() ; break; 2414 case lir_sqrt : __ fsqrt(); break; 2415 case lir_sin : 2416 // Should consider not saving rbx, if not necessary 2417 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2418 break; 2419 case lir_cos : 2420 // Should consider not saving rbx, if not necessary 2421 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2422 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2423 break; 2424 case lir_tan : 2425 // Should consider not saving rbx, if not necessary 2426 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2427 break; 2428 default : ShouldNotReachHere(); 2429 } 2430 } else { 2431 Unimplemented(); 2432 } 2433 } 2434 2435 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2436 // assert(left->destroys_register(), "check"); 2437 if (left->is_single_cpu()) { 2438 Register reg = left->as_register(); 2439 if (right->is_constant()) { 2440 int val = right->as_constant_ptr()->as_jint(); 2441 switch (code) { 2442 case lir_logic_and: __ andl (reg, val); break; 2443 case lir_logic_or: __ orl (reg, val); break; 2444 case lir_logic_xor: __ xorl (reg, val); break; 2445 default: ShouldNotReachHere(); 2446 } 2447 } else if (right->is_stack()) { 2448 // added support for stack operands 2449 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2450 switch (code) { 2451 case lir_logic_and: __ andl (reg, raddr); break; 2452 case lir_logic_or: __ orl (reg, raddr); break; 2453 case lir_logic_xor: __ xorl (reg, raddr); break; 2454 default: ShouldNotReachHere(); 2455 } 2456 } else { 2457 Register rright = right->as_register(); 2458 switch (code) { 2459 case lir_logic_and: __ andptr (reg, rright); break; 2460 case lir_logic_or : __ orptr (reg, rright); break; 2461 case lir_logic_xor: __ xorptr (reg, rright); break; 2462 default: ShouldNotReachHere(); 2463 } 2464 } 2465 move_regs(reg, dst->as_register()); 2466 } else { 2467 Register l_lo = left->as_register_lo(); 2468 Register l_hi = left->as_register_hi(); 2469 if (right->is_constant()) { 2470 #ifdef _LP64 2471 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2472 switch (code) { 2473 case lir_logic_and: 2474 __ andq(l_lo, rscratch1); 2475 break; 2476 case lir_logic_or: 2477 __ orq(l_lo, rscratch1); 2478 break; 2479 case lir_logic_xor: 2480 __ xorq(l_lo, rscratch1); 2481 break; 2482 default: ShouldNotReachHere(); 2483 } 2484 #else 2485 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2486 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2487 switch (code) { 2488 case lir_logic_and: 2489 __ andl(l_lo, r_lo); 2490 __ andl(l_hi, r_hi); 2491 break; 2492 case lir_logic_or: 2493 __ orl(l_lo, r_lo); 2494 __ orl(l_hi, r_hi); 2495 break; 2496 case lir_logic_xor: 2497 __ xorl(l_lo, r_lo); 2498 __ xorl(l_hi, r_hi); 2499 break; 2500 default: ShouldNotReachHere(); 2501 } 2502 #endif // _LP64 2503 } else { 2504 #ifdef _LP64 2505 Register r_lo; 2506 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2507 r_lo = right->as_register(); 2508 } else { 2509 r_lo = right->as_register_lo(); 2510 } 2511 #else 2512 Register r_lo = right->as_register_lo(); 2513 Register r_hi = right->as_register_hi(); 2514 assert(l_lo != r_hi, "overwriting registers"); 2515 #endif 2516 switch (code) { 2517 case lir_logic_and: 2518 __ andptr(l_lo, r_lo); 2519 NOT_LP64(__ andptr(l_hi, r_hi);) 2520 break; 2521 case lir_logic_or: 2522 __ orptr(l_lo, r_lo); 2523 NOT_LP64(__ orptr(l_hi, r_hi);) 2524 break; 2525 case lir_logic_xor: 2526 __ xorptr(l_lo, r_lo); 2527 NOT_LP64(__ xorptr(l_hi, r_hi);) 2528 break; 2529 default: ShouldNotReachHere(); 2530 } 2531 } 2532 2533 Register dst_lo = dst->as_register_lo(); 2534 Register dst_hi = dst->as_register_hi(); 2535 2536 #ifdef _LP64 2537 move_regs(l_lo, dst_lo); 2538 #else 2539 if (dst_lo == l_hi) { 2540 assert(dst_hi != l_lo, "overwriting registers"); 2541 move_regs(l_hi, dst_hi); 2542 move_regs(l_lo, dst_lo); 2543 } else { 2544 assert(dst_lo != l_hi, "overwriting registers"); 2545 move_regs(l_lo, dst_lo); 2546 move_regs(l_hi, dst_hi); 2547 } 2548 #endif // _LP64 2549 } 2550 } 2551 2552 2553 // we assume that rax, and rdx can be overwritten 2554 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2555 2556 assert(left->is_single_cpu(), "left must be register"); 2557 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2558 assert(result->is_single_cpu(), "result must be register"); 2559 2560 // assert(left->destroys_register(), "check"); 2561 // assert(right->destroys_register(), "check"); 2562 2563 Register lreg = left->as_register(); 2564 Register dreg = result->as_register(); 2565 2566 if (right->is_constant()) { 2567 int divisor = right->as_constant_ptr()->as_jint(); 2568 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2569 if (code == lir_idiv) { 2570 assert(lreg == rax, "must be rax,"); 2571 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2572 __ cdql(); // sign extend into rdx:rax 2573 if (divisor == 2) { 2574 __ subl(lreg, rdx); 2575 } else { 2576 __ andl(rdx, divisor - 1); 2577 __ addl(lreg, rdx); 2578 } 2579 __ sarl(lreg, log2_intptr(divisor)); 2580 move_regs(lreg, dreg); 2581 } else if (code == lir_irem) { 2582 Label done; 2583 __ mov(dreg, lreg); 2584 __ andl(dreg, 0x80000000 | (divisor - 1)); 2585 __ jcc(Assembler::positive, done); 2586 __ decrement(dreg); 2587 __ orl(dreg, ~(divisor - 1)); 2588 __ increment(dreg); 2589 __ bind(done); 2590 } else { 2591 ShouldNotReachHere(); 2592 } 2593 } else { 2594 Register rreg = right->as_register(); 2595 assert(lreg == rax, "left register must be rax,"); 2596 assert(rreg != rdx, "right register must not be rdx"); 2597 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2598 2599 move_regs(lreg, rax); 2600 2601 int idivl_offset = __ corrected_idivl(rreg); 2602 add_debug_info_for_div0(idivl_offset, info); 2603 if (code == lir_irem) { 2604 move_regs(rdx, dreg); // result is in rdx 2605 } else { 2606 move_regs(rax, dreg); 2607 } 2608 } 2609 } 2610 2611 2612 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2613 if (opr1->is_single_cpu()) { 2614 Register reg1 = opr1->as_register(); 2615 if (opr2->is_single_cpu()) { 2616 // cpu register - cpu register 2617 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2618 __ cmpptr(reg1, opr2->as_register()); 2619 } else { 2620 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2621 __ cmpl(reg1, opr2->as_register()); 2622 } 2623 } else if (opr2->is_stack()) { 2624 // cpu register - stack 2625 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2626 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2627 } else { 2628 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2629 } 2630 } else if (opr2->is_constant()) { 2631 // cpu register - constant 2632 LIR_Const* c = opr2->as_constant_ptr(); 2633 if (c->type() == T_INT) { 2634 __ cmpl(reg1, c->as_jint()); 2635 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2636 // In 64bit oops are single register 2637 jobject o = c->as_jobject(); 2638 if (o == NULL) { 2639 __ cmpptr(reg1, (int32_t)NULL_WORD); 2640 } else { 2641 #ifdef _LP64 2642 __ movoop(rscratch1, o); 2643 __ cmpptr(reg1, rscratch1); 2644 #else 2645 __ cmpoop(reg1, c->as_jobject()); 2646 #endif // _LP64 2647 } 2648 } else { 2649 ShouldNotReachHere(); 2650 } 2651 // cpu register - address 2652 } else if (opr2->is_address()) { 2653 if (op->info() != NULL) { 2654 add_debug_info_for_null_check_here(op->info()); 2655 } 2656 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2657 } else { 2658 ShouldNotReachHere(); 2659 } 2660 2661 } else if(opr1->is_double_cpu()) { 2662 Register xlo = opr1->as_register_lo(); 2663 Register xhi = opr1->as_register_hi(); 2664 if (opr2->is_double_cpu()) { 2665 #ifdef _LP64 2666 __ cmpptr(xlo, opr2->as_register_lo()); 2667 #else 2668 // cpu register - cpu register 2669 Register ylo = opr2->as_register_lo(); 2670 Register yhi = opr2->as_register_hi(); 2671 __ subl(xlo, ylo); 2672 __ sbbl(xhi, yhi); 2673 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2674 __ orl(xhi, xlo); 2675 } 2676 #endif // _LP64 2677 } else if (opr2->is_constant()) { 2678 // cpu register - constant 0 2679 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2680 #ifdef _LP64 2681 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2682 #else 2683 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2684 __ orl(xhi, xlo); 2685 #endif // _LP64 2686 } else { 2687 ShouldNotReachHere(); 2688 } 2689 2690 } else if (opr1->is_single_xmm()) { 2691 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2692 if (opr2->is_single_xmm()) { 2693 // xmm register - xmm register 2694 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2695 } else if (opr2->is_stack()) { 2696 // xmm register - stack 2697 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2698 } else if (opr2->is_constant()) { 2699 // xmm register - constant 2700 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2701 } else if (opr2->is_address()) { 2702 // xmm register - address 2703 if (op->info() != NULL) { 2704 add_debug_info_for_null_check_here(op->info()); 2705 } 2706 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2707 } else { 2708 ShouldNotReachHere(); 2709 } 2710 2711 } else if (opr1->is_double_xmm()) { 2712 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2713 if (opr2->is_double_xmm()) { 2714 // xmm register - xmm register 2715 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2716 } else if (opr2->is_stack()) { 2717 // xmm register - stack 2718 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2719 } else if (opr2->is_constant()) { 2720 // xmm register - constant 2721 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2722 } else if (opr2->is_address()) { 2723 // xmm register - address 2724 if (op->info() != NULL) { 2725 add_debug_info_for_null_check_here(op->info()); 2726 } 2727 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2728 } else { 2729 ShouldNotReachHere(); 2730 } 2731 2732 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2733 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2734 assert(opr2->is_fpu_register(), "both must be registers"); 2735 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2736 2737 } else if (opr1->is_address() && opr2->is_constant()) { 2738 LIR_Const* c = opr2->as_constant_ptr(); 2739 #ifdef _LP64 2740 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2741 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2742 __ movoop(rscratch1, c->as_jobject()); 2743 } 2744 #endif // LP64 2745 if (op->info() != NULL) { 2746 add_debug_info_for_null_check_here(op->info()); 2747 } 2748 // special case: address - constant 2749 LIR_Address* addr = opr1->as_address_ptr(); 2750 if (c->type() == T_INT) { 2751 __ cmpl(as_Address(addr), c->as_jint()); 2752 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2753 #ifdef _LP64 2754 // %%% Make this explode if addr isn't reachable until we figure out a 2755 // better strategy by giving noreg as the temp for as_Address 2756 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2757 #else 2758 __ cmpoop(as_Address(addr), c->as_jobject()); 2759 #endif // _LP64 2760 } else { 2761 ShouldNotReachHere(); 2762 } 2763 2764 } else { 2765 ShouldNotReachHere(); 2766 } 2767 } 2768 2769 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2770 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2771 if (left->is_single_xmm()) { 2772 assert(right->is_single_xmm(), "must match"); 2773 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2774 } else if (left->is_double_xmm()) { 2775 assert(right->is_double_xmm(), "must match"); 2776 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2777 2778 } else { 2779 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2780 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2781 2782 assert(left->fpu() == 0, "left must be on TOS"); 2783 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2784 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2785 } 2786 } else { 2787 assert(code == lir_cmp_l2i, "check"); 2788 #ifdef _LP64 2789 Label done; 2790 Register dest = dst->as_register(); 2791 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2792 __ movl(dest, -1); 2793 __ jccb(Assembler::less, done); 2794 __ set_byte_if_not_zero(dest); 2795 __ movzbl(dest, dest); 2796 __ bind(done); 2797 #else 2798 __ lcmp2int(left->as_register_hi(), 2799 left->as_register_lo(), 2800 right->as_register_hi(), 2801 right->as_register_lo()); 2802 move_regs(left->as_register_hi(), dst->as_register()); 2803 #endif // _LP64 2804 } 2805 } 2806 2807 2808 void LIR_Assembler::align_call(LIR_Code code) { 2809 if (os::is_MP()) { 2810 // make sure that the displacement word of the call ends up word aligned 2811 int offset = __ offset(); 2812 switch (code) { 2813 case lir_static_call: 2814 case lir_optvirtual_call: 2815 case lir_dynamic_call: 2816 offset += NativeCall::displacement_offset; 2817 break; 2818 case lir_icvirtual_call: 2819 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2820 break; 2821 case lir_virtual_call: // currently, sparc-specific for niagara 2822 default: ShouldNotReachHere(); 2823 } 2824 while (offset++ % BytesPerWord != 0) { 2825 __ nop(); 2826 } 2827 } 2828 } 2829 2830 2831 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2832 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2833 "must be aligned"); 2834 __ call(AddressLiteral(op->addr(), rtype)); 2835 add_call_info(code_offset(), op->info()); 2836 } 2837 2838 2839 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2840 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2841 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); 2842 assert(!os::is_MP() || 2843 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2844 "must be aligned"); 2845 __ call(AddressLiteral(op->addr(), rh)); 2846 add_call_info(code_offset(), op->info()); 2847 } 2848 2849 2850 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2851 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2852 ShouldNotReachHere(); 2853 } 2854 2855 2856 void LIR_Assembler::emit_static_call_stub() { 2857 address call_pc = __ pc(); 2858 address stub = __ start_a_stub(call_stub_size); 2859 if (stub == NULL) { 2860 bailout("static call stub overflow"); 2861 return; 2862 } 2863 2864 int start = __ offset(); 2865 if (os::is_MP()) { 2866 // make sure that the displacement word of the call ends up word aligned 2867 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2868 while (offset++ % BytesPerWord != 0) { 2869 __ nop(); 2870 } 2871 } 2872 __ relocate(static_stub_Relocation::spec(call_pc)); 2873 __ movoop(rbx, (jobject)NULL); 2874 // must be set to -1 at code generation time 2875 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2876 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2877 __ jump(RuntimeAddress(__ pc())); 2878 2879 assert(__ offset() - start <= call_stub_size, "stub too big"); 2880 __ end_a_stub(); 2881 } 2882 2883 2884 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2885 assert(exceptionOop->as_register() == rax, "must match"); 2886 assert(exceptionPC->as_register() == rdx, "must match"); 2887 2888 // exception object is not added to oop map by LinearScan 2889 // (LinearScan assumes that no oops are in fixed registers) 2890 info->add_register_oop(exceptionOop); 2891 Runtime1::StubID unwind_id; 2892 2893 // get current pc information 2894 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2895 int pc_for_athrow_offset = __ offset(); 2896 InternalAddress pc_for_athrow(__ pc()); 2897 __ lea(exceptionPC->as_register(), pc_for_athrow); 2898 add_call_info(pc_for_athrow_offset, info); // for exception handler 2899 2900 __ verify_not_null_oop(rax); 2901 // search an exception handler (rax: exception oop, rdx: throwing pc) 2902 if (compilation()->has_fpu_code()) { 2903 unwind_id = Runtime1::handle_exception_id; 2904 } else { 2905 unwind_id = Runtime1::handle_exception_nofpu_id; 2906 } 2907 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2908 2909 // enough room for two byte trap 2910 __ nop(); 2911 } 2912 2913 2914 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2915 assert(exceptionOop->as_register() == rax, "must match"); 2916 2917 __ jmp(_unwind_handler_entry); 2918 } 2919 2920 2921 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2922 2923 // optimized version for linear scan: 2924 // * count must be already in ECX (guaranteed by LinearScan) 2925 // * left and dest must be equal 2926 // * tmp must be unused 2927 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2928 assert(left == dest, "left and dest must be equal"); 2929 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2930 2931 if (left->is_single_cpu()) { 2932 Register value = left->as_register(); 2933 assert(value != SHIFT_count, "left cannot be ECX"); 2934 2935 switch (code) { 2936 case lir_shl: __ shll(value); break; 2937 case lir_shr: __ sarl(value); break; 2938 case lir_ushr: __ shrl(value); break; 2939 default: ShouldNotReachHere(); 2940 } 2941 } else if (left->is_double_cpu()) { 2942 Register lo = left->as_register_lo(); 2943 Register hi = left->as_register_hi(); 2944 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2945 #ifdef _LP64 2946 switch (code) { 2947 case lir_shl: __ shlptr(lo); break; 2948 case lir_shr: __ sarptr(lo); break; 2949 case lir_ushr: __ shrptr(lo); break; 2950 default: ShouldNotReachHere(); 2951 } 2952 #else 2953 2954 switch (code) { 2955 case lir_shl: __ lshl(hi, lo); break; 2956 case lir_shr: __ lshr(hi, lo, true); break; 2957 case lir_ushr: __ lshr(hi, lo, false); break; 2958 default: ShouldNotReachHere(); 2959 } 2960 #endif // LP64 2961 } else { 2962 ShouldNotReachHere(); 2963 } 2964 } 2965 2966 2967 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2968 if (dest->is_single_cpu()) { 2969 // first move left into dest so that left is not destroyed by the shift 2970 Register value = dest->as_register(); 2971 count = count & 0x1F; // Java spec 2972 2973 move_regs(left->as_register(), value); 2974 switch (code) { 2975 case lir_shl: __ shll(value, count); break; 2976 case lir_shr: __ sarl(value, count); break; 2977 case lir_ushr: __ shrl(value, count); break; 2978 default: ShouldNotReachHere(); 2979 } 2980 } else if (dest->is_double_cpu()) { 2981 #ifndef _LP64 2982 Unimplemented(); 2983 #else 2984 // first move left into dest so that left is not destroyed by the shift 2985 Register value = dest->as_register_lo(); 2986 count = count & 0x1F; // Java spec 2987 2988 move_regs(left->as_register_lo(), value); 2989 switch (code) { 2990 case lir_shl: __ shlptr(value, count); break; 2991 case lir_shr: __ sarptr(value, count); break; 2992 case lir_ushr: __ shrptr(value, count); break; 2993 default: ShouldNotReachHere(); 2994 } 2995 #endif // _LP64 2996 } else { 2997 ShouldNotReachHere(); 2998 } 2999 } 3000 3001 3002 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3003 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3004 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3005 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3006 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3007 } 3008 3009 3010 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3011 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3012 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3013 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3014 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3015 } 3016 3017 3018 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3019 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3020 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3021 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3022 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3023 } 3024 3025 3026 // This code replaces a call to arraycopy; no exception may 3027 // be thrown in this code, they must be thrown in the System.arraycopy 3028 // activation frame; we could save some checks if this would not be the case 3029 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3030 ciArrayKlass* default_type = op->expected_type(); 3031 Register src = op->src()->as_register(); 3032 Register dst = op->dst()->as_register(); 3033 Register src_pos = op->src_pos()->as_register(); 3034 Register dst_pos = op->dst_pos()->as_register(); 3035 Register length = op->length()->as_register(); 3036 Register tmp = op->tmp()->as_register(); 3037 3038 CodeStub* stub = op->stub(); 3039 int flags = op->flags(); 3040 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3041 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3042 3043 // if we don't know anything or it's an object array, just go through the generic arraycopy 3044 if (default_type == NULL) { 3045 Label done; 3046 // save outgoing arguments on stack in case call to System.arraycopy is needed 3047 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3048 // for interpreter calling conventions. Now we have to do it in new style conventions. 3049 // For the moment until C1 gets the new register allocator I just force all the 3050 // args to the right place (except the register args) and then on the back side 3051 // reload the register args properly if we go slow path. Yuck 3052 3053 // These are proper for the calling convention 3054 3055 store_parameter(length, 2); 3056 store_parameter(dst_pos, 1); 3057 store_parameter(dst, 0); 3058 3059 // these are just temporary placements until we need to reload 3060 store_parameter(src_pos, 3); 3061 store_parameter(src, 4); 3062 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3063 3064 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3065 3066 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3067 #ifdef _LP64 3068 // The arguments are in java calling convention so we can trivially shift them to C 3069 // convention 3070 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3071 __ mov(c_rarg0, j_rarg0); 3072 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3073 __ mov(c_rarg1, j_rarg1); 3074 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3075 __ mov(c_rarg2, j_rarg2); 3076 assert_different_registers(c_rarg3, j_rarg4); 3077 __ mov(c_rarg3, j_rarg3); 3078 #ifdef _WIN64 3079 // Allocate abi space for args but be sure to keep stack aligned 3080 __ subptr(rsp, 6*wordSize); 3081 store_parameter(j_rarg4, 4); 3082 __ call(RuntimeAddress(entry)); 3083 __ addptr(rsp, 6*wordSize); 3084 #else 3085 __ mov(c_rarg4, j_rarg4); 3086 __ call(RuntimeAddress(entry)); 3087 #endif // _WIN64 3088 #else 3089 __ push(length); 3090 __ push(dst_pos); 3091 __ push(dst); 3092 __ push(src_pos); 3093 __ push(src); 3094 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack 3095 3096 #endif // _LP64 3097 3098 __ cmpl(rax, 0); 3099 __ jcc(Assembler::equal, *stub->continuation()); 3100 3101 // Reload values from the stack so they are where the stub 3102 // expects them. 3103 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3104 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3105 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3106 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3107 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3108 __ jmp(*stub->entry()); 3109 3110 __ bind(*stub->continuation()); 3111 return; 3112 } 3113 3114 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3115 3116 int elem_size = type2aelembytes(basic_type); 3117 int shift_amount; 3118 Address::ScaleFactor scale; 3119 3120 switch (elem_size) { 3121 case 1 : 3122 shift_amount = 0; 3123 scale = Address::times_1; 3124 break; 3125 case 2 : 3126 shift_amount = 1; 3127 scale = Address::times_2; 3128 break; 3129 case 4 : 3130 shift_amount = 2; 3131 scale = Address::times_4; 3132 break; 3133 case 8 : 3134 shift_amount = 3; 3135 scale = Address::times_8; 3136 break; 3137 default: 3138 ShouldNotReachHere(); 3139 } 3140 3141 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3142 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3143 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3144 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3145 3146 // length and pos's are all sign extended at this point on 64bit 3147 3148 // test for NULL 3149 if (flags & LIR_OpArrayCopy::src_null_check) { 3150 __ testptr(src, src); 3151 __ jcc(Assembler::zero, *stub->entry()); 3152 } 3153 if (flags & LIR_OpArrayCopy::dst_null_check) { 3154 __ testptr(dst, dst); 3155 __ jcc(Assembler::zero, *stub->entry()); 3156 } 3157 3158 // check if negative 3159 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3160 __ testl(src_pos, src_pos); 3161 __ jcc(Assembler::less, *stub->entry()); 3162 } 3163 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3164 __ testl(dst_pos, dst_pos); 3165 __ jcc(Assembler::less, *stub->entry()); 3166 } 3167 if (flags & LIR_OpArrayCopy::length_positive_check) { 3168 __ testl(length, length); 3169 __ jcc(Assembler::less, *stub->entry()); 3170 } 3171 3172 if (flags & LIR_OpArrayCopy::src_range_check) { 3173 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3174 __ cmpl(tmp, src_length_addr); 3175 __ jcc(Assembler::above, *stub->entry()); 3176 } 3177 if (flags & LIR_OpArrayCopy::dst_range_check) { 3178 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3179 __ cmpl(tmp, dst_length_addr); 3180 __ jcc(Assembler::above, *stub->entry()); 3181 } 3182 3183 if (flags & LIR_OpArrayCopy::type_check) { 3184 __ movptr(tmp, src_klass_addr); 3185 __ cmpptr(tmp, dst_klass_addr); 3186 __ jcc(Assembler::notEqual, *stub->entry()); 3187 } 3188 3189 #ifdef ASSERT 3190 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3191 // Sanity check the known type with the incoming class. For the 3192 // primitive case the types must match exactly with src.klass and 3193 // dst.klass each exactly matching the default type. For the 3194 // object array case, if no type check is needed then either the 3195 // dst type is exactly the expected type and the src type is a 3196 // subtype which we can't check or src is the same array as dst 3197 // but not necessarily exactly of type default_type. 3198 Label known_ok, halt; 3199 __ movoop(tmp, default_type->constant_encoding()); 3200 if (basic_type != T_OBJECT) { 3201 __ cmpptr(tmp, dst_klass_addr); 3202 __ jcc(Assembler::notEqual, halt); 3203 __ cmpptr(tmp, src_klass_addr); 3204 __ jcc(Assembler::equal, known_ok); 3205 } else { 3206 __ cmpptr(tmp, dst_klass_addr); 3207 __ jcc(Assembler::equal, known_ok); 3208 __ cmpptr(src, dst); 3209 __ jcc(Assembler::equal, known_ok); 3210 } 3211 __ bind(halt); 3212 __ stop("incorrect type information in arraycopy"); 3213 __ bind(known_ok); 3214 } 3215 #endif 3216 3217 if (shift_amount > 0 && basic_type != T_OBJECT) { 3218 __ shlptr(length, shift_amount); 3219 } 3220 3221 #ifdef _LP64 3222 assert_different_registers(c_rarg0, dst, dst_pos, length); 3223 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3224 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3225 assert_different_registers(c_rarg1, length); 3226 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3227 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3228 __ mov(c_rarg2, length); 3229 3230 #else 3231 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3232 store_parameter(tmp, 0); 3233 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3234 store_parameter(tmp, 1); 3235 store_parameter(length, 2); 3236 #endif // _LP64 3237 if (basic_type == T_OBJECT) { 3238 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); 3239 } else { 3240 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); 3241 } 3242 3243 __ bind(*stub->continuation()); 3244 } 3245 3246 3247 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3248 Register obj = op->obj_opr()->as_register(); // may not be an oop 3249 Register hdr = op->hdr_opr()->as_register(); 3250 Register lock = op->lock_opr()->as_register(); 3251 if (!UseFastLocking) { 3252 __ jmp(*op->stub()->entry()); 3253 } else if (op->code() == lir_lock) { 3254 Register scratch = noreg; 3255 if (UseBiasedLocking) { 3256 scratch = op->scratch_opr()->as_register(); 3257 } 3258 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3259 // add debug info for NullPointerException only if one is possible 3260 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3261 if (op->info() != NULL) { 3262 add_debug_info_for_null_check(null_check_offset, op->info()); 3263 } 3264 // done 3265 } else if (op->code() == lir_unlock) { 3266 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3267 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3268 } else { 3269 Unimplemented(); 3270 } 3271 __ bind(*op->stub()->continuation()); 3272 } 3273 3274 3275 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3276 ciMethod* method = op->profiled_method(); 3277 int bci = op->profiled_bci(); 3278 3279 // Update counter for all call types 3280 ciMethodData* md = method->method_data(); 3281 if (md == NULL) { 3282 bailout("out of memory building methodDataOop"); 3283 return; 3284 } 3285 ciProfileData* data = md->bci_to_data(bci); 3286 assert(data->is_CounterData(), "need CounterData for calls"); 3287 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3288 Register mdo = op->mdo()->as_register(); 3289 __ movoop(mdo, md->constant_encoding()); 3290 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3291 Bytecodes::Code bc = method->java_code_at_bci(bci); 3292 // Perform additional virtual call profiling for invokevirtual and 3293 // invokeinterface bytecodes 3294 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3295 C1ProfileVirtualCalls) { 3296 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3297 Register recv = op->recv()->as_register(); 3298 assert_different_registers(mdo, recv); 3299 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3300 ciKlass* known_klass = op->known_holder(); 3301 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3302 // We know the type that will be seen at this call site; we can 3303 // statically update the methodDataOop rather than needing to do 3304 // dynamic tests on the receiver type 3305 3306 // NOTE: we should probably put a lock around this search to 3307 // avoid collisions by concurrent compilations 3308 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3309 uint i; 3310 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3311 ciKlass* receiver = vc_data->receiver(i); 3312 if (known_klass->equals(receiver)) { 3313 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3314 __ addptr(data_addr, DataLayout::counter_increment); 3315 return; 3316 } 3317 } 3318 3319 // Receiver type not found in profile data; select an empty slot 3320 3321 // Note that this is less efficient than it should be because it 3322 // always does a write to the receiver part of the 3323 // VirtualCallData rather than just the first time 3324 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3325 ciKlass* receiver = vc_data->receiver(i); 3326 if (receiver == NULL) { 3327 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3328 __ movoop(recv_addr, known_klass->constant_encoding()); 3329 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3330 __ addptr(data_addr, DataLayout::counter_increment); 3331 return; 3332 } 3333 } 3334 } else { 3335 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); 3336 Label update_done; 3337 type_profile_helper(mdo, md, data, recv, &update_done); 3338 // Receiver did not match any saved receiver and there is no empty row for it. 3339 // Increment total counter to indicate polymorphic case. 3340 __ addptr(counter_addr, DataLayout::counter_increment); 3341 3342 __ bind(update_done); 3343 } 3344 } else { 3345 // Static call 3346 __ addptr(counter_addr, DataLayout::counter_increment); 3347 } 3348 } 3349 3350 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3351 Unimplemented(); 3352 } 3353 3354 3355 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3356 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3357 } 3358 3359 3360 void LIR_Assembler::align_backward_branch_target() { 3361 __ align(BytesPerWord); 3362 } 3363 3364 3365 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3366 if (left->is_single_cpu()) { 3367 __ negl(left->as_register()); 3368 move_regs(left->as_register(), dest->as_register()); 3369 3370 } else if (left->is_double_cpu()) { 3371 Register lo = left->as_register_lo(); 3372 #ifdef _LP64 3373 Register dst = dest->as_register_lo(); 3374 __ movptr(dst, lo); 3375 __ negptr(dst); 3376 #else 3377 Register hi = left->as_register_hi(); 3378 __ lneg(hi, lo); 3379 if (dest->as_register_lo() == hi) { 3380 assert(dest->as_register_hi() != lo, "destroying register"); 3381 move_regs(hi, dest->as_register_hi()); 3382 move_regs(lo, dest->as_register_lo()); 3383 } else { 3384 move_regs(lo, dest->as_register_lo()); 3385 move_regs(hi, dest->as_register_hi()); 3386 } 3387 #endif // _LP64 3388 3389 } else if (dest->is_single_xmm()) { 3390 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3391 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3392 } 3393 __ xorps(dest->as_xmm_float_reg(), 3394 ExternalAddress((address)float_signflip_pool)); 3395 3396 } else if (dest->is_double_xmm()) { 3397 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3398 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3399 } 3400 __ xorpd(dest->as_xmm_double_reg(), 3401 ExternalAddress((address)double_signflip_pool)); 3402 3403 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3404 assert(left->fpu() == 0, "arg must be on TOS"); 3405 assert(dest->fpu() == 0, "dest must be TOS"); 3406 __ fchs(); 3407 3408 } else { 3409 ShouldNotReachHere(); 3410 } 3411 } 3412 3413 3414 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3415 assert(addr->is_address() && dest->is_register(), "check"); 3416 Register reg; 3417 reg = dest->as_pointer_register(); 3418 __ lea(reg, as_Address(addr->as_address_ptr())); 3419 } 3420 3421 3422 3423 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3424 assert(!tmp->is_valid(), "don't need temporary"); 3425 __ call(RuntimeAddress(dest)); 3426 if (info != NULL) { 3427 add_call_info_here(info); 3428 } 3429 } 3430 3431 3432 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3433 assert(type == T_LONG, "only for volatile long fields"); 3434 3435 if (info != NULL) { 3436 add_debug_info_for_null_check_here(info); 3437 } 3438 3439 if (src->is_double_xmm()) { 3440 if (dest->is_double_cpu()) { 3441 #ifdef _LP64 3442 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3443 #else 3444 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3445 __ psrlq(src->as_xmm_double_reg(), 32); 3446 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3447 #endif // _LP64 3448 } else if (dest->is_double_stack()) { 3449 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3450 } else if (dest->is_address()) { 3451 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3452 } else { 3453 ShouldNotReachHere(); 3454 } 3455 3456 } else if (dest->is_double_xmm()) { 3457 if (src->is_double_stack()) { 3458 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3459 } else if (src->is_address()) { 3460 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3461 } else { 3462 ShouldNotReachHere(); 3463 } 3464 3465 } else if (src->is_double_fpu()) { 3466 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3467 if (dest->is_double_stack()) { 3468 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3469 } else if (dest->is_address()) { 3470 __ fistp_d(as_Address(dest->as_address_ptr())); 3471 } else { 3472 ShouldNotReachHere(); 3473 } 3474 3475 } else if (dest->is_double_fpu()) { 3476 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3477 if (src->is_double_stack()) { 3478 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3479 } else if (src->is_address()) { 3480 __ fild_d(as_Address(src->as_address_ptr())); 3481 } else { 3482 ShouldNotReachHere(); 3483 } 3484 } else { 3485 ShouldNotReachHere(); 3486 } 3487 } 3488 3489 3490 void LIR_Assembler::membar() { 3491 // QQQ sparc TSO uses this, 3492 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3493 } 3494 3495 void LIR_Assembler::membar_acquire() { 3496 // No x86 machines currently require load fences 3497 // __ load_fence(); 3498 } 3499 3500 void LIR_Assembler::membar_release() { 3501 // No x86 machines currently require store fences 3502 // __ store_fence(); 3503 } 3504 3505 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3506 assert(result_reg->is_register(), "check"); 3507 #ifdef _LP64 3508 // __ get_thread(result_reg->as_register_lo()); 3509 __ mov(result_reg->as_register(), r15_thread); 3510 #else 3511 __ get_thread(result_reg->as_register()); 3512 #endif // _LP64 3513 } 3514 3515 3516 void LIR_Assembler::peephole(LIR_List*) { 3517 // do nothing for now 3518 } 3519 3520 3521 #undef __