1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_x86.cpp.incl"
27
28
29 // These masks are used to provide 128-bit aligned bitmasks to the XMM
30 // instructions, to allow sign-masking or sign-bit flipping. They allow
31 // fast versions of NegF/NegD and AbsF/AbsD.
32
33 // Note: 'double' and 'long long' have 32-bits alignment on x86.
34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
36 // of 128-bits operands for SSE instructions.
37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
38 // Store the value to a 128-bits operand.
39 operand[0] = lo;
40 operand[1] = hi;
41 return operand;
42 }
43
44 // Buffer for 128-bits masks used by SSE instructions.
45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
46
47 // Static initialization during VM startup.
48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
52
53
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rax; // where the IC klass is cached
57 const Register SYNC_header = rax; // synchronization header
58 const Register SHIFT_count = rcx; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
100 if (opr->is_constant()) {
101 LIR_Const* constant = opr->as_constant_ptr();
102 switch (constant->type()) {
103 case T_INT: {
104 return true;
105 }
106
107 default:
108 return false;
109 }
110 }
111 return false;
112 }
113
114
115 LIR_Opr LIR_Assembler::receiverOpr() {
116 return FrameMap::receiver_opr;
117 }
118
119 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
120 return receiverOpr();
121 }
122
123 LIR_Opr LIR_Assembler::osrBufferPointer() {
124 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
125 }
126
127 //--------------fpu register translations-----------------------
128
129
130 address LIR_Assembler::float_constant(float f) {
131 address const_addr = __ float_constant(f);
132 if (const_addr == NULL) {
133 bailout("const section overflow");
134 return __ code()->consts()->start();
135 } else {
136 return const_addr;
137 }
138 }
139
140
141 address LIR_Assembler::double_constant(double d) {
142 address const_addr = __ double_constant(d);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 void LIR_Assembler::set_24bit_FPU() {
153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
154 }
155
156 void LIR_Assembler::reset_FPU() {
157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
158 }
159
160 void LIR_Assembler::fpop() {
161 __ fpop();
162 }
163
164 void LIR_Assembler::fxch(int i) {
165 __ fxch(i);
166 }
167
168 void LIR_Assembler::fld(int i) {
169 __ fld_s(i);
170 }
171
172 void LIR_Assembler::ffree(int i) {
173 __ ffree(i);
174 }
175
176 void LIR_Assembler::breakpoint() {
177 __ int3();
178 }
179
180 void LIR_Assembler::push(LIR_Opr opr) {
181 if (opr->is_single_cpu()) {
182 __ push_reg(opr->as_register());
183 } else if (opr->is_double_cpu()) {
184 NOT_LP64(__ push_reg(opr->as_register_hi()));
185 __ push_reg(opr->as_register_lo());
186 } else if (opr->is_stack()) {
187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
188 } else if (opr->is_constant()) {
189 LIR_Const* const_opr = opr->as_constant_ptr();
190 if (const_opr->type() == T_OBJECT) {
191 __ push_oop(const_opr->as_jobject());
192 } else if (const_opr->type() == T_INT) {
193 __ push_jint(const_opr->as_jint());
194 } else {
195 ShouldNotReachHere();
196 }
197
198 } else {
199 ShouldNotReachHere();
200 }
201 }
202
203 void LIR_Assembler::pop(LIR_Opr opr) {
204 if (opr->is_single_cpu()) {
205 __ pop_reg(opr->as_register());
206 } else {
207 ShouldNotReachHere();
208 }
209 }
210
211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
212 return addr->base()->is_illegal() && addr->index()->is_illegal();
213 }
214
215 //-------------------------------------------
216
217 Address LIR_Assembler::as_Address(LIR_Address* addr) {
218 return as_Address(addr, rscratch1);
219 }
220
221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
222 if (addr->base()->is_illegal()) {
223 assert(addr->index()->is_illegal(), "must be illegal too");
224 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
225 if (! __ reachable(laddr)) {
226 __ movptr(tmp, laddr.addr());
227 Address res(tmp, 0);
228 return res;
229 } else {
230 return __ as_Address(laddr);
231 }
232 }
233
234 Register base = addr->base()->as_pointer_register();
235
236 if (addr->index()->is_illegal()) {
237 return Address( base, addr->disp());
238 } else if (addr->index()->is_cpu_register()) {
239 Register index = addr->index()->as_pointer_register();
240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
241 } else if (addr->index()->is_constant()) {
242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
243 assert(Assembler::is_simm32(addr_offset), "must be");
244
245 return Address(base, addr_offset);
246 } else {
247 Unimplemented();
248 return Address();
249 }
250 }
251
252
253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
254 Address base = as_Address(addr);
255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
256 }
257
258
259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
260 return as_Address(addr);
261 }
262
263
264 void LIR_Assembler::osr_entry() {
265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
266 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
267 ValueStack* entry_state = osr_entry->state();
268 int number_of_locks = entry_state->locks_size();
269
270 // we jump here if osr happens with the interpreter
271 // state set up to continue at the beginning of the
272 // loop that triggered osr - in particular, we have
273 // the following registers setup:
274 //
275 // rcx: osr buffer
276 //
277
278 // build frame
279 ciMethod* m = compilation()->method();
280 __ build_frame(initial_frame_size_in_bytes());
281
282 // OSR buffer is
283 //
284 // locals[nlocals-1..0]
285 // monitors[0..number_of_locks]
286 //
287 // locals is a direct copy of the interpreter frame so in the osr buffer
288 // so first slot in the local array is the last local from the interpreter
289 // and last slot is local[0] (receiver) from the interpreter
290 //
291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
293 // in the interpreter frame (the method lock if a sync method)
294
295 // Initialize monitors in the compiled activation.
296 // rcx: pointer to osr buffer
297 //
298 // All other registers are dead at this point and the locals will be
299 // copied into place by code emitted in the IR.
300
301 Register OSR_buf = osrBufferPointer()->as_pointer_register();
302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
303 int monitor_offset = BytesPerWord * method()->max_locals() +
304 (2 * BytesPerWord) * (number_of_locks - 1);
305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
306 // the OSR buffer using 2 word entries: first the lock and then
307 // the oop.
308 for (int i = 0; i < number_of_locks; i++) {
309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
310 #ifdef ASSERT
311 // verify the interpreter's monitor has a non-null object
312 {
313 Label L;
314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
315 __ jcc(Assembler::notZero, L);
316 __ stop("locked object is NULL");
317 __ bind(L);
318 }
319 #endif
320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
323 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
324 }
325 }
326 }
327
328
329 // inline cache check; done before the frame is built.
330 int LIR_Assembler::check_icache() {
331 Register receiver = FrameMap::receiver_opr->as_register();
332 Register ic_klass = IC_Klass;
333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
334 const bool do_post_padding = VerifyOops || UseCompressedOops;
335 if (!do_post_padding) {
336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
338 __ nop();
339 }
340 }
341 int offset = __ offset();
342 __ inline_cache_check(receiver, IC_Klass);
343 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
344 if (do_post_padding) {
345 // force alignment after the cache check.
346 // It's been verified to be aligned if !VerifyOops
347 __ align(CodeEntryAlignment);
348 }
349 return offset;
350 }
351
352
353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
354 jobject o = NULL;
355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
356 __ movoop(reg, o);
357 patching_epilog(patch, lir_patch_normal, reg, info);
358 }
359
360
361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
362 if (exception->is_valid()) {
363 // preserve exception
364 // note: the monitor_exit runtime call is a leaf routine
365 // and cannot block => no GC can happen
366 // The slow case (MonitorAccessStub) uses the first two stack slots
367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
368 __ movptr (Address(rsp, 2*wordSize), exception);
369 }
370
371 Register obj_reg = obj_opr->as_register();
372 Register lock_reg = lock_opr->as_register();
373
374 // setup registers (lock_reg must be rax, for lock_object)
375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
376 Register hdr = lock_reg;
377 assert(new_hdr == SYNC_header, "wrong register");
378 lock_reg = new_hdr;
379 // compute pointer to BasicLock
380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
381 __ lea(lock_reg, lock_addr);
382 // unlock object
383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
384 // _slow_case_stubs->append(slow_case);
385 // temporary fix: must be created after exceptionhandler, therefore as call stub
386 _slow_case_stubs->append(slow_case);
387 if (UseFastLocking) {
388 // try inlined fast unlocking first, revert to slow locking if it fails
389 // note: lock_reg points to the displaced header since the displaced header offset is 0!
390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
392 } else {
393 // always do slow unlocking
394 // note: the slow unlocking code could be inlined here, however if we use
395 // slow unlocking, speed doesn't matter anyway and this solution is
396 // simpler and requires less duplicated code - additionally, the
397 // slow unlocking code is the same in either case which simplifies
398 // debugging
399 __ jmp(*slow_case->entry());
400 }
401 // done
402 __ bind(*slow_case->continuation());
403
404 if (exception->is_valid()) {
405 // restore exception
406 __ movptr (exception, Address(rsp, 2 * wordSize));
407 }
408 }
409
410 // This specifies the rsp decrement needed to build the frame
411 int LIR_Assembler::initial_frame_size_in_bytes() {
412 // if rounding, must let FrameMap know!
413
414 // The frame_map records size in slots (32bit word)
415
416 // subtract two words to account for return address and link
417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
418 }
419
420
421 int LIR_Assembler::emit_exception_handler() {
422 // if the last instruction is a call (typically to do a throw which
423 // is coming at the end after block reordering) the return address
424 // must still point into the code area in order to avoid assertion
425 // failures when searching for the corresponding bci => add a nop
426 // (was bug 5/14/1999 - gri)
427 __ nop();
428
429 // generate code for exception handler
430 address handler_base = __ start_a_stub(exception_handler_size);
431 if (handler_base == NULL) {
432 // not enough space left for the handler
433 bailout("exception handler overflow");
434 return -1;
435 }
436
437 int offset = code_offset();
438
439 // the exception oop and pc are in rax, and rdx
440 // no other registers need to be preserved, so invalidate them
441 __ invalidate_registers(false, true, true, false, true, true);
442
443 // check that there is really an exception
444 __ verify_not_null_oop(rax);
445
446 // search an exception handler (rax: exception oop, rdx: throwing pc)
447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
448
449 __ stop("should not reach here");
450
451 assert(code_offset() - offset <= exception_handler_size, "overflow");
452 __ end_a_stub();
453
454 return offset;
455 }
456
457
458 // Emit the code to remove the frame from the stack in the exception
459 // unwind path.
460 int LIR_Assembler::emit_unwind_handler() {
461 #ifndef PRODUCT
462 if (CommentedAssembly) {
463 _masm->block_comment("Unwind handler");
464 }
465 #endif
466
467 int offset = code_offset();
468
469 // Fetch the exception from TLS and clear out exception related thread state
470 __ get_thread(rsi);
471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
474
475 __ bind(_unwind_handler_entry);
476 __ verify_not_null_oop(rax);
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rsi, rax); // Preserve the exception
479 }
480
481 // Preform needed unlocking
482 MonitorExitStub* stub = NULL;
483 if (method()->is_synchronized()) {
484 monitor_address(0, FrameMap::rax_opr);
485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
486 __ unlock_object(rdi, rbx, rax, *stub->entry());
487 __ bind(*stub->continuation());
488 }
489
490 if (compilation()->env()->dtrace_method_probes()) {
491 __ get_thread(rax);
492 __ movptr(Address(rsp, 0), rax);
493 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding());
494 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
495 }
496
497 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
498 __ mov(rax, rsi); // Restore the exception
499 }
500
501 // remove the activation and dispatch to the unwind handler
502 __ remove_frame(initial_frame_size_in_bytes());
503 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
504
505 // Emit the slow path assembly
506 if (stub != NULL) {
507 stub->emit_code(this);
508 }
509
510 return offset;
511 }
512
513
514 int LIR_Assembler::emit_deopt_handler() {
515 // if the last instruction is a call (typically to do a throw which
516 // is coming at the end after block reordering) the return address
517 // must still point into the code area in order to avoid assertion
518 // failures when searching for the corresponding bci => add a nop
519 // (was bug 5/14/1999 - gri)
520 __ nop();
521
522 // generate code for exception handler
523 address handler_base = __ start_a_stub(deopt_handler_size);
524 if (handler_base == NULL) {
525 // not enough space left for the handler
526 bailout("deopt handler overflow");
527 return -1;
528 }
529
530 int offset = code_offset();
531 InternalAddress here(__ pc());
532
533 __ pushptr(here.addr());
534 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
535
536 assert(code_offset() - offset <= deopt_handler_size, "overflow");
537 __ end_a_stub();
538
539 return offset;
540 }
541
542
543 // This is the fast version of java.lang.String.compare; it has not
544 // OSR-entry and therefore, we generate a slow version for OSR's
545 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
546 __ movptr (rbx, rcx); // receiver is in rcx
547 __ movptr (rax, arg1->as_register());
548
549 // Get addresses of first characters from both Strings
550 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
551 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
552 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
553
554
555 // rbx, may be NULL
556 add_debug_info_for_null_check_here(info);
557 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
558 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
559 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
560
561 // compute minimum length (in rax) and difference of lengths (on top of stack)
562 if (VM_Version::supports_cmov()) {
563 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
564 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
565 __ mov (rcx, rbx);
566 __ subptr (rbx, rax); // subtract lengths
567 __ push (rbx); // result
568 __ cmov (Assembler::lessEqual, rax, rcx);
569 } else {
570 Label L;
571 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
572 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
573 __ mov (rax, rbx);
574 __ subptr (rbx, rcx);
575 __ push (rbx);
576 __ jcc (Assembler::lessEqual, L);
577 __ mov (rax, rcx);
578 __ bind (L);
579 }
580 // is minimum length 0?
581 Label noLoop, haveResult;
582 __ testptr (rax, rax);
583 __ jcc (Assembler::zero, noLoop);
584
585 // compare first characters
586 __ load_unsigned_short(rcx, Address(rdi, 0));
587 __ load_unsigned_short(rbx, Address(rsi, 0));
588 __ subl(rcx, rbx);
589 __ jcc(Assembler::notZero, haveResult);
590 // starting loop
591 __ decrement(rax); // we already tested index: skip one
592 __ jcc(Assembler::zero, noLoop);
593
594 // set rsi.edi to the end of the arrays (arrays have same length)
595 // negate the index
596
597 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
598 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
599 __ negptr(rax);
600
601 // compare the strings in a loop
602
603 Label loop;
604 __ align(wordSize);
605 __ bind(loop);
606 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
607 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
608 __ subl(rcx, rbx);
609 __ jcc(Assembler::notZero, haveResult);
610 __ increment(rax);
611 __ jcc(Assembler::notZero, loop);
612
613 // strings are equal up to min length
614
615 __ bind(noLoop);
616 __ pop(rax);
617 return_op(LIR_OprFact::illegalOpr);
618
619 __ bind(haveResult);
620 // leave instruction is going to discard the TOS value
621 __ mov (rax, rcx); // result of call is in rax,
622 }
623
624
625 void LIR_Assembler::return_op(LIR_Opr result) {
626 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
627 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
628 assert(result->fpu() == 0, "result must already be on TOS");
629 }
630
631 // Pop the stack before the safepoint code
632 __ remove_frame(initial_frame_size_in_bytes());
633
634 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
635
636 // Note: we do not need to round double result; float result has the right precision
637 // the poll sets the condition code, but no data registers
638 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
639 relocInfo::poll_return_type);
640
641 // NOTE: the requires that the polling page be reachable else the reloc
642 // goes to the movq that loads the address and not the faulting instruction
643 // which breaks the signal handler code
644
645 __ test32(rax, polling_page);
646
647 __ ret(0);
648 }
649
650
651 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
652 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
653 relocInfo::poll_type);
654
655 if (info != NULL) {
656 add_debug_info_for_branch(info);
657 } else {
658 ShouldNotReachHere();
659 }
660
661 int offset = __ offset();
662
663 // NOTE: the requires that the polling page be reachable else the reloc
664 // goes to the movq that loads the address and not the faulting instruction
665 // which breaks the signal handler code
666
667 __ test32(rax, polling_page);
668 return offset;
669 }
670
671
672 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
673 if (from_reg != to_reg) __ mov(to_reg, from_reg);
674 }
675
676 void LIR_Assembler::swap_reg(Register a, Register b) {
677 __ xchgptr(a, b);
678 }
679
680
681 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
682 assert(src->is_constant(), "should not call otherwise");
683 assert(dest->is_register(), "should not call otherwise");
684 LIR_Const* c = src->as_constant_ptr();
685
686 switch (c->type()) {
687 case T_INT: {
688 assert(patch_code == lir_patch_none, "no patching handled here");
689 __ movl(dest->as_register(), c->as_jint());
690 break;
691 }
692
693 case T_ADDRESS: {
694 assert(patch_code == lir_patch_none, "no patching handled here");
695 __ movptr(dest->as_register(), c->as_jint());
696 break;
697 }
698
699 case T_LONG: {
700 assert(patch_code == lir_patch_none, "no patching handled here");
701 #ifdef _LP64
702 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
703 #else
704 __ movptr(dest->as_register_lo(), c->as_jint_lo());
705 __ movptr(dest->as_register_hi(), c->as_jint_hi());
706 #endif // _LP64
707 break;
708 }
709
710 case T_OBJECT: {
711 if (patch_code != lir_patch_none) {
712 jobject2reg_with_patching(dest->as_register(), info);
713 } else {
714 __ movoop(dest->as_register(), c->as_jobject());
715 }
716 break;
717 }
718
719 case T_FLOAT: {
720 if (dest->is_single_xmm()) {
721 if (c->is_zero_float()) {
722 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
723 } else {
724 __ movflt(dest->as_xmm_float_reg(),
725 InternalAddress(float_constant(c->as_jfloat())));
726 }
727 } else {
728 assert(dest->is_single_fpu(), "must be");
729 assert(dest->fpu_regnr() == 0, "dest must be TOS");
730 if (c->is_zero_float()) {
731 __ fldz();
732 } else if (c->is_one_float()) {
733 __ fld1();
734 } else {
735 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
736 }
737 }
738 break;
739 }
740
741 case T_DOUBLE: {
742 if (dest->is_double_xmm()) {
743 if (c->is_zero_double()) {
744 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
745 } else {
746 __ movdbl(dest->as_xmm_double_reg(),
747 InternalAddress(double_constant(c->as_jdouble())));
748 }
749 } else {
750 assert(dest->is_double_fpu(), "must be");
751 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
752 if (c->is_zero_double()) {
753 __ fldz();
754 } else if (c->is_one_double()) {
755 __ fld1();
756 } else {
757 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
758 }
759 }
760 break;
761 }
762
763 default:
764 ShouldNotReachHere();
765 }
766 }
767
768 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
769 assert(src->is_constant(), "should not call otherwise");
770 assert(dest->is_stack(), "should not call otherwise");
771 LIR_Const* c = src->as_constant_ptr();
772
773 switch (c->type()) {
774 case T_INT: // fall through
775 case T_FLOAT:
776 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
777 break;
778
779 case T_ADDRESS:
780 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
781 break;
782
783 case T_OBJECT:
784 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
785 break;
786
787 case T_LONG: // fall through
788 case T_DOUBLE:
789 #ifdef _LP64
790 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
791 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
792 #else
793 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
794 lo_word_offset_in_bytes), c->as_jint_lo_bits());
795 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
796 hi_word_offset_in_bytes), c->as_jint_hi_bits());
797 #endif // _LP64
798 break;
799
800 default:
801 ShouldNotReachHere();
802 }
803 }
804
805 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
806 assert(src->is_constant(), "should not call otherwise");
807 assert(dest->is_address(), "should not call otherwise");
808 LIR_Const* c = src->as_constant_ptr();
809 LIR_Address* addr = dest->as_address_ptr();
810
811 int null_check_here = code_offset();
812 switch (type) {
813 case T_INT: // fall through
814 case T_FLOAT:
815 __ movl(as_Address(addr), c->as_jint_bits());
816 break;
817
818 case T_ADDRESS:
819 __ movptr(as_Address(addr), c->as_jint_bits());
820 break;
821
822 case T_OBJECT: // fall through
823 case T_ARRAY:
824 if (c->as_jobject() == NULL) {
825 #ifdef _LP64
826 if (UseCompressedOops && !wide) {
827 __ movl(as_Address(addr), (int32_t)NULL_WORD);
828 } else {
829 __ movptr(as_Address(addr), NULL_WORD);
830 }
831 #else
832 __ movptr(as_Address(addr), NULL_WORD);
833 #endif
834 } else {
835 if (is_literal_address(addr)) {
836 ShouldNotReachHere();
837 __ movoop(as_Address(addr, noreg), c->as_jobject());
838 } else {
839 #ifdef _LP64
840 __ movoop(rscratch1, c->as_jobject());
841 if (UseCompressedOops && !wide) {
842 __ encode_heap_oop(rscratch1);
843 null_check_here = code_offset();
844 __ movl(as_Address_lo(addr), rscratch1);
845 } else {
846 null_check_here = code_offset();
847 __ movptr(as_Address_lo(addr), rscratch1);
848 }
849 #else
850 __ movoop(as_Address(addr), c->as_jobject());
851 #endif
852 }
853 }
854 break;
855
856 case T_LONG: // fall through
857 case T_DOUBLE:
858 #ifdef _LP64
859 if (is_literal_address(addr)) {
860 ShouldNotReachHere();
861 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
862 } else {
863 __ movptr(r10, (intptr_t)c->as_jlong_bits());
864 null_check_here = code_offset();
865 __ movptr(as_Address_lo(addr), r10);
866 }
867 #else
868 // Always reachable in 32bit so this doesn't produce useless move literal
869 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
870 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
871 #endif // _LP64
872 break;
873
874 case T_BOOLEAN: // fall through
875 case T_BYTE:
876 __ movb(as_Address(addr), c->as_jint() & 0xFF);
877 break;
878
879 case T_CHAR: // fall through
880 case T_SHORT:
881 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
882 break;
883
884 default:
885 ShouldNotReachHere();
886 };
887
888 if (info != NULL) {
889 add_debug_info_for_null_check(null_check_here, info);
890 }
891 }
892
893
894 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
895 assert(src->is_register(), "should not call otherwise");
896 assert(dest->is_register(), "should not call otherwise");
897
898 // move between cpu-registers
899 if (dest->is_single_cpu()) {
900 #ifdef _LP64
901 if (src->type() == T_LONG) {
902 // Can do LONG -> OBJECT
903 move_regs(src->as_register_lo(), dest->as_register());
904 return;
905 }
906 #endif
907 assert(src->is_single_cpu(), "must match");
908 if (src->type() == T_OBJECT) {
909 __ verify_oop(src->as_register());
910 }
911 move_regs(src->as_register(), dest->as_register());
912
913 } else if (dest->is_double_cpu()) {
914 #ifdef _LP64
915 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
916 // Surprising to me but we can see move of a long to t_object
917 __ verify_oop(src->as_register());
918 move_regs(src->as_register(), dest->as_register_lo());
919 return;
920 }
921 #endif
922 assert(src->is_double_cpu(), "must match");
923 Register f_lo = src->as_register_lo();
924 Register f_hi = src->as_register_hi();
925 Register t_lo = dest->as_register_lo();
926 Register t_hi = dest->as_register_hi();
927 #ifdef _LP64
928 assert(f_hi == f_lo, "must be same");
929 assert(t_hi == t_lo, "must be same");
930 move_regs(f_lo, t_lo);
931 #else
932 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
933
934
935 if (f_lo == t_hi && f_hi == t_lo) {
936 swap_reg(f_lo, f_hi);
937 } else if (f_hi == t_lo) {
938 assert(f_lo != t_hi, "overwriting register");
939 move_regs(f_hi, t_hi);
940 move_regs(f_lo, t_lo);
941 } else {
942 assert(f_hi != t_lo, "overwriting register");
943 move_regs(f_lo, t_lo);
944 move_regs(f_hi, t_hi);
945 }
946 #endif // LP64
947
948 // special moves from fpu-register to xmm-register
949 // necessary for method results
950 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
951 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
952 __ fld_s(Address(rsp, 0));
953 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
954 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
955 __ fld_d(Address(rsp, 0));
956 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
957 __ fstp_s(Address(rsp, 0));
958 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
959 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
960 __ fstp_d(Address(rsp, 0));
961 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
962
963 // move between xmm-registers
964 } else if (dest->is_single_xmm()) {
965 assert(src->is_single_xmm(), "must match");
966 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
967 } else if (dest->is_double_xmm()) {
968 assert(src->is_double_xmm(), "must match");
969 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
970
971 // move between fpu-registers (no instruction necessary because of fpu-stack)
972 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
973 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
974 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
975 } else {
976 ShouldNotReachHere();
977 }
978 }
979
980 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
981 assert(src->is_register(), "should not call otherwise");
982 assert(dest->is_stack(), "should not call otherwise");
983
984 if (src->is_single_cpu()) {
985 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
986 if (type == T_OBJECT || type == T_ARRAY) {
987 __ verify_oop(src->as_register());
988 __ movptr (dst, src->as_register());
989 } else {
990 __ movl (dst, src->as_register());
991 }
992
993 } else if (src->is_double_cpu()) {
994 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
995 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
996 __ movptr (dstLO, src->as_register_lo());
997 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
998
999 } else if (src->is_single_xmm()) {
1000 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1001 __ movflt(dst_addr, src->as_xmm_float_reg());
1002
1003 } else if (src->is_double_xmm()) {
1004 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1005 __ movdbl(dst_addr, src->as_xmm_double_reg());
1006
1007 } else if (src->is_single_fpu()) {
1008 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1009 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1010 if (pop_fpu_stack) __ fstp_s (dst_addr);
1011 else __ fst_s (dst_addr);
1012
1013 } else if (src->is_double_fpu()) {
1014 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1015 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1016 if (pop_fpu_stack) __ fstp_d (dst_addr);
1017 else __ fst_d (dst_addr);
1018
1019 } else {
1020 ShouldNotReachHere();
1021 }
1022 }
1023
1024
1025 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */, bool wide) {
1026 LIR_Address* to_addr = dest->as_address_ptr();
1027 PatchingStub* patch = NULL;
1028
1029 #ifdef _LP64
1030 Register compressed_src = rscratch1;
1031 #endif
1032
1033 if (type == T_ARRAY || type == T_OBJECT) {
1034 __ verify_oop(src->as_register());
1035 #ifdef _LP64
1036 if (UseCompressedOops && !wide) {
1037 __ movptr(compressed_src, src->as_register());
1038 __ encode_heap_oop(compressed_src);
1039 }
1040 #endif
1041 }
1042
1043 if (patch_code != lir_patch_none) {
1044 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1045 Address toa = as_Address(to_addr);
1046 assert(toa.disp() != 0, "must have");
1047 }
1048
1049 int null_check_here = code_offset();
1050 switch (type) {
1051 case T_FLOAT: {
1052 if (src->is_single_xmm()) {
1053 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1054 } else {
1055 assert(src->is_single_fpu(), "must be");
1056 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1057 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1058 else __ fst_s (as_Address(to_addr));
1059 }
1060 break;
1061 }
1062
1063 case T_DOUBLE: {
1064 if (src->is_double_xmm()) {
1065 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1066 } else {
1067 assert(src->is_double_fpu(), "must be");
1068 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1069 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1070 else __ fst_d (as_Address(to_addr));
1071 }
1072 break;
1073 }
1074
1075 case T_ARRAY: // fall through
1076 case T_OBJECT: // fall through
1077 #ifdef _LP64
1078 if (UseCompressedOops && !wide) {
1079 __ movl(as_Address(to_addr), compressed_src);
1080 } else {
1081 __ movptr(as_Address(to_addr), src->as_register());
1082 }
1083 break;
1084 #endif // _LP64
1085 case T_ADDRESS:
1086 __ movptr(as_Address(to_addr), src->as_register());
1087 break;
1088 case T_INT:
1089 __ movl(as_Address(to_addr), src->as_register());
1090 break;
1091
1092 case T_LONG: {
1093 Register from_lo = src->as_register_lo();
1094 Register from_hi = src->as_register_hi();
1095 #ifdef _LP64
1096 __ movptr(as_Address_lo(to_addr), from_lo);
1097 #else
1098 Register base = to_addr->base()->as_register();
1099 Register index = noreg;
1100 if (to_addr->index()->is_register()) {
1101 index = to_addr->index()->as_register();
1102 }
1103 if (base == from_lo || index == from_lo) {
1104 assert(base != from_hi, "can't be");
1105 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1106 __ movl(as_Address_hi(to_addr), from_hi);
1107 if (patch != NULL) {
1108 patching_epilog(patch, lir_patch_high, base, info);
1109 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1110 patch_code = lir_patch_low;
1111 }
1112 __ movl(as_Address_lo(to_addr), from_lo);
1113 } else {
1114 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1115 __ movl(as_Address_lo(to_addr), from_lo);
1116 if (patch != NULL) {
1117 patching_epilog(patch, lir_patch_low, base, info);
1118 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1119 patch_code = lir_patch_high;
1120 }
1121 __ movl(as_Address_hi(to_addr), from_hi);
1122 }
1123 #endif // _LP64
1124 break;
1125 }
1126
1127 case T_BYTE: // fall through
1128 case T_BOOLEAN: {
1129 Register src_reg = src->as_register();
1130 Address dst_addr = as_Address(to_addr);
1131 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1132 __ movb(dst_addr, src_reg);
1133 break;
1134 }
1135
1136 case T_CHAR: // fall through
1137 case T_SHORT:
1138 __ movw(as_Address(to_addr), src->as_register());
1139 break;
1140
1141 default:
1142 ShouldNotReachHere();
1143 }
1144 if (info != NULL) {
1145 add_debug_info_for_null_check(null_check_here, info);
1146 }
1147
1148 if (patch_code != lir_patch_none) {
1149 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1150 }
1151 }
1152
1153
1154 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1155 assert(src->is_stack(), "should not call otherwise");
1156 assert(dest->is_register(), "should not call otherwise");
1157
1158 if (dest->is_single_cpu()) {
1159 if (type == T_ARRAY || type == T_OBJECT) {
1160 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1161 __ verify_oop(dest->as_register());
1162 } else {
1163 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1164 }
1165
1166 } else if (dest->is_double_cpu()) {
1167 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1168 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1169 __ movptr(dest->as_register_lo(), src_addr_LO);
1170 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1171
1172 } else if (dest->is_single_xmm()) {
1173 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1174 __ movflt(dest->as_xmm_float_reg(), src_addr);
1175
1176 } else if (dest->is_double_xmm()) {
1177 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1178 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1179
1180 } else if (dest->is_single_fpu()) {
1181 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1182 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1183 __ fld_s(src_addr);
1184
1185 } else if (dest->is_double_fpu()) {
1186 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1187 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1188 __ fld_d(src_addr);
1189
1190 } else {
1191 ShouldNotReachHere();
1192 }
1193 }
1194
1195
1196 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1197 if (src->is_single_stack()) {
1198 if (type == T_OBJECT || type == T_ARRAY) {
1199 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1200 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1201 } else {
1202 #ifndef _LP64
1203 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1204 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1205 #else
1206 //no pushl on 64bits
1207 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1208 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1209 #endif
1210 }
1211
1212 } else if (src->is_double_stack()) {
1213 #ifdef _LP64
1214 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1215 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1216 #else
1217 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1218 // push and pop the part at src + wordSize, adding wordSize for the previous push
1219 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1220 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1221 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1222 #endif // _LP64
1223
1224 } else {
1225 ShouldNotReachHere();
1226 }
1227 }
1228
1229
1230 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */, bool wide) {
1231 assert(src->is_address(), "should not call otherwise");
1232 assert(dest->is_register(), "should not call otherwise");
1233
1234 LIR_Address* addr = src->as_address_ptr();
1235 Address from_addr = as_Address(addr);
1236
1237 switch (type) {
1238 case T_BOOLEAN: // fall through
1239 case T_BYTE: // fall through
1240 case T_CHAR: // fall through
1241 case T_SHORT:
1242 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1243 // on pre P6 processors we may get partial register stalls
1244 // so blow away the value of to_rinfo before loading a
1245 // partial word into it. Do it here so that it precedes
1246 // the potential patch point below.
1247 __ xorptr(dest->as_register(), dest->as_register());
1248 }
1249 break;
1250 }
1251
1252 PatchingStub* patch = NULL;
1253 if (patch_code != lir_patch_none) {
1254 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1255 assert(from_addr.disp() != 0, "must have");
1256 }
1257 if (info != NULL) {
1258 add_debug_info_for_null_check_here(info);
1259 }
1260
1261 switch (type) {
1262 case T_FLOAT: {
1263 if (dest->is_single_xmm()) {
1264 __ movflt(dest->as_xmm_float_reg(), from_addr);
1265 } else {
1266 assert(dest->is_single_fpu(), "must be");
1267 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1268 __ fld_s(from_addr);
1269 }
1270 break;
1271 }
1272
1273 case T_DOUBLE: {
1274 if (dest->is_double_xmm()) {
1275 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1276 } else {
1277 assert(dest->is_double_fpu(), "must be");
1278 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1279 __ fld_d(from_addr);
1280 }
1281 break;
1282 }
1283
1284 case T_OBJECT: // fall through
1285 case T_ARRAY: // fall through
1286 #ifdef _LP64
1287 if (UseCompressedOops && !wide) {
1288 __ movl(dest->as_register(), from_addr);
1289 } else {
1290 __ movptr(dest->as_register(), from_addr);
1291 }
1292 break;
1293 #endif // _L64
1294 case T_ADDRESS:
1295 __ movptr(dest->as_register(), from_addr);
1296 break;
1297 case T_INT:
1298 __ movl(dest->as_register(), from_addr);
1299 break;
1300
1301 case T_LONG: {
1302 Register to_lo = dest->as_register_lo();
1303 Register to_hi = dest->as_register_hi();
1304 #ifdef _LP64
1305 __ movptr(to_lo, as_Address_lo(addr));
1306 #else
1307 Register base = addr->base()->as_register();
1308 Register index = noreg;
1309 if (addr->index()->is_register()) {
1310 index = addr->index()->as_register();
1311 }
1312 if ((base == to_lo && index == to_hi) ||
1313 (base == to_hi && index == to_lo)) {
1314 // addresses with 2 registers are only formed as a result of
1315 // array access so this code will never have to deal with
1316 // patches or null checks.
1317 assert(info == NULL && patch == NULL, "must be");
1318 __ lea(to_hi, as_Address(addr));
1319 __ movl(to_lo, Address(to_hi, 0));
1320 __ movl(to_hi, Address(to_hi, BytesPerWord));
1321 } else if (base == to_lo || index == to_lo) {
1322 assert(base != to_hi, "can't be");
1323 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1324 __ movl(to_hi, as_Address_hi(addr));
1325 if (patch != NULL) {
1326 patching_epilog(patch, lir_patch_high, base, info);
1327 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1328 patch_code = lir_patch_low;
1329 }
1330 __ movl(to_lo, as_Address_lo(addr));
1331 } else {
1332 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1333 __ movl(to_lo, as_Address_lo(addr));
1334 if (patch != NULL) {
1335 patching_epilog(patch, lir_patch_low, base, info);
1336 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1337 patch_code = lir_patch_high;
1338 }
1339 __ movl(to_hi, as_Address_hi(addr));
1340 }
1341 #endif // _LP64
1342 break;
1343 }
1344
1345 case T_BOOLEAN: // fall through
1346 case T_BYTE: {
1347 Register dest_reg = dest->as_register();
1348 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1349 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1350 __ movsbl(dest_reg, from_addr);
1351 } else {
1352 __ movb(dest_reg, from_addr);
1353 __ shll(dest_reg, 24);
1354 __ sarl(dest_reg, 24);
1355 }
1356 break;
1357 }
1358
1359 case T_CHAR: {
1360 Register dest_reg = dest->as_register();
1361 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1362 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1363 __ movzwl(dest_reg, from_addr);
1364 } else {
1365 __ movw(dest_reg, from_addr);
1366 }
1367 break;
1368 }
1369
1370 case T_SHORT: {
1371 Register dest_reg = dest->as_register();
1372 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1373 __ movswl(dest_reg, from_addr);
1374 } else {
1375 __ movw(dest_reg, from_addr);
1376 __ shll(dest_reg, 16);
1377 __ sarl(dest_reg, 16);
1378 }
1379 break;
1380 }
1381
1382 default:
1383 ShouldNotReachHere();
1384 }
1385
1386 if (patch != NULL) {
1387 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1388 }
1389
1390 if (type == T_ARRAY || type == T_OBJECT) {
1391 #ifdef _LP64
1392 if (UseCompressedOops && !wide) {
1393 __ decode_heap_oop(dest->as_register());
1394 }
1395 #endif
1396 __ verify_oop(dest->as_register());
1397 }
1398 }
1399
1400
1401 void LIR_Assembler::prefetchr(LIR_Opr src) {
1402 LIR_Address* addr = src->as_address_ptr();
1403 Address from_addr = as_Address(addr);
1404
1405 if (VM_Version::supports_sse()) {
1406 switch (ReadPrefetchInstr) {
1407 case 0:
1408 __ prefetchnta(from_addr); break;
1409 case 1:
1410 __ prefetcht0(from_addr); break;
1411 case 2:
1412 __ prefetcht2(from_addr); break;
1413 default:
1414 ShouldNotReachHere(); break;
1415 }
1416 } else if (VM_Version::supports_3dnow()) {
1417 __ prefetchr(from_addr);
1418 }
1419 }
1420
1421
1422 void LIR_Assembler::prefetchw(LIR_Opr src) {
1423 LIR_Address* addr = src->as_address_ptr();
1424 Address from_addr = as_Address(addr);
1425
1426 if (VM_Version::supports_sse()) {
1427 switch (AllocatePrefetchInstr) {
1428 case 0:
1429 __ prefetchnta(from_addr); break;
1430 case 1:
1431 __ prefetcht0(from_addr); break;
1432 case 2:
1433 __ prefetcht2(from_addr); break;
1434 case 3:
1435 __ prefetchw(from_addr); break;
1436 default:
1437 ShouldNotReachHere(); break;
1438 }
1439 } else if (VM_Version::supports_3dnow()) {
1440 __ prefetchw(from_addr);
1441 }
1442 }
1443
1444
1445 NEEDS_CLEANUP; // This could be static?
1446 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1447 int elem_size = type2aelembytes(type);
1448 switch (elem_size) {
1449 case 1: return Address::times_1;
1450 case 2: return Address::times_2;
1451 case 4: return Address::times_4;
1452 case 8: return Address::times_8;
1453 }
1454 ShouldNotReachHere();
1455 return Address::no_scale;
1456 }
1457
1458
1459 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1460 switch (op->code()) {
1461 case lir_idiv:
1462 case lir_irem:
1463 arithmetic_idiv(op->code(),
1464 op->in_opr1(),
1465 op->in_opr2(),
1466 op->in_opr3(),
1467 op->result_opr(),
1468 op->info());
1469 break;
1470 default: ShouldNotReachHere(); break;
1471 }
1472 }
1473
1474 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1475 #ifdef ASSERT
1476 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1477 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1478 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1479 #endif
1480
1481 if (op->cond() == lir_cond_always) {
1482 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1483 __ jmp (*(op->label()));
1484 } else {
1485 Assembler::Condition acond = Assembler::zero;
1486 if (op->code() == lir_cond_float_branch) {
1487 assert(op->ublock() != NULL, "must have unordered successor");
1488 __ jcc(Assembler::parity, *(op->ublock()->label()));
1489 switch(op->cond()) {
1490 case lir_cond_equal: acond = Assembler::equal; break;
1491 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1492 case lir_cond_less: acond = Assembler::below; break;
1493 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1494 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1495 case lir_cond_greater: acond = Assembler::above; break;
1496 default: ShouldNotReachHere();
1497 }
1498 } else {
1499 switch (op->cond()) {
1500 case lir_cond_equal: acond = Assembler::equal; break;
1501 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1502 case lir_cond_less: acond = Assembler::less; break;
1503 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1504 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1505 case lir_cond_greater: acond = Assembler::greater; break;
1506 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1507 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1508 default: ShouldNotReachHere();
1509 }
1510 }
1511 __ jcc(acond,*(op->label()));
1512 }
1513 }
1514
1515 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1516 LIR_Opr src = op->in_opr();
1517 LIR_Opr dest = op->result_opr();
1518
1519 switch (op->bytecode()) {
1520 case Bytecodes::_i2l:
1521 #ifdef _LP64
1522 __ movl2ptr(dest->as_register_lo(), src->as_register());
1523 #else
1524 move_regs(src->as_register(), dest->as_register_lo());
1525 move_regs(src->as_register(), dest->as_register_hi());
1526 __ sarl(dest->as_register_hi(), 31);
1527 #endif // LP64
1528 break;
1529
1530 case Bytecodes::_l2i:
1531 move_regs(src->as_register_lo(), dest->as_register());
1532 break;
1533
1534 case Bytecodes::_i2b:
1535 move_regs(src->as_register(), dest->as_register());
1536 __ sign_extend_byte(dest->as_register());
1537 break;
1538
1539 case Bytecodes::_i2c:
1540 move_regs(src->as_register(), dest->as_register());
1541 __ andl(dest->as_register(), 0xFFFF);
1542 break;
1543
1544 case Bytecodes::_i2s:
1545 move_regs(src->as_register(), dest->as_register());
1546 __ sign_extend_short(dest->as_register());
1547 break;
1548
1549
1550 case Bytecodes::_f2d:
1551 case Bytecodes::_d2f:
1552 if (dest->is_single_xmm()) {
1553 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1554 } else if (dest->is_double_xmm()) {
1555 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1556 } else {
1557 assert(src->fpu() == dest->fpu(), "register must be equal");
1558 // do nothing (float result is rounded later through spilling)
1559 }
1560 break;
1561
1562 case Bytecodes::_i2f:
1563 case Bytecodes::_i2d:
1564 if (dest->is_single_xmm()) {
1565 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1566 } else if (dest->is_double_xmm()) {
1567 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1568 } else {
1569 assert(dest->fpu() == 0, "result must be on TOS");
1570 __ movl(Address(rsp, 0), src->as_register());
1571 __ fild_s(Address(rsp, 0));
1572 }
1573 break;
1574
1575 case Bytecodes::_f2i:
1576 case Bytecodes::_d2i:
1577 if (src->is_single_xmm()) {
1578 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1579 } else if (src->is_double_xmm()) {
1580 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1581 } else {
1582 assert(src->fpu() == 0, "input must be on TOS");
1583 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1584 __ fist_s(Address(rsp, 0));
1585 __ movl(dest->as_register(), Address(rsp, 0));
1586 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1587 }
1588
1589 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1590 assert(op->stub() != NULL, "stub required");
1591 __ cmpl(dest->as_register(), 0x80000000);
1592 __ jcc(Assembler::equal, *op->stub()->entry());
1593 __ bind(*op->stub()->continuation());
1594 break;
1595
1596 case Bytecodes::_l2f:
1597 case Bytecodes::_l2d:
1598 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1599 assert(dest->fpu() == 0, "result must be on TOS");
1600
1601 __ movptr(Address(rsp, 0), src->as_register_lo());
1602 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1603 __ fild_d(Address(rsp, 0));
1604 // float result is rounded later through spilling
1605 break;
1606
1607 case Bytecodes::_f2l:
1608 case Bytecodes::_d2l:
1609 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1610 assert(src->fpu() == 0, "input must be on TOS");
1611 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1612
1613 // instruction sequence too long to inline it here
1614 {
1615 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1616 }
1617 break;
1618
1619 default: ShouldNotReachHere();
1620 }
1621 }
1622
1623 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1624 if (op->init_check()) {
1625 __ cmpl(Address(op->klass()->as_register(),
1626 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1627 instanceKlass::fully_initialized);
1628 add_debug_info_for_null_check_here(op->stub()->info());
1629 __ jcc(Assembler::notEqual, *op->stub()->entry());
1630 }
1631 __ allocate_object(op->obj()->as_register(),
1632 op->tmp1()->as_register(),
1633 op->tmp2()->as_register(),
1634 op->header_size(),
1635 op->object_size(),
1636 op->klass()->as_register(),
1637 *op->stub()->entry());
1638 __ bind(*op->stub()->continuation());
1639 }
1640
1641 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1642 if (UseSlowPath ||
1643 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1644 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1645 __ jmp(*op->stub()->entry());
1646 } else {
1647 Register len = op->len()->as_register();
1648 Register tmp1 = op->tmp1()->as_register();
1649 Register tmp2 = op->tmp2()->as_register();
1650 Register tmp3 = op->tmp3()->as_register();
1651 if (len == tmp1) {
1652 tmp1 = tmp3;
1653 } else if (len == tmp2) {
1654 tmp2 = tmp3;
1655 } else if (len == tmp3) {
1656 // everything is ok
1657 } else {
1658 __ mov(tmp3, len);
1659 }
1660 __ allocate_array(op->obj()->as_register(),
1661 len,
1662 tmp1,
1663 tmp2,
1664 arrayOopDesc::header_size(op->type()),
1665 array_element_size(op->type()),
1666 op->klass()->as_register(),
1667 *op->stub()->entry());
1668 }
1669 __ bind(*op->stub()->continuation());
1670 }
1671
1672 void LIR_Assembler::type_profile_helper(Register mdo,
1673 ciMethodData *md, ciProfileData *data,
1674 Register recv, Label* update_done) {
1675 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1676 Label next_test;
1677 // See if the receiver is receiver[n].
1678 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1679 __ jccb(Assembler::notEqual, next_test);
1680 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1681 __ addptr(data_addr, DataLayout::counter_increment);
1682 __ jmp(*update_done);
1683 __ bind(next_test);
1684 }
1685
1686 // Didn't find receiver; find next empty slot and fill it in
1687 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1688 Label next_test;
1689 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1690 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1691 __ jccb(Assembler::notEqual, next_test);
1692 __ movptr(recv_addr, recv);
1693 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1694 __ jmp(*update_done);
1695 __ bind(next_test);
1696 }
1697 }
1698
1699 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1700 // we always need a stub for the failure case.
1701 CodeStub* stub = op->stub();
1702 Register obj = op->object()->as_register();
1703 Register k_RInfo = op->tmp1()->as_register();
1704 Register klass_RInfo = op->tmp2()->as_register();
1705 Register dst = op->result_opr()->as_register();
1706 ciKlass* k = op->klass();
1707 Register Rtmp1 = noreg;
1708
1709 // check if it needs to be profiled
1710 ciMethodData* md;
1711 ciProfileData* data;
1712
1713 if (op->should_profile()) {
1714 ciMethod* method = op->profiled_method();
1715 assert(method != NULL, "Should have method");
1716 int bci = op->profiled_bci();
1717 md = method->method_data();
1718 if (md == NULL) {
1719 bailout("out of memory building methodDataOop");
1720 return;
1721 }
1722 data = md->bci_to_data(bci);
1723 assert(data != NULL, "need data for type check");
1724 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1725 }
1726 Label profile_cast_success, profile_cast_failure;
1727 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1728 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1729
1730 if (obj == k_RInfo) {
1731 k_RInfo = dst;
1732 } else if (obj == klass_RInfo) {
1733 klass_RInfo = dst;
1734 }
1735 if (k->is_loaded() && LP64_ONLY(!UseCompressedOops) NOT_LP64(true)) {
1736 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1737 } else {
1738 Rtmp1 = op->tmp3()->as_register();
1739 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1740 }
1741
1742 assert_different_registers(obj, k_RInfo, klass_RInfo);
1743 if (!k->is_loaded()) {
1744 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1745 } else {
1746 #ifdef _LP64
1747 __ movoop(k_RInfo, k->constant_encoding());
1748 #endif // _LP64
1749 }
1750 assert(obj != k_RInfo, "must be different");
1751
1752 __ cmpptr(obj, (int32_t)NULL_WORD);
1753 if (op->should_profile()) {
1754 Label not_null;
1755 __ jccb(Assembler::notEqual, not_null);
1756 // Object is null; update MDO and exit
1757 Register mdo = klass_RInfo;
1758 __ movoop(mdo, md->constant_encoding());
1759 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1760 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1761 __ orl(data_addr, header_bits);
1762 __ jmp(*obj_is_null);
1763 __ bind(not_null);
1764 } else {
1765 __ jcc(Assembler::equal, *obj_is_null);
1766 }
1767 __ verify_oop(obj);
1768
1769 if (op->fast_check()) {
1770 // get object class
1771 // not a safepoint as obj null check happens earlier
1772 #ifdef _LP64
1773 if (UseCompressedOops) {
1774 __ load_klass(Rtmp1, obj);
1775 __ cmpl(k_RInfo, Rtmp1);
1776 } else {
1777 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1778 }
1779 #else
1780 if (k->is_loaded()) {
1781 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1782 } else {
1783 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1784 }
1785 #endif
1786 __ jcc(Assembler::notEqual, *failure_target);
1787 // successful cast, fall through to profile or jump
1788 } else {
1789 // get object class
1790 // not a safepoint as obj null check happens earlier
1791 __ load_klass(klass_RInfo, obj);
1792 if (k->is_loaded()) {
1793 // See if we get an immediate positive hit
1794 #ifdef _LP64
1795 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1796 #else
1797 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1798 #endif // _LP64
1799 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1800 __ jcc(Assembler::notEqual, *failure_target);
1801 // successful cast, fall through to profile or jump
1802 } else {
1803 // See if we get an immediate positive hit
1804 __ jcc(Assembler::equal, *success_target);
1805 // check for self
1806 #ifdef _LP64
1807 __ cmpptr(klass_RInfo, k_RInfo);
1808 #else
1809 __ cmpoop(klass_RInfo, k->constant_encoding());
1810 #endif // _LP64
1811 __ jcc(Assembler::equal, *success_target);
1812
1813 __ push(klass_RInfo);
1814 #ifdef _LP64
1815 __ push(k_RInfo);
1816 #else
1817 __ pushoop(k->constant_encoding());
1818 #endif // _LP64
1819 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1820 __ pop(klass_RInfo);
1821 __ pop(klass_RInfo);
1822 // result is a boolean
1823 __ cmpl(klass_RInfo, 0);
1824 __ jcc(Assembler::equal, *failure_target);
1825 // successful cast, fall through to profile or jump
1826 }
1827 } else {
1828 // perform the fast part of the checking logic
1829 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1830 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1831 __ push(klass_RInfo);
1832 __ push(k_RInfo);
1833 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1834 __ pop(klass_RInfo);
1835 __ pop(k_RInfo);
1836 // result is a boolean
1837 __ cmpl(k_RInfo, 0);
1838 __ jcc(Assembler::equal, *failure_target);
1839 // successful cast, fall through to profile or jump
1840 }
1841 }
1842 if (op->should_profile()) {
1843 Register mdo = klass_RInfo, recv = k_RInfo;
1844 __ bind(profile_cast_success);
1845 __ movoop(mdo, md->constant_encoding());
1846 __ load_klass(recv, obj);
1847 Label update_done;
1848 type_profile_helper(mdo, md, data, recv, success);
1849 __ jmp(*success);
1850
1851 __ bind(profile_cast_failure);
1852 __ movoop(mdo, md->constant_encoding());
1853 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1854 __ subptr(counter_addr, DataLayout::counter_increment);
1855 __ jmp(*failure);
1856 }
1857 __ jmp(*success);
1858 }
1859
1860
1861 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1862 LIR_Code code = op->code();
1863 if (code == lir_store_check) {
1864 Register value = op->object()->as_register();
1865 Register array = op->array()->as_register();
1866 Register k_RInfo = op->tmp1()->as_register();
1867 Register klass_RInfo = op->tmp2()->as_register();
1868 Register Rtmp1 = op->tmp3()->as_register();
1869
1870 CodeStub* stub = op->stub();
1871
1872 // check if it needs to be profiled
1873 ciMethodData* md;
1874 ciProfileData* data;
1875
1876 if (op->should_profile()) {
1877 ciMethod* method = op->profiled_method();
1878 assert(method != NULL, "Should have method");
1879 int bci = op->profiled_bci();
1880 md = method->method_data();
1881 if (md == NULL) {
1882 bailout("out of memory building methodDataOop");
1883 return;
1884 }
1885 data = md->bci_to_data(bci);
1886 assert(data != NULL, "need data for type check");
1887 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1888 }
1889 Label profile_cast_success, profile_cast_failure, done;
1890 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1891 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1892
1893 __ cmpptr(value, (int32_t)NULL_WORD);
1894 if (op->should_profile()) {
1895 Label not_null;
1896 __ jccb(Assembler::notEqual, not_null);
1897 // Object is null; update MDO and exit
1898 Register mdo = klass_RInfo;
1899 __ movoop(mdo, md->constant_encoding());
1900 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1901 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1902 __ orl(data_addr, header_bits);
1903 __ jmp(done);
1904 __ bind(not_null);
1905 } else {
1906 __ jcc(Assembler::equal, done);
1907 }
1908
1909 add_debug_info_for_null_check_here(op->info_for_exception());
1910 __ load_klass(k_RInfo, array);
1911 __ load_klass(klass_RInfo, value);
1912
1913 // get instance klass (it's already uncompressed)
1914 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1915 // perform the fast part of the checking logic
1916 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1917 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1918 __ push(klass_RInfo);
1919 __ push(k_RInfo);
1920 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1921 __ pop(klass_RInfo);
1922 __ pop(k_RInfo);
1923 // result is a boolean
1924 __ cmpl(k_RInfo, 0);
1925 __ jcc(Assembler::equal, *failure_target);
1926 // fall through to the success case
1927
1928 if (op->should_profile()) {
1929 Register mdo = klass_RInfo, recv = k_RInfo;
1930 __ bind(profile_cast_success);
1931 __ movoop(mdo, md->constant_encoding());
1932 __ load_klass(recv, value);
1933 Label update_done;
1934 type_profile_helper(mdo, md, data, recv, &done);
1935 __ jmpb(done);
1936
1937 __ bind(profile_cast_failure);
1938 __ movoop(mdo, md->constant_encoding());
1939 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1940 __ subptr(counter_addr, DataLayout::counter_increment);
1941 __ jmp(*stub->entry());
1942 }
1943
1944 __ bind(done);
1945 } else
1946 if (code == lir_checkcast) {
1947 Register obj = op->object()->as_register();
1948 Register dst = op->result_opr()->as_register();
1949 Label success;
1950 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1951 __ bind(success);
1952 if (dst != obj) {
1953 __ mov(dst, obj);
1954 }
1955 } else
1956 if (code == lir_instanceof) {
1957 Register obj = op->object()->as_register();
1958 Register dst = op->result_opr()->as_register();
1959 Label success, failure, done;
1960 emit_typecheck_helper(op, &success, &failure, &failure);
1961 __ bind(failure);
1962 __ xorptr(dst, dst);
1963 __ jmpb(done);
1964 __ bind(success);
1965 __ movptr(dst, 1);
1966 __ bind(done);
1967 } else {
1968 ShouldNotReachHere();
1969 }
1970
1971 }
1972
1973
1974 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1975 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1976 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1977 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1978 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1979 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1980 Register addr = op->addr()->as_register();
1981 if (os::is_MP()) {
1982 __ lock();
1983 }
1984 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1985
1986 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1987 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1988 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1989 Register newval = op->new_value()->as_register();
1990 Register cmpval = op->cmp_value()->as_register();
1991 assert(cmpval == rax, "wrong register");
1992 assert(newval != NULL, "new val must be register");
1993 assert(cmpval != newval, "cmp and new values must be in different registers");
1994 assert(cmpval != addr, "cmp and addr must be in different registers");
1995 assert(newval != addr, "new value and addr must be in different registers");
1996
1997 if ( op->code() == lir_cas_obj) {
1998 #ifdef _LP64
1999 if (UseCompressedOops) {
2000 __ mov(rscratch1, cmpval);
2001 __ encode_heap_oop(cmpval);
2002 __ mov(rscratch2, newval);
2003 __ encode_heap_oop(rscratch2);
2004 if (os::is_MP()) {
2005 __ lock();
2006 }
2007 __ cmpxchgl(rscratch2, Address(addr, 0));
2008 __ mov(cmpval, rscratch1);
2009 } else
2010 #endif
2011 {
2012 if (os::is_MP()) {
2013 __ lock();
2014 }
2015 __ cmpxchgptr(newval, Address(addr, 0));
2016 }
2017 } else {
2018 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2019 if (os::is_MP()) {
2020 __ lock();
2021 }
2022 __ cmpxchgl(newval, Address(addr, 0));
2023 }
2024 #ifdef _LP64
2025 } else if (op->code() == lir_cas_long) {
2026 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2027 Register newval = op->new_value()->as_register_lo();
2028 Register cmpval = op->cmp_value()->as_register_lo();
2029 assert(cmpval == rax, "wrong register");
2030 assert(newval != NULL, "new val must be register");
2031 assert(cmpval != newval, "cmp and new values must be in different registers");
2032 assert(cmpval != addr, "cmp and addr must be in different registers");
2033 assert(newval != addr, "new value and addr must be in different registers");
2034 if (os::is_MP()) {
2035 __ lock();
2036 }
2037 __ cmpxchgq(newval, Address(addr, 0));
2038 #endif // _LP64
2039 } else {
2040 Unimplemented();
2041 }
2042 }
2043
2044 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
2045 Assembler::Condition acond, ncond;
2046 switch (condition) {
2047 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2048 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2049 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2050 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2051 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2052 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2053 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2054 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2055 default: ShouldNotReachHere();
2056 }
2057
2058 if (opr1->is_cpu_register()) {
2059 reg2reg(opr1, result);
2060 } else if (opr1->is_stack()) {
2061 stack2reg(opr1, result, result->type());
2062 } else if (opr1->is_constant()) {
2063 const2reg(opr1, result, lir_patch_none, NULL);
2064 } else {
2065 ShouldNotReachHere();
2066 }
2067
2068 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2069 // optimized version that does not require a branch
2070 if (opr2->is_single_cpu()) {
2071 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2072 __ cmov(ncond, result->as_register(), opr2->as_register());
2073 } else if (opr2->is_double_cpu()) {
2074 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2075 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2076 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2077 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2078 } else if (opr2->is_single_stack()) {
2079 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2080 } else if (opr2->is_double_stack()) {
2081 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2082 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2083 } else {
2084 ShouldNotReachHere();
2085 }
2086
2087 } else {
2088 Label skip;
2089 __ jcc (acond, skip);
2090 if (opr2->is_cpu_register()) {
2091 reg2reg(opr2, result);
2092 } else if (opr2->is_stack()) {
2093 stack2reg(opr2, result, result->type());
2094 } else if (opr2->is_constant()) {
2095 const2reg(opr2, result, lir_patch_none, NULL);
2096 } else {
2097 ShouldNotReachHere();
2098 }
2099 __ bind(skip);
2100 }
2101 }
2102
2103
2104 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2105 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2106
2107 if (left->is_single_cpu()) {
2108 assert(left == dest, "left and dest must be equal");
2109 Register lreg = left->as_register();
2110
2111 if (right->is_single_cpu()) {
2112 // cpu register - cpu register
2113 Register rreg = right->as_register();
2114 switch (code) {
2115 case lir_add: __ addl (lreg, rreg); break;
2116 case lir_sub: __ subl (lreg, rreg); break;
2117 case lir_mul: __ imull(lreg, rreg); break;
2118 default: ShouldNotReachHere();
2119 }
2120
2121 } else if (right->is_stack()) {
2122 // cpu register - stack
2123 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2124 switch (code) {
2125 case lir_add: __ addl(lreg, raddr); break;
2126 case lir_sub: __ subl(lreg, raddr); break;
2127 default: ShouldNotReachHere();
2128 }
2129
2130 } else if (right->is_constant()) {
2131 // cpu register - constant
2132 jint c = right->as_constant_ptr()->as_jint();
2133 switch (code) {
2134 case lir_add: {
2135 __ incrementl(lreg, c);
2136 break;
2137 }
2138 case lir_sub: {
2139 __ decrementl(lreg, c);
2140 break;
2141 }
2142 default: ShouldNotReachHere();
2143 }
2144
2145 } else {
2146 ShouldNotReachHere();
2147 }
2148
2149 } else if (left->is_double_cpu()) {
2150 assert(left == dest, "left and dest must be equal");
2151 Register lreg_lo = left->as_register_lo();
2152 Register lreg_hi = left->as_register_hi();
2153
2154 if (right->is_double_cpu()) {
2155 // cpu register - cpu register
2156 Register rreg_lo = right->as_register_lo();
2157 Register rreg_hi = right->as_register_hi();
2158 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2159 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2160 switch (code) {
2161 case lir_add:
2162 __ addptr(lreg_lo, rreg_lo);
2163 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2164 break;
2165 case lir_sub:
2166 __ subptr(lreg_lo, rreg_lo);
2167 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2168 break;
2169 case lir_mul:
2170 #ifdef _LP64
2171 __ imulq(lreg_lo, rreg_lo);
2172 #else
2173 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2174 __ imull(lreg_hi, rreg_lo);
2175 __ imull(rreg_hi, lreg_lo);
2176 __ addl (rreg_hi, lreg_hi);
2177 __ mull (rreg_lo);
2178 __ addl (lreg_hi, rreg_hi);
2179 #endif // _LP64
2180 break;
2181 default:
2182 ShouldNotReachHere();
2183 }
2184
2185 } else if (right->is_constant()) {
2186 // cpu register - constant
2187 #ifdef _LP64
2188 jlong c = right->as_constant_ptr()->as_jlong_bits();
2189 __ movptr(r10, (intptr_t) c);
2190 switch (code) {
2191 case lir_add:
2192 __ addptr(lreg_lo, r10);
2193 break;
2194 case lir_sub:
2195 __ subptr(lreg_lo, r10);
2196 break;
2197 default:
2198 ShouldNotReachHere();
2199 }
2200 #else
2201 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2202 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2203 switch (code) {
2204 case lir_add:
2205 __ addptr(lreg_lo, c_lo);
2206 __ adcl(lreg_hi, c_hi);
2207 break;
2208 case lir_sub:
2209 __ subptr(lreg_lo, c_lo);
2210 __ sbbl(lreg_hi, c_hi);
2211 break;
2212 default:
2213 ShouldNotReachHere();
2214 }
2215 #endif // _LP64
2216
2217 } else {
2218 ShouldNotReachHere();
2219 }
2220
2221 } else if (left->is_single_xmm()) {
2222 assert(left == dest, "left and dest must be equal");
2223 XMMRegister lreg = left->as_xmm_float_reg();
2224
2225 if (right->is_single_xmm()) {
2226 XMMRegister rreg = right->as_xmm_float_reg();
2227 switch (code) {
2228 case lir_add: __ addss(lreg, rreg); break;
2229 case lir_sub: __ subss(lreg, rreg); break;
2230 case lir_mul_strictfp: // fall through
2231 case lir_mul: __ mulss(lreg, rreg); break;
2232 case lir_div_strictfp: // fall through
2233 case lir_div: __ divss(lreg, rreg); break;
2234 default: ShouldNotReachHere();
2235 }
2236 } else {
2237 Address raddr;
2238 if (right->is_single_stack()) {
2239 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2240 } else if (right->is_constant()) {
2241 // hack for now
2242 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2243 } else {
2244 ShouldNotReachHere();
2245 }
2246 switch (code) {
2247 case lir_add: __ addss(lreg, raddr); break;
2248 case lir_sub: __ subss(lreg, raddr); break;
2249 case lir_mul_strictfp: // fall through
2250 case lir_mul: __ mulss(lreg, raddr); break;
2251 case lir_div_strictfp: // fall through
2252 case lir_div: __ divss(lreg, raddr); break;
2253 default: ShouldNotReachHere();
2254 }
2255 }
2256
2257 } else if (left->is_double_xmm()) {
2258 assert(left == dest, "left and dest must be equal");
2259
2260 XMMRegister lreg = left->as_xmm_double_reg();
2261 if (right->is_double_xmm()) {
2262 XMMRegister rreg = right->as_xmm_double_reg();
2263 switch (code) {
2264 case lir_add: __ addsd(lreg, rreg); break;
2265 case lir_sub: __ subsd(lreg, rreg); break;
2266 case lir_mul_strictfp: // fall through
2267 case lir_mul: __ mulsd(lreg, rreg); break;
2268 case lir_div_strictfp: // fall through
2269 case lir_div: __ divsd(lreg, rreg); break;
2270 default: ShouldNotReachHere();
2271 }
2272 } else {
2273 Address raddr;
2274 if (right->is_double_stack()) {
2275 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2276 } else if (right->is_constant()) {
2277 // hack for now
2278 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2279 } else {
2280 ShouldNotReachHere();
2281 }
2282 switch (code) {
2283 case lir_add: __ addsd(lreg, raddr); break;
2284 case lir_sub: __ subsd(lreg, raddr); break;
2285 case lir_mul_strictfp: // fall through
2286 case lir_mul: __ mulsd(lreg, raddr); break;
2287 case lir_div_strictfp: // fall through
2288 case lir_div: __ divsd(lreg, raddr); break;
2289 default: ShouldNotReachHere();
2290 }
2291 }
2292
2293 } else if (left->is_single_fpu()) {
2294 assert(dest->is_single_fpu(), "fpu stack allocation required");
2295
2296 if (right->is_single_fpu()) {
2297 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2298
2299 } else {
2300 assert(left->fpu_regnr() == 0, "left must be on TOS");
2301 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2302
2303 Address raddr;
2304 if (right->is_single_stack()) {
2305 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2306 } else if (right->is_constant()) {
2307 address const_addr = float_constant(right->as_jfloat());
2308 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2309 // hack for now
2310 raddr = __ as_Address(InternalAddress(const_addr));
2311 } else {
2312 ShouldNotReachHere();
2313 }
2314
2315 switch (code) {
2316 case lir_add: __ fadd_s(raddr); break;
2317 case lir_sub: __ fsub_s(raddr); break;
2318 case lir_mul_strictfp: // fall through
2319 case lir_mul: __ fmul_s(raddr); break;
2320 case lir_div_strictfp: // fall through
2321 case lir_div: __ fdiv_s(raddr); break;
2322 default: ShouldNotReachHere();
2323 }
2324 }
2325
2326 } else if (left->is_double_fpu()) {
2327 assert(dest->is_double_fpu(), "fpu stack allocation required");
2328
2329 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2330 // Double values require special handling for strictfp mul/div on x86
2331 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2332 __ fmulp(left->fpu_regnrLo() + 1);
2333 }
2334
2335 if (right->is_double_fpu()) {
2336 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2337
2338 } else {
2339 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2340 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2341
2342 Address raddr;
2343 if (right->is_double_stack()) {
2344 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2345 } else if (right->is_constant()) {
2346 // hack for now
2347 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2348 } else {
2349 ShouldNotReachHere();
2350 }
2351
2352 switch (code) {
2353 case lir_add: __ fadd_d(raddr); break;
2354 case lir_sub: __ fsub_d(raddr); break;
2355 case lir_mul_strictfp: // fall through
2356 case lir_mul: __ fmul_d(raddr); break;
2357 case lir_div_strictfp: // fall through
2358 case lir_div: __ fdiv_d(raddr); break;
2359 default: ShouldNotReachHere();
2360 }
2361 }
2362
2363 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2364 // Double values require special handling for strictfp mul/div on x86
2365 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2366 __ fmulp(dest->fpu_regnrLo() + 1);
2367 }
2368
2369 } else if (left->is_single_stack() || left->is_address()) {
2370 assert(left == dest, "left and dest must be equal");
2371
2372 Address laddr;
2373 if (left->is_single_stack()) {
2374 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2375 } else if (left->is_address()) {
2376 laddr = as_Address(left->as_address_ptr());
2377 } else {
2378 ShouldNotReachHere();
2379 }
2380
2381 if (right->is_single_cpu()) {
2382 Register rreg = right->as_register();
2383 switch (code) {
2384 case lir_add: __ addl(laddr, rreg); break;
2385 case lir_sub: __ subl(laddr, rreg); break;
2386 default: ShouldNotReachHere();
2387 }
2388 } else if (right->is_constant()) {
2389 jint c = right->as_constant_ptr()->as_jint();
2390 switch (code) {
2391 case lir_add: {
2392 __ incrementl(laddr, c);
2393 break;
2394 }
2395 case lir_sub: {
2396 __ decrementl(laddr, c);
2397 break;
2398 }
2399 default: ShouldNotReachHere();
2400 }
2401 } else {
2402 ShouldNotReachHere();
2403 }
2404
2405 } else {
2406 ShouldNotReachHere();
2407 }
2408 }
2409
2410 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2411 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2412 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2413 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2414
2415 bool left_is_tos = (left_index == 0);
2416 bool dest_is_tos = (dest_index == 0);
2417 int non_tos_index = (left_is_tos ? right_index : left_index);
2418
2419 switch (code) {
2420 case lir_add:
2421 if (pop_fpu_stack) __ faddp(non_tos_index);
2422 else if (dest_is_tos) __ fadd (non_tos_index);
2423 else __ fadda(non_tos_index);
2424 break;
2425
2426 case lir_sub:
2427 if (left_is_tos) {
2428 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2429 else if (dest_is_tos) __ fsub (non_tos_index);
2430 else __ fsubra(non_tos_index);
2431 } else {
2432 if (pop_fpu_stack) __ fsubp (non_tos_index);
2433 else if (dest_is_tos) __ fsubr (non_tos_index);
2434 else __ fsuba (non_tos_index);
2435 }
2436 break;
2437
2438 case lir_mul_strictfp: // fall through
2439 case lir_mul:
2440 if (pop_fpu_stack) __ fmulp(non_tos_index);
2441 else if (dest_is_tos) __ fmul (non_tos_index);
2442 else __ fmula(non_tos_index);
2443 break;
2444
2445 case lir_div_strictfp: // fall through
2446 case lir_div:
2447 if (left_is_tos) {
2448 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2449 else if (dest_is_tos) __ fdiv (non_tos_index);
2450 else __ fdivra(non_tos_index);
2451 } else {
2452 if (pop_fpu_stack) __ fdivp (non_tos_index);
2453 else if (dest_is_tos) __ fdivr (non_tos_index);
2454 else __ fdiva (non_tos_index);
2455 }
2456 break;
2457
2458 case lir_rem:
2459 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2460 __ fremr(noreg);
2461 break;
2462
2463 default:
2464 ShouldNotReachHere();
2465 }
2466 }
2467
2468
2469 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2470 if (value->is_double_xmm()) {
2471 switch(code) {
2472 case lir_abs :
2473 {
2474 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2475 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2476 }
2477 __ andpd(dest->as_xmm_double_reg(),
2478 ExternalAddress((address)double_signmask_pool));
2479 }
2480 break;
2481
2482 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2483 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2484 default : ShouldNotReachHere();
2485 }
2486
2487 } else if (value->is_double_fpu()) {
2488 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2489 switch(code) {
2490 case lir_log : __ flog() ; break;
2491 case lir_log10 : __ flog10() ; break;
2492 case lir_abs : __ fabs() ; break;
2493 case lir_sqrt : __ fsqrt(); break;
2494 case lir_sin :
2495 // Should consider not saving rbx, if not necessary
2496 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2497 break;
2498 case lir_cos :
2499 // Should consider not saving rbx, if not necessary
2500 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2501 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2502 break;
2503 case lir_tan :
2504 // Should consider not saving rbx, if not necessary
2505 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2506 break;
2507 default : ShouldNotReachHere();
2508 }
2509 } else {
2510 Unimplemented();
2511 }
2512 }
2513
2514 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2515 // assert(left->destroys_register(), "check");
2516 if (left->is_single_cpu()) {
2517 Register reg = left->as_register();
2518 if (right->is_constant()) {
2519 int val = right->as_constant_ptr()->as_jint();
2520 switch (code) {
2521 case lir_logic_and: __ andl (reg, val); break;
2522 case lir_logic_or: __ orl (reg, val); break;
2523 case lir_logic_xor: __ xorl (reg, val); break;
2524 default: ShouldNotReachHere();
2525 }
2526 } else if (right->is_stack()) {
2527 // added support for stack operands
2528 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2529 switch (code) {
2530 case lir_logic_and: __ andl (reg, raddr); break;
2531 case lir_logic_or: __ orl (reg, raddr); break;
2532 case lir_logic_xor: __ xorl (reg, raddr); break;
2533 default: ShouldNotReachHere();
2534 }
2535 } else {
2536 Register rright = right->as_register();
2537 switch (code) {
2538 case lir_logic_and: __ andptr (reg, rright); break;
2539 case lir_logic_or : __ orptr (reg, rright); break;
2540 case lir_logic_xor: __ xorptr (reg, rright); break;
2541 default: ShouldNotReachHere();
2542 }
2543 }
2544 move_regs(reg, dst->as_register());
2545 } else {
2546 Register l_lo = left->as_register_lo();
2547 Register l_hi = left->as_register_hi();
2548 if (right->is_constant()) {
2549 #ifdef _LP64
2550 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2551 switch (code) {
2552 case lir_logic_and:
2553 __ andq(l_lo, rscratch1);
2554 break;
2555 case lir_logic_or:
2556 __ orq(l_lo, rscratch1);
2557 break;
2558 case lir_logic_xor:
2559 __ xorq(l_lo, rscratch1);
2560 break;
2561 default: ShouldNotReachHere();
2562 }
2563 #else
2564 int r_lo = right->as_constant_ptr()->as_jint_lo();
2565 int r_hi = right->as_constant_ptr()->as_jint_hi();
2566 switch (code) {
2567 case lir_logic_and:
2568 __ andl(l_lo, r_lo);
2569 __ andl(l_hi, r_hi);
2570 break;
2571 case lir_logic_or:
2572 __ orl(l_lo, r_lo);
2573 __ orl(l_hi, r_hi);
2574 break;
2575 case lir_logic_xor:
2576 __ xorl(l_lo, r_lo);
2577 __ xorl(l_hi, r_hi);
2578 break;
2579 default: ShouldNotReachHere();
2580 }
2581 #endif // _LP64
2582 } else {
2583 #ifdef _LP64
2584 Register r_lo;
2585 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2586 r_lo = right->as_register();
2587 } else {
2588 r_lo = right->as_register_lo();
2589 }
2590 #else
2591 Register r_lo = right->as_register_lo();
2592 Register r_hi = right->as_register_hi();
2593 assert(l_lo != r_hi, "overwriting registers");
2594 #endif
2595 switch (code) {
2596 case lir_logic_and:
2597 __ andptr(l_lo, r_lo);
2598 NOT_LP64(__ andptr(l_hi, r_hi);)
2599 break;
2600 case lir_logic_or:
2601 __ orptr(l_lo, r_lo);
2602 NOT_LP64(__ orptr(l_hi, r_hi);)
2603 break;
2604 case lir_logic_xor:
2605 __ xorptr(l_lo, r_lo);
2606 NOT_LP64(__ xorptr(l_hi, r_hi);)
2607 break;
2608 default: ShouldNotReachHere();
2609 }
2610 }
2611
2612 Register dst_lo = dst->as_register_lo();
2613 Register dst_hi = dst->as_register_hi();
2614
2615 #ifdef _LP64
2616 move_regs(l_lo, dst_lo);
2617 #else
2618 if (dst_lo == l_hi) {
2619 assert(dst_hi != l_lo, "overwriting registers");
2620 move_regs(l_hi, dst_hi);
2621 move_regs(l_lo, dst_lo);
2622 } else {
2623 assert(dst_lo != l_hi, "overwriting registers");
2624 move_regs(l_lo, dst_lo);
2625 move_regs(l_hi, dst_hi);
2626 }
2627 #endif // _LP64
2628 }
2629 }
2630
2631
2632 // we assume that rax, and rdx can be overwritten
2633 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2634
2635 assert(left->is_single_cpu(), "left must be register");
2636 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2637 assert(result->is_single_cpu(), "result must be register");
2638
2639 // assert(left->destroys_register(), "check");
2640 // assert(right->destroys_register(), "check");
2641
2642 Register lreg = left->as_register();
2643 Register dreg = result->as_register();
2644
2645 if (right->is_constant()) {
2646 int divisor = right->as_constant_ptr()->as_jint();
2647 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2648 if (code == lir_idiv) {
2649 assert(lreg == rax, "must be rax,");
2650 assert(temp->as_register() == rdx, "tmp register must be rdx");
2651 __ cdql(); // sign extend into rdx:rax
2652 if (divisor == 2) {
2653 __ subl(lreg, rdx);
2654 } else {
2655 __ andl(rdx, divisor - 1);
2656 __ addl(lreg, rdx);
2657 }
2658 __ sarl(lreg, log2_intptr(divisor));
2659 move_regs(lreg, dreg);
2660 } else if (code == lir_irem) {
2661 Label done;
2662 __ mov(dreg, lreg);
2663 __ andl(dreg, 0x80000000 | (divisor - 1));
2664 __ jcc(Assembler::positive, done);
2665 __ decrement(dreg);
2666 __ orl(dreg, ~(divisor - 1));
2667 __ increment(dreg);
2668 __ bind(done);
2669 } else {
2670 ShouldNotReachHere();
2671 }
2672 } else {
2673 Register rreg = right->as_register();
2674 assert(lreg == rax, "left register must be rax,");
2675 assert(rreg != rdx, "right register must not be rdx");
2676 assert(temp->as_register() == rdx, "tmp register must be rdx");
2677
2678 move_regs(lreg, rax);
2679
2680 int idivl_offset = __ corrected_idivl(rreg);
2681 add_debug_info_for_div0(idivl_offset, info);
2682 if (code == lir_irem) {
2683 move_regs(rdx, dreg); // result is in rdx
2684 } else {
2685 move_regs(rax, dreg);
2686 }
2687 }
2688 }
2689
2690
2691 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2692 if (opr1->is_single_cpu()) {
2693 Register reg1 = opr1->as_register();
2694 if (opr2->is_single_cpu()) {
2695 // cpu register - cpu register
2696 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2697 __ cmpptr(reg1, opr2->as_register());
2698 } else {
2699 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2700 __ cmpl(reg1, opr2->as_register());
2701 }
2702 } else if (opr2->is_stack()) {
2703 // cpu register - stack
2704 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2705 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2706 } else {
2707 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2708 }
2709 } else if (opr2->is_constant()) {
2710 // cpu register - constant
2711 LIR_Const* c = opr2->as_constant_ptr();
2712 if (c->type() == T_INT) {
2713 __ cmpl(reg1, c->as_jint());
2714 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2715 // In 64bit oops are single register
2716 jobject o = c->as_jobject();
2717 if (o == NULL) {
2718 __ cmpptr(reg1, (int32_t)NULL_WORD);
2719 } else {
2720 #ifdef _LP64
2721 __ movoop(rscratch1, o);
2722 __ cmpptr(reg1, rscratch1);
2723 #else
2724 __ cmpoop(reg1, c->as_jobject());
2725 #endif // _LP64
2726 }
2727 } else {
2728 ShouldNotReachHere();
2729 }
2730 // cpu register - address
2731 } else if (opr2->is_address()) {
2732 if (op->info() != NULL) {
2733 add_debug_info_for_null_check_here(op->info());
2734 }
2735 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2736 } else {
2737 ShouldNotReachHere();
2738 }
2739
2740 } else if(opr1->is_double_cpu()) {
2741 Register xlo = opr1->as_register_lo();
2742 Register xhi = opr1->as_register_hi();
2743 if (opr2->is_double_cpu()) {
2744 #ifdef _LP64
2745 __ cmpptr(xlo, opr2->as_register_lo());
2746 #else
2747 // cpu register - cpu register
2748 Register ylo = opr2->as_register_lo();
2749 Register yhi = opr2->as_register_hi();
2750 __ subl(xlo, ylo);
2751 __ sbbl(xhi, yhi);
2752 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2753 __ orl(xhi, xlo);
2754 }
2755 #endif // _LP64
2756 } else if (opr2->is_constant()) {
2757 // cpu register - constant 0
2758 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2759 #ifdef _LP64
2760 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2761 #else
2762 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2763 __ orl(xhi, xlo);
2764 #endif // _LP64
2765 } else {
2766 ShouldNotReachHere();
2767 }
2768
2769 } else if (opr1->is_single_xmm()) {
2770 XMMRegister reg1 = opr1->as_xmm_float_reg();
2771 if (opr2->is_single_xmm()) {
2772 // xmm register - xmm register
2773 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2774 } else if (opr2->is_stack()) {
2775 // xmm register - stack
2776 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2777 } else if (opr2->is_constant()) {
2778 // xmm register - constant
2779 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2780 } else if (opr2->is_address()) {
2781 // xmm register - address
2782 if (op->info() != NULL) {
2783 add_debug_info_for_null_check_here(op->info());
2784 }
2785 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2786 } else {
2787 ShouldNotReachHere();
2788 }
2789
2790 } else if (opr1->is_double_xmm()) {
2791 XMMRegister reg1 = opr1->as_xmm_double_reg();
2792 if (opr2->is_double_xmm()) {
2793 // xmm register - xmm register
2794 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2795 } else if (opr2->is_stack()) {
2796 // xmm register - stack
2797 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2798 } else if (opr2->is_constant()) {
2799 // xmm register - constant
2800 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2801 } else if (opr2->is_address()) {
2802 // xmm register - address
2803 if (op->info() != NULL) {
2804 add_debug_info_for_null_check_here(op->info());
2805 }
2806 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2807 } else {
2808 ShouldNotReachHere();
2809 }
2810
2811 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2812 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2813 assert(opr2->is_fpu_register(), "both must be registers");
2814 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2815
2816 } else if (opr1->is_address() && opr2->is_constant()) {
2817 LIR_Const* c = opr2->as_constant_ptr();
2818 #ifdef _LP64
2819 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2820 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2821 __ movoop(rscratch1, c->as_jobject());
2822 }
2823 #endif // LP64
2824 if (op->info() != NULL) {
2825 add_debug_info_for_null_check_here(op->info());
2826 }
2827 // special case: address - constant
2828 LIR_Address* addr = opr1->as_address_ptr();
2829 if (c->type() == T_INT) {
2830 __ cmpl(as_Address(addr), c->as_jint());
2831 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2832 #ifdef _LP64
2833 // %%% Make this explode if addr isn't reachable until we figure out a
2834 // better strategy by giving noreg as the temp for as_Address
2835 __ cmpptr(rscratch1, as_Address(addr, noreg));
2836 #else
2837 __ cmpoop(as_Address(addr), c->as_jobject());
2838 #endif // _LP64
2839 } else {
2840 ShouldNotReachHere();
2841 }
2842
2843 } else {
2844 ShouldNotReachHere();
2845 }
2846 }
2847
2848 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2849 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2850 if (left->is_single_xmm()) {
2851 assert(right->is_single_xmm(), "must match");
2852 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2853 } else if (left->is_double_xmm()) {
2854 assert(right->is_double_xmm(), "must match");
2855 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2856
2857 } else {
2858 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2859 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2860
2861 assert(left->fpu() == 0, "left must be on TOS");
2862 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2863 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2864 }
2865 } else {
2866 assert(code == lir_cmp_l2i, "check");
2867 #ifdef _LP64
2868 Label done;
2869 Register dest = dst->as_register();
2870 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2871 __ movl(dest, -1);
2872 __ jccb(Assembler::less, done);
2873 __ set_byte_if_not_zero(dest);
2874 __ movzbl(dest, dest);
2875 __ bind(done);
2876 #else
2877 __ lcmp2int(left->as_register_hi(),
2878 left->as_register_lo(),
2879 right->as_register_hi(),
2880 right->as_register_lo());
2881 move_regs(left->as_register_hi(), dst->as_register());
2882 #endif // _LP64
2883 }
2884 }
2885
2886
2887 void LIR_Assembler::align_call(LIR_Code code) {
2888 if (os::is_MP()) {
2889 // make sure that the displacement word of the call ends up word aligned
2890 int offset = __ offset();
2891 switch (code) {
2892 case lir_static_call:
2893 case lir_optvirtual_call:
2894 case lir_dynamic_call:
2895 offset += NativeCall::displacement_offset;
2896 break;
2897 case lir_icvirtual_call:
2898 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2899 break;
2900 case lir_virtual_call: // currently, sparc-specific for niagara
2901 default: ShouldNotReachHere();
2902 }
2903 while (offset++ % BytesPerWord != 0) {
2904 __ nop();
2905 }
2906 }
2907 }
2908
2909
2910 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2911 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2912 "must be aligned");
2913 __ call(AddressLiteral(op->addr(), rtype));
2914 add_call_info(code_offset(), op->info());
2915 }
2916
2917
2918 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2919 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2920 __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2921 assert(!os::is_MP() ||
2922 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2923 "must be aligned");
2924 __ call(AddressLiteral(op->addr(), rh));
2925 add_call_info(code_offset(), op->info());
2926 }
2927
2928
2929 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2930 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2931 ShouldNotReachHere();
2932 }
2933
2934
2935 void LIR_Assembler::emit_static_call_stub() {
2936 address call_pc = __ pc();
2937 address stub = __ start_a_stub(call_stub_size);
2938 if (stub == NULL) {
2939 bailout("static call stub overflow");
2940 return;
2941 }
2942
2943 int start = __ offset();
2944 if (os::is_MP()) {
2945 // make sure that the displacement word of the call ends up word aligned
2946 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2947 while (offset++ % BytesPerWord != 0) {
2948 __ nop();
2949 }
2950 }
2951 __ relocate(static_stub_Relocation::spec(call_pc));
2952 __ movoop(rbx, (jobject)NULL);
2953 // must be set to -1 at code generation time
2954 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2955 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2956 __ jump(RuntimeAddress(__ pc()));
2957
2958 assert(__ offset() - start <= call_stub_size, "stub too big");
2959 __ end_a_stub();
2960 }
2961
2962
2963 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2964 assert(exceptionOop->as_register() == rax, "must match");
2965 assert(exceptionPC->as_register() == rdx, "must match");
2966
2967 // exception object is not added to oop map by LinearScan
2968 // (LinearScan assumes that no oops are in fixed registers)
2969 info->add_register_oop(exceptionOop);
2970 Runtime1::StubID unwind_id;
2971
2972 // get current pc information
2973 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2974 int pc_for_athrow_offset = __ offset();
2975 InternalAddress pc_for_athrow(__ pc());
2976 __ lea(exceptionPC->as_register(), pc_for_athrow);
2977 add_call_info(pc_for_athrow_offset, info); // for exception handler
2978
2979 __ verify_not_null_oop(rax);
2980 // search an exception handler (rax: exception oop, rdx: throwing pc)
2981 if (compilation()->has_fpu_code()) {
2982 unwind_id = Runtime1::handle_exception_id;
2983 } else {
2984 unwind_id = Runtime1::handle_exception_nofpu_id;
2985 }
2986 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2987
2988 // enough room for two byte trap
2989 __ nop();
2990 }
2991
2992
2993 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2994 assert(exceptionOop->as_register() == rax, "must match");
2995
2996 __ jmp(_unwind_handler_entry);
2997 }
2998
2999
3000 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
3001
3002 // optimized version for linear scan:
3003 // * count must be already in ECX (guaranteed by LinearScan)
3004 // * left and dest must be equal
3005 // * tmp must be unused
3006 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3007 assert(left == dest, "left and dest must be equal");
3008 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3009
3010 if (left->is_single_cpu()) {
3011 Register value = left->as_register();
3012 assert(value != SHIFT_count, "left cannot be ECX");
3013
3014 switch (code) {
3015 case lir_shl: __ shll(value); break;
3016 case lir_shr: __ sarl(value); break;
3017 case lir_ushr: __ shrl(value); break;
3018 default: ShouldNotReachHere();
3019 }
3020 } else if (left->is_double_cpu()) {
3021 Register lo = left->as_register_lo();
3022 Register hi = left->as_register_hi();
3023 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3024 #ifdef _LP64
3025 switch (code) {
3026 case lir_shl: __ shlptr(lo); break;
3027 case lir_shr: __ sarptr(lo); break;
3028 case lir_ushr: __ shrptr(lo); break;
3029 default: ShouldNotReachHere();
3030 }
3031 #else
3032
3033 switch (code) {
3034 case lir_shl: __ lshl(hi, lo); break;
3035 case lir_shr: __ lshr(hi, lo, true); break;
3036 case lir_ushr: __ lshr(hi, lo, false); break;
3037 default: ShouldNotReachHere();
3038 }
3039 #endif // LP64
3040 } else {
3041 ShouldNotReachHere();
3042 }
3043 }
3044
3045
3046 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3047 if (dest->is_single_cpu()) {
3048 // first move left into dest so that left is not destroyed by the shift
3049 Register value = dest->as_register();
3050 count = count & 0x1F; // Java spec
3051
3052 move_regs(left->as_register(), value);
3053 switch (code) {
3054 case lir_shl: __ shll(value, count); break;
3055 case lir_shr: __ sarl(value, count); break;
3056 case lir_ushr: __ shrl(value, count); break;
3057 default: ShouldNotReachHere();
3058 }
3059 } else if (dest->is_double_cpu()) {
3060 #ifndef _LP64
3061 Unimplemented();
3062 #else
3063 // first move left into dest so that left is not destroyed by the shift
3064 Register value = dest->as_register_lo();
3065 count = count & 0x1F; // Java spec
3066
3067 move_regs(left->as_register_lo(), value);
3068 switch (code) {
3069 case lir_shl: __ shlptr(value, count); break;
3070 case lir_shr: __ sarptr(value, count); break;
3071 case lir_ushr: __ shrptr(value, count); break;
3072 default: ShouldNotReachHere();
3073 }
3074 #endif // _LP64
3075 } else {
3076 ShouldNotReachHere();
3077 }
3078 }
3079
3080
3081 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3082 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3083 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3084 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3085 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3086 }
3087
3088
3089 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3090 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3091 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3092 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3093 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3094 }
3095
3096
3097 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3098 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3099 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3100 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3101 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3102 }
3103
3104
3105 // This code replaces a call to arraycopy; no exception may
3106 // be thrown in this code, they must be thrown in the System.arraycopy
3107 // activation frame; we could save some checks if this would not be the case
3108 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3109 ciArrayKlass* default_type = op->expected_type();
3110 Register src = op->src()->as_register();
3111 Register dst = op->dst()->as_register();
3112 Register src_pos = op->src_pos()->as_register();
3113 Register dst_pos = op->dst_pos()->as_register();
3114 Register length = op->length()->as_register();
3115 Register tmp = op->tmp()->as_register();
3116
3117 CodeStub* stub = op->stub();
3118 int flags = op->flags();
3119 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3120 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3121
3122 // if we don't know anything or it's an object array, just go through the generic arraycopy
3123 if (default_type == NULL) {
3124 Label done;
3125 // save outgoing arguments on stack in case call to System.arraycopy is needed
3126 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3127 // for interpreter calling conventions. Now we have to do it in new style conventions.
3128 // For the moment until C1 gets the new register allocator I just force all the
3129 // args to the right place (except the register args) and then on the back side
3130 // reload the register args properly if we go slow path. Yuck
3131
3132 // These are proper for the calling convention
3133
3134 store_parameter(length, 2);
3135 store_parameter(dst_pos, 1);
3136 store_parameter(dst, 0);
3137
3138 // these are just temporary placements until we need to reload
3139 store_parameter(src_pos, 3);
3140 store_parameter(src, 4);
3141 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3142
3143 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3144
3145 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3146 #ifdef _LP64
3147 // The arguments are in java calling convention so we can trivially shift them to C
3148 // convention
3149 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3150 __ mov(c_rarg0, j_rarg0);
3151 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3152 __ mov(c_rarg1, j_rarg1);
3153 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3154 __ mov(c_rarg2, j_rarg2);
3155 assert_different_registers(c_rarg3, j_rarg4);
3156 __ mov(c_rarg3, j_rarg3);
3157 #ifdef _WIN64
3158 // Allocate abi space for args but be sure to keep stack aligned
3159 __ subptr(rsp, 6*wordSize);
3160 store_parameter(j_rarg4, 4);
3161 __ call(RuntimeAddress(entry));
3162 __ addptr(rsp, 6*wordSize);
3163 #else
3164 __ mov(c_rarg4, j_rarg4);
3165 __ call(RuntimeAddress(entry));
3166 #endif // _WIN64
3167 #else
3168 __ push(length);
3169 __ push(dst_pos);
3170 __ push(dst);
3171 __ push(src_pos);
3172 __ push(src);
3173 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3174
3175 #endif // _LP64
3176
3177 __ cmpl(rax, 0);
3178 __ jcc(Assembler::equal, *stub->continuation());
3179
3180 // Reload values from the stack so they are where the stub
3181 // expects them.
3182 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3183 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3184 __ movptr (length, Address(rsp, 2*BytesPerWord));
3185 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3186 __ movptr (src, Address(rsp, 4*BytesPerWord));
3187 __ jmp(*stub->entry());
3188
3189 __ bind(*stub->continuation());
3190 return;
3191 }
3192
3193 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3194
3195 int elem_size = type2aelembytes(basic_type);
3196 int shift_amount;
3197 Address::ScaleFactor scale;
3198
3199 switch (elem_size) {
3200 case 1 :
3201 shift_amount = 0;
3202 scale = Address::times_1;
3203 break;
3204 case 2 :
3205 shift_amount = 1;
3206 scale = Address::times_2;
3207 break;
3208 case 4 :
3209 shift_amount = 2;
3210 scale = Address::times_4;
3211 break;
3212 case 8 :
3213 shift_amount = 3;
3214 scale = Address::times_8;
3215 break;
3216 default:
3217 ShouldNotReachHere();
3218 }
3219
3220 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3221 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3222 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3223 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3224
3225 // length and pos's are all sign extended at this point on 64bit
3226
3227 // test for NULL
3228 if (flags & LIR_OpArrayCopy::src_null_check) {
3229 __ testptr(src, src);
3230 __ jcc(Assembler::zero, *stub->entry());
3231 }
3232 if (flags & LIR_OpArrayCopy::dst_null_check) {
3233 __ testptr(dst, dst);
3234 __ jcc(Assembler::zero, *stub->entry());
3235 }
3236
3237 // check if negative
3238 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3239 __ testl(src_pos, src_pos);
3240 __ jcc(Assembler::less, *stub->entry());
3241 }
3242 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3243 __ testl(dst_pos, dst_pos);
3244 __ jcc(Assembler::less, *stub->entry());
3245 }
3246 if (flags & LIR_OpArrayCopy::length_positive_check) {
3247 __ testl(length, length);
3248 __ jcc(Assembler::less, *stub->entry());
3249 }
3250
3251 if (flags & LIR_OpArrayCopy::src_range_check) {
3252 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3253 __ cmpl(tmp, src_length_addr);
3254 __ jcc(Assembler::above, *stub->entry());
3255 }
3256 if (flags & LIR_OpArrayCopy::dst_range_check) {
3257 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3258 __ cmpl(tmp, dst_length_addr);
3259 __ jcc(Assembler::above, *stub->entry());
3260 }
3261
3262 if (flags & LIR_OpArrayCopy::type_check) {
3263 #ifdef _LP64
3264 if (UseCompressedOops) {
3265 __ movl(tmp, src_klass_addr);
3266 __ cmpl(tmp, dst_klass_addr);
3267 } else
3268 #endif
3269 {
3270 __ movptr(tmp, src_klass_addr);
3271 __ cmpptr(tmp, dst_klass_addr);
3272 }
3273 __ jcc(Assembler::notEqual, *stub->entry());
3274 }
3275
3276 #ifdef ASSERT
3277 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3278 // Sanity check the known type with the incoming class. For the
3279 // primitive case the types must match exactly with src.klass and
3280 // dst.klass each exactly matching the default type. For the
3281 // object array case, if no type check is needed then either the
3282 // dst type is exactly the expected type and the src type is a
3283 // subtype which we can't check or src is the same array as dst
3284 // but not necessarily exactly of type default_type.
3285 Label known_ok, halt;
3286 __ movoop(tmp, default_type->constant_encoding());
3287 #ifdef _LP64
3288 if (UseCompressedOops) {
3289 __ encode_heap_oop(tmp);
3290 }
3291 #endif
3292
3293 if (basic_type != T_OBJECT) {
3294 #ifdef _LP64
3295 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr);
3296 else
3297 #endif
3298 __ cmpptr(tmp, dst_klass_addr);
3299 __ jcc(Assembler::notEqual, halt);
3300 #ifdef _LP64
3301 if (UseCompressedOops) __ cmpl(tmp, src_klass_addr);
3302 else
3303 #endif
3304 __ cmpptr(tmp, src_klass_addr);
3305 __ jcc(Assembler::equal, known_ok);
3306 } else {
3307 #ifdef _LP64
3308 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr);
3309 else
3310 #endif
3311 __ cmpptr(tmp, dst_klass_addr);
3312 __ jcc(Assembler::equal, known_ok);
3313 __ cmpptr(src, dst);
3314 __ jcc(Assembler::equal, known_ok);
3315 }
3316 __ bind(halt);
3317 __ stop("incorrect type information in arraycopy");
3318 __ bind(known_ok);
3319 }
3320 #endif
3321
3322 if (shift_amount > 0 && basic_type != T_OBJECT) {
3323 __ shlptr(length, shift_amount);
3324 }
3325
3326 #ifdef _LP64
3327 assert_different_registers(c_rarg0, dst, dst_pos, length);
3328 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3329 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3330 assert_different_registers(c_rarg1, length);
3331 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3332 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3333 __ mov(c_rarg2, length);
3334
3335 #else
3336 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3337 store_parameter(tmp, 0);
3338 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3339 store_parameter(tmp, 1);
3340 store_parameter(length, 2);
3341 #endif // _LP64
3342 if (basic_type == T_OBJECT) {
3343 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3344 } else {
3345 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3346 }
3347
3348 __ bind(*stub->continuation());
3349 }
3350
3351
3352 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3353 Register obj = op->obj_opr()->as_register(); // may not be an oop
3354 Register hdr = op->hdr_opr()->as_register();
3355 Register lock = op->lock_opr()->as_register();
3356 if (!UseFastLocking) {
3357 __ jmp(*op->stub()->entry());
3358 } else if (op->code() == lir_lock) {
3359 Register scratch = noreg;
3360 if (UseBiasedLocking) {
3361 scratch = op->scratch_opr()->as_register();
3362 }
3363 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3364 // add debug info for NullPointerException only if one is possible
3365 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3366 if (op->info() != NULL) {
3367 add_debug_info_for_null_check(null_check_offset, op->info());
3368 }
3369 // done
3370 } else if (op->code() == lir_unlock) {
3371 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3372 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3373 } else {
3374 Unimplemented();
3375 }
3376 __ bind(*op->stub()->continuation());
3377 }
3378
3379
3380 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3381 ciMethod* method = op->profiled_method();
3382 int bci = op->profiled_bci();
3383
3384 // Update counter for all call types
3385 ciMethodData* md = method->method_data();
3386 if (md == NULL) {
3387 bailout("out of memory building methodDataOop");
3388 return;
3389 }
3390 ciProfileData* data = md->bci_to_data(bci);
3391 assert(data->is_CounterData(), "need CounterData for calls");
3392 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3393 Register mdo = op->mdo()->as_register();
3394 __ movoop(mdo, md->constant_encoding());
3395 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3396 Bytecodes::Code bc = method->java_code_at_bci(bci);
3397 // Perform additional virtual call profiling for invokevirtual and
3398 // invokeinterface bytecodes
3399 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3400 C1ProfileVirtualCalls) {
3401 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3402 Register recv = op->recv()->as_register();
3403 assert_different_registers(mdo, recv);
3404 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3405 ciKlass* known_klass = op->known_holder();
3406 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3407 // We know the type that will be seen at this call site; we can
3408 // statically update the methodDataOop rather than needing to do
3409 // dynamic tests on the receiver type
3410
3411 // NOTE: we should probably put a lock around this search to
3412 // avoid collisions by concurrent compilations
3413 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3414 uint i;
3415 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3416 ciKlass* receiver = vc_data->receiver(i);
3417 if (known_klass->equals(receiver)) {
3418 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3419 __ addptr(data_addr, DataLayout::counter_increment);
3420 return;
3421 }
3422 }
3423
3424 // Receiver type not found in profile data; select an empty slot
3425
3426 // Note that this is less efficient than it should be because it
3427 // always does a write to the receiver part of the
3428 // VirtualCallData rather than just the first time
3429 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3430 ciKlass* receiver = vc_data->receiver(i);
3431 if (receiver == NULL) {
3432 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3433 __ movoop(recv_addr, known_klass->constant_encoding());
3434 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3435 __ addptr(data_addr, DataLayout::counter_increment);
3436 return;
3437 }
3438 }
3439 } else {
3440 __ load_klass(recv, recv);
3441 Label update_done;
3442 type_profile_helper(mdo, md, data, recv, &update_done);
3443 // Receiver did not match any saved receiver and there is no empty row for it.
3444 // Increment total counter to indicate polymorphic case.
3445 __ addptr(counter_addr, DataLayout::counter_increment);
3446
3447 __ bind(update_done);
3448 }
3449 } else {
3450 // Static call
3451 __ addptr(counter_addr, DataLayout::counter_increment);
3452 }
3453 }
3454
3455 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3456 Unimplemented();
3457 }
3458
3459
3460 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3461 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3462 }
3463
3464
3465 void LIR_Assembler::align_backward_branch_target() {
3466 __ align(BytesPerWord);
3467 }
3468
3469
3470 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3471 if (left->is_single_cpu()) {
3472 __ negl(left->as_register());
3473 move_regs(left->as_register(), dest->as_register());
3474
3475 } else if (left->is_double_cpu()) {
3476 Register lo = left->as_register_lo();
3477 #ifdef _LP64
3478 Register dst = dest->as_register_lo();
3479 __ movptr(dst, lo);
3480 __ negptr(dst);
3481 #else
3482 Register hi = left->as_register_hi();
3483 __ lneg(hi, lo);
3484 if (dest->as_register_lo() == hi) {
3485 assert(dest->as_register_hi() != lo, "destroying register");
3486 move_regs(hi, dest->as_register_hi());
3487 move_regs(lo, dest->as_register_lo());
3488 } else {
3489 move_regs(lo, dest->as_register_lo());
3490 move_regs(hi, dest->as_register_hi());
3491 }
3492 #endif // _LP64
3493
3494 } else if (dest->is_single_xmm()) {
3495 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3496 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3497 }
3498 __ xorps(dest->as_xmm_float_reg(),
3499 ExternalAddress((address)float_signflip_pool));
3500
3501 } else if (dest->is_double_xmm()) {
3502 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3503 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3504 }
3505 __ xorpd(dest->as_xmm_double_reg(),
3506 ExternalAddress((address)double_signflip_pool));
3507
3508 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3509 assert(left->fpu() == 0, "arg must be on TOS");
3510 assert(dest->fpu() == 0, "dest must be TOS");
3511 __ fchs();
3512
3513 } else {
3514 ShouldNotReachHere();
3515 }
3516 }
3517
3518
3519 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3520 assert(addr->is_address() && dest->is_register(), "check");
3521 Register reg;
3522 reg = dest->as_pointer_register();
3523 __ lea(reg, as_Address(addr->as_address_ptr()));
3524 }
3525
3526
3527
3528 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3529 assert(!tmp->is_valid(), "don't need temporary");
3530 __ call(RuntimeAddress(dest));
3531 if (info != NULL) {
3532 add_call_info_here(info);
3533 }
3534 }
3535
3536
3537 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3538 assert(type == T_LONG, "only for volatile long fields");
3539
3540 if (info != NULL) {
3541 add_debug_info_for_null_check_here(info);
3542 }
3543
3544 if (src->is_double_xmm()) {
3545 if (dest->is_double_cpu()) {
3546 #ifdef _LP64
3547 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3548 #else
3549 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3550 __ psrlq(src->as_xmm_double_reg(), 32);
3551 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3552 #endif // _LP64
3553 } else if (dest->is_double_stack()) {
3554 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3555 } else if (dest->is_address()) {
3556 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3557 } else {
3558 ShouldNotReachHere();
3559 }
3560
3561 } else if (dest->is_double_xmm()) {
3562 if (src->is_double_stack()) {
3563 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3564 } else if (src->is_address()) {
3565 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3566 } else {
3567 ShouldNotReachHere();
3568 }
3569
3570 } else if (src->is_double_fpu()) {
3571 assert(src->fpu_regnrLo() == 0, "must be TOS");
3572 if (dest->is_double_stack()) {
3573 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3574 } else if (dest->is_address()) {
3575 __ fistp_d(as_Address(dest->as_address_ptr()));
3576 } else {
3577 ShouldNotReachHere();
3578 }
3579
3580 } else if (dest->is_double_fpu()) {
3581 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3582 if (src->is_double_stack()) {
3583 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3584 } else if (src->is_address()) {
3585 __ fild_d(as_Address(src->as_address_ptr()));
3586 } else {
3587 ShouldNotReachHere();
3588 }
3589 } else {
3590 ShouldNotReachHere();
3591 }
3592 }
3593
3594
3595 void LIR_Assembler::membar() {
3596 // QQQ sparc TSO uses this,
3597 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3598 }
3599
3600 void LIR_Assembler::membar_acquire() {
3601 // No x86 machines currently require load fences
3602 // __ load_fence();
3603 }
3604
3605 void LIR_Assembler::membar_release() {
3606 // No x86 machines currently require store fences
3607 // __ store_fence();
3608 }
3609
3610 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3611 assert(result_reg->is_register(), "check");
3612 #ifdef _LP64
3613 // __ get_thread(result_reg->as_register_lo());
3614 __ mov(result_reg->as_register(), r15_thread);
3615 #else
3616 __ get_thread(result_reg->as_register());
3617 #endif // _LP64
3618 }
3619
3620
3621 void LIR_Assembler::peephole(LIR_List*) {
3622 // do nothing for now
3623 }
3624
3625
3626 #undef __