1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "assembler_sparc.inline.hpp"
27 #include "gc_interface/collectedHeap.inline.hpp"
28 #include "interpreter/interpreter.hpp"
29 #include "memory/cardTableModRefBS.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/methodHandles.hpp"
32 #include "runtime/biasedLocking.hpp"
33 #include "runtime/interfaceSupport.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #ifndef SERIALGC
39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
41 #include "gc_implementation/g1/heapRegion.hpp"
42 #endif
43
44 // Convert the raw encoding form into the form expected by the
45 // constructor for Address.
46 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
47 assert(scale == 0, "not supported");
48 RelocationHolder rspec;
49 if (disp_is_oop) {
50 rspec = Relocation::spec_simple(relocInfo::oop_type);
51 }
52
53 Register rindex = as_Register(index);
54 if (rindex != G0) {
55 Address madr(as_Register(base), rindex);
56 madr._rspec = rspec;
57 return madr;
58 } else {
59 Address madr(as_Register(base), disp);
60 madr._rspec = rspec;
61 return madr;
62 }
63 }
64
65 Address Argument::address_in_frame() const {
66 // Warning: In LP64 mode disp will occupy more than 10 bits, but
67 // op codes such as ld or ldx, only access disp() to get
68 // their simm13 argument.
69 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
70 if (is_in())
71 return Address(FP, disp); // In argument.
72 else
73 return Address(SP, disp); // Out argument.
74 }
75
76 static const char* argumentNames[][2] = {
77 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
78 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
79 {"A(n>9)","P(n>9)"}
80 };
81
82 const char* Argument::name() const {
83 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
84 int num = number();
85 if (num >= nofArgs) num = nofArgs - 1;
86 return argumentNames[num][is_in() ? 1 : 0];
87 }
88
89 void Assembler::print_instruction(int inst) {
90 const char* s;
91 switch (inv_op(inst)) {
92 default: s = "????"; break;
93 case call_op: s = "call"; break;
94 case branch_op:
95 switch (inv_op2(inst)) {
96 case bpr_op2: s = "bpr"; break;
97 case fb_op2: s = "fb"; break;
98 case fbp_op2: s = "fbp"; break;
99 case br_op2: s = "br"; break;
100 case bp_op2: s = "bp"; break;
101 case cb_op2: s = "cb"; break;
102 default: s = "????"; break;
103 }
104 }
105 ::tty->print("%s", s);
106 }
107
108
109 // Patch instruction inst at offset inst_pos to refer to dest_pos
110 // and return the resulting instruction.
111 // We should have pcs, not offsets, but since all is relative, it will work out
112 // OK.
113 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {
114
115 int m; // mask for displacement field
116 int v; // new value for displacement field
117 const int word_aligned_ones = -4;
118 switch (inv_op(inst)) {
119 default: ShouldNotReachHere();
120 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
121 case branch_op:
122 switch (inv_op2(inst)) {
123 case bpr_op2: m = wdisp16(word_aligned_ones, 0); v = wdisp16(dest_pos, inst_pos); break;
124 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
125 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
126 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
127 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
128 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
129 default: ShouldNotReachHere();
130 }
131 }
132 return inst & ~m | v;
133 }
134
135 // Return the offset of the branch destionation of instruction inst
136 // at offset pos.
137 // Should have pcs, but since all is relative, it works out.
138 int Assembler::branch_destination(int inst, int pos) {
139 int r;
140 switch (inv_op(inst)) {
141 default: ShouldNotReachHere();
142 case call_op: r = inv_wdisp(inst, pos, 30); break;
143 case branch_op:
144 switch (inv_op2(inst)) {
145 case bpr_op2: r = inv_wdisp16(inst, pos); break;
146 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
147 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
148 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
149 case br_op2: r = inv_wdisp( inst, pos, 22); break;
150 case cb_op2: r = inv_wdisp( inst, pos, 22); break;
151 default: ShouldNotReachHere();
152 }
153 }
154 return r;
155 }
156
157 int AbstractAssembler::code_fill_byte() {
158 return 0x00; // illegal instruction 0x00000000
159 }
160
161 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {
162 switch (in) {
163 case rc_z: return equal;
164 case rc_lez: return lessEqual;
165 case rc_lz: return less;
166 case rc_nz: return notEqual;
167 case rc_gz: return greater;
168 case rc_gez: return greaterEqual;
169 default:
170 ShouldNotReachHere();
171 }
172 return equal;
173 }
174
175 // Generate a bunch 'o stuff (including v9's
176 #ifndef PRODUCT
177 void Assembler::test_v9() {
178 add( G0, G1, G2 );
179 add( G3, 0, G4 );
180
181 addcc( G5, G6, G7 );
182 addcc( I0, 1, I1 );
183 addc( I2, I3, I4 );
184 addc( I5, -1, I6 );
185 addccc( I7, L0, L1 );
186 addccc( L2, (1 << 12) - 2, L3 );
187
188 Label lbl1, lbl2, lbl3;
189
190 bind(lbl1);
191
192 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type );
193 delayed()->nop();
194 bpr( rc_lez, false, pt, L5, lbl1);
195 delayed()->nop();
196
197 fb( f_never, true, pc() + 4, relocInfo::none);
198 delayed()->nop();
199 fb( f_notEqual, false, lbl2 );
200 delayed()->nop();
201
202 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none);
203 delayed()->nop();
204 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 );
205 delayed()->nop();
206
207 br( equal, true, pc() + 1024, relocInfo::none);
208 delayed()->nop();
209 br( lessEqual, false, lbl1 );
210 delayed()->nop();
211 br( never, false, lbl1 );
212 delayed()->nop();
213
214 bp( less, true, icc, pn, pc(), relocInfo::none);
215 delayed()->nop();
216 bp( lessEqualUnsigned, false, xcc, pt, lbl2 );
217 delayed()->nop();
218
219 call( pc(), relocInfo::none);
220 delayed()->nop();
221 call( lbl3 );
222 delayed()->nop();
223
224
225 casa( L6, L7, O0 );
226 casxa( O1, O2, O3, 0 );
227
228 udiv( O4, O5, O7 );
229 udiv( G0, (1 << 12) - 1, G1 );
230 sdiv( G1, G2, G3 );
231 sdiv( G4, -((1 << 12) - 1), G5 );
232 udivcc( G6, G7, I0 );
233 udivcc( I1, -((1 << 12) - 2), I2 );
234 sdivcc( I3, I4, I5 );
235 sdivcc( I6, -((1 << 12) - 0), I7 );
236
237 done();
238 retry();
239
240 fadd( FloatRegisterImpl::S, F0, F1, F2 );
241 fsub( FloatRegisterImpl::D, F34, F0, F62 );
242
243 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60);
244 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30);
245
246 ftox( FloatRegisterImpl::D, F2, F4 );
247 ftoi( FloatRegisterImpl::Q, F4, F8 );
248
249 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 );
250
251 fxtof( FloatRegisterImpl::S, F4, F5 );
252 fitof( FloatRegisterImpl::D, F6, F8 );
253
254 fmov( FloatRegisterImpl::Q, F16, F20 );
255 fneg( FloatRegisterImpl::S, F6, F7 );
256 fabs( FloatRegisterImpl::D, F10, F12 );
257
258 fmul( FloatRegisterImpl::Q, F24, F28, F32 );
259 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 );
260 fdiv( FloatRegisterImpl::S, F10, F11, F12 );
261
262 fsqrt( FloatRegisterImpl::S, F13, F14 );
263
264 flush( L0, L1 );
265 flush( L2, -1 );
266
267 flushw();
268
269 illtrap( (1 << 22) - 2);
270
271 impdep1( 17, (1 << 19) - 1 );
272 impdep2( 3, 0 );
273
274 jmpl( L3, L4, L5 );
275 delayed()->nop();
276 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none));
277 delayed()->nop();
278
279
280 ldf( FloatRegisterImpl::S, O0, O1, F15 );
281 ldf( FloatRegisterImpl::D, O2, -1, F14 );
282
283
284 ldfsr( O3, O4 );
285 ldfsr( O5, -1 );
286 ldxfsr( O6, O7 );
287 ldxfsr( I0, -1 );
288
289 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 );
290 ldfa( FloatRegisterImpl::Q, I3, -1, F36 );
291
292 ldsb( I4, I5, I6 );
293 ldsb( I7, -1, G0 );
294 ldsh( G1, G3, G4 );
295 ldsh( G5, -1, G6 );
296 ldsw( G7, L0, L1 );
297 ldsw( L2, -1, L3 );
298 ldub( L4, L5, L6 );
299 ldub( L7, -1, O0 );
300 lduh( O1, O2, O3 );
301 lduh( O4, -1, O5 );
302 lduw( O6, O7, G0 );
303 lduw( G1, -1, G2 );
304 ldx( G3, G4, G5 );
305 ldx( G6, -1, G7 );
306 ldd( I0, I1, I2 );
307 ldd( I3, -1, I4 );
308
309 ldsba( I5, I6, 2, I7 );
310 ldsba( L0, -1, L1 );
311 ldsha( L2, L3, 3, L4 );
312 ldsha( L5, -1, L6 );
313 ldswa( L7, O0, (1 << 8) - 1, O1 );
314 ldswa( O2, -1, O3 );
315 lduba( O4, O5, 0, O6 );
316 lduba( O7, -1, I0 );
317 lduha( I1, I2, 1, I3 );
318 lduha( I4, -1, I5 );
319 lduwa( I6, I7, 2, L0 );
320 lduwa( L1, -1, L2 );
321 ldxa( L3, L4, 3, L5 );
322 ldxa( L6, -1, L7 );
323 ldda( G0, G1, 4, G2 );
324 ldda( G3, -1, G4 );
325
326 ldstub( G5, G6, G7 );
327 ldstub( O0, -1, O1 );
328
329 ldstuba( O2, O3, 5, O4 );
330 ldstuba( O5, -1, O6 );
331
332 and3( I0, L0, O0 );
333 and3( G7, -1, O7 );
334 andcc( L2, I2, G2 );
335 andcc( L4, -1, G4 );
336 andn( I5, I6, I7 );
337 andn( I6, -1, I7 );
338 andncc( I5, I6, I7 );
339 andncc( I7, -1, I6 );
340 or3( I5, I6, I7 );
341 or3( I7, -1, I6 );
342 orcc( I5, I6, I7 );
343 orcc( I7, -1, I6 );
344 orn( I5, I6, I7 );
345 orn( I7, -1, I6 );
346 orncc( I5, I6, I7 );
347 orncc( I7, -1, I6 );
348 xor3( I5, I6, I7 );
349 xor3( I7, -1, I6 );
350 xorcc( I5, I6, I7 );
351 xorcc( I7, -1, I6 );
352 xnor( I5, I6, I7 );
353 xnor( I7, -1, I6 );
354 xnorcc( I5, I6, I7 );
355 xnorcc( I7, -1, I6 );
356
357 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) );
358 membar( StoreStore );
359 membar( LoadStore );
360 membar( StoreLoad );
361 membar( LoadLoad );
362 membar( Sync );
363 membar( MemIssue );
364 membar( Lookaside );
365
366 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 );
367 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 );
368
369 movcc( overflowClear, false, icc, I6, L4 );
370 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 );
371
372 movr( rc_nz, I5, I6, I7 );
373 movr( rc_gz, L1, -1, L2 );
374
375 mulx( I5, I6, I7 );
376 mulx( I7, -1, I6 );
377 sdivx( I5, I6, I7 );
378 sdivx( I7, -1, I6 );
379 udivx( I5, I6, I7 );
380 udivx( I7, -1, I6 );
381
382 umul( I5, I6, I7 );
383 umul( I7, -1, I6 );
384 smul( I5, I6, I7 );
385 smul( I7, -1, I6 );
386 umulcc( I5, I6, I7 );
387 umulcc( I7, -1, I6 );
388 smulcc( I5, I6, I7 );
389 smulcc( I7, -1, I6 );
390
391 mulscc( I5, I6, I7 );
392 mulscc( I7, -1, I6 );
393
394 nop();
395
396
397 popc( G0, G1);
398 popc( -1, G2);
399
400 prefetch( L1, L2, severalReads );
401 prefetch( L3, -1, oneRead );
402 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads );
403 prefetcha( G2, -1, oneWrite );
404
405 rett( I7, I7);
406 delayed()->nop();
407 rett( G0, -1, relocInfo::none);
408 delayed()->nop();
409
410 save( I5, I6, I7 );
411 save( I7, -1, I6 );
412 restore( I5, I6, I7 );
413 restore( I7, -1, I6 );
414
415 saved();
416 restored();
417
418 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none));
419
420 sll( I5, I6, I7 );
421 sll( I7, 31, I6 );
422 srl( I5, I6, I7 );
423 srl( I7, 0, I6 );
424 sra( I5, I6, I7 );
425 sra( I7, 30, I6 );
426 sllx( I5, I6, I7 );
427 sllx( I7, 63, I6 );
428 srlx( I5, I6, I7 );
429 srlx( I7, 0, I6 );
430 srax( I5, I6, I7 );
431 srax( I7, 62, I6 );
432
433 sir( -1 );
434
435 stbar();
436
437 stf( FloatRegisterImpl::Q, F40, G0, I7 );
438 stf( FloatRegisterImpl::S, F18, I3, -1 );
439
440 stfsr( L1, L2 );
441 stfsr( I7, -1 );
442 stxfsr( I6, I5 );
443 stxfsr( L4, -1 );
444
445 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 );
446 stfa( FloatRegisterImpl::Q, F44, G0, -1 );
447
448 stb( L5, O2, I7 );
449 stb( I7, I6, -1 );
450 sth( L5, O2, I7 );
451 sth( I7, I6, -1 );
452 stw( L5, O2, I7 );
453 stw( I7, I6, -1 );
454 stx( L5, O2, I7 );
455 stx( I7, I6, -1 );
456 std( L5, O2, I7 );
457 std( I7, I6, -1 );
458
459 stba( L5, O2, I7, 8 );
460 stba( I7, I6, -1 );
461 stha( L5, O2, I7, 9 );
462 stha( I7, I6, -1 );
463 stwa( L5, O2, I7, 0 );
464 stwa( I7, I6, -1 );
465 stxa( L5, O2, I7, 11 );
466 stxa( I7, I6, -1 );
467 stda( L5, O2, I7, 12 );
468 stda( I7, I6, -1 );
469
470 sub( I5, I6, I7 );
471 sub( I7, -1, I6 );
472 subcc( I5, I6, I7 );
473 subcc( I7, -1, I6 );
474 subc( I5, I6, I7 );
475 subc( I7, -1, I6 );
476 subccc( I5, I6, I7 );
477 subccc( I7, -1, I6 );
478
479 swap( I5, I6, I7 );
480 swap( I7, -1, I6 );
481
482 swapa( G0, G1, 13, G2 );
483 swapa( I7, -1, I6 );
484
485 taddcc( I5, I6, I7 );
486 taddcc( I7, -1, I6 );
487 taddcctv( I5, I6, I7 );
488 taddcctv( I7, -1, I6 );
489
490 tsubcc( I5, I6, I7 );
491 tsubcc( I7, -1, I6 );
492 tsubcctv( I5, I6, I7 );
493 tsubcctv( I7, -1, I6 );
494
495 trap( overflowClear, xcc, G0, G1 );
496 trap( lessEqual, icc, I7, 17 );
497
498 bind(lbl2);
499 bind(lbl3);
500
501 code()->decode();
502 }
503
504 // Generate a bunch 'o stuff unique to V8
505 void Assembler::test_v8_onlys() {
506 Label lbl1;
507
508 cb( cp_0or1or2, false, pc() - 4, relocInfo::none);
509 delayed()->nop();
510 cb( cp_never, true, lbl1);
511 delayed()->nop();
512
513 cpop1(1, 2, 3, 4);
514 cpop2(5, 6, 7, 8);
515
516 ldc( I0, I1, 31);
517 ldc( I2, -1, 0);
518
519 lddc( I4, I4, 30);
520 lddc( I6, 0, 1 );
521
522 ldcsr( L0, L1, 0);
523 ldcsr( L1, (1 << 12) - 1, 17 );
524
525 stc( 31, L4, L5);
526 stc( 30, L6, -(1 << 12) );
527
528 stdc( 0, L7, G0);
529 stdc( 1, G1, 0 );
530
531 stcsr( 16, G2, G3);
532 stcsr( 17, G4, 1 );
533
534 stdcq( 4, G5, G6);
535 stdcq( 5, G7, -1 );
536
537 bind(lbl1);
538
539 code()->decode();
540 }
541 #endif
542
543 // Implementation of MacroAssembler
544
545 void MacroAssembler::null_check(Register reg, int offset) {
546 if (needs_explicit_null_check((intptr_t)offset)) {
547 // provoke OS NULL exception if reg = NULL by
548 // accessing M[reg] w/o changing any registers
549 ld_ptr(reg, 0, G0);
550 }
551 else {
552 // nothing to do, (later) access of M[reg + offset]
553 // will provoke OS NULL exception if reg = NULL
554 }
555 }
556
557 // Ring buffer jumps
558
559 #ifndef PRODUCT
560 void MacroAssembler::ret( bool trace ) { if (trace) {
561 mov(I7, O7); // traceable register
562 JMP(O7, 2 * BytesPerInstWord);
563 } else {
564 jmpl( I7, 2 * BytesPerInstWord, G0 );
565 }
566 }
567
568 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
569 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
570 #endif /* PRODUCT */
571
572
573 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
574 assert_not_delayed();
575 // This can only be traceable if r1 & r2 are visible after a window save
576 if (TraceJumps) {
577 #ifndef PRODUCT
578 save_frame(0);
579 verify_thread();
580 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
581 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
582 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
583 add(O2, O1, O1);
584
585 add(r1->after_save(), r2->after_save(), O2);
586 set((intptr_t)file, O3);
587 set(line, O4);
588 Label L;
589 // get nearby pc, store jmp target
590 call(L, relocInfo::none); // No relocation for call to pc+0x8
591 delayed()->st(O2, O1, 0);
592 bind(L);
593
594 // store nearby pc
595 st(O7, O1, sizeof(intptr_t));
596 // store file
597 st(O3, O1, 2*sizeof(intptr_t));
598 // store line
599 st(O4, O1, 3*sizeof(intptr_t));
600 add(O0, 1, O0);
601 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
602 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
603 restore();
604 #endif /* PRODUCT */
605 }
606 jmpl(r1, r2, G0);
607 }
608 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
609 assert_not_delayed();
610 // This can only be traceable if r1 is visible after a window save
611 if (TraceJumps) {
612 #ifndef PRODUCT
613 save_frame(0);
614 verify_thread();
615 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
616 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
617 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
618 add(O2, O1, O1);
619
620 add(r1->after_save(), offset, O2);
621 set((intptr_t)file, O3);
622 set(line, O4);
623 Label L;
624 // get nearby pc, store jmp target
625 call(L, relocInfo::none); // No relocation for call to pc+0x8
626 delayed()->st(O2, O1, 0);
627 bind(L);
628
629 // store nearby pc
630 st(O7, O1, sizeof(intptr_t));
631 // store file
632 st(O3, O1, 2*sizeof(intptr_t));
633 // store line
634 st(O4, O1, 3*sizeof(intptr_t));
635 add(O0, 1, O0);
636 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
637 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
638 restore();
639 #endif /* PRODUCT */
640 }
641 jmp(r1, offset);
642 }
643
644 // This code sequence is relocatable to any address, even on LP64.
645 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
646 assert_not_delayed();
647 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
648 // variable length instruction streams.
649 patchable_sethi(addrlit, temp);
650 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
651 if (TraceJumps) {
652 #ifndef PRODUCT
653 // Must do the add here so relocation can find the remainder of the
654 // value to be relocated.
655 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
656 save_frame(0);
657 verify_thread();
658 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
659 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
660 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
661 add(O2, O1, O1);
662
663 set((intptr_t)file, O3);
664 set(line, O4);
665 Label L;
666
667 // get nearby pc, store jmp target
668 call(L, relocInfo::none); // No relocation for call to pc+0x8
669 delayed()->st(a.base()->after_save(), O1, 0);
670 bind(L);
671
672 // store nearby pc
673 st(O7, O1, sizeof(intptr_t));
674 // store file
675 st(O3, O1, 2*sizeof(intptr_t));
676 // store line
677 st(O4, O1, 3*sizeof(intptr_t));
678 add(O0, 1, O0);
679 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
680 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
681 restore();
682 jmpl(a.base(), G0, d);
683 #else
684 jmpl(a.base(), a.disp(), d);
685 #endif /* PRODUCT */
686 } else {
687 jmpl(a.base(), a.disp(), d);
688 }
689 }
690
691 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
692 jumpl(addrlit, temp, G0, offset, file, line);
693 }
694
695
696 // Convert to C varargs format
697 void MacroAssembler::set_varargs( Argument inArg, Register d ) {
698 // spill register-resident args to their memory slots
699 // (SPARC calling convention requires callers to have already preallocated these)
700 // Note that the inArg might in fact be an outgoing argument,
701 // if a leaf routine or stub does some tricky argument shuffling.
702 // This routine must work even though one of the saved arguments
703 // is in the d register (e.g., set_varargs(Argument(0, false), O0)).
704 for (Argument savePtr = inArg;
705 savePtr.is_register();
706 savePtr = savePtr.successor()) {
707 st_ptr(savePtr.as_register(), savePtr.address_in_frame());
708 }
709 // return the address of the first memory slot
710 Address a = inArg.address_in_frame();
711 add(a.base(), a.disp(), d);
712 }
713
714 // Conditional breakpoint (for assertion checks in assembly code)
715 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
716 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
717 }
718
719 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
720 void MacroAssembler::breakpoint_trap() {
721 trap(ST_RESERVED_FOR_USER_0);
722 }
723
724 // flush windows (except current) using flushw instruction if avail.
725 void MacroAssembler::flush_windows() {
726 if (VM_Version::v9_instructions_work()) flushw();
727 else flush_windows_trap();
728 }
729
730 // Write serialization page so VM thread can do a pseudo remote membar
731 // We use the current thread pointer to calculate a thread specific
732 // offset to write to within the page. This minimizes bus traffic
733 // due to cache line collision.
734 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
735 srl(thread, os::get_serialize_page_shift_count(), tmp2);
736 if (Assembler::is_simm13(os::vm_page_size())) {
737 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
738 }
739 else {
740 set((os::vm_page_size() - sizeof(int)), tmp1);
741 and3(tmp2, tmp1, tmp2);
742 }
743 set(os::get_memory_serialize_page(), tmp1);
744 st(G0, tmp1, tmp2);
745 }
746
747
748
749 void MacroAssembler::enter() {
750 Unimplemented();
751 }
752
753 void MacroAssembler::leave() {
754 Unimplemented();
755 }
756
757 void MacroAssembler::mult(Register s1, Register s2, Register d) {
758 if(VM_Version::v9_instructions_work()) {
759 mulx (s1, s2, d);
760 } else {
761 smul (s1, s2, d);
762 }
763 }
764
765 void MacroAssembler::mult(Register s1, int simm13a, Register d) {
766 if(VM_Version::v9_instructions_work()) {
767 mulx (s1, simm13a, d);
768 } else {
769 smul (s1, simm13a, d);
770 }
771 }
772
773
774 #ifdef ASSERT
775 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {
776 const Register s1 = G3_scratch;
777 const Register s2 = G4_scratch;
778 Label get_psr_test;
779 // Get the condition codes the V8 way.
780 read_ccr_trap(s1);
781 mov(ccr_save, s2);
782 // This is a test of V8 which has icc but not xcc
783 // so mask off the xcc bits
784 and3(s2, 0xf, s2);
785 // Compare condition codes from the V8 and V9 ways.
786 subcc(s2, s1, G0);
787 br(Assembler::notEqual, true, Assembler::pt, get_psr_test);
788 delayed()->breakpoint_trap();
789 bind(get_psr_test);
790 }
791
792 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {
793 const Register s1 = G3_scratch;
794 const Register s2 = G4_scratch;
795 Label set_psr_test;
796 // Write out the saved condition codes the V8 way
797 write_ccr_trap(ccr_save, s1, s2);
798 // Read back the condition codes using the V9 instruction
799 rdccr(s1);
800 mov(ccr_save, s2);
801 // This is a test of V8 which has icc but not xcc
802 // so mask off the xcc bits
803 and3(s2, 0xf, s2);
804 and3(s1, 0xf, s1);
805 // Compare the V8 way with the V9 way.
806 subcc(s2, s1, G0);
807 br(Assembler::notEqual, true, Assembler::pt, set_psr_test);
808 delayed()->breakpoint_trap();
809 bind(set_psr_test);
810 }
811 #else
812 #define read_ccr_v8_assert(x)
813 #define write_ccr_v8_assert(x)
814 #endif // ASSERT
815
816 void MacroAssembler::read_ccr(Register ccr_save) {
817 if (VM_Version::v9_instructions_work()) {
818 rdccr(ccr_save);
819 // Test code sequence used on V8. Do not move above rdccr.
820 read_ccr_v8_assert(ccr_save);
821 } else {
822 read_ccr_trap(ccr_save);
823 }
824 }
825
826 void MacroAssembler::write_ccr(Register ccr_save) {
827 if (VM_Version::v9_instructions_work()) {
828 // Test code sequence used on V8. Do not move below wrccr.
829 write_ccr_v8_assert(ccr_save);
830 wrccr(ccr_save);
831 } else {
832 const Register temp_reg1 = G3_scratch;
833 const Register temp_reg2 = G4_scratch;
834 write_ccr_trap(ccr_save, temp_reg1, temp_reg2);
835 }
836 }
837
838
839 // Calls to C land
840
841 #ifdef ASSERT
842 // a hook for debugging
843 static Thread* reinitialize_thread() {
844 return ThreadLocalStorage::thread();
845 }
846 #else
847 #define reinitialize_thread ThreadLocalStorage::thread
848 #endif
849
850 #ifdef ASSERT
851 address last_get_thread = NULL;
852 #endif
853
854 // call this when G2_thread is not known to be valid
855 void MacroAssembler::get_thread() {
856 save_frame(0); // to avoid clobbering O0
857 mov(G1, L0); // avoid clobbering G1
858 mov(G5_method, L1); // avoid clobbering G5
859 mov(G3, L2); // avoid clobbering G3 also
860 mov(G4, L5); // avoid clobbering G4
861 #ifdef ASSERT
862 AddressLiteral last_get_thread_addrlit(&last_get_thread);
863 set(last_get_thread_addrlit, L3);
864 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call
865 st_ptr(L4, L3, 0);
866 #endif
867 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
868 delayed()->nop();
869 mov(L0, G1);
870 mov(L1, G5_method);
871 mov(L2, G3);
872 mov(L5, G4);
873 restore(O0, 0, G2_thread);
874 }
875
876 static Thread* verify_thread_subroutine(Thread* gthread_value) {
877 Thread* correct_value = ThreadLocalStorage::thread();
878 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
879 return correct_value;
880 }
881
882 void MacroAssembler::verify_thread() {
883 if (VerifyThread) {
884 // NOTE: this chops off the heads of the 64-bit O registers.
885 #ifdef CC_INTERP
886 save_frame(0);
887 #else
888 // make sure G2_thread contains the right value
889 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
890 mov(G1, L1); // avoid clobbering G1
891 // G2 saved below
892 mov(G3, L3); // avoid clobbering G3
893 mov(G4, L4); // avoid clobbering G4
894 mov(G5_method, L5); // avoid clobbering G5_method
895 #endif /* CC_INTERP */
896 #if defined(COMPILER2) && !defined(_LP64)
897 // Save & restore possible 64-bit Long arguments in G-regs
898 srlx(G1,32,L0);
899 srlx(G4,32,L6);
900 #endif
901 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
902 delayed()->mov(G2_thread, O0);
903
904 mov(L1, G1); // Restore G1
905 // G2 restored below
906 mov(L3, G3); // restore G3
907 mov(L4, G4); // restore G4
908 mov(L5, G5_method); // restore G5_method
909 #if defined(COMPILER2) && !defined(_LP64)
910 // Save & restore possible 64-bit Long arguments in G-regs
911 sllx(L0,32,G2); // Move old high G1 bits high in G2
912 sllx(G1, 0,G1); // Clear current high G1 bits
913 or3 (G1,G2,G1); // Recover 64-bit G1
914 sllx(L6,32,G2); // Move old high G4 bits high in G2
915 sllx(G4, 0,G4); // Clear current high G4 bits
916 or3 (G4,G2,G4); // Recover 64-bit G4
917 #endif
918 restore(O0, 0, G2_thread);
919 }
920 }
921
922
923 void MacroAssembler::save_thread(const Register thread_cache) {
924 verify_thread();
925 if (thread_cache->is_valid()) {
926 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
927 mov(G2_thread, thread_cache);
928 }
929 if (VerifyThread) {
930 // smash G2_thread, as if the VM were about to anyway
931 set(0x67676767, G2_thread);
932 }
933 }
934
935
936 void MacroAssembler::restore_thread(const Register thread_cache) {
937 if (thread_cache->is_valid()) {
938 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
939 mov(thread_cache, G2_thread);
940 verify_thread();
941 } else {
942 // do it the slow way
943 get_thread();
944 }
945 }
946
947
948 // %%% maybe get rid of [re]set_last_Java_frame
949 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
950 assert_not_delayed();
951 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
952 JavaFrameAnchor::flags_offset());
953 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
954
955 // Always set last_Java_pc and flags first because once last_Java_sp is visible
956 // has_last_Java_frame is true and users will look at the rest of the fields.
957 // (Note: flags should always be zero before we get here so doesn't need to be set.)
958
959 #ifdef ASSERT
960 // Verify that flags was zeroed on return to Java
961 Label PcOk;
962 save_frame(0); // to avoid clobbering O0
963 ld_ptr(pc_addr, L0);
964 tst(L0);
965 #ifdef _LP64
966 brx(Assembler::zero, false, Assembler::pt, PcOk);
967 #else
968 br(Assembler::zero, false, Assembler::pt, PcOk);
969 #endif // _LP64
970 delayed() -> nop();
971 stop("last_Java_pc not zeroed before leaving Java");
972 bind(PcOk);
973
974 // Verify that flags was zeroed on return to Java
975 Label FlagsOk;
976 ld(flags, L0);
977 tst(L0);
978 br(Assembler::zero, false, Assembler::pt, FlagsOk);
979 delayed() -> restore();
980 stop("flags not zeroed before leaving Java");
981 bind(FlagsOk);
982 #endif /* ASSERT */
983 //
984 // When returning from calling out from Java mode the frame anchor's last_Java_pc
985 // will always be set to NULL. It is set here so that if we are doing a call to
986 // native (not VM) that we capture the known pc and don't have to rely on the
987 // native call having a standard frame linkage where we can find the pc.
988
989 if (last_Java_pc->is_valid()) {
990 st_ptr(last_Java_pc, pc_addr);
991 }
992
993 #ifdef _LP64
994 #ifdef ASSERT
995 // Make sure that we have an odd stack
996 Label StackOk;
997 andcc(last_java_sp, 0x01, G0);
998 br(Assembler::notZero, false, Assembler::pt, StackOk);
999 delayed() -> nop();
1000 stop("Stack Not Biased in set_last_Java_frame");
1001 bind(StackOk);
1002 #endif // ASSERT
1003 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
1004 add( last_java_sp, STACK_BIAS, G4_scratch );
1005 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
1006 #else
1007 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
1008 #endif // _LP64
1009 }
1010
1011 void MacroAssembler::reset_last_Java_frame(void) {
1012 assert_not_delayed();
1013
1014 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
1015 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1016 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
1017
1018 #ifdef ASSERT
1019 // check that it WAS previously set
1020 #ifdef CC_INTERP
1021 save_frame(0);
1022 #else
1023 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
1024 #endif /* CC_INTERP */
1025 ld_ptr(sp_addr, L0);
1026 tst(L0);
1027 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
1028 restore();
1029 #endif // ASSERT
1030
1031 st_ptr(G0, sp_addr);
1032 // Always return last_Java_pc to zero
1033 st_ptr(G0, pc_addr);
1034 // Always null flags after return to Java
1035 st(G0, flags);
1036 }
1037
1038
1039 void MacroAssembler::call_VM_base(
1040 Register oop_result,
1041 Register thread_cache,
1042 Register last_java_sp,
1043 address entry_point,
1044 int number_of_arguments,
1045 bool check_exceptions)
1046 {
1047 assert_not_delayed();
1048
1049 // determine last_java_sp register
1050 if (!last_java_sp->is_valid()) {
1051 last_java_sp = SP;
1052 }
1053 // debugging support
1054 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1055
1056 // 64-bit last_java_sp is biased!
1057 set_last_Java_frame(last_java_sp, noreg);
1058 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
1059 save_thread(thread_cache);
1060 // do the call
1061 call(entry_point, relocInfo::runtime_call_type);
1062 if (!VerifyThread)
1063 delayed()->mov(G2_thread, O0); // pass thread as first argument
1064 else
1065 delayed()->nop(); // (thread already passed)
1066 restore_thread(thread_cache);
1067 reset_last_Java_frame();
1068
1069 // check for pending exceptions. use Gtemp as scratch register.
1070 if (check_exceptions) {
1071 check_and_forward_exception(Gtemp);
1072 }
1073
1074 // get oop result if there is one and reset the value in the thread
1075 if (oop_result->is_valid()) {
1076 get_vm_result(oop_result);
1077 }
1078 }
1079
1080 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
1081 {
1082 Label L;
1083
1084 check_and_handle_popframe(scratch_reg);
1085 check_and_handle_earlyret(scratch_reg);
1086
1087 Address exception_addr(G2_thread, Thread::pending_exception_offset());
1088 ld_ptr(exception_addr, scratch_reg);
1089 br_null(scratch_reg,false,pt,L);
1090 delayed()->nop();
1091 // we use O7 linkage so that forward_exception_entry has the issuing PC
1092 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1093 delayed()->nop();
1094 bind(L);
1095 }
1096
1097
1098 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
1099 }
1100
1101
1102 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
1103 }
1104
1105
1106 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1107 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
1108 }
1109
1110
1111 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
1112 // O0 is reserved for the thread
1113 mov(arg_1, O1);
1114 call_VM(oop_result, entry_point, 1, check_exceptions);
1115 }
1116
1117
1118 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
1119 // O0 is reserved for the thread
1120 mov(arg_1, O1);
1121 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1122 call_VM(oop_result, entry_point, 2, check_exceptions);
1123 }
1124
1125
1126 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
1127 // O0 is reserved for the thread
1128 mov(arg_1, O1);
1129 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1130 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
1131 call_VM(oop_result, entry_point, 3, check_exceptions);
1132 }
1133
1134
1135
1136 // Note: The following call_VM overloadings are useful when a "save"
1137 // has already been performed by a stub, and the last Java frame is
1138 // the previous one. In that case, last_java_sp must be passed as FP
1139 // instead of SP.
1140
1141
1142 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
1143 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1144 }
1145
1146
1147 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
1148 // O0 is reserved for the thread
1149 mov(arg_1, O1);
1150 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1151 }
1152
1153
1154 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
1155 // O0 is reserved for the thread
1156 mov(arg_1, O1);
1157 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1158 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1159 }
1160
1161
1162 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
1163 // O0 is reserved for the thread
1164 mov(arg_1, O1);
1165 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1166 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
1167 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1168 }
1169
1170
1171
1172 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
1173 assert_not_delayed();
1174 save_thread(thread_cache);
1175 // do the call
1176 call(entry_point, relocInfo::runtime_call_type);
1177 delayed()->nop();
1178 restore_thread(thread_cache);
1179 }
1180
1181
1182 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
1183 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
1184 }
1185
1186
1187 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
1188 mov(arg_1, O0);
1189 call_VM_leaf(thread_cache, entry_point, 1);
1190 }
1191
1192
1193 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
1194 mov(arg_1, O0);
1195 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
1196 call_VM_leaf(thread_cache, entry_point, 2);
1197 }
1198
1199
1200 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
1201 mov(arg_1, O0);
1202 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
1203 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
1204 call_VM_leaf(thread_cache, entry_point, 3);
1205 }
1206
1207
1208 void MacroAssembler::get_vm_result(Register oop_result) {
1209 verify_thread();
1210 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
1211 ld_ptr( vm_result_addr, oop_result);
1212 st_ptr(G0, vm_result_addr);
1213 verify_oop(oop_result);
1214 }
1215
1216
1217 void MacroAssembler::get_vm_result_2(Register oop_result) {
1218 verify_thread();
1219 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
1220 ld_ptr(vm_result_addr_2, oop_result);
1221 st_ptr(G0, vm_result_addr_2);
1222 verify_oop(oop_result);
1223 }
1224
1225
1226 // We require that C code which does not return a value in vm_result will
1227 // leave it undisturbed.
1228 void MacroAssembler::set_vm_result(Register oop_result) {
1229 verify_thread();
1230 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
1231 verify_oop(oop_result);
1232
1233 # ifdef ASSERT
1234 // Check that we are not overwriting any other oop.
1235 #ifdef CC_INTERP
1236 save_frame(0);
1237 #else
1238 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
1239 #endif /* CC_INTERP */
1240 ld_ptr(vm_result_addr, L0);
1241 tst(L0);
1242 restore();
1243 breakpoint_trap(notZero, Assembler::ptr_cc);
1244 // }
1245 # endif
1246
1247 st_ptr(oop_result, vm_result_addr);
1248 }
1249
1250
1251 void MacroAssembler::card_table_write(jbyte* byte_map_base,
1252 Register tmp, Register obj) {
1253 #ifdef _LP64
1254 srlx(obj, CardTableModRefBS::card_shift, obj);
1255 #else
1256 srl(obj, CardTableModRefBS::card_shift, obj);
1257 #endif
1258 assert(tmp != obj, "need separate temp reg");
1259 set((address) byte_map_base, tmp);
1260 stb(G0, tmp, obj);
1261 }
1262
1263
1264 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
1265 address save_pc;
1266 int shiftcnt;
1267 #ifdef _LP64
1268 # ifdef CHECK_DELAY
1269 assert_not_delayed((char*) "cannot put two instructions in delay slot");
1270 # endif
1271 v9_dep();
1272 save_pc = pc();
1273
1274 int msb32 = (int) (addrlit.value() >> 32);
1275 int lsb32 = (int) (addrlit.value());
1276
1277 if (msb32 == 0 && lsb32 >= 0) {
1278 Assembler::sethi(lsb32, d, addrlit.rspec());
1279 }
1280 else if (msb32 == -1) {
1281 Assembler::sethi(~lsb32, d, addrlit.rspec());
1282 xor3(d, ~low10(~0), d);
1283 }
1284 else {
1285 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
1286 if (msb32 & 0x3ff) // Any bits?
1287 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
1288 if (lsb32 & 0xFFFFFC00) { // done?
1289 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
1290 sllx(d, 12, d); // Make room for next 12 bits
1291 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
1292 shiftcnt = 0; // We already shifted
1293 }
1294 else
1295 shiftcnt = 12;
1296 if ((lsb32 >> 10) & 0x3ff) {
1297 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
1298 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
1299 shiftcnt = 0;
1300 }
1301 else
1302 shiftcnt = 10;
1303 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
1304 }
1305 else
1306 sllx(d, 32, d);
1307 }
1308 // Pad out the instruction sequence so it can be patched later.
1309 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
1310 addrlit.rtype() != relocInfo::runtime_call_type)) {
1311 while (pc() < (save_pc + (7 * BytesPerInstWord)))
1312 nop();
1313 }
1314 #else
1315 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
1316 #endif
1317 }
1318
1319
1320 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
1321 internal_sethi(addrlit, d, false);
1322 }
1323
1324
1325 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
1326 internal_sethi(addrlit, d, true);
1327 }
1328
1329
1330 int MacroAssembler::size_of_sethi(address a, bool worst_case) {
1331 #ifdef _LP64
1332 if (worst_case) return 7;
1333 intptr_t iaddr = (intptr_t)a;
1334 int hi32 = (int)(iaddr >> 32);
1335 int lo32 = (int)(iaddr);
1336 int inst_count;
1337 if (hi32 == 0 && lo32 >= 0)
1338 inst_count = 1;
1339 else if (hi32 == -1)
1340 inst_count = 2;
1341 else {
1342 inst_count = 2;
1343 if ( hi32 & 0x3ff )
1344 inst_count++;
1345 if ( lo32 & 0xFFFFFC00 ) {
1346 if( (lo32 >> 20) & 0xfff ) inst_count += 2;
1347 if( (lo32 >> 10) & 0x3ff ) inst_count += 2;
1348 }
1349 }
1350 return BytesPerInstWord * inst_count;
1351 #else
1352 return BytesPerInstWord;
1353 #endif
1354 }
1355
1356 int MacroAssembler::worst_case_size_of_set() {
1357 return size_of_sethi(NULL, true) + 1;
1358 }
1359
1360
1361 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
1362 intptr_t value = addrlit.value();
1363
1364 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
1365 // can optimize
1366 if (-4096 <= value && value <= 4095) {
1367 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
1368 return;
1369 }
1370 if (inv_hi22(hi22(value)) == value) {
1371 sethi(addrlit, d);
1372 return;
1373 }
1374 }
1375 assert_not_delayed((char*) "cannot put two instructions in delay slot");
1376 internal_sethi(addrlit, d, ForceRelocatable);
1377 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
1378 add(d, addrlit.low10(), d, addrlit.rspec());
1379 }
1380 }
1381
1382 void MacroAssembler::set(const AddressLiteral& al, Register d) {
1383 internal_set(al, d, false);
1384 }
1385
1386 void MacroAssembler::set(intptr_t value, Register d) {
1387 AddressLiteral al(value);
1388 internal_set(al, d, false);
1389 }
1390
1391 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
1392 AddressLiteral al(addr, rspec);
1393 internal_set(al, d, false);
1394 }
1395
1396 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
1397 internal_set(al, d, true);
1398 }
1399
1400 void MacroAssembler::patchable_set(intptr_t value, Register d) {
1401 AddressLiteral al(value);
1402 internal_set(al, d, true);
1403 }
1404
1405
1406 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
1407 assert_not_delayed();
1408 v9_dep();
1409
1410 int hi = (int)(value >> 32);
1411 int lo = (int)(value & ~0);
1412 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1413 if (Assembler::is_simm13(lo) && value == lo) {
1414 or3(G0, lo, d);
1415 } else if (hi == 0) {
1416 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
1417 if (low10(lo) != 0)
1418 or3(d, low10(lo), d);
1419 }
1420 else if (hi == -1) {
1421 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
1422 xor3(d, low10(lo) ^ ~low10(~0), d);
1423 }
1424 else if (lo == 0) {
1425 if (Assembler::is_simm13(hi)) {
1426 or3(G0, hi, d);
1427 } else {
1428 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
1429 if (low10(hi) != 0)
1430 or3(d, low10(hi), d);
1431 }
1432 sllx(d, 32, d);
1433 }
1434 else {
1435 Assembler::sethi(hi, tmp);
1436 Assembler::sethi(lo, d); // macro assembler version sign-extends
1437 if (low10(hi) != 0)
1438 or3 (tmp, low10(hi), tmp);
1439 if (low10(lo) != 0)
1440 or3 ( d, low10(lo), d);
1441 sllx(tmp, 32, tmp);
1442 or3 (d, tmp, d);
1443 }
1444 }
1445
1446 // compute size in bytes of sparc frame, given
1447 // number of extraWords
1448 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
1449
1450 int nWords = frame::memory_parameter_word_sp_offset;
1451
1452 nWords += extraWords;
1453
1454 if (nWords & 1) ++nWords; // round up to double-word
1455
1456 return nWords * BytesPerWord;
1457 }
1458
1459
1460 // save_frame: given number of "extra" words in frame,
1461 // issue approp. save instruction (p 200, v8 manual)
1462
1463 void MacroAssembler::save_frame(int extraWords = 0) {
1464 int delta = -total_frame_size_in_bytes(extraWords);
1465 if (is_simm13(delta)) {
1466 save(SP, delta, SP);
1467 } else {
1468 set(delta, G3_scratch);
1469 save(SP, G3_scratch, SP);
1470 }
1471 }
1472
1473
1474 void MacroAssembler::save_frame_c1(int size_in_bytes) {
1475 if (is_simm13(-size_in_bytes)) {
1476 save(SP, -size_in_bytes, SP);
1477 } else {
1478 set(-size_in_bytes, G3_scratch);
1479 save(SP, G3_scratch, SP);
1480 }
1481 }
1482
1483
1484 void MacroAssembler::save_frame_and_mov(int extraWords,
1485 Register s1, Register d1,
1486 Register s2, Register d2) {
1487 assert_not_delayed();
1488
1489 // The trick here is to use precisely the same memory word
1490 // that trap handlers also use to save the register.
1491 // This word cannot be used for any other purpose, but
1492 // it works fine to save the register's value, whether or not
1493 // an interrupt flushes register windows at any given moment!
1494 Address s1_addr;
1495 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
1496 s1_addr = s1->address_in_saved_window();
1497 st_ptr(s1, s1_addr);
1498 }
1499
1500 Address s2_addr;
1501 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
1502 s2_addr = s2->address_in_saved_window();
1503 st_ptr(s2, s2_addr);
1504 }
1505
1506 save_frame(extraWords);
1507
1508 if (s1_addr.base() == SP) {
1509 ld_ptr(s1_addr.after_save(), d1);
1510 } else if (s1->is_valid()) {
1511 mov(s1->after_save(), d1);
1512 }
1513
1514 if (s2_addr.base() == SP) {
1515 ld_ptr(s2_addr.after_save(), d2);
1516 } else if (s2->is_valid()) {
1517 mov(s2->after_save(), d2);
1518 }
1519 }
1520
1521
1522 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
1523 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1524 int oop_index = oop_recorder()->allocate_index(obj);
1525 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1526 }
1527
1528
1529 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1530 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1531 int oop_index = oop_recorder()->find_index(obj);
1532 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1533 }
1534
1535 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
1536 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1537 int oop_index = oop_recorder()->find_index(obj);
1538 RelocationHolder rspec = oop_Relocation::spec(oop_index);
1539
1540 assert_not_delayed();
1541 // Relocation with special format (see relocInfo_sparc.hpp).
1542 relocate(rspec, 1);
1543 // Assembler::sethi(0x3fffff, d);
1544 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
1545 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1546 add(d, 0x3ff, d);
1547
1548 }
1549
1550
1551 void MacroAssembler::align(int modulus) {
1552 while (offset() % modulus != 0) nop();
1553 }
1554
1555
1556 void MacroAssembler::safepoint() {
1557 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));
1558 }
1559
1560
1561 void RegistersForDebugging::print(outputStream* s) {
1562 int j;
1563 for ( j = 0; j < 8; ++j )
1564 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]);
1565 else s->print_cr( "fp = 0x%.16lx", i[j]);
1566 s->cr();
1567
1568 for ( j = 0; j < 8; ++j )
1569 s->print_cr("l%d = 0x%.16lx", j, l[j]);
1570 s->cr();
1571
1572 for ( j = 0; j < 8; ++j )
1573 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]);
1574 else s->print_cr( "sp = 0x%.16lx", o[j]);
1575 s->cr();
1576
1577 for ( j = 0; j < 8; ++j )
1578 s->print_cr("g%d = 0x%.16lx", j, g[j]);
1579 s->cr();
1580
1581 // print out floats with compression
1582 for (j = 0; j < 32; ) {
1583 jfloat val = f[j];
1584 int last = j;
1585 for ( ; last+1 < 32; ++last ) {
1586 char b1[1024], b2[1024];
1587 sprintf(b1, "%f", val);
1588 sprintf(b2, "%f", f[last+1]);
1589 if (strcmp(b1, b2))
1590 break;
1591 }
1592 s->print("f%d", j);
1593 if ( j != last ) s->print(" - f%d", last);
1594 s->print(" = %f", val);
1595 s->fill_to(25);
1596 s->print_cr(" (0x%x)", val);
1597 j = last + 1;
1598 }
1599 s->cr();
1600
1601 // and doubles (evens only)
1602 for (j = 0; j < 32; ) {
1603 jdouble val = d[j];
1604 int last = j;
1605 for ( ; last+1 < 32; ++last ) {
1606 char b1[1024], b2[1024];
1607 sprintf(b1, "%f", val);
1608 sprintf(b2, "%f", d[last+1]);
1609 if (strcmp(b1, b2))
1610 break;
1611 }
1612 s->print("d%d", 2 * j);
1613 if ( j != last ) s->print(" - d%d", last);
1614 s->print(" = %f", val);
1615 s->fill_to(30);
1616 s->print("(0x%x)", *(int*)&val);
1617 s->fill_to(42);
1618 s->print_cr("(0x%x)", *(1 + (int*)&val));
1619 j = last + 1;
1620 }
1621 s->cr();
1622 }
1623
1624 void RegistersForDebugging::save_registers(MacroAssembler* a) {
1625 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
1626 a->flush_windows();
1627 int i;
1628 for (i = 0; i < 8; ++i) {
1629 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
1630 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
1631 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
1632 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
1633 }
1634 for (i = 0; i < 32; ++i) {
1635 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
1636 }
1637 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {
1638 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
1639 }
1640 }
1641
1642 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
1643 for (int i = 1; i < 8; ++i) {
1644 a->ld_ptr(r, g_offset(i), as_gRegister(i));
1645 }
1646 for (int j = 0; j < 32; ++j) {
1647 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
1648 }
1649 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {
1650 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
1651 }
1652 }
1653
1654
1655 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1656 void MacroAssembler::push_fTOS() {
1657 // %%%%%% need to implement this
1658 }
1659
1660 // pops double TOS element from CPU stack and pushes on FPU stack
1661 void MacroAssembler::pop_fTOS() {
1662 // %%%%%% need to implement this
1663 }
1664
1665 void MacroAssembler::empty_FPU_stack() {
1666 // %%%%%% need to implement this
1667 }
1668
1669 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
1670 // plausibility check for oops
1671 if (!VerifyOops) return;
1672
1673 if (reg == G0) return; // always NULL, which is always an oop
1674
1675 char buffer[64];
1676 #ifdef COMPILER1
1677 if (CommentedAssembly) {
1678 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
1679 block_comment(buffer);
1680 }
1681 #endif
1682
1683 int len = strlen(file) + strlen(msg) + 1 + 4;
1684 sprintf(buffer, "%d", line);
1685 len += strlen(buffer);
1686 sprintf(buffer, " at offset %d ", offset());
1687 len += strlen(buffer);
1688 char * real_msg = new char[len];
1689 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);
1690
1691 // Call indirectly to solve generation ordering problem
1692 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1693
1694 // Make some space on stack above the current register window.
1695 // Enough to hold 8 64-bit registers.
1696 add(SP,-8*8,SP);
1697
1698 // Save some 64-bit registers; a normal 'save' chops the heads off
1699 // of 64-bit longs in the 32-bit build.
1700 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1701 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1702 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
1703 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1704
1705 set((intptr_t)real_msg, O1);
1706 // Load address to call to into O7
1707 load_ptr_contents(a, O7);
1708 // Register call to verify_oop_subroutine
1709 callr(O7, G0);
1710 delayed()->nop();
1711 // recover frame size
1712 add(SP, 8*8,SP);
1713 }
1714
1715 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
1716 // plausibility check for oops
1717 if (!VerifyOops) return;
1718
1719 char buffer[64];
1720 sprintf(buffer, "%d", line);
1721 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);
1722 sprintf(buffer, " at SP+%d ", addr.disp());
1723 len += strlen(buffer);
1724 char * real_msg = new char[len];
1725 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
1726
1727 // Call indirectly to solve generation ordering problem
1728 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1729
1730 // Make some space on stack above the current register window.
1731 // Enough to hold 8 64-bit registers.
1732 add(SP,-8*8,SP);
1733
1734 // Save some 64-bit registers; a normal 'save' chops the heads off
1735 // of 64-bit longs in the 32-bit build.
1736 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1737 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1738 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
1739 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1740
1741 set((intptr_t)real_msg, O1);
1742 // Load address to call to into O7
1743 load_ptr_contents(a, O7);
1744 // Register call to verify_oop_subroutine
1745 callr(O7, G0);
1746 delayed()->nop();
1747 // recover frame size
1748 add(SP, 8*8,SP);
1749 }
1750
1751 // side-door communication with signalHandler in os_solaris.cpp
1752 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
1753
1754 // This macro is expanded just once; it creates shared code. Contract:
1755 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
1756 // registers, including flags. May not use a register 'save', as this blows
1757 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
1758 // call.
1759 void MacroAssembler::verify_oop_subroutine() {
1760 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );
1761
1762 // Leaf call; no frame.
1763 Label succeed, fail, null_or_fail;
1764
1765 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
1766 // O0 is now the oop to be checked. O7 is the return address.
1767 Register O0_obj = O0;
1768
1769 // Save some more registers for temps.
1770 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
1771 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
1772 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
1773 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
1774
1775 // Save flags
1776 Register O5_save_flags = O5;
1777 rdccr( O5_save_flags );
1778
1779 { // count number of verifies
1780 Register O2_adr = O2;
1781 Register O3_accum = O3;
1782 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1783 }
1784
1785 Register O2_mask = O2;
1786 Register O3_bits = O3;
1787 Register O4_temp = O4;
1788
1789 // mark lower end of faulting range
1790 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1791 _verify_oop_implicit_branch[0] = pc();
1792
1793 // We can't check the mark oop because it could be in the process of
1794 // locking or unlocking while this is running.
1795 set(Universe::verify_oop_mask (), O2_mask);
1796 set(Universe::verify_oop_bits (), O3_bits);
1797
1798 // assert((obj & oop_mask) == oop_bits);
1799 and3(O0_obj, O2_mask, O4_temp);
1800 cmp(O4_temp, O3_bits);
1801 brx(notEqual, false, pn, null_or_fail);
1802 delayed()->nop();
1803
1804 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1805 // the null_or_fail case is useless; must test for null separately
1806 br_null(O0_obj, false, pn, succeed);
1807 delayed()->nop();
1808 }
1809
1810 // Check the klassOop of this object for being in the right area of memory.
1811 // Cannot do the load in the delay above slot in case O0 is null
1812 load_klass(O0_obj, O0_obj);
1813 // assert((klass & klass_mask) == klass_bits);
1814 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() )
1815 set(Universe::verify_klass_mask(), O2_mask);
1816 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() )
1817 set(Universe::verify_klass_bits(), O3_bits);
1818 and3(O0_obj, O2_mask, O4_temp);
1819 cmp(O4_temp, O3_bits);
1820 brx(notEqual, false, pn, fail);
1821 delayed()->nop();
1822 // Check the klass's klass
1823 load_klass(O0_obj, O0_obj);
1824 and3(O0_obj, O2_mask, O4_temp);
1825 cmp(O4_temp, O3_bits);
1826 brx(notEqual, false, pn, fail);
1827 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1828
1829 // mark upper end of faulting range
1830 _verify_oop_implicit_branch[1] = pc();
1831
1832 //-----------------------
1833 // all tests pass
1834 bind(succeed);
1835
1836 // Restore prior 64-bit registers
1837 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1838 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1839 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1840 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1841 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
1842 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
1843
1844 retl(); // Leaf return; restore prior O7 in delay slot
1845 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
1846
1847 //-----------------------
1848 bind(null_or_fail); // nulls are less common but OK
1849 br_null(O0_obj, false, pt, succeed);
1850 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1851
1852 //-----------------------
1853 // report failure:
1854 bind(fail);
1855 _verify_oop_implicit_branch[2] = pc();
1856
1857 wrccr( O5_save_flags ); // Restore CCR's
1858
1859 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1860
1861 // stop_subroutine expects message pointer in I1.
1862 mov(I1, O1);
1863
1864 // Restore prior 64-bit registers
1865 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
1866 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
1867 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
1868 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
1869 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
1870 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
1871
1872 // factor long stop-sequence into subroutine to save space
1873 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1874
1875 // call indirectly to solve generation ordering problem
1876 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
1877 load_ptr_contents(al, O5);
1878 jmpl(O5, 0, O7);
1879 delayed()->nop();
1880 }
1881
1882
1883 void MacroAssembler::stop(const char* msg) {
1884 // save frame first to get O7 for return address
1885 // add one word to size in case struct is odd number of words long
1886 // It must be doubleword-aligned for storing doubles into it.
1887
1888 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1889
1890 // stop_subroutine expects message pointer in I1.
1891 set((intptr_t)msg, O1);
1892
1893 // factor long stop-sequence into subroutine to save space
1894 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1895
1896 // call indirectly to solve generation ordering problem
1897 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
1898 load_ptr_contents(a, O5);
1899 jmpl(O5, 0, O7);
1900 delayed()->nop();
1901
1902 breakpoint_trap(); // make stop actually stop rather than writing
1903 // unnoticeable results in the output files.
1904
1905 // restore(); done in callee to save space!
1906 }
1907
1908
1909 void MacroAssembler::warn(const char* msg) {
1910 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1911 RegistersForDebugging::save_registers(this);
1912 mov(O0, L0);
1913 set((intptr_t)msg, O0);
1914 call( CAST_FROM_FN_PTR(address, warning) );
1915 delayed()->nop();
1916 // ret();
1917 // delayed()->restore();
1918 RegistersForDebugging::restore_registers(this, L0);
1919 restore();
1920 }
1921
1922
1923 void MacroAssembler::untested(const char* what) {
1924 // We must be able to turn interactive prompting off
1925 // in order to run automated test scripts on the VM
1926 // Use the flag ShowMessageBoxOnError
1927
1928 char* b = new char[1024];
1929 sprintf(b, "untested: %s", what);
1930
1931 if ( ShowMessageBoxOnError ) stop(b);
1932 else warn(b);
1933 }
1934
1935
1936 void MacroAssembler::stop_subroutine() {
1937 RegistersForDebugging::save_registers(this);
1938
1939 // for the sake of the debugger, stick a PC on the current frame
1940 // (this assumes that the caller has performed an extra "save")
1941 mov(I7, L7);
1942 add(O7, -7 * BytesPerInt, I7);
1943
1944 save_frame(); // one more save to free up another O7 register
1945 mov(I0, O1); // addr of reg save area
1946
1947 // We expect pointer to message in I1. Caller must set it up in O1
1948 mov(I1, O0); // get msg
1949 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
1950 delayed()->nop();
1951
1952 restore();
1953
1954 RegistersForDebugging::restore_registers(this, O0);
1955
1956 save_frame(0);
1957 call(CAST_FROM_FN_PTR(address,breakpoint));
1958 delayed()->nop();
1959 restore();
1960
1961 mov(L7, I7);
1962 retl();
1963 delayed()->restore(); // see stop above
1964 }
1965
1966
1967 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
1968 if ( ShowMessageBoxOnError ) {
1969 JavaThreadState saved_state = JavaThread::current()->thread_state();
1970 JavaThread::current()->set_thread_state(_thread_in_vm);
1971 {
1972 // In order to get locks work, we need to fake a in_VM state
1973 ttyLocker ttyl;
1974 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
1975 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
1976 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value());
1977 }
1978 if (os::message_box(msg, "Execution stopped, print registers?"))
1979 regs->print(::tty);
1980 }
1981 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
1982 }
1983 else
1984 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
1985 assert(false, "error");
1986 }
1987
1988
1989 #ifndef PRODUCT
1990 void MacroAssembler::test() {
1991 ResourceMark rm;
1992
1993 CodeBuffer cb("test", 10000, 10000);
1994 MacroAssembler* a = new MacroAssembler(&cb);
1995 VM_Version::allow_all();
1996 a->test_v9();
1997 a->test_v8_onlys();
1998 VM_Version::revert();
1999
2000 StubRoutines::Sparc::test_stop_entry()();
2001 }
2002 #endif
2003
2004
2005 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
2006 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
2007 Label no_extras;
2008 br( negative, true, pt, no_extras ); // if neg, clear reg
2009 delayed()->set(0, Rresult); // annuled, so only if taken
2010 bind( no_extras );
2011 }
2012
2013
2014 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
2015 #ifdef _LP64
2016 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
2017 #else
2018 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
2019 #endif
2020 bclr(1, Rresult);
2021 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
2022 }
2023
2024
2025 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
2026 calc_frame_size(Rextra_words, Rresult);
2027 neg(Rresult);
2028 save(SP, Rresult, SP);
2029 }
2030
2031
2032 // ---------------------------------------------------------
2033 Assembler::RCondition cond2rcond(Assembler::Condition c) {
2034 switch (c) {
2035 /*case zero: */
2036 case Assembler::equal: return Assembler::rc_z;
2037 case Assembler::lessEqual: return Assembler::rc_lez;
2038 case Assembler::less: return Assembler::rc_lz;
2039 /*case notZero:*/
2040 case Assembler::notEqual: return Assembler::rc_nz;
2041 case Assembler::greater: return Assembler::rc_gz;
2042 case Assembler::greaterEqual: return Assembler::rc_gez;
2043 }
2044 ShouldNotReachHere();
2045 return Assembler::rc_z;
2046 }
2047
2048 // compares register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
2049 void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) {
2050 tst(s1);
2051 br (c, a, p, L);
2052 }
2053
2054
2055 // Compares a pointer register with zero and branches on null.
2056 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
2057 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
2058 assert_not_delayed();
2059 #ifdef _LP64
2060 bpr( rc_z, a, p, s1, L );
2061 #else
2062 tst(s1);
2063 br ( zero, a, p, L );
2064 #endif
2065 }
2066
2067 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
2068 assert_not_delayed();
2069 #ifdef _LP64
2070 bpr( rc_nz, a, p, s1, L );
2071 #else
2072 tst(s1);
2073 br ( notZero, a, p, L );
2074 #endif
2075 }
2076
2077 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2078 Register s1, address d,
2079 relocInfo::relocType rt ) {
2080 if (VM_Version::v9_instructions_work()) {
2081 bpr(rc, a, p, s1, d, rt);
2082 } else {
2083 tst(s1);
2084 br(reg_cond_to_cc_cond(rc), a, p, d, rt);
2085 }
2086 }
2087
2088 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2089 Register s1, Label& L ) {
2090 if (VM_Version::v9_instructions_work()) {
2091 bpr(rc, a, p, s1, L);
2092 } else {
2093 tst(s1);
2094 br(reg_cond_to_cc_cond(rc), a, p, L);
2095 }
2096 }
2097
2098
2099 // instruction sequences factored across compiler & interpreter
2100
2101
2102 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
2103 Register Rb_hi, Register Rb_low,
2104 Register Rresult) {
2105
2106 Label check_low_parts, done;
2107
2108 cmp(Ra_hi, Rb_hi ); // compare hi parts
2109 br(equal, true, pt, check_low_parts);
2110 delayed()->cmp(Ra_low, Rb_low); // test low parts
2111
2112 // And, with an unsigned comparison, it does not matter if the numbers
2113 // are negative or not.
2114 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
2115 // The second one is bigger (unsignedly).
2116
2117 // Other notes: The first move in each triplet can be unconditional
2118 // (and therefore probably prefetchable).
2119 // And the equals case for the high part does not need testing,
2120 // since that triplet is reached only after finding the high halves differ.
2121
2122 if (VM_Version::v9_instructions_work()) {
2123
2124 mov ( -1, Rresult);
2125 ba( false, done ); delayed()-> movcc(greater, false, icc, 1, Rresult);
2126 }
2127 else {
2128 br(less, true, pt, done); delayed()-> set(-1, Rresult);
2129 br(greater, true, pt, done); delayed()-> set( 1, Rresult);
2130 }
2131
2132 bind( check_low_parts );
2133
2134 if (VM_Version::v9_instructions_work()) {
2135 mov( -1, Rresult);
2136 movcc(equal, false, icc, 0, Rresult);
2137 movcc(greaterUnsigned, false, icc, 1, Rresult);
2138 }
2139 else {
2140 set(-1, Rresult);
2141 br(equal, true, pt, done); delayed()->set( 0, Rresult);
2142 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
2143 }
2144 bind( done );
2145 }
2146
2147 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
2148 subcc( G0, Rlow, Rlow );
2149 subc( G0, Rhi, Rhi );
2150 }
2151
2152 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
2153 Register Rcount,
2154 Register Rout_high, Register Rout_low,
2155 Register Rtemp ) {
2156
2157
2158 Register Ralt_count = Rtemp;
2159 Register Rxfer_bits = Rtemp;
2160
2161 assert( Ralt_count != Rin_high
2162 && Ralt_count != Rin_low
2163 && Ralt_count != Rcount
2164 && Rxfer_bits != Rin_low
2165 && Rxfer_bits != Rin_high
2166 && Rxfer_bits != Rcount
2167 && Rxfer_bits != Rout_low
2168 && Rout_low != Rin_high,
2169 "register alias checks");
2170
2171 Label big_shift, done;
2172
2173 // This code can be optimized to use the 64 bit shifts in V9.
2174 // Here we use the 32 bit shifts.
2175
2176 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2177 subcc(Rcount, 31, Ralt_count);
2178 br(greater, true, pn, big_shift);
2179 delayed()->
2180 dec(Ralt_count);
2181
2182 // shift < 32 bits, Ralt_count = Rcount-31
2183
2184 // We get the transfer bits by shifting right by 32-count the low
2185 // register. This is done by shifting right by 31-count and then by one
2186 // more to take care of the special (rare) case where count is zero
2187 // (shifting by 32 would not work).
2188
2189 neg( Ralt_count );
2190
2191 // The order of the next two instructions is critical in the case where
2192 // Rin and Rout are the same and should not be reversed.
2193
2194 srl( Rin_low, Ralt_count, Rxfer_bits ); // shift right by 31-count
2195 if (Rcount != Rout_low) {
2196 sll( Rin_low, Rcount, Rout_low ); // low half
2197 }
2198 sll( Rin_high, Rcount, Rout_high );
2199 if (Rcount == Rout_low) {
2200 sll( Rin_low, Rcount, Rout_low ); // low half
2201 }
2202 srl( Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
2203 ba (false, done);
2204 delayed()->
2205 or3( Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
2206
2207 // shift >= 32 bits, Ralt_count = Rcount-32
2208 bind(big_shift);
2209 sll( Rin_low, Ralt_count, Rout_high );
2210 clr( Rout_low );
2211
2212 bind(done);
2213 }
2214
2215
2216 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
2217 Register Rcount,
2218 Register Rout_high, Register Rout_low,
2219 Register Rtemp ) {
2220
2221 Register Ralt_count = Rtemp;
2222 Register Rxfer_bits = Rtemp;
2223
2224 assert( Ralt_count != Rin_high
2225 && Ralt_count != Rin_low
2226 && Ralt_count != Rcount
2227 && Rxfer_bits != Rin_low
2228 && Rxfer_bits != Rin_high
2229 && Rxfer_bits != Rcount
2230 && Rxfer_bits != Rout_high
2231 && Rout_high != Rin_low,
2232 "register alias checks");
2233
2234 Label big_shift, done;
2235
2236 // This code can be optimized to use the 64 bit shifts in V9.
2237 // Here we use the 32 bit shifts.
2238
2239 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2240 subcc(Rcount, 31, Ralt_count);
2241 br(greater, true, pn, big_shift);
2242 delayed()->dec(Ralt_count);
2243
2244 // shift < 32 bits, Ralt_count = Rcount-31
2245
2246 // We get the transfer bits by shifting left by 32-count the high
2247 // register. This is done by shifting left by 31-count and then by one
2248 // more to take care of the special (rare) case where count is zero
2249 // (shifting by 32 would not work).
2250
2251 neg( Ralt_count );
2252 if (Rcount != Rout_low) {
2253 srl( Rin_low, Rcount, Rout_low );
2254 }
2255
2256 // The order of the next two instructions is critical in the case where
2257 // Rin and Rout are the same and should not be reversed.
2258
2259 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count
2260 sra( Rin_high, Rcount, Rout_high ); // high half
2261 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more
2262 if (Rcount == Rout_low) {
2263 srl( Rin_low, Rcount, Rout_low );
2264 }
2265 ba (false, done);
2266 delayed()->
2267 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high
2268
2269 // shift >= 32 bits, Ralt_count = Rcount-32
2270 bind(big_shift);
2271
2272 sra( Rin_high, Ralt_count, Rout_low );
2273 sra( Rin_high, 31, Rout_high ); // sign into hi
2274
2275 bind( done );
2276 }
2277
2278
2279
2280 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
2281 Register Rcount,
2282 Register Rout_high, Register Rout_low,
2283 Register Rtemp ) {
2284
2285 Register Ralt_count = Rtemp;
2286 Register Rxfer_bits = Rtemp;
2287
2288 assert( Ralt_count != Rin_high
2289 && Ralt_count != Rin_low
2290 && Ralt_count != Rcount
2291 && Rxfer_bits != Rin_low
2292 && Rxfer_bits != Rin_high
2293 && Rxfer_bits != Rcount
2294 && Rxfer_bits != Rout_high
2295 && Rout_high != Rin_low,
2296 "register alias checks");
2297
2298 Label big_shift, done;
2299
2300 // This code can be optimized to use the 64 bit shifts in V9.
2301 // Here we use the 32 bit shifts.
2302
2303 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2304 subcc(Rcount, 31, Ralt_count);
2305 br(greater, true, pn, big_shift);
2306 delayed()->dec(Ralt_count);
2307
2308 // shift < 32 bits, Ralt_count = Rcount-31
2309
2310 // We get the transfer bits by shifting left by 32-count the high
2311 // register. This is done by shifting left by 31-count and then by one
2312 // more to take care of the special (rare) case where count is zero
2313 // (shifting by 32 would not work).
2314
2315 neg( Ralt_count );
2316 if (Rcount != Rout_low) {
2317 srl( Rin_low, Rcount, Rout_low );
2318 }
2319
2320 // The order of the next two instructions is critical in the case where
2321 // Rin and Rout are the same and should not be reversed.
2322
2323 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count
2324 srl( Rin_high, Rcount, Rout_high ); // high half
2325 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more
2326 if (Rcount == Rout_low) {
2327 srl( Rin_low, Rcount, Rout_low );
2328 }
2329 ba (false, done);
2330 delayed()->
2331 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high
2332
2333 // shift >= 32 bits, Ralt_count = Rcount-32
2334 bind(big_shift);
2335
2336 srl( Rin_high, Ralt_count, Rout_low );
2337 clr( Rout_high );
2338
2339 bind( done );
2340 }
2341
2342 #ifdef _LP64
2343 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
2344 cmp(Ra, Rb);
2345 mov( -1, Rresult);
2346 movcc(equal, false, xcc, 0, Rresult);
2347 movcc(greater, false, xcc, 1, Rresult);
2348 }
2349 #endif
2350
2351
2352 void MacroAssembler::load_sized_value(Address src, Register dst,
2353 size_t size_in_bytes, bool is_signed) {
2354 switch (size_in_bytes) {
2355 case 8: ldx(src, dst); break;
2356 case 4: ld( src, dst); break;
2357 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;
2358 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;
2359 default: ShouldNotReachHere();
2360 }
2361 }
2362
2363
2364 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2365 FloatRegister Fa, FloatRegister Fb,
2366 Register Rresult) {
2367
2368 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
2369
2370 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less;
2371 Condition eq = f_equal;
2372 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater;
2373
2374 if (VM_Version::v9_instructions_work()) {
2375
2376 mov( -1, Rresult );
2377 movcc( eq, true, fcc0, 0, Rresult );
2378 movcc( gt, true, fcc0, 1, Rresult );
2379
2380 } else {
2381 Label done;
2382
2383 set( -1, Rresult );
2384 //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
2385 fb( eq, true, pn, done); delayed()->set( 0, Rresult );
2386 fb( gt, true, pn, done); delayed()->set( 1, Rresult );
2387
2388 bind (done);
2389 }
2390 }
2391
2392
2393 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2394 {
2395 if (VM_Version::v9_instructions_work()) {
2396 Assembler::fneg(w, s, d);
2397 } else {
2398 if (w == FloatRegisterImpl::S) {
2399 Assembler::fneg(w, s, d);
2400 } else if (w == FloatRegisterImpl::D) {
2401 // number() does a sanity check on the alignment.
2402 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2403 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2404
2405 Assembler::fneg(FloatRegisterImpl::S, s, d);
2406 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2407 } else {
2408 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2409
2410 // number() does a sanity check on the alignment.
2411 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2412 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2413
2414 Assembler::fneg(FloatRegisterImpl::S, s, d);
2415 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2416 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2417 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2418 }
2419 }
2420 }
2421
2422 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2423 {
2424 if (VM_Version::v9_instructions_work()) {
2425 Assembler::fmov(w, s, d);
2426 } else {
2427 if (w == FloatRegisterImpl::S) {
2428 Assembler::fmov(w, s, d);
2429 } else if (w == FloatRegisterImpl::D) {
2430 // number() does a sanity check on the alignment.
2431 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2432 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2433
2434 Assembler::fmov(FloatRegisterImpl::S, s, d);
2435 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2436 } else {
2437 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2438
2439 // number() does a sanity check on the alignment.
2440 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2441 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2442
2443 Assembler::fmov(FloatRegisterImpl::S, s, d);
2444 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2445 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2446 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2447 }
2448 }
2449 }
2450
2451 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2452 {
2453 if (VM_Version::v9_instructions_work()) {
2454 Assembler::fabs(w, s, d);
2455 } else {
2456 if (w == FloatRegisterImpl::S) {
2457 Assembler::fabs(w, s, d);
2458 } else if (w == FloatRegisterImpl::D) {
2459 // number() does a sanity check on the alignment.
2460 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2461 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2462
2463 Assembler::fabs(FloatRegisterImpl::S, s, d);
2464 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2465 } else {
2466 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2467
2468 // number() does a sanity check on the alignment.
2469 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2470 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2471
2472 Assembler::fabs(FloatRegisterImpl::S, s, d);
2473 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2474 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2475 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2476 }
2477 }
2478 }
2479
2480 void MacroAssembler::save_all_globals_into_locals() {
2481 mov(G1,L1);
2482 mov(G2,L2);
2483 mov(G3,L3);
2484 mov(G4,L4);
2485 mov(G5,L5);
2486 mov(G6,L6);
2487 mov(G7,L7);
2488 }
2489
2490 void MacroAssembler::restore_globals_from_locals() {
2491 mov(L1,G1);
2492 mov(L2,G2);
2493 mov(L3,G3);
2494 mov(L4,G4);
2495 mov(L5,G5);
2496 mov(L6,G6);
2497 mov(L7,G7);
2498 }
2499
2500 // Use for 64 bit operation.
2501 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2502 {
2503 // store ptr_reg as the new top value
2504 #ifdef _LP64
2505 casx(top_ptr_reg, top_reg, ptr_reg);
2506 #else
2507 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);
2508 #endif // _LP64
2509 }
2510
2511 // [RGV] This routine does not handle 64 bit operations.
2512 // use casx_under_lock() or casx directly!!!
2513 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2514 {
2515 // store ptr_reg as the new top value
2516 if (VM_Version::v9_instructions_work()) {
2517 cas(top_ptr_reg, top_reg, ptr_reg);
2518 } else {
2519
2520 // If the register is not an out nor global, it is not visible
2521 // after the save. Allocate a register for it, save its
2522 // value in the register save area (the save may not flush
2523 // registers to the save area).
2524
2525 Register top_ptr_reg_after_save;
2526 Register top_reg_after_save;
2527 Register ptr_reg_after_save;
2528
2529 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {
2530 top_ptr_reg_after_save = top_ptr_reg->after_save();
2531 } else {
2532 Address reg_save_addr = top_ptr_reg->address_in_saved_window();
2533 top_ptr_reg_after_save = L0;
2534 st(top_ptr_reg, reg_save_addr);
2535 }
2536
2537 if (top_reg->is_out() || top_reg->is_global()) {
2538 top_reg_after_save = top_reg->after_save();
2539 } else {
2540 Address reg_save_addr = top_reg->address_in_saved_window();
2541 top_reg_after_save = L1;
2542 st(top_reg, reg_save_addr);
2543 }
2544
2545 if (ptr_reg->is_out() || ptr_reg->is_global()) {
2546 ptr_reg_after_save = ptr_reg->after_save();
2547 } else {
2548 Address reg_save_addr = ptr_reg->address_in_saved_window();
2549 ptr_reg_after_save = L2;
2550 st(ptr_reg, reg_save_addr);
2551 }
2552
2553 const Register& lock_reg = L3;
2554 const Register& lock_ptr_reg = L4;
2555 const Register& value_reg = L5;
2556 const Register& yield_reg = L6;
2557 const Register& yieldall_reg = L7;
2558
2559 save_frame();
2560
2561 if (top_ptr_reg_after_save == L0) {
2562 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);
2563 }
2564
2565 if (top_reg_after_save == L1) {
2566 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
2567 }
2568
2569 if (ptr_reg_after_save == L2) {
2570 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
2571 }
2572
2573 Label(retry_get_lock);
2574 Label(not_same);
2575 Label(dont_yield);
2576
2577 assert(lock_addr, "lock_address should be non null for v8");
2578 set((intptr_t)lock_addr, lock_ptr_reg);
2579 // Initialize yield counter
2580 mov(G0,yield_reg);
2581 mov(G0, yieldall_reg);
2582 set(StubRoutines::Sparc::locked, lock_reg);
2583
2584 bind(retry_get_lock);
2585 cmp(yield_reg, V8AtomicOperationUnderLockSpinCount);
2586 br(Assembler::less, false, Assembler::pt, dont_yield);
2587 delayed()->nop();
2588
2589 if(use_call_vm) {
2590 Untested("Need to verify global reg consistancy");
2591 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
2592 } else {
2593 // Save the regs and make space for a C call
2594 save(SP, -96, SP);
2595 save_all_globals_into_locals();
2596 call(CAST_FROM_FN_PTR(address,os::yield_all));
2597 delayed()->mov(yieldall_reg, O0);
2598 restore_globals_from_locals();
2599 restore();
2600 }
2601
2602 // reset the counter
2603 mov(G0,yield_reg);
2604 add(yieldall_reg, 1, yieldall_reg);
2605
2606 bind(dont_yield);
2607 // try to get lock
2608 swap(lock_ptr_reg, 0, lock_reg);
2609
2610 // did we get the lock?
2611 cmp(lock_reg, StubRoutines::Sparc::unlocked);
2612 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
2613 delayed()->add(yield_reg,1,yield_reg);
2614
2615 // yes, got lock. do we have the same top?
2616 ld(top_ptr_reg_after_save, 0, value_reg);
2617 cmp(value_reg, top_reg_after_save);
2618 br(Assembler::notEqual, false, Assembler::pn, not_same);
2619 delayed()->nop();
2620
2621 // yes, same top.
2622 st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
2623 membar(Assembler::StoreStore);
2624
2625 bind(not_same);
2626 mov(value_reg, ptr_reg_after_save);
2627 st(lock_reg, lock_ptr_reg, 0); // unlock
2628
2629 restore();
2630 }
2631 }
2632
2633 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2634 Register tmp,
2635 int offset) {
2636 intptr_t value = *delayed_value_addr;
2637 if (value != 0)
2638 return RegisterOrConstant(value + offset);
2639
2640 // load indirectly to solve generation ordering problem
2641 AddressLiteral a(delayed_value_addr);
2642 load_ptr_contents(a, tmp);
2643
2644 #ifdef ASSERT
2645 tst(tmp);
2646 breakpoint_trap(zero, xcc);
2647 #endif
2648
2649 if (offset != 0)
2650 add(tmp, offset, tmp);
2651
2652 return RegisterOrConstant(tmp);
2653 }
2654
2655
2656 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2657 assert(d.register_or_noreg() != G0, "lost side effect");
2658 if ((s2.is_constant() && s2.as_constant() == 0) ||
2659 (s2.is_register() && s2.as_register() == G0)) {
2660 // Do nothing, just move value.
2661 if (s1.is_register()) {
2662 if (d.is_constant()) d = temp;
2663 mov(s1.as_register(), d.as_register());
2664 return d;
2665 } else {
2666 return s1;
2667 }
2668 }
2669
2670 if (s1.is_register()) {
2671 assert_different_registers(s1.as_register(), temp);
2672 if (d.is_constant()) d = temp;
2673 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2674 return d;
2675 } else {
2676 if (s2.is_register()) {
2677 assert_different_registers(s2.as_register(), temp);
2678 if (d.is_constant()) d = temp;
2679 set(s1.as_constant(), temp);
2680 andn(temp, s2.as_register(), d.as_register());
2681 return d;
2682 } else {
2683 intptr_t res = s1.as_constant() & ~s2.as_constant();
2684 return res;
2685 }
2686 }
2687 }
2688
2689 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2690 assert(d.register_or_noreg() != G0, "lost side effect");
2691 if ((s2.is_constant() && s2.as_constant() == 0) ||
2692 (s2.is_register() && s2.as_register() == G0)) {
2693 // Do nothing, just move value.
2694 if (s1.is_register()) {
2695 if (d.is_constant()) d = temp;
2696 mov(s1.as_register(), d.as_register());
2697 return d;
2698 } else {
2699 return s1;
2700 }
2701 }
2702
2703 if (s1.is_register()) {
2704 assert_different_registers(s1.as_register(), temp);
2705 if (d.is_constant()) d = temp;
2706 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2707 return d;
2708 } else {
2709 if (s2.is_register()) {
2710 assert_different_registers(s2.as_register(), temp);
2711 if (d.is_constant()) d = temp;
2712 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register());
2713 return d;
2714 } else {
2715 intptr_t res = s1.as_constant() + s2.as_constant();
2716 return res;
2717 }
2718 }
2719 }
2720
2721 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2722 assert(d.register_or_noreg() != G0, "lost side effect");
2723 if (!is_simm13(s2.constant_or_zero()))
2724 s2 = (s2.as_constant() & 0xFF);
2725 if ((s2.is_constant() && s2.as_constant() == 0) ||
2726 (s2.is_register() && s2.as_register() == G0)) {
2727 // Do nothing, just move value.
2728 if (s1.is_register()) {
2729 if (d.is_constant()) d = temp;
2730 mov(s1.as_register(), d.as_register());
2731 return d;
2732 } else {
2733 return s1;
2734 }
2735 }
2736
2737 if (s1.is_register()) {
2738 assert_different_registers(s1.as_register(), temp);
2739 if (d.is_constant()) d = temp;
2740 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2741 return d;
2742 } else {
2743 if (s2.is_register()) {
2744 assert_different_registers(s2.as_register(), temp);
2745 if (d.is_constant()) d = temp;
2746 set(s1.as_constant(), temp);
2747 sll_ptr(temp, s2.as_register(), d.as_register());
2748 return d;
2749 } else {
2750 intptr_t res = s1.as_constant() << s2.as_constant();
2751 return res;
2752 }
2753 }
2754 }
2755
2756
2757 // Look up the method for a megamorphic invokeinterface call.
2758 // The target method is determined by <intf_klass, itable_index>.
2759 // The receiver klass is in recv_klass.
2760 // On success, the result will be in method_result, and execution falls through.
2761 // On failure, execution transfers to the given label.
2762 void MacroAssembler::lookup_interface_method(Register recv_klass,
2763 Register intf_klass,
2764 RegisterOrConstant itable_index,
2765 Register method_result,
2766 Register scan_temp,
2767 Register sethi_temp,
2768 Label& L_no_such_interface) {
2769 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
2770 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
2771 "caller must use same register for non-constant itable index as for method");
2772
2773 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2774 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
2775 int scan_step = itableOffsetEntry::size() * wordSize;
2776 int vte_size = vtableEntry::size() * wordSize;
2777
2778 lduw(recv_klass, instanceKlass::vtable_length_offset() * wordSize, scan_temp);
2779 // %%% We should store the aligned, prescaled offset in the klassoop.
2780 // Then the next several instructions would fold away.
2781
2782 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
2783 int itb_offset = vtable_base;
2784 if (round_to_unit != 0) {
2785 // hoist first instruction of round_to(scan_temp, BytesPerLong):
2786 itb_offset += round_to_unit - wordSize;
2787 }
2788 int itb_scale = exact_log2(vtableEntry::size() * wordSize);
2789 sll(scan_temp, itb_scale, scan_temp);
2790 add(scan_temp, itb_offset, scan_temp);
2791 if (round_to_unit != 0) {
2792 // Round up to align_object_offset boundary
2793 // see code for instanceKlass::start_of_itable!
2794 // Was: round_to(scan_temp, BytesPerLong);
2795 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
2796 and3(scan_temp, -round_to_unit, scan_temp);
2797 }
2798 add(recv_klass, scan_temp, scan_temp);
2799
2800 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
2801 RegisterOrConstant itable_offset = itable_index;
2802 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset);
2803 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset);
2804 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass);
2805
2806 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
2807 // if (scan->interface() == intf) {
2808 // result = (klass + scan->offset() + itable_index);
2809 // }
2810 // }
2811 Label search, found_method;
2812
2813 for (int peel = 1; peel >= 0; peel--) {
2814 // %%%% Could load both offset and interface in one ldx, if they were
2815 // in the opposite order. This would save a load.
2816 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
2817
2818 // Check that this entry is non-null. A null entry means that
2819 // the receiver class doesn't implement the interface, and wasn't the
2820 // same as when the caller was compiled.
2821 bpr(Assembler::rc_z, false, Assembler::pn, method_result, L_no_such_interface);
2822 delayed()->cmp(method_result, intf_klass);
2823
2824 if (peel) {
2825 brx(Assembler::equal, false, Assembler::pt, found_method);
2826 } else {
2827 brx(Assembler::notEqual, false, Assembler::pn, search);
2828 // (invert the test to fall through to found_method...)
2829 }
2830 delayed()->add(scan_temp, scan_step, scan_temp);
2831
2832 if (!peel) break;
2833
2834 bind(search);
2835 }
2836
2837 bind(found_method);
2838
2839 // Got a hit.
2840 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
2841 // scan_temp[-scan_step] points to the vtable offset we need
2842 ito_offset -= scan_step;
2843 lduw(scan_temp, ito_offset, scan_temp);
2844 ld_ptr(recv_klass, scan_temp, method_result);
2845 }
2846
2847
2848 void MacroAssembler::check_klass_subtype(Register sub_klass,
2849 Register super_klass,
2850 Register temp_reg,
2851 Register temp2_reg,
2852 Label& L_success) {
2853 Label L_failure, L_pop_to_failure;
2854 check_klass_subtype_fast_path(sub_klass, super_klass,
2855 temp_reg, temp2_reg,
2856 &L_success, &L_failure, NULL);
2857 Register sub_2 = sub_klass;
2858 Register sup_2 = super_klass;
2859 if (!sub_2->is_global()) sub_2 = L0;
2860 if (!sup_2->is_global()) sup_2 = L1;
2861
2862 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2863 check_klass_subtype_slow_path(sub_2, sup_2,
2864 L2, L3, L4, L5,
2865 NULL, &L_pop_to_failure);
2866
2867 // on success:
2868 restore();
2869 ba(false, L_success);
2870 delayed()->nop();
2871
2872 // on failure:
2873 bind(L_pop_to_failure);
2874 restore();
2875 bind(L_failure);
2876 }
2877
2878
2879 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
2880 Register super_klass,
2881 Register temp_reg,
2882 Register temp2_reg,
2883 Label* L_success,
2884 Label* L_failure,
2885 Label* L_slow_path,
2886 RegisterOrConstant super_check_offset,
2887 Register instanceof_hack) {
2888 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
2889 Klass::secondary_super_cache_offset_in_bytes());
2890 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
2891 Klass::super_check_offset_offset_in_bytes());
2892
2893 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
2894 bool need_slow_path = (must_load_sco ||
2895 super_check_offset.constant_or_zero() == sco_offset);
2896
2897 assert_different_registers(sub_klass, super_klass, temp_reg);
2898 if (super_check_offset.is_register()) {
2899 assert_different_registers(sub_klass, super_klass, temp_reg,
2900 super_check_offset.as_register());
2901 } else if (must_load_sco) {
2902 assert(temp2_reg != noreg, "supply either a temp or a register offset");
2903 }
2904
2905 Label L_fallthrough;
2906 int label_nulls = 0;
2907 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2908 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2909 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
2910 assert(label_nulls <= 1 || instanceof_hack != noreg ||
2911 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
2912 "at most one NULL in the batch, usually");
2913
2914 // Support for the instanceof hack, which uses delay slots to
2915 // set a destination register to zero or one.
2916 bool do_bool_sets = (instanceof_hack != noreg);
2917 #define BOOL_SET(bool_value) \
2918 if (do_bool_sets && bool_value >= 0) \
2919 set(bool_value, instanceof_hack)
2920 #define DELAYED_BOOL_SET(bool_value) \
2921 if (do_bool_sets && bool_value >= 0) \
2922 delayed()->set(bool_value, instanceof_hack); \
2923 else delayed()->nop()
2924 // Hacked ba(), which may only be used just before L_fallthrough.
2925 #define FINAL_JUMP(label, bool_value) \
2926 if (&(label) == &L_fallthrough) { \
2927 BOOL_SET(bool_value); \
2928 } else { \
2929 ba((do_bool_sets && bool_value >= 0), label); \
2930 DELAYED_BOOL_SET(bool_value); \
2931 }
2932
2933 // If the pointers are equal, we are done (e.g., String[] elements).
2934 // This self-check enables sharing of secondary supertype arrays among
2935 // non-primary types such as array-of-interface. Otherwise, each such
2936 // type would need its own customized SSA.
2937 // We move this check to the front of the fast path because many
2938 // type checks are in fact trivially successful in this manner,
2939 // so we get a nicely predicted branch right at the start of the check.
2940 cmp(super_klass, sub_klass);
2941 brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success);
2942 DELAYED_BOOL_SET(1);
2943
2944 // Check the supertype display:
2945 if (must_load_sco) {
2946 // The super check offset is always positive...
2947 lduw(super_klass, sco_offset, temp2_reg);
2948 super_check_offset = RegisterOrConstant(temp2_reg);
2949 // super_check_offset is register.
2950 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
2951 }
2952 ld_ptr(sub_klass, super_check_offset, temp_reg);
2953 cmp(super_klass, temp_reg);
2954
2955 // This check has worked decisively for primary supers.
2956 // Secondary supers are sought in the super_cache ('super_cache_addr').
2957 // (Secondary supers are interfaces and very deeply nested subtypes.)
2958 // This works in the same check above because of a tricky aliasing
2959 // between the super_cache and the primary super display elements.
2960 // (The 'super_check_addr' can address either, as the case requires.)
2961 // Note that the cache is updated below if it does not help us find
2962 // what we need immediately.
2963 // So if it was a primary super, we can just fail immediately.
2964 // Otherwise, it's the slow path for us (no success at this point).
2965
2966 if (super_check_offset.is_register()) {
2967 brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success);
2968 delayed(); if (do_bool_sets) BOOL_SET(1);
2969 // if !do_bool_sets, sneak the next cmp into the delay slot:
2970 cmp(super_check_offset.as_register(), sc_offset);
2971
2972 if (L_failure == &L_fallthrough) {
2973 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_slow_path);
2974 delayed()->nop();
2975 BOOL_SET(0); // fallthrough on failure
2976 } else {
2977 brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure);
2978 DELAYED_BOOL_SET(0);
2979 FINAL_JUMP(*L_slow_path, -1); // -1 => vanilla delay slot
2980 }
2981 } else if (super_check_offset.as_constant() == sc_offset) {
2982 // Need a slow path; fast failure is impossible.
2983 if (L_slow_path == &L_fallthrough) {
2984 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success);
2985 DELAYED_BOOL_SET(1);
2986 } else {
2987 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
2988 delayed()->nop();
2989 FINAL_JUMP(*L_success, 1);
2990 }
2991 } else {
2992 // No slow path; it's a fast decision.
2993 if (L_failure == &L_fallthrough) {
2994 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success);
2995 DELAYED_BOOL_SET(1);
2996 BOOL_SET(0);
2997 } else {
2998 brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure);
2999 DELAYED_BOOL_SET(0);
3000 FINAL_JUMP(*L_success, 1);
3001 }
3002 }
3003
3004 bind(L_fallthrough);
3005
3006 #undef final_jump
3007 #undef bool_set
3008 #undef DELAYED_BOOL_SET
3009 #undef final_jump
3010 }
3011
3012
3013 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3014 Register super_klass,
3015 Register count_temp,
3016 Register scan_temp,
3017 Register scratch_reg,
3018 Register coop_reg,
3019 Label* L_success,
3020 Label* L_failure) {
3021 assert_different_registers(sub_klass, super_klass,
3022 count_temp, scan_temp, scratch_reg, coop_reg);
3023
3024 Label L_fallthrough, L_loop;
3025 int label_nulls = 0;
3026 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3027 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3028 assert(label_nulls <= 1, "at most one NULL in the batch");
3029
3030 // a couple of useful fields in sub_klass:
3031 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
3032 Klass::secondary_supers_offset_in_bytes());
3033 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
3034 Klass::secondary_super_cache_offset_in_bytes());
3035
3036 // Do a linear scan of the secondary super-klass chain.
3037 // This code is rarely used, so simplicity is a virtue here.
3038
3039 #ifndef PRODUCT
3040 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3041 inc_counter((address) pst_counter, count_temp, scan_temp);
3042 #endif
3043
3044 // We will consult the secondary-super array.
3045 ld_ptr(sub_klass, ss_offset, scan_temp);
3046
3047 // Compress superclass if necessary.
3048 Register search_key = super_klass;
3049 bool decode_super_klass = false;
3050 if (UseCompressedOops) {
3051 if (coop_reg != noreg) {
3052 encode_heap_oop_not_null(super_klass, coop_reg);
3053 search_key = coop_reg;
3054 } else {
3055 encode_heap_oop_not_null(super_klass);
3056 decode_super_klass = true; // scarce temps!
3057 }
3058 // The superclass is never null; it would be a basic system error if a null
3059 // pointer were to sneak in here. Note that we have already loaded the
3060 // Klass::super_check_offset from the super_klass in the fast path,
3061 // so if there is a null in that register, we are already in the afterlife.
3062 }
3063
3064 // Load the array length. (Positive movl does right thing on LP64.)
3065 lduw(scan_temp, arrayOopDesc::length_offset_in_bytes(), count_temp);
3066
3067 // Check for empty secondary super list
3068 tst(count_temp);
3069
3070 // Top of search loop
3071 bind(L_loop);
3072 br(Assembler::equal, false, Assembler::pn, *L_failure);
3073 delayed()->add(scan_temp, heapOopSize, scan_temp);
3074 assert(heapOopSize != 0, "heapOopSize should be initialized");
3075
3076 // Skip the array header in all array accesses.
3077 int elem_offset = arrayOopDesc::base_offset_in_bytes(T_OBJECT);
3078 elem_offset -= heapOopSize; // the scan pointer was pre-incremented also
3079
3080 // Load next super to check
3081 if (UseCompressedOops) {
3082 // Don't use load_heap_oop; we don't want to decode the element.
3083 lduw( scan_temp, elem_offset, scratch_reg );
3084 } else {
3085 ld_ptr( scan_temp, elem_offset, scratch_reg );
3086 }
3087
3088 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
3089 cmp(scratch_reg, search_key);
3090
3091 // A miss means we are NOT a subtype and need to keep looping
3092 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
3093 delayed()->deccc(count_temp); // decrement trip counter in delay slot
3094
3095 // Falling out the bottom means we found a hit; we ARE a subtype
3096 if (decode_super_klass) decode_heap_oop(super_klass);
3097
3098 // Success. Cache the super we found and proceed in triumph.
3099 st_ptr(super_klass, sub_klass, sc_offset);
3100
3101 if (L_success != &L_fallthrough) {
3102 ba(false, *L_success);
3103 delayed()->nop();
3104 }
3105
3106 bind(L_fallthrough);
3107 }
3108
3109
3110 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
3111 Register temp_reg,
3112 Label& wrong_method_type) {
3113 assert_different_registers(mtype_reg, mh_reg, temp_reg);
3114 // compare method type against that of the receiver
3115 RegisterOrConstant mhtype_offset = delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg);
3116 load_heap_oop(mh_reg, mhtype_offset, temp_reg);
3117 cmp(temp_reg, mtype_reg);
3118 br(Assembler::notEqual, false, Assembler::pn, wrong_method_type);
3119 delayed()->nop();
3120 }
3121
3122
3123 // A method handle has a "vmslots" field which gives the size of its
3124 // argument list in JVM stack slots. This field is either located directly
3125 // in every method handle, or else is indirectly accessed through the
3126 // method handle's MethodType. This macro hides the distinction.
3127 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
3128 Register temp_reg) {
3129 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
3130 // load mh.type.form.vmslots
3131 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) {
3132 // hoist vmslots into every mh to avoid dependent load chain
3133 ld( Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
3134 } else {
3135 Register temp2_reg = vmslots_reg;
3136 load_heap_oop(Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)), temp2_reg);
3137 load_heap_oop(Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)), temp2_reg);
3138 ld( Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)), vmslots_reg);
3139 }
3140 }
3141
3142
3143 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop) {
3144 assert(mh_reg == G3_method_handle, "caller must put MH object in G3");
3145 assert_different_registers(mh_reg, temp_reg);
3146
3147 // pick out the interpreted side of the handler
3148 // NOTE: vmentry is not an oop!
3149 ld_ptr(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg), temp_reg);
3150
3151 // off we go...
3152 ld_ptr(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes(), temp_reg);
3153 jmp(temp_reg, 0);
3154
3155 // for the various stubs which take control at this point,
3156 // see MethodHandles::generate_method_handle_stub
3157
3158 // Some callers can fill the delay slot.
3159 if (emit_delayed_nop) {
3160 delayed()->nop();
3161 }
3162 }
3163
3164
3165 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
3166 int extra_slot_offset) {
3167 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
3168 int stackElementSize = Interpreter::stackElementSize;
3169 int offset = extra_slot_offset * stackElementSize;
3170 if (arg_slot.is_constant()) {
3171 offset += arg_slot.as_constant() * stackElementSize;
3172 return offset;
3173 } else {
3174 Register temp = arg_slot.as_register();
3175 sll_ptr(temp, exact_log2(stackElementSize), temp);
3176 if (offset != 0)
3177 add(temp, offset, temp);
3178 return temp;
3179 }
3180 }
3181
3182
3183 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
3184 int extra_slot_offset) {
3185 return Address(Gargs, argument_offset(arg_slot, extra_slot_offset));
3186 }
3187
3188
3189 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
3190 Register temp_reg,
3191 Label& done, Label* slow_case,
3192 BiasedLockingCounters* counters) {
3193 assert(UseBiasedLocking, "why call this otherwise?");
3194
3195 if (PrintBiasedLockingStatistics) {
3196 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
3197 if (counters == NULL)
3198 counters = BiasedLocking::counters();
3199 }
3200
3201 Label cas_label;
3202
3203 // Biased locking
3204 // See whether the lock is currently biased toward our thread and
3205 // whether the epoch is still valid
3206 // Note that the runtime guarantees sufficient alignment of JavaThread
3207 // pointers to allow age to be placed into low bits
3208 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
3209 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3210 cmp(temp_reg, markOopDesc::biased_lock_pattern);
3211 brx(Assembler::notEqual, false, Assembler::pn, cas_label);
3212 delayed()->nop();
3213
3214 load_klass(obj_reg, temp_reg);
3215 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3216 or3(G2_thread, temp_reg, temp_reg);
3217 xor3(mark_reg, temp_reg, temp_reg);
3218 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
3219 if (counters != NULL) {
3220 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
3221 // Reload mark_reg as we may need it later
3222 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
3223 }
3224 brx(Assembler::equal, true, Assembler::pt, done);
3225 delayed()->nop();
3226
3227 Label try_revoke_bias;
3228 Label try_rebias;
3229 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3230 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3231
3232 // At this point we know that the header has the bias pattern and
3233 // that we are not the bias owner in the current epoch. We need to
3234 // figure out more details about the state of the header in order to
3235 // know what operations can be legally performed on the object's
3236 // header.
3237
3238 // If the low three bits in the xor result aren't clear, that means
3239 // the prototype header is no longer biased and we have to revoke
3240 // the bias on this object.
3241 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
3242 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
3243
3244 // Biasing is still enabled for this data type. See whether the
3245 // epoch of the current bias is still valid, meaning that the epoch
3246 // bits of the mark word are equal to the epoch bits of the
3247 // prototype header. (Note that the prototype header's epoch bits
3248 // only change at a safepoint.) If not, attempt to rebias the object
3249 // toward the current thread. Note that we must be absolutely sure
3250 // that the current epoch is invalid in order to do this because
3251 // otherwise the manipulations it performs on the mark word are
3252 // illegal.
3253 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
3254 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
3255
3256 // The epoch of the current bias is still valid but we know nothing
3257 // about the owner; it might be set or it might be clear. Try to
3258 // acquire the bias of the object using an atomic operation. If this
3259 // fails we will go in to the runtime to revoke the object's bias.
3260 // Note that we first construct the presumed unbiased header so we
3261 // don't accidentally blow away another thread's valid bias.
3262 delayed()->and3(mark_reg,
3263 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
3264 mark_reg);
3265 or3(G2_thread, mark_reg, temp_reg);
3266 casn(mark_addr.base(), mark_reg, temp_reg);
3267 // If the biasing toward our thread failed, this means that
3268 // another thread succeeded in biasing it toward itself and we
3269 // need to revoke that bias. The revocation will occur in the
3270 // interpreter runtime in the slow case.
3271 cmp(mark_reg, temp_reg);
3272 if (counters != NULL) {
3273 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
3274 }
3275 if (slow_case != NULL) {
3276 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3277 delayed()->nop();
3278 }
3279 br(Assembler::always, false, Assembler::pt, done);
3280 delayed()->nop();
3281
3282 bind(try_rebias);
3283 // At this point we know the epoch has expired, meaning that the
3284 // current "bias owner", if any, is actually invalid. Under these
3285 // circumstances _only_, we are allowed to use the current header's
3286 // value as the comparison value when doing the cas to acquire the
3287 // bias in the current epoch. In other words, we allow transfer of
3288 // the bias from one thread to another directly in this situation.
3289 //
3290 // FIXME: due to a lack of registers we currently blow away the age
3291 // bits in this situation. Should attempt to preserve them.
3292 load_klass(obj_reg, temp_reg);
3293 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3294 or3(G2_thread, temp_reg, temp_reg);
3295 casn(mark_addr.base(), mark_reg, temp_reg);
3296 // If the biasing toward our thread failed, this means that
3297 // another thread succeeded in biasing it toward itself and we
3298 // need to revoke that bias. The revocation will occur in the
3299 // interpreter runtime in the slow case.
3300 cmp(mark_reg, temp_reg);
3301 if (counters != NULL) {
3302 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
3303 }
3304 if (slow_case != NULL) {
3305 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3306 delayed()->nop();
3307 }
3308 br(Assembler::always, false, Assembler::pt, done);
3309 delayed()->nop();
3310
3311 bind(try_revoke_bias);
3312 // The prototype mark in the klass doesn't have the bias bit set any
3313 // more, indicating that objects of this data type are not supposed
3314 // to be biased any more. We are going to try to reset the mark of
3315 // this object to the prototype value and fall through to the
3316 // CAS-based locking scheme. Note that if our CAS fails, it means
3317 // that another thread raced us for the privilege of revoking the
3318 // bias of this particular object, so it's okay to continue in the
3319 // normal locking code.
3320 //
3321 // FIXME: due to a lack of registers we currently blow away the age
3322 // bits in this situation. Should attempt to preserve them.
3323 load_klass(obj_reg, temp_reg);
3324 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3325 casn(mark_addr.base(), mark_reg, temp_reg);
3326 // Fall through to the normal CAS-based lock, because no matter what
3327 // the result of the above CAS, some thread must have succeeded in
3328 // removing the bias bit from the object's header.
3329 if (counters != NULL) {
3330 cmp(mark_reg, temp_reg);
3331 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
3332 }
3333
3334 bind(cas_label);
3335 }
3336
3337 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
3338 bool allow_delay_slot_filling) {
3339 // Check for biased locking unlock case, which is a no-op
3340 // Note: we do not have to check the thread ID for two reasons.
3341 // First, the interpreter checks for IllegalMonitorStateException at
3342 // a higher level. Second, if the bias was revoked while we held the
3343 // lock, the object could not be rebiased toward another thread, so
3344 // the bias bit would be clear.
3345 ld_ptr(mark_addr, temp_reg);
3346 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3347 cmp(temp_reg, markOopDesc::biased_lock_pattern);
3348 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
3349 delayed();
3350 if (!allow_delay_slot_filling) {
3351 nop();
3352 }
3353 }
3354
3355
3356 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
3357 // Solaris/SPARC's "as". Another apt name would be cas_ptr()
3358
3359 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
3360 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ;
3361 }
3362
3363
3364
3365 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
3366 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
3367 // The code could be tightened up considerably.
3368 //
3369 // box->dhw disposition - post-conditions at DONE_LABEL.
3370 // - Successful inflated lock: box->dhw != 0.
3371 // Any non-zero value suffices.
3372 // Consider G2_thread, rsp, boxReg, or unused_mark()
3373 // - Successful Stack-lock: box->dhw == mark.
3374 // box->dhw must contain the displaced mark word value
3375 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
3376 // The slow-path fast_enter() and slow_enter() operators
3377 // are responsible for setting box->dhw = NonZero (typically ::unused_mark).
3378 // - Biased: box->dhw is undefined
3379 //
3380 // SPARC refworkload performance - specifically jetstream and scimark - are
3381 // extremely sensitive to the size of the code emitted by compiler_lock_object
3382 // and compiler_unlock_object. Critically, the key factor is code size, not path
3383 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
3384 // effect).
3385
3386
3387 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
3388 Register Rbox, Register Rscratch,
3389 BiasedLockingCounters* counters,
3390 bool try_bias) {
3391 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3392
3393 verify_oop(Roop);
3394 Label done ;
3395
3396 if (counters != NULL) {
3397 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
3398 }
3399
3400 if (EmitSync & 1) {
3401 mov (3, Rscratch) ;
3402 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3403 cmp (SP, G0) ;
3404 return ;
3405 }
3406
3407 if (EmitSync & 2) {
3408
3409 // Fetch object's markword
3410 ld_ptr(mark_addr, Rmark);
3411
3412 if (try_bias) {
3413 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3414 }
3415
3416 // Save Rbox in Rscratch to be used for the cas operation
3417 mov(Rbox, Rscratch);
3418
3419 // set Rmark to markOop | markOopDesc::unlocked_value
3420 or3(Rmark, markOopDesc::unlocked_value, Rmark);
3421
3422 // Initialize the box. (Must happen before we update the object mark!)
3423 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3424
3425 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
3426 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3427 casx_under_lock(mark_addr.base(), Rmark, Rscratch,
3428 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3429
3430 // if compare/exchange succeeded we found an unlocked object and we now have locked it
3431 // hence we are done
3432 cmp(Rmark, Rscratch);
3433 #ifdef _LP64
3434 sub(Rscratch, STACK_BIAS, Rscratch);
3435 #endif
3436 brx(Assembler::equal, false, Assembler::pt, done);
3437 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
3438
3439 // we did not find an unlocked object so see if this is a recursive case
3440 // sub(Rscratch, SP, Rscratch);
3441 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3442 andcc(Rscratch, 0xfffff003, Rscratch);
3443 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3444 bind (done) ;
3445 return ;
3446 }
3447
3448 Label Egress ;
3449
3450 if (EmitSync & 256) {
3451 Label IsInflated ;
3452
3453 ld_ptr (mark_addr, Rmark); // fetch obj->mark
3454 // Triage: biased, stack-locked, neutral, inflated
3455 if (try_bias) {
3456 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3457 // Invariant: if control reaches this point in the emitted stream
3458 // then Rmark has not been modified.
3459 }
3460
3461 // Store mark into displaced mark field in the on-stack basic-lock "box"
3462 // Critically, this must happen before the CAS
3463 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
3464 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3465 andcc (Rmark, 2, G0) ;
3466 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3467 delayed() ->
3468
3469 // Try stack-lock acquisition.
3470 // Beware: the 1st instruction is in a delay slot
3471 mov (Rbox, Rscratch);
3472 or3 (Rmark, markOopDesc::unlocked_value, Rmark);
3473 assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3474 casn (mark_addr.base(), Rmark, Rscratch) ;
3475 cmp (Rmark, Rscratch);
3476 brx (Assembler::equal, false, Assembler::pt, done);
3477 delayed()->sub(Rscratch, SP, Rscratch);
3478
3479 // Stack-lock attempt failed - check for recursive stack-lock.
3480 // See the comments below about how we might remove this case.
3481 #ifdef _LP64
3482 sub (Rscratch, STACK_BIAS, Rscratch);
3483 #endif
3484 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3485 andcc (Rscratch, 0xfffff003, Rscratch);
3486 br (Assembler::always, false, Assembler::pt, done) ;
3487 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3488
3489 bind (IsInflated) ;
3490 if (EmitSync & 64) {
3491 // If m->owner != null goto IsLocked
3492 // Pessimistic form: Test-and-CAS vs CAS
3493 // The optimistic form avoids RTS->RTO cache line upgrades.
3494 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3495 andcc (Rscratch, Rscratch, G0) ;
3496 brx (Assembler::notZero, false, Assembler::pn, done) ;
3497 delayed()->nop() ;
3498 // m->owner == null : it's unlocked.
3499 }
3500
3501 // Try to CAS m->owner from null to Self
3502 // Invariant: if we acquire the lock then _recursions should be 0.
3503 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3504 mov (G2_thread, Rscratch) ;
3505 casn (Rmark, G0, Rscratch) ;
3506 cmp (Rscratch, G0) ;
3507 // Intentional fall-through into done
3508 } else {
3509 // Aggressively avoid the Store-before-CAS penalty
3510 // Defer the store into box->dhw until after the CAS
3511 Label IsInflated, Recursive ;
3512
3513 // Anticipate CAS -- Avoid RTS->RTO upgrade
3514 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3515
3516 ld_ptr (mark_addr, Rmark); // fetch obj->mark
3517 // Triage: biased, stack-locked, neutral, inflated
3518
3519 if (try_bias) {
3520 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3521 // Invariant: if control reaches this point in the emitted stream
3522 // then Rmark has not been modified.
3523 }
3524 andcc (Rmark, 2, G0) ;
3525 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3526 delayed()-> // Beware - dangling delay-slot
3527
3528 // Try stack-lock acquisition.
3529 // Transiently install BUSY (0) encoding in the mark word.
3530 // if the CAS of 0 into the mark was successful then we execute:
3531 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
3532 // ST obj->mark = box -- overwrite transient 0 value
3533 // This presumes TSO, of course.
3534
3535 mov (0, Rscratch) ;
3536 or3 (Rmark, markOopDesc::unlocked_value, Rmark);
3537 assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3538 casn (mark_addr.base(), Rmark, Rscratch) ;
3539 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3540 cmp (Rscratch, Rmark) ;
3541 brx (Assembler::notZero, false, Assembler::pn, Recursive) ;
3542 delayed() ->
3543 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3544 if (counters != NULL) {
3545 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3546 }
3547 br (Assembler::always, false, Assembler::pt, done);
3548 delayed() ->
3549 st_ptr (Rbox, mark_addr) ;
3550
3551 bind (Recursive) ;
3552 // Stack-lock attempt failed - check for recursive stack-lock.
3553 // Tests show that we can remove the recursive case with no impact
3554 // on refworkload 0.83. If we need to reduce the size of the code
3555 // emitted by compiler_lock_object() the recursive case is perfect
3556 // candidate.
3557 //
3558 // A more extreme idea is to always inflate on stack-lock recursion.
3559 // This lets us eliminate the recursive checks in compiler_lock_object
3560 // and compiler_unlock_object and the (box->dhw == 0) encoding.
3561 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
3562 // and showed a performance *increase*. In the same experiment I eliminated
3563 // the fast-path stack-lock code from the interpreter and always passed
3564 // control to the "slow" operators in synchronizer.cpp.
3565
3566 // RScratch contains the fetched obj->mark value from the failed CASN.
3567 #ifdef _LP64
3568 sub (Rscratch, STACK_BIAS, Rscratch);
3569 #endif
3570 sub(Rscratch, SP, Rscratch);
3571 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3572 andcc (Rscratch, 0xfffff003, Rscratch);
3573 if (counters != NULL) {
3574 // Accounting needs the Rscratch register
3575 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3576 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3577 br (Assembler::always, false, Assembler::pt, done) ;
3578 delayed()->nop() ;
3579 } else {
3580 br (Assembler::always, false, Assembler::pt, done) ;
3581 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3582 }
3583
3584 bind (IsInflated) ;
3585 if (EmitSync & 64) {
3586 // If m->owner != null goto IsLocked
3587 // Test-and-CAS vs CAS
3588 // Pessimistic form avoids futile (doomed) CAS attempts
3589 // The optimistic form avoids RTS->RTO cache line upgrades.
3590 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3591 andcc (Rscratch, Rscratch, G0) ;
3592 brx (Assembler::notZero, false, Assembler::pn, done) ;
3593 delayed()->nop() ;
3594 // m->owner == null : it's unlocked.
3595 }
3596
3597 // Try to CAS m->owner from null to Self
3598 // Invariant: if we acquire the lock then _recursions should be 0.
3599 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3600 mov (G2_thread, Rscratch) ;
3601 casn (Rmark, G0, Rscratch) ;
3602 cmp (Rscratch, G0) ;
3603 // ST box->displaced_header = NonZero.
3604 // Any non-zero value suffices:
3605 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
3606 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
3607 // Intentional fall-through into done
3608 }
3609
3610 bind (done) ;
3611 }
3612
3613 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
3614 Register Rbox, Register Rscratch,
3615 bool try_bias) {
3616 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3617
3618 Label done ;
3619
3620 if (EmitSync & 4) {
3621 cmp (SP, G0) ;
3622 return ;
3623 }
3624
3625 if (EmitSync & 8) {
3626 if (try_bias) {
3627 biased_locking_exit(mark_addr, Rscratch, done);
3628 }
3629
3630 // Test first if it is a fast recursive unlock
3631 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
3632 cmp(Rmark, G0);
3633 brx(Assembler::equal, false, Assembler::pt, done);
3634 delayed()->nop();
3635
3636 // Check if it is still a light weight lock, this is is true if we see
3637 // the stack address of the basicLock in the markOop of the object
3638 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3639 casx_under_lock(mark_addr.base(), Rbox, Rmark,
3640 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3641 br (Assembler::always, false, Assembler::pt, done);
3642 delayed()->cmp(Rbox, Rmark);
3643 bind (done) ;
3644 return ;
3645 }
3646
3647 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
3648 // is too large performance rolls abruptly off a cliff.
3649 // This could be related to inlining policies, code cache management, or
3650 // I$ effects.
3651 Label LStacked ;
3652
3653 if (try_bias) {
3654 // TODO: eliminate redundant LDs of obj->mark
3655 biased_locking_exit(mark_addr, Rscratch, done);
3656 }
3657
3658 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ;
3659 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3660 andcc (Rscratch, Rscratch, G0);
3661 brx (Assembler::zero, false, Assembler::pn, done);
3662 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS
3663 andcc (Rmark, 2, G0) ;
3664 brx (Assembler::zero, false, Assembler::pt, LStacked) ;
3665 delayed()-> nop() ;
3666
3667 // It's inflated
3668 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3669 // the ST of 0 into _owner which releases the lock. This prevents loads
3670 // and stores within the critical section from reordering (floating)
3671 // past the store that releases the lock. But TSO is a strong memory model
3672 // and that particular flavor of barrier is a noop, so we can safely elide it.
3673 // Note that we use 1-0 locking by default for the inflated case. We
3674 // close the resultant (and rare) race by having contented threads in
3675 // monitorenter periodically poll _owner.
3676 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3677 ld_ptr (Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
3678 xor3 (Rscratch, G2_thread, Rscratch) ;
3679 orcc (Rbox, Rscratch, Rbox) ;
3680 brx (Assembler::notZero, false, Assembler::pn, done) ;
3681 delayed()->
3682 ld_ptr (Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
3683 ld_ptr (Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
3684 orcc (Rbox, Rscratch, G0) ;
3685 if (EmitSync & 65536) {
3686 Label LSucc ;
3687 brx (Assembler::notZero, false, Assembler::pn, LSucc) ;
3688 delayed()->nop() ;
3689 br (Assembler::always, false, Assembler::pt, done) ;
3690 delayed()->
3691 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3692
3693 bind (LSucc) ;
3694 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3695 if (os::is_MP()) { membar (StoreLoad) ; }
3696 ld_ptr (Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
3697 andcc (Rscratch, Rscratch, G0) ;
3698 brx (Assembler::notZero, false, Assembler::pt, done) ;
3699 delayed()-> andcc (G0, G0, G0) ;
3700 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3701 mov (G2_thread, Rscratch) ;
3702 casn (Rmark, G0, Rscratch) ;
3703 cmp (Rscratch, G0) ;
3704 // invert icc.zf and goto done
3705 brx (Assembler::notZero, false, Assembler::pt, done) ;
3706 delayed() -> cmp (G0, G0) ;
3707 br (Assembler::always, false, Assembler::pt, done);
3708 delayed() -> cmp (G0, 1) ;
3709 } else {
3710 brx (Assembler::notZero, false, Assembler::pn, done) ;
3711 delayed()->nop() ;
3712 br (Assembler::always, false, Assembler::pt, done) ;
3713 delayed()->
3714 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3715 }
3716
3717 bind (LStacked) ;
3718 // Consider: we could replace the expensive CAS in the exit
3719 // path with a simple ST of the displaced mark value fetched from
3720 // the on-stack basiclock box. That admits a race where a thread T2
3721 // in the slow lock path -- inflating with monitor M -- could race a
3722 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3723 // More precisely T1 in the stack-lock unlock path could "stomp" the
3724 // inflated mark value M installed by T2, resulting in an orphan
3725 // object monitor M and T2 becoming stranded. We can remedy that situation
3726 // by having T2 periodically poll the object's mark word using timed wait
3727 // operations. If T2 discovers that a stomp has occurred it vacates
3728 // the monitor M and wakes any other threads stranded on the now-orphan M.
3729 // In addition the monitor scavenger, which performs deflation,
3730 // would also need to check for orpan monitors and stranded threads.
3731 //
3732 // Finally, inflation is also used when T2 needs to assign a hashCode
3733 // to O and O is stack-locked by T1. The "stomp" race could cause
3734 // an assigned hashCode value to be lost. We can avoid that condition
3735 // and provide the necessary hashCode stability invariants by ensuring
3736 // that hashCode generation is idempotent between copying GCs.
3737 // For example we could compute the hashCode of an object O as
3738 // O's heap address XOR some high quality RNG value that is refreshed
3739 // at GC-time. The monitor scavenger would install the hashCode
3740 // found in any orphan monitors. Again, the mechanism admits a
3741 // lost-update "stomp" WAW race but detects and recovers as needed.
3742 //
3743 // A prototype implementation showed excellent results, although
3744 // the scavenger and timeout code was rather involved.
3745
3746 casn (mark_addr.base(), Rbox, Rscratch) ;
3747 cmp (Rbox, Rscratch);
3748 // Intentional fall through into done ...
3749
3750 bind (done) ;
3751 }
3752
3753
3754
3755 void MacroAssembler::print_CPU_state() {
3756 // %%%%% need to implement this
3757 }
3758
3759 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3760 // %%%%% need to implement this
3761 }
3762
3763 void MacroAssembler::push_IU_state() {
3764 // %%%%% need to implement this
3765 }
3766
3767
3768 void MacroAssembler::pop_IU_state() {
3769 // %%%%% need to implement this
3770 }
3771
3772
3773 void MacroAssembler::push_FPU_state() {
3774 // %%%%% need to implement this
3775 }
3776
3777
3778 void MacroAssembler::pop_FPU_state() {
3779 // %%%%% need to implement this
3780 }
3781
3782
3783 void MacroAssembler::push_CPU_state() {
3784 // %%%%% need to implement this
3785 }
3786
3787
3788 void MacroAssembler::pop_CPU_state() {
3789 // %%%%% need to implement this
3790 }
3791
3792
3793
3794 void MacroAssembler::verify_tlab() {
3795 #ifdef ASSERT
3796 if (UseTLAB && VerifyOops) {
3797 Label next, next2, ok;
3798 Register t1 = L0;
3799 Register t2 = L1;
3800 Register t3 = L2;
3801
3802 save_frame(0);
3803 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3804 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3805 or3(t1, t2, t3);
3806 cmp(t1, t2);
3807 br(Assembler::greaterEqual, false, Assembler::pn, next);
3808 delayed()->nop();
3809 stop("assert(top >= start)");
3810 should_not_reach_here();
3811
3812 bind(next);
3813 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3814 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3815 or3(t3, t2, t3);
3816 cmp(t1, t2);
3817 br(Assembler::lessEqual, false, Assembler::pn, next2);
3818 delayed()->nop();
3819 stop("assert(top <= end)");
3820 should_not_reach_here();
3821
3822 bind(next2);
3823 and3(t3, MinObjAlignmentInBytesMask, t3);
3824 cmp(t3, 0);
3825 br(Assembler::lessEqual, false, Assembler::pn, ok);
3826 delayed()->nop();
3827 stop("assert(aligned)");
3828 should_not_reach_here();
3829
3830 bind(ok);
3831 restore();
3832 }
3833 #endif
3834 }
3835
3836
3837 void MacroAssembler::eden_allocate(
3838 Register obj, // result: pointer to object after successful allocation
3839 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3840 int con_size_in_bytes, // object size in bytes if known at compile time
3841 Register t1, // temp register
3842 Register t2, // temp register
3843 Label& slow_case // continuation point if fast allocation fails
3844 ){
3845 // make sure arguments make sense
3846 assert_different_registers(obj, var_size_in_bytes, t1, t2);
3847 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3848 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3849
3850 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3851 // No allocation in the shared eden.
3852 br(Assembler::always, false, Assembler::pt, slow_case);
3853 delayed()->nop();
3854 } else {
3855 // get eden boundaries
3856 // note: we need both top & top_addr!
3857 const Register top_addr = t1;
3858 const Register end = t2;
3859
3860 CollectedHeap* ch = Universe::heap();
3861 set((intx)ch->top_addr(), top_addr);
3862 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3863 ld_ptr(top_addr, delta, end);
3864 ld_ptr(top_addr, 0, obj);
3865
3866 // try to allocate
3867 Label retry;
3868 bind(retry);
3869 #ifdef ASSERT
3870 // make sure eden top is properly aligned
3871 {
3872 Label L;
3873 btst(MinObjAlignmentInBytesMask, obj);
3874 br(Assembler::zero, false, Assembler::pt, L);
3875 delayed()->nop();
3876 stop("eden top is not properly aligned");
3877 bind(L);
3878 }
3879 #endif // ASSERT
3880 const Register free = end;
3881 sub(end, obj, free); // compute amount of free space
3882 if (var_size_in_bytes->is_valid()) {
3883 // size is unknown at compile time
3884 cmp(free, var_size_in_bytes);
3885 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3886 delayed()->add(obj, var_size_in_bytes, end);
3887 } else {
3888 // size is known at compile time
3889 cmp(free, con_size_in_bytes);
3890 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3891 delayed()->add(obj, con_size_in_bytes, end);
3892 }
3893 // Compare obj with the value at top_addr; if still equal, swap the value of
3894 // end with the value at top_addr. If not equal, read the value at top_addr
3895 // into end.
3896 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3897 // if someone beat us on the allocation, try again, otherwise continue
3898 cmp(obj, end);
3899 brx(Assembler::notEqual, false, Assembler::pn, retry);
3900 delayed()->mov(end, obj); // nop if successfull since obj == end
3901
3902 #ifdef ASSERT
3903 // make sure eden top is properly aligned
3904 {
3905 Label L;
3906 const Register top_addr = t1;
3907
3908 set((intx)ch->top_addr(), top_addr);
3909 ld_ptr(top_addr, 0, top_addr);
3910 btst(MinObjAlignmentInBytesMask, top_addr);
3911 br(Assembler::zero, false, Assembler::pt, L);
3912 delayed()->nop();
3913 stop("eden top is not properly aligned");
3914 bind(L);
3915 }
3916 #endif // ASSERT
3917 }
3918 }
3919
3920
3921 void MacroAssembler::tlab_allocate(
3922 Register obj, // result: pointer to object after successful allocation
3923 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3924 int con_size_in_bytes, // object size in bytes if known at compile time
3925 Register t1, // temp register
3926 Label& slow_case // continuation point if fast allocation fails
3927 ){
3928 // make sure arguments make sense
3929 assert_different_registers(obj, var_size_in_bytes, t1);
3930 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
3931 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3932
3933 const Register free = t1;
3934
3935 verify_tlab();
3936
3937 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
3938
3939 // calculate amount of free space
3940 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
3941 sub(free, obj, free);
3942
3943 Label done;
3944 if (var_size_in_bytes == noreg) {
3945 cmp(free, con_size_in_bytes);
3946 } else {
3947 cmp(free, var_size_in_bytes);
3948 }
3949 br(Assembler::less, false, Assembler::pn, slow_case);
3950 // calculate the new top pointer
3951 if (var_size_in_bytes == noreg) {
3952 delayed()->add(obj, con_size_in_bytes, free);
3953 } else {
3954 delayed()->add(obj, var_size_in_bytes, free);
3955 }
3956
3957 bind(done);
3958
3959 #ifdef ASSERT
3960 // make sure new free pointer is properly aligned
3961 {
3962 Label L;
3963 btst(MinObjAlignmentInBytesMask, free);
3964 br(Assembler::zero, false, Assembler::pt, L);
3965 delayed()->nop();
3966 stop("updated TLAB free is not properly aligned");
3967 bind(L);
3968 }
3969 #endif // ASSERT
3970
3971 // update the tlab top pointer
3972 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3973 verify_tlab();
3974 }
3975
3976
3977 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
3978 Register top = O0;
3979 Register t1 = G1;
3980 Register t2 = G3;
3981 Register t3 = O1;
3982 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
3983 Label do_refill, discard_tlab;
3984
3985 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3986 // No allocation in the shared eden.
3987 br(Assembler::always, false, Assembler::pt, slow_case);
3988 delayed()->nop();
3989 }
3990
3991 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
3992 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
3993 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
3994
3995 // calculate amount of free space
3996 sub(t1, top, t1);
3997 srl_ptr(t1, LogHeapWordSize, t1);
3998
3999 // Retain tlab and allocate object in shared space if
4000 // the amount free in the tlab is too large to discard.
4001 cmp(t1, t2);
4002 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
4003
4004 // increment waste limit to prevent getting stuck on this slow path
4005 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
4006 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
4007 if (TLABStats) {
4008 // increment number of slow_allocations
4009 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
4010 add(t2, 1, t2);
4011 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
4012 }
4013 br(Assembler::always, false, Assembler::pt, try_eden);
4014 delayed()->nop();
4015
4016 bind(discard_tlab);
4017 if (TLABStats) {
4018 // increment number of refills
4019 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
4020 add(t2, 1, t2);
4021 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
4022 // accumulate wastage
4023 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
4024 add(t2, t1, t2);
4025 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
4026 }
4027
4028 // if tlab is currently allocated (top or end != null) then
4029 // fill [top, end + alignment_reserve) with array object
4030 br_null(top, false, Assembler::pn, do_refill);
4031 delayed()->nop();
4032
4033 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
4034 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
4035 // set klass to intArrayKlass
4036 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
4037 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
4038 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
4039 st(t1, top, arrayOopDesc::length_offset_in_bytes());
4040 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
4041 ld_ptr(t2, 0, t2);
4042 // store klass last. concurrent gcs assumes klass length is valid if
4043 // klass field is not null.
4044 store_klass(t2, top);
4045 verify_oop(top);
4046
4047 // refill the tlab with an eden allocation
4048 bind(do_refill);
4049 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
4050 sll_ptr(t1, LogHeapWordSize, t1);
4051 // add object_size ??
4052 eden_allocate(top, t1, 0, t2, t3, slow_case);
4053
4054 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
4055 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
4056 #ifdef ASSERT
4057 // check that tlab_size (t1) is still valid
4058 {
4059 Label ok;
4060 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
4061 sll_ptr(t2, LogHeapWordSize, t2);
4062 cmp(t1, t2);
4063 br(Assembler::equal, false, Assembler::pt, ok);
4064 delayed()->nop();
4065 stop("assert(t1 == tlab_size)");
4066 should_not_reach_here();
4067
4068 bind(ok);
4069 }
4070 #endif // ASSERT
4071 add(top, t1, top); // t1 is tlab_size
4072 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
4073 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
4074 verify_tlab();
4075 br(Assembler::always, false, Assembler::pt, retry);
4076 delayed()->nop();
4077 }
4078
4079 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
4080 switch (cond) {
4081 // Note some conditions are synonyms for others
4082 case Assembler::never: return Assembler::always;
4083 case Assembler::zero: return Assembler::notZero;
4084 case Assembler::lessEqual: return Assembler::greater;
4085 case Assembler::less: return Assembler::greaterEqual;
4086 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
4087 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
4088 case Assembler::negative: return Assembler::positive;
4089 case Assembler::overflowSet: return Assembler::overflowClear;
4090 case Assembler::always: return Assembler::never;
4091 case Assembler::notZero: return Assembler::zero;
4092 case Assembler::greater: return Assembler::lessEqual;
4093 case Assembler::greaterEqual: return Assembler::less;
4094 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
4095 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
4096 case Assembler::positive: return Assembler::negative;
4097 case Assembler::overflowClear: return Assembler::overflowSet;
4098 }
4099
4100 ShouldNotReachHere(); return Assembler::overflowClear;
4101 }
4102
4103 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
4104 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
4105 Condition negated_cond = negate_condition(cond);
4106 Label L;
4107 brx(negated_cond, false, Assembler::pt, L);
4108 delayed()->nop();
4109 inc_counter(counter_ptr, Rtmp1, Rtmp2);
4110 bind(L);
4111 }
4112
4113 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
4114 AddressLiteral addrlit(counter_addr);
4115 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
4116 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
4117 ld(addr, Rtmp2);
4118 inc(Rtmp2);
4119 st(Rtmp2, addr);
4120 }
4121
4122 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
4123 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
4124 }
4125
4126 SkipIfEqual::SkipIfEqual(
4127 MacroAssembler* masm, Register temp, const bool* flag_addr,
4128 Assembler::Condition condition) {
4129 _masm = masm;
4130 AddressLiteral flag(flag_addr);
4131 _masm->sethi(flag, temp);
4132 _masm->ldub(temp, flag.low10(), temp);
4133 _masm->tst(temp);
4134 _masm->br(condition, false, Assembler::pt, _label);
4135 _masm->delayed()->nop();
4136 }
4137
4138 SkipIfEqual::~SkipIfEqual() {
4139 _masm->bind(_label);
4140 }
4141
4142
4143 // Writes to stack successive pages until offset reached to check for
4144 // stack overflow + shadow pages. This clobbers tsp and scratch.
4145 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
4146 Register Rscratch) {
4147 // Use stack pointer in temp stack pointer
4148 mov(SP, Rtsp);
4149
4150 // Bang stack for total size given plus stack shadow page size.
4151 // Bang one page at a time because a large size can overflow yellow and
4152 // red zones (the bang will fail but stack overflow handling can't tell that
4153 // it was a stack overflow bang vs a regular segv).
4154 int offset = os::vm_page_size();
4155 Register Roffset = Rscratch;
4156
4157 Label loop;
4158 bind(loop);
4159 set((-offset)+STACK_BIAS, Rscratch);
4160 st(G0, Rtsp, Rscratch);
4161 set(offset, Roffset);
4162 sub(Rsize, Roffset, Rsize);
4163 cmp(Rsize, G0);
4164 br(Assembler::greater, false, Assembler::pn, loop);
4165 delayed()->sub(Rtsp, Roffset, Rtsp);
4166
4167 // Bang down shadow pages too.
4168 // The -1 because we already subtracted 1 page.
4169 for (int i = 0; i< StackShadowPages-1; i++) {
4170 set((-i*offset)+STACK_BIAS, Rscratch);
4171 st(G0, Rtsp, Rscratch);
4172 }
4173 }
4174
4175 ///////////////////////////////////////////////////////////////////////////////////
4176 #ifndef SERIALGC
4177
4178 static uint num_stores = 0;
4179 static uint num_null_pre_stores = 0;
4180
4181 static void count_null_pre_vals(void* pre_val) {
4182 num_stores++;
4183 if (pre_val == NULL) num_null_pre_stores++;
4184 if ((num_stores % 1000000) == 0) {
4185 tty->print_cr(UINT32_FORMAT " stores, " UINT32_FORMAT " (%5.2f%%) with null pre-vals.",
4186 num_stores, num_null_pre_stores,
4187 100.0*(float)num_null_pre_stores/(float)num_stores);
4188 }
4189 }
4190
4191 static address satb_log_enqueue_with_frame = 0;
4192 static u_char* satb_log_enqueue_with_frame_end = 0;
4193
4194 static address satb_log_enqueue_frameless = 0;
4195 static u_char* satb_log_enqueue_frameless_end = 0;
4196
4197 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
4198
4199 // The calls to this don't work. We'd need to do a fair amount of work to
4200 // make it work.
4201 static void check_index(int ind) {
4202 assert(0 <= ind && ind <= 64*K && ((ind % oopSize) == 0),
4203 "Invariants.");
4204 }
4205
4206 static void generate_satb_log_enqueue(bool with_frame) {
4207 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
4208 CodeBuffer buf(bb);
4209 MacroAssembler masm(&buf);
4210 address start = masm.pc();
4211 Register pre_val;
4212
4213 Label refill, restart;
4214 if (with_frame) {
4215 masm.save_frame(0);
4216 pre_val = I0; // Was O0 before the save.
4217 } else {
4218 pre_val = O0;
4219 }
4220 int satb_q_index_byte_offset =
4221 in_bytes(JavaThread::satb_mark_queue_offset() +
4222 PtrQueue::byte_offset_of_index());
4223 int satb_q_buf_byte_offset =
4224 in_bytes(JavaThread::satb_mark_queue_offset() +
4225 PtrQueue::byte_offset_of_buf());
4226 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
4227 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
4228 "check sizes in assembly below");
4229
4230 masm.bind(restart);
4231 masm.ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
4232
4233 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill);
4234 // If the branch is taken, no harm in executing this in the delay slot.
4235 masm.delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
4236 masm.sub(L0, oopSize, L0);
4237
4238 masm.st_ptr(pre_val, L1, L0); // [_buf + index] := I0
4239 if (!with_frame) {
4240 // Use return-from-leaf
4241 masm.retl();
4242 masm.delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4243 } else {
4244 // Not delayed.
4245 masm.st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4246 }
4247 if (with_frame) {
4248 masm.ret();
4249 masm.delayed()->restore();
4250 }
4251 masm.bind(refill);
4252
4253 address handle_zero =
4254 CAST_FROM_FN_PTR(address,
4255 &SATBMarkQueueSet::handle_zero_index_for_thread);
4256 // This should be rare enough that we can afford to save all the
4257 // scratch registers that the calling context might be using.
4258 masm.mov(G1_scratch, L0);
4259 masm.mov(G3_scratch, L1);
4260 masm.mov(G4, L2);
4261 // We need the value of O0 above (for the write into the buffer), so we
4262 // save and restore it.
4263 masm.mov(O0, L3);
4264 // Since the call will overwrite O7, we save and restore that, as well.
4265 masm.mov(O7, L4);
4266 masm.call_VM_leaf(L5, handle_zero, G2_thread);
4267 masm.mov(L0, G1_scratch);
4268 masm.mov(L1, G3_scratch);
4269 masm.mov(L2, G4);
4270 masm.mov(L3, O0);
4271 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4272 masm.delayed()->mov(L4, O7);
4273
4274 if (with_frame) {
4275 satb_log_enqueue_with_frame = start;
4276 satb_log_enqueue_with_frame_end = masm.pc();
4277 } else {
4278 satb_log_enqueue_frameless = start;
4279 satb_log_enqueue_frameless_end = masm.pc();
4280 }
4281 }
4282
4283 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
4284 if (with_frame) {
4285 if (satb_log_enqueue_with_frame == 0) {
4286 generate_satb_log_enqueue(with_frame);
4287 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
4288 if (G1SATBPrintStubs) {
4289 tty->print_cr("Generated with-frame satb enqueue:");
4290 Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
4291 satb_log_enqueue_with_frame_end,
4292 tty);
4293 }
4294 }
4295 } else {
4296 if (satb_log_enqueue_frameless == 0) {
4297 generate_satb_log_enqueue(with_frame);
4298 assert(satb_log_enqueue_frameless != 0, "postcondition.");
4299 if (G1SATBPrintStubs) {
4300 tty->print_cr("Generated frameless satb enqueue:");
4301 Disassembler::decode((u_char*)satb_log_enqueue_frameless,
4302 satb_log_enqueue_frameless_end,
4303 tty);
4304 }
4305 }
4306 }
4307 }
4308
4309 void MacroAssembler::g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs) {
4310 assert(offset == 0 || index == noreg, "choose one");
4311
4312 if (G1DisablePreBarrier) return;
4313 // satb_log_barrier(tmp, obj, offset, preserve_o_regs);
4314 Label filtered;
4315 // satb_log_barrier_work0(tmp, filtered);
4316 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4317 ld(G2,
4318 in_bytes(JavaThread::satb_mark_queue_offset() +
4319 PtrQueue::byte_offset_of_active()),
4320 tmp);
4321 } else {
4322 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
4323 "Assumption");
4324 ldsb(G2,
4325 in_bytes(JavaThread::satb_mark_queue_offset() +
4326 PtrQueue::byte_offset_of_active()),
4327 tmp);
4328 }
4329
4330 // Check on whether to annul.
4331 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4332 delayed() -> nop();
4333
4334 // satb_log_barrier_work1(tmp, offset);
4335 if (index == noreg) {
4336 if (Assembler::is_simm13(offset)) {
4337 load_heap_oop(obj, offset, tmp);
4338 } else {
4339 set(offset, tmp);
4340 load_heap_oop(obj, tmp, tmp);
4341 }
4342 } else {
4343 load_heap_oop(obj, index, tmp);
4344 }
4345
4346 // satb_log_barrier_work2(obj, tmp, offset);
4347
4348 // satb_log_barrier_work3(tmp, filtered, preserve_o_regs);
4349
4350 const Register pre_val = tmp;
4351
4352 if (G1SATBBarrierPrintNullPreVals) {
4353 save_frame(0);
4354 mov(pre_val, O0);
4355 // Save G-regs that target may use.
4356 mov(G1, L1);
4357 mov(G2, L2);
4358 mov(G3, L3);
4359 mov(G4, L4);
4360 mov(G5, L5);
4361 call(CAST_FROM_FN_PTR(address, &count_null_pre_vals));
4362 delayed()->nop();
4363 // Restore G-regs that target may have used.
4364 mov(L1, G1);
4365 mov(L2, G2);
4366 mov(L3, G3);
4367 mov(L4, G4);
4368 mov(L5, G5);
4369 restore(G0, G0, G0);
4370 }
4371
4372 // Check on whether to annul.
4373 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered);
4374 delayed() -> nop();
4375
4376 // OK, it's not filtered, so we'll need to call enqueue. In the normal
4377 // case, pre_val will be a scratch G-reg, but there's some cases in which
4378 // it's an O-reg. In the first case, do a normal call. In the latter,
4379 // do a save here and call the frameless version.
4380
4381 guarantee(pre_val->is_global() || pre_val->is_out(),
4382 "Or we need to think harder.");
4383 if (pre_val->is_global() && !preserve_o_regs) {
4384 generate_satb_log_enqueue_if_necessary(true); // with frame.
4385 call(satb_log_enqueue_with_frame);
4386 delayed()->mov(pre_val, O0);
4387 } else {
4388 generate_satb_log_enqueue_if_necessary(false); // with frameless.
4389 save_frame(0);
4390 call(satb_log_enqueue_frameless);
4391 delayed()->mov(pre_val->after_save(), O0);
4392 restore();
4393 }
4394
4395 bind(filtered);
4396 }
4397
4398 static jint num_ct_writes = 0;
4399 static jint num_ct_writes_filtered_in_hr = 0;
4400 static jint num_ct_writes_filtered_null = 0;
4401 static G1CollectedHeap* g1 = NULL;
4402
4403 static Thread* count_ct_writes(void* filter_val, void* new_val) {
4404 Atomic::inc(&num_ct_writes);
4405 if (filter_val == NULL) {
4406 Atomic::inc(&num_ct_writes_filtered_in_hr);
4407 } else if (new_val == NULL) {
4408 Atomic::inc(&num_ct_writes_filtered_null);
4409 } else {
4410 if (g1 == NULL) {
4411 g1 = G1CollectedHeap::heap();
4412 }
4413 }
4414 if ((num_ct_writes % 1000000) == 0) {
4415 jint num_ct_writes_filtered =
4416 num_ct_writes_filtered_in_hr +
4417 num_ct_writes_filtered_null;
4418
4419 tty->print_cr("%d potential CT writes: %5.2f%% filtered\n"
4420 " (%5.2f%% intra-HR, %5.2f%% null).",
4421 num_ct_writes,
4422 100.0*(float)num_ct_writes_filtered/(float)num_ct_writes,
4423 100.0*(float)num_ct_writes_filtered_in_hr/
4424 (float)num_ct_writes,
4425 100.0*(float)num_ct_writes_filtered_null/
4426 (float)num_ct_writes);
4427 }
4428 return Thread::current();
4429 }
4430
4431 static address dirty_card_log_enqueue = 0;
4432 static u_char* dirty_card_log_enqueue_end = 0;
4433
4434 // This gets to assume that o0 contains the object address.
4435 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
4436 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
4437 CodeBuffer buf(bb);
4438 MacroAssembler masm(&buf);
4439 address start = masm.pc();
4440
4441 Label not_already_dirty, restart, refill;
4442
4443 #ifdef _LP64
4444 masm.srlx(O0, CardTableModRefBS::card_shift, O0);
4445 #else
4446 masm.srl(O0, CardTableModRefBS::card_shift, O0);
4447 #endif
4448 AddressLiteral addrlit(byte_map_base);
4449 masm.set(addrlit, O1); // O1 := <card table base>
4450 masm.ldub(O0, O1, O2); // O2 := [O0 + O1]
4451
4452 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt,
4453 O2, not_already_dirty);
4454 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch
4455 // case, harmless if not.
4456 masm.delayed()->add(O0, O1, O3);
4457
4458 // We didn't take the branch, so we're already dirty: return.
4459 // Use return-from-leaf
4460 masm.retl();
4461 masm.delayed()->nop();
4462
4463 // Not dirty.
4464 masm.bind(not_already_dirty);
4465 // First, dirty it.
4466 masm.stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
4467 int dirty_card_q_index_byte_offset =
4468 in_bytes(JavaThread::dirty_card_queue_offset() +
4469 PtrQueue::byte_offset_of_index());
4470 int dirty_card_q_buf_byte_offset =
4471 in_bytes(JavaThread::dirty_card_queue_offset() +
4472 PtrQueue::byte_offset_of_buf());
4473 masm.bind(restart);
4474 masm.ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
4475
4476 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn,
4477 L0, refill);
4478 // If the branch is taken, no harm in executing this in the delay slot.
4479 masm.delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
4480 masm.sub(L0, oopSize, L0);
4481
4482 masm.st_ptr(O3, L1, L0); // [_buf + index] := I0
4483 // Use return-from-leaf
4484 masm.retl();
4485 masm.delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
4486
4487 masm.bind(refill);
4488 address handle_zero =
4489 CAST_FROM_FN_PTR(address,
4490 &DirtyCardQueueSet::handle_zero_index_for_thread);
4491 // This should be rare enough that we can afford to save all the
4492 // scratch registers that the calling context might be using.
4493 masm.mov(G1_scratch, L3);
4494 masm.mov(G3_scratch, L5);
4495 // We need the value of O3 above (for the write into the buffer), so we
4496 // save and restore it.
4497 masm.mov(O3, L6);
4498 // Since the call will overwrite O7, we save and restore that, as well.
4499 masm.mov(O7, L4);
4500
4501 masm.call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
4502 masm.mov(L3, G1_scratch);
4503 masm.mov(L5, G3_scratch);
4504 masm.mov(L6, O3);
4505 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4506 masm.delayed()->mov(L4, O7);
4507
4508 dirty_card_log_enqueue = start;
4509 dirty_card_log_enqueue_end = masm.pc();
4510 // XXX Should have a guarantee here about not going off the end!
4511 // Does it already do so? Do an experiment...
4512 }
4513
4514 static inline void
4515 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
4516 if (dirty_card_log_enqueue == 0) {
4517 generate_dirty_card_log_enqueue(byte_map_base);
4518 assert(dirty_card_log_enqueue != 0, "postcondition.");
4519 if (G1SATBPrintStubs) {
4520 tty->print_cr("Generated dirty_card enqueue:");
4521 Disassembler::decode((u_char*)dirty_card_log_enqueue,
4522 dirty_card_log_enqueue_end,
4523 tty);
4524 }
4525 }
4526 }
4527
4528
4529 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4530
4531 Label filtered;
4532 MacroAssembler* post_filter_masm = this;
4533
4534 if (new_val == G0) return;
4535 if (G1DisablePostBarrier) return;
4536
4537 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
4538 assert(bs->kind() == BarrierSet::G1SATBCT ||
4539 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
4540 if (G1RSBarrierRegionFilter) {
4541 xor3(store_addr, new_val, tmp);
4542 #ifdef _LP64
4543 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4544 #else
4545 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4546 #endif
4547 if (G1PrintCTFilterStats) {
4548 guarantee(tmp->is_global(), "Or stats won't work...");
4549 // This is a sleazy hack: I'm temporarily hijacking G2, which I
4550 // promise to restore.
4551 mov(new_val, G2);
4552 save_frame(0);
4553 mov(tmp, O0);
4554 mov(G2, O1);
4555 // Save G-regs that target may use.
4556 mov(G1, L1);
4557 mov(G2, L2);
4558 mov(G3, L3);
4559 mov(G4, L4);
4560 mov(G5, L5);
4561 call(CAST_FROM_FN_PTR(address, &count_ct_writes));
4562 delayed()->nop();
4563 mov(O0, G2);
4564 // Restore G-regs that target may have used.
4565 mov(L1, G1);
4566 mov(L3, G3);
4567 mov(L4, G4);
4568 mov(L5, G5);
4569 restore(G0, G0, G0);
4570 }
4571 // XXX Should I predict this taken or not? Does it mattern?
4572 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4573 delayed()->nop();
4574 }
4575
4576 // If the "store_addr" register is an "in" or "local" register, move it to
4577 // a scratch reg so we can pass it as an argument.
4578 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
4579 // Pick a scratch register different from "tmp".
4580 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
4581 // Make sure we use up the delay slot!
4582 if (use_scr) {
4583 post_filter_masm->mov(store_addr, scr);
4584 } else {
4585 post_filter_masm->nop();
4586 }
4587 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
4588 save_frame(0);
4589 call(dirty_card_log_enqueue);
4590 if (use_scr) {
4591 delayed()->mov(scr, O0);
4592 } else {
4593 delayed()->mov(store_addr->after_save(), O0);
4594 }
4595 restore();
4596
4597 bind(filtered);
4598
4599 }
4600
4601 #endif // SERIALGC
4602 ///////////////////////////////////////////////////////////////////////////////////
4603
4604 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4605 // If we're writing constant NULL, we can skip the write barrier.
4606 if (new_val == G0) return;
4607 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
4608 assert(bs->kind() == BarrierSet::CardTableModRef ||
4609 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
4610 card_table_write(bs->byte_map_base, tmp, store_addr);
4611 }
4612
4613 void MacroAssembler::load_klass(Register src_oop, Register klass) {
4614 // The number of bytes in this code is used by
4615 // MachCallDynamicJavaNode::ret_addr_offset()
4616 // if this changes, change that.
4617 if (UseCompressedOops) {
4618 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4619 decode_heap_oop_not_null(klass);
4620 } else {
4621 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4622 }
4623 }
4624
4625 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
4626 if (UseCompressedOops) {
4627 assert(dst_oop != klass, "not enough registers");
4628 encode_heap_oop_not_null(klass);
4629 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4630 } else {
4631 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4632 }
4633 }
4634
4635 void MacroAssembler::store_klass_gap(Register s, Register d) {
4636 if (UseCompressedOops) {
4637 assert(s != d, "not enough registers");
4638 st(s, d, oopDesc::klass_gap_offset_in_bytes());
4639 }
4640 }
4641
4642 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
4643 if (UseCompressedOops) {
4644 lduw(s, d);
4645 decode_heap_oop(d);
4646 } else {
4647 ld_ptr(s, d);
4648 }
4649 }
4650
4651 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
4652 if (UseCompressedOops) {
4653 lduw(s1, s2, d);
4654 decode_heap_oop(d, d);
4655 } else {
4656 ld_ptr(s1, s2, d);
4657 }
4658 }
4659
4660 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
4661 if (UseCompressedOops) {
4662 lduw(s1, simm13a, d);
4663 decode_heap_oop(d, d);
4664 } else {
4665 ld_ptr(s1, simm13a, d);
4666 }
4667 }
4668
4669 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
4670 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d);
4671 else load_heap_oop(s1, s2.as_register(), d);
4672 }
4673
4674 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
4675 if (UseCompressedOops) {
4676 assert(s1 != d && s2 != d, "not enough registers");
4677 encode_heap_oop(d);
4678 st(d, s1, s2);
4679 } else {
4680 st_ptr(d, s1, s2);
4681 }
4682 }
4683
4684 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
4685 if (UseCompressedOops) {
4686 assert(s1 != d, "not enough registers");
4687 encode_heap_oop(d);
4688 st(d, s1, simm13a);
4689 } else {
4690 st_ptr(d, s1, simm13a);
4691 }
4692 }
4693
4694 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
4695 if (UseCompressedOops) {
4696 assert(a.base() != d, "not enough registers");
4697 encode_heap_oop(d);
4698 st(d, a, offset);
4699 } else {
4700 st_ptr(d, a, offset);
4701 }
4702 }
4703
4704
4705 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
4706 assert (UseCompressedOops, "must be compressed");
4707 assert (Universe::heap() != NULL, "java heap should be initialized");
4708 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4709 verify_oop(src);
4710 if (Universe::narrow_oop_base() == NULL) {
4711 srlx(src, LogMinObjAlignmentInBytes, dst);
4712 return;
4713 }
4714 Label done;
4715 if (src == dst) {
4716 // optimize for frequent case src == dst
4717 bpr(rc_nz, true, Assembler::pt, src, done);
4718 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
4719 bind(done);
4720 srlx(src, LogMinObjAlignmentInBytes, dst);
4721 } else {
4722 bpr(rc_z, false, Assembler::pn, src, done);
4723 delayed() -> mov(G0, dst);
4724 // could be moved before branch, and annulate delay,
4725 // but may add some unneeded work decoding null
4726 sub(src, G6_heapbase, dst);
4727 srlx(dst, LogMinObjAlignmentInBytes, dst);
4728 bind(done);
4729 }
4730 }
4731
4732
4733 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4734 assert (UseCompressedOops, "must be compressed");
4735 assert (Universe::heap() != NULL, "java heap should be initialized");
4736 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4737 verify_oop(r);
4738 if (Universe::narrow_oop_base() != NULL)
4739 sub(r, G6_heapbase, r);
4740 srlx(r, LogMinObjAlignmentInBytes, r);
4741 }
4742
4743 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
4744 assert (UseCompressedOops, "must be compressed");
4745 assert (Universe::heap() != NULL, "java heap should be initialized");
4746 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4747 verify_oop(src);
4748 if (Universe::narrow_oop_base() == NULL) {
4749 srlx(src, LogMinObjAlignmentInBytes, dst);
4750 } else {
4751 sub(src, G6_heapbase, dst);
4752 srlx(dst, LogMinObjAlignmentInBytes, dst);
4753 }
4754 }
4755
4756 // Same algorithm as oops.inline.hpp decode_heap_oop.
4757 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
4758 assert (UseCompressedOops, "must be compressed");
4759 assert (Universe::heap() != NULL, "java heap should be initialized");
4760 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4761 sllx(src, LogMinObjAlignmentInBytes, dst);
4762 if (Universe::narrow_oop_base() != NULL) {
4763 Label done;
4764 bpr(rc_nz, true, Assembler::pt, dst, done);
4765 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
4766 bind(done);
4767 }
4768 verify_oop(dst);
4769 }
4770
4771 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4772 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4773 // pd_code_size_limit.
4774 // Also do not verify_oop as this is called by verify_oop.
4775 assert (UseCompressedOops, "must be compressed");
4776 assert (Universe::heap() != NULL, "java heap should be initialized");
4777 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4778 sllx(r, LogMinObjAlignmentInBytes, r);
4779 if (Universe::narrow_oop_base() != NULL)
4780 add(r, G6_heapbase, r);
4781 }
4782
4783 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
4784 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4785 // pd_code_size_limit.
4786 // Also do not verify_oop as this is called by verify_oop.
4787 assert (UseCompressedOops, "must be compressed");
4788 assert (Universe::heap() != NULL, "java heap should be initialized");
4789 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4790 sllx(src, LogMinObjAlignmentInBytes, dst);
4791 if (Universe::narrow_oop_base() != NULL)
4792 add(dst, G6_heapbase, dst);
4793 }
4794
4795 void MacroAssembler::reinit_heapbase() {
4796 if (UseCompressedOops) {
4797 // call indirectly to solve generation ordering problem
4798 AddressLiteral base(Universe::narrow_oop_base_addr());
4799 load_ptr_contents(base, G6_heapbase);
4800 }
4801 }
4802
4803 // Compare char[] arrays aligned to 4 bytes.
4804 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4805 Register limit, Register result,
4806 Register chr1, Register chr2, Label& Ldone) {
4807 Label Lvector, Lloop;
4808 assert(chr1 == result, "should be the same");
4809
4810 // Note: limit contains number of bytes (2*char_elements) != 0.
4811 andcc(limit, 0x2, chr1); // trailing character ?
4812 br(Assembler::zero, false, Assembler::pt, Lvector);
4813 delayed()->nop();
4814
4815 // compare the trailing char
4816 sub(limit, sizeof(jchar), limit);
4817 lduh(ary1, limit, chr1);
4818 lduh(ary2, limit, chr2);
4819 cmp(chr1, chr2);
4820 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4821 delayed()->mov(G0, result); // not equal
4822
4823 // only one char ?
4824 br_on_reg_cond(rc_z, true, Assembler::pn, limit, Ldone);
4825 delayed()->add(G0, 1, result); // zero-length arrays are equal
4826
4827 // word by word compare, dont't need alignment check
4828 bind(Lvector);
4829 // Shift ary1 and ary2 to the end of the arrays, negate limit
4830 add(ary1, limit, ary1);
4831 add(ary2, limit, ary2);
4832 neg(limit, limit);
4833
4834 lduw(ary1, limit, chr1);
4835 bind(Lloop);
4836 lduw(ary2, limit, chr2);
4837 cmp(chr1, chr2);
4838 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4839 delayed()->mov(G0, result); // not equal
4840 inccc(limit, 2*sizeof(jchar));
4841 // annul LDUW if branch is not taken to prevent access past end of array
4842 br(Assembler::notZero, true, Assembler::pt, Lloop);
4843 delayed()->lduw(ary1, limit, chr1); // hoisted
4844
4845 // Caller should set it:
4846 // add(G0, 1, result); // equals
4847 }
4848