817 StoreLoad = 1 << 1,
818 LoadLoad = 1 << 0,
819
820 Sync = 1 << 6,
821 MemIssue = 1 << 5,
822 Lookaside = 1 << 4
823 };
824
825 // test if x is within signed immediate range for nbits
826 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
827
828 // test if -4096 <= x <= 4095
829 static bool is_simm13(int x) { return is_simm(x, 13); }
830
831 // test if label is in simm16 range in words (wdisp16).
832 bool is_in_wdisp16_range(Label& L) {
833 intptr_t d = intptr_t(pc()) - intptr_t(target(L));
834 return is_simm(d, 18);
835 }
836
837 enum ASIs { // page 72, v9
838 ASI_PRIMARY = 0x80,
839 ASI_PRIMARY_LITTLE = 0x88
840 // add more from book as needed
841 };
842
843 protected:
844 // helpers
845
846 // x is supposed to fit in a field "nbits" wide
847 // and be sign-extended. Check the range.
848
849 static void assert_signed_range(intptr_t x, int nbits) {
850 assert( nbits == 32
851 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
852 "value out of range");
853 }
854
855 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
856 assert( (x & 3) == 0, "not word aligned");
1781 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1782
1783 // Support for NULL-checks
1784 //
1785 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1786 // If the accessed location is M[reg + offset] and the offset is known, provide the
1787 // offset. No explicit code generation is needed if the offset is within a certain
1788 // range (0 <= offset <= page_size).
1789 //
1790 // %%%%%% Currently not done for SPARC
1791
1792 void null_check(Register reg, int offset = -1);
1793 static bool needs_explicit_null_check(intptr_t offset);
1794
1795 // support for delayed instructions
1796 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1797
1798 // branches that use right instruction for v8 vs. v9
1799 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1800 inline void br( Condition c, bool a, Predict p, Label& L );
1801 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1802 inline void fb( Condition c, bool a, Predict p, Label& L );
1803
1804 // compares register with zero and branches (V9 and V8 instructions)
1805 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1806 // Compares a pointer register with zero and branches on (not)null.
1807 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1808 void br_null ( Register s1, bool a, Predict p, Label& L );
1809 void br_notnull( Register s1, bool a, Predict p, Label& L );
1810
1811 // These versions will do the most efficient thing on v8 and v9. Perhaps
1812 // this is what the routine above was meant to do, but it didn't (and
1813 // didn't cover both target address kinds.)
1814 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1815 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1816
1817 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1818 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1819
1820 // Branch that tests xcc in LP64 and icc in !LP64
|
817 StoreLoad = 1 << 1,
818 LoadLoad = 1 << 0,
819
820 Sync = 1 << 6,
821 MemIssue = 1 << 5,
822 Lookaside = 1 << 4
823 };
824
825 // test if x is within signed immediate range for nbits
826 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
827
828 // test if -4096 <= x <= 4095
829 static bool is_simm13(int x) { return is_simm(x, 13); }
830
831 // test if label is in simm16 range in words (wdisp16).
832 bool is_in_wdisp16_range(Label& L) {
833 intptr_t d = intptr_t(pc()) - intptr_t(target(L));
834 return is_simm(d, 18);
835 }
836
837 static CC heap_oop_cc() {
838 #ifdef _LP64
839 if (UseCompressedOops) return icc;
840 else return xcc;
841 #endif
842 return icc;
843 }
844
845 enum ASIs { // page 72, v9
846 ASI_PRIMARY = 0x80,
847 ASI_PRIMARY_LITTLE = 0x88
848 // add more from book as needed
849 };
850
851 protected:
852 // helpers
853
854 // x is supposed to fit in a field "nbits" wide
855 // and be sign-extended. Check the range.
856
857 static void assert_signed_range(intptr_t x, int nbits) {
858 assert( nbits == 32
859 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
860 "value out of range");
861 }
862
863 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
864 assert( (x & 3) == 0, "not word aligned");
1789 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1790
1791 // Support for NULL-checks
1792 //
1793 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1794 // If the accessed location is M[reg + offset] and the offset is known, provide the
1795 // offset. No explicit code generation is needed if the offset is within a certain
1796 // range (0 <= offset <= page_size).
1797 //
1798 // %%%%%% Currently not done for SPARC
1799
1800 void null_check(Register reg, int offset = -1);
1801 static bool needs_explicit_null_check(intptr_t offset);
1802
1803 // support for delayed instructions
1804 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1805
1806 // branches that use right instruction for v8 vs. v9
1807 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1808 inline void br( Condition c, bool a, Predict p, Label& L );
1809 // branches on specific condition code (always icc on 32 bit)
1810 inline void br( Condition c, CC cc, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1811 inline void br( Condition c, CC cc, bool a, Predict p, Label& L );
1812
1813 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1814 inline void fb( Condition c, bool a, Predict p, Label& L );
1815
1816 // compares register with zero and branches (V9 and V8 instructions)
1817 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1818 // Compares a pointer register with zero and branches on (not)null.
1819 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1820 void br_null ( Register s1, bool a, Predict p, Label& L );
1821 void br_notnull( Register s1, bool a, Predict p, Label& L );
1822
1823 // These versions will do the most efficient thing on v8 and v9. Perhaps
1824 // this is what the routine above was meant to do, but it didn't (and
1825 // didn't cover both target address kinds.)
1826 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1827 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1828
1829 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1830 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1831
1832 // Branch that tests xcc in LP64 and icc in !LP64
|