83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (dst->is_register()) {
104 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
105 return !PatchALot;
106 } else if (src->is_single_stack()) {
107 return true;
108 }
109 }
110
111 if (src->is_register()) {
112 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
113 return !PatchALot;
114 } else if (dst->is_single_stack()) {
115 return true;
116 }
117 }
118
119 if (dst->is_register() &&
120 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
121 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
122 return true;
236 Register str0 = left->as_register();
237 Register str1 = right->as_register();
238
239 Label Ldone;
240
241 Register result = dst->as_register();
242 {
243 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
244 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
245 // Also, get string0.count-string1.count in o7 and get the condition code set
246 // Note: some instructions have been hoisted for better instruction scheduling
247
248 Register tmp0 = L0;
249 Register tmp1 = L1;
250 Register tmp2 = L2;
251
252 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
253 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
254 int count_offset = java_lang_String:: count_offset_in_bytes();
255
256 __ ld_ptr(str0, value_offset, tmp0);
257 __ ld(str0, offset_offset, tmp2);
258 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
259 __ ld(str0, count_offset, str0);
260 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
261
262 // str1 may be null
263 add_debug_info_for_null_check_here(info);
264
265 __ ld_ptr(str1, value_offset, tmp1);
266 __ add(tmp0, tmp2, tmp0);
267
268 __ ld(str1, offset_offset, tmp2);
269 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
270 __ ld(str1, count_offset, str1);
271 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
272 __ subcc(str0, str1, O7);
273 __ add(tmp1, tmp2, tmp1);
274 }
275
276 {
277 // Compute the minimum of the string lengths, scale it and store it in limit
278 Register count0 = I0;
279 Register count1 = I1;
280 Register limit = L3;
281
282 Label Lskip;
283 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
284 __ br(Assembler::greater, true, Assembler::pt, Lskip);
285 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
749
750 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
751 __ call(op->addr(), rtype);
752 // The peephole pass fills the delay slot, add_call_info is done in
753 // LIR_Assembler::emit_delay.
754 }
755
756
757 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
758 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
759 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
760 __ relocate(rspec);
761 __ call(op->addr(), relocInfo::none);
762 // The peephole pass fills the delay slot, add_call_info is done in
763 // LIR_Assembler::emit_delay.
764 }
765
766
767 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
768 add_debug_info_for_null_check_here(op->info());
769 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
770 if (__ is_simm13(op->vtable_offset())) {
771 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
772 } else {
773 // This will generate 2 instructions
774 __ set(op->vtable_offset(), G5_method);
775 // ld_ptr, set_hi, set
776 __ ld_ptr(G3_scratch, G5_method, G5_method);
777 }
778 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
779 __ callr(G3_scratch, G0);
780 // the peephole pass fills the delay slot
781 }
782
783
784 // load with 32-bit displacement
785 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
786 int load_offset = code_offset();
787 if (Assembler::is_simm13(disp)) {
788 if (info != NULL) add_debug_info_for_null_check_here(info);
789 switch(ld_type) {
790 case T_BOOLEAN: // fall through
791 case T_BYTE : __ ldsb(s, disp, d); break;
792 case T_CHAR : __ lduh(s, disp, d); break;
793 case T_SHORT : __ ldsh(s, disp, d); break;
794 case T_INT : __ ld(s, disp, d); break;
795 case T_ADDRESS:// fall through
796 case T_ARRAY : // fall through
797 case T_OBJECT: __ ld_ptr(s, disp, d); break;
798 default : ShouldNotReachHere();
799 }
800 } else {
801 __ set(disp, O7);
802 if (info != NULL) add_debug_info_for_null_check_here(info);
803 load_offset = code_offset();
804 switch(ld_type) {
805 case T_BOOLEAN: // fall through
806 case T_BYTE : __ ldsb(s, O7, d); break;
807 case T_CHAR : __ lduh(s, O7, d); break;
808 case T_SHORT : __ ldsh(s, O7, d); break;
809 case T_INT : __ ld(s, O7, d); break;
810 case T_ADDRESS:// fall through
811 case T_ARRAY : // fall through
812 case T_OBJECT: __ ld_ptr(s, O7, d); break;
813 default : ShouldNotReachHere();
814 }
815 }
816 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
817 return load_offset;
818 }
819
820
821 // store with 32-bit displacement
822 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
823 if (Assembler::is_simm13(offset)) {
824 if (info != NULL) add_debug_info_for_null_check_here(info);
825 switch (type) {
826 case T_BOOLEAN: // fall through
827 case T_BYTE : __ stb(value, base, offset); break;
828 case T_CHAR : __ sth(value, base, offset); break;
829 case T_SHORT : __ sth(value, base, offset); break;
830 case T_INT : __ stw(value, base, offset); break;
831 case T_ADDRESS:// fall through
832 case T_ARRAY : // fall through
833 case T_OBJECT: __ st_ptr(value, base, offset); break;
834 default : ShouldNotReachHere();
835 }
836 } else {
837 __ set(offset, O7);
838 if (info != NULL) add_debug_info_for_null_check_here(info);
839 switch (type) {
840 case T_BOOLEAN: // fall through
841 case T_BYTE : __ stb(value, base, O7); break;
842 case T_CHAR : __ sth(value, base, O7); break;
843 case T_SHORT : __ sth(value, base, O7); break;
844 case T_INT : __ stw(value, base, O7); break;
845 case T_ADDRESS:// fall through
846 case T_ARRAY : //fall through
847 case T_OBJECT: __ st_ptr(value, base, O7); break;
848 default : ShouldNotReachHere();
849 }
850 }
851 // Note: Do the store before verification as the code might be patched!
852 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
853 }
854
855
856 // load float with 32-bit displacement
857 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
858 FloatRegisterImpl::Width w;
859 switch(ld_type) {
860 case T_FLOAT : w = FloatRegisterImpl::S; break;
861 case T_DOUBLE: w = FloatRegisterImpl::D; break;
862 default : ShouldNotReachHere();
863 }
864
865 if (Assembler::is_simm13(disp)) {
866 if (info != NULL) add_debug_info_for_null_check_here(info);
867 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
868 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
869 __ ldf(FloatRegisterImpl::S, s, disp , d);
870 } else {
871 __ ldf(w, s, disp, d);
872 }
873 } else {
874 __ set(disp, O7);
875 if (info != NULL) add_debug_info_for_null_check_here(info);
876 __ ldf(w, s, O7, d);
877 }
878 }
879
880
881 // store float with 32-bit displacement
882 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
883 FloatRegisterImpl::Width w;
884 switch(type) {
885 case T_FLOAT : w = FloatRegisterImpl::S; break;
886 case T_DOUBLE: w = FloatRegisterImpl::D; break;
887 default : ShouldNotReachHere();
888 }
889
890 if (Assembler::is_simm13(offset)) {
891 if (info != NULL) add_debug_info_for_null_check_here(info);
892 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
893 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
894 __ stf(FloatRegisterImpl::S, value , base, offset);
895 } else {
896 __ stf(w, value, base, offset);
897 }
898 } else {
899 __ set(offset, O7);
900 if (info != NULL) add_debug_info_for_null_check_here(info);
901 __ stf(w, value, O7, base);
902 }
903 }
904
905
906 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
907 int store_offset;
908 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
909 assert(!unaligned, "can't handle this");
910 // for offsets larger than a simm13 we setup the offset in O7
911 __ set(offset, O7);
912 store_offset = store(from_reg, base, O7, type);
913 } else {
914 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
915 store_offset = code_offset();
916 switch (type) {
917 case T_BOOLEAN: // fall through
918 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
919 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
920 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
921 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
922 case T_LONG :
923 #ifdef _LP64
924 if (unaligned || PatchALot) {
925 __ srax(from_reg->as_register_lo(), 32, O7);
926 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
927 __ stw(O7, base, offset + hi_word_offset_in_bytes);
928 } else {
929 __ stx(from_reg->as_register_lo(), base, offset);
930 }
931 #else
932 assert(Assembler::is_simm13(offset + 4), "must be");
933 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
934 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
935 #endif
936 break;
937 case T_ADDRESS:// fall through
938 case T_ARRAY : // fall through
939 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
940 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
941 case T_DOUBLE:
942 {
943 FloatRegister reg = from_reg->as_double_reg();
944 // split unaligned stores
945 if (unaligned || PatchALot) {
946 assert(Assembler::is_simm13(offset + 4), "must be");
947 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
948 __ stf(FloatRegisterImpl::S, reg, base, offset);
949 } else {
950 __ stf(FloatRegisterImpl::D, reg, base, offset);
951 }
952 break;
953 }
954 default : ShouldNotReachHere();
955 }
956 }
957 return store_offset;
958 }
959
960
961 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
962 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
963 int store_offset = code_offset();
964 switch (type) {
965 case T_BOOLEAN: // fall through
966 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
967 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
968 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
969 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
970 case T_LONG :
971 #ifdef _LP64
972 __ stx(from_reg->as_register_lo(), base, disp);
973 #else
974 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
975 __ std(from_reg->as_register_hi(), base, disp);
976 #endif
977 break;
978 case T_ADDRESS:// fall through
979 case T_ARRAY : // fall through
980 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
981 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
982 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
983 default : ShouldNotReachHere();
984 }
985 return store_offset;
986 }
987
988
989 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
990 int load_offset;
991 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
992 assert(base != O7, "destroying register");
993 assert(!unaligned, "can't handle this");
994 // for offsets larger than a simm13 we setup the offset in O7
995 __ set(offset, O7);
996 load_offset = load(base, O7, to_reg, type);
997 } else {
998 load_offset = code_offset();
999 switch(type) {
1000 case T_BOOLEAN: // fall through
1001 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
1002 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
1003 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
1004 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
1005 case T_LONG :
1006 if (!unaligned) {
1007 #ifdef _LP64
1008 __ ldx(base, offset, to_reg->as_register_lo());
1009 #else
1010 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1011 "must be sequential");
1012 __ ldd(base, offset, to_reg->as_register_hi());
1013 #endif
1014 } else {
1015 #ifdef _LP64
1016 assert(base != to_reg->as_register_lo(), "can't handle this");
1017 assert(O7 != to_reg->as_register_lo(), "can't handle this");
1018 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
1019 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
1020 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
1021 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
1022 #else
1023 if (base == to_reg->as_register_lo()) {
1024 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1025 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1026 } else {
1027 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1028 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1029 }
1030 #endif
1031 }
1032 break;
1033 case T_ADDRESS:// fall through
1034 case T_ARRAY : // fall through
1035 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
1036 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
1037 case T_DOUBLE:
1038 {
1039 FloatRegister reg = to_reg->as_double_reg();
1040 // split unaligned loads
1041 if (unaligned || PatchALot) {
1042 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
1043 __ ldf(FloatRegisterImpl::S, base, offset, reg);
1044 } else {
1045 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
1046 }
1047 break;
1048 }
1049 default : ShouldNotReachHere();
1050 }
1051 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1052 }
1053 return load_offset;
1054 }
1055
1056
1057 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
1058 int load_offset = code_offset();
1059 switch(type) {
1060 case T_BOOLEAN: // fall through
1061 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1062 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1063 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1064 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1065 case T_ADDRESS:// fall through
1066 case T_ARRAY : // fall through
1067 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1068 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1069 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1070 case T_LONG :
1071 #ifdef _LP64
1072 __ ldx(base, disp, to_reg->as_register_lo());
1073 #else
1074 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1075 "must be sequential");
1076 __ ldd(base, disp, to_reg->as_register_hi());
1077 #endif
1078 break;
1079 default : ShouldNotReachHere();
1080 }
1081 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1082 return load_offset;
1083 }
1084
1085
1086 // load/store with an Address
1087 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1088 load(a.base(), a.disp() + offset, d, ld_type, info);
1089 }
1090
1091
1092 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1093 store(value, dest.base(), dest.disp() + offset, type, info);
1094 }
1095
1096
1097 // loadf/storef with an Address
1098 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1099 load(a.base(), a.disp() + offset, d, ld_type, info);
1100 }
1101
1102
1103 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1104 store(value, dest.base(), dest.disp() + offset, type, info);
1105 }
1106
1107
1108 // load/store with an Address
1109 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1110 load(as_Address(a), d, ld_type, info);
1111 }
1112
1113
1114 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1115 store(value, as_Address(dest), type, info);
1116 }
1117
1118
1119 // loadf/storef with an Address
1120 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1121 load(as_Address(a), d, ld_type, info);
1122 }
1123
1124
1125 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1126 store(value, as_Address(dest), type, info);
1127 }
1128
1129
1130 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1131 LIR_Const* c = src->as_constant_ptr();
1132 switch (c->type()) {
1133 case T_INT:
1134 case T_FLOAT:
1135 case T_ADDRESS: {
1136 Register src_reg = O7;
1137 int value = c->as_jint_bits();
1138 if (value == 0) {
1139 src_reg = G0;
1140 } else {
1141 __ set(value, O7);
1142 }
1143 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1144 __ stw(src_reg, addr.base(), addr.disp());
1145 break;
1146 }
1147 case T_OBJECT: {
1148 Register src_reg = O7;
1149 jobject2reg(c->as_jobject(), src_reg);
1150 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1151 __ st_ptr(src_reg, addr.base(), addr.disp());
1152 break;
1153 }
1154 case T_LONG:
1155 case T_DOUBLE: {
1156 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1157
1158 Register tmp = O7;
1159 int value_lo = c->as_jint_lo_bits();
1160 if (value_lo == 0) {
1161 tmp = G0;
1162 } else {
1163 __ set(value_lo, O7);
1164 }
1165 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1166 int value_hi = c->as_jint_hi_bits();
1167 if (value_hi == 0) {
1168 tmp = G0;
1169 } else {
1170 __ set(value_hi, O7);
1171 }
1172 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1173 break;
1174 }
1175 default:
1176 Unimplemented();
1177 }
1178 }
1179
1180
1181 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1182 LIR_Const* c = src->as_constant_ptr();
1183 LIR_Address* addr = dest->as_address_ptr();
1184 Register base = addr->base()->as_pointer_register();
1185
1186 if (info != NULL) {
1187 add_debug_info_for_null_check_here(info);
1188 }
1189 switch (c->type()) {
1190 case T_INT:
1191 case T_FLOAT:
1192 case T_ADDRESS: {
1193 LIR_Opr tmp = FrameMap::O7_opr;
1194 int value = c->as_jint_bits();
1195 if (value == 0) {
1196 tmp = FrameMap::G0_opr;
1197 } else if (Assembler::is_simm13(value)) {
1198 __ set(value, O7);
1199 }
1200 if (addr->index()->is_valid()) {
1201 assert(addr->disp() == 0, "must be zero");
1202 store(tmp, base, addr->index()->as_pointer_register(), type);
1203 } else {
1204 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1205 store(tmp, base, addr->disp(), type);
1206 }
1207 break;
1208 }
1209 case T_LONG:
1210 case T_DOUBLE: {
1211 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1212 assert(Assembler::is_simm13(addr->disp()) &&
1213 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1214
1215 Register tmp = O7;
1216 int value_lo = c->as_jint_lo_bits();
1217 if (value_lo == 0) {
1218 tmp = G0;
1219 } else {
1220 __ set(value_lo, O7);
1221 }
1222 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1223 int value_hi = c->as_jint_hi_bits();
1224 if (value_hi == 0) {
1225 tmp = G0;
1226 } else {
1227 __ set(value_hi, O7);
1228 }
1229 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1230 break;
1231 }
1232 case T_OBJECT: {
1233 jobject obj = c->as_jobject();
1234 LIR_Opr tmp;
1235 if (obj == NULL) {
1236 tmp = FrameMap::G0_opr;
1237 } else {
1238 tmp = FrameMap::O7_opr;
1239 jobject2reg(c->as_jobject(), O7);
1240 }
1241 // handle either reg+reg or reg+disp address
1242 if (addr->index()->is_valid()) {
1243 assert(addr->disp() == 0, "must be zero");
1244 store(tmp, base, addr->index()->as_pointer_register(), type);
1245 } else {
1246 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1247 store(tmp, base, addr->disp(), type);
1248 }
1249
1250 break;
1251 }
1252 default:
1253 Unimplemented();
1254 }
1255 }
1256
1257
1258 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1259 LIR_Const* c = src->as_constant_ptr();
1260 LIR_Opr to_reg = dest;
1261
1262 switch (c->type()) {
1263 case T_INT:
1264 case T_ADDRESS:
1265 {
1266 jint con = c->as_jint();
1267 if (to_reg->is_single_cpu()) {
1268 assert(patch_code == lir_patch_none, "no patching handled here");
1269 __ set(con, to_reg->as_register());
1270 } else {
1271 ShouldNotReachHere();
1272 assert(to_reg->is_single_fpu(), "wrong register kind");
1273
1274 __ set(con, O7);
1319 break;
1320
1321 case T_FLOAT:
1322 {
1323 address const_addr = __ float_constant(c->as_jfloat());
1324 if (const_addr == NULL) {
1325 bailout("const section overflow");
1326 break;
1327 }
1328 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1329 AddressLiteral const_addrlit(const_addr, rspec);
1330 if (to_reg->is_single_fpu()) {
1331 __ patchable_sethi(const_addrlit, O7);
1332 __ relocate(rspec);
1333 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1334
1335 } else {
1336 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1337
1338 __ set(const_addrlit, O7);
1339 load(O7, 0, to_reg->as_register(), T_INT);
1340 }
1341 }
1342 break;
1343
1344 case T_DOUBLE:
1345 {
1346 address const_addr = __ double_constant(c->as_jdouble());
1347 if (const_addr == NULL) {
1348 bailout("const section overflow");
1349 break;
1350 }
1351 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1352
1353 if (to_reg->is_double_fpu()) {
1354 AddressLiteral const_addrlit(const_addr, rspec);
1355 __ patchable_sethi(const_addrlit, O7);
1356 __ relocate(rspec);
1357 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1358 } else {
1359 assert(to_reg->is_double_cpu(), "Must be a long register.");
1412
1413 default:
1414 ShouldNotReachHere();
1415 }
1416 }
1417
1418
1419 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1420 Address base = as_Address(addr);
1421 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1422 }
1423
1424
1425 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1426 Address base = as_Address(addr);
1427 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1428 }
1429
1430
1431 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1432 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1433
1434 LIR_Address* addr = src_opr->as_address_ptr();
1435 LIR_Opr to_reg = dest;
1436
1437 Register src = addr->base()->as_pointer_register();
1438 Register disp_reg = noreg;
1439 int disp_value = addr->disp();
1440 bool needs_patching = (patch_code != lir_patch_none);
1441
1442 if (addr->base()->type() == T_OBJECT) {
1443 __ verify_oop(src);
1444 }
1445
1446 PatchingStub* patch = NULL;
1447 if (needs_patching) {
1448 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1449 assert(!to_reg->is_double_cpu() ||
1450 patch_code == lir_patch_none ||
1451 patch_code == lir_patch_normal, "patching doesn't match register");
1452 }
1458 } else {
1459 __ set(disp_value, O7);
1460 }
1461 disp_reg = O7;
1462 }
1463 } else if (unaligned || PatchALot) {
1464 __ add(src, addr->index()->as_register(), O7);
1465 src = O7;
1466 } else {
1467 disp_reg = addr->index()->as_pointer_register();
1468 assert(disp_value == 0, "can't handle 3 operand addresses");
1469 }
1470
1471 // remember the offset of the load. The patching_epilog must be done
1472 // before the call to add_debug_info, otherwise the PcDescs don't get
1473 // entered in increasing order.
1474 int offset = code_offset();
1475
1476 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1477 if (disp_reg == noreg) {
1478 offset = load(src, disp_value, to_reg, type, unaligned);
1479 } else {
1480 assert(!unaligned, "can't handle this");
1481 offset = load(src, disp_reg, to_reg, type);
1482 }
1483
1484 if (patch != NULL) {
1485 patching_epilog(patch, patch_code, src, info);
1486 }
1487
1488 if (info != NULL) add_debug_info_for_null_check(offset, info);
1489 }
1490
1491
1492 void LIR_Assembler::prefetchr(LIR_Opr src) {
1493 LIR_Address* addr = src->as_address_ptr();
1494 Address from_addr = as_Address(addr);
1495
1496 if (VM_Version::has_v9()) {
1497 __ prefetch(from_addr, Assembler::severalReads);
1498 }
1499 }
1500
1501
1502 void LIR_Assembler::prefetchw(LIR_Opr src) {
1503 LIR_Address* addr = src->as_address_ptr();
1504 Address from_addr = as_Address(addr);
1505
1506 if (VM_Version::has_v9()) {
1507 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1508 }
1509 }
1510
1511
1512 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1513 Address addr;
1514 if (src->is_single_word()) {
1515 addr = frame_map()->address_for_slot(src->single_stack_ix());
1516 } else if (src->is_double_word()) {
1517 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1518 }
1519
1520 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1521 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1522 }
1523
1524
1525 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1526 Address addr;
1527 if (dest->is_single_word()) {
1528 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1529 } else if (dest->is_double_word()) {
1530 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1531 }
1532 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1533 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1534 }
1535
1536
1537 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1538 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1539 if (from_reg->is_double_fpu()) {
1540 // double to double moves
1541 assert(to_reg->is_double_fpu(), "should match");
1542 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1543 } else {
1544 // float to float moves
1545 assert(to_reg->is_single_fpu(), "should match");
1546 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1547 }
1548 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1549 if (from_reg->is_double_cpu()) {
1550 #ifdef _LP64
1551 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1552 #else
1553 assert(to_reg->is_double_cpu() &&
1561 #ifdef _LP64
1562 } else if (to_reg->is_double_cpu()) {
1563 // int to int moves
1564 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1565 #endif
1566 } else {
1567 // int to int moves
1568 __ mov(from_reg->as_register(), to_reg->as_register());
1569 }
1570 } else {
1571 ShouldNotReachHere();
1572 }
1573 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1574 __ verify_oop(to_reg->as_register());
1575 }
1576 }
1577
1578
1579 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1580 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1581 bool unaligned) {
1582 LIR_Address* addr = dest->as_address_ptr();
1583
1584 Register src = addr->base()->as_pointer_register();
1585 Register disp_reg = noreg;
1586 int disp_value = addr->disp();
1587 bool needs_patching = (patch_code != lir_patch_none);
1588
1589 if (addr->base()->is_oop_register()) {
1590 __ verify_oop(src);
1591 }
1592
1593 PatchingStub* patch = NULL;
1594 if (needs_patching) {
1595 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1596 assert(!from_reg->is_double_cpu() ||
1597 patch_code == lir_patch_none ||
1598 patch_code == lir_patch_normal, "patching doesn't match register");
1599 }
1600
1601 if (addr->index()->is_illegal()) {
1605 } else {
1606 __ set(disp_value, O7);
1607 }
1608 disp_reg = O7;
1609 }
1610 } else if (unaligned || PatchALot) {
1611 __ add(src, addr->index()->as_register(), O7);
1612 src = O7;
1613 } else {
1614 disp_reg = addr->index()->as_pointer_register();
1615 assert(disp_value == 0, "can't handle 3 operand addresses");
1616 }
1617
1618 // remember the offset of the store. The patching_epilog must be done
1619 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1620 // entered in increasing order.
1621 int offset;
1622
1623 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1624 if (disp_reg == noreg) {
1625 offset = store(from_reg, src, disp_value, type, unaligned);
1626 } else {
1627 assert(!unaligned, "can't handle this");
1628 offset = store(from_reg, src, disp_reg, type);
1629 }
1630
1631 if (patch != NULL) {
1632 patching_epilog(patch, patch_code, src, info);
1633 }
1634
1635 if (info != NULL) add_debug_info_for_null_check(offset, info);
1636 }
1637
1638
1639 void LIR_Assembler::return_op(LIR_Opr result) {
1640 // the poll may need a register so just pick one that isn't the return register
1641 #if defined(TIERED) && !defined(_LP64)
1642 if (result->type_field() == LIR_OprDesc::long_type) {
1643 // Must move the result to G1
1644 // Must leave proper result in O0,O1 and G1 (TIERED only)
1645 __ sllx(I0, 32, G1); // Shift bits into high G1
1646 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1647 __ or3 (I1, G1, G1); // OR 64 bits into G1
1648 #ifdef ASSERT
2167 if (op->expected_type() == NULL ||
2168 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2169 __ mov(src, O0);
2170 __ mov(src_pos, O1);
2171 __ mov(dst, O2);
2172 __ mov(dst_pos, O3);
2173 __ mov(length, O4);
2174 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2175
2176 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2177 __ delayed()->nop();
2178 __ bind(*stub->continuation());
2179 return;
2180 }
2181
2182 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2183
2184 // make sure src and dst are non-null and load array length
2185 if (flags & LIR_OpArrayCopy::src_null_check) {
2186 __ tst(src);
2187 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2188 __ delayed()->nop();
2189 }
2190
2191 if (flags & LIR_OpArrayCopy::dst_null_check) {
2192 __ tst(dst);
2193 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2194 __ delayed()->nop();
2195 }
2196
2197 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2198 // test src_pos register
2199 __ tst(src_pos);
2200 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2201 __ delayed()->nop();
2202 }
2203
2204 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2205 // test dst_pos register
2206 __ tst(dst_pos);
2207 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2208 __ delayed()->nop();
2209 }
2210
2211 if (flags & LIR_OpArrayCopy::length_positive_check) {
2212 // make sure length isn't negative
2213 __ tst(length);
2215 __ delayed()->nop();
2216 }
2217
2218 if (flags & LIR_OpArrayCopy::src_range_check) {
2219 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2220 __ add(length, src_pos, tmp);
2221 __ cmp(tmp2, tmp);
2222 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2223 __ delayed()->nop();
2224 }
2225
2226 if (flags & LIR_OpArrayCopy::dst_range_check) {
2227 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2228 __ add(length, dst_pos, tmp);
2229 __ cmp(tmp2, tmp);
2230 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2231 __ delayed()->nop();
2232 }
2233
2234 if (flags & LIR_OpArrayCopy::type_check) {
2235 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2236 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2237 __ cmp(tmp, tmp2);
2238 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2239 __ delayed()->nop();
2240 }
2241
2242 #ifdef ASSERT
2243 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2244 // Sanity check the known type with the incoming class. For the
2245 // primitive case the types must match exactly with src.klass and
2246 // dst.klass each exactly matching the default type. For the
2247 // object array case, if no type check is needed then either the
2248 // dst type is exactly the expected type and the src type is a
2249 // subtype which we can't check or src is the same array as dst
2250 // but not necessarily exactly of type default_type.
2251 Label known_ok, halt;
2252 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2253 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2254 if (basic_type != T_OBJECT) {
2255 __ cmp(tmp, tmp2);
2256 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2257 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2258 __ cmp(tmp, tmp2);
2259 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2260 __ delayed()->nop();
2261 } else {
2262 __ cmp(tmp, tmp2);
2263 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2264 __ delayed()->cmp(src, dst);
2265 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2266 __ delayed()->nop();
2267 }
2268 __ bind(halt);
2269 __ stop("incorrect type information in arraycopy");
2270 __ bind(known_ok);
2271 }
2272 #endif
2273
2274 int shift = shift_amount(basic_type);
2275
2276 Register src_ptr = O0;
2277 Register dst_ptr = O1;
2278 Register len = O2;
2279
2280 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2281 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2282 if (shift == 0) {
2283 __ add(src_ptr, src_pos, src_ptr);
2284 } else {
2285 __ sll(src_pos, shift, tmp);
2454 __ ld_ptr(receiver_addr, tmp1);
2455 __ verify_oop(tmp1);
2456 __ cmp(recv, tmp1);
2457 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2458 __ delayed()->nop();
2459 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2460 mdo_offset_bias);
2461 __ ld_ptr(data_addr, tmp1);
2462 __ add(tmp1, DataLayout::counter_increment, tmp1);
2463 __ st_ptr(tmp1, data_addr);
2464 __ ba(false, *update_done);
2465 __ delayed()->nop();
2466 __ bind(next_test);
2467 }
2468
2469 // Didn't find receiver; find next empty slot and fill it in
2470 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2471 Label next_test;
2472 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2473 mdo_offset_bias);
2474 load(recv_addr, tmp1, T_OBJECT);
2475 __ br_notnull(tmp1, false, Assembler::pt, next_test);
2476 __ delayed()->nop();
2477 __ st_ptr(recv, recv_addr);
2478 __ set(DataLayout::counter_increment, tmp1);
2479 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2480 mdo_offset_bias);
2481 __ ba(false, *update_done);
2482 __ delayed()->nop();
2483 __ bind(next_test);
2484 }
2485 }
2486
2487
2488 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2489 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2490 md = method->method_data();
2491 if (md == NULL) {
2492 bailout("out of memory building methodDataOop");
2493 return;
2494 }
2546 } else {
2547 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2548 __ delayed()->nop();
2549 }
2550
2551 Label profile_cast_failure, profile_cast_success;
2552 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2553 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2554
2555 // patching may screw with our temporaries on sparc,
2556 // so let's do it before loading the class
2557 if (k->is_loaded()) {
2558 jobject2reg(k->constant_encoding(), k_RInfo);
2559 } else {
2560 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2561 }
2562 assert(obj != k_RInfo, "must be different");
2563
2564 // get object class
2565 // not a safepoint as obj null check happens earlier
2566 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2567 if (op->fast_check()) {
2568 assert_different_registers(klass_RInfo, k_RInfo);
2569 __ cmp(k_RInfo, klass_RInfo);
2570 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2571 __ delayed()->nop();
2572 } else {
2573 bool need_slow_path = true;
2574 if (k->is_loaded()) {
2575 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2576 need_slow_path = false;
2577 // perform the fast part of the checking logic
2578 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2579 (need_slow_path ? success_target : NULL),
2580 failure_target, NULL,
2581 RegisterOrConstant(k->super_check_offset()));
2582 } else {
2583 // perform the fast part of the checking logic
2584 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2585 failure_target, NULL);
2586 }
2588 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2589 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2590 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2591 __ delayed()->nop();
2592 __ cmp(G3, 0);
2593 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2594 __ delayed()->nop();
2595 // Fall through to success case
2596 }
2597 }
2598
2599 if (op->should_profile()) {
2600 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2601 assert_different_registers(obj, mdo, recv, tmp1);
2602 __ bind(profile_cast_success);
2603 jobject2reg(md->constant_encoding(), mdo);
2604 if (mdo_offset_bias > 0) {
2605 __ set(mdo_offset_bias, tmp1);
2606 __ add(mdo, tmp1, mdo);
2607 }
2608 load(Address(obj, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2609 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2610 // Jump over the failure case
2611 __ ba(false, *success);
2612 __ delayed()->nop();
2613 // Cast failure case
2614 __ bind(profile_cast_failure);
2615 jobject2reg(md->constant_encoding(), mdo);
2616 if (mdo_offset_bias > 0) {
2617 __ set(mdo_offset_bias, tmp1);
2618 __ add(mdo, tmp1, mdo);
2619 }
2620 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2621 __ ld_ptr(data_addr, tmp1);
2622 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2623 __ st_ptr(tmp1, data_addr);
2624 __ ba(false, *failure);
2625 __ delayed()->nop();
2626 }
2627 __ ba(false, *success);
2628 __ delayed()->nop();
2657 __ br_notnull(value, false, Assembler::pn, not_null);
2658 __ delayed()->nop();
2659 Register mdo = k_RInfo;
2660 Register data_val = Rtmp1;
2661 jobject2reg(md->constant_encoding(), mdo);
2662 if (mdo_offset_bias > 0) {
2663 __ set(mdo_offset_bias, data_val);
2664 __ add(mdo, data_val, mdo);
2665 }
2666 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2667 __ ldub(flags_addr, data_val);
2668 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2669 __ stb(data_val, flags_addr);
2670 __ ba(false, done);
2671 __ delayed()->nop();
2672 __ bind(not_null);
2673 } else {
2674 __ br_null(value, false, Assembler::pn, done);
2675 __ delayed()->nop();
2676 }
2677 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2678 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2679
2680 // get instance klass
2681 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2682 // perform the fast part of the checking logic
2683 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2684
2685 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2686 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2687 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2688 __ delayed()->nop();
2689 __ cmp(G3, 0);
2690 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2691 __ delayed()->nop();
2692 // fall through to the success case
2693
2694 if (op->should_profile()) {
2695 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2696 assert_different_registers(value, mdo, recv, tmp1);
2697 __ bind(profile_cast_success);
2698 jobject2reg(md->constant_encoding(), mdo);
2699 if (mdo_offset_bias > 0) {
2700 __ set(mdo_offset_bias, tmp1);
2701 __ add(mdo, tmp1, mdo);
2702 }
2703 load(Address(value, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2704 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2705 __ ba(false, done);
2706 __ delayed()->nop();
2707 // Cast failure case
2708 __ bind(profile_cast_failure);
2709 jobject2reg(md->constant_encoding(), mdo);
2710 if (mdo_offset_bias > 0) {
2711 __ set(mdo_offset_bias, tmp1);
2712 __ add(mdo, tmp1, mdo);
2713 }
2714 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2715 __ ld_ptr(data_addr, tmp1);
2716 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2717 __ st_ptr(tmp1, data_addr);
2718 __ ba(false, *stub->entry());
2719 __ delayed()->nop();
2720 }
2721 __ bind(done);
2722 } else if (code == lir_checkcast) {
2723 Register obj = op->object()->as_register();
2764 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2765 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2766 __ sllx(new_value_hi, 32, t2);
2767 __ srl(new_value_lo, 0, new_value_lo);
2768 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2769 #endif
2770 // perform the compare and swap operation
2771 __ casx(addr, t1, t2);
2772 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2773 // overwritten with the original value in "addr" and will be equal to t1.
2774 __ cmp(t1, t2);
2775
2776 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2777 Register addr = op->addr()->as_pointer_register();
2778 Register cmp_value = op->cmp_value()->as_register();
2779 Register new_value = op->new_value()->as_register();
2780 Register t1 = op->tmp1()->as_register();
2781 Register t2 = op->tmp2()->as_register();
2782 __ mov(cmp_value, t1);
2783 __ mov(new_value, t2);
2784 #ifdef _LP64
2785 if (op->code() == lir_cas_obj) {
2786 __ casx(addr, t1, t2);
2787 } else
2788 #endif
2789 {
2790 __ cas(addr, t1, t2);
2791 }
2792 __ cmp(t1, t2);
2793 } else {
2794 Unimplemented();
2795 }
2796 }
2797
2798 void LIR_Assembler::set_24bit_FPU() {
2799 Unimplemented();
2800 }
2801
2802
2803 void LIR_Assembler::reset_FPU() {
2804 Unimplemented();
2805 }
2806
2807
2808 void LIR_Assembler::breakpoint() {
2809 __ breakpoint_trap();
2949
2950 // Note that this is less efficient than it should be because it
2951 // always does a write to the receiver part of the
2952 // VirtualCallData rather than just the first time
2953 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2954 ciKlass* receiver = vc_data->receiver(i);
2955 if (receiver == NULL) {
2956 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2957 mdo_offset_bias);
2958 jobject2reg(known_klass->constant_encoding(), tmp1);
2959 __ st_ptr(tmp1, recv_addr);
2960 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2961 mdo_offset_bias);
2962 __ ld_ptr(data_addr, tmp1);
2963 __ add(tmp1, DataLayout::counter_increment, tmp1);
2964 __ st_ptr(tmp1, data_addr);
2965 return;
2966 }
2967 }
2968 } else {
2969 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2970 Label update_done;
2971 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2972 // Receiver did not match any saved receiver and there is no empty row for it.
2973 // Increment total counter to indicate polymorphic case.
2974 __ ld_ptr(counter_addr, tmp1);
2975 __ add(tmp1, DataLayout::counter_increment, tmp1);
2976 __ st_ptr(tmp1, counter_addr);
2977
2978 __ bind(update_done);
2979 }
2980 } else {
2981 // Static call
2982 __ ld_ptr(counter_addr, tmp1);
2983 __ add(tmp1, DataLayout::counter_increment, tmp1);
2984 __ st_ptr(tmp1, counter_addr);
2985 }
2986 }
2987
2988 void LIR_Assembler::align_backward_branch_target() {
2989 __ align(OptoLoopAlignment);
3143 } else {
3144 if (idx == noreg) {
3145 __ ldd(base, disp, G4);
3146 } else {
3147 __ ldd(base, idx, G4);
3148 }
3149 // G4 is high half, G5 is low half
3150 __ mov (G4, dest->as_register_hi());
3151 __ mov (G5, dest->as_register_lo());
3152 }
3153 } else {
3154 Unimplemented();
3155 }
3156 if (info != NULL) {
3157 add_debug_info_for_null_check(null_check_offset, info);
3158 }
3159
3160 } else {
3161 // use normal move for all other volatiles since they don't need
3162 // special handling to remain atomic.
3163 move_op(src, dest, type, lir_patch_none, info, false, false);
3164 }
3165 }
3166
3167 void LIR_Assembler::membar() {
3168 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3169 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3170 }
3171
3172 void LIR_Assembler::membar_acquire() {
3173 // no-op on TSO
3174 }
3175
3176 void LIR_Assembler::membar_release() {
3177 // no-op on TSO
3178 }
3179
3180 // Pack two sequential registers containing 32 bit values
3181 // into a single 64 bit register.
3182 // src and src->successor() are packed into dst
3183 // src and dst may be the same register.
|
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (UseCompressedOops) {
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
106 }
107
108 if (dst->is_register()) {
109 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
110 return !PatchALot;
111 } else if (src->is_single_stack()) {
112 return true;
113 }
114 }
115
116 if (src->is_register()) {
117 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
118 return !PatchALot;
119 } else if (dst->is_single_stack()) {
120 return true;
121 }
122 }
123
124 if (dst->is_register() &&
125 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
126 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
127 return true;
241 Register str0 = left->as_register();
242 Register str1 = right->as_register();
243
244 Label Ldone;
245
246 Register result = dst->as_register();
247 {
248 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
249 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
250 // Also, get string0.count-string1.count in o7 and get the condition code set
251 // Note: some instructions have been hoisted for better instruction scheduling
252
253 Register tmp0 = L0;
254 Register tmp1 = L1;
255 Register tmp2 = L2;
256
257 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
258 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
259 int count_offset = java_lang_String:: count_offset_in_bytes();
260
261 __ load_heap_oop(str0, value_offset, tmp0);
262 __ ld(str0, offset_offset, tmp2);
263 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
264 __ ld(str0, count_offset, str0);
265 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
266
267 // str1 may be null
268 add_debug_info_for_null_check_here(info);
269
270 __ load_heap_oop(str1, value_offset, tmp1);
271 __ add(tmp0, tmp2, tmp0);
272
273 __ ld(str1, offset_offset, tmp2);
274 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
275 __ ld(str1, count_offset, str1);
276 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
277 __ subcc(str0, str1, O7);
278 __ add(tmp1, tmp2, tmp1);
279 }
280
281 {
282 // Compute the minimum of the string lengths, scale it and store it in limit
283 Register count0 = I0;
284 Register count1 = I1;
285 Register limit = L3;
286
287 Label Lskip;
288 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
289 __ br(Assembler::greater, true, Assembler::pt, Lskip);
290 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
754
755 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
756 __ call(op->addr(), rtype);
757 // The peephole pass fills the delay slot, add_call_info is done in
758 // LIR_Assembler::emit_delay.
759 }
760
761
762 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
763 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
764 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
765 __ relocate(rspec);
766 __ call(op->addr(), relocInfo::none);
767 // The peephole pass fills the delay slot, add_call_info is done in
768 // LIR_Assembler::emit_delay.
769 }
770
771
772 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
773 add_debug_info_for_null_check_here(op->info());
774 __ load_klass(O0, G3_scratch);
775 if (__ is_simm13(op->vtable_offset())) {
776 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
777 } else {
778 // This will generate 2 instructions
779 __ set(op->vtable_offset(), G5_method);
780 // ld_ptr, set_hi, set
781 __ ld_ptr(G3_scratch, G5_method, G5_method);
782 }
783 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
784 __ callr(G3_scratch, G0);
785 // the peephole pass fills the delay slot
786 }
787
788 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
789 int store_offset;
790 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
791 assert(!unaligned, "can't handle this");
792 // for offsets larger than a simm13 we setup the offset in O7
793 __ set(offset, O7);
794 store_offset = store(from_reg, base, O7, type, wide);
795 } else {
796 if (type == T_ARRAY || type == T_OBJECT) {
797 __ verify_oop(from_reg->as_register());
798 }
799 store_offset = code_offset();
800 switch (type) {
801 case T_BOOLEAN: // fall through
802 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
803 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
804 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
805 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
806 case T_LONG :
807 #ifdef _LP64
808 if (unaligned || PatchALot) {
809 __ srax(from_reg->as_register_lo(), 32, O7);
810 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
811 __ stw(O7, base, offset + hi_word_offset_in_bytes);
812 } else {
813 __ stx(from_reg->as_register_lo(), base, offset);
814 }
815 #else
816 assert(Assembler::is_simm13(offset + 4), "must be");
817 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
818 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
819 #endif
820 break;
821 case T_ADDRESS:
822 __ st_ptr(from_reg->as_register(), base, offset);
823 break;
824 case T_ARRAY : // fall through
825 case T_OBJECT:
826 {
827 if (UseCompressedOops && !wide) {
828 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
829 store_offset = code_offset();
830 __ stw(G3_scratch, base, offset);
831 } else {
832 __ st_ptr(from_reg->as_register(), base, offset);
833 }
834 break;
835 }
836
837 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
838 case T_DOUBLE:
839 {
840 FloatRegister reg = from_reg->as_double_reg();
841 // split unaligned stores
842 if (unaligned || PatchALot) {
843 assert(Assembler::is_simm13(offset + 4), "must be");
844 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
845 __ stf(FloatRegisterImpl::S, reg, base, offset);
846 } else {
847 __ stf(FloatRegisterImpl::D, reg, base, offset);
848 }
849 break;
850 }
851 default : ShouldNotReachHere();
852 }
853 }
854 return store_offset;
855 }
856
857
858 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
859 if (type == T_ARRAY || type == T_OBJECT) {
860 __ verify_oop(from_reg->as_register());
861 }
862 int store_offset = code_offset();
863 switch (type) {
864 case T_BOOLEAN: // fall through
865 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
866 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
867 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
868 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
869 case T_LONG :
870 #ifdef _LP64
871 __ stx(from_reg->as_register_lo(), base, disp);
872 #else
873 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
874 __ std(from_reg->as_register_hi(), base, disp);
875 #endif
876 break;
877 case T_ADDRESS:
878 __ st_ptr(from_reg->as_register(), base, disp);
879 break;
880 case T_ARRAY : // fall through
881 case T_OBJECT:
882 {
883 if (UseCompressedOops && !wide) {
884 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
885 store_offset = code_offset();
886 __ stw(G3_scratch, base, disp);
887 } else {
888 __ st_ptr(from_reg->as_register(), base, disp);
889 }
890 break;
891 }
892 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
893 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
894 default : ShouldNotReachHere();
895 }
896 return store_offset;
897 }
898
899
900 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
901 int load_offset;
902 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
903 assert(base != O7, "destroying register");
904 assert(!unaligned, "can't handle this");
905 // for offsets larger than a simm13 we setup the offset in O7
906 __ set(offset, O7);
907 load_offset = load(base, O7, to_reg, type, wide);
908 } else {
909 load_offset = code_offset();
910 switch(type) {
911 case T_BOOLEAN: // fall through
912 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
913 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
914 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
915 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
916 case T_LONG :
917 if (!unaligned) {
918 #ifdef _LP64
919 __ ldx(base, offset, to_reg->as_register_lo());
920 #else
921 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
922 "must be sequential");
923 __ ldd(base, offset, to_reg->as_register_hi());
924 #endif
925 } else {
926 #ifdef _LP64
927 assert(base != to_reg->as_register_lo(), "can't handle this");
928 assert(O7 != to_reg->as_register_lo(), "can't handle this");
929 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
930 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
931 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
932 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
933 #else
934 if (base == to_reg->as_register_lo()) {
935 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
936 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
937 } else {
938 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
939 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
940 }
941 #endif
942 }
943 break;
944 case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break;
945 case T_ARRAY : // fall through
946 case T_OBJECT:
947 {
948 if (UseCompressedOops && !wide) {
949 __ lduw(base, offset, to_reg->as_register());
950 __ decode_heap_oop(to_reg->as_register());
951 } else {
952 __ ld_ptr(base, offset, to_reg->as_register());
953 }
954 break;
955 }
956 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
957 case T_DOUBLE:
958 {
959 FloatRegister reg = to_reg->as_double_reg();
960 // split unaligned loads
961 if (unaligned || PatchALot) {
962 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
963 __ ldf(FloatRegisterImpl::S, base, offset, reg);
964 } else {
965 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
966 }
967 break;
968 }
969 default : ShouldNotReachHere();
970 }
971 if (type == T_ARRAY || type == T_OBJECT) {
972 __ verify_oop(to_reg->as_register());
973 }
974 }
975 return load_offset;
976 }
977
978
979 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
980 int load_offset = code_offset();
981 switch(type) {
982 case T_BOOLEAN: // fall through
983 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
984 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
985 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
986 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
987 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
988 case T_ARRAY : // fall through
989 case T_OBJECT:
990 {
991 if (UseCompressedOops && !wide) {
992 __ lduw(base, disp, to_reg->as_register());
993 __ decode_heap_oop(to_reg->as_register());
994 } else {
995 __ ld_ptr(base, disp, to_reg->as_register());
996 }
997 break;
998 }
999 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1000 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1001 case T_LONG :
1002 #ifdef _LP64
1003 __ ldx(base, disp, to_reg->as_register_lo());
1004 #else
1005 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1006 "must be sequential");
1007 __ ldd(base, disp, to_reg->as_register_hi());
1008 #endif
1009 break;
1010 default : ShouldNotReachHere();
1011 }
1012 if (type == T_ARRAY || type == T_OBJECT) {
1013 __ verify_oop(to_reg->as_register());
1014 }
1015 return load_offset;
1016 }
1017
1018 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1019 LIR_Const* c = src->as_constant_ptr();
1020 switch (c->type()) {
1021 case T_INT:
1022 case T_FLOAT: {
1023 Register src_reg = O7;
1024 int value = c->as_jint_bits();
1025 if (value == 0) {
1026 src_reg = G0;
1027 } else {
1028 __ set(value, O7);
1029 }
1030 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1031 __ stw(src_reg, addr.base(), addr.disp());
1032 break;
1033 }
1034 case T_ADDRESS: {
1035 Register src_reg = O7;
1036 int value = c->as_jint_bits();
1037 if (value == 0) {
1038 src_reg = G0;
1039 } else {
1040 __ set(value, O7);
1041 }
1042 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1043 __ st_ptr(src_reg, addr.base(), addr.disp());
1044 break;
1045 }
1046 case T_OBJECT: {
1047 Register src_reg = O7;
1048 jobject2reg(c->as_jobject(), src_reg);
1049 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1050 __ st_ptr(src_reg, addr.base(), addr.disp());
1051 break;
1052 }
1053 case T_LONG:
1054 case T_DOUBLE: {
1055 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1056
1057 Register tmp = O7;
1058 int value_lo = c->as_jint_lo_bits();
1059 if (value_lo == 0) {
1060 tmp = G0;
1061 } else {
1062 __ set(value_lo, O7);
1063 }
1064 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1065 int value_hi = c->as_jint_hi_bits();
1066 if (value_hi == 0) {
1067 tmp = G0;
1068 } else {
1069 __ set(value_hi, O7);
1070 }
1071 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1072 break;
1073 }
1074 default:
1075 Unimplemented();
1076 }
1077 }
1078
1079
1080 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1081 LIR_Const* c = src->as_constant_ptr();
1082 LIR_Address* addr = dest->as_address_ptr();
1083 Register base = addr->base()->as_pointer_register();
1084 int offset = -1;
1085
1086 switch (c->type()) {
1087 case T_INT:
1088 case T_FLOAT:
1089 case T_ADDRESS: {
1090 LIR_Opr tmp = FrameMap::O7_opr;
1091 int value = c->as_jint_bits();
1092 if (value == 0) {
1093 tmp = FrameMap::G0_opr;
1094 } else if (Assembler::is_simm13(value)) {
1095 __ set(value, O7);
1096 }
1097 if (addr->index()->is_valid()) {
1098 assert(addr->disp() == 0, "must be zero");
1099 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1100 } else {
1101 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1102 offset = store(tmp, base, addr->disp(), type, wide, false);
1103 }
1104 break;
1105 }
1106 case T_LONG:
1107 case T_DOUBLE: {
1108 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1109 assert(Assembler::is_simm13(addr->disp()) &&
1110 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1111
1112 LIR_Opr tmp = FrameMap::O7_opr;
1113 int value_lo = c->as_jint_lo_bits();
1114 if (value_lo == 0) {
1115 tmp = FrameMap::G0_opr;
1116 } else {
1117 __ set(value_lo, O7);
1118 }
1119 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1120 int value_hi = c->as_jint_hi_bits();
1121 if (value_hi == 0) {
1122 tmp = FrameMap::G0_opr;
1123 } else {
1124 __ set(value_hi, O7);
1125 }
1126 offset = store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1127 break;
1128 }
1129 case T_OBJECT: {
1130 jobject obj = c->as_jobject();
1131 LIR_Opr tmp;
1132 if (obj == NULL) {
1133 tmp = FrameMap::G0_opr;
1134 } else {
1135 tmp = FrameMap::O7_opr;
1136 jobject2reg(c->as_jobject(), O7);
1137 }
1138 // handle either reg+reg or reg+disp address
1139 if (addr->index()->is_valid()) {
1140 assert(addr->disp() == 0, "must be zero");
1141 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1142 } else {
1143 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1144 offset = store(tmp, base, addr->disp(), type, wide, false);
1145 }
1146
1147 break;
1148 }
1149 default:
1150 Unimplemented();
1151 }
1152 if (info != NULL) {
1153 assert(offset != -1, "offset should've been set");
1154 add_debug_info_for_null_check(offset, info);
1155 }
1156 }
1157
1158
1159 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1160 LIR_Const* c = src->as_constant_ptr();
1161 LIR_Opr to_reg = dest;
1162
1163 switch (c->type()) {
1164 case T_INT:
1165 case T_ADDRESS:
1166 {
1167 jint con = c->as_jint();
1168 if (to_reg->is_single_cpu()) {
1169 assert(patch_code == lir_patch_none, "no patching handled here");
1170 __ set(con, to_reg->as_register());
1171 } else {
1172 ShouldNotReachHere();
1173 assert(to_reg->is_single_fpu(), "wrong register kind");
1174
1175 __ set(con, O7);
1220 break;
1221
1222 case T_FLOAT:
1223 {
1224 address const_addr = __ float_constant(c->as_jfloat());
1225 if (const_addr == NULL) {
1226 bailout("const section overflow");
1227 break;
1228 }
1229 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1230 AddressLiteral const_addrlit(const_addr, rspec);
1231 if (to_reg->is_single_fpu()) {
1232 __ patchable_sethi(const_addrlit, O7);
1233 __ relocate(rspec);
1234 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1235
1236 } else {
1237 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1238
1239 __ set(const_addrlit, O7);
1240 __ ld(O7, 0, to_reg->as_register());
1241 }
1242 }
1243 break;
1244
1245 case T_DOUBLE:
1246 {
1247 address const_addr = __ double_constant(c->as_jdouble());
1248 if (const_addr == NULL) {
1249 bailout("const section overflow");
1250 break;
1251 }
1252 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1253
1254 if (to_reg->is_double_fpu()) {
1255 AddressLiteral const_addrlit(const_addr, rspec);
1256 __ patchable_sethi(const_addrlit, O7);
1257 __ relocate(rspec);
1258 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1259 } else {
1260 assert(to_reg->is_double_cpu(), "Must be a long register.");
1313
1314 default:
1315 ShouldNotReachHere();
1316 }
1317 }
1318
1319
1320 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1321 Address base = as_Address(addr);
1322 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1323 }
1324
1325
1326 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1327 Address base = as_Address(addr);
1328 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1329 }
1330
1331
1332 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1333 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1334
1335 LIR_Address* addr = src_opr->as_address_ptr();
1336 LIR_Opr to_reg = dest;
1337
1338 Register src = addr->base()->as_pointer_register();
1339 Register disp_reg = noreg;
1340 int disp_value = addr->disp();
1341 bool needs_patching = (patch_code != lir_patch_none);
1342
1343 if (addr->base()->type() == T_OBJECT) {
1344 __ verify_oop(src);
1345 }
1346
1347 PatchingStub* patch = NULL;
1348 if (needs_patching) {
1349 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1350 assert(!to_reg->is_double_cpu() ||
1351 patch_code == lir_patch_none ||
1352 patch_code == lir_patch_normal, "patching doesn't match register");
1353 }
1359 } else {
1360 __ set(disp_value, O7);
1361 }
1362 disp_reg = O7;
1363 }
1364 } else if (unaligned || PatchALot) {
1365 __ add(src, addr->index()->as_register(), O7);
1366 src = O7;
1367 } else {
1368 disp_reg = addr->index()->as_pointer_register();
1369 assert(disp_value == 0, "can't handle 3 operand addresses");
1370 }
1371
1372 // remember the offset of the load. The patching_epilog must be done
1373 // before the call to add_debug_info, otherwise the PcDescs don't get
1374 // entered in increasing order.
1375 int offset = code_offset();
1376
1377 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1378 if (disp_reg == noreg) {
1379 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1380 } else {
1381 assert(!unaligned, "can't handle this");
1382 offset = load(src, disp_reg, to_reg, type, wide);
1383 }
1384
1385 if (patch != NULL) {
1386 patching_epilog(patch, patch_code, src, info);
1387 }
1388 if (info != NULL) add_debug_info_for_null_check(offset, info);
1389 }
1390
1391
1392 void LIR_Assembler::prefetchr(LIR_Opr src) {
1393 LIR_Address* addr = src->as_address_ptr();
1394 Address from_addr = as_Address(addr);
1395
1396 if (VM_Version::has_v9()) {
1397 __ prefetch(from_addr, Assembler::severalReads);
1398 }
1399 }
1400
1401
1402 void LIR_Assembler::prefetchw(LIR_Opr src) {
1403 LIR_Address* addr = src->as_address_ptr();
1404 Address from_addr = as_Address(addr);
1405
1406 if (VM_Version::has_v9()) {
1407 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1408 }
1409 }
1410
1411
1412 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1413 Address addr;
1414 if (src->is_single_word()) {
1415 addr = frame_map()->address_for_slot(src->single_stack_ix());
1416 } else if (src->is_double_word()) {
1417 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1418 }
1419
1420 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1421 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1422 }
1423
1424
1425 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1426 Address addr;
1427 if (dest->is_single_word()) {
1428 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1429 } else if (dest->is_double_word()) {
1430 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1431 }
1432 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1433 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1434 }
1435
1436
1437 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1438 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1439 if (from_reg->is_double_fpu()) {
1440 // double to double moves
1441 assert(to_reg->is_double_fpu(), "should match");
1442 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1443 } else {
1444 // float to float moves
1445 assert(to_reg->is_single_fpu(), "should match");
1446 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1447 }
1448 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1449 if (from_reg->is_double_cpu()) {
1450 #ifdef _LP64
1451 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1452 #else
1453 assert(to_reg->is_double_cpu() &&
1461 #ifdef _LP64
1462 } else if (to_reg->is_double_cpu()) {
1463 // int to int moves
1464 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1465 #endif
1466 } else {
1467 // int to int moves
1468 __ mov(from_reg->as_register(), to_reg->as_register());
1469 }
1470 } else {
1471 ShouldNotReachHere();
1472 }
1473 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1474 __ verify_oop(to_reg->as_register());
1475 }
1476 }
1477
1478
1479 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1480 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1481 bool wide, bool unaligned) {
1482 LIR_Address* addr = dest->as_address_ptr();
1483
1484 Register src = addr->base()->as_pointer_register();
1485 Register disp_reg = noreg;
1486 int disp_value = addr->disp();
1487 bool needs_patching = (patch_code != lir_patch_none);
1488
1489 if (addr->base()->is_oop_register()) {
1490 __ verify_oop(src);
1491 }
1492
1493 PatchingStub* patch = NULL;
1494 if (needs_patching) {
1495 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1496 assert(!from_reg->is_double_cpu() ||
1497 patch_code == lir_patch_none ||
1498 patch_code == lir_patch_normal, "patching doesn't match register");
1499 }
1500
1501 if (addr->index()->is_illegal()) {
1505 } else {
1506 __ set(disp_value, O7);
1507 }
1508 disp_reg = O7;
1509 }
1510 } else if (unaligned || PatchALot) {
1511 __ add(src, addr->index()->as_register(), O7);
1512 src = O7;
1513 } else {
1514 disp_reg = addr->index()->as_pointer_register();
1515 assert(disp_value == 0, "can't handle 3 operand addresses");
1516 }
1517
1518 // remember the offset of the store. The patching_epilog must be done
1519 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1520 // entered in increasing order.
1521 int offset;
1522
1523 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1524 if (disp_reg == noreg) {
1525 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1526 } else {
1527 assert(!unaligned, "can't handle this");
1528 offset = store(from_reg, src, disp_reg, type, wide);
1529 }
1530
1531 if (patch != NULL) {
1532 patching_epilog(patch, patch_code, src, info);
1533 }
1534
1535 if (info != NULL) add_debug_info_for_null_check(offset, info);
1536 }
1537
1538
1539 void LIR_Assembler::return_op(LIR_Opr result) {
1540 // the poll may need a register so just pick one that isn't the return register
1541 #if defined(TIERED) && !defined(_LP64)
1542 if (result->type_field() == LIR_OprDesc::long_type) {
1543 // Must move the result to G1
1544 // Must leave proper result in O0,O1 and G1 (TIERED only)
1545 __ sllx(I0, 32, G1); // Shift bits into high G1
1546 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1547 __ or3 (I1, G1, G1); // OR 64 bits into G1
1548 #ifdef ASSERT
2067 if (op->expected_type() == NULL ||
2068 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2069 __ mov(src, O0);
2070 __ mov(src_pos, O1);
2071 __ mov(dst, O2);
2072 __ mov(dst_pos, O3);
2073 __ mov(length, O4);
2074 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2075
2076 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2077 __ delayed()->nop();
2078 __ bind(*stub->continuation());
2079 return;
2080 }
2081
2082 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2083
2084 // make sure src and dst are non-null and load array length
2085 if (flags & LIR_OpArrayCopy::src_null_check) {
2086 __ tst(src);
2087 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2088 __ delayed()->nop();
2089 }
2090
2091 if (flags & LIR_OpArrayCopy::dst_null_check) {
2092 __ tst(dst);
2093 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2094 __ delayed()->nop();
2095 }
2096
2097 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2098 // test src_pos register
2099 __ tst(src_pos);
2100 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2101 __ delayed()->nop();
2102 }
2103
2104 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2105 // test dst_pos register
2106 __ tst(dst_pos);
2107 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2108 __ delayed()->nop();
2109 }
2110
2111 if (flags & LIR_OpArrayCopy::length_positive_check) {
2112 // make sure length isn't negative
2113 __ tst(length);
2115 __ delayed()->nop();
2116 }
2117
2118 if (flags & LIR_OpArrayCopy::src_range_check) {
2119 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2120 __ add(length, src_pos, tmp);
2121 __ cmp(tmp2, tmp);
2122 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2123 __ delayed()->nop();
2124 }
2125
2126 if (flags & LIR_OpArrayCopy::dst_range_check) {
2127 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2128 __ add(length, dst_pos, tmp);
2129 __ cmp(tmp2, tmp);
2130 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2131 __ delayed()->nop();
2132 }
2133
2134 if (flags & LIR_OpArrayCopy::type_check) {
2135 if (UseCompressedOops) {
2136 // We don't need decode because we just need to compare
2137 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
2138 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2139 } else {
2140 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2141 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2142 }
2143 __ cmp(tmp, tmp2);
2144 __ br(Assembler::notEqual, Assembler::heap_oop_cc(), false, Assembler::pt, *stub->entry());
2145 __ delayed()->nop();
2146 }
2147
2148 #ifdef ASSERT
2149 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2150 // Sanity check the known type with the incoming class. For the
2151 // primitive case the types must match exactly with src.klass and
2152 // dst.klass each exactly matching the default type. For the
2153 // object array case, if no type check is needed then either the
2154 // dst type is exactly the expected type and the src type is a
2155 // subtype which we can't check or src is the same array as dst
2156 // but not necessarily exactly of type default_type.
2157 Label known_ok, halt;
2158 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2159 if (UseCompressedOops) {
2160 // tmp holds the default type. It currently comes uncompressed after the
2161 // load of a constant, so encode it.
2162 __ encode_heap_oop(tmp);
2163 // load the raw value of the dst klass, since we will be comparing
2164 // uncompressed values directly.
2165 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2166 } else {
2167 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2168 }
2169 if (basic_type != T_OBJECT) {
2170 __ cmp(tmp, tmp2);
2171 __ br(Assembler::notEqual, Assembler::heap_oop_cc(), false, Assembler::pn, halt);
2172 if (UseCompressedOops) {
2173 // load the raw value of the src klass.
2174 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2175 } else {
2176 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2177 }
2178 __ cmp(tmp, tmp2);
2179 __ br(Assembler::equal, Assembler::heap_oop_cc(), false, Assembler::pn, known_ok);
2180 __ delayed()->nop();
2181 } else {
2182 __ cmp(tmp, tmp2);
2183 __ br(Assembler::equal, Assembler::heap_oop_cc(), false, Assembler::pn, known_ok);
2184 __ delayed()->cmp(src, dst);
2185 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2186 __ delayed()->nop();
2187 }
2188 __ bind(halt);
2189 __ stop("incorrect type information in arraycopy");
2190 __ bind(known_ok);
2191 }
2192 #endif
2193
2194 int shift = shift_amount(basic_type);
2195
2196 Register src_ptr = O0;
2197 Register dst_ptr = O1;
2198 Register len = O2;
2199
2200 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2201 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2202 if (shift == 0) {
2203 __ add(src_ptr, src_pos, src_ptr);
2204 } else {
2205 __ sll(src_pos, shift, tmp);
2374 __ ld_ptr(receiver_addr, tmp1);
2375 __ verify_oop(tmp1);
2376 __ cmp(recv, tmp1);
2377 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2378 __ delayed()->nop();
2379 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2380 mdo_offset_bias);
2381 __ ld_ptr(data_addr, tmp1);
2382 __ add(tmp1, DataLayout::counter_increment, tmp1);
2383 __ st_ptr(tmp1, data_addr);
2384 __ ba(false, *update_done);
2385 __ delayed()->nop();
2386 __ bind(next_test);
2387 }
2388
2389 // Didn't find receiver; find next empty slot and fill it in
2390 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2391 Label next_test;
2392 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2393 mdo_offset_bias);
2394 __ ld_ptr(recv_addr, tmp1);
2395 __ br_notnull(tmp1, false, Assembler::pt, next_test);
2396 __ delayed()->nop();
2397 __ st_ptr(recv, recv_addr);
2398 __ set(DataLayout::counter_increment, tmp1);
2399 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2400 mdo_offset_bias);
2401 __ ba(false, *update_done);
2402 __ delayed()->nop();
2403 __ bind(next_test);
2404 }
2405 }
2406
2407
2408 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2409 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2410 md = method->method_data();
2411 if (md == NULL) {
2412 bailout("out of memory building methodDataOop");
2413 return;
2414 }
2466 } else {
2467 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2468 __ delayed()->nop();
2469 }
2470
2471 Label profile_cast_failure, profile_cast_success;
2472 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2473 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2474
2475 // patching may screw with our temporaries on sparc,
2476 // so let's do it before loading the class
2477 if (k->is_loaded()) {
2478 jobject2reg(k->constant_encoding(), k_RInfo);
2479 } else {
2480 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2481 }
2482 assert(obj != k_RInfo, "must be different");
2483
2484 // get object class
2485 // not a safepoint as obj null check happens earlier
2486 __ load_klass(obj, klass_RInfo);
2487 if (op->fast_check()) {
2488 assert_different_registers(klass_RInfo, k_RInfo);
2489 __ cmp(k_RInfo, klass_RInfo);
2490 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2491 __ delayed()->nop();
2492 } else {
2493 bool need_slow_path = true;
2494 if (k->is_loaded()) {
2495 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2496 need_slow_path = false;
2497 // perform the fast part of the checking logic
2498 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2499 (need_slow_path ? success_target : NULL),
2500 failure_target, NULL,
2501 RegisterOrConstant(k->super_check_offset()));
2502 } else {
2503 // perform the fast part of the checking logic
2504 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2505 failure_target, NULL);
2506 }
2508 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2509 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2510 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2511 __ delayed()->nop();
2512 __ cmp(G3, 0);
2513 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2514 __ delayed()->nop();
2515 // Fall through to success case
2516 }
2517 }
2518
2519 if (op->should_profile()) {
2520 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2521 assert_different_registers(obj, mdo, recv, tmp1);
2522 __ bind(profile_cast_success);
2523 jobject2reg(md->constant_encoding(), mdo);
2524 if (mdo_offset_bias > 0) {
2525 __ set(mdo_offset_bias, tmp1);
2526 __ add(mdo, tmp1, mdo);
2527 }
2528 __ load_klass(obj, recv);
2529 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2530 // Jump over the failure case
2531 __ ba(false, *success);
2532 __ delayed()->nop();
2533 // Cast failure case
2534 __ bind(profile_cast_failure);
2535 jobject2reg(md->constant_encoding(), mdo);
2536 if (mdo_offset_bias > 0) {
2537 __ set(mdo_offset_bias, tmp1);
2538 __ add(mdo, tmp1, mdo);
2539 }
2540 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2541 __ ld_ptr(data_addr, tmp1);
2542 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2543 __ st_ptr(tmp1, data_addr);
2544 __ ba(false, *failure);
2545 __ delayed()->nop();
2546 }
2547 __ ba(false, *success);
2548 __ delayed()->nop();
2577 __ br_notnull(value, false, Assembler::pn, not_null);
2578 __ delayed()->nop();
2579 Register mdo = k_RInfo;
2580 Register data_val = Rtmp1;
2581 jobject2reg(md->constant_encoding(), mdo);
2582 if (mdo_offset_bias > 0) {
2583 __ set(mdo_offset_bias, data_val);
2584 __ add(mdo, data_val, mdo);
2585 }
2586 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2587 __ ldub(flags_addr, data_val);
2588 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2589 __ stb(data_val, flags_addr);
2590 __ ba(false, done);
2591 __ delayed()->nop();
2592 __ bind(not_null);
2593 } else {
2594 __ br_null(value, false, Assembler::pn, done);
2595 __ delayed()->nop();
2596 }
2597 add_debug_info_for_null_check_here(op->info_for_exception());
2598 __ load_klass(array, k_RInfo);
2599 __ load_klass(value, klass_RInfo);
2600
2601 // get instance klass
2602 __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)), k_RInfo);
2603 // perform the fast part of the checking logic
2604 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2605
2606 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2607 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2608 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2609 __ delayed()->nop();
2610 __ cmp(G3, 0);
2611 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2612 __ delayed()->nop();
2613 // fall through to the success case
2614
2615 if (op->should_profile()) {
2616 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2617 assert_different_registers(value, mdo, recv, tmp1);
2618 __ bind(profile_cast_success);
2619 jobject2reg(md->constant_encoding(), mdo);
2620 if (mdo_offset_bias > 0) {
2621 __ set(mdo_offset_bias, tmp1);
2622 __ add(mdo, tmp1, mdo);
2623 }
2624 __ load_klass(value, recv);
2625 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2626 __ ba(false, done);
2627 __ delayed()->nop();
2628 // Cast failure case
2629 __ bind(profile_cast_failure);
2630 jobject2reg(md->constant_encoding(), mdo);
2631 if (mdo_offset_bias > 0) {
2632 __ set(mdo_offset_bias, tmp1);
2633 __ add(mdo, tmp1, mdo);
2634 }
2635 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2636 __ ld_ptr(data_addr, tmp1);
2637 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2638 __ st_ptr(tmp1, data_addr);
2639 __ ba(false, *stub->entry());
2640 __ delayed()->nop();
2641 }
2642 __ bind(done);
2643 } else if (code == lir_checkcast) {
2644 Register obj = op->object()->as_register();
2685 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2686 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2687 __ sllx(new_value_hi, 32, t2);
2688 __ srl(new_value_lo, 0, new_value_lo);
2689 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2690 #endif
2691 // perform the compare and swap operation
2692 __ casx(addr, t1, t2);
2693 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2694 // overwritten with the original value in "addr" and will be equal to t1.
2695 __ cmp(t1, t2);
2696
2697 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2698 Register addr = op->addr()->as_pointer_register();
2699 Register cmp_value = op->cmp_value()->as_register();
2700 Register new_value = op->new_value()->as_register();
2701 Register t1 = op->tmp1()->as_register();
2702 Register t2 = op->tmp2()->as_register();
2703 __ mov(cmp_value, t1);
2704 __ mov(new_value, t2);
2705 if (op->code() == lir_cas_obj) {
2706 if (UseCompressedOops) {
2707 __ encode_heap_oop(t1);
2708 __ encode_heap_oop(t2);
2709 __ cas(addr, t1, t2);
2710 } else {
2711 __ casx(addr, t1, t2);
2712 }
2713 } else {
2714 __ cas(addr, t1, t2);
2715 }
2716 __ cmp(t1, t2);
2717 } else {
2718 Unimplemented();
2719 }
2720 }
2721
2722 void LIR_Assembler::set_24bit_FPU() {
2723 Unimplemented();
2724 }
2725
2726
2727 void LIR_Assembler::reset_FPU() {
2728 Unimplemented();
2729 }
2730
2731
2732 void LIR_Assembler::breakpoint() {
2733 __ breakpoint_trap();
2873
2874 // Note that this is less efficient than it should be because it
2875 // always does a write to the receiver part of the
2876 // VirtualCallData rather than just the first time
2877 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2878 ciKlass* receiver = vc_data->receiver(i);
2879 if (receiver == NULL) {
2880 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2881 mdo_offset_bias);
2882 jobject2reg(known_klass->constant_encoding(), tmp1);
2883 __ st_ptr(tmp1, recv_addr);
2884 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2885 mdo_offset_bias);
2886 __ ld_ptr(data_addr, tmp1);
2887 __ add(tmp1, DataLayout::counter_increment, tmp1);
2888 __ st_ptr(tmp1, data_addr);
2889 return;
2890 }
2891 }
2892 } else {
2893 __ load_klass(recv, recv);
2894 Label update_done;
2895 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2896 // Receiver did not match any saved receiver and there is no empty row for it.
2897 // Increment total counter to indicate polymorphic case.
2898 __ ld_ptr(counter_addr, tmp1);
2899 __ add(tmp1, DataLayout::counter_increment, tmp1);
2900 __ st_ptr(tmp1, counter_addr);
2901
2902 __ bind(update_done);
2903 }
2904 } else {
2905 // Static call
2906 __ ld_ptr(counter_addr, tmp1);
2907 __ add(tmp1, DataLayout::counter_increment, tmp1);
2908 __ st_ptr(tmp1, counter_addr);
2909 }
2910 }
2911
2912 void LIR_Assembler::align_backward_branch_target() {
2913 __ align(OptoLoopAlignment);
3067 } else {
3068 if (idx == noreg) {
3069 __ ldd(base, disp, G4);
3070 } else {
3071 __ ldd(base, idx, G4);
3072 }
3073 // G4 is high half, G5 is low half
3074 __ mov (G4, dest->as_register_hi());
3075 __ mov (G5, dest->as_register_lo());
3076 }
3077 } else {
3078 Unimplemented();
3079 }
3080 if (info != NULL) {
3081 add_debug_info_for_null_check(null_check_offset, info);
3082 }
3083
3084 } else {
3085 // use normal move for all other volatiles since they don't need
3086 // special handling to remain atomic.
3087 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3088 }
3089 }
3090
3091 void LIR_Assembler::membar() {
3092 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3093 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3094 }
3095
3096 void LIR_Assembler::membar_acquire() {
3097 // no-op on TSO
3098 }
3099
3100 void LIR_Assembler::membar_release() {
3101 // no-op on TSO
3102 }
3103
3104 // Pack two sequential registers containing 32 bit values
3105 // into a single 64 bit register.
3106 // src and src->successor() are packed into dst
3107 // src and dst may be the same register.
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