src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp
Index Unified diffs Context diffs Sdiffs Patch New Old Previous File Next File c1-coops Sdiff src/cpu/sparc/vm

src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp

Print this page




  23  */
  24 
  25 #ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
  27 
  28  private:
  29 
  30   //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  31   //
  32   // Sparc load/store emission
  33   //
  34   // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
  35   // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
  36   // by allowing 32 bit displacements:
  37   //
  38   //    When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
  39   //    When disp >  13 bits long, code is emitted to set the displacement into the O7 register,
  40   //       and then a load or store is emitted with ([O7] + [d]).
  41   //
  42 
  43   // some load/store variants return the code_offset for proper positioning of debug info for null checks

  44 
  45   // load/store with 32 bit displacement
  46   int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
  47   void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);
  48 
  49   // loadf/storef with 32 bit displacement
  50   void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
  51   void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);
  52 
  53   // convienence methods for calling load/store with an Address
  54   void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
  55   void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
  56   void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
  57   void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
  58 
  59   // convienence methods for calling load/store with an LIR_Address
  60   void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
  61   void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
  62   void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
  63   void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
  64 
  65   int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
  66   int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);
  67 
  68   int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
  69   int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);
  70 
  71   void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
  72 
  73   int shift_amount(BasicType t);
  74 
  75   static bool is_single_instruction(LIR_Op* op);
  76 
  77   // Record the type of the receiver in ReceiverTypeData
  78   void type_profile_helper(Register mdo, int mdo_offset_bias,
  79                            ciMethodData *md, ciProfileData *data,
  80                            Register recv, Register tmp1, Label* update_done);
  81   // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
  82   void setup_md_access(ciMethod* method, int bci,
  83                        ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
  84  public:
  85   void   pack64(LIR_Opr src, LIR_Opr dst);
  86   void unpack64(LIR_Opr src, LIR_Opr dst);
  87 
  88 enum {
  89 #ifdef _LP64


  23  */
  24 
  25 #ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
  27 
  28  private:
  29 
  30   //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  31   //
  32   // Sparc load/store emission
  33   //
  34   // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
  35   // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
  36   // by allowing 32 bit displacements:
  37   //
  38   //    When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
  39   //    When disp >  13 bits long, code is emitted to set the displacement into the O7 register,
  40   //       and then a load or store is emitted with ([O7] + [d]).
  41   //
  42 
  43   int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);
  44   int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);
  45 
  46   int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);
  47   int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);























  48 
  49   void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
  50 
  51   int shift_amount(BasicType t);
  52 
  53   static bool is_single_instruction(LIR_Op* op);
  54 
  55   // Record the type of the receiver in ReceiverTypeData
  56   void type_profile_helper(Register mdo, int mdo_offset_bias,
  57                            ciMethodData *md, ciProfileData *data,
  58                            Register recv, Register tmp1, Label* update_done);
  59   // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
  60   void setup_md_access(ciMethod* method, int bci,
  61                        ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
  62  public:
  63   void   pack64(LIR_Opr src, LIR_Opr dst);
  64   void unpack64(LIR_Opr src, LIR_Opr dst);
  65 
  66 enum {
  67 #ifdef _LP64
src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp
Index Unified diffs Context diffs Sdiffs Patch New Old Previous File Next File