141 142 void FrameMap::initialize() { 143 assert(!_init_done, "once"); 144 145 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers"); 146 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); 147 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); 148 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); 149 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); 150 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); 151 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); 152 153 #ifndef _LP64 154 // The unallocatable registers are at the end 155 map_register(6, rsp); 156 map_register(7, rbp); 157 #else 158 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6); 159 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7); 160 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8); 161 map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9); 162 map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10); 163 map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11); 164 // The unallocatable registers are at the end 165 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12); 166 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13); 167 map_register(14, rsp); 168 map_register(15, rbp); 169 #endif // _LP64 170 171 #ifdef _LP64 172 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/); 173 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/); 174 #else 175 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/); 176 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/); 177 #endif // _LP64 178 fpu0_float_opr = LIR_OprFact::single_fpu(0); 179 fpu0_double_opr = LIR_OprFact::double_fpu(0); 180 xmm0_float_opr = LIR_OprFact::single_xmm(0); 181 xmm0_double_opr = LIR_OprFact::double_xmm(0); 182 183 _caller_save_cpu_regs[0] = rsi_opr; 184 _caller_save_cpu_regs[1] = rdi_opr; 185 _caller_save_cpu_regs[2] = rbx_opr; 186 _caller_save_cpu_regs[3] = rax_opr; 187 _caller_save_cpu_regs[4] = rdx_opr; 188 _caller_save_cpu_regs[5] = rcx_opr; 189 190 #ifdef _LP64 191 _caller_save_cpu_regs[6] = r8_opr; 192 _caller_save_cpu_regs[7] = r9_opr; 193 _caller_save_cpu_regs[8] = r11_opr; 194 _caller_save_cpu_regs[9] = r12_opr; 195 _caller_save_cpu_regs[10] = r13_opr; 196 _caller_save_cpu_regs[11] = r14_opr; 197 #endif // _LP64 198 199 200 _xmm_regs[0] = xmm0; 201 _xmm_regs[1] = xmm1; 202 _xmm_regs[2] = xmm2; 203 _xmm_regs[3] = xmm3; 204 _xmm_regs[4] = xmm4; 205 _xmm_regs[5] = xmm5; 206 _xmm_regs[6] = xmm6; 207 _xmm_regs[7] = xmm7; 208 209 #ifdef _LP64 210 _xmm_regs[8] = xmm8; 211 _xmm_regs[9] = xmm9; 212 _xmm_regs[10] = xmm10; 213 _xmm_regs[11] = xmm11; 214 _xmm_regs[12] = xmm12; 215 _xmm_regs[13] = xmm13; 216 _xmm_regs[14] = xmm14; | 141 142 void FrameMap::initialize() { 143 assert(!_init_done, "once"); 144 145 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers"); 146 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); 147 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); 148 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); 149 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); 150 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); 151 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); 152 153 #ifndef _LP64 154 // The unallocatable registers are at the end 155 map_register(6, rsp); 156 map_register(7, rbp); 157 #else 158 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6); 159 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7); 160 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8); 161 map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9); 162 map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10); 163 // r12 is allocated conditionally. With compressed oops it holds 164 // the heapbase value and is not visible to the allocator. 165 map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11); 166 // The unallocatable registers are at the end 167 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12); 168 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13); 169 map_register(14, rsp); 170 map_register(15, rbp); 171 #endif // _LP64 172 173 #ifdef _LP64 174 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/); 175 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/); 176 #else 177 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/); 178 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/); 179 #endif // _LP64 180 fpu0_float_opr = LIR_OprFact::single_fpu(0); 181 fpu0_double_opr = LIR_OprFact::double_fpu(0); 182 xmm0_float_opr = LIR_OprFact::single_xmm(0); 183 xmm0_double_opr = LIR_OprFact::double_xmm(0); 184 185 _caller_save_cpu_regs[0] = rsi_opr; 186 _caller_save_cpu_regs[1] = rdi_opr; 187 _caller_save_cpu_regs[2] = rbx_opr; 188 _caller_save_cpu_regs[3] = rax_opr; 189 _caller_save_cpu_regs[4] = rdx_opr; 190 _caller_save_cpu_regs[5] = rcx_opr; 191 192 #ifdef _LP64 193 _caller_save_cpu_regs[6] = r8_opr; 194 _caller_save_cpu_regs[7] = r9_opr; 195 _caller_save_cpu_regs[8] = r11_opr; 196 _caller_save_cpu_regs[9] = r13_opr; 197 _caller_save_cpu_regs[10] = r14_opr; 198 _caller_save_cpu_regs[11] = r12_opr; 199 #endif // _LP64 200 201 202 _xmm_regs[0] = xmm0; 203 _xmm_regs[1] = xmm1; 204 _xmm_regs[2] = xmm2; 205 _xmm_regs[3] = xmm3; 206 _xmm_regs[4] = xmm4; 207 _xmm_regs[5] = xmm5; 208 _xmm_regs[6] = xmm6; 209 _xmm_regs[7] = xmm7; 210 211 #ifdef _LP64 212 _xmm_regs[8] = xmm8; 213 _xmm_regs[9] = xmm9; 214 _xmm_regs[10] = xmm10; 215 _xmm_regs[11] = xmm11; 216 _xmm_regs[12] = xmm12; 217 _xmm_regs[13] = xmm13; 218 _xmm_regs[14] = xmm14; |