1 /*
   2  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_C1_FRAMEMAP_X86_HPP
  26 #define CPU_X86_VM_C1_FRAMEMAP_X86_HPP
  27 
  28 //  On i486 the frame looks as follows:
  29 //
  30 //  +-----------------------------+---------+----------------------------------------+----------------+-----------
  31 //  | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
  32 //  +-----------------------------+---------+----------------------------------------+----------------+-----------
  33 //
  34 //  The FPU registers are mapped with their offset from TOS; therefore the
  35 //  status of FPU stack must be updated during code emission.
  36 
  37  public:
  38   static const int pd_c_runtime_reserved_arg_size;
  39 
  40   enum {
  41     nof_xmm_regs = pd_nof_xmm_regs_frame_map,
  42     nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
  43     first_available_sp_in_frame = 0,
  44 #ifndef _LP64
  45     frame_pad_in_bytes = 8,
  46     nof_reg_args = 2
  47 #else
  48     frame_pad_in_bytes = 16,
  49     nof_reg_args = 6
  50 #endif // _LP64
  51   };
  52 
  53  private:
  54   static LIR_Opr      _caller_save_xmm_regs [nof_caller_save_xmm_regs];
  55 
  56   static XMMRegister _xmm_regs[nof_xmm_regs];
  57 
  58  public:
  59   static LIR_Opr receiver_opr;
  60 
  61   static LIR_Opr rsi_opr;
  62   static LIR_Opr rdi_opr;
  63   static LIR_Opr rbx_opr;
  64   static LIR_Opr rax_opr;
  65   static LIR_Opr rdx_opr;
  66   static LIR_Opr rcx_opr;
  67   static LIR_Opr rsp_opr;
  68   static LIR_Opr rbp_opr;
  69 
  70   static LIR_Opr rsi_oop_opr;
  71   static LIR_Opr rdi_oop_opr;
  72   static LIR_Opr rbx_oop_opr;
  73   static LIR_Opr rax_oop_opr;
  74   static LIR_Opr rdx_oop_opr;
  75   static LIR_Opr rcx_oop_opr;
  76 #ifdef _LP64
  77 
  78   static LIR_Opr  r8_opr;
  79   static LIR_Opr  r9_opr;
  80   static LIR_Opr r10_opr;
  81   static LIR_Opr r11_opr;
  82   static LIR_Opr r12_opr;
  83   static LIR_Opr r13_opr;
  84   static LIR_Opr r14_opr;
  85   static LIR_Opr r15_opr;
  86 
  87   static LIR_Opr  r8_oop_opr;
  88   static LIR_Opr  r9_oop_opr;
  89 
  90   static LIR_Opr r11_oop_opr;
  91   static LIR_Opr r12_oop_opr;
  92   static LIR_Opr r13_oop_opr;
  93   static LIR_Opr r14_oop_opr;
  94 
  95 #endif // _LP64
  96 
  97   static LIR_Opr long0_opr;
  98   static LIR_Opr long1_opr;
  99   static LIR_Opr fpu0_float_opr;
 100   static LIR_Opr fpu0_double_opr;
 101   static LIR_Opr xmm0_float_opr;
 102   static LIR_Opr xmm0_double_opr;
 103 
 104 #ifdef _LP64
 105   static LIR_Opr as_long_opr(Register r) {
 106     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
 107   }
 108   static LIR_Opr as_pointer_opr(Register r) {
 109     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
 110   }
 111 #else
 112   static LIR_Opr as_long_opr(Register r, Register r2) {
 113     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
 114   }
 115   static LIR_Opr as_pointer_opr(Register r) {
 116     return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
 117   }
 118 #endif // _LP64
 119 
 120   // VMReg name for spilled physical FPU stack slot n
 121   static VMReg fpu_regname (int n);
 122 
 123   static XMMRegister nr2xmmreg(int rnr);
 124 
 125   static bool is_caller_save_register (LIR_Opr opr) { return true; }
 126   static bool is_caller_save_register (Register r) { return true; }
 127 
 128   static LIR_Opr caller_save_xmm_reg_at(int i) {
 129     assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
 130     return _caller_save_xmm_regs[i];
 131   }
 132 
 133   static int adjust_reg_range(int range) {
 134     // Reduce the number of available regs (to free r12) in case of compressed oops
 135     if (UseCompressedOops) return range - 1;
 136     return range;
 137   }
 138 
 139   static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); }
 140   static int last_cpu_reg()             { return adjust_reg_range(pd_last_cpu_reg);  }
 141   static int last_byte_reg()            { return adjust_reg_range(pd_last_byte_reg); }
 142 
 143 #endif // CPU_X86_VM_C1_FRAMEMAP_X86_HPP
 144