src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp

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 326         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 327         __ jcc(Assembler::notZero, L);
 328         __ stop("locked object is NULL");
 329         __ bind(L);
 330       }
 331 #endif
 332       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 333       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 334       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 335       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 336     }
 337   }
 338 }
 339 
 340 
 341 // inline cache check; done before the frame is built.
 342 int LIR_Assembler::check_icache() {
 343   Register receiver = FrameMap::receiver_opr->as_register();
 344   Register ic_klass = IC_Klass;
 345   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 346 
 347   if (!VerifyOops) {
 348     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 349     while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
 350       __ nop();
 351     }
 352   }
 353   int offset = __ offset();
 354   __ inline_cache_check(receiver, IC_Klass);
 355   assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
 356   if (VerifyOops) {
 357     // force alignment after the cache check.
 358     // It's been verified to be aligned if !VerifyOops
 359     __ align(CodeEntryAlignment);
 360   }
 361   return offset;
 362 }
 363 
 364 
 365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 366   jobject o = NULL;
 367   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 368   __ movoop(reg, o);
 369   patching_epilog(patch, lir_patch_normal, reg, info);
 370 }
 371 
 372 
 373 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
 374   if (exception->is_valid()) {
 375     // preserve exception
 376     // note: the monitor_exit runtime call is a leaf routine


 542   int offset = code_offset();
 543   InternalAddress here(__ pc());
 544 
 545   __ pushptr(here.addr());
 546   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 547 
 548   assert(code_offset() - offset <= deopt_handler_size, "overflow");
 549   __ end_a_stub();
 550 
 551   return offset;
 552 }
 553 
 554 
 555 // This is the fast version of java.lang.String.compare; it has not
 556 // OSR-entry and therefore, we generate a slow version for OSR's
 557 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
 558   __ movptr (rbx, rcx); // receiver is in rcx
 559   __ movptr (rax, arg1->as_register());
 560 
 561   // Get addresses of first characters from both Strings
 562   __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
 563   __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
 564   __ lea    (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 565 
 566 
 567   // rbx, may be NULL
 568   add_debug_info_for_null_check_here(info);
 569   __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
 570   __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
 571   __ lea    (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 572 
 573   // compute minimum length (in rax) and difference of lengths (on top of stack)
 574   if (VM_Version::supports_cmov()) {
 575     __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 576     __ movl     (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
 577     __ mov      (rcx, rbx);
 578     __ subptr   (rbx, rax); // subtract lengths
 579     __ push     (rbx);      // result
 580     __ cmov     (Assembler::lessEqual, rax, rcx);
 581   } else {
 582     Label L;
 583     __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 584     __ movl     (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
 585     __ mov      (rax, rbx);
 586     __ subptr   (rbx, rcx);
 587     __ push     (rbx);
 588     __ jcc      (Assembler::lessEqual, L);
 589     __ mov      (rax, rcx);


 679   __ test32(rax, polling_page);
 680   return offset;
 681 }
 682 
 683 
 684 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 685   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 686 }
 687 
 688 void LIR_Assembler::swap_reg(Register a, Register b) {
 689   __ xchgptr(a, b);
 690 }
 691 
 692 
 693 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 694   assert(src->is_constant(), "should not call otherwise");
 695   assert(dest->is_register(), "should not call otherwise");
 696   LIR_Const* c = src->as_constant_ptr();
 697 
 698   switch (c->type()) {
 699     case T_INT:
 700     case T_ADDRESS: {
 701       assert(patch_code == lir_patch_none, "no patching handled here");
 702       __ movl(dest->as_register(), c->as_jint());
 703       break;
 704     }
 705 






 706     case T_LONG: {
 707       assert(patch_code == lir_patch_none, "no patching handled here");
 708 #ifdef _LP64
 709       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 710 #else
 711       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 712       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 713 #endif // _LP64
 714       break;
 715     }
 716 
 717     case T_OBJECT: {
 718       if (patch_code != lir_patch_none) {
 719         jobject2reg_with_patching(dest->as_register(), info);
 720       } else {
 721         __ movoop(dest->as_register(), c->as_jobject());
 722       }
 723       break;
 724     }
 725 


 763         } else {
 764           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 765         }
 766       }
 767       break;
 768     }
 769 
 770     default:
 771       ShouldNotReachHere();
 772   }
 773 }
 774 
 775 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 776   assert(src->is_constant(), "should not call otherwise");
 777   assert(dest->is_stack(), "should not call otherwise");
 778   LIR_Const* c = src->as_constant_ptr();
 779 
 780   switch (c->type()) {
 781     case T_INT:  // fall through
 782     case T_FLOAT:
 783     case T_ADDRESS:
 784       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 785       break;
 786 




 787     case T_OBJECT:
 788       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 789       break;
 790 
 791     case T_LONG:  // fall through
 792     case T_DOUBLE:
 793 #ifdef _LP64
 794       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 795                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 796 #else
 797       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 798                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 799       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 800                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 801 #endif // _LP64
 802       break;
 803 
 804     default:
 805       ShouldNotReachHere();
 806   }
 807 }
 808 
 809 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
 810   assert(src->is_constant(), "should not call otherwise");
 811   assert(dest->is_address(), "should not call otherwise");
 812   LIR_Const* c = src->as_constant_ptr();
 813   LIR_Address* addr = dest->as_address_ptr();
 814 
 815   int null_check_here = code_offset();
 816   switch (type) {
 817     case T_INT:    // fall through
 818     case T_FLOAT:
 819     case T_ADDRESS:
 820       __ movl(as_Address(addr), c->as_jint_bits());
 821       break;
 822 




 823     case T_OBJECT:  // fall through
 824     case T_ARRAY:
 825       if (c->as_jobject() == NULL) {



 826         __ movptr(as_Address(addr), NULL_WORD);

 827       } else {
 828         if (is_literal_address(addr)) {
 829           ShouldNotReachHere();
 830           __ movoop(as_Address(addr, noreg), c->as_jobject());
 831         } else {
 832 #ifdef _LP64
 833           __ movoop(rscratch1, c->as_jobject());





 834           null_check_here = code_offset();
 835           __ movptr(as_Address_lo(addr), rscratch1);

 836 #else
 837           __ movoop(as_Address(addr), c->as_jobject());
 838 #endif
 839         }
 840       }
 841       break;
 842 
 843     case T_LONG:    // fall through
 844     case T_DOUBLE:
 845 #ifdef _LP64
 846       if (is_literal_address(addr)) {
 847         ShouldNotReachHere();
 848         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 849       } else {
 850         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 851         null_check_here = code_offset();
 852         __ movptr(as_Address_lo(addr), r10);
 853       }
 854 #else
 855       // Always reachable in 32bit so this doesn't produce useless move literal


 992     __ movdbl(dst_addr, src->as_xmm_double_reg());
 993 
 994   } else if (src->is_single_fpu()) {
 995     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 996     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 997     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 998     else                   __ fst_s  (dst_addr);
 999 
1000   } else if (src->is_double_fpu()) {
1001     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1002     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1003     if (pop_fpu_stack)     __ fstp_d (dst_addr);
1004     else                   __ fst_d  (dst_addr);
1005 
1006   } else {
1007     ShouldNotReachHere();
1008   }
1009 }
1010 
1011 
1012 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
1013   LIR_Address* to_addr = dest->as_address_ptr();
1014   PatchingStub* patch = NULL;

1015 
1016   if (type == T_ARRAY || type == T_OBJECT) {
1017     __ verify_oop(src->as_register());






1018   }

1019   if (patch_code != lir_patch_none) {
1020     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1021     Address toa = as_Address(to_addr);
1022     assert(toa.disp() != 0, "must have");
1023   }
1024   if (info != NULL) {
1025     add_debug_info_for_null_check_here(info);
1026   }
1027 

1028   switch (type) {
1029     case T_FLOAT: {
1030       if (src->is_single_xmm()) {
1031         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1032       } else {
1033         assert(src->is_single_fpu(), "must be");
1034         assert(src->fpu_regnr() == 0, "argument must be on TOS");
1035         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
1036         else                    __ fst_s (as_Address(to_addr));
1037       }
1038       break;
1039     }
1040 
1041     case T_DOUBLE: {
1042       if (src->is_double_xmm()) {
1043         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1044       } else {
1045         assert(src->is_double_fpu(), "must be");
1046         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1047         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1048         else                    __ fst_d (as_Address(to_addr));
1049       }
1050       break;
1051     }
1052 
1053     case T_ADDRESS: // fall through
1054     case T_ARRAY:   // fall through
1055     case T_OBJECT:  // fall through
1056 #ifdef _LP64






1057       __ movptr(as_Address(to_addr), src->as_register());
1058       break;
1059 #endif // _LP64
1060     case T_INT:
1061       __ movl(as_Address(to_addr), src->as_register());
1062       break;
1063 
1064     case T_LONG: {
1065       Register from_lo = src->as_register_lo();
1066       Register from_hi = src->as_register_hi();
1067 #ifdef _LP64
1068       __ movptr(as_Address_lo(to_addr), from_lo);
1069 #else
1070       Register base = to_addr->base()->as_register();
1071       Register index = noreg;
1072       if (to_addr->index()->is_register()) {
1073         index = to_addr->index()->as_register();
1074       }
1075       if (base == from_lo || index == from_lo) {
1076         assert(base != from_hi, "can't be");
1077         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1078         __ movl(as_Address_hi(to_addr), from_hi);
1079         if (patch != NULL) {


1096       break;
1097     }
1098 
1099     case T_BYTE:    // fall through
1100     case T_BOOLEAN: {
1101       Register src_reg = src->as_register();
1102       Address dst_addr = as_Address(to_addr);
1103       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1104       __ movb(dst_addr, src_reg);
1105       break;
1106     }
1107 
1108     case T_CHAR:    // fall through
1109     case T_SHORT:
1110       __ movw(as_Address(to_addr), src->as_register());
1111       break;
1112 
1113     default:
1114       ShouldNotReachHere();
1115   }



1116 
1117   if (patch_code != lir_patch_none) {
1118     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1119   }
1120 }
1121 
1122 
1123 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1124   assert(src->is_stack(), "should not call otherwise");
1125   assert(dest->is_register(), "should not call otherwise");
1126 
1127   if (dest->is_single_cpu()) {
1128     if (type == T_ARRAY || type == T_OBJECT) {
1129       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1130       __ verify_oop(dest->as_register());
1131     } else {
1132       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1133     }
1134 
1135   } else if (dest->is_double_cpu()) {


1179     }
1180 
1181   } else if (src->is_double_stack()) {
1182 #ifdef _LP64
1183     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1184     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1185 #else
1186     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1187     // push and pop the part at src + wordSize, adding wordSize for the previous push
1188     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1189     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1190     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1191 #endif // _LP64
1192 
1193   } else {
1194     ShouldNotReachHere();
1195   }
1196 }
1197 
1198 
1199 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1200   assert(src->is_address(), "should not call otherwise");
1201   assert(dest->is_register(), "should not call otherwise");
1202 
1203   LIR_Address* addr = src->as_address_ptr();
1204   Address from_addr = as_Address(addr);
1205 
1206   switch (type) {
1207     case T_BOOLEAN: // fall through
1208     case T_BYTE:    // fall through
1209     case T_CHAR:    // fall through
1210     case T_SHORT:
1211       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1212         // on pre P6 processors we may get partial register stalls
1213         // so blow away the value of to_rinfo before loading a
1214         // partial word into it.  Do it here so that it precedes
1215         // the potential patch point below.
1216         __ xorptr(dest->as_register(), dest->as_register());
1217       }
1218       break;
1219   }


1233         __ movflt(dest->as_xmm_float_reg(), from_addr);
1234       } else {
1235         assert(dest->is_single_fpu(), "must be");
1236         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1237         __ fld_s(from_addr);
1238       }
1239       break;
1240     }
1241 
1242     case T_DOUBLE: {
1243       if (dest->is_double_xmm()) {
1244         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1245       } else {
1246         assert(dest->is_double_fpu(), "must be");
1247         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1248         __ fld_d(from_addr);
1249       }
1250       break;
1251     }
1252 
1253     case T_ADDRESS: // fall through
1254     case T_OBJECT:  // fall through
1255     case T_ARRAY:   // fall through
1256 #ifdef _LP64







1257       __ movptr(dest->as_register(), from_addr);
1258       break;
1259 #endif // _L64
1260     case T_INT:
1261       __ movl(dest->as_register(), from_addr);
1262       break;
1263 
1264     case T_LONG: {
1265       Register to_lo = dest->as_register_lo();
1266       Register to_hi = dest->as_register_hi();
1267 #ifdef _LP64
1268       __ movptr(to_lo, as_Address_lo(addr));
1269 #else
1270       Register base = addr->base()->as_register();
1271       Register index = noreg;
1272       if (addr->index()->is_register()) {
1273         index = addr->index()->as_register();
1274       }
1275       if ((base == to_lo && index == to_hi) ||
1276           (base == to_hi && index == to_lo)) {
1277         // addresses with 2 registers are only formed as a result of
1278         // array access so this code will never have to deal with
1279         // patches or null checks.


1334       Register dest_reg = dest->as_register();
1335       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1336         __ movswl(dest_reg, from_addr);
1337       } else {
1338         __ movw(dest_reg, from_addr);
1339         __ shll(dest_reg, 16);
1340         __ sarl(dest_reg, 16);
1341       }
1342       break;
1343     }
1344 
1345     default:
1346       ShouldNotReachHere();
1347   }
1348 
1349   if (patch != NULL) {
1350     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1351   }
1352 
1353   if (type == T_ARRAY || type == T_OBJECT) {





1354     __ verify_oop(dest->as_register());
1355   }
1356 }
1357 
1358 
1359 void LIR_Assembler::prefetchr(LIR_Opr src) {
1360   LIR_Address* addr = src->as_address_ptr();
1361   Address from_addr = as_Address(addr);
1362 
1363   if (VM_Version::supports_sse()) {
1364     switch (ReadPrefetchInstr) {
1365       case 0:
1366         __ prefetchnta(from_addr); break;
1367       case 1:
1368         __ prefetcht0(from_addr); break;
1369       case 2:
1370         __ prefetcht2(from_addr); break;
1371       default:
1372         ShouldNotReachHere(); break;
1373     }


1673     assert(method != NULL, "Should have method");
1674     int bci = op->profiled_bci();
1675     md = method->method_data();
1676     if (md == NULL) {
1677       bailout("out of memory building methodDataOop");
1678       return;
1679     }
1680     data = md->bci_to_data(bci);
1681     assert(data != NULL,                "need data for type check");
1682     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1683   }
1684   Label profile_cast_success, profile_cast_failure;
1685   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1686   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1687 
1688   if (obj == k_RInfo) {
1689     k_RInfo = dst;
1690   } else if (obj == klass_RInfo) {
1691     klass_RInfo = dst;
1692   }
1693   if (k->is_loaded()) {
1694     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1695   } else {
1696     Rtmp1 = op->tmp3()->as_register();
1697     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1698   }
1699 
1700   assert_different_registers(obj, k_RInfo, klass_RInfo);
1701   if (!k->is_loaded()) {
1702     jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1703   } else {
1704 #ifdef _LP64
1705     __ movoop(k_RInfo, k->constant_encoding());
1706 #endif // _LP64
1707   }
1708   assert(obj != k_RInfo, "must be different");
1709 
1710   __ cmpptr(obj, (int32_t)NULL_WORD);
1711   if (op->should_profile()) {
1712     Label not_null;
1713     __ jccb(Assembler::notEqual, not_null);
1714     // Object is null; update MDO and exit
1715     Register mdo  = klass_RInfo;
1716     __ movoop(mdo, md->constant_encoding());
1717     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1718     int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1719     __ orl(data_addr, header_bits);
1720     __ jmp(*obj_is_null);
1721     __ bind(not_null);
1722   } else {
1723     __ jcc(Assembler::equal, *obj_is_null);
1724   }
1725   __ verify_oop(obj);
1726 
1727   if (op->fast_check()) {
1728     // get object class
1729     // not a safepoint as obj null check happens earlier
1730     if (k->is_loaded()) {
1731 #ifdef _LP64




1732       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));

1733 #else

1734       __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1735 #endif // _LP64
1736     } else {
1737       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1738     }

1739     __ jcc(Assembler::notEqual, *failure_target);
1740     // successful cast, fall through to profile or jump
1741   } else {
1742     // get object class
1743     // not a safepoint as obj null check happens earlier
1744     __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1745     if (k->is_loaded()) {
1746       // See if we get an immediate positive hit
1747 #ifdef _LP64
1748       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1749 #else
1750       __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1751 #endif // _LP64
1752       if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1753         __ jcc(Assembler::notEqual, *failure_target);
1754         // successful cast, fall through to profile or jump
1755       } else {
1756         // See if we get an immediate positive hit
1757         __ jcc(Assembler::equal, *success_target);
1758         // check for self
1759 #ifdef _LP64
1760         __ cmpptr(klass_RInfo, k_RInfo);
1761 #else
1762         __ cmpoop(klass_RInfo, k->constant_encoding());
1763 #endif // _LP64
1764         __ jcc(Assembler::equal, *success_target);


1779       }
1780     } else {
1781       // perform the fast part of the checking logic
1782       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1783       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1784       __ push(klass_RInfo);
1785       __ push(k_RInfo);
1786       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1787       __ pop(klass_RInfo);
1788       __ pop(k_RInfo);
1789       // result is a boolean
1790       __ cmpl(k_RInfo, 0);
1791       __ jcc(Assembler::equal, *failure_target);
1792       // successful cast, fall through to profile or jump
1793     }
1794   }
1795   if (op->should_profile()) {
1796     Register mdo  = klass_RInfo, recv = k_RInfo;
1797     __ bind(profile_cast_success);
1798     __ movoop(mdo, md->constant_encoding());
1799     __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes()));
1800     Label update_done;
1801     type_profile_helper(mdo, md, data, recv, success);
1802     __ jmp(*success);
1803 
1804     __ bind(profile_cast_failure);
1805     __ movoop(mdo, md->constant_encoding());
1806     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1807     __ subptr(counter_addr, DataLayout::counter_increment);
1808     __ jmp(*failure);
1809   }
1810   __ jmp(*success);
1811 }
1812 
1813 
1814 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1815   LIR_Code code = op->code();
1816   if (code == lir_store_check) {
1817     Register value = op->object()->as_register();
1818     Register array = op->array()->as_register();
1819     Register k_RInfo = op->tmp1()->as_register();


1843     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1844     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1845 
1846     __ cmpptr(value, (int32_t)NULL_WORD);
1847     if (op->should_profile()) {
1848       Label not_null;
1849       __ jccb(Assembler::notEqual, not_null);
1850       // Object is null; update MDO and exit
1851       Register mdo  = klass_RInfo;
1852       __ movoop(mdo, md->constant_encoding());
1853       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1854       int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1855       __ orl(data_addr, header_bits);
1856       __ jmp(done);
1857       __ bind(not_null);
1858     } else {
1859       __ jcc(Assembler::equal, done);
1860     }
1861 
1862     add_debug_info_for_null_check_here(op->info_for_exception());
1863     __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1864     __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1865 
1866     // get instance klass
1867     __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1868     // perform the fast part of the checking logic
1869     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1870     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1871     __ push(klass_RInfo);
1872     __ push(k_RInfo);
1873     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1874     __ pop(klass_RInfo);
1875     __ pop(k_RInfo);
1876     // result is a boolean
1877     __ cmpl(k_RInfo, 0);
1878     __ jcc(Assembler::equal, *failure_target);
1879     // fall through to the success case
1880 
1881     if (op->should_profile()) {
1882       Register mdo  = klass_RInfo, recv = k_RInfo;
1883       __ bind(profile_cast_success);
1884       __ movoop(mdo, md->constant_encoding());
1885       __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes()));
1886       Label update_done;
1887       type_profile_helper(mdo, md, data, recv, &done);
1888       __ jmpb(done);
1889 
1890       __ bind(profile_cast_failure);
1891       __ movoop(mdo, md->constant_encoding());
1892       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1893       __ subptr(counter_addr, DataLayout::counter_increment);
1894       __ jmp(*stub->entry());
1895     }
1896 
1897     __ bind(done);
1898   } else
1899     if (code == lir_checkcast) {
1900       Register obj = op->object()->as_register();
1901       Register dst = op->result_opr()->as_register();
1902       Label success;
1903       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1904       __ bind(success);
1905       if (dst != obj) {


1929     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1930     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1931     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1932     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1933     Register addr = op->addr()->as_register();
1934     if (os::is_MP()) {
1935       __ lock();
1936     }
1937     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1938 
1939   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1940     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1941     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1942     Register newval = op->new_value()->as_register();
1943     Register cmpval = op->cmp_value()->as_register();
1944     assert(cmpval == rax, "wrong register");
1945     assert(newval != NULL, "new val must be register");
1946     assert(cmpval != newval, "cmp and new values must be in different registers");
1947     assert(cmpval != addr, "cmp and addr must be in different registers");
1948     assert(newval != addr, "new value and addr must be in different registers");
















1949     if (os::is_MP()) {
1950       __ lock();
1951     }
1952     if ( op->code() == lir_cas_obj) {
1953       __ cmpxchgptr(newval, Address(addr, 0));
1954     } else if (op->code() == lir_cas_int) {





1955       __ cmpxchgl(newval, Address(addr, 0));
1956     }
1957 #ifdef _LP64
1958   } else if (op->code() == lir_cas_long) {
1959     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1960     Register newval = op->new_value()->as_register_lo();
1961     Register cmpval = op->cmp_value()->as_register_lo();
1962     assert(cmpval == rax, "wrong register");
1963     assert(newval != NULL, "new val must be register");
1964     assert(cmpval != newval, "cmp and new values must be in different registers");
1965     assert(cmpval != addr, "cmp and addr must be in different registers");
1966     assert(newval != addr, "new value and addr must be in different registers");
1967     if (os::is_MP()) {
1968       __ lock();
1969     }
1970     __ cmpxchgq(newval, Address(addr, 0));
1971 #endif // _LP64
1972   } else {
1973     Unimplemented();
1974   }


3176     __ testl(dst_pos, dst_pos);
3177     __ jcc(Assembler::less, *stub->entry());
3178   }
3179   if (flags & LIR_OpArrayCopy::length_positive_check) {
3180     __ testl(length, length);
3181     __ jcc(Assembler::less, *stub->entry());
3182   }
3183 
3184   if (flags & LIR_OpArrayCopy::src_range_check) {
3185     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3186     __ cmpl(tmp, src_length_addr);
3187     __ jcc(Assembler::above, *stub->entry());
3188   }
3189   if (flags & LIR_OpArrayCopy::dst_range_check) {
3190     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3191     __ cmpl(tmp, dst_length_addr);
3192     __ jcc(Assembler::above, *stub->entry());
3193   }
3194 
3195   if (flags & LIR_OpArrayCopy::type_check) {




3196     __ movptr(tmp, src_klass_addr);
3197     __ cmpptr(tmp, dst_klass_addr);

3198     __ jcc(Assembler::notEqual, *stub->entry());
3199   }
3200 
3201 #ifdef ASSERT
3202   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3203     // Sanity check the known type with the incoming class.  For the
3204     // primitive case the types must match exactly with src.klass and
3205     // dst.klass each exactly matching the default type.  For the
3206     // object array case, if no type check is needed then either the
3207     // dst type is exactly the expected type and the src type is a
3208     // subtype which we can't check or src is the same array as dst
3209     // but not necessarily exactly of type default_type.
3210     Label known_ok, halt;
3211     __ movoop(tmp, default_type->constant_encoding());






3212     if (basic_type != T_OBJECT) {
3213       __ cmpptr(tmp, dst_klass_addr);


3214       __ jcc(Assembler::notEqual, halt);
3215       __ cmpptr(tmp, src_klass_addr);

3216       __ jcc(Assembler::equal, known_ok);
3217     } else {
3218       __ cmpptr(tmp, dst_klass_addr);

3219       __ jcc(Assembler::equal, known_ok);
3220       __ cmpptr(src, dst);
3221       __ jcc(Assembler::equal, known_ok);
3222     }
3223     __ bind(halt);
3224     __ stop("incorrect type information in arraycopy");
3225     __ bind(known_ok);
3226   }
3227 #endif
3228 
3229   if (shift_amount > 0 && basic_type != T_OBJECT) {
3230     __ shlptr(length, shift_amount);
3231   }
3232 
3233 #ifdef _LP64
3234   assert_different_registers(c_rarg0, dst, dst_pos, length);
3235   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3236   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3237   assert_different_registers(c_rarg1, length);
3238   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null


3327           return;
3328         }
3329       }
3330 
3331       // Receiver type not found in profile data; select an empty slot
3332 
3333       // Note that this is less efficient than it should be because it
3334       // always does a write to the receiver part of the
3335       // VirtualCallData rather than just the first time
3336       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3337         ciKlass* receiver = vc_data->receiver(i);
3338         if (receiver == NULL) {
3339           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3340           __ movoop(recv_addr, known_klass->constant_encoding());
3341           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3342           __ addptr(data_addr, DataLayout::counter_increment);
3343           return;
3344         }
3345       }
3346     } else {
3347       __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3348       Label update_done;
3349       type_profile_helper(mdo, md, data, recv, &update_done);
3350       // Receiver did not match any saved receiver and there is no empty row for it.
3351       // Increment total counter to indicate polymorphic case.
3352       __ addptr(counter_addr, DataLayout::counter_increment);
3353 
3354       __ bind(update_done);
3355     }
3356   } else {
3357     // Static call
3358     __ addptr(counter_addr, DataLayout::counter_increment);
3359   }
3360 }
3361 
3362 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3363   Unimplemented();
3364 }
3365 
3366 
3367 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {




 326         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 327         __ jcc(Assembler::notZero, L);
 328         __ stop("locked object is NULL");
 329         __ bind(L);
 330       }
 331 #endif
 332       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 333       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 334       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 335       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 336     }
 337   }
 338 }
 339 
 340 
 341 // inline cache check; done before the frame is built.
 342 int LIR_Assembler::check_icache() {
 343   Register receiver = FrameMap::receiver_opr->as_register();
 344   Register ic_klass = IC_Klass;
 345   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 346   const bool do_post_padding = VerifyOops || UseCompressedOops;
 347   if (!do_post_padding) {
 348     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 349     while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
 350       __ nop();
 351     }
 352   }
 353   int offset = __ offset();
 354   __ inline_cache_check(receiver, IC_Klass);
 355   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 356   if (do_post_padding) {
 357     // force alignment after the cache check.
 358     // It's been verified to be aligned if !VerifyOops
 359     __ align(CodeEntryAlignment);
 360   }
 361   return offset;
 362 }
 363 
 364 
 365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 366   jobject o = NULL;
 367   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 368   __ movoop(reg, o);
 369   patching_epilog(patch, lir_patch_normal, reg, info);
 370 }
 371 
 372 
 373 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
 374   if (exception->is_valid()) {
 375     // preserve exception
 376     // note: the monitor_exit runtime call is a leaf routine


 542   int offset = code_offset();
 543   InternalAddress here(__ pc());
 544 
 545   __ pushptr(here.addr());
 546   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 547 
 548   assert(code_offset() - offset <= deopt_handler_size, "overflow");
 549   __ end_a_stub();
 550 
 551   return offset;
 552 }
 553 
 554 
 555 // This is the fast version of java.lang.String.compare; it has not
 556 // OSR-entry and therefore, we generate a slow version for OSR's
 557 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
 558   __ movptr (rbx, rcx); // receiver is in rcx
 559   __ movptr (rax, arg1->as_register());
 560 
 561   // Get addresses of first characters from both Strings
 562   __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
 563   __ movptr       (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
 564   __ lea          (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 565 
 566 
 567   // rbx, may be NULL
 568   add_debug_info_for_null_check_here(info);
 569   __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
 570   __ movptr       (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
 571   __ lea          (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
 572 
 573   // compute minimum length (in rax) and difference of lengths (on top of stack)
 574   if (VM_Version::supports_cmov()) {
 575     __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 576     __ movl     (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
 577     __ mov      (rcx, rbx);
 578     __ subptr   (rbx, rax); // subtract lengths
 579     __ push     (rbx);      // result
 580     __ cmov     (Assembler::lessEqual, rax, rcx);
 581   } else {
 582     Label L;
 583     __ movl     (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
 584     __ movl     (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
 585     __ mov      (rax, rbx);
 586     __ subptr   (rbx, rcx);
 587     __ push     (rbx);
 588     __ jcc      (Assembler::lessEqual, L);
 589     __ mov      (rax, rcx);


 679   __ test32(rax, polling_page);
 680   return offset;
 681 }
 682 
 683 
 684 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 685   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 686 }
 687 
 688 void LIR_Assembler::swap_reg(Register a, Register b) {
 689   __ xchgptr(a, b);
 690 }
 691 
 692 
 693 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 694   assert(src->is_constant(), "should not call otherwise");
 695   assert(dest->is_register(), "should not call otherwise");
 696   LIR_Const* c = src->as_constant_ptr();
 697 
 698   switch (c->type()) {
 699     case T_INT: {

 700       assert(patch_code == lir_patch_none, "no patching handled here");
 701       __ movl(dest->as_register(), c->as_jint());
 702       break;
 703     }
 704 
 705     case T_ADDRESS: {
 706       assert(patch_code == lir_patch_none, "no patching handled here");
 707       __ movptr(dest->as_register(), c->as_jint());
 708       break;
 709     }
 710 
 711     case T_LONG: {
 712       assert(patch_code == lir_patch_none, "no patching handled here");
 713 #ifdef _LP64
 714       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 715 #else
 716       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 717       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 718 #endif // _LP64
 719       break;
 720     }
 721 
 722     case T_OBJECT: {
 723       if (patch_code != lir_patch_none) {
 724         jobject2reg_with_patching(dest->as_register(), info);
 725       } else {
 726         __ movoop(dest->as_register(), c->as_jobject());
 727       }
 728       break;
 729     }
 730 


 768         } else {
 769           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 770         }
 771       }
 772       break;
 773     }
 774 
 775     default:
 776       ShouldNotReachHere();
 777   }
 778 }
 779 
 780 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 781   assert(src->is_constant(), "should not call otherwise");
 782   assert(dest->is_stack(), "should not call otherwise");
 783   LIR_Const* c = src->as_constant_ptr();
 784 
 785   switch (c->type()) {
 786     case T_INT:  // fall through
 787     case T_FLOAT:

 788       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 789       break;
 790 
 791     case T_ADDRESS:
 792       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 793       break;
 794 
 795     case T_OBJECT:
 796       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 797       break;
 798 
 799     case T_LONG:  // fall through
 800     case T_DOUBLE:
 801 #ifdef _LP64
 802       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 803                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 804 #else
 805       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 806                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 807       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 808                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 809 #endif // _LP64
 810       break;
 811 
 812     default:
 813       ShouldNotReachHere();
 814   }
 815 }
 816 
 817 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 818   assert(src->is_constant(), "should not call otherwise");
 819   assert(dest->is_address(), "should not call otherwise");
 820   LIR_Const* c = src->as_constant_ptr();
 821   LIR_Address* addr = dest->as_address_ptr();
 822 
 823   int null_check_here = code_offset();
 824   switch (type) {
 825     case T_INT:    // fall through
 826     case T_FLOAT:

 827       __ movl(as_Address(addr), c->as_jint_bits());
 828       break;
 829 
 830     case T_ADDRESS:
 831       __ movptr(as_Address(addr), c->as_jint_bits());
 832       break;
 833 
 834     case T_OBJECT:  // fall through
 835     case T_ARRAY:
 836       if (c->as_jobject() == NULL) {
 837         if (UseCompressedOops && !wide) {
 838           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 839         } else {
 840           __ movptr(as_Address(addr), NULL_WORD);
 841         }
 842       } else {
 843         if (is_literal_address(addr)) {
 844           ShouldNotReachHere();
 845           __ movoop(as_Address(addr, noreg), c->as_jobject());
 846         } else {
 847 #ifdef _LP64
 848           __ movoop(rscratch1, c->as_jobject());
 849           if (UseCompressedOops && !wide) {
 850             __ encode_heap_oop(rscratch1);
 851             null_check_here = code_offset();
 852             __ movl(as_Address_lo(addr), rscratch1);
 853           } else {
 854             null_check_here = code_offset();
 855             __ movptr(as_Address_lo(addr), rscratch1);
 856           }
 857 #else
 858           __ movoop(as_Address(addr), c->as_jobject());
 859 #endif
 860         }
 861       }
 862       break;
 863 
 864     case T_LONG:    // fall through
 865     case T_DOUBLE:
 866 #ifdef _LP64
 867       if (is_literal_address(addr)) {
 868         ShouldNotReachHere();
 869         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 870       } else {
 871         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 872         null_check_here = code_offset();
 873         __ movptr(as_Address_lo(addr), r10);
 874       }
 875 #else
 876       // Always reachable in 32bit so this doesn't produce useless move literal


1013     __ movdbl(dst_addr, src->as_xmm_double_reg());
1014 
1015   } else if (src->is_single_fpu()) {
1016     assert(src->fpu_regnr() == 0, "argument must be on TOS");
1017     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1018     if (pop_fpu_stack)     __ fstp_s (dst_addr);
1019     else                   __ fst_s  (dst_addr);
1020 
1021   } else if (src->is_double_fpu()) {
1022     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1023     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1024     if (pop_fpu_stack)     __ fstp_d (dst_addr);
1025     else                   __ fst_d  (dst_addr);
1026 
1027   } else {
1028     ShouldNotReachHere();
1029   }
1030 }
1031 
1032 
1033 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
1034   LIR_Address* to_addr = dest->as_address_ptr();
1035   PatchingStub* patch = NULL;
1036   Register compressed_src = rscratch1;
1037 
1038   if (type == T_ARRAY || type == T_OBJECT) {
1039     __ verify_oop(src->as_register());
1040 #ifdef _LP64
1041     if (UseCompressedOops && !wide) {
1042       __ movptr(compressed_src, src->as_register());
1043       __ encode_heap_oop(compressed_src);
1044     }
1045 #endif
1046   }
1047 
1048   if (patch_code != lir_patch_none) {
1049     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1050     Address toa = as_Address(to_addr);
1051     assert(toa.disp() != 0, "must have");
1052   }



1053 
1054   int null_check_here = code_offset();
1055   switch (type) {
1056     case T_FLOAT: {
1057       if (src->is_single_xmm()) {
1058         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1059       } else {
1060         assert(src->is_single_fpu(), "must be");
1061         assert(src->fpu_regnr() == 0, "argument must be on TOS");
1062         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
1063         else                    __ fst_s (as_Address(to_addr));
1064       }
1065       break;
1066     }
1067 
1068     case T_DOUBLE: {
1069       if (src->is_double_xmm()) {
1070         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1071       } else {
1072         assert(src->is_double_fpu(), "must be");
1073         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1074         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1075         else                    __ fst_d (as_Address(to_addr));
1076       }
1077       break;
1078     }
1079 

1080     case T_ARRAY:   // fall through
1081     case T_OBJECT:  // fall through
1082       if (UseCompressedOops && !wide) {
1083         __ movl(as_Address(to_addr), compressed_src);
1084       } else {
1085         __ movptr(as_Address(to_addr), src->as_register());
1086       }
1087       break;
1088     case T_ADDRESS:
1089       __ movptr(as_Address(to_addr), src->as_register());
1090       break;

1091     case T_INT:
1092       __ movl(as_Address(to_addr), src->as_register());
1093       break;
1094 
1095     case T_LONG: {
1096       Register from_lo = src->as_register_lo();
1097       Register from_hi = src->as_register_hi();
1098 #ifdef _LP64
1099       __ movptr(as_Address_lo(to_addr), from_lo);
1100 #else
1101       Register base = to_addr->base()->as_register();
1102       Register index = noreg;
1103       if (to_addr->index()->is_register()) {
1104         index = to_addr->index()->as_register();
1105       }
1106       if (base == from_lo || index == from_lo) {
1107         assert(base != from_hi, "can't be");
1108         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1109         __ movl(as_Address_hi(to_addr), from_hi);
1110         if (patch != NULL) {


1127       break;
1128     }
1129 
1130     case T_BYTE:    // fall through
1131     case T_BOOLEAN: {
1132       Register src_reg = src->as_register();
1133       Address dst_addr = as_Address(to_addr);
1134       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1135       __ movb(dst_addr, src_reg);
1136       break;
1137     }
1138 
1139     case T_CHAR:    // fall through
1140     case T_SHORT:
1141       __ movw(as_Address(to_addr), src->as_register());
1142       break;
1143 
1144     default:
1145       ShouldNotReachHere();
1146   }
1147   if (info != NULL) {
1148     add_debug_info_for_null_check(null_check_here, info);
1149   }
1150 
1151   if (patch_code != lir_patch_none) {
1152     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1153   }
1154 }
1155 
1156 
1157 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1158   assert(src->is_stack(), "should not call otherwise");
1159   assert(dest->is_register(), "should not call otherwise");
1160 
1161   if (dest->is_single_cpu()) {
1162     if (type == T_ARRAY || type == T_OBJECT) {
1163       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1164       __ verify_oop(dest->as_register());
1165     } else {
1166       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1167     }
1168 
1169   } else if (dest->is_double_cpu()) {


1213     }
1214 
1215   } else if (src->is_double_stack()) {
1216 #ifdef _LP64
1217     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1218     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1219 #else
1220     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1221     // push and pop the part at src + wordSize, adding wordSize for the previous push
1222     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1223     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1224     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1225 #endif // _LP64
1226 
1227   } else {
1228     ShouldNotReachHere();
1229   }
1230 }
1231 
1232 
1233 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1234   assert(src->is_address(), "should not call otherwise");
1235   assert(dest->is_register(), "should not call otherwise");
1236 
1237   LIR_Address* addr = src->as_address_ptr();
1238   Address from_addr = as_Address(addr);
1239 
1240   switch (type) {
1241     case T_BOOLEAN: // fall through
1242     case T_BYTE:    // fall through
1243     case T_CHAR:    // fall through
1244     case T_SHORT:
1245       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1246         // on pre P6 processors we may get partial register stalls
1247         // so blow away the value of to_rinfo before loading a
1248         // partial word into it.  Do it here so that it precedes
1249         // the potential patch point below.
1250         __ xorptr(dest->as_register(), dest->as_register());
1251       }
1252       break;
1253   }


1267         __ movflt(dest->as_xmm_float_reg(), from_addr);
1268       } else {
1269         assert(dest->is_single_fpu(), "must be");
1270         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1271         __ fld_s(from_addr);
1272       }
1273       break;
1274     }
1275 
1276     case T_DOUBLE: {
1277       if (dest->is_double_xmm()) {
1278         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1279       } else {
1280         assert(dest->is_double_fpu(), "must be");
1281         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1282         __ fld_d(from_addr);
1283       }
1284       break;
1285     }
1286 

1287     case T_OBJECT:  // fall through
1288     case T_ARRAY:   // fall through
1289       if (UseCompressedOops && !wide) {
1290         __ movl(dest->as_register(), from_addr);
1291       } else {
1292         __ movptr(dest->as_register(), from_addr);
1293       }
1294       break;
1295 
1296     case T_ADDRESS:
1297       __ movptr(dest->as_register(), from_addr);
1298       break;

1299     case T_INT:
1300       __ movl(dest->as_register(), from_addr);
1301       break;
1302 
1303     case T_LONG: {
1304       Register to_lo = dest->as_register_lo();
1305       Register to_hi = dest->as_register_hi();
1306 #ifdef _LP64
1307       __ movptr(to_lo, as_Address_lo(addr));
1308 #else
1309       Register base = addr->base()->as_register();
1310       Register index = noreg;
1311       if (addr->index()->is_register()) {
1312         index = addr->index()->as_register();
1313       }
1314       if ((base == to_lo && index == to_hi) ||
1315           (base == to_hi && index == to_lo)) {
1316         // addresses with 2 registers are only formed as a result of
1317         // array access so this code will never have to deal with
1318         // patches or null checks.


1373       Register dest_reg = dest->as_register();
1374       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1375         __ movswl(dest_reg, from_addr);
1376       } else {
1377         __ movw(dest_reg, from_addr);
1378         __ shll(dest_reg, 16);
1379         __ sarl(dest_reg, 16);
1380       }
1381       break;
1382     }
1383 
1384     default:
1385       ShouldNotReachHere();
1386   }
1387 
1388   if (patch != NULL) {
1389     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1390   }
1391 
1392   if (type == T_ARRAY || type == T_OBJECT) {
1393 #ifdef _LP64
1394     if (UseCompressedOops && !wide) {
1395       __ decode_heap_oop(dest->as_register());
1396     }
1397 #endif
1398     __ verify_oop(dest->as_register());
1399   }
1400 }
1401 
1402 
1403 void LIR_Assembler::prefetchr(LIR_Opr src) {
1404   LIR_Address* addr = src->as_address_ptr();
1405   Address from_addr = as_Address(addr);
1406 
1407   if (VM_Version::supports_sse()) {
1408     switch (ReadPrefetchInstr) {
1409       case 0:
1410         __ prefetchnta(from_addr); break;
1411       case 1:
1412         __ prefetcht0(from_addr); break;
1413       case 2:
1414         __ prefetcht2(from_addr); break;
1415       default:
1416         ShouldNotReachHere(); break;
1417     }


1717     assert(method != NULL, "Should have method");
1718     int bci = op->profiled_bci();
1719     md = method->method_data();
1720     if (md == NULL) {
1721       bailout("out of memory building methodDataOop");
1722       return;
1723     }
1724     data = md->bci_to_data(bci);
1725     assert(data != NULL,                "need data for type check");
1726     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1727   }
1728   Label profile_cast_success, profile_cast_failure;
1729   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1730   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1731 
1732   if (obj == k_RInfo) {
1733     k_RInfo = dst;
1734   } else if (obj == klass_RInfo) {
1735     klass_RInfo = dst;
1736   }
1737   if (k->is_loaded() && !UseCompressedOops) {
1738     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1739   } else {
1740     Rtmp1 = op->tmp3()->as_register();
1741     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1742   }
1743 
1744   assert_different_registers(obj, k_RInfo, klass_RInfo);
1745   if (!k->is_loaded()) {
1746     jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1747   } else {
1748 #ifdef _LP64
1749     __ movoop(k_RInfo, k->constant_encoding());
1750 #endif // _LP64
1751   }
1752   assert(obj != k_RInfo, "must be different");
1753 
1754   __ cmpptr(obj, (int32_t)NULL_WORD);
1755   if (op->should_profile()) {
1756     Label not_null;
1757     __ jccb(Assembler::notEqual, not_null);
1758     // Object is null; update MDO and exit
1759     Register mdo  = klass_RInfo;
1760     __ movoop(mdo, md->constant_encoding());
1761     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1762     int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1763     __ orl(data_addr, header_bits);
1764     __ jmp(*obj_is_null);
1765     __ bind(not_null);
1766   } else {
1767     __ jcc(Assembler::equal, *obj_is_null);
1768   }
1769   __ verify_oop(obj);
1770 
1771   if (op->fast_check()) {
1772     // get object class
1773     // not a safepoint as obj null check happens earlier

1774 #ifdef _LP64
1775     if (UseCompressedOops) {
1776       __ load_klass(Rtmp1, obj);
1777       __ cmpptr(k_RInfo, Rtmp1);
1778     } else {
1779       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1780     }
1781 #else
1782     if (k->is_loaded()) {
1783       __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());

1784     } else {
1785       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1786     }
1787 #endif
1788     __ jcc(Assembler::notEqual, *failure_target);
1789     // successful cast, fall through to profile or jump
1790   } else {
1791     // get object class
1792     // not a safepoint as obj null check happens earlier
1793     __ load_klass(klass_RInfo, obj);
1794     if (k->is_loaded()) {
1795       // See if we get an immediate positive hit
1796 #ifdef _LP64
1797       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1798 #else
1799       __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1800 #endif // _LP64
1801       if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1802         __ jcc(Assembler::notEqual, *failure_target);
1803         // successful cast, fall through to profile or jump
1804       } else {
1805         // See if we get an immediate positive hit
1806         __ jcc(Assembler::equal, *success_target);
1807         // check for self
1808 #ifdef _LP64
1809         __ cmpptr(klass_RInfo, k_RInfo);
1810 #else
1811         __ cmpoop(klass_RInfo, k->constant_encoding());
1812 #endif // _LP64
1813         __ jcc(Assembler::equal, *success_target);


1828       }
1829     } else {
1830       // perform the fast part of the checking logic
1831       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1832       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1833       __ push(klass_RInfo);
1834       __ push(k_RInfo);
1835       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1836       __ pop(klass_RInfo);
1837       __ pop(k_RInfo);
1838       // result is a boolean
1839       __ cmpl(k_RInfo, 0);
1840       __ jcc(Assembler::equal, *failure_target);
1841       // successful cast, fall through to profile or jump
1842     }
1843   }
1844   if (op->should_profile()) {
1845     Register mdo  = klass_RInfo, recv = k_RInfo;
1846     __ bind(profile_cast_success);
1847     __ movoop(mdo, md->constant_encoding());
1848     __ load_klass(recv, obj);
1849     Label update_done;
1850     type_profile_helper(mdo, md, data, recv, success);
1851     __ jmp(*success);
1852 
1853     __ bind(profile_cast_failure);
1854     __ movoop(mdo, md->constant_encoding());
1855     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1856     __ subptr(counter_addr, DataLayout::counter_increment);
1857     __ jmp(*failure);
1858   }
1859   __ jmp(*success);
1860 }
1861 
1862 
1863 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1864   LIR_Code code = op->code();
1865   if (code == lir_store_check) {
1866     Register value = op->object()->as_register();
1867     Register array = op->array()->as_register();
1868     Register k_RInfo = op->tmp1()->as_register();


1892     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1893     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1894 
1895     __ cmpptr(value, (int32_t)NULL_WORD);
1896     if (op->should_profile()) {
1897       Label not_null;
1898       __ jccb(Assembler::notEqual, not_null);
1899       // Object is null; update MDO and exit
1900       Register mdo  = klass_RInfo;
1901       __ movoop(mdo, md->constant_encoding());
1902       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1903       int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1904       __ orl(data_addr, header_bits);
1905       __ jmp(done);
1906       __ bind(not_null);
1907     } else {
1908       __ jcc(Assembler::equal, done);
1909     }
1910 
1911     add_debug_info_for_null_check_here(op->info_for_exception());
1912     __ load_klass(k_RInfo, array);
1913     __ load_klass(klass_RInfo, value);
1914 
1915     // get instance klass (it's already uncompressed)
1916     __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1917     // perform the fast part of the checking logic
1918     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1919     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1920     __ push(klass_RInfo);
1921     __ push(k_RInfo);
1922     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1923     __ pop(klass_RInfo);
1924     __ pop(k_RInfo);
1925     // result is a boolean
1926     __ cmpl(k_RInfo, 0);
1927     __ jcc(Assembler::equal, *failure_target);
1928     // fall through to the success case
1929 
1930     if (op->should_profile()) {
1931       Register mdo  = klass_RInfo, recv = k_RInfo;
1932       __ bind(profile_cast_success);
1933       __ movoop(mdo, md->constant_encoding());
1934       __ load_klass(recv, value);
1935       Label update_done;
1936       type_profile_helper(mdo, md, data, recv, &done);
1937       __ jmpb(done);
1938 
1939       __ bind(profile_cast_failure);
1940       __ movoop(mdo, md->constant_encoding());
1941       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1942       __ subptr(counter_addr, DataLayout::counter_increment);
1943       __ jmp(*stub->entry());
1944     }
1945 
1946     __ bind(done);
1947   } else
1948     if (code == lir_checkcast) {
1949       Register obj = op->object()->as_register();
1950       Register dst = op->result_opr()->as_register();
1951       Label success;
1952       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1953       __ bind(success);
1954       if (dst != obj) {


1978     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1979     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1980     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1981     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1982     Register addr = op->addr()->as_register();
1983     if (os::is_MP()) {
1984       __ lock();
1985     }
1986     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1987 
1988   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1989     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1990     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1991     Register newval = op->new_value()->as_register();
1992     Register cmpval = op->cmp_value()->as_register();
1993     assert(cmpval == rax, "wrong register");
1994     assert(newval != NULL, "new val must be register");
1995     assert(cmpval != newval, "cmp and new values must be in different registers");
1996     assert(cmpval != addr, "cmp and addr must be in different registers");
1997     assert(newval != addr, "new value and addr must be in different registers");
1998 
1999     if ( op->code() == lir_cas_obj) {
2000 #ifdef _LP64
2001       if (UseCompressedOops) {
2002         __ mov(rscratch1, cmpval);
2003         __ encode_heap_oop(cmpval);
2004         __ mov(rscratch2, newval);
2005         __ encode_heap_oop(rscratch2);
2006         if (os::is_MP()) {
2007           __ lock();
2008         }
2009         __ cmpxchgl(rscratch2, Address(addr, 0));
2010         __ mov(cmpval, rscratch1);
2011       } else 
2012 #endif
2013       {
2014         if (os::is_MP()) {
2015           __ lock();
2016         }

2017         __ cmpxchgptr(newval, Address(addr, 0));
2018       }
2019     } else {
2020       assert(op->code() == lir_cas_int, "lir_cas_int expected");
2021       if (os::is_MP()) {
2022         __ lock();
2023       }
2024       __ cmpxchgl(newval, Address(addr, 0));
2025     }
2026 #ifdef _LP64
2027   } else if (op->code() == lir_cas_long) {
2028     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2029     Register newval = op->new_value()->as_register_lo();
2030     Register cmpval = op->cmp_value()->as_register_lo();
2031     assert(cmpval == rax, "wrong register");
2032     assert(newval != NULL, "new val must be register");
2033     assert(cmpval != newval, "cmp and new values must be in different registers");
2034     assert(cmpval != addr, "cmp and addr must be in different registers");
2035     assert(newval != addr, "new value and addr must be in different registers");
2036     if (os::is_MP()) {
2037       __ lock();
2038     }
2039     __ cmpxchgq(newval, Address(addr, 0));
2040 #endif // _LP64
2041   } else {
2042     Unimplemented();
2043   }


3245     __ testl(dst_pos, dst_pos);
3246     __ jcc(Assembler::less, *stub->entry());
3247   }
3248   if (flags & LIR_OpArrayCopy::length_positive_check) {
3249     __ testl(length, length);
3250     __ jcc(Assembler::less, *stub->entry());
3251   }
3252 
3253   if (flags & LIR_OpArrayCopy::src_range_check) {
3254     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3255     __ cmpl(tmp, src_length_addr);
3256     __ jcc(Assembler::above, *stub->entry());
3257   }
3258   if (flags & LIR_OpArrayCopy::dst_range_check) {
3259     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3260     __ cmpl(tmp, dst_length_addr);
3261     __ jcc(Assembler::above, *stub->entry());
3262   }
3263 
3264   if (flags & LIR_OpArrayCopy::type_check) {
3265     if (UseCompressedOops) {
3266       __ movl(tmp, src_klass_addr);
3267       __ cmpl(tmp, dst_klass_addr);
3268     } else {
3269       __ movptr(tmp, src_klass_addr);
3270       __ cmpptr(tmp, dst_klass_addr);
3271     }
3272     __ jcc(Assembler::notEqual, *stub->entry());
3273   }
3274 
3275 #ifdef ASSERT
3276   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3277     // Sanity check the known type with the incoming class.  For the
3278     // primitive case the types must match exactly with src.klass and
3279     // dst.klass each exactly matching the default type.  For the
3280     // object array case, if no type check is needed then either the
3281     // dst type is exactly the expected type and the src type is a
3282     // subtype which we can't check or src is the same array as dst
3283     // but not necessarily exactly of type default_type.
3284     Label known_ok, halt;
3285     __ movoop(tmp, default_type->constant_encoding());
3286 #ifdef _LP64
3287     if (UseCompressedOops) {
3288       __ encode_heap_oop(tmp);
3289     }
3290 #endif
3291 
3292     if (basic_type != T_OBJECT) {
3293 
3294       if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr);
3295       else                   __ cmpptr(tmp, dst_klass_addr);
3296       __ jcc(Assembler::notEqual, halt);
3297       if (UseCompressedOops) __ cmpl(tmp, src_klass_addr);
3298       else                   __ cmpptr(tmp, src_klass_addr);
3299       __ jcc(Assembler::equal, known_ok);
3300     } else {
3301       if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr);
3302       else                   __ cmpptr(tmp, dst_klass_addr);
3303       __ jcc(Assembler::equal, known_ok);
3304       __ cmpptr(src, dst);
3305       __ jcc(Assembler::equal, known_ok);
3306     }
3307     __ bind(halt);
3308     __ stop("incorrect type information in arraycopy");
3309     __ bind(known_ok);
3310   }
3311 #endif
3312 
3313   if (shift_amount > 0 && basic_type != T_OBJECT) {
3314     __ shlptr(length, shift_amount);
3315   }
3316 
3317 #ifdef _LP64
3318   assert_different_registers(c_rarg0, dst, dst_pos, length);
3319   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3320   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3321   assert_different_registers(c_rarg1, length);
3322   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null


3411           return;
3412         }
3413       }
3414 
3415       // Receiver type not found in profile data; select an empty slot
3416 
3417       // Note that this is less efficient than it should be because it
3418       // always does a write to the receiver part of the
3419       // VirtualCallData rather than just the first time
3420       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3421         ciKlass* receiver = vc_data->receiver(i);
3422         if (receiver == NULL) {
3423           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3424           __ movoop(recv_addr, known_klass->constant_encoding());
3425           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3426           __ addptr(data_addr, DataLayout::counter_increment);
3427           return;
3428         }
3429       }
3430     } else {
3431       __ load_klass(recv, recv);
3432       Label update_done;
3433       type_profile_helper(mdo, md, data, recv, &update_done);
3434       // Receiver did not match any saved receiver and there is no empty row for it.
3435       // Increment total counter to indicate polymorphic case.
3436       __ addptr(counter_addr, DataLayout::counter_increment);
3437 
3438       __ bind(update_done);
3439     }
3440   } else {
3441     // Static call
3442     __ addptr(counter_addr, DataLayout::counter_increment);
3443   }
3444 }
3445 
3446 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3447   Unimplemented();
3448 }
3449 
3450 
3451 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {


src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
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