1 /*
2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_C1_LINEARSCAN_X86_HPP
26 #define CPU_X86_VM_C1_LINEARSCAN_X86_HPP
27
28 inline bool LinearScan::is_processed_reg_num(int reg_num) {
29 #ifndef _LP64
30 // rsp and rbp (numbers 6 ancd 7) are ignored
31 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
32 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
33 assert(reg_num >= 0, "invalid reg_num");
34
35 return reg_num < 6 || reg_num > 7;
36 #else
37 // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
38 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
39 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
40 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
41 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
42 assert(reg_num >= 0, "invalid reg_num");
43
44 return reg_num < 12 || reg_num > 15;
45 #endif // _LP64
46 }
47
48 inline int LinearScan::num_physical_regs(BasicType type) {
49 // Intel requires two cpu registers for long,
50 // but requires only one fpu register for double
51 if (LP64_ONLY(false &&) type == T_LONG) {
52 return 2;
53 }
54 return 1;
55 }
56
57
58 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
59 return false;
60 }
61
62 inline bool LinearScan::is_caller_save(int assigned_reg) {
63 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
64 return true; // no callee-saved registers on Intel
65
66 }
67
68
69 inline void LinearScan::pd_add_temps(LIR_Op* op) {
70 switch (op->code()) {
71 case lir_tan:
72 case lir_sin:
73 case lir_cos: {
74 // The slow path for these functions may need to save and
75 // restore all live registers but we don't want to save and
76 // restore everything all the time, so mark the xmms as being
77 // killed. If the slow path were explicit or we could propagate
78 // live register masks down to the assembly we could do better
79 // but we don't have any easy way to do that right now. We
80 // could also consider not killing all xmm registers if we
81 // assume that slow paths are uncommon but it's not clear that
82 // would be a good idea.
83 if (UseSSE > 0) {
84 #ifndef PRODUCT
85 if (TraceLinearScanLevel >= 2) {
86 tty->print_cr("killing XMMs for trig");
87 }
88 #endif
89 int op_id = op->id();
90 for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) {
91 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
92 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
93 }
94 }
95 break;
96 }
97 }
98 }
99
100
101 // Implementation of LinearScanWalker
102
103 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
104 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
105 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
106 _first_reg = pd_first_byte_reg;
107 _last_reg = pd_last_byte_reg;
108 return true;
109 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
110 _first_reg = pd_first_xmm_reg;
111 _last_reg = pd_last_xmm_reg;
112 return true;
113 }
114
115 return false;
116 }
117
118
119 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
120 private:
121 Compilation* _compilation;
122 LinearScan* _allocator;
123
124 LIR_OpVisitState visitor;
125
126 LIR_List* _lir;
127 int _pos;
128 FpuStackSim _sim;
129 FpuStackSim _temp_sim;
130
131 bool _debug_information_computed;
132
133 LinearScan* allocator() { return _allocator; }
134 Compilation* compilation() const { return _compilation; }
135
136 // unified bailout support
137 void bailout(const char* msg) const { compilation()->bailout(msg); }
138 bool bailed_out() const { return compilation()->bailed_out(); }
139
140 int pos() { return _pos; }
141 void set_pos(int pos) { _pos = pos; }
142 LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); }
143 LIR_List* lir() { return _lir; }
144 void set_lir(LIR_List* lir) { _lir = lir; }
145 FpuStackSim* sim() { return &_sim; }
146 FpuStackSim* temp_sim() { return &_temp_sim; }
147
148 int fpu_num(LIR_Opr opr);
149 int tos_offset(LIR_Opr opr);
150 LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false);
151
152 // Helper functions for handling operations
153 void insert_op(LIR_Op* op);
154 void insert_exchange(int offset);
155 void insert_exchange(LIR_Opr opr);
156 void insert_free(int offset);
157 void insert_free_if_dead(LIR_Opr opr);
158 void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore);
159 void insert_copy(LIR_Opr from, LIR_Opr to);
160 void do_rename(LIR_Opr from, LIR_Opr to);
161 void do_push(LIR_Opr opr);
162 void pop_if_last_use(LIR_Op* op, LIR_Opr opr);
163 void pop_always(LIR_Op* op, LIR_Opr opr);
164 void clear_fpu_stack(LIR_Opr preserve);
165 void handle_op1(LIR_Op1* op1);
166 void handle_op2(LIR_Op2* op2);
167 void handle_opCall(LIR_OpCall* opCall);
168 void compute_debug_information(LIR_Op* op);
169 void allocate_exception_handler(XHandler* xhandler);
170 void allocate_block(BlockBegin* block);
171
172 #ifndef PRODUCT
173 void check_invalid_lir_op(LIR_Op* op);
174 #endif
175
176 // Helper functions for merging of fpu stacks
177 void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg);
178 void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot);
179 void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim);
180 bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot);
181 void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim);
182 void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs);
183 bool merge_fpu_stack_with_successors(BlockBegin* block);
184
185 public:
186 LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information
187
188 FpuStackAllocator(Compilation* compilation, LinearScan* allocator);
189 void allocate();
190 };
191
192 #endif // CPU_X86_VM_C1_LINEARSCAN_X86_HPP