14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_C1_LINEARSCAN_X86_HPP
26 #define CPU_X86_VM_C1_LINEARSCAN_X86_HPP
27
28 inline bool LinearScan::is_processed_reg_num(int reg_num) {
29 #ifndef _LP64
30 // rsp and rbp (numbers 6 ancd 7) are ignored
31 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
32 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
33 assert(reg_num >= 0, "invalid reg_num");
34
35 return reg_num < 6 || reg_num > 7;
36 #else
37 // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
38 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
39 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
40 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
41 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
42 assert(reg_num >= 0, "invalid reg_num");
43
44 return reg_num < 12 || reg_num > 15;
45 #endif // _LP64
46 }
47
48 inline int LinearScan::num_physical_regs(BasicType type) {
49 // Intel requires two cpu registers for long,
50 // but requires only one fpu register for double
51 if (LP64_ONLY(false &&) type == T_LONG) {
52 return 2;
53 }
54 return 1;
55 }
56
57
58 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
59 return false;
60 }
61
62 inline bool LinearScan::is_caller_save(int assigned_reg) {
63 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
64 return true; // no callee-saved registers on Intel
65
87 }
88 #endif
89 int op_id = op->id();
90 for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) {
91 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
92 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
93 }
94 }
95 break;
96 }
97 }
98 }
99
100
101 // Implementation of LinearScanWalker
102
103 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
104 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
105 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
106 _first_reg = pd_first_byte_reg;
107 _last_reg = pd_last_byte_reg;
108 return true;
109 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
110 _first_reg = pd_first_xmm_reg;
111 _last_reg = pd_last_xmm_reg;
112 return true;
113 }
114
115 return false;
116 }
117
118
119 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
120 private:
121 Compilation* _compilation;
122 LinearScan* _allocator;
123
124 LIR_OpVisitState visitor;
125
126 LIR_List* _lir;
127 int _pos;
|
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_C1_LINEARSCAN_X86_HPP
26 #define CPU_X86_VM_C1_LINEARSCAN_X86_HPP
27
28 inline bool LinearScan::is_processed_reg_num(int reg_num) {
29 #ifndef _LP64
30 // rsp and rbp (numbers 6 ancd 7) are ignored
31 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
32 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
33 assert(reg_num >= 0, "invalid reg_num");
34 #else
35 // rsp and rbp, r10, r15 (numbers [12,15]) are ignored
36 // r12 (number 11) is conditional on compressed oops.
37 assert(FrameMap::r12_opr->cpu_regnr() == 11, "wrong assumption below");
38 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
39 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
40 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
41 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
42 assert(reg_num >= 0, "invalid reg_num");
43 #endif // _LP64
44 return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map;
45 }
46
47 inline int LinearScan::num_physical_regs(BasicType type) {
48 // Intel requires two cpu registers for long,
49 // but requires only one fpu register for double
50 if (LP64_ONLY(false &&) type == T_LONG) {
51 return 2;
52 }
53 return 1;
54 }
55
56
57 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
58 return false;
59 }
60
61 inline bool LinearScan::is_caller_save(int assigned_reg) {
62 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
63 return true; // no callee-saved registers on Intel
64
86 }
87 #endif
88 int op_id = op->id();
89 for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) {
90 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
91 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
92 }
93 }
94 break;
95 }
96 }
97 }
98
99
100 // Implementation of LinearScanWalker
101
102 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
103 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
104 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
105 _first_reg = pd_first_byte_reg;
106 _last_reg = FrameMap::last_byte_reg();
107 return true;
108 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
109 _first_reg = pd_first_xmm_reg;
110 _last_reg = pd_last_xmm_reg;
111 return true;
112 }
113
114 return false;
115 }
116
117
118 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
119 private:
120 Compilation* _compilation;
121 LinearScan* _allocator;
122
123 LIR_OpVisitState visitor;
124
125 LIR_List* _lir;
126 int _pos;
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