*** old/src/cpu/x86/vm/c1_LinearScan_x86.hpp	Thu Nov 25 07:06:00 2010
--- new/src/cpu/x86/vm/c1_LinearScan_x86.hpp	Thu Nov 25 07:06:00 2010

*** 29,50 ****
--- 29,49 ----
  #ifndef _LP64
    // rsp and rbp (numbers 6 ancd 7) are ignored
    assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
    assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
    assert(reg_num >= 0, "invalid reg_num");
  
    return reg_num < 6 || reg_num > 7;
  #else
!   // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
!   // rsp and rbp, r10, r15 (numbers [12,15]) are ignored
+   // r12 (number 11) is conditional on compressed oops.
+   assert(FrameMap::r12_opr->cpu_regnr() == 11, "wrong assumption below");
    assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
    assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
    assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
    assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
    assert(reg_num >= 0, "invalid reg_num");
  
    return reg_num < 12 || reg_num > 15;
  #endif // _LP64
+   return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map;
  }
  
  inline int LinearScan::num_physical_regs(BasicType type) {
    // Intel requires two cpu registers for long,
    // but requires only one fpu register for double

*** 102,112 ****
--- 101,111 ----
  
  inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
    if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
      assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
      _first_reg = pd_first_byte_reg;
!     _last_reg = pd_last_byte_reg;
!     _last_reg = FrameMap::last_byte_reg();
      return true;
    } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
      _first_reg = pd_first_xmm_reg;
      _last_reg = pd_last_xmm_reg;
      return true;