36   LIR_Opr opr = LIR_OprFact::illegalOpr;
  37   VMReg r_1 = reg->first();
  38   VMReg r_2 = reg->second();
  39   if (r_1->is_stack()) {
  40     // Convert stack slot to an SP offset
  41     // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
  42     // so we must add it in here.
  43     int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
  44     opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
  45   } else if (r_1->is_Register()) {
  46     Register reg = r_1->as_Register();
  47     if (outgoing) {
  48       assert(!reg->is_in(), "should be using I regs");
  49     } else {
  50       assert(!reg->is_out(), "should be using O regs");
  51     }
  52     if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
  53       opr = as_long_opr(reg);
  54     } else if (type == T_OBJECT || type == T_ARRAY) {
  55       opr = as_oop_opr(reg);


  56     } else {
  57       opr = as_opr(reg);
  58     }
  59   } else if (r_1->is_FloatRegister()) {
  60     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
  61     FloatRegister f = r_1->as_FloatRegister();
  62     if (type == T_DOUBLE) {
  63       opr = as_double_opr(f);
  64     } else {
  65       opr = as_float_opr(f);
  66     }
  67   }
  68   return opr;
  69 }
  70 
  71 //               FrameMap
  72 //--------------------------------------------------------
  73 
  74 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
  75 

  36   LIR_Opr opr = LIR_OprFact::illegalOpr;
  37   VMReg r_1 = reg->first();
  38   VMReg r_2 = reg->second();
  39   if (r_1->is_stack()) {
  40     // Convert stack slot to an SP offset
  41     // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
  42     // so we must add it in here.
  43     int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
  44     opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
  45   } else if (r_1->is_Register()) {
  46     Register reg = r_1->as_Register();
  47     if (outgoing) {
  48       assert(!reg->is_in(), "should be using I regs");
  49     } else {
  50       assert(!reg->is_out(), "should be using O regs");
  51     }
  52     if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
  53       opr = as_long_opr(reg);
  54     } else if (type == T_OBJECT || type == T_ARRAY) {
  55       opr = as_oop_opr(reg);
  56     } else if (type == T_METADATA) {
  57       opr = as_metadata_opr(reg);
  58     } else {
  59       opr = as_opr(reg);
  60     }
  61   } else if (r_1->is_FloatRegister()) {
  62     assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
  63     FloatRegister f = r_1->as_FloatRegister();
  64     if (type == T_DOUBLE) {
  65       opr = as_double_opr(f);
  66     } else {
  67       opr = as_float_opr(f);
  68     }
  69   }
  70   return opr;
  71 }
  72 
  73 //               FrameMap
  74 //--------------------------------------------------------
  75 
  76 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
  77