1 /*
2 * Copyright (c) 1999, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_FrameMap.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "runtime/sharedRuntime.hpp"
29 #include "vmreg_x86.inline.hpp"
30
31 const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
32
33 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
34 LIR_Opr opr = LIR_OprFact::illegalOpr;
35 VMReg r_1 = reg->first();
36 VMReg r_2 = reg->second();
37 if (r_1->is_stack()) {
38 // Convert stack slot to an SP offset
39 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
40 // so we must add it in here.
41 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
42 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
43 } else if (r_1->is_Register()) {
44 Register reg = r_1->as_Register();
45 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
46 Register reg2 = r_2->as_Register();
47 #ifdef _LP64
48 assert(reg2 == reg, "must be same register");
49 opr = as_long_opr(reg);
50 #else
51 opr = as_long_opr(reg2, reg);
52 #endif // _LP64
53 } else if (type == T_OBJECT || type == T_ARRAY) {
54 opr = as_oop_opr(reg);
55 } else {
56 opr = as_opr(reg);
57 }
58 } else if (r_1->is_FloatRegister()) {
59 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
60 int num = r_1->as_FloatRegister()->encoding();
61 if (type == T_FLOAT) {
62 opr = LIR_OprFact::single_fpu(num);
63 } else {
64 opr = LIR_OprFact::double_fpu(num);
65 }
66 } else if (r_1->is_XMMRegister()) {
67 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
68 int num = r_1->as_XMMRegister()->encoding();
69 if (type == T_FLOAT) {
70 opr = LIR_OprFact::single_xmm(num);
71 } else {
72 opr = LIR_OprFact::double_xmm(num);
73 }
74 } else {
75 ShouldNotReachHere();
76 }
77 return opr;
78 }
79
80
81 LIR_Opr FrameMap::rsi_opr;
82 LIR_Opr FrameMap::rdi_opr;
83 LIR_Opr FrameMap::rbx_opr;
84 LIR_Opr FrameMap::rax_opr;
85 LIR_Opr FrameMap::rdx_opr;
86 LIR_Opr FrameMap::rcx_opr;
87 LIR_Opr FrameMap::rsp_opr;
88 LIR_Opr FrameMap::rbp_opr;
89
90 LIR_Opr FrameMap::receiver_opr;
91
92 LIR_Opr FrameMap::rsi_oop_opr;
93 LIR_Opr FrameMap::rdi_oop_opr;
94 LIR_Opr FrameMap::rbx_oop_opr;
95 LIR_Opr FrameMap::rax_oop_opr;
96 LIR_Opr FrameMap::rdx_oop_opr;
97 LIR_Opr FrameMap::rcx_oop_opr;
98
99 LIR_Opr FrameMap::rsi_metadata_opr;
100 LIR_Opr FrameMap::rdi_metadata_opr;
101 LIR_Opr FrameMap::rbx_metadata_opr;
102 LIR_Opr FrameMap::rax_metadata_opr;
103 LIR_Opr FrameMap::rdx_metadata_opr;
104 LIR_Opr FrameMap::rcx_metadata_opr;
105
106 LIR_Opr FrameMap::long0_opr;
107 LIR_Opr FrameMap::long1_opr;
108 LIR_Opr FrameMap::fpu0_float_opr;
109 LIR_Opr FrameMap::fpu0_double_opr;
110 LIR_Opr FrameMap::xmm0_float_opr;
111 LIR_Opr FrameMap::xmm0_double_opr;
112
113 #ifdef _LP64
114
115 LIR_Opr FrameMap::r8_opr;
116 LIR_Opr FrameMap::r9_opr;
117 LIR_Opr FrameMap::r10_opr;
118 LIR_Opr FrameMap::r11_opr;
119 LIR_Opr FrameMap::r12_opr;
120 LIR_Opr FrameMap::r13_opr;
121 LIR_Opr FrameMap::r14_opr;
122 LIR_Opr FrameMap::r15_opr;
123
124 // r10 and r15 can never contain oops since they aren't available to
125 // the allocator
126 LIR_Opr FrameMap::r8_oop_opr;
127 LIR_Opr FrameMap::r9_oop_opr;
128 LIR_Opr FrameMap::r11_oop_opr;
129 LIR_Opr FrameMap::r12_oop_opr;
130 LIR_Opr FrameMap::r13_oop_opr;
131 LIR_Opr FrameMap::r14_oop_opr;
132
133 LIR_Opr FrameMap::r8_metadata_opr;
134 LIR_Opr FrameMap::r9_metadata_opr;
135 LIR_Opr FrameMap::r11_metadata_opr;
136 LIR_Opr FrameMap::r12_metadata_opr;
137 LIR_Opr FrameMap::r13_metadata_opr;
138 LIR_Opr FrameMap::r14_metadata_opr;
139 #endif // _LP64
140
141 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
142 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
143 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
144
145 XMMRegister FrameMap::_xmm_regs [] = { 0, };
146
147 XMMRegister FrameMap::nr2xmmreg(int rnr) {
148 assert(_init_done, "tables not initialized");
149 return _xmm_regs[rnr];
150 }
151
152 //--------------------------------------------------------
153 // FrameMap
154 //--------------------------------------------------------
155
156 void FrameMap::initialize() {
157 assert(!_init_done, "once");
158
159 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
160 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
161 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
162 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
163 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
164 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
165 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
166
167 #ifndef _LP64
168 // The unallocatable registers are at the end
169 map_register(6, rsp);
170 map_register(7, rbp);
171 #else
172 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
173 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
174 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
175 map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9);
176 map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10);
177 // r12 is allocated conditionally. With compressed oops it holds
178 // the heapbase value and is not visible to the allocator.
179 map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11);
180 // The unallocatable registers are at the end
181 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
182 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
183 map_register(14, rsp);
184 map_register(15, rbp);
185 #endif // _LP64
186
187 #ifdef _LP64
188 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
189 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
190 #else
191 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
192 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
193 #endif // _LP64
194 fpu0_float_opr = LIR_OprFact::single_fpu(0);
195 fpu0_double_opr = LIR_OprFact::double_fpu(0);
196 xmm0_float_opr = LIR_OprFact::single_xmm(0);
197 xmm0_double_opr = LIR_OprFact::double_xmm(0);
198
199 _caller_save_cpu_regs[0] = rsi_opr;
200 _caller_save_cpu_regs[1] = rdi_opr;
201 _caller_save_cpu_regs[2] = rbx_opr;
202 _caller_save_cpu_regs[3] = rax_opr;
203 _caller_save_cpu_regs[4] = rdx_opr;
204 _caller_save_cpu_regs[5] = rcx_opr;
205
206 #ifdef _LP64
207 _caller_save_cpu_regs[6] = r8_opr;
208 _caller_save_cpu_regs[7] = r9_opr;
209 _caller_save_cpu_regs[8] = r11_opr;
210 _caller_save_cpu_regs[9] = r13_opr;
211 _caller_save_cpu_regs[10] = r14_opr;
212 _caller_save_cpu_regs[11] = r12_opr;
213 #endif // _LP64
214
215
216 _xmm_regs[0] = xmm0;
217 _xmm_regs[1] = xmm1;
218 _xmm_regs[2] = xmm2;
219 _xmm_regs[3] = xmm3;
220 _xmm_regs[4] = xmm4;
221 _xmm_regs[5] = xmm5;
222 _xmm_regs[6] = xmm6;
223 _xmm_regs[7] = xmm7;
224
225 #ifdef _LP64
226 _xmm_regs[8] = xmm8;
227 _xmm_regs[9] = xmm9;
228 _xmm_regs[10] = xmm10;
229 _xmm_regs[11] = xmm11;
230 _xmm_regs[12] = xmm12;
231 _xmm_regs[13] = xmm13;
232 _xmm_regs[14] = xmm14;
233 _xmm_regs[15] = xmm15;
234 #endif // _LP64
235
236 for (int i = 0; i < 8; i++) {
237 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
238 }
239
240 for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
241 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
242 }
243
244 _init_done = true;
245
246 rsi_oop_opr = as_oop_opr(rsi);
247 rdi_oop_opr = as_oop_opr(rdi);
248 rbx_oop_opr = as_oop_opr(rbx);
249 rax_oop_opr = as_oop_opr(rax);
250 rdx_oop_opr = as_oop_opr(rdx);
251 rcx_oop_opr = as_oop_opr(rcx);
252
253 rsi_metadata_opr = as_metadata_opr(rsi);
254 rdi_metadata_opr = as_metadata_opr(rdi);
255 rbx_metadata_opr = as_metadata_opr(rbx);
256 rax_metadata_opr = as_metadata_opr(rax);
257 rdx_metadata_opr = as_metadata_opr(rdx);
258 rcx_metadata_opr = as_metadata_opr(rcx);
259
260 rsp_opr = as_pointer_opr(rsp);
261 rbp_opr = as_pointer_opr(rbp);
262
263 #ifdef _LP64
264 r8_oop_opr = as_oop_opr(r8);
265 r9_oop_opr = as_oop_opr(r9);
266 r11_oop_opr = as_oop_opr(r11);
267 r12_oop_opr = as_oop_opr(r12);
268 r13_oop_opr = as_oop_opr(r13);
269 r14_oop_opr = as_oop_opr(r14);
270
271 r8_metadata_opr = as_metadata_opr(r8);
272 r9_metadata_opr = as_metadata_opr(r9);
273 r11_metadata_opr = as_metadata_opr(r11);
274 r12_metadata_opr = as_metadata_opr(r12);
275 r13_metadata_opr = as_metadata_opr(r13);
276 r14_metadata_opr = as_metadata_opr(r14);
277 #endif // _LP64
278
279 VMRegPair regs;
280 BasicType sig_bt = T_OBJECT;
281 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
282 receiver_opr = as_oop_opr(regs.first()->as_Register());
283
284 }
285
286
287 Address FrameMap::make_new_address(ByteSize sp_offset) const {
288 // for rbp, based address use this:
289 // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
290 return Address(rsp, in_bytes(sp_offset));
291 }
292
293
294 // ----------------mapping-----------------------
295 // all mapping is based on rbp, addressing, except for simple leaf methods where we access
296 // the locals rsp based (and no frame is built)
297
298
299 // Frame for simple leaf methods (quick entries)
300 //
301 // +----------+
302 // | ret addr | <- TOS
303 // +----------+
304 // | args |
305 // | ...... |
306
307 // Frame for standard methods
308 //
309 // | .........| <- TOS
310 // | locals |
311 // +----------+
312 // | old rbp, | <- EBP
313 // +----------+
314 // | ret addr |
315 // +----------+
316 // | args |
317 // | .........|
318
319
320 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
321 // This is the offset from sp() in the frame of the slot for the index,
322 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
323 //
324 // framesize +
325 // stack0 stack0 0 <- VMReg
326 // | | <registers> |
327 // ...........|..............|.............|
328 // 0 1 2 3 x x 4 5 6 ... | <- local indices
329 // ^ ^ sp() ( x x indicate link
330 // | | and return addr)
331 // arguments non-argument locals
332
333
334 VMReg FrameMap::fpu_regname (int n) {
335 // Return the OptoReg name for the fpu stack slot "n"
336 // A spilled fpu stack slot comprises to two single-word OptoReg's.
337 return as_FloatRegister(n)->as_VMReg();
338 }
339
340 LIR_Opr FrameMap::stack_pointer() {
341 return FrameMap::rsp_opr;
342 }
343
344
345 // JSR 292
346 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
347 assert(rbp == rbp_mh_SP_save, "must be same register");
348 return rbp_opr;
349 }
350
351
352 bool FrameMap::validate_frame() {
353 return true;
354 }