1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
94
95 // Implementation of Address
96
97 #ifdef _LP64
98
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
105
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
134
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
143
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
152
153 #endif // _LP64
154
155
156
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
176
177 // Implementation of Assembler
178
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
182
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
189
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
199
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
208
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
216
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
226
227
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
242
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
252
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
267
268
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
274
275
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
281
282 // Encode the registers as needed in the fields they are used in
283
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
287
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
366
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
370
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
382
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
393
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
399
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
402
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
406
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
413
414 // If "which" is end_pc_operand, find the end of the instruction.
415
416 address ip = inst;
417 bool is_64bit = false;
418
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
421
422 again_after_prefix:
423 switch (0xFF & *ip++) {
424
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
431
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
442
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
454
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
466
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
475
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
482
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
519
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
530 #endif // _LP64
531 return ip;
532
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
538
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
547
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
553
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
567
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
583
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
589
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
594
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
603
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
610
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
616
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
626
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
641
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
649
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
665
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
668
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
688
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
700
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
706
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
710
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
737
738 default:
739 ShouldNotReachHere();
740
741 #undef REP8
742 #undef REP16
743 }
744
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
753
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
765
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
773
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
780
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
787
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
796
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
801
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
805
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
813
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
818
819
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
825
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
843
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
850
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
857
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
862
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
868
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
874
875
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
882
883
884 // Now the Assembler instructions (identical for 32/64 bits)
885
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
891
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
898
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
903
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
910
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
915
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
921
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
928
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
933
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
940
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
945
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
954
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
964
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
985
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
990
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1013
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1020
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1028
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1035
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1043
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1050
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1058
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1065
1066
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 InstructionMark im(this);
1094 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1095 int encode = vex_prefix_and_encode(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1096 emit_int8((unsigned char)0xF2);
1097 emit_int8((unsigned char)(0xC0 | encode));
1098 }
1099
1100 void Assembler::andnl(Register dst, Register src1, Address src2) {
1101 InstructionMark im(this);
1102 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1103 vex_prefix(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1104 emit_int8((unsigned char)0xF2);
1105 emit_operand(dst, src2);
1106 }
1107
1108 void Assembler::bsfl(Register dst, Register src) {
1109 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1110 emit_int8(0x0F);
1111 emit_int8((unsigned char)0xBC);
1112 emit_int8((unsigned char)(0xC0 | encode));
1113 }
1114
1115 void Assembler::bsrl(Register dst, Register src) {
1116 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1117 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1118 emit_int8(0x0F);
1119 emit_int8((unsigned char)0xBD);
1120 emit_int8((unsigned char)(0xC0 | encode));
1121 }
1122
1123 void Assembler::bswapl(Register reg) { // bswap
1124 int encode = prefix_and_encode(reg->encoding());
1125 emit_int8(0x0F);
1126 emit_int8((unsigned char)(0xC8 | encode));
1127 }
1128
1129 void Assembler::blsil(Register dst, Register src) {
1130 InstructionMark im(this);
1131 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1132 int encode = vex_prefix_and_encode(rbx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1133 emit_int8((unsigned char)0xF3);
1134 emit_int8((unsigned char)(0xC0 | encode));
1135 }
1136
1137 void Assembler::blsil(Register dst, Address src) {
1138 InstructionMark im(this);
1139 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1140 vex_prefix(rbx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1141 emit_int8((unsigned char)0xF3);
1142 emit_operand(rbx, src);
1143 }
1144
1145 void Assembler::blsmskl(Register dst, Register src) {
1146 InstructionMark im(this);
1147 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1148 int encode = vex_prefix_and_encode(rdx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1149 emit_int8((unsigned char)0xF3);
1150 emit_int8((unsigned char)(0xC0 | encode));
1151 }
1152
1153 void Assembler::blsmskl(Register dst, Address src) {
1154 InstructionMark im(this);
1155 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1156 vex_prefix(rdx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1157 emit_int8((unsigned char)0xF3);
1158 emit_operand(rdx, src);
1159 }
1160
1161 void Assembler::blsrl(Register dst, Register src) {
1162 InstructionMark im(this);
1163 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1164 int encode = vex_prefix_and_encode(rcx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1165 emit_int8((unsigned char)0xF3);
1166 emit_int8((unsigned char)(0xC0 | encode));
1167 }
1168
1169 void Assembler::blsrl(Register dst, Address src) {
1170 InstructionMark im(this);
1171 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1172 vex_prefix(rcx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, false, false);
1173 emit_int8((unsigned char)0xF3);
1174 emit_operand(rcx, src);
1175 }
1176
1177 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1178 // suspect disp32 is always good
1179 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1180
1181 if (L.is_bound()) {
1182 const int long_size = 5;
1183 int offs = (int)( target(L) - pc() );
1184 assert(offs <= 0, "assembler error");
1185 InstructionMark im(this);
1186 // 1110 1000 #32-bit disp
1187 emit_int8((unsigned char)0xE8);
1188 emit_data(offs - long_size, rtype, operand);
1189 } else {
1190 InstructionMark im(this);
1191 // 1110 1000 #32-bit disp
1192 L.add_patch_at(code(), locator());
1193
1194 emit_int8((unsigned char)0xE8);
1195 emit_data(int(0), rtype, operand);
1196 }
1197 }
1198
1199 void Assembler::call(Register dst) {
1200 int encode = prefix_and_encode(dst->encoding());
1201 emit_int8((unsigned char)0xFF);
1202 emit_int8((unsigned char)(0xD0 | encode));
1203 }
1204
1205
1206 void Assembler::call(Address adr) {
1207 InstructionMark im(this);
1208 prefix(adr);
1209 emit_int8((unsigned char)0xFF);
1210 emit_operand(rdx, adr);
1211 }
1212
1213 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1214 assert(entry != NULL, "call most probably wrong");
1215 InstructionMark im(this);
1216 emit_int8((unsigned char)0xE8);
1217 intptr_t disp = entry - (pc() + sizeof(int32_t));
1218 assert(is_simm32(disp), "must be 32bit offset (call2)");
1219 // Technically, should use call32_operand, but this format is
1220 // implied by the fact that we're emitting a call instruction.
1221
1222 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1223 emit_data((int) disp, rspec, operand);
1224 }
1225
1226 void Assembler::cdql() {
1227 emit_int8((unsigned char)0x99);
1228 }
1229
1230 void Assembler::cld() {
1231 emit_int8((unsigned char)0xFC);
1232 }
1233
1234 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1235 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1236 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1237 emit_int8(0x0F);
1238 emit_int8(0x40 | cc);
1239 emit_int8((unsigned char)(0xC0 | encode));
1240 }
1241
1242
1243 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1244 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1245 prefix(src, dst);
1246 emit_int8(0x0F);
1247 emit_int8(0x40 | cc);
1248 emit_operand(dst, src);
1249 }
1250
1251 void Assembler::cmpb(Address dst, int imm8) {
1252 InstructionMark im(this);
1253 prefix(dst);
1254 emit_int8((unsigned char)0x80);
1255 emit_operand(rdi, dst, 1);
1256 emit_int8(imm8);
1257 }
1258
1259 void Assembler::cmpl(Address dst, int32_t imm32) {
1260 InstructionMark im(this);
1261 prefix(dst);
1262 emit_int8((unsigned char)0x81);
1263 emit_operand(rdi, dst, 4);
1264 emit_int32(imm32);
1265 }
1266
1267 void Assembler::cmpl(Register dst, int32_t imm32) {
1268 prefix(dst);
1269 emit_arith(0x81, 0xF8, dst, imm32);
1270 }
1271
1272 void Assembler::cmpl(Register dst, Register src) {
1273 (void) prefix_and_encode(dst->encoding(), src->encoding());
1274 emit_arith(0x3B, 0xC0, dst, src);
1275 }
1276
1277
1278 void Assembler::cmpl(Register dst, Address src) {
1279 InstructionMark im(this);
1280 prefix(src, dst);
1281 emit_int8((unsigned char)0x3B);
1282 emit_operand(dst, src);
1283 }
1284
1285 void Assembler::cmpw(Address dst, int imm16) {
1286 InstructionMark im(this);
1287 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1288 emit_int8(0x66);
1289 emit_int8((unsigned char)0x81);
1290 emit_operand(rdi, dst, 2);
1291 emit_int16(imm16);
1292 }
1293
1294 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1295 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1296 // The ZF is set if the compared values were equal, and cleared otherwise.
1297 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1298 InstructionMark im(this);
1299 prefix(adr, reg);
1300 emit_int8(0x0F);
1301 emit_int8((unsigned char)0xB1);
1302 emit_operand(reg, adr);
1303 }
1304
1305 void Assembler::comisd(XMMRegister dst, Address src) {
1306 // NOTE: dbx seems to decode this as comiss even though the
1307 // 0x66 is there. Strangly ucomisd comes out correct
1308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1309 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1310 }
1311
1312 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1313 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1314 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1315 }
1316
1317 void Assembler::comiss(XMMRegister dst, Address src) {
1318 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1319 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1320 }
1321
1322 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1323 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1324 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1325 }
1326
1327 void Assembler::cpuid() {
1328 emit_int8(0x0F);
1329 emit_int8((unsigned char)0xA2);
1330 }
1331
1332 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1334 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1335 }
1336
1337 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1339 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1340 }
1341
1342 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1344 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1345 }
1346
1347 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1349 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1350 }
1351
1352 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1354 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1355 emit_int8(0x2A);
1356 emit_int8((unsigned char)(0xC0 | encode));
1357 }
1358
1359 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1360 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1361 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1362 }
1363
1364 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1365 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1366 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1367 emit_int8(0x2A);
1368 emit_int8((unsigned char)(0xC0 | encode));
1369 }
1370
1371 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1372 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1373 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1374 }
1375
1376 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1378 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1379 }
1380
1381 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1383 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1384 }
1385
1386
1387 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1389 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1390 emit_int8(0x2C);
1391 emit_int8((unsigned char)(0xC0 | encode));
1392 }
1393
1394 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1395 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1396 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1397 emit_int8(0x2C);
1398 emit_int8((unsigned char)(0xC0 | encode));
1399 }
1400
1401 void Assembler::decl(Address dst) {
1402 // Don't use it directly. Use MacroAssembler::decrement() instead.
1403 InstructionMark im(this);
1404 prefix(dst);
1405 emit_int8((unsigned char)0xFF);
1406 emit_operand(rcx, dst);
1407 }
1408
1409 void Assembler::divsd(XMMRegister dst, Address src) {
1410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1411 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1412 }
1413
1414 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1415 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1416 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1417 }
1418
1419 void Assembler::divss(XMMRegister dst, Address src) {
1420 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1421 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1422 }
1423
1424 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1425 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1426 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1427 }
1428
1429 void Assembler::emms() {
1430 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1431 emit_int8(0x0F);
1432 emit_int8(0x77);
1433 }
1434
1435 void Assembler::hlt() {
1436 emit_int8((unsigned char)0xF4);
1437 }
1438
1439 void Assembler::idivl(Register src) {
1440 int encode = prefix_and_encode(src->encoding());
1441 emit_int8((unsigned char)0xF7);
1442 emit_int8((unsigned char)(0xF8 | encode));
1443 }
1444
1445 void Assembler::divl(Register src) { // Unsigned
1446 int encode = prefix_and_encode(src->encoding());
1447 emit_int8((unsigned char)0xF7);
1448 emit_int8((unsigned char)(0xF0 | encode));
1449 }
1450
1451 void Assembler::imull(Register dst, Register src) {
1452 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1453 emit_int8(0x0F);
1454 emit_int8((unsigned char)0xAF);
1455 emit_int8((unsigned char)(0xC0 | encode));
1456 }
1457
1458
1459 void Assembler::imull(Register dst, Register src, int value) {
1460 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1461 if (is8bit(value)) {
1462 emit_int8(0x6B);
1463 emit_int8((unsigned char)(0xC0 | encode));
1464 emit_int8(value & 0xFF);
1465 } else {
1466 emit_int8(0x69);
1467 emit_int8((unsigned char)(0xC0 | encode));
1468 emit_int32(value);
1469 }
1470 }
1471
1472 void Assembler::imull(Register dst, Address src) {
1473 InstructionMark im(this);
1474 prefix(src, dst);
1475 emit_int8(0x0F);
1476 emit_int8((unsigned char) 0xAF);
1477 emit_operand(dst, src);
1478 }
1479
1480
1481 void Assembler::incl(Address dst) {
1482 // Don't use it directly. Use MacroAssembler::increment() instead.
1483 InstructionMark im(this);
1484 prefix(dst);
1485 emit_int8((unsigned char)0xFF);
1486 emit_operand(rax, dst);
1487 }
1488
1489 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1490 InstructionMark im(this);
1491 assert((0 <= cc) && (cc < 16), "illegal cc");
1492 if (L.is_bound()) {
1493 address dst = target(L);
1494 assert(dst != NULL, "jcc most probably wrong");
1495
1496 const int short_size = 2;
1497 const int long_size = 6;
1498 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1499 if (maybe_short && is8bit(offs - short_size)) {
1500 // 0111 tttn #8-bit disp
1501 emit_int8(0x70 | cc);
1502 emit_int8((offs - short_size) & 0xFF);
1503 } else {
1504 // 0000 1111 1000 tttn #32-bit disp
1505 assert(is_simm32(offs - long_size),
1506 "must be 32bit offset (call4)");
1507 emit_int8(0x0F);
1508 emit_int8((unsigned char)(0x80 | cc));
1509 emit_int32(offs - long_size);
1510 }
1511 } else {
1512 // Note: could eliminate cond. jumps to this jump if condition
1513 // is the same however, seems to be rather unlikely case.
1514 // Note: use jccb() if label to be bound is very close to get
1515 // an 8-bit displacement
1516 L.add_patch_at(code(), locator());
1517 emit_int8(0x0F);
1518 emit_int8((unsigned char)(0x80 | cc));
1519 emit_int32(0);
1520 }
1521 }
1522
1523 void Assembler::jccb(Condition cc, Label& L) {
1524 if (L.is_bound()) {
1525 const int short_size = 2;
1526 address entry = target(L);
1527 #ifdef ASSERT
1528 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1529 intptr_t delta = short_branch_delta();
1530 if (delta != 0) {
1531 dist += (dist < 0 ? (-delta) :delta);
1532 }
1533 assert(is8bit(dist), "Dispacement too large for a short jmp");
1534 #endif
1535 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1536 // 0111 tttn #8-bit disp
1537 emit_int8(0x70 | cc);
1538 emit_int8((offs - short_size) & 0xFF);
1539 } else {
1540 InstructionMark im(this);
1541 L.add_patch_at(code(), locator());
1542 emit_int8(0x70 | cc);
1543 emit_int8(0);
1544 }
1545 }
1546
1547 void Assembler::jmp(Address adr) {
1548 InstructionMark im(this);
1549 prefix(adr);
1550 emit_int8((unsigned char)0xFF);
1551 emit_operand(rsp, adr);
1552 }
1553
1554 void Assembler::jmp(Label& L, bool maybe_short) {
1555 if (L.is_bound()) {
1556 address entry = target(L);
1557 assert(entry != NULL, "jmp most probably wrong");
1558 InstructionMark im(this);
1559 const int short_size = 2;
1560 const int long_size = 5;
1561 intptr_t offs = entry - pc();
1562 if (maybe_short && is8bit(offs - short_size)) {
1563 emit_int8((unsigned char)0xEB);
1564 emit_int8((offs - short_size) & 0xFF);
1565 } else {
1566 emit_int8((unsigned char)0xE9);
1567 emit_int32(offs - long_size);
1568 }
1569 } else {
1570 // By default, forward jumps are always 32-bit displacements, since
1571 // we can't yet know where the label will be bound. If you're sure that
1572 // the forward jump will not run beyond 256 bytes, use jmpb to
1573 // force an 8-bit displacement.
1574 InstructionMark im(this);
1575 L.add_patch_at(code(), locator());
1576 emit_int8((unsigned char)0xE9);
1577 emit_int32(0);
1578 }
1579 }
1580
1581 void Assembler::jmp(Register entry) {
1582 int encode = prefix_and_encode(entry->encoding());
1583 emit_int8((unsigned char)0xFF);
1584 emit_int8((unsigned char)(0xE0 | encode));
1585 }
1586
1587 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1588 InstructionMark im(this);
1589 emit_int8((unsigned char)0xE9);
1590 assert(dest != NULL, "must have a target");
1591 intptr_t disp = dest - (pc() + sizeof(int32_t));
1592 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1593 emit_data(disp, rspec.reloc(), call32_operand);
1594 }
1595
1596 void Assembler::jmpb(Label& L) {
1597 if (L.is_bound()) {
1598 const int short_size = 2;
1599 address entry = target(L);
1600 assert(entry != NULL, "jmp most probably wrong");
1601 #ifdef ASSERT
1602 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1603 intptr_t delta = short_branch_delta();
1604 if (delta != 0) {
1605 dist += (dist < 0 ? (-delta) :delta);
1606 }
1607 assert(is8bit(dist), "Dispacement too large for a short jmp");
1608 #endif
1609 intptr_t offs = entry - pc();
1610 emit_int8((unsigned char)0xEB);
1611 emit_int8((offs - short_size) & 0xFF);
1612 } else {
1613 InstructionMark im(this);
1614 L.add_patch_at(code(), locator());
1615 emit_int8((unsigned char)0xEB);
1616 emit_int8(0);
1617 }
1618 }
1619
1620 void Assembler::ldmxcsr( Address src) {
1621 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1622 InstructionMark im(this);
1623 prefix(src);
1624 emit_int8(0x0F);
1625 emit_int8((unsigned char)0xAE);
1626 emit_operand(as_Register(2), src);
1627 }
1628
1629 void Assembler::leal(Register dst, Address src) {
1630 InstructionMark im(this);
1631 #ifdef _LP64
1632 emit_int8(0x67); // addr32
1633 prefix(src, dst);
1634 #endif // LP64
1635 emit_int8((unsigned char)0x8D);
1636 emit_operand(dst, src);
1637 }
1638
1639 void Assembler::lfence() {
1640 emit_int8(0x0F);
1641 emit_int8((unsigned char)0xAE);
1642 emit_int8((unsigned char)0xE8);
1643 }
1644
1645 void Assembler::lock() {
1646 emit_int8((unsigned char)0xF0);
1647 }
1648
1649 void Assembler::lzcntl(Register dst, Register src) {
1650 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1651 emit_int8((unsigned char)0xF3);
1652 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1653 emit_int8(0x0F);
1654 emit_int8((unsigned char)0xBD);
1655 emit_int8((unsigned char)(0xC0 | encode));
1656 }
1657
1658 // Emit mfence instruction
1659 void Assembler::mfence() {
1660 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1661 emit_int8(0x0F);
1662 emit_int8((unsigned char)0xAE);
1663 emit_int8((unsigned char)0xF0);
1664 }
1665
1666 void Assembler::mov(Register dst, Register src) {
1667 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1668 }
1669
1670 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1671 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1672 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1673 }
1674
1675 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1676 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1677 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1678 }
1679
1680 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1681 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1682 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1683 emit_int8(0x16);
1684 emit_int8((unsigned char)(0xC0 | encode));
1685 }
1686
1687 void Assembler::movb(Register dst, Address src) {
1688 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1689 InstructionMark im(this);
1690 prefix(src, dst, true);
1691 emit_int8((unsigned char)0x8A);
1692 emit_operand(dst, src);
1693 }
1694
1695
1696 void Assembler::movb(Address dst, int imm8) {
1697 InstructionMark im(this);
1698 prefix(dst);
1699 emit_int8((unsigned char)0xC6);
1700 emit_operand(rax, dst, 1);
1701 emit_int8(imm8);
1702 }
1703
1704
1705 void Assembler::movb(Address dst, Register src) {
1706 assert(src->has_byte_register(), "must have byte register");
1707 InstructionMark im(this);
1708 prefix(dst, src, true);
1709 emit_int8((unsigned char)0x88);
1710 emit_operand(src, dst);
1711 }
1712
1713 void Assembler::movdl(XMMRegister dst, Register src) {
1714 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1715 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1716 emit_int8(0x6E);
1717 emit_int8((unsigned char)(0xC0 | encode));
1718 }
1719
1720 void Assembler::movdl(Register dst, XMMRegister src) {
1721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1722 // swap src/dst to get correct prefix
1723 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1724 emit_int8(0x7E);
1725 emit_int8((unsigned char)(0xC0 | encode));
1726 }
1727
1728 void Assembler::movdl(XMMRegister dst, Address src) {
1729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1730 InstructionMark im(this);
1731 simd_prefix(dst, src, VEX_SIMD_66);
1732 emit_int8(0x6E);
1733 emit_operand(dst, src);
1734 }
1735
1736 void Assembler::movdl(Address dst, XMMRegister src) {
1737 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1738 InstructionMark im(this);
1739 simd_prefix(dst, src, VEX_SIMD_66);
1740 emit_int8(0x7E);
1741 emit_operand(src, dst);
1742 }
1743
1744 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1746 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1747 }
1748
1749 void Assembler::movdqa(XMMRegister dst, Address src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1752 }
1753
1754 void Assembler::movdqu(XMMRegister dst, Address src) {
1755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1756 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1757 }
1758
1759 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1762 }
1763
1764 void Assembler::movdqu(Address dst, XMMRegister src) {
1765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1766 InstructionMark im(this);
1767 simd_prefix(dst, src, VEX_SIMD_F3);
1768 emit_int8(0x7F);
1769 emit_operand(src, dst);
1770 }
1771
1772 // Move Unaligned 256bit Vector
1773 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1774 assert(UseAVX, "");
1775 bool vector256 = true;
1776 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1777 emit_int8(0x6F);
1778 emit_int8((unsigned char)(0xC0 | encode));
1779 }
1780
1781 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1782 assert(UseAVX, "");
1783 InstructionMark im(this);
1784 bool vector256 = true;
1785 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1786 emit_int8(0x6F);
1787 emit_operand(dst, src);
1788 }
1789
1790 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1791 assert(UseAVX, "");
1792 InstructionMark im(this);
1793 bool vector256 = true;
1794 // swap src<->dst for encoding
1795 assert(src != xnoreg, "sanity");
1796 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1797 emit_int8(0x7F);
1798 emit_operand(src, dst);
1799 }
1800
1801 // Uses zero extension on 64bit
1802
1803 void Assembler::movl(Register dst, int32_t imm32) {
1804 int encode = prefix_and_encode(dst->encoding());
1805 emit_int8((unsigned char)(0xB8 | encode));
1806 emit_int32(imm32);
1807 }
1808
1809 void Assembler::movl(Register dst, Register src) {
1810 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1811 emit_int8((unsigned char)0x8B);
1812 emit_int8((unsigned char)(0xC0 | encode));
1813 }
1814
1815 void Assembler::movl(Register dst, Address src) {
1816 InstructionMark im(this);
1817 prefix(src, dst);
1818 emit_int8((unsigned char)0x8B);
1819 emit_operand(dst, src);
1820 }
1821
1822 void Assembler::movl(Address dst, int32_t imm32) {
1823 InstructionMark im(this);
1824 prefix(dst);
1825 emit_int8((unsigned char)0xC7);
1826 emit_operand(rax, dst, 4);
1827 emit_int32(imm32);
1828 }
1829
1830 void Assembler::movl(Address dst, Register src) {
1831 InstructionMark im(this);
1832 prefix(dst, src);
1833 emit_int8((unsigned char)0x89);
1834 emit_operand(src, dst);
1835 }
1836
1837 // New cpus require to use movsd and movss to avoid partial register stall
1838 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1839 // The selection is done in MacroAssembler::movdbl() and movflt().
1840 void Assembler::movlpd(XMMRegister dst, Address src) {
1841 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1842 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1843 }
1844
1845 void Assembler::movq( MMXRegister dst, Address src ) {
1846 assert( VM_Version::supports_mmx(), "" );
1847 emit_int8(0x0F);
1848 emit_int8(0x6F);
1849 emit_operand(dst, src);
1850 }
1851
1852 void Assembler::movq( Address dst, MMXRegister src ) {
1853 assert( VM_Version::supports_mmx(), "" );
1854 emit_int8(0x0F);
1855 emit_int8(0x7F);
1856 // workaround gcc (3.2.1-7a) bug
1857 // In that version of gcc with only an emit_operand(MMX, Address)
1858 // gcc will tail jump and try and reverse the parameters completely
1859 // obliterating dst in the process. By having a version available
1860 // that doesn't need to swap the args at the tail jump the bug is
1861 // avoided.
1862 emit_operand(dst, src);
1863 }
1864
1865 void Assembler::movq(XMMRegister dst, Address src) {
1866 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1867 InstructionMark im(this);
1868 simd_prefix(dst, src, VEX_SIMD_F3);
1869 emit_int8(0x7E);
1870 emit_operand(dst, src);
1871 }
1872
1873 void Assembler::movq(Address dst, XMMRegister src) {
1874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1875 InstructionMark im(this);
1876 simd_prefix(dst, src, VEX_SIMD_66);
1877 emit_int8((unsigned char)0xD6);
1878 emit_operand(src, dst);
1879 }
1880
1881 void Assembler::movsbl(Register dst, Address src) { // movsxb
1882 InstructionMark im(this);
1883 prefix(src, dst);
1884 emit_int8(0x0F);
1885 emit_int8((unsigned char)0xBE);
1886 emit_operand(dst, src);
1887 }
1888
1889 void Assembler::movsbl(Register dst, Register src) { // movsxb
1890 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1891 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1892 emit_int8(0x0F);
1893 emit_int8((unsigned char)0xBE);
1894 emit_int8((unsigned char)(0xC0 | encode));
1895 }
1896
1897 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1899 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1900 }
1901
1902 void Assembler::movsd(XMMRegister dst, Address src) {
1903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1904 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1905 }
1906
1907 void Assembler::movsd(Address dst, XMMRegister src) {
1908 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1909 InstructionMark im(this);
1910 simd_prefix(dst, src, VEX_SIMD_F2);
1911 emit_int8(0x11);
1912 emit_operand(src, dst);
1913 }
1914
1915 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1916 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1917 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1918 }
1919
1920 void Assembler::movss(XMMRegister dst, Address src) {
1921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1922 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1923 }
1924
1925 void Assembler::movss(Address dst, XMMRegister src) {
1926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1927 InstructionMark im(this);
1928 simd_prefix(dst, src, VEX_SIMD_F3);
1929 emit_int8(0x11);
1930 emit_operand(src, dst);
1931 }
1932
1933 void Assembler::movswl(Register dst, Address src) { // movsxw
1934 InstructionMark im(this);
1935 prefix(src, dst);
1936 emit_int8(0x0F);
1937 emit_int8((unsigned char)0xBF);
1938 emit_operand(dst, src);
1939 }
1940
1941 void Assembler::movswl(Register dst, Register src) { // movsxw
1942 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char)0xBF);
1945 emit_int8((unsigned char)(0xC0 | encode));
1946 }
1947
1948 void Assembler::movw(Address dst, int imm16) {
1949 InstructionMark im(this);
1950
1951 emit_int8(0x66); // switch to 16-bit mode
1952 prefix(dst);
1953 emit_int8((unsigned char)0xC7);
1954 emit_operand(rax, dst, 2);
1955 emit_int16(imm16);
1956 }
1957
1958 void Assembler::movw(Register dst, Address src) {
1959 InstructionMark im(this);
1960 emit_int8(0x66);
1961 prefix(src, dst);
1962 emit_int8((unsigned char)0x8B);
1963 emit_operand(dst, src);
1964 }
1965
1966 void Assembler::movw(Address dst, Register src) {
1967 InstructionMark im(this);
1968 emit_int8(0x66);
1969 prefix(dst, src);
1970 emit_int8((unsigned char)0x89);
1971 emit_operand(src, dst);
1972 }
1973
1974 void Assembler::movzbl(Register dst, Address src) { // movzxb
1975 InstructionMark im(this);
1976 prefix(src, dst);
1977 emit_int8(0x0F);
1978 emit_int8((unsigned char)0xB6);
1979 emit_operand(dst, src);
1980 }
1981
1982 void Assembler::movzbl(Register dst, Register src) { // movzxb
1983 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1984 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1985 emit_int8(0x0F);
1986 emit_int8((unsigned char)0xB6);
1987 emit_int8(0xC0 | encode);
1988 }
1989
1990 void Assembler::movzwl(Register dst, Address src) { // movzxw
1991 InstructionMark im(this);
1992 prefix(src, dst);
1993 emit_int8(0x0F);
1994 emit_int8((unsigned char)0xB7);
1995 emit_operand(dst, src);
1996 }
1997
1998 void Assembler::movzwl(Register dst, Register src) { // movzxw
1999 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2000 emit_int8(0x0F);
2001 emit_int8((unsigned char)0xB7);
2002 emit_int8(0xC0 | encode);
2003 }
2004
2005 void Assembler::mull(Address src) {
2006 InstructionMark im(this);
2007 prefix(src);
2008 emit_int8((unsigned char)0xF7);
2009 emit_operand(rsp, src);
2010 }
2011
2012 void Assembler::mull(Register src) {
2013 int encode = prefix_and_encode(src->encoding());
2014 emit_int8((unsigned char)0xF7);
2015 emit_int8((unsigned char)(0xE0 | encode));
2016 }
2017
2018 void Assembler::mulsd(XMMRegister dst, Address src) {
2019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2020 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2021 }
2022
2023 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2024 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2025 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2026 }
2027
2028 void Assembler::mulss(XMMRegister dst, Address src) {
2029 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2030 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2031 }
2032
2033 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2034 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2035 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2036 }
2037
2038 void Assembler::negl(Register dst) {
2039 int encode = prefix_and_encode(dst->encoding());
2040 emit_int8((unsigned char)0xF7);
2041 emit_int8((unsigned char)(0xD8 | encode));
2042 }
2043
2044 void Assembler::nop(int i) {
2045 #ifdef ASSERT
2046 assert(i > 0, " ");
2047 // The fancy nops aren't currently recognized by debuggers making it a
2048 // pain to disassemble code while debugging. If asserts are on clearly
2049 // speed is not an issue so simply use the single byte traditional nop
2050 // to do alignment.
2051
2052 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2053 return;
2054
2055 #endif // ASSERT
2056
2057 if (UseAddressNop && VM_Version::is_intel()) {
2058 //
2059 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2060 // 1: 0x90
2061 // 2: 0x66 0x90
2062 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2063 // 4: 0x0F 0x1F 0x40 0x00
2064 // 5: 0x0F 0x1F 0x44 0x00 0x00
2065 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2066 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2067 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2068 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2069 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2070 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2071
2072 // The rest coding is Intel specific - don't use consecutive address nops
2073
2074 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2075 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2076 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2077 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2078
2079 while(i >= 15) {
2080 // For Intel don't generate consecutive addess nops (mix with regular nops)
2081 i -= 15;
2082 emit_int8(0x66); // size prefix
2083 emit_int8(0x66); // size prefix
2084 emit_int8(0x66); // size prefix
2085 addr_nop_8();
2086 emit_int8(0x66); // size prefix
2087 emit_int8(0x66); // size prefix
2088 emit_int8(0x66); // size prefix
2089 emit_int8((unsigned char)0x90);
2090 // nop
2091 }
2092 switch (i) {
2093 case 14:
2094 emit_int8(0x66); // size prefix
2095 case 13:
2096 emit_int8(0x66); // size prefix
2097 case 12:
2098 addr_nop_8();
2099 emit_int8(0x66); // size prefix
2100 emit_int8(0x66); // size prefix
2101 emit_int8(0x66); // size prefix
2102 emit_int8((unsigned char)0x90);
2103 // nop
2104 break;
2105 case 11:
2106 emit_int8(0x66); // size prefix
2107 case 10:
2108 emit_int8(0x66); // size prefix
2109 case 9:
2110 emit_int8(0x66); // size prefix
2111 case 8:
2112 addr_nop_8();
2113 break;
2114 case 7:
2115 addr_nop_7();
2116 break;
2117 case 6:
2118 emit_int8(0x66); // size prefix
2119 case 5:
2120 addr_nop_5();
2121 break;
2122 case 4:
2123 addr_nop_4();
2124 break;
2125 case 3:
2126 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2127 emit_int8(0x66); // size prefix
2128 case 2:
2129 emit_int8(0x66); // size prefix
2130 case 1:
2131 emit_int8((unsigned char)0x90);
2132 // nop
2133 break;
2134 default:
2135 assert(i == 0, " ");
2136 }
2137 return;
2138 }
2139 if (UseAddressNop && VM_Version::is_amd()) {
2140 //
2141 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2142 // 1: 0x90
2143 // 2: 0x66 0x90
2144 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2145 // 4: 0x0F 0x1F 0x40 0x00
2146 // 5: 0x0F 0x1F 0x44 0x00 0x00
2147 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2148 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2149 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2150 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2151 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2152 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2153
2154 // The rest coding is AMD specific - use consecutive address nops
2155
2156 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2157 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2158 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2159 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2160 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2161 // Size prefixes (0x66) are added for larger sizes
2162
2163 while(i >= 22) {
2164 i -= 11;
2165 emit_int8(0x66); // size prefix
2166 emit_int8(0x66); // size prefix
2167 emit_int8(0x66); // size prefix
2168 addr_nop_8();
2169 }
2170 // Generate first nop for size between 21-12
2171 switch (i) {
2172 case 21:
2173 i -= 1;
2174 emit_int8(0x66); // size prefix
2175 case 20:
2176 case 19:
2177 i -= 1;
2178 emit_int8(0x66); // size prefix
2179 case 18:
2180 case 17:
2181 i -= 1;
2182 emit_int8(0x66); // size prefix
2183 case 16:
2184 case 15:
2185 i -= 8;
2186 addr_nop_8();
2187 break;
2188 case 14:
2189 case 13:
2190 i -= 7;
2191 addr_nop_7();
2192 break;
2193 case 12:
2194 i -= 6;
2195 emit_int8(0x66); // size prefix
2196 addr_nop_5();
2197 break;
2198 default:
2199 assert(i < 12, " ");
2200 }
2201
2202 // Generate second nop for size between 11-1
2203 switch (i) {
2204 case 11:
2205 emit_int8(0x66); // size prefix
2206 case 10:
2207 emit_int8(0x66); // size prefix
2208 case 9:
2209 emit_int8(0x66); // size prefix
2210 case 8:
2211 addr_nop_8();
2212 break;
2213 case 7:
2214 addr_nop_7();
2215 break;
2216 case 6:
2217 emit_int8(0x66); // size prefix
2218 case 5:
2219 addr_nop_5();
2220 break;
2221 case 4:
2222 addr_nop_4();
2223 break;
2224 case 3:
2225 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2226 emit_int8(0x66); // size prefix
2227 case 2:
2228 emit_int8(0x66); // size prefix
2229 case 1:
2230 emit_int8((unsigned char)0x90);
2231 // nop
2232 break;
2233 default:
2234 assert(i == 0, " ");
2235 }
2236 return;
2237 }
2238
2239 // Using nops with size prefixes "0x66 0x90".
2240 // From AMD Optimization Guide:
2241 // 1: 0x90
2242 // 2: 0x66 0x90
2243 // 3: 0x66 0x66 0x90
2244 // 4: 0x66 0x66 0x66 0x90
2245 // 5: 0x66 0x66 0x90 0x66 0x90
2246 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2247 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2248 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2249 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2250 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2251 //
2252 while(i > 12) {
2253 i -= 4;
2254 emit_int8(0x66); // size prefix
2255 emit_int8(0x66);
2256 emit_int8(0x66);
2257 emit_int8((unsigned char)0x90);
2258 // nop
2259 }
2260 // 1 - 12 nops
2261 if(i > 8) {
2262 if(i > 9) {
2263 i -= 1;
2264 emit_int8(0x66);
2265 }
2266 i -= 3;
2267 emit_int8(0x66);
2268 emit_int8(0x66);
2269 emit_int8((unsigned char)0x90);
2270 }
2271 // 1 - 8 nops
2272 if(i > 4) {
2273 if(i > 6) {
2274 i -= 1;
2275 emit_int8(0x66);
2276 }
2277 i -= 3;
2278 emit_int8(0x66);
2279 emit_int8(0x66);
2280 emit_int8((unsigned char)0x90);
2281 }
2282 switch (i) {
2283 case 4:
2284 emit_int8(0x66);
2285 case 3:
2286 emit_int8(0x66);
2287 case 2:
2288 emit_int8(0x66);
2289 case 1:
2290 emit_int8((unsigned char)0x90);
2291 break;
2292 default:
2293 assert(i == 0, " ");
2294 }
2295 }
2296
2297 void Assembler::notl(Register dst) {
2298 int encode = prefix_and_encode(dst->encoding());
2299 emit_int8((unsigned char)0xF7);
2300 emit_int8((unsigned char)(0xD0 | encode));
2301 }
2302
2303 void Assembler::orl(Address dst, int32_t imm32) {
2304 InstructionMark im(this);
2305 prefix(dst);
2306 emit_arith_operand(0x81, rcx, dst, imm32);
2307 }
2308
2309 void Assembler::orl(Register dst, int32_t imm32) {
2310 prefix(dst);
2311 emit_arith(0x81, 0xC8, dst, imm32);
2312 }
2313
2314 void Assembler::orl(Register dst, Address src) {
2315 InstructionMark im(this);
2316 prefix(src, dst);
2317 emit_int8(0x0B);
2318 emit_operand(dst, src);
2319 }
2320
2321 void Assembler::orl(Register dst, Register src) {
2322 (void) prefix_and_encode(dst->encoding(), src->encoding());
2323 emit_arith(0x0B, 0xC0, dst, src);
2324 }
2325
2326 void Assembler::packuswb(XMMRegister dst, Address src) {
2327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2328 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2329 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2330 }
2331
2332 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2334 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2335 }
2336
2337 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2338 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2339 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2340 }
2341
2342 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2343 assert(VM_Version::supports_avx2(), "");
2344 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2345 emit_int8(0x00);
2346 emit_int8(0xC0 | encode);
2347 emit_int8(imm8);
2348 }
2349
2350 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2351 assert(VM_Version::supports_sse4_2(), "");
2352 InstructionMark im(this);
2353 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2354 emit_int8(0x61);
2355 emit_operand(dst, src);
2356 emit_int8(imm8);
2357 }
2358
2359 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2360 assert(VM_Version::supports_sse4_2(), "");
2361 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2362 emit_int8(0x61);
2363 emit_int8((unsigned char)(0xC0 | encode));
2364 emit_int8(imm8);
2365 }
2366
2367 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2368 assert(VM_Version::supports_sse4_1(), "");
2369 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2370 emit_int8(0x16);
2371 emit_int8((unsigned char)(0xC0 | encode));
2372 emit_int8(imm8);
2373 }
2374
2375 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2376 assert(VM_Version::supports_sse4_1(), "");
2377 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2378 emit_int8(0x16);
2379 emit_int8((unsigned char)(0xC0 | encode));
2380 emit_int8(imm8);
2381 }
2382
2383 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2384 assert(VM_Version::supports_sse4_1(), "");
2385 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2386 emit_int8(0x22);
2387 emit_int8((unsigned char)(0xC0 | encode));
2388 emit_int8(imm8);
2389 }
2390
2391 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2392 assert(VM_Version::supports_sse4_1(), "");
2393 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2394 emit_int8(0x22);
2395 emit_int8((unsigned char)(0xC0 | encode));
2396 emit_int8(imm8);
2397 }
2398
2399 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2400 assert(VM_Version::supports_sse4_1(), "");
2401 InstructionMark im(this);
2402 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2403 emit_int8(0x30);
2404 emit_operand(dst, src);
2405 }
2406
2407 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2408 assert(VM_Version::supports_sse4_1(), "");
2409 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2410 emit_int8(0x30);
2411 emit_int8((unsigned char)(0xC0 | encode));
2412 }
2413
2414 // generic
2415 void Assembler::pop(Register dst) {
2416 int encode = prefix_and_encode(dst->encoding());
2417 emit_int8(0x58 | encode);
2418 }
2419
2420 void Assembler::popcntl(Register dst, Address src) {
2421 assert(VM_Version::supports_popcnt(), "must support");
2422 InstructionMark im(this);
2423 emit_int8((unsigned char)0xF3);
2424 prefix(src, dst);
2425 emit_int8(0x0F);
2426 emit_int8((unsigned char)0xB8);
2427 emit_operand(dst, src);
2428 }
2429
2430 void Assembler::popcntl(Register dst, Register src) {
2431 assert(VM_Version::supports_popcnt(), "must support");
2432 emit_int8((unsigned char)0xF3);
2433 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2434 emit_int8(0x0F);
2435 emit_int8((unsigned char)0xB8);
2436 emit_int8((unsigned char)(0xC0 | encode));
2437 }
2438
2439 void Assembler::popf() {
2440 emit_int8((unsigned char)0x9D);
2441 }
2442
2443 #ifndef _LP64 // no 32bit push/pop on amd64
2444 void Assembler::popl(Address dst) {
2445 // NOTE: this will adjust stack by 8byte on 64bits
2446 InstructionMark im(this);
2447 prefix(dst);
2448 emit_int8((unsigned char)0x8F);
2449 emit_operand(rax, dst);
2450 }
2451 #endif
2452
2453 void Assembler::prefetch_prefix(Address src) {
2454 prefix(src);
2455 emit_int8(0x0F);
2456 }
2457
2458 void Assembler::prefetchnta(Address src) {
2459 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2460 InstructionMark im(this);
2461 prefetch_prefix(src);
2462 emit_int8(0x18);
2463 emit_operand(rax, src); // 0, src
2464 }
2465
2466 void Assembler::prefetchr(Address src) {
2467 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2468 InstructionMark im(this);
2469 prefetch_prefix(src);
2470 emit_int8(0x0D);
2471 emit_operand(rax, src); // 0, src
2472 }
2473
2474 void Assembler::prefetcht0(Address src) {
2475 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2476 InstructionMark im(this);
2477 prefetch_prefix(src);
2478 emit_int8(0x18);
2479 emit_operand(rcx, src); // 1, src
2480 }
2481
2482 void Assembler::prefetcht1(Address src) {
2483 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2484 InstructionMark im(this);
2485 prefetch_prefix(src);
2486 emit_int8(0x18);
2487 emit_operand(rdx, src); // 2, src
2488 }
2489
2490 void Assembler::prefetcht2(Address src) {
2491 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2492 InstructionMark im(this);
2493 prefetch_prefix(src);
2494 emit_int8(0x18);
2495 emit_operand(rbx, src); // 3, src
2496 }
2497
2498 void Assembler::prefetchw(Address src) {
2499 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2500 InstructionMark im(this);
2501 prefetch_prefix(src);
2502 emit_int8(0x0D);
2503 emit_operand(rcx, src); // 1, src
2504 }
2505
2506 void Assembler::prefix(Prefix p) {
2507 emit_int8(p);
2508 }
2509
2510 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2511 assert(VM_Version::supports_ssse3(), "");
2512 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2513 emit_int8(0x00);
2514 emit_int8((unsigned char)(0xC0 | encode));
2515 }
2516
2517 void Assembler::pshufb(XMMRegister dst, Address src) {
2518 assert(VM_Version::supports_ssse3(), "");
2519 InstructionMark im(this);
2520 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2521 emit_int8(0x00);
2522 emit_operand(dst, src);
2523 }
2524
2525 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2526 assert(isByte(mode), "invalid value");
2527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2528 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2529 emit_int8(mode & 0xFF);
2530
2531 }
2532
2533 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2534 assert(isByte(mode), "invalid value");
2535 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2536 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2537 InstructionMark im(this);
2538 simd_prefix(dst, src, VEX_SIMD_66);
2539 emit_int8(0x70);
2540 emit_operand(dst, src);
2541 emit_int8(mode & 0xFF);
2542 }
2543
2544 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2545 assert(isByte(mode), "invalid value");
2546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2547 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2548 emit_int8(mode & 0xFF);
2549 }
2550
2551 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2552 assert(isByte(mode), "invalid value");
2553 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2554 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2555 InstructionMark im(this);
2556 simd_prefix(dst, src, VEX_SIMD_F2);
2557 emit_int8(0x70);
2558 emit_operand(dst, src);
2559 emit_int8(mode & 0xFF);
2560 }
2561
2562 void Assembler::psrldq(XMMRegister dst, int shift) {
2563 // Shift 128 bit value in xmm register by number of bytes.
2564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2565 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2566 emit_int8(0x73);
2567 emit_int8((unsigned char)(0xC0 | encode));
2568 emit_int8(shift);
2569 }
2570
2571 void Assembler::ptest(XMMRegister dst, Address src) {
2572 assert(VM_Version::supports_sse4_1(), "");
2573 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2574 InstructionMark im(this);
2575 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2576 emit_int8(0x17);
2577 emit_operand(dst, src);
2578 }
2579
2580 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2581 assert(VM_Version::supports_sse4_1(), "");
2582 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2583 emit_int8(0x17);
2584 emit_int8((unsigned char)(0xC0 | encode));
2585 }
2586
2587 void Assembler::vptest(XMMRegister dst, Address src) {
2588 assert(VM_Version::supports_avx(), "");
2589 InstructionMark im(this);
2590 bool vector256 = true;
2591 assert(dst != xnoreg, "sanity");
2592 int dst_enc = dst->encoding();
2593 // swap src<->dst for encoding
2594 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2595 emit_int8(0x17);
2596 emit_operand(dst, src);
2597 }
2598
2599 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2600 assert(VM_Version::supports_avx(), "");
2601 bool vector256 = true;
2602 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2603 emit_int8(0x17);
2604 emit_int8((unsigned char)(0xC0 | encode));
2605 }
2606
2607 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2609 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2610 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2611 }
2612
2613 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2615 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2616 }
2617
2618 void Assembler::punpckldq(XMMRegister dst, Address src) {
2619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2620 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2621 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2622 }
2623
2624 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2626 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2627 }
2628
2629 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2630 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2631 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2632 }
2633
2634 void Assembler::push(int32_t imm32) {
2635 // in 64bits we push 64bits onto the stack but only
2636 // take a 32bit immediate
2637 emit_int8(0x68);
2638 emit_int32(imm32);
2639 }
2640
2641 void Assembler::push(Register src) {
2642 int encode = prefix_and_encode(src->encoding());
2643
2644 emit_int8(0x50 | encode);
2645 }
2646
2647 void Assembler::pushf() {
2648 emit_int8((unsigned char)0x9C);
2649 }
2650
2651 #ifndef _LP64 // no 32bit push/pop on amd64
2652 void Assembler::pushl(Address src) {
2653 // Note this will push 64bit on 64bit
2654 InstructionMark im(this);
2655 prefix(src);
2656 emit_int8((unsigned char)0xFF);
2657 emit_operand(rsi, src);
2658 }
2659 #endif
2660
2661 void Assembler::rcll(Register dst, int imm8) {
2662 assert(isShiftCount(imm8), "illegal shift count");
2663 int encode = prefix_and_encode(dst->encoding());
2664 if (imm8 == 1) {
2665 emit_int8((unsigned char)0xD1);
2666 emit_int8((unsigned char)(0xD0 | encode));
2667 } else {
2668 emit_int8((unsigned char)0xC1);
2669 emit_int8((unsigned char)0xD0 | encode);
2670 emit_int8(imm8);
2671 }
2672 }
2673
2674 // copies data from [esi] to [edi] using rcx pointer sized words
2675 // generic
2676 void Assembler::rep_mov() {
2677 emit_int8((unsigned char)0xF3);
2678 // MOVSQ
2679 LP64_ONLY(prefix(REX_W));
2680 emit_int8((unsigned char)0xA5);
2681 }
2682
2683 // sets rcx bytes with rax, value at [edi]
2684 void Assembler::rep_stosb() {
2685 emit_int8((unsigned char)0xF3); // REP
2686 LP64_ONLY(prefix(REX_W));
2687 emit_int8((unsigned char)0xAA); // STOSB
2688 }
2689
2690 // sets rcx pointer sized words with rax, value at [edi]
2691 // generic
2692 void Assembler::rep_stos() {
2693 emit_int8((unsigned char)0xF3); // REP
2694 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2695 emit_int8((unsigned char)0xAB);
2696 }
2697
2698 // scans rcx pointer sized words at [edi] for occurance of rax,
2699 // generic
2700 void Assembler::repne_scan() { // repne_scan
2701 emit_int8((unsigned char)0xF2);
2702 // SCASQ
2703 LP64_ONLY(prefix(REX_W));
2704 emit_int8((unsigned char)0xAF);
2705 }
2706
2707 #ifdef _LP64
2708 // scans rcx 4 byte words at [edi] for occurance of rax,
2709 // generic
2710 void Assembler::repne_scanl() { // repne_scan
2711 emit_int8((unsigned char)0xF2);
2712 // SCASL
2713 emit_int8((unsigned char)0xAF);
2714 }
2715 #endif
2716
2717 void Assembler::ret(int imm16) {
2718 if (imm16 == 0) {
2719 emit_int8((unsigned char)0xC3);
2720 } else {
2721 emit_int8((unsigned char)0xC2);
2722 emit_int16(imm16);
2723 }
2724 }
2725
2726 void Assembler::sahf() {
2727 #ifdef _LP64
2728 // Not supported in 64bit mode
2729 ShouldNotReachHere();
2730 #endif
2731 emit_int8((unsigned char)0x9E);
2732 }
2733
2734 void Assembler::sarl(Register dst, int imm8) {
2735 int encode = prefix_and_encode(dst->encoding());
2736 assert(isShiftCount(imm8), "illegal shift count");
2737 if (imm8 == 1) {
2738 emit_int8((unsigned char)0xD1);
2739 emit_int8((unsigned char)(0xF8 | encode));
2740 } else {
2741 emit_int8((unsigned char)0xC1);
2742 emit_int8((unsigned char)(0xF8 | encode));
2743 emit_int8(imm8);
2744 }
2745 }
2746
2747 void Assembler::sarl(Register dst) {
2748 int encode = prefix_and_encode(dst->encoding());
2749 emit_int8((unsigned char)0xD3);
2750 emit_int8((unsigned char)(0xF8 | encode));
2751 }
2752
2753 void Assembler::sbbl(Address dst, int32_t imm32) {
2754 InstructionMark im(this);
2755 prefix(dst);
2756 emit_arith_operand(0x81, rbx, dst, imm32);
2757 }
2758
2759 void Assembler::sbbl(Register dst, int32_t imm32) {
2760 prefix(dst);
2761 emit_arith(0x81, 0xD8, dst, imm32);
2762 }
2763
2764
2765 void Assembler::sbbl(Register dst, Address src) {
2766 InstructionMark im(this);
2767 prefix(src, dst);
2768 emit_int8(0x1B);
2769 emit_operand(dst, src);
2770 }
2771
2772 void Assembler::sbbl(Register dst, Register src) {
2773 (void) prefix_and_encode(dst->encoding(), src->encoding());
2774 emit_arith(0x1B, 0xC0, dst, src);
2775 }
2776
2777 void Assembler::setb(Condition cc, Register dst) {
2778 assert(0 <= cc && cc < 16, "illegal cc");
2779 int encode = prefix_and_encode(dst->encoding(), true);
2780 emit_int8(0x0F);
2781 emit_int8((unsigned char)0x90 | cc);
2782 emit_int8((unsigned char)(0xC0 | encode));
2783 }
2784
2785 void Assembler::shll(Register dst, int imm8) {
2786 assert(isShiftCount(imm8), "illegal shift count");
2787 int encode = prefix_and_encode(dst->encoding());
2788 if (imm8 == 1 ) {
2789 emit_int8((unsigned char)0xD1);
2790 emit_int8((unsigned char)(0xE0 | encode));
2791 } else {
2792 emit_int8((unsigned char)0xC1);
2793 emit_int8((unsigned char)(0xE0 | encode));
2794 emit_int8(imm8);
2795 }
2796 }
2797
2798 void Assembler::shll(Register dst) {
2799 int encode = prefix_and_encode(dst->encoding());
2800 emit_int8((unsigned char)0xD3);
2801 emit_int8((unsigned char)(0xE0 | encode));
2802 }
2803
2804 void Assembler::shrl(Register dst, int imm8) {
2805 assert(isShiftCount(imm8), "illegal shift count");
2806 int encode = prefix_and_encode(dst->encoding());
2807 emit_int8((unsigned char)0xC1);
2808 emit_int8((unsigned char)(0xE8 | encode));
2809 emit_int8(imm8);
2810 }
2811
2812 void Assembler::shrl(Register dst) {
2813 int encode = prefix_and_encode(dst->encoding());
2814 emit_int8((unsigned char)0xD3);
2815 emit_int8((unsigned char)(0xE8 | encode));
2816 }
2817
2818 // copies a single word from [esi] to [edi]
2819 void Assembler::smovl() {
2820 emit_int8((unsigned char)0xA5);
2821 }
2822
2823 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2825 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2826 }
2827
2828 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2829 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2830 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2831 }
2832
2833 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2834 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2835 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2836 }
2837
2838 void Assembler::std() {
2839 emit_int8((unsigned char)0xFD);
2840 }
2841
2842 void Assembler::sqrtss(XMMRegister dst, Address src) {
2843 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2844 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2845 }
2846
2847 void Assembler::stmxcsr( Address dst) {
2848 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2849 InstructionMark im(this);
2850 prefix(dst);
2851 emit_int8(0x0F);
2852 emit_int8((unsigned char)0xAE);
2853 emit_operand(as_Register(3), dst);
2854 }
2855
2856 void Assembler::subl(Address dst, int32_t imm32) {
2857 InstructionMark im(this);
2858 prefix(dst);
2859 emit_arith_operand(0x81, rbp, dst, imm32);
2860 }
2861
2862 void Assembler::subl(Address dst, Register src) {
2863 InstructionMark im(this);
2864 prefix(dst, src);
2865 emit_int8(0x29);
2866 emit_operand(src, dst);
2867 }
2868
2869 void Assembler::subl(Register dst, int32_t imm32) {
2870 prefix(dst);
2871 emit_arith(0x81, 0xE8, dst, imm32);
2872 }
2873
2874 // Force generation of a 4 byte immediate value even if it fits into 8bit
2875 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2876 prefix(dst);
2877 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2878 }
2879
2880 void Assembler::subl(Register dst, Address src) {
2881 InstructionMark im(this);
2882 prefix(src, dst);
2883 emit_int8(0x2B);
2884 emit_operand(dst, src);
2885 }
2886
2887 void Assembler::subl(Register dst, Register src) {
2888 (void) prefix_and_encode(dst->encoding(), src->encoding());
2889 emit_arith(0x2B, 0xC0, dst, src);
2890 }
2891
2892 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2894 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2895 }
2896
2897 void Assembler::subsd(XMMRegister dst, Address src) {
2898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2899 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2900 }
2901
2902 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2903 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2904 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2905 }
2906
2907 void Assembler::subss(XMMRegister dst, Address src) {
2908 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2909 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2910 }
2911
2912 void Assembler::testb(Register dst, int imm8) {
2913 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2914 (void) prefix_and_encode(dst->encoding(), true);
2915 emit_arith_b(0xF6, 0xC0, dst, imm8);
2916 }
2917
2918 void Assembler::testl(Register dst, int32_t imm32) {
2919 // not using emit_arith because test
2920 // doesn't support sign-extension of
2921 // 8bit operands
2922 int encode = dst->encoding();
2923 if (encode == 0) {
2924 emit_int8((unsigned char)0xA9);
2925 } else {
2926 encode = prefix_and_encode(encode);
2927 emit_int8((unsigned char)0xF7);
2928 emit_int8((unsigned char)(0xC0 | encode));
2929 }
2930 emit_int32(imm32);
2931 }
2932
2933 void Assembler::testl(Register dst, Register src) {
2934 (void) prefix_and_encode(dst->encoding(), src->encoding());
2935 emit_arith(0x85, 0xC0, dst, src);
2936 }
2937
2938 void Assembler::testl(Register dst, Address src) {
2939 InstructionMark im(this);
2940 prefix(src, dst);
2941 emit_int8((unsigned char)0x85);
2942 emit_operand(dst, src);
2943 }
2944
2945 void Assembler::tzcntl(Register dst, Register src) {
2946 InstructionMark im(this);
2947 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2948 emit_int8((unsigned char)0xF3);
2949 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2950 emit_int8(0x0F);
2951 emit_int8((unsigned char)0xBC);
2952 emit_int8((unsigned char)0xC0 | encode);
2953 }
2954
2955 void Assembler::tzcntq(Register dst, Register src) {
2956 InstructionMark im(this);
2957 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2958 emit_int8((unsigned char)0xF3);
2959 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2960 emit_int8(0x0F);
2961 emit_int8((unsigned char)0xBC);
2962 emit_int8((unsigned char)(0xC0 | encode));
2963 }
2964
2965 void Assembler::ucomisd(XMMRegister dst, Address src) {
2966 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2967 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2968 }
2969
2970 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2971 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2972 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2973 }
2974
2975 void Assembler::ucomiss(XMMRegister dst, Address src) {
2976 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2977 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2978 }
2979
2980 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2981 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2982 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2983 }
2984
2985
2986 void Assembler::xaddl(Address dst, Register src) {
2987 InstructionMark im(this);
2988 prefix(dst, src);
2989 emit_int8(0x0F);
2990 emit_int8((unsigned char)0xC1);
2991 emit_operand(src, dst);
2992 }
2993
2994 void Assembler::xchgl(Register dst, Address src) { // xchg
2995 InstructionMark im(this);
2996 prefix(src, dst);
2997 emit_int8((unsigned char)0x87);
2998 emit_operand(dst, src);
2999 }
3000
3001 void Assembler::xchgl(Register dst, Register src) {
3002 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3003 emit_int8((unsigned char)0x87);
3004 emit_int8((unsigned char)(0xC0 | encode));
3005 }
3006
3007 void Assembler::xgetbv() {
3008 emit_int8(0x0F);
3009 emit_int8(0x01);
3010 emit_int8((unsigned char)0xD0);
3011 }
3012
3013 void Assembler::xorl(Register dst, int32_t imm32) {
3014 prefix(dst);
3015 emit_arith(0x81, 0xF0, dst, imm32);
3016 }
3017
3018 void Assembler::xorl(Register dst, Address src) {
3019 InstructionMark im(this);
3020 prefix(src, dst);
3021 emit_int8(0x33);
3022 emit_operand(dst, src);
3023 }
3024
3025 void Assembler::xorl(Register dst, Register src) {
3026 (void) prefix_and_encode(dst->encoding(), src->encoding());
3027 emit_arith(0x33, 0xC0, dst, src);
3028 }
3029
3030
3031 // AVX 3-operands scalar float-point arithmetic instructions
3032
3033 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3034 assert(VM_Version::supports_avx(), "");
3035 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3036 }
3037
3038 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3039 assert(VM_Version::supports_avx(), "");
3040 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3041 }
3042
3043 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3044 assert(VM_Version::supports_avx(), "");
3045 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3046 }
3047
3048 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3049 assert(VM_Version::supports_avx(), "");
3050 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3051 }
3052
3053 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3054 assert(VM_Version::supports_avx(), "");
3055 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3056 }
3057
3058 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3059 assert(VM_Version::supports_avx(), "");
3060 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3061 }
3062
3063 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3064 assert(VM_Version::supports_avx(), "");
3065 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3066 }
3067
3068 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3069 assert(VM_Version::supports_avx(), "");
3070 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3071 }
3072
3073 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3074 assert(VM_Version::supports_avx(), "");
3075 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3076 }
3077
3078 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3079 assert(VM_Version::supports_avx(), "");
3080 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3081 }
3082
3083 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3084 assert(VM_Version::supports_avx(), "");
3085 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3086 }
3087
3088 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3089 assert(VM_Version::supports_avx(), "");
3090 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3091 }
3092
3093 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3094 assert(VM_Version::supports_avx(), "");
3095 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3096 }
3097
3098 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3099 assert(VM_Version::supports_avx(), "");
3100 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3101 }
3102
3103 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3104 assert(VM_Version::supports_avx(), "");
3105 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3106 }
3107
3108 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3109 assert(VM_Version::supports_avx(), "");
3110 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3111 }
3112
3113 //====================VECTOR ARITHMETIC=====================================
3114
3115 // Float-point vector arithmetic
3116
3117 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3119 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3120 }
3121
3122 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3123 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3124 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3125 }
3126
3127 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3128 assert(VM_Version::supports_avx(), "");
3129 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3130 }
3131
3132 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3133 assert(VM_Version::supports_avx(), "");
3134 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3135 }
3136
3137 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3138 assert(VM_Version::supports_avx(), "");
3139 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3140 }
3141
3142 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3143 assert(VM_Version::supports_avx(), "");
3144 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3145 }
3146
3147 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3149 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3150 }
3151
3152 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3154 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3155 }
3156
3157 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3158 assert(VM_Version::supports_avx(), "");
3159 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3160 }
3161
3162 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3163 assert(VM_Version::supports_avx(), "");
3164 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3165 }
3166
3167 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3168 assert(VM_Version::supports_avx(), "");
3169 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3170 }
3171
3172 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3173 assert(VM_Version::supports_avx(), "");
3174 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3175 }
3176
3177 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3179 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3180 }
3181
3182 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3184 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3185 }
3186
3187 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3188 assert(VM_Version::supports_avx(), "");
3189 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3190 }
3191
3192 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3193 assert(VM_Version::supports_avx(), "");
3194 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3195 }
3196
3197 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3198 assert(VM_Version::supports_avx(), "");
3199 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3200 }
3201
3202 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3203 assert(VM_Version::supports_avx(), "");
3204 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3205 }
3206
3207 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3208 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3209 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3210 }
3211
3212 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3213 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3214 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3215 }
3216
3217 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3218 assert(VM_Version::supports_avx(), "");
3219 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3220 }
3221
3222 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3223 assert(VM_Version::supports_avx(), "");
3224 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3225 }
3226
3227 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3228 assert(VM_Version::supports_avx(), "");
3229 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3230 }
3231
3232 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3233 assert(VM_Version::supports_avx(), "");
3234 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3235 }
3236
3237 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3239 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3240 }
3241
3242 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3243 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3244 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3245 }
3246
3247 void Assembler::andps(XMMRegister dst, Address src) {
3248 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3249 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3250 }
3251
3252 void Assembler::andpd(XMMRegister dst, Address src) {
3253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3254 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3255 }
3256
3257 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3258 assert(VM_Version::supports_avx(), "");
3259 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3260 }
3261
3262 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3263 assert(VM_Version::supports_avx(), "");
3264 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3265 }
3266
3267 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3268 assert(VM_Version::supports_avx(), "");
3269 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3270 }
3271
3272 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3273 assert(VM_Version::supports_avx(), "");
3274 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3275 }
3276
3277 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3278 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3279 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3280 }
3281
3282 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3283 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3284 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3285 }
3286
3287 void Assembler::xorpd(XMMRegister dst, Address src) {
3288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3289 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3290 }
3291
3292 void Assembler::xorps(XMMRegister dst, Address src) {
3293 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3294 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3295 }
3296
3297 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3298 assert(VM_Version::supports_avx(), "");
3299 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3300 }
3301
3302 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3303 assert(VM_Version::supports_avx(), "");
3304 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3305 }
3306
3307 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3308 assert(VM_Version::supports_avx(), "");
3309 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3310 }
3311
3312 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3313 assert(VM_Version::supports_avx(), "");
3314 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3315 }
3316
3317
3318 // Integer vector arithmetic
3319 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3321 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3322 }
3323
3324 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3326 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3327 }
3328
3329 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3330 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3331 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3332 }
3333
3334 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3336 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3337 }
3338
3339 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3340 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3341 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3342 }
3343
3344 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3345 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3346 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3347 }
3348
3349 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3350 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3351 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3352 }
3353
3354 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3355 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3356 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3357 }
3358
3359 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3360 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3361 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3362 }
3363
3364 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3365 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3366 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3367 }
3368
3369 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3370 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3371 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3372 }
3373
3374 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3375 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3376 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3377 }
3378
3379 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3381 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3382 }
3383
3384 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3385 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3386 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3387 }
3388
3389 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3391 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3392 }
3393
3394 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3395 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3396 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3397 }
3398
3399 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3400 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3401 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3402 }
3403
3404 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3405 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3406 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3407 }
3408
3409 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3410 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3411 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3412 }
3413
3414 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3415 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3416 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3417 }
3418
3419 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3420 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3421 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3422 }
3423
3424 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3425 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3426 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3427 }
3428
3429 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3430 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3431 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3432 }
3433
3434 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3435 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3436 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3437 }
3438
3439 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3440 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3441 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3442 }
3443
3444 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3445 assert(VM_Version::supports_sse4_1(), "");
3446 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3447 emit_int8(0x40);
3448 emit_int8((unsigned char)(0xC0 | encode));
3449 }
3450
3451 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3452 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3453 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3454 }
3455
3456 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3457 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3458 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3459 emit_int8(0x40);
3460 emit_int8((unsigned char)(0xC0 | encode));
3461 }
3462
3463 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3464 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3465 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3466 }
3467
3468 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3469 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3470 InstructionMark im(this);
3471 int dst_enc = dst->encoding();
3472 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3473 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3474 emit_int8(0x40);
3475 emit_operand(dst, src);
3476 }
3477
3478 // Shift packed integers left by specified number of bits.
3479 void Assembler::psllw(XMMRegister dst, int shift) {
3480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3481 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3482 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3483 emit_int8(0x71);
3484 emit_int8((unsigned char)(0xC0 | encode));
3485 emit_int8(shift & 0xFF);
3486 }
3487
3488 void Assembler::pslld(XMMRegister dst, int shift) {
3489 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3490 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3491 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3492 emit_int8(0x72);
3493 emit_int8((unsigned char)(0xC0 | encode));
3494 emit_int8(shift & 0xFF);
3495 }
3496
3497 void Assembler::psllq(XMMRegister dst, int shift) {
3498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3499 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3500 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3501 emit_int8(0x73);
3502 emit_int8((unsigned char)(0xC0 | encode));
3503 emit_int8(shift & 0xFF);
3504 }
3505
3506 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3507 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3508 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3509 }
3510
3511 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3513 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3514 }
3515
3516 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3517 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3518 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3519 }
3520
3521 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3522 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3523 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3524 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3525 emit_int8(shift & 0xFF);
3526 }
3527
3528 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3529 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3530 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3531 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3532 emit_int8(shift & 0xFF);
3533 }
3534
3535 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3536 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3537 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3538 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3539 emit_int8(shift & 0xFF);
3540 }
3541
3542 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3543 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3544 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3545 }
3546
3547 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3548 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3549 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3550 }
3551
3552 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3553 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3554 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3555 }
3556
3557 // Shift packed integers logically right by specified number of bits.
3558 void Assembler::psrlw(XMMRegister dst, int shift) {
3559 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3560 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3561 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3562 emit_int8(0x71);
3563 emit_int8((unsigned char)(0xC0 | encode));
3564 emit_int8(shift & 0xFF);
3565 }
3566
3567 void Assembler::psrld(XMMRegister dst, int shift) {
3568 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3569 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3570 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3571 emit_int8(0x72);
3572 emit_int8((unsigned char)(0xC0 | encode));
3573 emit_int8(shift & 0xFF);
3574 }
3575
3576 void Assembler::psrlq(XMMRegister dst, int shift) {
3577 // Do not confuse it with psrldq SSE2 instruction which
3578 // shifts 128 bit value in xmm register by number of bytes.
3579 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3580 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3581 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3582 emit_int8(0x73);
3583 emit_int8((unsigned char)(0xC0 | encode));
3584 emit_int8(shift & 0xFF);
3585 }
3586
3587 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3588 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3589 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3590 }
3591
3592 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3594 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3595 }
3596
3597 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3598 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3599 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3600 }
3601
3602 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3603 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3604 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3605 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3606 emit_int8(shift & 0xFF);
3607 }
3608
3609 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3610 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3611 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3612 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3613 emit_int8(shift & 0xFF);
3614 }
3615
3616 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3617 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3618 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3619 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3620 emit_int8(shift & 0xFF);
3621 }
3622
3623 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3624 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3625 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3626 }
3627
3628 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3629 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3630 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3631 }
3632
3633 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3634 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3635 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3636 }
3637
3638 // Shift packed integers arithmetically right by specified number of bits.
3639 void Assembler::psraw(XMMRegister dst, int shift) {
3640 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3641 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3642 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3643 emit_int8(0x71);
3644 emit_int8((unsigned char)(0xC0 | encode));
3645 emit_int8(shift & 0xFF);
3646 }
3647
3648 void Assembler::psrad(XMMRegister dst, int shift) {
3649 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3650 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3651 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3652 emit_int8(0x72);
3653 emit_int8((unsigned char)(0xC0 | encode));
3654 emit_int8(shift & 0xFF);
3655 }
3656
3657 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3658 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3659 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3660 }
3661
3662 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3664 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3665 }
3666
3667 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3668 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3669 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3670 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3671 emit_int8(shift & 0xFF);
3672 }
3673
3674 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3675 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3676 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3677 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3678 emit_int8(shift & 0xFF);
3679 }
3680
3681 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3682 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3683 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3684 }
3685
3686 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3687 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3688 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3689 }
3690
3691
3692 // AND packed integers
3693 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3695 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3696 }
3697
3698 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3699 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3700 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3701 }
3702
3703 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3704 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3705 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3706 }
3707
3708 void Assembler::por(XMMRegister dst, XMMRegister src) {
3709 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3710 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3711 }
3712
3713 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3714 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3715 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3716 }
3717
3718 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3719 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3720 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3721 }
3722
3723 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3725 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3726 }
3727
3728 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3729 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3730 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3731 }
3732
3733 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3734 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3735 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3736 }
3737
3738
3739 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3740 assert(VM_Version::supports_avx(), "");
3741 bool vector256 = true;
3742 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3743 emit_int8(0x18);
3744 emit_int8((unsigned char)(0xC0 | encode));
3745 // 0x00 - insert into lower 128 bits
3746 // 0x01 - insert into upper 128 bits
3747 emit_int8(0x01);
3748 }
3749
3750 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3751 assert(VM_Version::supports_avx(), "");
3752 InstructionMark im(this);
3753 bool vector256 = true;
3754 assert(dst != xnoreg, "sanity");
3755 int dst_enc = dst->encoding();
3756 // swap src<->dst for encoding
3757 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3758 emit_int8(0x18);
3759 emit_operand(dst, src);
3760 // 0x01 - insert into upper 128 bits
3761 emit_int8(0x01);
3762 }
3763
3764 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3765 assert(VM_Version::supports_avx(), "");
3766 InstructionMark im(this);
3767 bool vector256 = true;
3768 assert(src != xnoreg, "sanity");
3769 int src_enc = src->encoding();
3770 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3771 emit_int8(0x19);
3772 emit_operand(src, dst);
3773 // 0x01 - extract from upper 128 bits
3774 emit_int8(0x01);
3775 }
3776
3777 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3778 assert(VM_Version::supports_avx2(), "");
3779 bool vector256 = true;
3780 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3781 emit_int8(0x38);
3782 emit_int8((unsigned char)(0xC0 | encode));
3783 // 0x00 - insert into lower 128 bits
3784 // 0x01 - insert into upper 128 bits
3785 emit_int8(0x01);
3786 }
3787
3788 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3789 assert(VM_Version::supports_avx2(), "");
3790 InstructionMark im(this);
3791 bool vector256 = true;
3792 assert(dst != xnoreg, "sanity");
3793 int dst_enc = dst->encoding();
3794 // swap src<->dst for encoding
3795 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3796 emit_int8(0x38);
3797 emit_operand(dst, src);
3798 // 0x01 - insert into upper 128 bits
3799 emit_int8(0x01);
3800 }
3801
3802 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3803 assert(VM_Version::supports_avx2(), "");
3804 InstructionMark im(this);
3805 bool vector256 = true;
3806 assert(src != xnoreg, "sanity");
3807 int src_enc = src->encoding();
3808 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3809 emit_int8(0x39);
3810 emit_operand(src, dst);
3811 // 0x01 - extract from upper 128 bits
3812 emit_int8(0x01);
3813 }
3814
3815 // duplicate 4-bytes integer data from src into 8 locations in dest
3816 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3817 assert(VM_Version::supports_avx2(), "");
3818 bool vector256 = true;
3819 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3820 emit_int8(0x58);
3821 emit_int8((unsigned char)(0xC0 | encode));
3822 }
3823
3824 // Carry-Less Multiplication Quadword
3825 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3826 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3827 bool vector256 = false;
3828 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3829 emit_int8(0x44);
3830 emit_int8((unsigned char)(0xC0 | encode));
3831 emit_int8((unsigned char)mask);
3832 }
3833
3834 void Assembler::vzeroupper() {
3835 assert(VM_Version::supports_avx(), "");
3836 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3837 emit_int8(0x77);
3838 }
3839
3840
3841 #ifndef _LP64
3842 // 32bit only pieces of the assembler
3843
3844 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3845 // NO PREFIX AS NEVER 64BIT
3846 InstructionMark im(this);
3847 emit_int8((unsigned char)0x81);
3848 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3849 emit_data(imm32, rspec, 0);
3850 }
3851
3852 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3853 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3854 InstructionMark im(this);
3855 emit_int8((unsigned char)0x81);
3856 emit_operand(rdi, src1);
3857 emit_data(imm32, rspec, 0);
3858 }
3859
3860 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3861 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3862 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3863 void Assembler::cmpxchg8(Address adr) {
3864 InstructionMark im(this);
3865 emit_int8(0x0F);
3866 emit_int8((unsigned char)0xC7);
3867 emit_operand(rcx, adr);
3868 }
3869
3870 void Assembler::decl(Register dst) {
3871 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3872 emit_int8(0x48 | dst->encoding());
3873 }
3874
3875 #endif // _LP64
3876
3877 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3878
3879 void Assembler::fabs() {
3880 emit_int8((unsigned char)0xD9);
3881 emit_int8((unsigned char)0xE1);
3882 }
3883
3884 void Assembler::fadd(int i) {
3885 emit_farith(0xD8, 0xC0, i);
3886 }
3887
3888 void Assembler::fadd_d(Address src) {
3889 InstructionMark im(this);
3890 emit_int8((unsigned char)0xDC);
3891 emit_operand32(rax, src);
3892 }
3893
3894 void Assembler::fadd_s(Address src) {
3895 InstructionMark im(this);
3896 emit_int8((unsigned char)0xD8);
3897 emit_operand32(rax, src);
3898 }
3899
3900 void Assembler::fadda(int i) {
3901 emit_farith(0xDC, 0xC0, i);
3902 }
3903
3904 void Assembler::faddp(int i) {
3905 emit_farith(0xDE, 0xC0, i);
3906 }
3907
3908 void Assembler::fchs() {
3909 emit_int8((unsigned char)0xD9);
3910 emit_int8((unsigned char)0xE0);
3911 }
3912
3913 void Assembler::fcom(int i) {
3914 emit_farith(0xD8, 0xD0, i);
3915 }
3916
3917 void Assembler::fcomp(int i) {
3918 emit_farith(0xD8, 0xD8, i);
3919 }
3920
3921 void Assembler::fcomp_d(Address src) {
3922 InstructionMark im(this);
3923 emit_int8((unsigned char)0xDC);
3924 emit_operand32(rbx, src);
3925 }
3926
3927 void Assembler::fcomp_s(Address src) {
3928 InstructionMark im(this);
3929 emit_int8((unsigned char)0xD8);
3930 emit_operand32(rbx, src);
3931 }
3932
3933 void Assembler::fcompp() {
3934 emit_int8((unsigned char)0xDE);
3935 emit_int8((unsigned char)0xD9);
3936 }
3937
3938 void Assembler::fcos() {
3939 emit_int8((unsigned char)0xD9);
3940 emit_int8((unsigned char)0xFF);
3941 }
3942
3943 void Assembler::fdecstp() {
3944 emit_int8((unsigned char)0xD9);
3945 emit_int8((unsigned char)0xF6);
3946 }
3947
3948 void Assembler::fdiv(int i) {
3949 emit_farith(0xD8, 0xF0, i);
3950 }
3951
3952 void Assembler::fdiv_d(Address src) {
3953 InstructionMark im(this);
3954 emit_int8((unsigned char)0xDC);
3955 emit_operand32(rsi, src);
3956 }
3957
3958 void Assembler::fdiv_s(Address src) {
3959 InstructionMark im(this);
3960 emit_int8((unsigned char)0xD8);
3961 emit_operand32(rsi, src);
3962 }
3963
3964 void Assembler::fdiva(int i) {
3965 emit_farith(0xDC, 0xF8, i);
3966 }
3967
3968 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3969 // is erroneous for some of the floating-point instructions below.
3970
3971 void Assembler::fdivp(int i) {
3972 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3973 }
3974
3975 void Assembler::fdivr(int i) {
3976 emit_farith(0xD8, 0xF8, i);
3977 }
3978
3979 void Assembler::fdivr_d(Address src) {
3980 InstructionMark im(this);
3981 emit_int8((unsigned char)0xDC);
3982 emit_operand32(rdi, src);
3983 }
3984
3985 void Assembler::fdivr_s(Address src) {
3986 InstructionMark im(this);
3987 emit_int8((unsigned char)0xD8);
3988 emit_operand32(rdi, src);
3989 }
3990
3991 void Assembler::fdivra(int i) {
3992 emit_farith(0xDC, 0xF0, i);
3993 }
3994
3995 void Assembler::fdivrp(int i) {
3996 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3997 }
3998
3999 void Assembler::ffree(int i) {
4000 emit_farith(0xDD, 0xC0, i);
4001 }
4002
4003 void Assembler::fild_d(Address adr) {
4004 InstructionMark im(this);
4005 emit_int8((unsigned char)0xDF);
4006 emit_operand32(rbp, adr);
4007 }
4008
4009 void Assembler::fild_s(Address adr) {
4010 InstructionMark im(this);
4011 emit_int8((unsigned char)0xDB);
4012 emit_operand32(rax, adr);
4013 }
4014
4015 void Assembler::fincstp() {
4016 emit_int8((unsigned char)0xD9);
4017 emit_int8((unsigned char)0xF7);
4018 }
4019
4020 void Assembler::finit() {
4021 emit_int8((unsigned char)0x9B);
4022 emit_int8((unsigned char)0xDB);
4023 emit_int8((unsigned char)0xE3);
4024 }
4025
4026 void Assembler::fist_s(Address adr) {
4027 InstructionMark im(this);
4028 emit_int8((unsigned char)0xDB);
4029 emit_operand32(rdx, adr);
4030 }
4031
4032 void Assembler::fistp_d(Address adr) {
4033 InstructionMark im(this);
4034 emit_int8((unsigned char)0xDF);
4035 emit_operand32(rdi, adr);
4036 }
4037
4038 void Assembler::fistp_s(Address adr) {
4039 InstructionMark im(this);
4040 emit_int8((unsigned char)0xDB);
4041 emit_operand32(rbx, adr);
4042 }
4043
4044 void Assembler::fld1() {
4045 emit_int8((unsigned char)0xD9);
4046 emit_int8((unsigned char)0xE8);
4047 }
4048
4049 void Assembler::fld_d(Address adr) {
4050 InstructionMark im(this);
4051 emit_int8((unsigned char)0xDD);
4052 emit_operand32(rax, adr);
4053 }
4054
4055 void Assembler::fld_s(Address adr) {
4056 InstructionMark im(this);
4057 emit_int8((unsigned char)0xD9);
4058 emit_operand32(rax, adr);
4059 }
4060
4061
4062 void Assembler::fld_s(int index) {
4063 emit_farith(0xD9, 0xC0, index);
4064 }
4065
4066 void Assembler::fld_x(Address adr) {
4067 InstructionMark im(this);
4068 emit_int8((unsigned char)0xDB);
4069 emit_operand32(rbp, adr);
4070 }
4071
4072 void Assembler::fldcw(Address src) {
4073 InstructionMark im(this);
4074 emit_int8((unsigned char)0xD9);
4075 emit_operand32(rbp, src);
4076 }
4077
4078 void Assembler::fldenv(Address src) {
4079 InstructionMark im(this);
4080 emit_int8((unsigned char)0xD9);
4081 emit_operand32(rsp, src);
4082 }
4083
4084 void Assembler::fldlg2() {
4085 emit_int8((unsigned char)0xD9);
4086 emit_int8((unsigned char)0xEC);
4087 }
4088
4089 void Assembler::fldln2() {
4090 emit_int8((unsigned char)0xD9);
4091 emit_int8((unsigned char)0xED);
4092 }
4093
4094 void Assembler::fldz() {
4095 emit_int8((unsigned char)0xD9);
4096 emit_int8((unsigned char)0xEE);
4097 }
4098
4099 void Assembler::flog() {
4100 fldln2();
4101 fxch();
4102 fyl2x();
4103 }
4104
4105 void Assembler::flog10() {
4106 fldlg2();
4107 fxch();
4108 fyl2x();
4109 }
4110
4111 void Assembler::fmul(int i) {
4112 emit_farith(0xD8, 0xC8, i);
4113 }
4114
4115 void Assembler::fmul_d(Address src) {
4116 InstructionMark im(this);
4117 emit_int8((unsigned char)0xDC);
4118 emit_operand32(rcx, src);
4119 }
4120
4121 void Assembler::fmul_s(Address src) {
4122 InstructionMark im(this);
4123 emit_int8((unsigned char)0xD8);
4124 emit_operand32(rcx, src);
4125 }
4126
4127 void Assembler::fmula(int i) {
4128 emit_farith(0xDC, 0xC8, i);
4129 }
4130
4131 void Assembler::fmulp(int i) {
4132 emit_farith(0xDE, 0xC8, i);
4133 }
4134
4135 void Assembler::fnsave(Address dst) {
4136 InstructionMark im(this);
4137 emit_int8((unsigned char)0xDD);
4138 emit_operand32(rsi, dst);
4139 }
4140
4141 void Assembler::fnstcw(Address src) {
4142 InstructionMark im(this);
4143 emit_int8((unsigned char)0x9B);
4144 emit_int8((unsigned char)0xD9);
4145 emit_operand32(rdi, src);
4146 }
4147
4148 void Assembler::fnstsw_ax() {
4149 emit_int8((unsigned char)0xDF);
4150 emit_int8((unsigned char)0xE0);
4151 }
4152
4153 void Assembler::fprem() {
4154 emit_int8((unsigned char)0xD9);
4155 emit_int8((unsigned char)0xF8);
4156 }
4157
4158 void Assembler::fprem1() {
4159 emit_int8((unsigned char)0xD9);
4160 emit_int8((unsigned char)0xF5);
4161 }
4162
4163 void Assembler::frstor(Address src) {
4164 InstructionMark im(this);
4165 emit_int8((unsigned char)0xDD);
4166 emit_operand32(rsp, src);
4167 }
4168
4169 void Assembler::fsin() {
4170 emit_int8((unsigned char)0xD9);
4171 emit_int8((unsigned char)0xFE);
4172 }
4173
4174 void Assembler::fsqrt() {
4175 emit_int8((unsigned char)0xD9);
4176 emit_int8((unsigned char)0xFA);
4177 }
4178
4179 void Assembler::fst_d(Address adr) {
4180 InstructionMark im(this);
4181 emit_int8((unsigned char)0xDD);
4182 emit_operand32(rdx, adr);
4183 }
4184
4185 void Assembler::fst_s(Address adr) {
4186 InstructionMark im(this);
4187 emit_int8((unsigned char)0xD9);
4188 emit_operand32(rdx, adr);
4189 }
4190
4191 void Assembler::fstp_d(Address adr) {
4192 InstructionMark im(this);
4193 emit_int8((unsigned char)0xDD);
4194 emit_operand32(rbx, adr);
4195 }
4196
4197 void Assembler::fstp_d(int index) {
4198 emit_farith(0xDD, 0xD8, index);
4199 }
4200
4201 void Assembler::fstp_s(Address adr) {
4202 InstructionMark im(this);
4203 emit_int8((unsigned char)0xD9);
4204 emit_operand32(rbx, adr);
4205 }
4206
4207 void Assembler::fstp_x(Address adr) {
4208 InstructionMark im(this);
4209 emit_int8((unsigned char)0xDB);
4210 emit_operand32(rdi, adr);
4211 }
4212
4213 void Assembler::fsub(int i) {
4214 emit_farith(0xD8, 0xE0, i);
4215 }
4216
4217 void Assembler::fsub_d(Address src) {
4218 InstructionMark im(this);
4219 emit_int8((unsigned char)0xDC);
4220 emit_operand32(rsp, src);
4221 }
4222
4223 void Assembler::fsub_s(Address src) {
4224 InstructionMark im(this);
4225 emit_int8((unsigned char)0xD8);
4226 emit_operand32(rsp, src);
4227 }
4228
4229 void Assembler::fsuba(int i) {
4230 emit_farith(0xDC, 0xE8, i);
4231 }
4232
4233 void Assembler::fsubp(int i) {
4234 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4235 }
4236
4237 void Assembler::fsubr(int i) {
4238 emit_farith(0xD8, 0xE8, i);
4239 }
4240
4241 void Assembler::fsubr_d(Address src) {
4242 InstructionMark im(this);
4243 emit_int8((unsigned char)0xDC);
4244 emit_operand32(rbp, src);
4245 }
4246
4247 void Assembler::fsubr_s(Address src) {
4248 InstructionMark im(this);
4249 emit_int8((unsigned char)0xD8);
4250 emit_operand32(rbp, src);
4251 }
4252
4253 void Assembler::fsubra(int i) {
4254 emit_farith(0xDC, 0xE0, i);
4255 }
4256
4257 void Assembler::fsubrp(int i) {
4258 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4259 }
4260
4261 void Assembler::ftan() {
4262 emit_int8((unsigned char)0xD9);
4263 emit_int8((unsigned char)0xF2);
4264 emit_int8((unsigned char)0xDD);
4265 emit_int8((unsigned char)0xD8);
4266 }
4267
4268 void Assembler::ftst() {
4269 emit_int8((unsigned char)0xD9);
4270 emit_int8((unsigned char)0xE4);
4271 }
4272
4273 void Assembler::fucomi(int i) {
4274 // make sure the instruction is supported (introduced for P6, together with cmov)
4275 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4276 emit_farith(0xDB, 0xE8, i);
4277 }
4278
4279 void Assembler::fucomip(int i) {
4280 // make sure the instruction is supported (introduced for P6, together with cmov)
4281 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4282 emit_farith(0xDF, 0xE8, i);
4283 }
4284
4285 void Assembler::fwait() {
4286 emit_int8((unsigned char)0x9B);
4287 }
4288
4289 void Assembler::fxch(int i) {
4290 emit_farith(0xD9, 0xC8, i);
4291 }
4292
4293 void Assembler::fyl2x() {
4294 emit_int8((unsigned char)0xD9);
4295 emit_int8((unsigned char)0xF1);
4296 }
4297
4298 void Assembler::frndint() {
4299 emit_int8((unsigned char)0xD9);
4300 emit_int8((unsigned char)0xFC);
4301 }
4302
4303 void Assembler::f2xm1() {
4304 emit_int8((unsigned char)0xD9);
4305 emit_int8((unsigned char)0xF0);
4306 }
4307
4308 void Assembler::fldl2e() {
4309 emit_int8((unsigned char)0xD9);
4310 emit_int8((unsigned char)0xEA);
4311 }
4312
4313 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4314 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4315 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4316 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4317
4318 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4319 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4320 if (pre > 0) {
4321 emit_int8(simd_pre[pre]);
4322 }
4323 if (rex_w) {
4324 prefixq(adr, xreg);
4325 } else {
4326 prefix(adr, xreg);
4327 }
4328 if (opc > 0) {
4329 emit_int8(0x0F);
4330 int opc2 = simd_opc[opc];
4331 if (opc2 > 0) {
4332 emit_int8(opc2);
4333 }
4334 }
4335 }
4336
4337 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4338 if (pre > 0) {
4339 emit_int8(simd_pre[pre]);
4340 }
4341 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4342 prefix_and_encode(dst_enc, src_enc);
4343 if (opc > 0) {
4344 emit_int8(0x0F);
4345 int opc2 = simd_opc[opc];
4346 if (opc2 > 0) {
4347 emit_int8(opc2);
4348 }
4349 }
4350 return encode;
4351 }
4352
4353
4354 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4355 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4356 prefix(VEX_3bytes);
4357
4358 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4359 byte1 = (~byte1) & 0xE0;
4360 byte1 |= opc;
4361 emit_int8(byte1);
4362
4363 int byte2 = ((~nds_enc) & 0xf) << 3;
4364 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4365 emit_int8(byte2);
4366 } else {
4367 prefix(VEX_2bytes);
4368
4369 int byte1 = vex_r ? VEX_R : 0;
4370 byte1 = (~byte1) & 0x80;
4371 byte1 |= ((~nds_enc) & 0xf) << 3;
4372 byte1 |= (vector256 ? 4 : 0) | pre;
4373 emit_int8(byte1);
4374 }
4375 }
4376
4377 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4378 bool vex_r = (xreg_enc >= 8);
4379 bool vex_b = adr.base_needs_rex();
4380 bool vex_x = adr.index_needs_rex();
4381 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4382 }
4383
4384 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4385 bool vex_r = (dst_enc >= 8);
4386 bool vex_b = (src_enc >= 8);
4387 bool vex_x = false;
4388 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4389 return (((dst_enc & 7) << 3) | (src_enc & 7));
4390 }
4391
4392
4393 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4394 if (UseAVX > 0) {
4395 int xreg_enc = xreg->encoding();
4396 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4397 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4398 } else {
4399 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4400 rex_prefix(adr, xreg, pre, opc, rex_w);
4401 }
4402 }
4403
4404 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4405 int dst_enc = dst->encoding();
4406 int src_enc = src->encoding();
4407 if (UseAVX > 0) {
4408 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4409 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4410 } else {
4411 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4412 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4413 }
4414 }
4415
4416 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4417 InstructionMark im(this);
4418 simd_prefix(dst, dst, src, pre);
4419 emit_int8(opcode);
4420 emit_operand(dst, src);
4421 }
4422
4423 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4424 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4425 emit_int8(opcode);
4426 emit_int8((unsigned char)(0xC0 | encode));
4427 }
4428
4429 // Versions with no second source register (non-destructive source).
4430 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4431 InstructionMark im(this);
4432 simd_prefix(dst, xnoreg, src, pre);
4433 emit_int8(opcode);
4434 emit_operand(dst, src);
4435 }
4436
4437 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4438 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4439 emit_int8(opcode);
4440 emit_int8((unsigned char)(0xC0 | encode));
4441 }
4442
4443 // 3-operands AVX instructions
4444 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4445 Address src, VexSimdPrefix pre, bool vector256) {
4446 InstructionMark im(this);
4447 vex_prefix(dst, nds, src, pre, vector256);
4448 emit_int8(opcode);
4449 emit_operand(dst, src);
4450 }
4451
4452 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4453 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4454 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4455 emit_int8(opcode);
4456 emit_int8((unsigned char)(0xC0 | encode));
4457 }
4458
4459 #ifndef _LP64
4460
4461 void Assembler::incl(Register dst) {
4462 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4463 emit_int8(0x40 | dst->encoding());
4464 }
4465
4466 void Assembler::lea(Register dst, Address src) {
4467 leal(dst, src);
4468 }
4469
4470 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4471 InstructionMark im(this);
4472 emit_int8((unsigned char)0xC7);
4473 emit_operand(rax, dst);
4474 emit_data((int)imm32, rspec, 0);
4475 }
4476
4477 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4478 InstructionMark im(this);
4479 int encode = prefix_and_encode(dst->encoding());
4480 emit_int8((unsigned char)(0xB8 | encode));
4481 emit_data((int)imm32, rspec, 0);
4482 }
4483
4484 void Assembler::popa() { // 32bit
4485 emit_int8(0x61);
4486 }
4487
4488 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4489 InstructionMark im(this);
4490 emit_int8(0x68);
4491 emit_data(imm32, rspec, 0);
4492 }
4493
4494 void Assembler::pusha() { // 32bit
4495 emit_int8(0x60);
4496 }
4497
4498 void Assembler::set_byte_if_not_zero(Register dst) {
4499 emit_int8(0x0F);
4500 emit_int8((unsigned char)0x95);
4501 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4502 }
4503
4504 void Assembler::shldl(Register dst, Register src) {
4505 emit_int8(0x0F);
4506 emit_int8((unsigned char)0xA5);
4507 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4508 }
4509
4510 void Assembler::shrdl(Register dst, Register src) {
4511 emit_int8(0x0F);
4512 emit_int8((unsigned char)0xAD);
4513 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4514 }
4515
4516 #else // LP64
4517
4518 void Assembler::set_byte_if_not_zero(Register dst) {
4519 int enc = prefix_and_encode(dst->encoding(), true);
4520 emit_int8(0x0F);
4521 emit_int8((unsigned char)0x95);
4522 emit_int8((unsigned char)(0xE0 | enc));
4523 }
4524
4525 // 64bit only pieces of the assembler
4526 // This should only be used by 64bit instructions that can use rip-relative
4527 // it cannot be used by instructions that want an immediate value.
4528
4529 bool Assembler::reachable(AddressLiteral adr) {
4530 int64_t disp;
4531 // None will force a 64bit literal to the code stream. Likely a placeholder
4532 // for something that will be patched later and we need to certain it will
4533 // always be reachable.
4534 if (adr.reloc() == relocInfo::none) {
4535 return false;
4536 }
4537 if (adr.reloc() == relocInfo::internal_word_type) {
4538 // This should be rip relative and easily reachable.
4539 return true;
4540 }
4541 if (adr.reloc() == relocInfo::virtual_call_type ||
4542 adr.reloc() == relocInfo::opt_virtual_call_type ||
4543 adr.reloc() == relocInfo::static_call_type ||
4544 adr.reloc() == relocInfo::static_stub_type ) {
4545 // This should be rip relative within the code cache and easily
4546 // reachable until we get huge code caches. (At which point
4547 // ic code is going to have issues).
4548 return true;
4549 }
4550 if (adr.reloc() != relocInfo::external_word_type &&
4551 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4552 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4553 adr.reloc() != relocInfo::runtime_call_type ) {
4554 return false;
4555 }
4556
4557 // Stress the correction code
4558 if (ForceUnreachable) {
4559 // Must be runtimecall reloc, see if it is in the codecache
4560 // Flipping stuff in the codecache to be unreachable causes issues
4561 // with things like inline caches where the additional instructions
4562 // are not handled.
4563 if (CodeCache::find_blob(adr._target) == NULL) {
4564 return false;
4565 }
4566 }
4567 // For external_word_type/runtime_call_type if it is reachable from where we
4568 // are now (possibly a temp buffer) and where we might end up
4569 // anywhere in the codeCache then we are always reachable.
4570 // This would have to change if we ever save/restore shared code
4571 // to be more pessimistic.
4572 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4573 if (!is_simm32(disp)) return false;
4574 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4575 if (!is_simm32(disp)) return false;
4576
4577 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4578
4579 // Because rip relative is a disp + address_of_next_instruction and we
4580 // don't know the value of address_of_next_instruction we apply a fudge factor
4581 // to make sure we will be ok no matter the size of the instruction we get placed into.
4582 // We don't have to fudge the checks above here because they are already worst case.
4583
4584 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4585 // + 4 because better safe than sorry.
4586 const int fudge = 12 + 4;
4587 if (disp < 0) {
4588 disp -= fudge;
4589 } else {
4590 disp += fudge;
4591 }
4592 return is_simm32(disp);
4593 }
4594
4595 // Check if the polling page is not reachable from the code cache using rip-relative
4596 // addressing.
4597 bool Assembler::is_polling_page_far() {
4598 intptr_t addr = (intptr_t)os::get_polling_page();
4599 return ForceUnreachable ||
4600 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4601 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4602 }
4603
4604 void Assembler::emit_data64(jlong data,
4605 relocInfo::relocType rtype,
4606 int format) {
4607 if (rtype == relocInfo::none) {
4608 emit_int64(data);
4609 } else {
4610 emit_data64(data, Relocation::spec_simple(rtype), format);
4611 }
4612 }
4613
4614 void Assembler::emit_data64(jlong data,
4615 RelocationHolder const& rspec,
4616 int format) {
4617 assert(imm_operand == 0, "default format must be immediate in this file");
4618 assert(imm_operand == format, "must be immediate");
4619 assert(inst_mark() != NULL, "must be inside InstructionMark");
4620 // Do not use AbstractAssembler::relocate, which is not intended for
4621 // embedded words. Instead, relocate to the enclosing instruction.
4622 code_section()->relocate(inst_mark(), rspec, format);
4623 #ifdef ASSERT
4624 check_relocation(rspec, format);
4625 #endif
4626 emit_int64(data);
4627 }
4628
4629 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4630 if (reg_enc >= 8) {
4631 prefix(REX_B);
4632 reg_enc -= 8;
4633 } else if (byteinst && reg_enc >= 4) {
4634 prefix(REX);
4635 }
4636 return reg_enc;
4637 }
4638
4639 int Assembler::prefixq_and_encode(int reg_enc) {
4640 if (reg_enc < 8) {
4641 prefix(REX_W);
4642 } else {
4643 prefix(REX_WB);
4644 reg_enc -= 8;
4645 }
4646 return reg_enc;
4647 }
4648
4649 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4650 if (dst_enc < 8) {
4651 if (src_enc >= 8) {
4652 prefix(REX_B);
4653 src_enc -= 8;
4654 } else if (byteinst && src_enc >= 4) {
4655 prefix(REX);
4656 }
4657 } else {
4658 if (src_enc < 8) {
4659 prefix(REX_R);
4660 } else {
4661 prefix(REX_RB);
4662 src_enc -= 8;
4663 }
4664 dst_enc -= 8;
4665 }
4666 return dst_enc << 3 | src_enc;
4667 }
4668
4669 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4670 if (dst_enc < 8) {
4671 if (src_enc < 8) {
4672 prefix(REX_W);
4673 } else {
4674 prefix(REX_WB);
4675 src_enc -= 8;
4676 }
4677 } else {
4678 if (src_enc < 8) {
4679 prefix(REX_WR);
4680 } else {
4681 prefix(REX_WRB);
4682 src_enc -= 8;
4683 }
4684 dst_enc -= 8;
4685 }
4686 return dst_enc << 3 | src_enc;
4687 }
4688
4689 void Assembler::prefix(Register reg) {
4690 if (reg->encoding() >= 8) {
4691 prefix(REX_B);
4692 }
4693 }
4694
4695 void Assembler::prefix(Address adr) {
4696 if (adr.base_needs_rex()) {
4697 if (adr.index_needs_rex()) {
4698 prefix(REX_XB);
4699 } else {
4700 prefix(REX_B);
4701 }
4702 } else {
4703 if (adr.index_needs_rex()) {
4704 prefix(REX_X);
4705 }
4706 }
4707 }
4708
4709 void Assembler::prefixq(Address adr) {
4710 if (adr.base_needs_rex()) {
4711 if (adr.index_needs_rex()) {
4712 prefix(REX_WXB);
4713 } else {
4714 prefix(REX_WB);
4715 }
4716 } else {
4717 if (adr.index_needs_rex()) {
4718 prefix(REX_WX);
4719 } else {
4720 prefix(REX_W);
4721 }
4722 }
4723 }
4724
4725
4726 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4727 if (reg->encoding() < 8) {
4728 if (adr.base_needs_rex()) {
4729 if (adr.index_needs_rex()) {
4730 prefix(REX_XB);
4731 } else {
4732 prefix(REX_B);
4733 }
4734 } else {
4735 if (adr.index_needs_rex()) {
4736 prefix(REX_X);
4737 } else if (byteinst && reg->encoding() >= 4 ) {
4738 prefix(REX);
4739 }
4740 }
4741 } else {
4742 if (adr.base_needs_rex()) {
4743 if (adr.index_needs_rex()) {
4744 prefix(REX_RXB);
4745 } else {
4746 prefix(REX_RB);
4747 }
4748 } else {
4749 if (adr.index_needs_rex()) {
4750 prefix(REX_RX);
4751 } else {
4752 prefix(REX_R);
4753 }
4754 }
4755 }
4756 }
4757
4758 void Assembler::prefixq(Address adr, Register src) {
4759 if (src->encoding() < 8) {
4760 if (adr.base_needs_rex()) {
4761 if (adr.index_needs_rex()) {
4762 prefix(REX_WXB);
4763 } else {
4764 prefix(REX_WB);
4765 }
4766 } else {
4767 if (adr.index_needs_rex()) {
4768 prefix(REX_WX);
4769 } else {
4770 prefix(REX_W);
4771 }
4772 }
4773 } else {
4774 if (adr.base_needs_rex()) {
4775 if (adr.index_needs_rex()) {
4776 prefix(REX_WRXB);
4777 } else {
4778 prefix(REX_WRB);
4779 }
4780 } else {
4781 if (adr.index_needs_rex()) {
4782 prefix(REX_WRX);
4783 } else {
4784 prefix(REX_WR);
4785 }
4786 }
4787 }
4788 }
4789
4790 void Assembler::prefix(Address adr, XMMRegister reg) {
4791 if (reg->encoding() < 8) {
4792 if (adr.base_needs_rex()) {
4793 if (adr.index_needs_rex()) {
4794 prefix(REX_XB);
4795 } else {
4796 prefix(REX_B);
4797 }
4798 } else {
4799 if (adr.index_needs_rex()) {
4800 prefix(REX_X);
4801 }
4802 }
4803 } else {
4804 if (adr.base_needs_rex()) {
4805 if (adr.index_needs_rex()) {
4806 prefix(REX_RXB);
4807 } else {
4808 prefix(REX_RB);
4809 }
4810 } else {
4811 if (adr.index_needs_rex()) {
4812 prefix(REX_RX);
4813 } else {
4814 prefix(REX_R);
4815 }
4816 }
4817 }
4818 }
4819
4820 void Assembler::prefixq(Address adr, XMMRegister src) {
4821 if (src->encoding() < 8) {
4822 if (adr.base_needs_rex()) {
4823 if (adr.index_needs_rex()) {
4824 prefix(REX_WXB);
4825 } else {
4826 prefix(REX_WB);
4827 }
4828 } else {
4829 if (adr.index_needs_rex()) {
4830 prefix(REX_WX);
4831 } else {
4832 prefix(REX_W);
4833 }
4834 }
4835 } else {
4836 if (adr.base_needs_rex()) {
4837 if (adr.index_needs_rex()) {
4838 prefix(REX_WRXB);
4839 } else {
4840 prefix(REX_WRB);
4841 }
4842 } else {
4843 if (adr.index_needs_rex()) {
4844 prefix(REX_WRX);
4845 } else {
4846 prefix(REX_WR);
4847 }
4848 }
4849 }
4850 }
4851
4852 void Assembler::adcq(Register dst, int32_t imm32) {
4853 (void) prefixq_and_encode(dst->encoding());
4854 emit_arith(0x81, 0xD0, dst, imm32);
4855 }
4856
4857 void Assembler::adcq(Register dst, Address src) {
4858 InstructionMark im(this);
4859 prefixq(src, dst);
4860 emit_int8(0x13);
4861 emit_operand(dst, src);
4862 }
4863
4864 void Assembler::adcq(Register dst, Register src) {
4865 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4866 emit_arith(0x13, 0xC0, dst, src);
4867 }
4868
4869 void Assembler::addq(Address dst, int32_t imm32) {
4870 InstructionMark im(this);
4871 prefixq(dst);
4872 emit_arith_operand(0x81, rax, dst,imm32);
4873 }
4874
4875 void Assembler::addq(Address dst, Register src) {
4876 InstructionMark im(this);
4877 prefixq(dst, src);
4878 emit_int8(0x01);
4879 emit_operand(src, dst);
4880 }
4881
4882 void Assembler::addq(Register dst, int32_t imm32) {
4883 (void) prefixq_and_encode(dst->encoding());
4884 emit_arith(0x81, 0xC0, dst, imm32);
4885 }
4886
4887 void Assembler::addq(Register dst, Address src) {
4888 InstructionMark im(this);
4889 prefixq(src, dst);
4890 emit_int8(0x03);
4891 emit_operand(dst, src);
4892 }
4893
4894 void Assembler::addq(Register dst, Register src) {
4895 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4896 emit_arith(0x03, 0xC0, dst, src);
4897 }
4898
4899 void Assembler::andq(Address dst, int32_t imm32) {
4900 InstructionMark im(this);
4901 prefixq(dst);
4902 emit_int8((unsigned char)0x81);
4903 emit_operand(rsp, dst, 4);
4904 emit_int32(imm32);
4905 }
4906
4907 void Assembler::andq(Register dst, int32_t imm32) {
4908 (void) prefixq_and_encode(dst->encoding());
4909 emit_arith(0x81, 0xE0, dst, imm32);
4910 }
4911
4912 void Assembler::andq(Register dst, Address src) {
4913 InstructionMark im(this);
4914 prefixq(src, dst);
4915 emit_int8(0x23);
4916 emit_operand(dst, src);
4917 }
4918
4919 void Assembler::andq(Register dst, Register src) {
4920 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4921 emit_arith(0x23, 0xC0, dst, src);
4922 }
4923
4924 void Assembler::andnq(Register dst, Register src1, Register src2) {
4925 InstructionMark im(this);
4926 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4927 int encode = vex_prefix_and_encode(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4928 emit_int8((unsigned char)0xF2);
4929 emit_int8((unsigned char)(0xC0 | encode));
4930 }
4931
4932 void Assembler::andnq(Register dst, Register src1, Address src2) {
4933 InstructionMark im(this);
4934 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4935 vex_prefix(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4936 emit_int8((unsigned char)0xF2);
4937 emit_operand(dst, src2);
4938 }
4939
4940 void Assembler::bsfq(Register dst, Register src) {
4941 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4942 emit_int8(0x0F);
4943 emit_int8((unsigned char)0xBC);
4944 emit_int8((unsigned char)(0xC0 | encode));
4945 }
4946
4947 void Assembler::bsrq(Register dst, Register src) {
4948 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4949 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4950 emit_int8(0x0F);
4951 emit_int8((unsigned char)0xBD);
4952 emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954
4955 void Assembler::bswapq(Register reg) {
4956 int encode = prefixq_and_encode(reg->encoding());
4957 emit_int8(0x0F);
4958 emit_int8((unsigned char)(0xC8 | encode));
4959 }
4960
4961 void Assembler::blsiq(Register dst, Register src) {
4962 InstructionMark im(this);
4963 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4964 int encode = vex_prefix_and_encode(rbx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4965 emit_int8((unsigned char)0xF3);
4966 emit_int8((unsigned char)(0xC0 | encode));
4967 }
4968
4969 void Assembler::blsiq(Register dst, Address src) {
4970 InstructionMark im(this);
4971 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4972 vex_prefix(rbx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4973 emit_int8((unsigned char)0xF3);
4974 emit_operand(rbx, src);
4975 }
4976
4977 void Assembler::blsmskq(Register dst, Register src) {
4978 InstructionMark im(this);
4979 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4980 int encode = vex_prefix_and_encode(rdx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4981 emit_int8((unsigned char)0xF3);
4982 emit_int8((unsigned char)(0xC0 | encode));
4983 }
4984
4985 void Assembler::blsmskq(Register dst, Address src) {
4986 InstructionMark im(this);
4987 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4988 vex_prefix(rdx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4989 emit_int8((unsigned char)0xF3);
4990 emit_operand(rdx, src);
4991 }
4992
4993 void Assembler::blsrq(Register dst, Register src) {
4994 InstructionMark im(this);
4995 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4996 int encode = vex_prefix_and_encode(rcx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
4997 emit_int8((unsigned char)0xF3);
4998 emit_int8((unsigned char)(0xC0 | encode));
4999 }
5000
5001 void Assembler::blsrq(Register dst, Address src) {
5002 InstructionMark im(this);
5003 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5004 vex_prefix(rcx, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, true, false);
5005 emit_int8((unsigned char)0xF3);
5006 emit_operand(rcx, src);
5007 }
5008
5009 void Assembler::cdqq() {
5010 prefix(REX_W);
5011 emit_int8((unsigned char)0x99);
5012 }
5013
5014 void Assembler::clflush(Address adr) {
5015 prefix(adr);
5016 emit_int8(0x0F);
5017 emit_int8((unsigned char)0xAE);
5018 emit_operand(rdi, adr);
5019 }
5020
5021 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5022 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5023 emit_int8(0x0F);
5024 emit_int8(0x40 | cc);
5025 emit_int8((unsigned char)(0xC0 | encode));
5026 }
5027
5028 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5029 InstructionMark im(this);
5030 prefixq(src, dst);
5031 emit_int8(0x0F);
5032 emit_int8(0x40 | cc);
5033 emit_operand(dst, src);
5034 }
5035
5036 void Assembler::cmpq(Address dst, int32_t imm32) {
5037 InstructionMark im(this);
5038 prefixq(dst);
5039 emit_int8((unsigned char)0x81);
5040 emit_operand(rdi, dst, 4);
5041 emit_int32(imm32);
5042 }
5043
5044 void Assembler::cmpq(Register dst, int32_t imm32) {
5045 (void) prefixq_and_encode(dst->encoding());
5046 emit_arith(0x81, 0xF8, dst, imm32);
5047 }
5048
5049 void Assembler::cmpq(Address dst, Register src) {
5050 InstructionMark im(this);
5051 prefixq(dst, src);
5052 emit_int8(0x3B);
5053 emit_operand(src, dst);
5054 }
5055
5056 void Assembler::cmpq(Register dst, Register src) {
5057 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5058 emit_arith(0x3B, 0xC0, dst, src);
5059 }
5060
5061 void Assembler::cmpq(Register dst, Address src) {
5062 InstructionMark im(this);
5063 prefixq(src, dst);
5064 emit_int8(0x3B);
5065 emit_operand(dst, src);
5066 }
5067
5068 void Assembler::cmpxchgq(Register reg, Address adr) {
5069 InstructionMark im(this);
5070 prefixq(adr, reg);
5071 emit_int8(0x0F);
5072 emit_int8((unsigned char)0xB1);
5073 emit_operand(reg, adr);
5074 }
5075
5076 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5077 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5078 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5079 emit_int8(0x2A);
5080 emit_int8((unsigned char)(0xC0 | encode));
5081 }
5082
5083 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5085 InstructionMark im(this);
5086 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5087 emit_int8(0x2A);
5088 emit_operand(dst, src);
5089 }
5090
5091 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5092 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5093 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5094 emit_int8(0x2A);
5095 emit_int8((unsigned char)(0xC0 | encode));
5096 }
5097
5098 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5099 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5100 InstructionMark im(this);
5101 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5102 emit_int8(0x2A);
5103 emit_operand(dst, src);
5104 }
5105
5106 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5107 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5108 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5109 emit_int8(0x2C);
5110 emit_int8((unsigned char)(0xC0 | encode));
5111 }
5112
5113 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5114 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5115 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5116 emit_int8(0x2C);
5117 emit_int8((unsigned char)(0xC0 | encode));
5118 }
5119
5120 void Assembler::decl(Register dst) {
5121 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5122 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5123 int encode = prefix_and_encode(dst->encoding());
5124 emit_int8((unsigned char)0xFF);
5125 emit_int8((unsigned char)(0xC8 | encode));
5126 }
5127
5128 void Assembler::decq(Register dst) {
5129 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5130 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5131 int encode = prefixq_and_encode(dst->encoding());
5132 emit_int8((unsigned char)0xFF);
5133 emit_int8(0xC8 | encode);
5134 }
5135
5136 void Assembler::decq(Address dst) {
5137 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5138 InstructionMark im(this);
5139 prefixq(dst);
5140 emit_int8((unsigned char)0xFF);
5141 emit_operand(rcx, dst);
5142 }
5143
5144 void Assembler::fxrstor(Address src) {
5145 prefixq(src);
5146 emit_int8(0x0F);
5147 emit_int8((unsigned char)0xAE);
5148 emit_operand(as_Register(1), src);
5149 }
5150
5151 void Assembler::fxsave(Address dst) {
5152 prefixq(dst);
5153 emit_int8(0x0F);
5154 emit_int8((unsigned char)0xAE);
5155 emit_operand(as_Register(0), dst);
5156 }
5157
5158 void Assembler::idivq(Register src) {
5159 int encode = prefixq_and_encode(src->encoding());
5160 emit_int8((unsigned char)0xF7);
5161 emit_int8((unsigned char)(0xF8 | encode));
5162 }
5163
5164 void Assembler::imulq(Register dst, Register src) {
5165 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5166 emit_int8(0x0F);
5167 emit_int8((unsigned char)0xAF);
5168 emit_int8((unsigned char)(0xC0 | encode));
5169 }
5170
5171 void Assembler::imulq(Register dst, Register src, int value) {
5172 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5173 if (is8bit(value)) {
5174 emit_int8(0x6B);
5175 emit_int8((unsigned char)(0xC0 | encode));
5176 emit_int8(value & 0xFF);
5177 } else {
5178 emit_int8(0x69);
5179 emit_int8((unsigned char)(0xC0 | encode));
5180 emit_int32(value);
5181 }
5182 }
5183
5184 void Assembler::imulq(Register dst, Address src) {
5185 InstructionMark im(this);
5186 prefixq(src, dst);
5187 emit_int8(0x0F);
5188 emit_int8((unsigned char) 0xAF);
5189 emit_operand(dst, src);
5190 }
5191
5192 void Assembler::incl(Register dst) {
5193 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5194 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5195 int encode = prefix_and_encode(dst->encoding());
5196 emit_int8((unsigned char)0xFF);
5197 emit_int8((unsigned char)(0xC0 | encode));
5198 }
5199
5200 void Assembler::incq(Register dst) {
5201 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5202 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5203 int encode = prefixq_and_encode(dst->encoding());
5204 emit_int8((unsigned char)0xFF);
5205 emit_int8((unsigned char)(0xC0 | encode));
5206 }
5207
5208 void Assembler::incq(Address dst) {
5209 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5210 InstructionMark im(this);
5211 prefixq(dst);
5212 emit_int8((unsigned char)0xFF);
5213 emit_operand(rax, dst);
5214 }
5215
5216 void Assembler::lea(Register dst, Address src) {
5217 leaq(dst, src);
5218 }
5219
5220 void Assembler::leaq(Register dst, Address src) {
5221 InstructionMark im(this);
5222 prefixq(src, dst);
5223 emit_int8((unsigned char)0x8D);
5224 emit_operand(dst, src);
5225 }
5226
5227 void Assembler::mov64(Register dst, int64_t imm64) {
5228 InstructionMark im(this);
5229 int encode = prefixq_and_encode(dst->encoding());
5230 emit_int8((unsigned char)(0xB8 | encode));
5231 emit_int64(imm64);
5232 }
5233
5234 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5235 InstructionMark im(this);
5236 int encode = prefixq_and_encode(dst->encoding());
5237 emit_int8(0xB8 | encode);
5238 emit_data64(imm64, rspec);
5239 }
5240
5241 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5242 InstructionMark im(this);
5243 int encode = prefix_and_encode(dst->encoding());
5244 emit_int8((unsigned char)(0xB8 | encode));
5245 emit_data((int)imm32, rspec, narrow_oop_operand);
5246 }
5247
5248 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5249 InstructionMark im(this);
5250 prefix(dst);
5251 emit_int8((unsigned char)0xC7);
5252 emit_operand(rax, dst, 4);
5253 emit_data((int)imm32, rspec, narrow_oop_operand);
5254 }
5255
5256 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5257 InstructionMark im(this);
5258 int encode = prefix_and_encode(src1->encoding());
5259 emit_int8((unsigned char)0x81);
5260 emit_int8((unsigned char)(0xF8 | encode));
5261 emit_data((int)imm32, rspec, narrow_oop_operand);
5262 }
5263
5264 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5265 InstructionMark im(this);
5266 prefix(src1);
5267 emit_int8((unsigned char)0x81);
5268 emit_operand(rax, src1, 4);
5269 emit_data((int)imm32, rspec, narrow_oop_operand);
5270 }
5271
5272 void Assembler::lzcntq(Register dst, Register src) {
5273 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5274 emit_int8((unsigned char)0xF3);
5275 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5276 emit_int8(0x0F);
5277 emit_int8((unsigned char)0xBD);
5278 emit_int8((unsigned char)(0xC0 | encode));
5279 }
5280
5281 void Assembler::movdq(XMMRegister dst, Register src) {
5282 // table D-1 says MMX/SSE2
5283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5284 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5285 emit_int8(0x6E);
5286 emit_int8((unsigned char)(0xC0 | encode));
5287 }
5288
5289 void Assembler::movdq(Register dst, XMMRegister src) {
5290 // table D-1 says MMX/SSE2
5291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5292 // swap src/dst to get correct prefix
5293 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5294 emit_int8(0x7E);
5295 emit_int8((unsigned char)(0xC0 | encode));
5296 }
5297
5298 void Assembler::movq(Register dst, Register src) {
5299 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5300 emit_int8((unsigned char)0x8B);
5301 emit_int8((unsigned char)(0xC0 | encode));
5302 }
5303
5304 void Assembler::movq(Register dst, Address src) {
5305 InstructionMark im(this);
5306 prefixq(src, dst);
5307 emit_int8((unsigned char)0x8B);
5308 emit_operand(dst, src);
5309 }
5310
5311 void Assembler::movq(Address dst, Register src) {
5312 InstructionMark im(this);
5313 prefixq(dst, src);
5314 emit_int8((unsigned char)0x89);
5315 emit_operand(src, dst);
5316 }
5317
5318 void Assembler::movsbq(Register dst, Address src) {
5319 InstructionMark im(this);
5320 prefixq(src, dst);
5321 emit_int8(0x0F);
5322 emit_int8((unsigned char)0xBE);
5323 emit_operand(dst, src);
5324 }
5325
5326 void Assembler::movsbq(Register dst, Register src) {
5327 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5328 emit_int8(0x0F);
5329 emit_int8((unsigned char)0xBE);
5330 emit_int8((unsigned char)(0xC0 | encode));
5331 }
5332
5333 void Assembler::movslq(Register dst, int32_t imm32) {
5334 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5335 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5336 // as a result we shouldn't use until tested at runtime...
5337 ShouldNotReachHere();
5338 InstructionMark im(this);
5339 int encode = prefixq_and_encode(dst->encoding());
5340 emit_int8((unsigned char)(0xC7 | encode));
5341 emit_int32(imm32);
5342 }
5343
5344 void Assembler::movslq(Address dst, int32_t imm32) {
5345 assert(is_simm32(imm32), "lost bits");
5346 InstructionMark im(this);
5347 prefixq(dst);
5348 emit_int8((unsigned char)0xC7);
5349 emit_operand(rax, dst, 4);
5350 emit_int32(imm32);
5351 }
5352
5353 void Assembler::movslq(Register dst, Address src) {
5354 InstructionMark im(this);
5355 prefixq(src, dst);
5356 emit_int8(0x63);
5357 emit_operand(dst, src);
5358 }
5359
5360 void Assembler::movslq(Register dst, Register src) {
5361 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5362 emit_int8(0x63);
5363 emit_int8((unsigned char)(0xC0 | encode));
5364 }
5365
5366 void Assembler::movswq(Register dst, Address src) {
5367 InstructionMark im(this);
5368 prefixq(src, dst);
5369 emit_int8(0x0F);
5370 emit_int8((unsigned char)0xBF);
5371 emit_operand(dst, src);
5372 }
5373
5374 void Assembler::movswq(Register dst, Register src) {
5375 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5376 emit_int8((unsigned char)0x0F);
5377 emit_int8((unsigned char)0xBF);
5378 emit_int8((unsigned char)(0xC0 | encode));
5379 }
5380
5381 void Assembler::movzbq(Register dst, Address src) {
5382 InstructionMark im(this);
5383 prefixq(src, dst);
5384 emit_int8((unsigned char)0x0F);
5385 emit_int8((unsigned char)0xB6);
5386 emit_operand(dst, src);
5387 }
5388
5389 void Assembler::movzbq(Register dst, Register src) {
5390 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5391 emit_int8(0x0F);
5392 emit_int8((unsigned char)0xB6);
5393 emit_int8(0xC0 | encode);
5394 }
5395
5396 void Assembler::movzwq(Register dst, Address src) {
5397 InstructionMark im(this);
5398 prefixq(src, dst);
5399 emit_int8((unsigned char)0x0F);
5400 emit_int8((unsigned char)0xB7);
5401 emit_operand(dst, src);
5402 }
5403
5404 void Assembler::movzwq(Register dst, Register src) {
5405 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5406 emit_int8((unsigned char)0x0F);
5407 emit_int8((unsigned char)0xB7);
5408 emit_int8((unsigned char)(0xC0 | encode));
5409 }
5410
5411 void Assembler::negq(Register dst) {
5412 int encode = prefixq_and_encode(dst->encoding());
5413 emit_int8((unsigned char)0xF7);
5414 emit_int8((unsigned char)(0xD8 | encode));
5415 }
5416
5417 void Assembler::notq(Register dst) {
5418 int encode = prefixq_and_encode(dst->encoding());
5419 emit_int8((unsigned char)0xF7);
5420 emit_int8((unsigned char)(0xD0 | encode));
5421 }
5422
5423 void Assembler::orq(Address dst, int32_t imm32) {
5424 InstructionMark im(this);
5425 prefixq(dst);
5426 emit_int8((unsigned char)0x81);
5427 emit_operand(rcx, dst, 4);
5428 emit_int32(imm32);
5429 }
5430
5431 void Assembler::orq(Register dst, int32_t imm32) {
5432 (void) prefixq_and_encode(dst->encoding());
5433 emit_arith(0x81, 0xC8, dst, imm32);
5434 }
5435
5436 void Assembler::orq(Register dst, Address src) {
5437 InstructionMark im(this);
5438 prefixq(src, dst);
5439 emit_int8(0x0B);
5440 emit_operand(dst, src);
5441 }
5442
5443 void Assembler::orq(Register dst, Register src) {
5444 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5445 emit_arith(0x0B, 0xC0, dst, src);
5446 }
5447
5448 void Assembler::popa() { // 64bit
5449 movq(r15, Address(rsp, 0));
5450 movq(r14, Address(rsp, wordSize));
5451 movq(r13, Address(rsp, 2 * wordSize));
5452 movq(r12, Address(rsp, 3 * wordSize));
5453 movq(r11, Address(rsp, 4 * wordSize));
5454 movq(r10, Address(rsp, 5 * wordSize));
5455 movq(r9, Address(rsp, 6 * wordSize));
5456 movq(r8, Address(rsp, 7 * wordSize));
5457 movq(rdi, Address(rsp, 8 * wordSize));
5458 movq(rsi, Address(rsp, 9 * wordSize));
5459 movq(rbp, Address(rsp, 10 * wordSize));
5460 // skip rsp
5461 movq(rbx, Address(rsp, 12 * wordSize));
5462 movq(rdx, Address(rsp, 13 * wordSize));
5463 movq(rcx, Address(rsp, 14 * wordSize));
5464 movq(rax, Address(rsp, 15 * wordSize));
5465
5466 addq(rsp, 16 * wordSize);
5467 }
5468
5469 void Assembler::popcntq(Register dst, Address src) {
5470 assert(VM_Version::supports_popcnt(), "must support");
5471 InstructionMark im(this);
5472 emit_int8((unsigned char)0xF3);
5473 prefixq(src, dst);
5474 emit_int8((unsigned char)0x0F);
5475 emit_int8((unsigned char)0xB8);
5476 emit_operand(dst, src);
5477 }
5478
5479 void Assembler::popcntq(Register dst, Register src) {
5480 assert(VM_Version::supports_popcnt(), "must support");
5481 emit_int8((unsigned char)0xF3);
5482 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5483 emit_int8((unsigned char)0x0F);
5484 emit_int8((unsigned char)0xB8);
5485 emit_int8((unsigned char)(0xC0 | encode));
5486 }
5487
5488 void Assembler::popq(Address dst) {
5489 InstructionMark im(this);
5490 prefixq(dst);
5491 emit_int8((unsigned char)0x8F);
5492 emit_operand(rax, dst);
5493 }
5494
5495 void Assembler::pusha() { // 64bit
5496 // we have to store original rsp. ABI says that 128 bytes
5497 // below rsp are local scratch.
5498 movq(Address(rsp, -5 * wordSize), rsp);
5499
5500 subq(rsp, 16 * wordSize);
5501
5502 movq(Address(rsp, 15 * wordSize), rax);
5503 movq(Address(rsp, 14 * wordSize), rcx);
5504 movq(Address(rsp, 13 * wordSize), rdx);
5505 movq(Address(rsp, 12 * wordSize), rbx);
5506 // skip rsp
5507 movq(Address(rsp, 10 * wordSize), rbp);
5508 movq(Address(rsp, 9 * wordSize), rsi);
5509 movq(Address(rsp, 8 * wordSize), rdi);
5510 movq(Address(rsp, 7 * wordSize), r8);
5511 movq(Address(rsp, 6 * wordSize), r9);
5512 movq(Address(rsp, 5 * wordSize), r10);
5513 movq(Address(rsp, 4 * wordSize), r11);
5514 movq(Address(rsp, 3 * wordSize), r12);
5515 movq(Address(rsp, 2 * wordSize), r13);
5516 movq(Address(rsp, wordSize), r14);
5517 movq(Address(rsp, 0), r15);
5518 }
5519
5520 void Assembler::pushq(Address src) {
5521 InstructionMark im(this);
5522 prefixq(src);
5523 emit_int8((unsigned char)0xFF);
5524 emit_operand(rsi, src);
5525 }
5526
5527 void Assembler::rclq(Register dst, int imm8) {
5528 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5529 int encode = prefixq_and_encode(dst->encoding());
5530 if (imm8 == 1) {
5531 emit_int8((unsigned char)0xD1);
5532 emit_int8((unsigned char)(0xD0 | encode));
5533 } else {
5534 emit_int8((unsigned char)0xC1);
5535 emit_int8((unsigned char)(0xD0 | encode));
5536 emit_int8(imm8);
5537 }
5538 }
5539 void Assembler::sarq(Register dst, int imm8) {
5540 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5541 int encode = prefixq_and_encode(dst->encoding());
5542 if (imm8 == 1) {
5543 emit_int8((unsigned char)0xD1);
5544 emit_int8((unsigned char)(0xF8 | encode));
5545 } else {
5546 emit_int8((unsigned char)0xC1);
5547 emit_int8((unsigned char)(0xF8 | encode));
5548 emit_int8(imm8);
5549 }
5550 }
5551
5552 void Assembler::sarq(Register dst) {
5553 int encode = prefixq_and_encode(dst->encoding());
5554 emit_int8((unsigned char)0xD3);
5555 emit_int8((unsigned char)(0xF8 | encode));
5556 }
5557
5558 void Assembler::sbbq(Address dst, int32_t imm32) {
5559 InstructionMark im(this);
5560 prefixq(dst);
5561 emit_arith_operand(0x81, rbx, dst, imm32);
5562 }
5563
5564 void Assembler::sbbq(Register dst, int32_t imm32) {
5565 (void) prefixq_and_encode(dst->encoding());
5566 emit_arith(0x81, 0xD8, dst, imm32);
5567 }
5568
5569 void Assembler::sbbq(Register dst, Address src) {
5570 InstructionMark im(this);
5571 prefixq(src, dst);
5572 emit_int8(0x1B);
5573 emit_operand(dst, src);
5574 }
5575
5576 void Assembler::sbbq(Register dst, Register src) {
5577 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5578 emit_arith(0x1B, 0xC0, dst, src);
5579 }
5580
5581 void Assembler::shlq(Register dst, int imm8) {
5582 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5583 int encode = prefixq_and_encode(dst->encoding());
5584 if (imm8 == 1) {
5585 emit_int8((unsigned char)0xD1);
5586 emit_int8((unsigned char)(0xE0 | encode));
5587 } else {
5588 emit_int8((unsigned char)0xC1);
5589 emit_int8((unsigned char)(0xE0 | encode));
5590 emit_int8(imm8);
5591 }
5592 }
5593
5594 void Assembler::shlq(Register dst) {
5595 int encode = prefixq_and_encode(dst->encoding());
5596 emit_int8((unsigned char)0xD3);
5597 emit_int8((unsigned char)(0xE0 | encode));
5598 }
5599
5600 void Assembler::shrq(Register dst, int imm8) {
5601 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5602 int encode = prefixq_and_encode(dst->encoding());
5603 emit_int8((unsigned char)0xC1);
5604 emit_int8((unsigned char)(0xE8 | encode));
5605 emit_int8(imm8);
5606 }
5607
5608 void Assembler::shrq(Register dst) {
5609 int encode = prefixq_and_encode(dst->encoding());
5610 emit_int8((unsigned char)0xD3);
5611 emit_int8(0xE8 | encode);
5612 }
5613
5614 void Assembler::subq(Address dst, int32_t imm32) {
5615 InstructionMark im(this);
5616 prefixq(dst);
5617 emit_arith_operand(0x81, rbp, dst, imm32);
5618 }
5619
5620 void Assembler::subq(Address dst, Register src) {
5621 InstructionMark im(this);
5622 prefixq(dst, src);
5623 emit_int8(0x29);
5624 emit_operand(src, dst);
5625 }
5626
5627 void Assembler::subq(Register dst, int32_t imm32) {
5628 (void) prefixq_and_encode(dst->encoding());
5629 emit_arith(0x81, 0xE8, dst, imm32);
5630 }
5631
5632 // Force generation of a 4 byte immediate value even if it fits into 8bit
5633 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5634 (void) prefixq_and_encode(dst->encoding());
5635 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5636 }
5637
5638 void Assembler::subq(Register dst, Address src) {
5639 InstructionMark im(this);
5640 prefixq(src, dst);
5641 emit_int8(0x2B);
5642 emit_operand(dst, src);
5643 }
5644
5645 void Assembler::subq(Register dst, Register src) {
5646 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5647 emit_arith(0x2B, 0xC0, dst, src);
5648 }
5649
5650 void Assembler::testq(Register dst, int32_t imm32) {
5651 // not using emit_arith because test
5652 // doesn't support sign-extension of
5653 // 8bit operands
5654 int encode = dst->encoding();
5655 if (encode == 0) {
5656 prefix(REX_W);
5657 emit_int8((unsigned char)0xA9);
5658 } else {
5659 encode = prefixq_and_encode(encode);
5660 emit_int8((unsigned char)0xF7);
5661 emit_int8((unsigned char)(0xC0 | encode));
5662 }
5663 emit_int32(imm32);
5664 }
5665
5666 void Assembler::testq(Register dst, Register src) {
5667 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5668 emit_arith(0x85, 0xC0, dst, src);
5669 }
5670
5671 void Assembler::xaddq(Address dst, Register src) {
5672 InstructionMark im(this);
5673 prefixq(dst, src);
5674 emit_int8(0x0F);
5675 emit_int8((unsigned char)0xC1);
5676 emit_operand(src, dst);
5677 }
5678
5679 void Assembler::xchgq(Register dst, Address src) {
5680 InstructionMark im(this);
5681 prefixq(src, dst);
5682 emit_int8((unsigned char)0x87);
5683 emit_operand(dst, src);
5684 }
5685
5686 void Assembler::xchgq(Register dst, Register src) {
5687 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5688 emit_int8((unsigned char)0x87);
5689 emit_int8((unsigned char)(0xc0 | encode));
5690 }
5691
5692 void Assembler::xorq(Register dst, Register src) {
5693 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5694 emit_arith(0x33, 0xC0, dst, src);
5695 }
5696
5697 void Assembler::xorq(Register dst, Address src) {
5698 InstructionMark im(this);
5699 prefixq(src, dst);
5700 emit_int8(0x33);
5701 emit_operand(dst, src);
5702 }
5703
5704 #endif // !LP64