573 void rex_prefix(Address adr, XMMRegister xreg,
574 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
575 int rex_prefix_and_encode(int dst_enc, int src_enc,
576 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
577
578 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
579 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
580 bool vector256);
581
582 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
583 VexSimdPrefix pre, VexOpcode opc,
584 bool vex_w, bool vector256);
585
586 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
587 VexSimdPrefix pre, bool vector256 = false) {
588 int dst_enc = dst->encoding();
589 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
590 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
591 }
592
593 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
594 VexSimdPrefix pre, VexOpcode opc,
595 bool vex_w, bool vector256);
596
597 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
598 VexSimdPrefix pre, bool vector256 = false,
599 VexOpcode opc = VEX_OPCODE_0F) {
600 int src_enc = src->encoding();
601 int dst_enc = dst->encoding();
602 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
603 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
604 }
605
606 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
607 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
608 bool rex_w = false, bool vector256 = false);
609
610 void simd_prefix(XMMRegister dst, Address src,
611 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
612 simd_prefix(dst, xnoreg, src, pre, opc);
613 }
614
615 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
616 simd_prefix(src, dst, pre);
880 void aesdec(XMMRegister dst, Address src);
881 void aesdec(XMMRegister dst, XMMRegister src);
882 void aesdeclast(XMMRegister dst, Address src);
883 void aesdeclast(XMMRegister dst, XMMRegister src);
884 void aesenc(XMMRegister dst, Address src);
885 void aesenc(XMMRegister dst, XMMRegister src);
886 void aesenclast(XMMRegister dst, Address src);
887 void aesenclast(XMMRegister dst, XMMRegister src);
888
889
890 void andl(Address dst, int32_t imm32);
891 void andl(Register dst, int32_t imm32);
892 void andl(Register dst, Address src);
893 void andl(Register dst, Register src);
894
895 void andq(Address dst, int32_t imm32);
896 void andq(Register dst, int32_t imm32);
897 void andq(Register dst, Address src);
898 void andq(Register dst, Register src);
899
900 void bsfl(Register dst, Register src);
901 void bsrl(Register dst, Register src);
902
903 #ifdef _LP64
904 void bsfq(Register dst, Register src);
905 void bsrq(Register dst, Register src);
906 #endif
907
908 void bswapl(Register reg);
909
910 void bswapq(Register reg);
911
912 void call(Label& L, relocInfo::relocType rtype);
913 void call(Register reg); // push pc; pc <- reg
914 void call(Address adr); // push pc; pc <- adr
915
916 void cdql();
917
918 void cdqq();
919
1557 void subl_imm32(Register dst, int32_t imm32);
1558 void subq_imm32(Register dst, int32_t imm32);
1559
1560 // Subtract Scalar Double-Precision Floating-Point Values
1561 void subsd(XMMRegister dst, Address src);
1562 void subsd(XMMRegister dst, XMMRegister src);
1563
1564 // Subtract Scalar Single-Precision Floating-Point Values
1565 void subss(XMMRegister dst, Address src);
1566 void subss(XMMRegister dst, XMMRegister src);
1567
1568 void testb(Register dst, int imm8);
1569
1570 void testl(Register dst, int32_t imm32);
1571 void testl(Register dst, Register src);
1572 void testl(Register dst, Address src);
1573
1574 void testq(Register dst, int32_t imm32);
1575 void testq(Register dst, Register src);
1576
1577
1578 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1579 void ucomisd(XMMRegister dst, Address src);
1580 void ucomisd(XMMRegister dst, XMMRegister src);
1581
1582 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1583 void ucomiss(XMMRegister dst, Address src);
1584 void ucomiss(XMMRegister dst, XMMRegister src);
1585
1586 void xaddl(Address dst, Register src);
1587
1588 void xaddq(Address dst, Register src);
1589
1590 void xchgl(Register reg, Address adr);
1591 void xchgl(Register dst, Register src);
1592
1593 void xchgq(Register reg, Address adr);
1594 void xchgq(Register dst, Register src);
1595
1596 // Get Value of Extended Control Register
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573 void rex_prefix(Address adr, XMMRegister xreg,
574 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
575 int rex_prefix_and_encode(int dst_enc, int src_enc,
576 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
577
578 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
579 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
580 bool vector256);
581
582 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
583 VexSimdPrefix pre, VexOpcode opc,
584 bool vex_w, bool vector256);
585
586 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
587 VexSimdPrefix pre, bool vector256 = false) {
588 int dst_enc = dst->encoding();
589 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
590 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
591 }
592
593 void vex_prefix(Register dst, Register nds, Address src,
594 VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
595 vex_prefix(src, nds->encoding(), dst->encoding(),
596 pre, opc, vex_w, vector256);
597 }
598
599 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
600 VexSimdPrefix pre, VexOpcode opc,
601 bool vex_w, bool vector256);
602
603 int vex_prefix_and_encode(Register dst, Register nds, Register src,
604 VexSimdPrefix pre, VexOpcode opc,
605 bool vex_w, bool vector256) {
606 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
607 pre, opc, vex_w, vector256);
608 }
609
610 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
611 VexSimdPrefix pre, bool vector256 = false,
612 VexOpcode opc = VEX_OPCODE_0F) {
613 int src_enc = src->encoding();
614 int dst_enc = dst->encoding();
615 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
616 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
617 }
618
619 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
620 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
621 bool rex_w = false, bool vector256 = false);
622
623 void simd_prefix(XMMRegister dst, Address src,
624 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
625 simd_prefix(dst, xnoreg, src, pre, opc);
626 }
627
628 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
629 simd_prefix(src, dst, pre);
893 void aesdec(XMMRegister dst, Address src);
894 void aesdec(XMMRegister dst, XMMRegister src);
895 void aesdeclast(XMMRegister dst, Address src);
896 void aesdeclast(XMMRegister dst, XMMRegister src);
897 void aesenc(XMMRegister dst, Address src);
898 void aesenc(XMMRegister dst, XMMRegister src);
899 void aesenclast(XMMRegister dst, Address src);
900 void aesenclast(XMMRegister dst, XMMRegister src);
901
902
903 void andl(Address dst, int32_t imm32);
904 void andl(Register dst, int32_t imm32);
905 void andl(Register dst, Address src);
906 void andl(Register dst, Register src);
907
908 void andq(Address dst, int32_t imm32);
909 void andq(Register dst, int32_t imm32);
910 void andq(Register dst, Address src);
911 void andq(Register dst, Register src);
912
913 // BMI instructions
914 void andnl(Register dst, Register src1, Register src2);
915 void andnl(Register dst, Register src1, Address src2);
916 void andnq(Register dst, Register src1, Register src2);
917 void andnq(Register dst, Register src1, Address src2);
918
919 void blsil(Register dst, Register src);
920 void blsil(Register dst, Address src);
921 void blsiq(Register dst, Register src);
922 void blsiq(Register dst, Address src);
923
924 void blsmskl(Register dst, Register src);
925 void blsmskl(Register dst, Address src);
926 void blsmskq(Register dst, Register src);
927 void blsmskq(Register dst, Address src);
928
929 void blsrl(Register dst, Register src);
930 void blsrl(Register dst, Address src);
931 void blsrq(Register dst, Register src);
932 void blsrq(Register dst, Address src);
933
934 void bsfl(Register dst, Register src);
935 void bsrl(Register dst, Register src);
936
937 #ifdef _LP64
938 void bsfq(Register dst, Register src);
939 void bsrq(Register dst, Register src);
940 #endif
941
942 void bswapl(Register reg);
943
944 void bswapq(Register reg);
945
946 void call(Label& L, relocInfo::relocType rtype);
947 void call(Register reg); // push pc; pc <- reg
948 void call(Address adr); // push pc; pc <- adr
949
950 void cdql();
951
952 void cdqq();
953
1591 void subl_imm32(Register dst, int32_t imm32);
1592 void subq_imm32(Register dst, int32_t imm32);
1593
1594 // Subtract Scalar Double-Precision Floating-Point Values
1595 void subsd(XMMRegister dst, Address src);
1596 void subsd(XMMRegister dst, XMMRegister src);
1597
1598 // Subtract Scalar Single-Precision Floating-Point Values
1599 void subss(XMMRegister dst, Address src);
1600 void subss(XMMRegister dst, XMMRegister src);
1601
1602 void testb(Register dst, int imm8);
1603
1604 void testl(Register dst, int32_t imm32);
1605 void testl(Register dst, Register src);
1606 void testl(Register dst, Address src);
1607
1608 void testq(Register dst, int32_t imm32);
1609 void testq(Register dst, Register src);
1610
1611 // BMI - count trailing zeros
1612 void tzcntl(Register dst, Register src);
1613 void tzcntq(Register dst, Register src);
1614
1615 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1616 void ucomisd(XMMRegister dst, Address src);
1617 void ucomisd(XMMRegister dst, XMMRegister src);
1618
1619 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1620 void ucomiss(XMMRegister dst, Address src);
1621 void ucomiss(XMMRegister dst, XMMRegister src);
1622
1623 void xaddl(Address dst, Register src);
1624
1625 void xaddq(Address dst, Register src);
1626
1627 void xchgl(Register reg, Address adr);
1628 void xchgl(Register dst, Register src);
1629
1630 void xchgq(Register reg, Address adr);
1631 void xchgq(Register dst, Register src);
1632
1633 // Get Value of Extended Control Register
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