1 /* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VM_VERSION_X86_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version : public Abstract_VM_Version { 32 public: 33 // cpuid result register layouts. These are all unions of a uint32_t 34 // (in case anyone wants access to the register as a whole) and a bitfield. 35 36 union StdCpuid1Eax { 37 uint32_t value; 38 struct { 39 uint32_t stepping : 4, 40 model : 4, 41 family : 4, 42 proc_type : 2, 43 : 2, 44 ext_model : 4, 45 ext_family : 8, 46 : 4; 47 } bits; 48 }; 49 50 union StdCpuid1Ebx { // example, unused 51 uint32_t value; 52 struct { 53 uint32_t brand_id : 8, 54 clflush_size : 8, 55 threads_per_cpu : 8, 56 apic_id : 8; 57 } bits; 58 }; 59 60 union StdCpuid1Ecx { 61 uint32_t value; 62 struct { 63 uint32_t sse3 : 1, 64 clmul : 1, 65 : 1, 66 monitor : 1, 67 : 1, 68 vmx : 1, 69 : 1, 70 est : 1, 71 : 1, 72 ssse3 : 1, 73 cid : 1, 74 : 2, 75 cmpxchg16: 1, 76 : 4, 77 dca : 1, 78 sse4_1 : 1, 79 sse4_2 : 1, 80 : 2, 81 popcnt : 1, 82 : 1, 83 aes : 1, 84 : 1, 85 osxsave : 1, 86 avx : 1, 87 : 3; 88 } bits; 89 }; 90 91 union StdCpuid1Edx { 92 uint32_t value; 93 struct { 94 uint32_t : 4, 95 tsc : 1, 96 : 3, 97 cmpxchg8 : 1, 98 : 6, 99 cmov : 1, 100 : 3, 101 clflush : 1, 102 : 3, 103 mmx : 1, 104 fxsr : 1, 105 sse : 1, 106 sse2 : 1, 107 : 1, 108 ht : 1, 109 : 3; 110 } bits; 111 }; 112 113 union DcpCpuid4Eax { 114 uint32_t value; 115 struct { 116 uint32_t cache_type : 5, 117 : 21, 118 cores_per_cpu : 6; 119 } bits; 120 }; 121 122 union DcpCpuid4Ebx { 123 uint32_t value; 124 struct { 125 uint32_t L1_line_size : 12, 126 partitions : 10, 127 associativity : 10; 128 } bits; 129 }; 130 131 union TplCpuidBEbx { 132 uint32_t value; 133 struct { 134 uint32_t logical_cpus : 16, 135 : 16; 136 } bits; 137 }; 138 139 union ExtCpuid1Ecx { 140 uint32_t value; 141 struct { 142 uint32_t LahfSahf : 1, 143 CmpLegacy : 1, 144 : 3, 145 lzcnt_intel : 1, 146 lzcnt : 1, 147 sse4a : 1, 148 misalignsse : 1, 149 prefetchw : 1, 150 : 22; 151 } bits; 152 }; 153 154 union ExtCpuid1Edx { 155 uint32_t value; 156 struct { 157 uint32_t : 22, 158 mmx_amd : 1, 159 mmx : 1, 160 fxsr : 1, 161 : 4, 162 long_mode : 1, 163 tdnow2 : 1, 164 tdnow : 1; 165 } bits; 166 }; 167 168 union ExtCpuid5Ex { 169 uint32_t value; 170 struct { 171 uint32_t L1_line_size : 8, 172 L1_tag_lines : 8, 173 L1_assoc : 8, 174 L1_size : 8; 175 } bits; 176 }; 177 178 union ExtCpuid7Edx { 179 uint32_t value; 180 struct { 181 uint32_t : 8, 182 tsc_invariance : 1, 183 : 23; 184 } bits; 185 }; 186 187 union ExtCpuid8Ecx { 188 uint32_t value; 189 struct { 190 uint32_t cores_per_cpu : 8, 191 : 24; 192 } bits; 193 }; 194 195 union SefCpuid7Eax { 196 uint32_t value; 197 }; 198 199 union SefCpuid7Ebx { 200 uint32_t value; 201 struct { 202 uint32_t fsgsbase : 1, 203 : 2, 204 bmi1 : 1, 205 : 1, 206 avx2 : 1, 207 : 2, 208 bmi2 : 1, 209 erms : 1, 210 : 22; 211 } bits; 212 }; 213 214 union XemXcr0Eax { 215 uint32_t value; 216 struct { 217 uint32_t x87 : 1, 218 sse : 1, 219 ymm : 1, 220 : 29; 221 } bits; 222 }; 223 224 protected: 225 static int _cpu; 226 static int _model; 227 static int _stepping; 228 static int _cpuFeatures; // features returned by the "cpuid" instruction 229 // 0 if this instruction is not available 230 static const char* _features_str; 231 232 enum { 233 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 234 CPU_CMOV = (1 << 1), 235 CPU_FXSR = (1 << 2), 236 CPU_HT = (1 << 3), 237 CPU_MMX = (1 << 4), 238 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 239 // may not necessarily support other 3dnow instructions 240 CPU_SSE = (1 << 6), 241 CPU_SSE2 = (1 << 7), 242 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 243 CPU_SSSE3 = (1 << 9), 244 CPU_SSE4A = (1 << 10), 245 CPU_SSE4_1 = (1 << 11), 246 CPU_SSE4_2 = (1 << 12), 247 CPU_POPCNT = (1 << 13), 248 CPU_LZCNT = (1 << 14), 249 CPU_TSC = (1 << 15), 250 CPU_TSCINV = (1 << 16), 251 CPU_AVX = (1 << 17), 252 CPU_AVX2 = (1 << 18), 253 CPU_AES = (1 << 19), 254 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 255 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 256 CPU_BMI1 = (1 << 22), 257 CPU_BMI2 = (1 << 23) 258 } cpuFeatureFlags; 259 260 enum { 261 // AMD 262 CPU_FAMILY_AMD_11H = 0x11, 263 // Intel 264 CPU_FAMILY_INTEL_CORE = 6, 265 CPU_MODEL_NEHALEM = 0x1e, 266 CPU_MODEL_NEHALEM_EP = 0x1a, 267 CPU_MODEL_NEHALEM_EX = 0x2e, 268 CPU_MODEL_WESTMERE = 0x25, 269 CPU_MODEL_WESTMERE_EP = 0x2c, 270 CPU_MODEL_WESTMERE_EX = 0x2f, 271 CPU_MODEL_SANDYBRIDGE = 0x2a, 272 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 273 CPU_MODEL_IVYBRIDGE_EP = 0x3a 274 } cpuExtendedFamily; 275 276 // cpuid information block. All info derived from executing cpuid with 277 // various function numbers is stored here. Intel and AMD info is 278 // merged in this block: accessor methods disentangle it. 279 // 280 // The info block is laid out in subblocks of 4 dwords corresponding to 281 // eax, ebx, ecx and edx, whether or not they contain anything useful. 282 struct CpuidInfo { 283 // cpuid function 0 284 uint32_t std_max_function; 285 uint32_t std_vendor_name_0; 286 uint32_t std_vendor_name_1; 287 uint32_t std_vendor_name_2; 288 289 // cpuid function 1 290 StdCpuid1Eax std_cpuid1_eax; 291 StdCpuid1Ebx std_cpuid1_ebx; 292 StdCpuid1Ecx std_cpuid1_ecx; 293 StdCpuid1Edx std_cpuid1_edx; 294 295 // cpuid function 4 (deterministic cache parameters) 296 DcpCpuid4Eax dcp_cpuid4_eax; 297 DcpCpuid4Ebx dcp_cpuid4_ebx; 298 uint32_t dcp_cpuid4_ecx; // unused currently 299 uint32_t dcp_cpuid4_edx; // unused currently 300 301 // cpuid function 7 (structured extended features) 302 SefCpuid7Eax sef_cpuid7_eax; 303 SefCpuid7Ebx sef_cpuid7_ebx; 304 uint32_t sef_cpuid7_ecx; // unused currently 305 uint32_t sef_cpuid7_edx; // unused currently 306 307 // cpuid function 0xB (processor topology) 308 // ecx = 0 309 uint32_t tpl_cpuidB0_eax; 310 TplCpuidBEbx tpl_cpuidB0_ebx; 311 uint32_t tpl_cpuidB0_ecx; // unused currently 312 uint32_t tpl_cpuidB0_edx; // unused currently 313 314 // ecx = 1 315 uint32_t tpl_cpuidB1_eax; 316 TplCpuidBEbx tpl_cpuidB1_ebx; 317 uint32_t tpl_cpuidB1_ecx; // unused currently 318 uint32_t tpl_cpuidB1_edx; // unused currently 319 320 // ecx = 2 321 uint32_t tpl_cpuidB2_eax; 322 TplCpuidBEbx tpl_cpuidB2_ebx; 323 uint32_t tpl_cpuidB2_ecx; // unused currently 324 uint32_t tpl_cpuidB2_edx; // unused currently 325 326 // cpuid function 0x80000000 // example, unused 327 uint32_t ext_max_function; 328 uint32_t ext_vendor_name_0; 329 uint32_t ext_vendor_name_1; 330 uint32_t ext_vendor_name_2; 331 332 // cpuid function 0x80000001 333 uint32_t ext_cpuid1_eax; // reserved 334 uint32_t ext_cpuid1_ebx; // reserved 335 ExtCpuid1Ecx ext_cpuid1_ecx; 336 ExtCpuid1Edx ext_cpuid1_edx; 337 338 // cpuid functions 0x80000002 thru 0x80000004: example, unused 339 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 340 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 341 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 342 343 // cpuid function 0x80000005 // AMD L1, Intel reserved 344 uint32_t ext_cpuid5_eax; // unused currently 345 uint32_t ext_cpuid5_ebx; // reserved 346 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 347 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 348 349 // cpuid function 0x80000007 350 uint32_t ext_cpuid7_eax; // reserved 351 uint32_t ext_cpuid7_ebx; // reserved 352 uint32_t ext_cpuid7_ecx; // reserved 353 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 354 355 // cpuid function 0x80000008 356 uint32_t ext_cpuid8_eax; // unused currently 357 uint32_t ext_cpuid8_ebx; // reserved 358 ExtCpuid8Ecx ext_cpuid8_ecx; 359 uint32_t ext_cpuid8_edx; // reserved 360 361 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 362 XemXcr0Eax xem_xcr0_eax; 363 uint32_t xem_xcr0_edx; // reserved 364 }; 365 366 // The actual cpuid info block 367 static CpuidInfo _cpuid_info; 368 369 // Extractors and predicates 370 static uint32_t extended_cpu_family() { 371 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 372 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 373 return result; 374 } 375 376 static uint32_t extended_cpu_model() { 377 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 378 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 379 return result; 380 } 381 382 static uint32_t cpu_stepping() { 383 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 384 return result; 385 } 386 387 static uint logical_processor_count() { 388 uint result = threads_per_core(); 389 return result; 390 } 391 392 static uint32_t feature_flags() { 393 uint32_t result = 0; 394 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 395 result |= CPU_CX8; 396 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 397 result |= CPU_CMOV; 398 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 399 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 400 result |= CPU_FXSR; 401 // HT flag is set for multi-core processors also. 402 if (threads_per_core() > 1) 403 result |= CPU_HT; 404 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 405 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 406 result |= CPU_MMX; 407 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 408 result |= CPU_SSE; 409 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 410 result |= CPU_SSE2; 411 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 412 result |= CPU_SSE3; 413 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 414 result |= CPU_SSSE3; 415 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 416 result |= CPU_SSE4_1; 417 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 418 result |= CPU_SSE4_2; 419 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 420 result |= CPU_POPCNT; 421 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 422 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 423 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 424 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 425 result |= CPU_AVX; 426 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 427 result |= CPU_AVX2; 428 } 429 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 430 result |= CPU_BMI1; 431 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 432 result |= CPU_TSC; 433 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 434 result |= CPU_TSCINV; 435 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 436 result |= CPU_AES; 437 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 438 result |= CPU_ERMS; 439 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 440 result |= CPU_CLMUL; 441 442 // AMD features. 443 if (is_amd()) { 444 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 445 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 446 result |= CPU_3DNOW_PREFETCH; 447 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 448 result |= CPU_LZCNT; 449 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 450 result |= CPU_SSE4A; 451 } 452 // Intel features. 453 if(is_intel()) { 454 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 455 result |= CPU_BMI2; 456 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 457 result |= CPU_LZCNT; 458 } 459 460 return result; 461 } 462 463 static void get_processor_features(); 464 465 public: 466 // Offsets for cpuid asm stub 467 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 468 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 469 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 470 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 471 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 472 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 473 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 474 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 475 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 476 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 477 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 478 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 479 480 // Initialization 481 static void initialize(); 482 483 // Asserts 484 static void assert_is_initialized() { 485 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 486 } 487 488 // 489 // Processor family: 490 // 3 - 386 491 // 4 - 486 492 // 5 - Pentium 493 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 494 // Pentium M, Core Solo, Core Duo, Core2 Duo 495 // family 6 model: 9, 13, 14, 15 496 // 0x0f - Pentium 4, Opteron 497 // 498 // Note: The cpu family should be used to select between 499 // instruction sequences which are valid on all Intel 500 // processors. Use the feature test functions below to 501 // determine whether a particular instruction is supported. 502 // 503 static int cpu_family() { return _cpu;} 504 static bool is_P6() { return cpu_family() >= 6; } 505 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 506 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 507 508 static bool supports_processor_topology() { 509 return (_cpuid_info.std_max_function >= 0xB) && 510 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 511 // Some cpus have max cpuid >= 0xB but do not support processor topology. 512 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 513 } 514 515 static uint cores_per_cpu() { 516 uint result = 1; 517 if (is_intel()) { 518 if (supports_processor_topology()) { 519 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 520 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 521 } else { 522 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 523 } 524 } else if (is_amd()) { 525 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 526 } 527 return result; 528 } 529 530 static uint threads_per_core() { 531 uint result = 1; 532 if (is_intel() && supports_processor_topology()) { 533 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 534 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 535 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 536 cores_per_cpu(); 537 } 538 return result; 539 } 540 541 static intx prefetch_data_size() { 542 intx result = 0; 543 if (is_intel()) { 544 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 545 } else if (is_amd()) { 546 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 547 } 548 if (result < 32) // not defined ? 549 result = 32; // 32 bytes by default on x86 and other x64 550 return result; 551 } 552 553 // 554 // Feature identification 555 // 556 static bool supports_cpuid() { return _cpuFeatures != 0; } 557 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } 558 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } 559 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } 560 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } 561 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } 562 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } 563 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } 564 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } 565 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } 566 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } 567 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } 568 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } 569 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } 570 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } 571 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } 572 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } 573 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 574 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } 575 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } 576 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } 577 // Intel features 578 static bool is_intel_family_core() { return is_intel() && 579 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 580 581 static bool is_intel_tsc_synched_at_init() { 582 if (is_intel_family_core()) { 583 uint32_t ext_model = extended_cpu_model(); 584 if (ext_model == CPU_MODEL_NEHALEM_EP || 585 ext_model == CPU_MODEL_WESTMERE_EP || 586 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 587 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 588 // <= 2-socket invariant tsc support. EX versions are usually used 589 // in > 2-socket systems and likely don't synchronize tscs at 590 // initialization. 591 // Code that uses tsc values must be prepared for them to arbitrarily 592 // jump forward or backward. 593 return true; 594 } 595 } 596 return false; 597 } 598 599 // AMD features 600 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } 601 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 602 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } 603 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } 604 605 static bool is_amd_Barcelona() { return is_amd() && 606 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 607 608 // Intel and AMD newer cores support fast timestamps well 609 static bool supports_tscinv_bit() { 610 return (_cpuFeatures & CPU_TSCINV) != 0; 611 } 612 static bool supports_tscinv() { 613 return supports_tscinv_bit() && 614 ( (is_amd() && !is_amd_Barcelona()) || 615 is_intel_tsc_synched_at_init() ); 616 } 617 618 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 619 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 620 supports_sse3() && _model != 0x1C; } 621 622 static bool supports_compare_and_exchange() { return true; } 623 624 static const char* cpu_features() { return _features_str; } 625 626 static intx allocate_prefetch_distance() { 627 // This method should be called before allocate_prefetch_style(). 628 // 629 // Hardware prefetching (distance/size in bytes): 630 // Pentium 3 - 64 / 32 631 // Pentium 4 - 256 / 128 632 // Athlon - 64 / 32 ???? 633 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 634 // Core - 128 / 64 635 // 636 // Software prefetching (distance in bytes / instruction with best score): 637 // Pentium 3 - 128 / prefetchnta 638 // Pentium 4 - 512 / prefetchnta 639 // Athlon - 128 / prefetchnta 640 // Opteron - 256 / prefetchnta 641 // Core - 256 / prefetchnta 642 // It will be used only when AllocatePrefetchStyle > 0 643 644 intx count = AllocatePrefetchDistance; 645 if (count < 0) { // default ? 646 if (is_amd()) { // AMD 647 if (supports_sse2()) 648 count = 256; // Opteron 649 else 650 count = 128; // Athlon 651 } else { // Intel 652 if (supports_sse2()) 653 if (cpu_family() == 6) { 654 count = 256; // Pentium M, Core, Core2 655 } else { 656 count = 512; // Pentium 4 657 } 658 else 659 count = 128; // Pentium 3 (and all other old CPUs) 660 } 661 } 662 return count; 663 } 664 static intx allocate_prefetch_style() { 665 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 666 // Return 0 if AllocatePrefetchDistance was not defined. 667 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 668 } 669 670 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from 671 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. 672 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. 673 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. 674 675 // gc copy/scan is disabled if prefetchw isn't supported, because 676 // Prefetch::write emits an inlined prefetchw on Linux. 677 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. 678 // The used prefetcht0 instruction works for both amd64 and em64t. 679 static intx prefetch_copy_interval_in_bytes() { 680 intx interval = PrefetchCopyIntervalInBytes; 681 return interval >= 0 ? interval : 576; 682 } 683 static intx prefetch_scan_interval_in_bytes() { 684 intx interval = PrefetchScanIntervalInBytes; 685 return interval >= 0 ? interval : 576; 686 } 687 static intx prefetch_fields_ahead() { 688 intx count = PrefetchFieldsAhead; 689 return count >= 0 ? count : 1; 690 } 691 }; 692 693 #endif // CPU_X86_VM_VM_VERSION_X86_HPP