1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
519
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
535
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
541
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
550
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
560
561
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
565
566 int framesize = C->frame_slots() << LogBytesPerInt;
567
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
569
570 C->set_frame_complete(cbuf.insts_size());
571
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
579
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
583
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
587
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
596
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
616
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
619
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
631
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
636
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
638
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
648
649 emit_opcode(cbuf, 0x58 | EBP_enc);
650
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
658
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
665
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
670
671 size++; // popl rbp,
672
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
680
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
684
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
688
689 int MachEpilogNode::safepoint_offset() const { return 0; }
690
691 //=============================================================================
692
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
695
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
698
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
708
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
728
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
768
769
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
806
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
821
822
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
837
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
850
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
865
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
877
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
880
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
884
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
887
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
982
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
996
997 // Generate spill code!
998 int size = 0;
999
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1002
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1044
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1070
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1074
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1093
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1098
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1126
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1134
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1141
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1146
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1151
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1168
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1188
1189 assert( size > 0, "missed a case" );
1190
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208
1209
1210 Unimplemented();
1211 }
1212
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1222
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1226
1227
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1253
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1263
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1269 st->print_cr("\tNOP");
1270 st->print_cr("\tNOP");
1271 if( !OptoBreakpoint )
1272 st->print_cr("\tNOP");
1273 }
1274 #endif
1275
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279 uint insts_size = cbuf.insts_size();
1280 #endif
1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282 masm.jump_cc(Assembler::notEqual,
1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284 /* WARNING these NOPs are critical so that verified entry point is properly
1285 aligned for patching by NativeJump::patch_verified_entry() */
1286 int nops_cnt = 2;
1287 if( !OptoBreakpoint ) // Leave space for int3
1288 nops_cnt += 1;
1289 masm.nop(nops_cnt);
1290
1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1293
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295 return OptoBreakpoint ? 11 : 12;
1296 }
1297
1298
1299 //=============================================================================
1300 uint size_exception_handler() {
1301 // NativeCall instruction size is the same as NativeJump.
1302 // exception handler starts out as jump and can be patched to
1303 // a call be deoptimization. (4932387)
1304 // Note that this value is also credited (in output.cpp) to
1305 // the size of the code section.
1306 return NativeJump::instruction_size;
1307 }
1308
1309 // Emit exception handler code. Stuff framesize into a register
1310 // and call a VM stub routine.
1311 int emit_exception_handler(CodeBuffer& cbuf) {
1312
1313 // Note that the code buffer's insts_mark is always relative to insts.
1314 // That's why we must use the macroassembler to generate a handler.
1315 MacroAssembler _masm(&cbuf);
1316 address base =
1317 __ start_a_stub(size_exception_handler());
1318 if (base == NULL) return 0; // CodeBuffer::expand failed
1319 int offset = __ offset();
1320 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1321 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1322 __ end_a_stub();
1323 return offset;
1324 }
1325
1326 uint size_deopt_handler() {
1327 // NativeCall instruction size is the same as NativeJump.
1328 // exception handler starts out as jump and can be patched to
1329 // a call be deoptimization. (4932387)
1330 // Note that this value is also credited (in output.cpp) to
1331 // the size of the code section.
1332 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1333 }
1334
1335 // Emit deopt handler code.
1336 int emit_deopt_handler(CodeBuffer& cbuf) {
1337
1338 // Note that the code buffer's insts_mark is always relative to insts.
1339 // That's why we must use the macroassembler to generate a handler.
1340 MacroAssembler _masm(&cbuf);
1341 address base =
1342 __ start_a_stub(size_exception_handler());
1343 if (base == NULL) return 0; // CodeBuffer::expand failed
1344 int offset = __ offset();
1345 InternalAddress here(__ pc());
1346 __ pushptr(here.addr());
1347
1348 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1349 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1350 __ end_a_stub();
1351 return offset;
1352 }
1353
1354 int Matcher::regnum_to_fpu_offset(int regnum) {
1355 return regnum - 32; // The FP registers are in the second chunk
1356 }
1357
1358 // This is UltraSparc specific, true just means we have fast l2f conversion
1359 const bool Matcher::convL2FSupported(void) {
1360 return true;
1361 }
1362
1363 // Is this branch offset short enough that a short branch can be used?
1364 //
1365 // NOTE: If the platform does not provide any short branch variants, then
1366 // this method should return false for offset 0.
1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1368 // The passed offset is relative to address of the branch.
1369 // On 86 a branch displacement is calculated relative to address
1370 // of a next instruction.
1371 offset -= br_size;
1372
1373 // the short version of jmpConUCF2 contains multiple branches,
1374 // making the reach slightly less
1375 if (rule == jmpConUCF2_rule)
1376 return (-126 <= offset && offset <= 125);
1377 return (-128 <= offset && offset <= 127);
1378 }
1379
1380 const bool Matcher::isSimpleConstant64(jlong value) {
1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1382 return false;
1383 }
1384
1385 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1386 const bool Matcher::init_array_count_is_in_bytes = false;
1387
1388 // Threshold size for cleararray.
1389 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1390
1391 // Needs 2 CMOV's for longs.
1392 const int Matcher::long_cmove_cost() { return 1; }
1393
1394 // No CMOVF/CMOVD with SSE/SSE2
1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1396
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1399
1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1401 // be subsumed into complex addressing expressions or compute them into
1402 // registers? True for Intel but false for most RISCs
1403 const bool Matcher::clone_shift_expressions = true;
1404
1405 // Do we need to mask the count passed to shift instructions or does
1406 // the cpu only look at the lower 5/6 bits anyway?
1407 const bool Matcher::need_masked_shift_count = false;
1408
1409 bool Matcher::narrow_oop_use_complex_address() {
1410 ShouldNotCallThis();
1411 return true;
1412 }
1413
1414 bool Matcher::narrow_klass_use_complex_address() {
1415 ShouldNotCallThis();
1416 return true;
1417 }
1418
1419
1420 // Is it better to copy float constants, or load them directly from memory?
1421 // Intel can load a float constant from a direct address, requiring no
1422 // extra registers. Most RISCs will have to materialize an address into a
1423 // register first, so they would do better to copy the constant from stack.
1424 const bool Matcher::rematerialize_float_constants = true;
1425
1426 // If CPU can load and store mis-aligned doubles directly then no fixup is
1427 // needed. Else we split the double into 2 integer pieces and move it
1428 // piece-by-piece. Only happens when passing doubles into C code as the
1429 // Java calling convention forces doubles to be aligned.
1430 const bool Matcher::misaligned_doubles_ok = true;
1431
1432
1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1434 // Get the memory operand from the node
1435 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1436 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1437 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1438 uint opcnt = 1; // First operand
1439 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1440 while( idx >= skipped+num_edges ) {
1441 skipped += num_edges;
1442 opcnt++; // Bump operand count
1443 assert( opcnt < numopnds, "Accessing non-existent operand" );
1444 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1445 }
1446
1447 MachOper *memory = node->_opnds[opcnt];
1448 MachOper *new_memory = NULL;
1449 switch (memory->opcode()) {
1450 case DIRECT:
1451 case INDOFFSET32X:
1452 // No transformation necessary.
1453 return;
1454 case INDIRECT:
1455 new_memory = new (C) indirect_win95_safeOper( );
1456 break;
1457 case INDOFFSET8:
1458 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1459 break;
1460 case INDOFFSET32:
1461 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1462 break;
1463 case INDINDEXOFFSET:
1464 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1465 break;
1466 case INDINDEXSCALE:
1467 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1468 break;
1469 case INDINDEXSCALEOFFSET:
1470 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1471 break;
1472 case LOAD_LONG_INDIRECT:
1473 case LOAD_LONG_INDOFFSET32:
1474 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1475 return;
1476 default:
1477 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1478 return;
1479 }
1480 node->_opnds[opcnt] = new_memory;
1481 }
1482
1483 // Advertise here if the CPU requires explicit rounding operations
1484 // to implement the UseStrictFP mode.
1485 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1486
1487 // Are floats conerted to double when stored to stack during deoptimization?
1488 // On x32 it is stored with convertion only when FPU is used for floats.
1489 bool Matcher::float_in_double() { return (UseSSE == 0); }
1490
1491 // Do ints take an entire long register or just half?
1492 const bool Matcher::int_in_long = false;
1493
1494 // Return whether or not this register is ever used as an argument. This
1495 // function is used on startup to build the trampoline stubs in generateOptoStub.
1496 // Registers not mentioned will be killed by the VM call in the trampoline, and
1497 // arguments in those registers not be available to the callee.
1498 bool Matcher::can_be_java_arg( int reg ) {
1499 if( reg == ECX_num || reg == EDX_num ) return true;
1500 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1501 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1502 return false;
1503 }
1504
1505 bool Matcher::is_spillable_arg( int reg ) {
1506 return can_be_java_arg(reg);
1507 }
1508
1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1510 // Use hardware integer DIV instruction when
1511 // it is faster than a code which use multiply.
1512 // Only when constant divisor fits into 32 bit
1513 // (min_jint is excluded to get only correct
1514 // positive 32 bit values from negative).
1515 return VM_Version::has_fast_idiv() &&
1516 (divisor == (int)divisor && divisor != min_jint);
1517 }
1518
1519 // Register for DIVI projection of divmodI
1520 RegMask Matcher::divI_proj_mask() {
1521 return EAX_REG_mask();
1522 }
1523
1524 // Register for MODI projection of divmodI
1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1528
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1534
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1540
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1544
1545 const RegMask Matcher::mathExactI_result_proj_mask() {
1546 return EAX_REG_mask();
1547 }
1548
1549 const RegMask Matcher::mathExactL_result_proj_mask() {
1550 ShouldNotReachHere();
1551 return RegMask();
1552 }
1553
1554 const RegMask Matcher::mathExactI_flags_proj_mask() {
1555 return INT_FLAGS_mask();
1556 }
1557
1558 // Returns true if the high 32 bits of the value is known to be zero.
1559 bool is_operand_hi32_zero(Node* n) {
1560 int opc = n->Opcode();
1561 if (opc == Op_AndL) {
1562 Node* o2 = n->in(2);
1563 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1564 return true;
1565 }
1566 }
1567 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1568 return true;
1569 }
1570 return false;
1571 }
1572
1573 %}
1574
1575 //----------ENCODING BLOCK-----------------------------------------------------
1576 // This block specifies the encoding classes used by the compiler to output
1577 // byte streams. Encoding classes generate functions which are called by
1578 // Machine Instruction Nodes in order to generate the bit encoding of the
1579 // instruction. Operands specify their base encoding interface with the
1580 // interface keyword. There are currently supported four interfaces,
1581 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1582 // operand to generate a function which returns its register number when
1583 // queried. CONST_INTER causes an operand to generate a function which
1584 // returns the value of the constant when queried. MEMORY_INTER causes an
1585 // operand to generate four functions which return the Base Register, the
1586 // Index Register, the Scale Value, and the Offset Value of the operand when
1587 // queried. COND_INTER causes an operand to generate six functions which
1588 // return the encoding code (ie - encoding bits for the instruction)
1589 // associated with each basic boolean condition for a conditional instruction.
1590 // Instructions specify two basic values for encoding. They use the
1591 // ins_encode keyword to specify their encoding class (which must be one of
1592 // the class names specified in the encoding block), and they use the
1593 // opcode keyword to specify, in order, their primary, secondary, and
1594 // tertiary opcode. Only the opcode sections which a particular instruction
1595 // needs for encoding need to be specified.
1596 encode %{
1597 // Build emit functions for each basic byte or larger field in the intel
1598 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1599 // code in the enc_class source block. Emit functions will live in the
1600 // main source block for now. In future, we can generalize this by
1601 // adding a syntax that specifies the sizes of fields in an order,
1602 // so that the adlc can build the emit functions automagically
1603
1604 // Emit primary opcode
1605 enc_class OpcP %{
1606 emit_opcode(cbuf, $primary);
1607 %}
1608
1609 // Emit secondary opcode
1610 enc_class OpcS %{
1611 emit_opcode(cbuf, $secondary);
1612 %}
1613
1614 // Emit opcode directly
1615 enc_class Opcode(immI d8) %{
1616 emit_opcode(cbuf, $d8$$constant);
1617 %}
1618
1619 enc_class SizePrefix %{
1620 emit_opcode(cbuf,0x66);
1621 %}
1622
1623 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1624 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1625 %}
1626
1627 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1628 emit_opcode(cbuf,$opcode$$constant);
1629 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1630 %}
1631
1632 enc_class mov_r32_imm0( rRegI dst ) %{
1633 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1634 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1635 %}
1636
1637 enc_class cdq_enc %{
1638 // Full implementation of Java idiv and irem; checks for
1639 // special case as described in JVM spec., p.243 & p.271.
1640 //
1641 // normal case special case
1642 //
1643 // input : rax,: dividend min_int
1644 // reg: divisor -1
1645 //
1646 // output: rax,: quotient (= rax, idiv reg) min_int
1647 // rdx: remainder (= rax, irem reg) 0
1648 //
1649 // Code sequnce:
1650 //
1651 // 81 F8 00 00 00 80 cmp rax,80000000h
1652 // 0F 85 0B 00 00 00 jne normal_case
1653 // 33 D2 xor rdx,edx
1654 // 83 F9 FF cmp rcx,0FFh
1655 // 0F 84 03 00 00 00 je done
1656 // normal_case:
1657 // 99 cdq
1658 // F7 F9 idiv rax,ecx
1659 // done:
1660 //
1661 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1662 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1664 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1665 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1667 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1668 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1669 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1670 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1671 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1672 // normal_case:
1673 emit_opcode(cbuf,0x99); // cdq
1674 // idiv (note: must be emitted by the user of this rule)
1675 // normal:
1676 %}
1677
1678 // Dense encoding for older common ops
1679 enc_class Opc_plus(immI opcode, rRegI reg) %{
1680 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1681 %}
1682
1683
1684 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1685 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1686 // Check for 8-bit immediate, and set sign extend bit in opcode
1687 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1688 emit_opcode(cbuf, $primary | 0x02);
1689 }
1690 else { // If 32-bit immediate
1691 emit_opcode(cbuf, $primary);
1692 }
1693 %}
1694
1695 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1696 // Emit primary opcode and set sign-extend bit
1697 // Check for 8-bit immediate, and set sign extend bit in opcode
1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1699 emit_opcode(cbuf, $primary | 0x02); }
1700 else { // If 32-bit immediate
1701 emit_opcode(cbuf, $primary);
1702 }
1703 // Emit r/m byte with secondary opcode, after primary opcode.
1704 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1705 %}
1706
1707 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1708 // Check for 8-bit immediate, and set sign extend bit in opcode
1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1710 $$$emit8$imm$$constant;
1711 }
1712 else { // If 32-bit immediate
1713 // Output immediate
1714 $$$emit32$imm$$constant;
1715 }
1716 %}
1717
1718 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1719 // Emit primary opcode and set sign-extend bit
1720 // Check for 8-bit immediate, and set sign extend bit in opcode
1721 int con = (int)$imm$$constant; // Throw away top bits
1722 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1723 // Emit r/m byte with secondary opcode, after primary opcode.
1724 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1725 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1726 else emit_d32(cbuf,con);
1727 %}
1728
1729 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1730 // Emit primary opcode and set sign-extend bit
1731 // Check for 8-bit immediate, and set sign extend bit in opcode
1732 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1734 // Emit r/m byte with tertiary opcode, after primary opcode.
1735 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1737 else emit_d32(cbuf,con);
1738 %}
1739
1740 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1741 emit_cc(cbuf, $secondary, $dst$$reg );
1742 %}
1743
1744 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1745 int destlo = $dst$$reg;
1746 int desthi = HIGH_FROM_LOW(destlo);
1747 // bswap lo
1748 emit_opcode(cbuf, 0x0F);
1749 emit_cc(cbuf, 0xC8, destlo);
1750 // bswap hi
1751 emit_opcode(cbuf, 0x0F);
1752 emit_cc(cbuf, 0xC8, desthi);
1753 // xchg lo and hi
1754 emit_opcode(cbuf, 0x87);
1755 emit_rm(cbuf, 0x3, destlo, desthi);
1756 %}
1757
1758 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1759 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1760 %}
1761
1762 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1763 $$$emit8$primary;
1764 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1765 %}
1766
1767 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1768 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1769 emit_d8(cbuf, op >> 8 );
1770 emit_d8(cbuf, op & 255);
1771 %}
1772
1773 // emulate a CMOV with a conditional branch around a MOV
1774 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1775 // Invert sense of branch from sense of CMOV
1776 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1777 emit_d8( cbuf, $brOffs$$constant );
1778 %}
1779
1780 enc_class enc_PartialSubtypeCheck( ) %{
1781 Register Redi = as_Register(EDI_enc); // result register
1782 Register Reax = as_Register(EAX_enc); // super class
1783 Register Recx = as_Register(ECX_enc); // killed
1784 Register Resi = as_Register(ESI_enc); // sub class
1785 Label miss;
1786
1787 MacroAssembler _masm(&cbuf);
1788 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1789 NULL, &miss,
1790 /*set_cond_codes:*/ true);
1791 if ($primary) {
1792 __ xorptr(Redi, Redi);
1793 }
1794 __ bind(miss);
1795 %}
1796
1797 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1798 MacroAssembler masm(&cbuf);
1799 int start = masm.offset();
1800 if (UseSSE >= 2) {
1801 if (VerifyFPU) {
1802 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1803 }
1804 } else {
1805 // External c_calling_convention expects the FPU stack to be 'clean'.
1806 // Compiled code leaves it dirty. Do cleanup now.
1807 masm.empty_FPU_stack();
1808 }
1809 if (sizeof_FFree_Float_Stack_All == -1) {
1810 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1811 } else {
1812 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1813 }
1814 %}
1815
1816 enc_class Verify_FPU_For_Leaf %{
1817 if( VerifyFPU ) {
1818 MacroAssembler masm(&cbuf);
1819 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1820 }
1821 %}
1822
1823 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1824 // This is the instruction starting address for relocation info.
1825 cbuf.set_insts_mark();
1826 $$$emit8$primary;
1827 // CALL directly to the runtime
1828 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1829 runtime_call_Relocation::spec(), RELOC_IMM32 );
1830
1831 if (UseSSE >= 2) {
1832 MacroAssembler _masm(&cbuf);
1833 BasicType rt = tf()->return_type();
1834
1835 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1836 // A C runtime call where the return value is unused. In SSE2+
1837 // mode the result needs to be removed from the FPU stack. It's
1838 // likely that this function call could be removed by the
1839 // optimizer if the C function is a pure function.
1840 __ ffree(0);
1841 } else if (rt == T_FLOAT) {
1842 __ lea(rsp, Address(rsp, -4));
1843 __ fstp_s(Address(rsp, 0));
1844 __ movflt(xmm0, Address(rsp, 0));
1845 __ lea(rsp, Address(rsp, 4));
1846 } else if (rt == T_DOUBLE) {
1847 __ lea(rsp, Address(rsp, -8));
1848 __ fstp_d(Address(rsp, 0));
1849 __ movdbl(xmm0, Address(rsp, 0));
1850 __ lea(rsp, Address(rsp, 8));
1851 }
1852 }
1853 %}
1854
1855
1856 enc_class pre_call_resets %{
1857 // If method sets FPU control word restore it here
1858 debug_only(int off0 = cbuf.insts_size());
1859 if (ra_->C->in_24_bit_fp_mode()) {
1860 MacroAssembler _masm(&cbuf);
1861 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1862 }
1863 if (ra_->C->max_vector_size() > 16) {
1864 // Clear upper bits of YMM registers when current compiled code uses
1865 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1866 MacroAssembler _masm(&cbuf);
1867 __ vzeroupper();
1868 }
1869 debug_only(int off1 = cbuf.insts_size());
1870 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1871 %}
1872
1873 enc_class post_call_FPU %{
1874 // If method sets FPU control word do it here also
1875 if (Compile::current()->in_24_bit_fp_mode()) {
1876 MacroAssembler masm(&cbuf);
1877 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1878 }
1879 %}
1880
1881 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1882 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1883 // who we intended to call.
1884 cbuf.set_insts_mark();
1885 $$$emit8$primary;
1886 if (!_method) {
1887 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1888 runtime_call_Relocation::spec(), RELOC_IMM32 );
1889 } else if (_optimized_virtual) {
1890 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1891 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1892 } else {
1893 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1894 static_call_Relocation::spec(), RELOC_IMM32 );
1895 }
1896 if (_method) { // Emit stub for static call.
1897 CompiledStaticCall::emit_to_interp_stub(cbuf);
1898 }
1899 %}
1900
1901 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1902 MacroAssembler _masm(&cbuf);
1903 __ ic_call((address)$meth$$method);
1904 %}
1905
1906 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1907 int disp = in_bytes(Method::from_compiled_offset());
1908 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1909
1910 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1911 cbuf.set_insts_mark();
1912 $$$emit8$primary;
1913 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1914 emit_d8(cbuf, disp); // Displacement
1915
1916 %}
1917
1918 // Following encoding is no longer used, but may be restored if calling
1919 // convention changes significantly.
1920 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1921 //
1922 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1923 // // int ic_reg = Matcher::inline_cache_reg();
1924 // // int ic_encode = Matcher::_regEncode[ic_reg];
1925 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1926 // // int imo_encode = Matcher::_regEncode[imo_reg];
1927 //
1928 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1929 // // // so we load it immediately before the call
1930 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1931 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1932 //
1933 // // xor rbp,ebp
1934 // emit_opcode(cbuf, 0x33);
1935 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1936 //
1937 // // CALL to interpreter.
1938 // cbuf.set_insts_mark();
1939 // $$$emit8$primary;
1940 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1941 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1942 // %}
1943
1944 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1945 $$$emit8$primary;
1946 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1947 $$$emit8$shift$$constant;
1948 %}
1949
1950 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1951 // Load immediate does not have a zero or sign extended version
1952 // for 8-bit immediates
1953 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1954 $$$emit32$src$$constant;
1955 %}
1956
1957 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1958 // Load immediate does not have a zero or sign extended version
1959 // for 8-bit immediates
1960 emit_opcode(cbuf, $primary + $dst$$reg);
1961 $$$emit32$src$$constant;
1962 %}
1963
1964 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1965 // Load immediate does not have a zero or sign extended version
1966 // for 8-bit immediates
1967 int dst_enc = $dst$$reg;
1968 int src_con = $src$$constant & 0x0FFFFFFFFL;
1969 if (src_con == 0) {
1970 // xor dst, dst
1971 emit_opcode(cbuf, 0x33);
1972 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1973 } else {
1974 emit_opcode(cbuf, $primary + dst_enc);
1975 emit_d32(cbuf, src_con);
1976 }
1977 %}
1978
1979 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1980 // Load immediate does not have a zero or sign extended version
1981 // for 8-bit immediates
1982 int dst_enc = $dst$$reg + 2;
1983 int src_con = ((julong)($src$$constant)) >> 32;
1984 if (src_con == 0) {
1985 // xor dst, dst
1986 emit_opcode(cbuf, 0x33);
1987 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1988 } else {
1989 emit_opcode(cbuf, $primary + dst_enc);
1990 emit_d32(cbuf, src_con);
1991 }
1992 %}
1993
1994
1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
1996 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1997 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1998 %}
1999
2000 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2001 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2002 %}
2003
2004 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2005 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2006 %}
2007
2008 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2009 $$$emit8$primary;
2010 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2011 %}
2012
2013 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2014 $$$emit8$secondary;
2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016 %}
2017
2018 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2019 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2020 %}
2021
2022 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2023 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2024 %}
2025
2026 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2027 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2028 %}
2029
2030 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2031 // Output immediate
2032 $$$emit32$src$$constant;
2033 %}
2034
2035 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2036 // Output Float immediate bits
2037 jfloat jf = $src$$constant;
2038 int jf_as_bits = jint_cast( jf );
2039 emit_d32(cbuf, jf_as_bits);
2040 %}
2041
2042 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2043 // Output Float immediate bits
2044 jfloat jf = $src$$constant;
2045 int jf_as_bits = jint_cast( jf );
2046 emit_d32(cbuf, jf_as_bits);
2047 %}
2048
2049 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2050 // Output immediate
2051 $$$emit16$src$$constant;
2052 %}
2053
2054 enc_class Con_d32(immI src) %{
2055 emit_d32(cbuf,$src$$constant);
2056 %}
2057
2058 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2059 // Output immediate memory reference
2060 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2061 emit_d32(cbuf, 0x00);
2062 %}
2063
2064 enc_class lock_prefix( ) %{
2065 if( os::is_MP() )
2066 emit_opcode(cbuf,0xF0); // [Lock]
2067 %}
2068
2069 // Cmp-xchg long value.
2070 // Note: we need to swap rbx, and rcx before and after the
2071 // cmpxchg8 instruction because the instruction uses
2072 // rcx as the high order word of the new value to store but
2073 // our register encoding uses rbx,.
2074 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2075
2076 // XCHG rbx,ecx
2077 emit_opcode(cbuf,0x87);
2078 emit_opcode(cbuf,0xD9);
2079 // [Lock]
2080 if( os::is_MP() )
2081 emit_opcode(cbuf,0xF0);
2082 // CMPXCHG8 [Eptr]
2083 emit_opcode(cbuf,0x0F);
2084 emit_opcode(cbuf,0xC7);
2085 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2086 // XCHG rbx,ecx
2087 emit_opcode(cbuf,0x87);
2088 emit_opcode(cbuf,0xD9);
2089 %}
2090
2091 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2092 // [Lock]
2093 if( os::is_MP() )
2094 emit_opcode(cbuf,0xF0);
2095
2096 // CMPXCHG [Eptr]
2097 emit_opcode(cbuf,0x0F);
2098 emit_opcode(cbuf,0xB1);
2099 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2100 %}
2101
2102 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2103 int res_encoding = $res$$reg;
2104
2105 // MOV res,0
2106 emit_opcode( cbuf, 0xB8 + res_encoding);
2107 emit_d32( cbuf, 0 );
2108 // JNE,s fail
2109 emit_opcode(cbuf,0x75);
2110 emit_d8(cbuf, 5 );
2111 // MOV res,1
2112 emit_opcode( cbuf, 0xB8 + res_encoding);
2113 emit_d32( cbuf, 1 );
2114 // fail:
2115 %}
2116
2117 enc_class set_instruction_start( ) %{
2118 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2119 %}
2120
2121 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2122 int reg_encoding = $ereg$$reg;
2123 int base = $mem$$base;
2124 int index = $mem$$index;
2125 int scale = $mem$$scale;
2126 int displace = $mem$$disp;
2127 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2128 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2129 %}
2130
2131 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2132 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2133 int base = $mem$$base;
2134 int index = $mem$$index;
2135 int scale = $mem$$scale;
2136 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2137 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2138 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2139 %}
2140
2141 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2142 int r1, r2;
2143 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2144 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,$tertiary);
2147 emit_rm(cbuf, 0x3, r1, r2);
2148 emit_d8(cbuf,$cnt$$constant);
2149 emit_d8(cbuf,$primary);
2150 emit_rm(cbuf, 0x3, $secondary, r1);
2151 emit_d8(cbuf,$cnt$$constant);
2152 %}
2153
2154 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2155 emit_opcode( cbuf, 0x8B ); // Move
2156 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2157 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2158 emit_d8(cbuf,$primary);
2159 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2160 emit_d8(cbuf,$cnt$$constant-32);
2161 }
2162 emit_d8(cbuf,$primary);
2163 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2164 emit_d8(cbuf,31);
2165 %}
2166
2167 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2168 int r1, r2;
2169 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2170 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2171
2172 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2173 emit_rm(cbuf, 0x3, r1, r2);
2174 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2175 emit_opcode(cbuf,$primary);
2176 emit_rm(cbuf, 0x3, $secondary, r1);
2177 emit_d8(cbuf,$cnt$$constant-32);
2178 }
2179 emit_opcode(cbuf,0x33); // XOR r2,r2
2180 emit_rm(cbuf, 0x3, r2, r2);
2181 %}
2182
2183 // Clone of RegMem but accepts an extra parameter to access each
2184 // half of a double in memory; it never needs relocation info.
2185 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2186 emit_opcode(cbuf,$opcode$$constant);
2187 int reg_encoding = $rm_reg$$reg;
2188 int base = $mem$$base;
2189 int index = $mem$$index;
2190 int scale = $mem$$scale;
2191 int displace = $mem$$disp + $disp_for_half$$constant;
2192 relocInfo::relocType disp_reloc = relocInfo::none;
2193 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2194 %}
2195
2196 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2197 //
2198 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2199 // and it never needs relocation information.
2200 // Frequently used to move data between FPU's Stack Top and memory.
2201 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2202 int rm_byte_opcode = $rm_opcode$$constant;
2203 int base = $mem$$base;
2204 int index = $mem$$index;
2205 int scale = $mem$$scale;
2206 int displace = $mem$$disp;
2207 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2208 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2209 %}
2210
2211 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2212 int rm_byte_opcode = $rm_opcode$$constant;
2213 int base = $mem$$base;
2214 int index = $mem$$index;
2215 int scale = $mem$$scale;
2216 int displace = $mem$$disp;
2217 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2218 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2219 %}
2220
2221 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2222 int reg_encoding = $dst$$reg;
2223 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2224 int index = 0x04; // 0x04 indicates no index
2225 int scale = 0x00; // 0x00 indicates no scale
2226 int displace = $src1$$constant; // 0x00 indicates no displacement
2227 relocInfo::relocType disp_reloc = relocInfo::none;
2228 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2229 %}
2230
2231 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2232 // Compare dst,src
2233 emit_opcode(cbuf,0x3B);
2234 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2235 // jmp dst < src around move
2236 emit_opcode(cbuf,0x7C);
2237 emit_d8(cbuf,2);
2238 // move dst,src
2239 emit_opcode(cbuf,0x8B);
2240 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2241 %}
2242
2243 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2244 // Compare dst,src
2245 emit_opcode(cbuf,0x3B);
2246 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2247 // jmp dst > src around move
2248 emit_opcode(cbuf,0x7F);
2249 emit_d8(cbuf,2);
2250 // move dst,src
2251 emit_opcode(cbuf,0x8B);
2252 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2253 %}
2254
2255 enc_class enc_FPR_store(memory mem, regDPR src) %{
2256 // If src is FPR1, we can just FST to store it.
2257 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2258 int reg_encoding = 0x2; // Just store
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2264 if( $src$$reg != FPR1L_enc ) {
2265 reg_encoding = 0x3; // Store & pop
2266 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2267 emit_d8( cbuf, 0xC0-1+$src$$reg );
2268 }
2269 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2270 emit_opcode(cbuf,$primary);
2271 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2272 %}
2273
2274 enc_class neg_reg(rRegI dst) %{
2275 // NEG $dst
2276 emit_opcode(cbuf,0xF7);
2277 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2278 %}
2279
2280 enc_class setLT_reg(eCXRegI dst) %{
2281 // SETLT $dst
2282 emit_opcode(cbuf,0x0F);
2283 emit_opcode(cbuf,0x9C);
2284 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2285 %}
2286
2287 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2288 int tmpReg = $tmp$$reg;
2289
2290 // SUB $p,$q
2291 emit_opcode(cbuf,0x2B);
2292 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2293 // SBB $tmp,$tmp
2294 emit_opcode(cbuf,0x1B);
2295 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2296 // AND $tmp,$y
2297 emit_opcode(cbuf,0x23);
2298 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2299 // ADD $p,$tmp
2300 emit_opcode(cbuf,0x03);
2301 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2302 %}
2303
2304 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2305 // TEST shift,32
2306 emit_opcode(cbuf,0xF7);
2307 emit_rm(cbuf, 0x3, 0, ECX_enc);
2308 emit_d32(cbuf,0x20);
2309 // JEQ,s small
2310 emit_opcode(cbuf, 0x74);
2311 emit_d8(cbuf, 0x04);
2312 // MOV $dst.hi,$dst.lo
2313 emit_opcode( cbuf, 0x8B );
2314 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2315 // CLR $dst.lo
2316 emit_opcode(cbuf, 0x33);
2317 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2318 // small:
2319 // SHLD $dst.hi,$dst.lo,$shift
2320 emit_opcode(cbuf,0x0F);
2321 emit_opcode(cbuf,0xA5);
2322 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2323 // SHL $dst.lo,$shift"
2324 emit_opcode(cbuf,0xD3);
2325 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2326 %}
2327
2328 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2329 // TEST shift,32
2330 emit_opcode(cbuf,0xF7);
2331 emit_rm(cbuf, 0x3, 0, ECX_enc);
2332 emit_d32(cbuf,0x20);
2333 // JEQ,s small
2334 emit_opcode(cbuf, 0x74);
2335 emit_d8(cbuf, 0x04);
2336 // MOV $dst.lo,$dst.hi
2337 emit_opcode( cbuf, 0x8B );
2338 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2339 // CLR $dst.hi
2340 emit_opcode(cbuf, 0x33);
2341 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2342 // small:
2343 // SHRD $dst.lo,$dst.hi,$shift
2344 emit_opcode(cbuf,0x0F);
2345 emit_opcode(cbuf,0xAD);
2346 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2347 // SHR $dst.hi,$shift"
2348 emit_opcode(cbuf,0xD3);
2349 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2350 %}
2351
2352 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2353 // TEST shift,32
2354 emit_opcode(cbuf,0xF7);
2355 emit_rm(cbuf, 0x3, 0, ECX_enc);
2356 emit_d32(cbuf,0x20);
2357 // JEQ,s small
2358 emit_opcode(cbuf, 0x74);
2359 emit_d8(cbuf, 0x05);
2360 // MOV $dst.lo,$dst.hi
2361 emit_opcode( cbuf, 0x8B );
2362 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2363 // SAR $dst.hi,31
2364 emit_opcode(cbuf, 0xC1);
2365 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2366 emit_d8(cbuf, 0x1F );
2367 // small:
2368 // SHRD $dst.lo,$dst.hi,$shift
2369 emit_opcode(cbuf,0x0F);
2370 emit_opcode(cbuf,0xAD);
2371 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2372 // SAR $dst.hi,$shift"
2373 emit_opcode(cbuf,0xD3);
2374 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2375 %}
2376
2377
2378 // ----------------- Encodings for floating point unit -----------------
2379 // May leave result in FPU-TOS or FPU reg depending on opcodes
2380 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2381 $$$emit8$primary;
2382 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2383 %}
2384
2385 // Pop argument in FPR0 with FSTP ST(0)
2386 enc_class PopFPU() %{
2387 emit_opcode( cbuf, 0xDD );
2388 emit_d8( cbuf, 0xD8 );
2389 %}
2390
2391 // !!!!! equivalent to Pop_Reg_F
2392 enc_class Pop_Reg_DPR( regDPR dst ) %{
2393 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2394 emit_d8( cbuf, 0xD8+$dst$$reg );
2395 %}
2396
2397 enc_class Push_Reg_DPR( regDPR dst ) %{
2398 emit_opcode( cbuf, 0xD9 );
2399 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2400 %}
2401
2402 enc_class strictfp_bias1( regDPR dst ) %{
2403 emit_opcode( cbuf, 0xDB ); // FLD m80real
2404 emit_opcode( cbuf, 0x2D );
2405 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2406 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2407 emit_opcode( cbuf, 0xC8+$dst$$reg );
2408 %}
2409
2410 enc_class strictfp_bias2( regDPR dst ) %{
2411 emit_opcode( cbuf, 0xDB ); // FLD m80real
2412 emit_opcode( cbuf, 0x2D );
2413 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2414 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2415 emit_opcode( cbuf, 0xC8+$dst$$reg );
2416 %}
2417
2418 // Special case for moving an integer register to a stack slot.
2419 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2420 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2421 %}
2422
2423 // Special case for moving a register to a stack slot.
2424 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2425 // Opcode already emitted
2426 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2427 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2428 emit_d32(cbuf, $dst$$disp); // Displacement
2429 %}
2430
2431 // Push the integer in stackSlot 'src' onto FP-stack
2432 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2433 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2434 %}
2435
2436 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2437 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2438 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2439 %}
2440
2441 // Same as Pop_Mem_F except for opcode
2442 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2443 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2444 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2445 %}
2446
2447 enc_class Pop_Reg_FPR( regFPR dst ) %{
2448 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2449 emit_d8( cbuf, 0xD8+$dst$$reg );
2450 %}
2451
2452 enc_class Push_Reg_FPR( regFPR dst ) %{
2453 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2454 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2455 %}
2456
2457 // Push FPU's float to a stack-slot, and pop FPU-stack
2458 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2459 int pop = 0x02;
2460 if ($src$$reg != FPR1L_enc) {
2461 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2462 emit_d8( cbuf, 0xC0-1+$src$$reg );
2463 pop = 0x03;
2464 }
2465 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2466 %}
2467
2468 // Push FPU's double to a stack-slot, and pop FPU-stack
2469 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2470 int pop = 0x02;
2471 if ($src$$reg != FPR1L_enc) {
2472 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2473 emit_d8( cbuf, 0xC0-1+$src$$reg );
2474 pop = 0x03;
2475 }
2476 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2477 %}
2478
2479 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2480 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2481 int pop = 0xD0 - 1; // -1 since we skip FLD
2482 if ($src$$reg != FPR1L_enc) {
2483 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2484 emit_d8( cbuf, 0xC0-1+$src$$reg );
2485 pop = 0xD8;
2486 }
2487 emit_opcode( cbuf, 0xDD );
2488 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2489 %}
2490
2491
2492 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2493 // load dst in FPR0
2494 emit_opcode( cbuf, 0xD9 );
2495 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2496 if ($src$$reg != FPR1L_enc) {
2497 // fincstp
2498 emit_opcode (cbuf, 0xD9);
2499 emit_opcode (cbuf, 0xF7);
2500 // swap src with FPR1:
2501 // FXCH FPR1 with src
2502 emit_opcode(cbuf, 0xD9);
2503 emit_d8(cbuf, 0xC8-1+$src$$reg );
2504 // fdecstp
2505 emit_opcode (cbuf, 0xD9);
2506 emit_opcode (cbuf, 0xF6);
2507 }
2508 %}
2509
2510 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2511 MacroAssembler _masm(&cbuf);
2512 __ subptr(rsp, 8);
2513 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2514 __ fld_d(Address(rsp, 0));
2515 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2516 __ fld_d(Address(rsp, 0));
2517 %}
2518
2519 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2520 MacroAssembler _masm(&cbuf);
2521 __ subptr(rsp, 4);
2522 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2523 __ fld_s(Address(rsp, 0));
2524 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2525 __ fld_s(Address(rsp, 0));
2526 %}
2527
2528 enc_class Push_ResultD(regD dst) %{
2529 MacroAssembler _masm(&cbuf);
2530 __ fstp_d(Address(rsp, 0));
2531 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2532 __ addptr(rsp, 8);
2533 %}
2534
2535 enc_class Push_ResultF(regF dst, immI d8) %{
2536 MacroAssembler _masm(&cbuf);
2537 __ fstp_s(Address(rsp, 0));
2538 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2539 __ addptr(rsp, $d8$$constant);
2540 %}
2541
2542 enc_class Push_SrcD(regD src) %{
2543 MacroAssembler _masm(&cbuf);
2544 __ subptr(rsp, 8);
2545 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2546 __ fld_d(Address(rsp, 0));
2547 %}
2548
2549 enc_class push_stack_temp_qword() %{
2550 MacroAssembler _masm(&cbuf);
2551 __ subptr(rsp, 8);
2552 %}
2553
2554 enc_class pop_stack_temp_qword() %{
2555 MacroAssembler _masm(&cbuf);
2556 __ addptr(rsp, 8);
2557 %}
2558
2559 enc_class push_xmm_to_fpr1(regD src) %{
2560 MacroAssembler _masm(&cbuf);
2561 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2562 __ fld_d(Address(rsp, 0));
2563 %}
2564
2565 enc_class Push_Result_Mod_DPR( regDPR src) %{
2566 if ($src$$reg != FPR1L_enc) {
2567 // fincstp
2568 emit_opcode (cbuf, 0xD9);
2569 emit_opcode (cbuf, 0xF7);
2570 // FXCH FPR1 with src
2571 emit_opcode(cbuf, 0xD9);
2572 emit_d8(cbuf, 0xC8-1+$src$$reg );
2573 // fdecstp
2574 emit_opcode (cbuf, 0xD9);
2575 emit_opcode (cbuf, 0xF6);
2576 }
2577 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2578 // // FSTP FPR$dst$$reg
2579 // emit_opcode( cbuf, 0xDD );
2580 // emit_d8( cbuf, 0xD8+$dst$$reg );
2581 %}
2582
2583 enc_class fnstsw_sahf_skip_parity() %{
2584 // fnstsw ax
2585 emit_opcode( cbuf, 0xDF );
2586 emit_opcode( cbuf, 0xE0 );
2587 // sahf
2588 emit_opcode( cbuf, 0x9E );
2589 // jnp ::skip
2590 emit_opcode( cbuf, 0x7B );
2591 emit_opcode( cbuf, 0x05 );
2592 %}
2593
2594 enc_class emitModDPR() %{
2595 // fprem must be iterative
2596 // :: loop
2597 // fprem
2598 emit_opcode( cbuf, 0xD9 );
2599 emit_opcode( cbuf, 0xF8 );
2600 // wait
2601 emit_opcode( cbuf, 0x9b );
2602 // fnstsw ax
2603 emit_opcode( cbuf, 0xDF );
2604 emit_opcode( cbuf, 0xE0 );
2605 // sahf
2606 emit_opcode( cbuf, 0x9E );
2607 // jp ::loop
2608 emit_opcode( cbuf, 0x0F );
2609 emit_opcode( cbuf, 0x8A );
2610 emit_opcode( cbuf, 0xF4 );
2611 emit_opcode( cbuf, 0xFF );
2612 emit_opcode( cbuf, 0xFF );
2613 emit_opcode( cbuf, 0xFF );
2614 %}
2615
2616 enc_class fpu_flags() %{
2617 // fnstsw_ax
2618 emit_opcode( cbuf, 0xDF);
2619 emit_opcode( cbuf, 0xE0);
2620 // test ax,0x0400
2621 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2622 emit_opcode( cbuf, 0xA9 );
2623 emit_d16 ( cbuf, 0x0400 );
2624 // // // This sequence works, but stalls for 12-16 cycles on PPro
2625 // // test rax,0x0400
2626 // emit_opcode( cbuf, 0xA9 );
2627 // emit_d32 ( cbuf, 0x00000400 );
2628 //
2629 // jz exit (no unordered comparison)
2630 emit_opcode( cbuf, 0x74 );
2631 emit_d8 ( cbuf, 0x02 );
2632 // mov ah,1 - treat as LT case (set carry flag)
2633 emit_opcode( cbuf, 0xB4 );
2634 emit_d8 ( cbuf, 0x01 );
2635 // sahf
2636 emit_opcode( cbuf, 0x9E);
2637 %}
2638
2639 enc_class cmpF_P6_fixup() %{
2640 // Fixup the integer flags in case comparison involved a NaN
2641 //
2642 // JNP exit (no unordered comparison, P-flag is set by NaN)
2643 emit_opcode( cbuf, 0x7B );
2644 emit_d8 ( cbuf, 0x03 );
2645 // MOV AH,1 - treat as LT case (set carry flag)
2646 emit_opcode( cbuf, 0xB4 );
2647 emit_d8 ( cbuf, 0x01 );
2648 // SAHF
2649 emit_opcode( cbuf, 0x9E);
2650 // NOP // target for branch to avoid branch to branch
2651 emit_opcode( cbuf, 0x90);
2652 %}
2653
2654 // fnstsw_ax();
2655 // sahf();
2656 // movl(dst, nan_result);
2657 // jcc(Assembler::parity, exit);
2658 // movl(dst, less_result);
2659 // jcc(Assembler::below, exit);
2660 // movl(dst, equal_result);
2661 // jcc(Assembler::equal, exit);
2662 // movl(dst, greater_result);
2663
2664 // less_result = 1;
2665 // greater_result = -1;
2666 // equal_result = 0;
2667 // nan_result = -1;
2668
2669 enc_class CmpF_Result(rRegI dst) %{
2670 // fnstsw_ax();
2671 emit_opcode( cbuf, 0xDF);
2672 emit_opcode( cbuf, 0xE0);
2673 // sahf
2674 emit_opcode( cbuf, 0x9E);
2675 // movl(dst, nan_result);
2676 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2677 emit_d32( cbuf, -1 );
2678 // jcc(Assembler::parity, exit);
2679 emit_opcode( cbuf, 0x7A );
2680 emit_d8 ( cbuf, 0x13 );
2681 // movl(dst, less_result);
2682 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2683 emit_d32( cbuf, -1 );
2684 // jcc(Assembler::below, exit);
2685 emit_opcode( cbuf, 0x72 );
2686 emit_d8 ( cbuf, 0x0C );
2687 // movl(dst, equal_result);
2688 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2689 emit_d32( cbuf, 0 );
2690 // jcc(Assembler::equal, exit);
2691 emit_opcode( cbuf, 0x74 );
2692 emit_d8 ( cbuf, 0x05 );
2693 // movl(dst, greater_result);
2694 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2695 emit_d32( cbuf, 1 );
2696 %}
2697
2698
2699 // Compare the longs and set flags
2700 // BROKEN! Do Not use as-is
2701 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2702 // CMP $src1.hi,$src2.hi
2703 emit_opcode( cbuf, 0x3B );
2704 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2705 // JNE,s done
2706 emit_opcode(cbuf,0x75);
2707 emit_d8(cbuf, 2 );
2708 // CMP $src1.lo,$src2.lo
2709 emit_opcode( cbuf, 0x3B );
2710 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2711 // done:
2712 %}
2713
2714 enc_class convert_int_long( regL dst, rRegI src ) %{
2715 // mov $dst.lo,$src
2716 int dst_encoding = $dst$$reg;
2717 int src_encoding = $src$$reg;
2718 encode_Copy( cbuf, dst_encoding , src_encoding );
2719 // mov $dst.hi,$src
2720 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2721 // sar $dst.hi,31
2722 emit_opcode( cbuf, 0xC1 );
2723 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2724 emit_d8(cbuf, 0x1F );
2725 %}
2726
2727 enc_class convert_long_double( eRegL src ) %{
2728 // push $src.hi
2729 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2730 // push $src.lo
2731 emit_opcode(cbuf, 0x50+$src$$reg );
2732 // fild 64-bits at [SP]
2733 emit_opcode(cbuf,0xdf);
2734 emit_d8(cbuf, 0x6C);
2735 emit_d8(cbuf, 0x24);
2736 emit_d8(cbuf, 0x00);
2737 // pop stack
2738 emit_opcode(cbuf, 0x83); // add SP, #8
2739 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2740 emit_d8(cbuf, 0x8);
2741 %}
2742
2743 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2744 // IMUL EDX:EAX,$src1
2745 emit_opcode( cbuf, 0xF7 );
2746 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2747 // SAR EDX,$cnt-32
2748 int shift_count = ((int)$cnt$$constant) - 32;
2749 if (shift_count > 0) {
2750 emit_opcode(cbuf, 0xC1);
2751 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2752 emit_d8(cbuf, shift_count);
2753 }
2754 %}
2755
2756 // this version doesn't have add sp, 8
2757 enc_class convert_long_double2( eRegL src ) %{
2758 // push $src.hi
2759 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2760 // push $src.lo
2761 emit_opcode(cbuf, 0x50+$src$$reg );
2762 // fild 64-bits at [SP]
2763 emit_opcode(cbuf,0xdf);
2764 emit_d8(cbuf, 0x6C);
2765 emit_d8(cbuf, 0x24);
2766 emit_d8(cbuf, 0x00);
2767 %}
2768
2769 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2770 // Basic idea: long = (long)int * (long)int
2771 // IMUL EDX:EAX, src
2772 emit_opcode( cbuf, 0xF7 );
2773 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2774 %}
2775
2776 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2777 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2778 // MUL EDX:EAX, src
2779 emit_opcode( cbuf, 0xF7 );
2780 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2781 %}
2782
2783 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2784 // Basic idea: lo(result) = lo(x_lo * y_lo)
2785 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2786 // MOV $tmp,$src.lo
2787 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2788 // IMUL $tmp,EDX
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0xAF );
2791 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2792 // MOV EDX,$src.hi
2793 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2794 // IMUL EDX,EAX
2795 emit_opcode( cbuf, 0x0F );
2796 emit_opcode( cbuf, 0xAF );
2797 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2798 // ADD $tmp,EDX
2799 emit_opcode( cbuf, 0x03 );
2800 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2801 // MUL EDX:EAX,$src.lo
2802 emit_opcode( cbuf, 0xF7 );
2803 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2804 // ADD EDX,ESI
2805 emit_opcode( cbuf, 0x03 );
2806 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2807 %}
2808
2809 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2810 // Basic idea: lo(result) = lo(src * y_lo)
2811 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2812 // IMUL $tmp,EDX,$src
2813 emit_opcode( cbuf, 0x6B );
2814 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2815 emit_d8( cbuf, (int)$src$$constant );
2816 // MOV EDX,$src
2817 emit_opcode(cbuf, 0xB8 + EDX_enc);
2818 emit_d32( cbuf, (int)$src$$constant );
2819 // MUL EDX:EAX,EDX
2820 emit_opcode( cbuf, 0xF7 );
2821 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2822 // ADD EDX,ESI
2823 emit_opcode( cbuf, 0x03 );
2824 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2825 %}
2826
2827 enc_class long_div( eRegL src1, eRegL src2 ) %{
2828 // PUSH src1.hi
2829 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2830 // PUSH src1.lo
2831 emit_opcode(cbuf, 0x50+$src1$$reg );
2832 // PUSH src2.hi
2833 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2834 // PUSH src2.lo
2835 emit_opcode(cbuf, 0x50+$src2$$reg );
2836 // CALL directly to the runtime
2837 cbuf.set_insts_mark();
2838 emit_opcode(cbuf,0xE8); // Call into runtime
2839 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2840 // Restore stack
2841 emit_opcode(cbuf, 0x83); // add SP, #framesize
2842 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2843 emit_d8(cbuf, 4*4);
2844 %}
2845
2846 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2847 // PUSH src1.hi
2848 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2849 // PUSH src1.lo
2850 emit_opcode(cbuf, 0x50+$src1$$reg );
2851 // PUSH src2.hi
2852 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2853 // PUSH src2.lo
2854 emit_opcode(cbuf, 0x50+$src2$$reg );
2855 // CALL directly to the runtime
2856 cbuf.set_insts_mark();
2857 emit_opcode(cbuf,0xE8); // Call into runtime
2858 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2859 // Restore stack
2860 emit_opcode(cbuf, 0x83); // add SP, #framesize
2861 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2862 emit_d8(cbuf, 4*4);
2863 %}
2864
2865 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2866 // MOV $tmp,$src.lo
2867 emit_opcode(cbuf, 0x8B);
2868 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2869 // OR $tmp,$src.hi
2870 emit_opcode(cbuf, 0x0B);
2871 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2872 %}
2873
2874 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2875 // CMP $src1.lo,$src2.lo
2876 emit_opcode( cbuf, 0x3B );
2877 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2878 // JNE,s skip
2879 emit_cc(cbuf, 0x70, 0x5);
2880 emit_d8(cbuf,2);
2881 // CMP $src1.hi,$src2.hi
2882 emit_opcode( cbuf, 0x3B );
2883 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2884 %}
2885
2886 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2887 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2888 emit_opcode( cbuf, 0x3B );
2889 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2890 // MOV $tmp,$src1.hi
2891 emit_opcode( cbuf, 0x8B );
2892 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2893 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2894 emit_opcode( cbuf, 0x1B );
2895 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2896 %}
2897
2898 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2899 // XOR $tmp,$tmp
2900 emit_opcode(cbuf,0x33); // XOR
2901 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2902 // CMP $tmp,$src.lo
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2905 // SBB $tmp,$src.hi
2906 emit_opcode( cbuf, 0x1B );
2907 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2908 %}
2909
2910 // Sniff, sniff... smells like Gnu Superoptimizer
2911 enc_class neg_long( eRegL dst ) %{
2912 emit_opcode(cbuf,0xF7); // NEG hi
2913 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2914 emit_opcode(cbuf,0xF7); // NEG lo
2915 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2916 emit_opcode(cbuf,0x83); // SBB hi,0
2917 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2918 emit_d8 (cbuf,0 );
2919 %}
2920
2921
2922 // Because the transitions from emitted code to the runtime
2923 // monitorenter/exit helper stubs are so slow it's critical that
2924 // we inline both the stack-locking fast-path and the inflated fast path.
2925 //
2926 // See also: cmpFastLock and cmpFastUnlock.
2927 //
2928 // What follows is a specialized inline transliteration of the code
2929 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2930 // another option would be to emit TrySlowEnter and TrySlowExit methods
2931 // at startup-time. These methods would accept arguments as
2932 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2933 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2934 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2935 // In practice, however, the # of lock sites is bounded and is usually small.
2936 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2937 // if the processor uses simple bimodal branch predictors keyed by EIP
2938 // Since the helper routines would be called from multiple synchronization
2939 // sites.
2940 //
2941 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2942 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2943 // to those specialized methods. That'd give us a mostly platform-independent
2944 // implementation that the JITs could optimize and inline at their pleasure.
2945 // Done correctly, the only time we'd need to cross to native could would be
2946 // to park() or unpark() threads. We'd also need a few more unsafe operators
2947 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2948 // (b) explicit barriers or fence operations.
2949 //
2950 // TODO:
2951 //
2952 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2953 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2954 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2955 // the lock operators would typically be faster than reifying Self.
2956 //
2957 // * Ideally I'd define the primitives as:
2958 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2959 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2960 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2961 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2962 // Furthermore the register assignments are overconstrained, possibly resulting in
2963 // sub-optimal code near the synchronization site.
2964 //
2965 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2966 // Alternately, use a better sp-proximity test.
2967 //
2968 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2969 // Either one is sufficient to uniquely identify a thread.
2970 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2971 //
2972 // * Intrinsify notify() and notifyAll() for the common cases where the
2973 // object is locked by the calling thread but the waitlist is empty.
2974 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2975 //
2976 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2977 // But beware of excessive branch density on AMD Opterons.
2978 //
2979 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2980 // or failure of the fast-path. If the fast-path fails then we pass
2981 // control to the slow-path, typically in C. In Fast_Lock and
2982 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2983 // will emit a conditional branch immediately after the node.
2984 // So we have branches to branches and lots of ICC.ZF games.
2985 // Instead, it might be better to have C2 pass a "FailureLabel"
2986 // into Fast_Lock and Fast_Unlock. In the case of success, control
2987 // will drop through the node. ICC.ZF is undefined at exit.
2988 // In the case of failure, the node will branch directly to the
2989 // FailureLabel
2990
2991
2992 // obj: object to lock
2993 // box: on-stack box address (displaced header location) - KILLED
2994 // rax,: tmp -- KILLED
2995 // scr: tmp -- KILLED
2996 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2997
2998 Register objReg = as_Register($obj$$reg);
2999 Register boxReg = as_Register($box$$reg);
3000 Register tmpReg = as_Register($tmp$$reg);
3001 Register scrReg = as_Register($scr$$reg);
3002
3003 // Ensure the register assignents are disjoint
3004 guarantee (objReg != boxReg, "") ;
3005 guarantee (objReg != tmpReg, "") ;
3006 guarantee (objReg != scrReg, "") ;
3007 guarantee (boxReg != tmpReg, "") ;
3008 guarantee (boxReg != scrReg, "") ;
3009 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3010
3011 MacroAssembler masm(&cbuf);
3012
3013 if (_counters != NULL) {
3014 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3015 }
3016 if (EmitSync & 1) {
3017 // set box->dhw = unused_mark (3)
3018 // Force all sync thru slow-path: slow_enter() and slow_exit()
3019 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3020 masm.cmpptr (rsp, (int32_t)0) ;
3021 } else
3022 if (EmitSync & 2) {
3023 Label DONE_LABEL ;
3024 if (UseBiasedLocking) {
3025 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3026 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3027 }
3028
3029 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3030 masm.orptr (tmpReg, 0x1);
3031 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3032 if (os::is_MP()) { masm.lock(); }
3033 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3034 masm.jcc(Assembler::equal, DONE_LABEL);
3035 // Recursive locking
3036 masm.subptr(tmpReg, rsp);
3037 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3038 masm.movptr(Address(boxReg, 0), tmpReg);
3039 masm.bind(DONE_LABEL) ;
3040 } else {
3041 // Possible cases that we'll encounter in fast_lock
3042 // ------------------------------------------------
3043 // * Inflated
3044 // -- unlocked
3045 // -- Locked
3046 // = by self
3047 // = by other
3048 // * biased
3049 // -- by Self
3050 // -- by other
3051 // * neutral
3052 // * stack-locked
3053 // -- by self
3054 // = sp-proximity test hits
3055 // = sp-proximity test generates false-negative
3056 // -- by other
3057 //
3058
3059 Label IsInflated, DONE_LABEL, PopDone ;
3060
3061 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3062 // order to reduce the number of conditional branches in the most common cases.
3063 // Beware -- there's a subtle invariant that fetch of the markword
3064 // at [FETCH], below, will never observe a biased encoding (*101b).
3065 // If this invariant is not held we risk exclusion (safety) failure.
3066 if (UseBiasedLocking && !UseOptoBiasInlining) {
3067 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3068 }
3069
3070 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3071 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3072 masm.jccb (Assembler::notZero, IsInflated) ;
3073
3074 // Attempt stack-locking ...
3075 masm.orptr (tmpReg, 0x1);
3076 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3077 if (os::is_MP()) { masm.lock(); }
3078 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3079 if (_counters != NULL) {
3080 masm.cond_inc32(Assembler::equal,
3081 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3082 }
3083 masm.jccb (Assembler::equal, DONE_LABEL);
3084
3085 // Recursive locking
3086 masm.subptr(tmpReg, rsp);
3087 masm.andptr(tmpReg, 0xFFFFF003 );
3088 masm.movptr(Address(boxReg, 0), tmpReg);
3089 if (_counters != NULL) {
3090 masm.cond_inc32(Assembler::equal,
3091 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3092 }
3093 masm.jmp (DONE_LABEL) ;
3094
3095 masm.bind (IsInflated) ;
3096
3097 // The object is inflated.
3098 //
3099 // TODO-FIXME: eliminate the ugly use of manifest constants:
3100 // Use markOopDesc::monitor_value instead of "2".
3101 // use markOop::unused_mark() instead of "3".
3102 // The tmpReg value is an objectMonitor reference ORed with
3103 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3104 // objectmonitor pointer by masking off the "2" bit or we can just
3105 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3106 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3107 //
3108 // I use the latter as it avoids AGI stalls.
3109 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3110 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3111 //
3112 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3113
3114 // boxReg refers to the on-stack BasicLock in the current frame.
3115 // We'd like to write:
3116 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3117 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3118 // additional latency as we have another ST in the store buffer that must drain.
3119
3120 if (EmitSync & 8192) {
3121 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3122 masm.get_thread (scrReg) ;
3123 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3124 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3125 if (os::is_MP()) { masm.lock(); }
3126 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3127 } else
3128 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3129 masm.movptr(scrReg, boxReg) ;
3130 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3131
3132 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3133 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3134 // prefetchw [eax + Offset(_owner)-2]
3135 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3136 }
3137
3138 if ((EmitSync & 64) == 0) {
3139 // Optimistic form: consider XORL tmpReg,tmpReg
3140 masm.movptr(tmpReg, NULL_WORD) ;
3141 } else {
3142 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3143 // Test-And-CAS instead of CAS
3144 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3145 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3146 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3147 }
3148
3149 // Appears unlocked - try to swing _owner from null to non-null.
3150 // Ideally, I'd manifest "Self" with get_thread and then attempt
3151 // to CAS the register containing Self into m->Owner.
3152 // But we don't have enough registers, so instead we can either try to CAS
3153 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3154 // we later store "Self" into m->Owner. Transiently storing a stack address
3155 // (rsp or the address of the box) into m->owner is harmless.
3156 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3157 if (os::is_MP()) { masm.lock(); }
3158 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3159 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3160 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3161 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3162 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3163 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3164
3165 // If the CAS fails we can either retry or pass control to the slow-path.
3166 // We use the latter tactic.
3167 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3168 // If the CAS was successful ...
3169 // Self has acquired the lock
3170 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3171 // Intentional fall-through into DONE_LABEL ...
3172 } else {
3173 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3174 masm.movptr(boxReg, tmpReg) ;
3175
3176 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3177 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3178 // prefetchw [eax + Offset(_owner)-2]
3179 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3180 }
3181
3182 if ((EmitSync & 64) == 0) {
3183 // Optimistic form
3184 masm.xorptr (tmpReg, tmpReg) ;
3185 } else {
3186 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3187 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3188 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3189 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3190 }
3191
3192 // Appears unlocked - try to swing _owner from null to non-null.
3193 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3194 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3195 masm.get_thread (scrReg) ;
3196 if (os::is_MP()) { masm.lock(); }
3197 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3198
3199 // If the CAS fails we can either retry or pass control to the slow-path.
3200 // We use the latter tactic.
3201 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3202 // If the CAS was successful ...
3203 // Self has acquired the lock
3204 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3205 // Intentional fall-through into DONE_LABEL ...
3206 }
3207
3208 // DONE_LABEL is a hot target - we'd really like to place it at the
3209 // start of cache line by padding with NOPs.
3210 // See the AMD and Intel software optimization manuals for the
3211 // most efficient "long" NOP encodings.
3212 // Unfortunately none of our alignment mechanisms suffice.
3213 masm.bind(DONE_LABEL);
3214
3215 // Avoid branch-to-branch on AMD processors
3216 // This appears to be superstition.
3217 if (EmitSync & 32) masm.nop() ;
3218
3219
3220 // At DONE_LABEL the icc ZFlag is set as follows ...
3221 // Fast_Unlock uses the same protocol.
3222 // ZFlag == 1 -> Success
3223 // ZFlag == 0 -> Failure - force control through the slow-path
3224 }
3225 %}
3226
3227 // obj: object to unlock
3228 // box: box address (displaced header location), killed. Must be EAX.
3229 // rbx,: killed tmp; cannot be obj nor box.
3230 //
3231 // Some commentary on balanced locking:
3232 //
3233 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3234 // Methods that don't have provably balanced locking are forced to run in the
3235 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3236 // The interpreter provides two properties:
3237 // I1: At return-time the interpreter automatically and quietly unlocks any
3238 // objects acquired the current activation (frame). Recall that the
3239 // interpreter maintains an on-stack list of locks currently held by
3240 // a frame.
3241 // I2: If a method attempts to unlock an object that is not held by the
3242 // the frame the interpreter throws IMSX.
3243 //
3244 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3245 // B() doesn't have provably balanced locking so it runs in the interpreter.
3246 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3247 // is still locked by A().
3248 //
3249 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3250 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3251 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3252 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3253
3254 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3255
3256 Register objReg = as_Register($obj$$reg);
3257 Register boxReg = as_Register($box$$reg);
3258 Register tmpReg = as_Register($tmp$$reg);
3259
3260 guarantee (objReg != boxReg, "") ;
3261 guarantee (objReg != tmpReg, "") ;
3262 guarantee (boxReg != tmpReg, "") ;
3263 guarantee (boxReg == as_Register(EAX_enc), "") ;
3264 MacroAssembler masm(&cbuf);
3265
3266 if (EmitSync & 4) {
3267 // Disable - inhibit all inlining. Force control through the slow-path
3268 masm.cmpptr (rsp, 0) ;
3269 } else
3270 if (EmitSync & 8) {
3271 Label DONE_LABEL ;
3272 if (UseBiasedLocking) {
3273 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3274 }
3275 // classic stack-locking code ...
3276 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3277 masm.testptr(tmpReg, tmpReg) ;
3278 masm.jcc (Assembler::zero, DONE_LABEL) ;
3279 if (os::is_MP()) { masm.lock(); }
3280 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3281 masm.bind(DONE_LABEL);
3282 } else {
3283 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3284
3285 // Critically, the biased locking test must have precedence over
3286 // and appear before the (box->dhw == 0) recursive stack-lock test.
3287 if (UseBiasedLocking && !UseOptoBiasInlining) {
3288 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3289 }
3290
3291 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3292 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3293 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3294
3295 masm.testptr(tmpReg, 0x02) ; // Inflated?
3296 masm.jccb (Assembler::zero, Stacked) ;
3297
3298 masm.bind (Inflated) ;
3299 // It's inflated.
3300 // Despite our balanced locking property we still check that m->_owner == Self
3301 // as java routines or native JNI code called by this thread might
3302 // have released the lock.
3303 // Refer to the comments in synchronizer.cpp for how we might encode extra
3304 // state in _succ so we can avoid fetching EntryList|cxq.
3305 //
3306 // I'd like to add more cases in fast_lock() and fast_unlock() --
3307 // such as recursive enter and exit -- but we have to be wary of
3308 // I$ bloat, T$ effects and BP$ effects.
3309 //
3310 // If there's no contention try a 1-0 exit. That is, exit without
3311 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3312 // we detect and recover from the race that the 1-0 exit admits.
3313 //
3314 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3315 // before it STs null into _owner, releasing the lock. Updates
3316 // to data protected by the critical section must be visible before
3317 // we drop the lock (and thus before any other thread could acquire
3318 // the lock and observe the fields protected by the lock).
3319 // IA32's memory-model is SPO, so STs are ordered with respect to
3320 // each other and there's no need for an explicit barrier (fence).
3321 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3322
3323 masm.get_thread (boxReg) ;
3324 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3325 // prefetchw [ebx + Offset(_owner)-2]
3326 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3327 }
3328
3329 // Note that we could employ various encoding schemes to reduce
3330 // the number of loads below (currently 4) to just 2 or 3.
3331 // Refer to the comments in synchronizer.cpp.
3332 // In practice the chain of fetches doesn't seem to impact performance, however.
3333 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3334 // Attempt to reduce branch density - AMD's branch predictor.
3335 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3336 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3337 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3338 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3339 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3340 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3341 masm.jmpb (DONE_LABEL) ;
3342 } else {
3343 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3344 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3345 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3346 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3347 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3348 masm.jccb (Assembler::notZero, CheckSucc) ;
3349 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3350 masm.jmpb (DONE_LABEL) ;
3351 }
3352
3353 // The Following code fragment (EmitSync & 65536) improves the performance of
3354 // contended applications and contended synchronization microbenchmarks.
3355 // Unfortunately the emission of the code - even though not executed - causes regressions
3356 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3357 // with an equal number of never-executed NOPs results in the same regression.
3358 // We leave it off by default.
3359
3360 if ((EmitSync & 65536) != 0) {
3361 Label LSuccess, LGoSlowPath ;
3362
3363 masm.bind (CheckSucc) ;
3364
3365 // Optional pre-test ... it's safe to elide this
3366 if ((EmitSync & 16) == 0) {
3367 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3368 masm.jccb (Assembler::zero, LGoSlowPath) ;
3369 }
3370
3371 // We have a classic Dekker-style idiom:
3372 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3373 // There are a number of ways to implement the barrier:
3374 // (1) lock:andl &m->_owner, 0
3375 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3376 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3377 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3378 // (2) If supported, an explicit MFENCE is appealing.
3379 // In older IA32 processors MFENCE is slower than lock:add or xchg
3380 // particularly if the write-buffer is full as might be the case if
3381 // if stores closely precede the fence or fence-equivalent instruction.
3382 // In more modern implementations MFENCE appears faster, however.
3383 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3384 // The $lines underlying the top-of-stack should be in M-state.
3385 // The locked add instruction is serializing, of course.
3386 // (4) Use xchg, which is serializing
3387 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3388 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3389 // The integer condition codes will tell us if succ was 0.
3390 // Since _succ and _owner should reside in the same $line and
3391 // we just stored into _owner, it's likely that the $line
3392 // remains in M-state for the lock:orl.
3393 //
3394 // We currently use (3), although it's likely that switching to (2)
3395 // is correct for the future.
3396
3397 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3398 if (os::is_MP()) {
3399 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3400 masm.mfence();
3401 } else {
3402 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3403 }
3404 }
3405 // Ratify _succ remains non-null
3406 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3407 masm.jccb (Assembler::notZero, LSuccess) ;
3408
3409 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3410 if (os::is_MP()) { masm.lock(); }
3411 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3412 masm.jccb (Assembler::notEqual, LSuccess) ;
3413 // Since we're low on registers we installed rsp as a placeholding in _owner.
3414 // Now install Self over rsp. This is safe as we're transitioning from
3415 // non-null to non=null
3416 masm.get_thread (boxReg) ;
3417 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3418 // Intentional fall-through into LGoSlowPath ...
3419
3420 masm.bind (LGoSlowPath) ;
3421 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3422 masm.jmpb (DONE_LABEL) ;
3423
3424 masm.bind (LSuccess) ;
3425 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3426 masm.jmpb (DONE_LABEL) ;
3427 }
3428
3429 masm.bind (Stacked) ;
3430 // It's not inflated and it's not recursively stack-locked and it's not biased.
3431 // It must be stack-locked.
3432 // Try to reset the header to displaced header.
3433 // The "box" value on the stack is stable, so we can reload
3434 // and be assured we observe the same value as above.
3435 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3436 if (os::is_MP()) { masm.lock(); }
3437 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3438 // Intention fall-thru into DONE_LABEL
3439
3440
3441 // DONE_LABEL is a hot target - we'd really like to place it at the
3442 // start of cache line by padding with NOPs.
3443 // See the AMD and Intel software optimization manuals for the
3444 // most efficient "long" NOP encodings.
3445 // Unfortunately none of our alignment mechanisms suffice.
3446 if ((EmitSync & 65536) == 0) {
3447 masm.bind (CheckSucc) ;
3448 }
3449 masm.bind(DONE_LABEL);
3450
3451 // Avoid branch to branch on AMD processors
3452 if (EmitSync & 32768) { masm.nop() ; }
3453 }
3454 %}
3455
3456
3457 enc_class enc_pop_rdx() %{
3458 emit_opcode(cbuf,0x5A);
3459 %}
3460
3461 enc_class enc_rethrow() %{
3462 cbuf.set_insts_mark();
3463 emit_opcode(cbuf, 0xE9); // jmp entry
3464 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3465 runtime_call_Relocation::spec(), RELOC_IMM32 );
3466 %}
3467
3468
3469 // Convert a double to an int. Java semantics require we do complex
3470 // manglelations in the corner cases. So we set the rounding mode to
3471 // 'zero', store the darned double down as an int, and reset the
3472 // rounding mode to 'nearest'. The hardware throws an exception which
3473 // patches up the correct value directly to the stack.
3474 enc_class DPR2I_encoding( regDPR src ) %{
3475 // Flip to round-to-zero mode. We attempted to allow invalid-op
3476 // exceptions here, so that a NAN or other corner-case value will
3477 // thrown an exception (but normal values get converted at full speed).
3478 // However, I2C adapters and other float-stack manglers leave pending
3479 // invalid-op exceptions hanging. We would have to clear them before
3480 // enabling them and that is more expensive than just testing for the
3481 // invalid value Intel stores down in the corner cases.
3482 emit_opcode(cbuf,0xD9); // FLDCW trunc
3483 emit_opcode(cbuf,0x2D);
3484 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3485 // Allocate a word
3486 emit_opcode(cbuf,0x83); // SUB ESP,4
3487 emit_opcode(cbuf,0xEC);
3488 emit_d8(cbuf,0x04);
3489 // Encoding assumes a double has been pushed into FPR0.
3490 // Store down the double as an int, popping the FPU stack
3491 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3492 emit_opcode(cbuf,0x1C);
3493 emit_d8(cbuf,0x24);
3494 // Restore the rounding mode; mask the exception
3495 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3496 emit_opcode(cbuf,0x2D);
3497 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3498 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3499 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3500
3501 // Load the converted int; adjust CPU stack
3502 emit_opcode(cbuf,0x58); // POP EAX
3503 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3504 emit_d32 (cbuf,0x80000000); // 0x80000000
3505 emit_opcode(cbuf,0x75); // JNE around_slow_call
3506 emit_d8 (cbuf,0x07); // Size of slow_call
3507 // Push src onto stack slow-path
3508 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3509 emit_d8 (cbuf,0xC0-1+$src$$reg );
3510 // CALL directly to the runtime
3511 cbuf.set_insts_mark();
3512 emit_opcode(cbuf,0xE8); // Call into runtime
3513 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3514 // Carry on here...
3515 %}
3516
3517 enc_class DPR2L_encoding( regDPR src ) %{
3518 emit_opcode(cbuf,0xD9); // FLDCW trunc
3519 emit_opcode(cbuf,0x2D);
3520 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3521 // Allocate a word
3522 emit_opcode(cbuf,0x83); // SUB ESP,8
3523 emit_opcode(cbuf,0xEC);
3524 emit_d8(cbuf,0x08);
3525 // Encoding assumes a double has been pushed into FPR0.
3526 // Store down the double as a long, popping the FPU stack
3527 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3528 emit_opcode(cbuf,0x3C);
3529 emit_d8(cbuf,0x24);
3530 // Restore the rounding mode; mask the exception
3531 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3532 emit_opcode(cbuf,0x2D);
3533 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3534 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3535 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3536
3537 // Load the converted int; adjust CPU stack
3538 emit_opcode(cbuf,0x58); // POP EAX
3539 emit_opcode(cbuf,0x5A); // POP EDX
3540 emit_opcode(cbuf,0x81); // CMP EDX,imm
3541 emit_d8 (cbuf,0xFA); // rdx
3542 emit_d32 (cbuf,0x80000000); // 0x80000000
3543 emit_opcode(cbuf,0x75); // JNE around_slow_call
3544 emit_d8 (cbuf,0x07+4); // Size of slow_call
3545 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3546 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3547 emit_opcode(cbuf,0x75); // JNE around_slow_call
3548 emit_d8 (cbuf,0x07); // Size of slow_call
3549 // Push src onto stack slow-path
3550 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3551 emit_d8 (cbuf,0xC0-1+$src$$reg );
3552 // CALL directly to the runtime
3553 cbuf.set_insts_mark();
3554 emit_opcode(cbuf,0xE8); // Call into runtime
3555 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3556 // Carry on here...
3557 %}
3558
3559 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3560 // Operand was loaded from memory into fp ST (stack top)
3561 // FMUL ST,$src /* D8 C8+i */
3562 emit_opcode(cbuf, 0xD8);
3563 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3564 %}
3565
3566 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3567 // FADDP ST,src2 /* D8 C0+i */
3568 emit_opcode(cbuf, 0xD8);
3569 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3570 //could use FADDP src2,fpST /* DE C0+i */
3571 %}
3572
3573 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3574 // FADDP src2,ST /* DE C0+i */
3575 emit_opcode(cbuf, 0xDE);
3576 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3577 %}
3578
3579 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3580 // Operand has been loaded into fp ST (stack top)
3581 // FSUB ST,$src1
3582 emit_opcode(cbuf, 0xD8);
3583 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3584
3585 // FDIV
3586 emit_opcode(cbuf, 0xD8);
3587 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3588 %}
3589
3590 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3591 // Operand was loaded from memory into fp ST (stack top)
3592 // FADD ST,$src /* D8 C0+i */
3593 emit_opcode(cbuf, 0xD8);
3594 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3595
3596 // FMUL ST,src2 /* D8 C*+i */
3597 emit_opcode(cbuf, 0xD8);
3598 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3599 %}
3600
3601
3602 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3603 // Operand was loaded from memory into fp ST (stack top)
3604 // FADD ST,$src /* D8 C0+i */
3605 emit_opcode(cbuf, 0xD8);
3606 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3607
3608 // FMULP src2,ST /* DE C8+i */
3609 emit_opcode(cbuf, 0xDE);
3610 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3611 %}
3612
3613 // Atomically load the volatile long
3614 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3615 emit_opcode(cbuf,0xDF);
3616 int rm_byte_opcode = 0x05;
3617 int base = $mem$$base;
3618 int index = $mem$$index;
3619 int scale = $mem$$scale;
3620 int displace = $mem$$disp;
3621 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3622 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3623 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3624 %}
3625
3626 // Volatile Store Long. Must be atomic, so move it into
3627 // the FP TOS and then do a 64-bit FIST. Has to probe the
3628 // target address before the store (for null-ptr checks)
3629 // so the memory operand is used twice in the encoding.
3630 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3631 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3632 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3633 emit_opcode(cbuf,0xDF);
3634 int rm_byte_opcode = 0x07;
3635 int base = $mem$$base;
3636 int index = $mem$$index;
3637 int scale = $mem$$scale;
3638 int displace = $mem$$disp;
3639 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3640 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3641 %}
3642
3643 // Safepoint Poll. This polls the safepoint page, and causes an
3644 // exception if it is not readable. Unfortunately, it kills the condition code
3645 // in the process
3646 // We current use TESTL [spp],EDI
3647 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3648
3649 enc_class Safepoint_Poll() %{
3650 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3651 emit_opcode(cbuf,0x85);
3652 emit_rm (cbuf, 0x0, 0x7, 0x5);
3653 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3654 %}
3655 %}
3656
3657
3658 //----------FRAME--------------------------------------------------------------
3659 // Definition of frame structure and management information.
3660 //
3661 // S T A C K L A Y O U T Allocators stack-slot number
3662 // | (to get allocators register number
3663 // G Owned by | | v add OptoReg::stack0())
3664 // r CALLER | |
3665 // o | +--------+ pad to even-align allocators stack-slot
3666 // w V | pad0 | numbers; owned by CALLER
3667 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3668 // h ^ | in | 5
3669 // | | args | 4 Holes in incoming args owned by SELF
3670 // | | | | 3
3671 // | | +--------+
3672 // V | | old out| Empty on Intel, window on Sparc
3673 // | old |preserve| Must be even aligned.
3674 // | SP-+--------+----> Matcher::_old_SP, even aligned
3675 // | | in | 3 area for Intel ret address
3676 // Owned by |preserve| Empty on Sparc.
3677 // SELF +--------+
3678 // | | pad2 | 2 pad to align old SP
3679 // | +--------+ 1
3680 // | | locks | 0
3681 // | +--------+----> OptoReg::stack0(), even aligned
3682 // | | pad1 | 11 pad to align new SP
3683 // | +--------+
3684 // | | | 10
3685 // | | spills | 9 spills
3686 // V | | 8 (pad0 slot for callee)
3687 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3688 // ^ | out | 7
3689 // | | args | 6 Holes in outgoing args owned by CALLEE
3690 // Owned by +--------+
3691 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3692 // | new |preserve| Must be even-aligned.
3693 // | SP-+--------+----> Matcher::_new_SP, even aligned
3694 // | | |
3695 //
3696 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3697 // known from SELF's arguments and the Java calling convention.
3698 // Region 6-7 is determined per call site.
3699 // Note 2: If the calling convention leaves holes in the incoming argument
3700 // area, those holes are owned by SELF. Holes in the outgoing area
3701 // are owned by the CALLEE. Holes should not be nessecary in the
3702 // incoming area, as the Java calling convention is completely under
3703 // the control of the AD file. Doubles can be sorted and packed to
3704 // avoid holes. Holes in the outgoing arguments may be nessecary for
3705 // varargs C calling conventions.
3706 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3707 // even aligned with pad0 as needed.
3708 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3709 // region 6-11 is even aligned; it may be padded out more so that
3710 // the region from SP to FP meets the minimum stack alignment.
3711
3712 frame %{
3713 // What direction does stack grow in (assumed to be same for C & Java)
3714 stack_direction(TOWARDS_LOW);
3715
3716 // These three registers define part of the calling convention
3717 // between compiled code and the interpreter.
3718 inline_cache_reg(EAX); // Inline Cache Register
3719 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3720
3721 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3722 cisc_spilling_operand_name(indOffset32);
3723
3724 // Number of stack slots consumed by locking an object
3725 sync_stack_slots(1);
3726
3727 // Compiled code's Frame Pointer
3728 frame_pointer(ESP);
3729 // Interpreter stores its frame pointer in a register which is
3730 // stored to the stack by I2CAdaptors.
3731 // I2CAdaptors convert from interpreted java to compiled java.
3732 interpreter_frame_pointer(EBP);
3733
3734 // Stack alignment requirement
3735 // Alignment size in bytes (128-bit -> 16 bytes)
3736 stack_alignment(StackAlignmentInBytes);
3737
3738 // Number of stack slots between incoming argument block and the start of
3739 // a new frame. The PROLOG must add this many slots to the stack. The
3740 // EPILOG must remove this many slots. Intel needs one slot for
3741 // return address and one for rbp, (must save rbp)
3742 in_preserve_stack_slots(2+VerifyStackAtCalls);
3743
3744 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3745 // for calls to C. Supports the var-args backing area for register parms.
3746 varargs_C_out_slots_killed(0);
3747
3748 // The after-PROLOG location of the return address. Location of
3749 // return address specifies a type (REG or STACK) and a number
3750 // representing the register number (i.e. - use a register name) or
3751 // stack slot.
3752 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3753 // Otherwise, it is above the locks and verification slot and alignment word
3754 return_addr(STACK - 1 +
3755 round_to((Compile::current()->in_preserve_stack_slots() +
3756 Compile::current()->fixed_slots()),
3757 stack_alignment_in_slots()));
3758
3759 // Body of function which returns an integer array locating
3760 // arguments either in registers or in stack slots. Passed an array
3761 // of ideal registers called "sig" and a "length" count. Stack-slot
3762 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3763 // arguments for a CALLEE. Incoming stack arguments are
3764 // automatically biased by the preserve_stack_slots field above.
3765 calling_convention %{
3766 // No difference between ingoing/outgoing just pass false
3767 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3768 %}
3769
3770
3771 // Body of function which returns an integer array locating
3772 // arguments either in registers or in stack slots. Passed an array
3773 // of ideal registers called "sig" and a "length" count. Stack-slot
3774 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3775 // arguments for a CALLEE. Incoming stack arguments are
3776 // automatically biased by the preserve_stack_slots field above.
3777 c_calling_convention %{
3778 // This is obviously always outgoing
3779 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3780 %}
3781
3782 // Location of C & interpreter return values
3783 c_return_value %{
3784 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3785 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3786 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3787
3788 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3789 // that C functions return float and double results in XMM0.
3790 if( ideal_reg == Op_RegD && UseSSE>=2 )
3791 return OptoRegPair(XMM0b_num,XMM0_num);
3792 if( ideal_reg == Op_RegF && UseSSE>=2 )
3793 return OptoRegPair(OptoReg::Bad,XMM0_num);
3794
3795 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3796 %}
3797
3798 // Location of return values
3799 return_value %{
3800 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3801 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3802 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3803 if( ideal_reg == Op_RegD && UseSSE>=2 )
3804 return OptoRegPair(XMM0b_num,XMM0_num);
3805 if( ideal_reg == Op_RegF && UseSSE>=1 )
3806 return OptoRegPair(OptoReg::Bad,XMM0_num);
3807 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3808 %}
3809
3810 %}
3811
3812 //----------ATTRIBUTES---------------------------------------------------------
3813 //----------Operand Attributes-------------------------------------------------
3814 op_attrib op_cost(0); // Required cost attribute
3815
3816 //----------Instruction Attributes---------------------------------------------
3817 ins_attrib ins_cost(100); // Required cost attribute
3818 ins_attrib ins_size(8); // Required size attribute (in bits)
3819 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3820 // non-matching short branch variant of some
3821 // long branch?
3822 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3823 // specifies the alignment that some part of the instruction (not
3824 // necessarily the start) requires. If > 1, a compute_padding()
3825 // function must be provided for the instruction
3826
3827 //----------OPERANDS-----------------------------------------------------------
3828 // Operand definitions must precede instruction definitions for correct parsing
3829 // in the ADLC because operands constitute user defined types which are used in
3830 // instruction definitions.
3831
3832 //----------Simple Operands----------------------------------------------------
3833 // Immediate Operands
3834 // Integer Immediate
3835 operand immI() %{
3836 match(ConI);
3837
3838 op_cost(10);
3839 format %{ %}
3840 interface(CONST_INTER);
3841 %}
3842
3843 // Constant for test vs zero
3844 operand immI0() %{
3845 predicate(n->get_int() == 0);
3846 match(ConI);
3847
3848 op_cost(0);
3849 format %{ %}
3850 interface(CONST_INTER);
3851 %}
3852
3853 // Constant for increment
3854 operand immI1() %{
3855 predicate(n->get_int() == 1);
3856 match(ConI);
3857
3858 op_cost(0);
3859 format %{ %}
3860 interface(CONST_INTER);
3861 %}
3862
3863 // Constant for decrement
3864 operand immI_M1() %{
3865 predicate(n->get_int() == -1);
3866 match(ConI);
3867
3868 op_cost(0);
3869 format %{ %}
3870 interface(CONST_INTER);
3871 %}
3872
3873 // Valid scale values for addressing modes
3874 operand immI2() %{
3875 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3876 match(ConI);
3877
3878 format %{ %}
3879 interface(CONST_INTER);
3880 %}
3881
3882 operand immI8() %{
3883 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3884 match(ConI);
3885
3886 op_cost(5);
3887 format %{ %}
3888 interface(CONST_INTER);
3889 %}
3890
3891 operand immI16() %{
3892 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3893 match(ConI);
3894
3895 op_cost(10);
3896 format %{ %}
3897 interface(CONST_INTER);
3898 %}
3899
3900 // Int Immediate non-negative
3901 operand immU31()
3902 %{
3903 predicate(n->get_int() >= 0);
3904 match(ConI);
3905
3906 op_cost(0);
3907 format %{ %}
3908 interface(CONST_INTER);
3909 %}
3910
3911 // Constant for long shifts
3912 operand immI_32() %{
3913 predicate( n->get_int() == 32 );
3914 match(ConI);
3915
3916 op_cost(0);
3917 format %{ %}
3918 interface(CONST_INTER);
3919 %}
3920
3921 operand immI_1_31() %{
3922 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3923 match(ConI);
3924
3925 op_cost(0);
3926 format %{ %}
3927 interface(CONST_INTER);
3928 %}
3929
3930 operand immI_32_63() %{
3931 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3932 match(ConI);
3933 op_cost(0);
3934
3935 format %{ %}
3936 interface(CONST_INTER);
3937 %}
3938
3939 operand immI_1() %{
3940 predicate( n->get_int() == 1 );
3941 match(ConI);
3942
3943 op_cost(0);
3944 format %{ %}
3945 interface(CONST_INTER);
3946 %}
3947
3948 operand immI_2() %{
3949 predicate( n->get_int() == 2 );
3950 match(ConI);
3951
3952 op_cost(0);
3953 format %{ %}
3954 interface(CONST_INTER);
3955 %}
3956
3957 operand immI_3() %{
3958 predicate( n->get_int() == 3 );
3959 match(ConI);
3960
3961 op_cost(0);
3962 format %{ %}
3963 interface(CONST_INTER);
3964 %}
3965
3966 // Pointer Immediate
3967 operand immP() %{
3968 match(ConP);
3969
3970 op_cost(10);
3971 format %{ %}
3972 interface(CONST_INTER);
3973 %}
3974
3975 // NULL Pointer Immediate
3976 operand immP0() %{
3977 predicate( n->get_ptr() == 0 );
3978 match(ConP);
3979 op_cost(0);
3980
3981 format %{ %}
3982 interface(CONST_INTER);
3983 %}
3984
3985 // Long Immediate
3986 operand immL() %{
3987 match(ConL);
3988
3989 op_cost(20);
3990 format %{ %}
3991 interface(CONST_INTER);
3992 %}
3993
3994 // Long Immediate zero
3995 operand immL0() %{
3996 predicate( n->get_long() == 0L );
3997 match(ConL);
3998 op_cost(0);
3999
4000 format %{ %}
4001 interface(CONST_INTER);
4002 %}
4003
4004 // Long Immediate zero
4005 operand immL_M1() %{
4006 predicate( n->get_long() == -1L );
4007 match(ConL);
4008 op_cost(0);
4009
4010 format %{ %}
4011 interface(CONST_INTER);
4012 %}
4013
4014 // Long immediate from 0 to 127.
4015 // Used for a shorter form of long mul by 10.
4016 operand immL_127() %{
4017 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4018 match(ConL);
4019 op_cost(0);
4020
4021 format %{ %}
4022 interface(CONST_INTER);
4023 %}
4024
4025 // Long Immediate: low 32-bit mask
4026 operand immL_32bits() %{
4027 predicate(n->get_long() == 0xFFFFFFFFL);
4028 match(ConL);
4029 op_cost(0);
4030
4031 format %{ %}
4032 interface(CONST_INTER);
4033 %}
4034
4035 // Long Immediate: low 32-bit mask
4036 operand immL32() %{
4037 predicate(n->get_long() == (int)(n->get_long()));
4038 match(ConL);
4039 op_cost(20);
4040
4041 format %{ %}
4042 interface(CONST_INTER);
4043 %}
4044
4045 //Double Immediate zero
4046 operand immDPR0() %{
4047 // Do additional (and counter-intuitive) test against NaN to work around VC++
4048 // bug that generates code such that NaNs compare equal to 0.0
4049 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4050 match(ConD);
4051
4052 op_cost(5);
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4056
4057 // Double Immediate one
4058 operand immDPR1() %{
4059 predicate( UseSSE<=1 && n->getd() == 1.0 );
4060 match(ConD);
4061
4062 op_cost(5);
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4066
4067 // Double Immediate
4068 operand immDPR() %{
4069 predicate(UseSSE<=1);
4070 match(ConD);
4071
4072 op_cost(5);
4073 format %{ %}
4074 interface(CONST_INTER);
4075 %}
4076
4077 operand immD() %{
4078 predicate(UseSSE>=2);
4079 match(ConD);
4080
4081 op_cost(5);
4082 format %{ %}
4083 interface(CONST_INTER);
4084 %}
4085
4086 // Double Immediate zero
4087 operand immD0() %{
4088 // Do additional (and counter-intuitive) test against NaN to work around VC++
4089 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4090 // compare equal to -0.0.
4091 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4092 match(ConD);
4093
4094 format %{ %}
4095 interface(CONST_INTER);
4096 %}
4097
4098 // Float Immediate zero
4099 operand immFPR0() %{
4100 predicate(UseSSE == 0 && n->getf() == 0.0F);
4101 match(ConF);
4102
4103 op_cost(5);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4107
4108 // Float Immediate one
4109 operand immFPR1() %{
4110 predicate(UseSSE == 0 && n->getf() == 1.0F);
4111 match(ConF);
4112
4113 op_cost(5);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4117
4118 // Float Immediate
4119 operand immFPR() %{
4120 predicate( UseSSE == 0 );
4121 match(ConF);
4122
4123 op_cost(5);
4124 format %{ %}
4125 interface(CONST_INTER);
4126 %}
4127
4128 // Float Immediate
4129 operand immF() %{
4130 predicate(UseSSE >= 1);
4131 match(ConF);
4132
4133 op_cost(5);
4134 format %{ %}
4135 interface(CONST_INTER);
4136 %}
4137
4138 // Float Immediate zero. Zero and not -0.0
4139 operand immF0() %{
4140 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4141 match(ConF);
4142
4143 op_cost(5);
4144 format %{ %}
4145 interface(CONST_INTER);
4146 %}
4147
4148 // Immediates for special shifts (sign extend)
4149
4150 // Constants for increment
4151 operand immI_16() %{
4152 predicate( n->get_int() == 16 );
4153 match(ConI);
4154
4155 format %{ %}
4156 interface(CONST_INTER);
4157 %}
4158
4159 operand immI_24() %{
4160 predicate( n->get_int() == 24 );
4161 match(ConI);
4162
4163 format %{ %}
4164 interface(CONST_INTER);
4165 %}
4166
4167 // Constant for byte-wide masking
4168 operand immI_255() %{
4169 predicate( n->get_int() == 255 );
4170 match(ConI);
4171
4172 format %{ %}
4173 interface(CONST_INTER);
4174 %}
4175
4176 // Constant for short-wide masking
4177 operand immI_65535() %{
4178 predicate(n->get_int() == 65535);
4179 match(ConI);
4180
4181 format %{ %}
4182 interface(CONST_INTER);
4183 %}
4184
4185 // Register Operands
4186 // Integer Register
4187 operand rRegI() %{
4188 constraint(ALLOC_IN_RC(int_reg));
4189 match(RegI);
4190 match(xRegI);
4191 match(eAXRegI);
4192 match(eBXRegI);
4193 match(eCXRegI);
4194 match(eDXRegI);
4195 match(eDIRegI);
4196 match(eSIRegI);
4197
4198 format %{ %}
4199 interface(REG_INTER);
4200 %}
4201
4202 // Subset of Integer Register
4203 operand xRegI(rRegI reg) %{
4204 constraint(ALLOC_IN_RC(int_x_reg));
4205 match(reg);
4206 match(eAXRegI);
4207 match(eBXRegI);
4208 match(eCXRegI);
4209 match(eDXRegI);
4210
4211 format %{ %}
4212 interface(REG_INTER);
4213 %}
4214
4215 // Special Registers
4216 operand eAXRegI(xRegI reg) %{
4217 constraint(ALLOC_IN_RC(eax_reg));
4218 match(reg);
4219 match(rRegI);
4220
4221 format %{ "EAX" %}
4222 interface(REG_INTER);
4223 %}
4224
4225 // Special Registers
4226 operand eBXRegI(xRegI reg) %{
4227 constraint(ALLOC_IN_RC(ebx_reg));
4228 match(reg);
4229 match(rRegI);
4230
4231 format %{ "EBX" %}
4232 interface(REG_INTER);
4233 %}
4234
4235 operand eCXRegI(xRegI reg) %{
4236 constraint(ALLOC_IN_RC(ecx_reg));
4237 match(reg);
4238 match(rRegI);
4239
4240 format %{ "ECX" %}
4241 interface(REG_INTER);
4242 %}
4243
4244 operand eDXRegI(xRegI reg) %{
4245 constraint(ALLOC_IN_RC(edx_reg));
4246 match(reg);
4247 match(rRegI);
4248
4249 format %{ "EDX" %}
4250 interface(REG_INTER);
4251 %}
4252
4253 operand eDIRegI(xRegI reg) %{
4254 constraint(ALLOC_IN_RC(edi_reg));
4255 match(reg);
4256 match(rRegI);
4257
4258 format %{ "EDI" %}
4259 interface(REG_INTER);
4260 %}
4261
4262 operand naxRegI() %{
4263 constraint(ALLOC_IN_RC(nax_reg));
4264 match(RegI);
4265 match(eCXRegI);
4266 match(eDXRegI);
4267 match(eSIRegI);
4268 match(eDIRegI);
4269
4270 format %{ %}
4271 interface(REG_INTER);
4272 %}
4273
4274 operand nadxRegI() %{
4275 constraint(ALLOC_IN_RC(nadx_reg));
4276 match(RegI);
4277 match(eBXRegI);
4278 match(eCXRegI);
4279 match(eSIRegI);
4280 match(eDIRegI);
4281
4282 format %{ %}
4283 interface(REG_INTER);
4284 %}
4285
4286 operand ncxRegI() %{
4287 constraint(ALLOC_IN_RC(ncx_reg));
4288 match(RegI);
4289 match(eAXRegI);
4290 match(eDXRegI);
4291 match(eSIRegI);
4292 match(eDIRegI);
4293
4294 format %{ %}
4295 interface(REG_INTER);
4296 %}
4297
4298 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4299 // //
4300 operand eSIRegI(xRegI reg) %{
4301 constraint(ALLOC_IN_RC(esi_reg));
4302 match(reg);
4303 match(rRegI);
4304
4305 format %{ "ESI" %}
4306 interface(REG_INTER);
4307 %}
4308
4309 // Pointer Register
4310 operand anyRegP() %{
4311 constraint(ALLOC_IN_RC(any_reg));
4312 match(RegP);
4313 match(eAXRegP);
4314 match(eBXRegP);
4315 match(eCXRegP);
4316 match(eDIRegP);
4317 match(eRegP);
4318
4319 format %{ %}
4320 interface(REG_INTER);
4321 %}
4322
4323 operand eRegP() %{
4324 constraint(ALLOC_IN_RC(int_reg));
4325 match(RegP);
4326 match(eAXRegP);
4327 match(eBXRegP);
4328 match(eCXRegP);
4329 match(eDIRegP);
4330
4331 format %{ %}
4332 interface(REG_INTER);
4333 %}
4334
4335 // On windows95, EBP is not safe to use for implicit null tests.
4336 operand eRegP_no_EBP() %{
4337 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4338 match(RegP);
4339 match(eAXRegP);
4340 match(eBXRegP);
4341 match(eCXRegP);
4342 match(eDIRegP);
4343
4344 op_cost(100);
4345 format %{ %}
4346 interface(REG_INTER);
4347 %}
4348
4349 operand naxRegP() %{
4350 constraint(ALLOC_IN_RC(nax_reg));
4351 match(RegP);
4352 match(eBXRegP);
4353 match(eDXRegP);
4354 match(eCXRegP);
4355 match(eSIRegP);
4356 match(eDIRegP);
4357
4358 format %{ %}
4359 interface(REG_INTER);
4360 %}
4361
4362 operand nabxRegP() %{
4363 constraint(ALLOC_IN_RC(nabx_reg));
4364 match(RegP);
4365 match(eCXRegP);
4366 match(eDXRegP);
4367 match(eSIRegP);
4368 match(eDIRegP);
4369
4370 format %{ %}
4371 interface(REG_INTER);
4372 %}
4373
4374 operand pRegP() %{
4375 constraint(ALLOC_IN_RC(p_reg));
4376 match(RegP);
4377 match(eBXRegP);
4378 match(eDXRegP);
4379 match(eSIRegP);
4380 match(eDIRegP);
4381
4382 format %{ %}
4383 interface(REG_INTER);
4384 %}
4385
4386 // Special Registers
4387 // Return a pointer value
4388 operand eAXRegP(eRegP reg) %{
4389 constraint(ALLOC_IN_RC(eax_reg));
4390 match(reg);
4391 format %{ "EAX" %}
4392 interface(REG_INTER);
4393 %}
4394
4395 // Used in AtomicAdd
4396 operand eBXRegP(eRegP reg) %{
4397 constraint(ALLOC_IN_RC(ebx_reg));
4398 match(reg);
4399 format %{ "EBX" %}
4400 interface(REG_INTER);
4401 %}
4402
4403 // Tail-call (interprocedural jump) to interpreter
4404 operand eCXRegP(eRegP reg) %{
4405 constraint(ALLOC_IN_RC(ecx_reg));
4406 match(reg);
4407 format %{ "ECX" %}
4408 interface(REG_INTER);
4409 %}
4410
4411 operand eSIRegP(eRegP reg) %{
4412 constraint(ALLOC_IN_RC(esi_reg));
4413 match(reg);
4414 format %{ "ESI" %}
4415 interface(REG_INTER);
4416 %}
4417
4418 // Used in rep stosw
4419 operand eDIRegP(eRegP reg) %{
4420 constraint(ALLOC_IN_RC(edi_reg));
4421 match(reg);
4422 format %{ "EDI" %}
4423 interface(REG_INTER);
4424 %}
4425
4426 operand eBPRegP() %{
4427 constraint(ALLOC_IN_RC(ebp_reg));
4428 match(RegP);
4429 format %{ "EBP" %}
4430 interface(REG_INTER);
4431 %}
4432
4433 operand eRegL() %{
4434 constraint(ALLOC_IN_RC(long_reg));
4435 match(RegL);
4436 match(eADXRegL);
4437
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4441
4442 operand eADXRegL( eRegL reg ) %{
4443 constraint(ALLOC_IN_RC(eadx_reg));
4444 match(reg);
4445
4446 format %{ "EDX:EAX" %}
4447 interface(REG_INTER);
4448 %}
4449
4450 operand eBCXRegL( eRegL reg ) %{
4451 constraint(ALLOC_IN_RC(ebcx_reg));
4452 match(reg);
4453
4454 format %{ "EBX:ECX" %}
4455 interface(REG_INTER);
4456 %}
4457
4458 // Special case for integer high multiply
4459 operand eADXRegL_low_only() %{
4460 constraint(ALLOC_IN_RC(eadx_reg));
4461 match(RegL);
4462
4463 format %{ "EAX" %}
4464 interface(REG_INTER);
4465 %}
4466
4467 // Flags register, used as output of compare instructions
4468 operand eFlagsReg() %{
4469 constraint(ALLOC_IN_RC(int_flags));
4470 match(RegFlags);
4471
4472 format %{ "EFLAGS" %}
4473 interface(REG_INTER);
4474 %}
4475
4476 // Flags register, used as output of FLOATING POINT compare instructions
4477 operand eFlagsRegU() %{
4478 constraint(ALLOC_IN_RC(int_flags));
4479 match(RegFlags);
4480
4481 format %{ "EFLAGS_U" %}
4482 interface(REG_INTER);
4483 %}
4484
4485 operand eFlagsRegUCF() %{
4486 constraint(ALLOC_IN_RC(int_flags));
4487 match(RegFlags);
4488 predicate(false);
4489
4490 format %{ "EFLAGS_U_CF" %}
4491 interface(REG_INTER);
4492 %}
4493
4494 // Condition Code Register used by long compare
4495 operand flagsReg_long_LTGE() %{
4496 constraint(ALLOC_IN_RC(int_flags));
4497 match(RegFlags);
4498 format %{ "FLAGS_LTGE" %}
4499 interface(REG_INTER);
4500 %}
4501 operand flagsReg_long_EQNE() %{
4502 constraint(ALLOC_IN_RC(int_flags));
4503 match(RegFlags);
4504 format %{ "FLAGS_EQNE" %}
4505 interface(REG_INTER);
4506 %}
4507 operand flagsReg_long_LEGT() %{
4508 constraint(ALLOC_IN_RC(int_flags));
4509 match(RegFlags);
4510 format %{ "FLAGS_LEGT" %}
4511 interface(REG_INTER);
4512 %}
4513
4514 // Float register operands
4515 operand regDPR() %{
4516 predicate( UseSSE < 2 );
4517 constraint(ALLOC_IN_RC(fp_dbl_reg));
4518 match(RegD);
4519 match(regDPR1);
4520 match(regDPR2);
4521 format %{ %}
4522 interface(REG_INTER);
4523 %}
4524
4525 operand regDPR1(regDPR reg) %{
4526 predicate( UseSSE < 2 );
4527 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4528 match(reg);
4529 format %{ "FPR1" %}
4530 interface(REG_INTER);
4531 %}
4532
4533 operand regDPR2(regDPR reg) %{
4534 predicate( UseSSE < 2 );
4535 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4536 match(reg);
4537 format %{ "FPR2" %}
4538 interface(REG_INTER);
4539 %}
4540
4541 operand regnotDPR1(regDPR reg) %{
4542 predicate( UseSSE < 2 );
4543 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4544 match(reg);
4545 format %{ %}
4546 interface(REG_INTER);
4547 %}
4548
4549 // Float register operands
4550 operand regFPR() %{
4551 predicate( UseSSE < 2 );
4552 constraint(ALLOC_IN_RC(fp_flt_reg));
4553 match(RegF);
4554 match(regFPR1);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4558
4559 // Float register operands
4560 operand regFPR1(regFPR reg) %{
4561 predicate( UseSSE < 2 );
4562 constraint(ALLOC_IN_RC(fp_flt_reg0));
4563 match(reg);
4564 format %{ "FPR1" %}
4565 interface(REG_INTER);
4566 %}
4567
4568 // XMM Float register operands
4569 operand regF() %{
4570 predicate( UseSSE>=1 );
4571 constraint(ALLOC_IN_RC(float_reg));
4572 match(RegF);
4573 format %{ %}
4574 interface(REG_INTER);
4575 %}
4576
4577 // XMM Double register operands
4578 operand regD() %{
4579 predicate( UseSSE>=2 );
4580 constraint(ALLOC_IN_RC(double_reg));
4581 match(RegD);
4582 format %{ %}
4583 interface(REG_INTER);
4584 %}
4585
4586
4587 //----------Memory Operands----------------------------------------------------
4588 // Direct Memory Operand
4589 operand direct(immP addr) %{
4590 match(addr);
4591
4592 format %{ "[$addr]" %}
4593 interface(MEMORY_INTER) %{
4594 base(0xFFFFFFFF);
4595 index(0x4);
4596 scale(0x0);
4597 disp($addr);
4598 %}
4599 %}
4600
4601 // Indirect Memory Operand
4602 operand indirect(eRegP reg) %{
4603 constraint(ALLOC_IN_RC(int_reg));
4604 match(reg);
4605
4606 format %{ "[$reg]" %}
4607 interface(MEMORY_INTER) %{
4608 base($reg);
4609 index(0x4);
4610 scale(0x0);
4611 disp(0x0);
4612 %}
4613 %}
4614
4615 // Indirect Memory Plus Short Offset Operand
4616 operand indOffset8(eRegP reg, immI8 off) %{
4617 match(AddP reg off);
4618
4619 format %{ "[$reg + $off]" %}
4620 interface(MEMORY_INTER) %{
4621 base($reg);
4622 index(0x4);
4623 scale(0x0);
4624 disp($off);
4625 %}
4626 %}
4627
4628 // Indirect Memory Plus Long Offset Operand
4629 operand indOffset32(eRegP reg, immI off) %{
4630 match(AddP reg off);
4631
4632 format %{ "[$reg + $off]" %}
4633 interface(MEMORY_INTER) %{
4634 base($reg);
4635 index(0x4);
4636 scale(0x0);
4637 disp($off);
4638 %}
4639 %}
4640
4641 // Indirect Memory Plus Long Offset Operand
4642 operand indOffset32X(rRegI reg, immP off) %{
4643 match(AddP off reg);
4644
4645 format %{ "[$reg + $off]" %}
4646 interface(MEMORY_INTER) %{
4647 base($reg);
4648 index(0x4);
4649 scale(0x0);
4650 disp($off);
4651 %}
4652 %}
4653
4654 // Indirect Memory Plus Index Register Plus Offset Operand
4655 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4656 match(AddP (AddP reg ireg) off);
4657
4658 op_cost(10);
4659 format %{"[$reg + $off + $ireg]" %}
4660 interface(MEMORY_INTER) %{
4661 base($reg);
4662 index($ireg);
4663 scale(0x0);
4664 disp($off);
4665 %}
4666 %}
4667
4668 // Indirect Memory Plus Index Register Plus Offset Operand
4669 operand indIndex(eRegP reg, rRegI ireg) %{
4670 match(AddP reg ireg);
4671
4672 op_cost(10);
4673 format %{"[$reg + $ireg]" %}
4674 interface(MEMORY_INTER) %{
4675 base($reg);
4676 index($ireg);
4677 scale(0x0);
4678 disp(0x0);
4679 %}
4680 %}
4681
4682 // // -------------------------------------------------------------------------
4683 // // 486 architecture doesn't support "scale * index + offset" with out a base
4684 // // -------------------------------------------------------------------------
4685 // // Scaled Memory Operands
4686 // // Indirect Memory Times Scale Plus Offset Operand
4687 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4688 // match(AddP off (LShiftI ireg scale));
4689 //
4690 // op_cost(10);
4691 // format %{"[$off + $ireg << $scale]" %}
4692 // interface(MEMORY_INTER) %{
4693 // base(0x4);
4694 // index($ireg);
4695 // scale($scale);
4696 // disp($off);
4697 // %}
4698 // %}
4699
4700 // Indirect Memory Times Scale Plus Index Register
4701 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4702 match(AddP reg (LShiftI ireg scale));
4703
4704 op_cost(10);
4705 format %{"[$reg + $ireg << $scale]" %}
4706 interface(MEMORY_INTER) %{
4707 base($reg);
4708 index($ireg);
4709 scale($scale);
4710 disp(0x0);
4711 %}
4712 %}
4713
4714 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4715 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4716 match(AddP (AddP reg (LShiftI ireg scale)) off);
4717
4718 op_cost(10);
4719 format %{"[$reg + $off + $ireg << $scale]" %}
4720 interface(MEMORY_INTER) %{
4721 base($reg);
4722 index($ireg);
4723 scale($scale);
4724 disp($off);
4725 %}
4726 %}
4727
4728 //----------Load Long Memory Operands------------------------------------------
4729 // The load-long idiom will use it's address expression again after loading
4730 // the first word of the long. If the load-long destination overlaps with
4731 // registers used in the addressing expression, the 2nd half will be loaded
4732 // from a clobbered address. Fix this by requiring that load-long use
4733 // address registers that do not overlap with the load-long target.
4734
4735 // load-long support
4736 operand load_long_RegP() %{
4737 constraint(ALLOC_IN_RC(esi_reg));
4738 match(RegP);
4739 match(eSIRegP);
4740 op_cost(100);
4741 format %{ %}
4742 interface(REG_INTER);
4743 %}
4744
4745 // Indirect Memory Operand Long
4746 operand load_long_indirect(load_long_RegP reg) %{
4747 constraint(ALLOC_IN_RC(esi_reg));
4748 match(reg);
4749
4750 format %{ "[$reg]" %}
4751 interface(MEMORY_INTER) %{
4752 base($reg);
4753 index(0x4);
4754 scale(0x0);
4755 disp(0x0);
4756 %}
4757 %}
4758
4759 // Indirect Memory Plus Long Offset Operand
4760 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4761 match(AddP reg off);
4762
4763 format %{ "[$reg + $off]" %}
4764 interface(MEMORY_INTER) %{
4765 base($reg);
4766 index(0x4);
4767 scale(0x0);
4768 disp($off);
4769 %}
4770 %}
4771
4772 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4773
4774
4775 //----------Special Memory Operands--------------------------------------------
4776 // Stack Slot Operand - This operand is used for loading and storing temporary
4777 // values on the stack where a match requires a value to
4778 // flow through memory.
4779 operand stackSlotP(sRegP reg) %{
4780 constraint(ALLOC_IN_RC(stack_slots));
4781 // No match rule because this operand is only generated in matching
4782 format %{ "[$reg]" %}
4783 interface(MEMORY_INTER) %{
4784 base(0x4); // ESP
4785 index(0x4); // No Index
4786 scale(0x0); // No Scale
4787 disp($reg); // Stack Offset
4788 %}
4789 %}
4790
4791 operand stackSlotI(sRegI reg) %{
4792 constraint(ALLOC_IN_RC(stack_slots));
4793 // No match rule because this operand is only generated in matching
4794 format %{ "[$reg]" %}
4795 interface(MEMORY_INTER) %{
4796 base(0x4); // ESP
4797 index(0x4); // No Index
4798 scale(0x0); // No Scale
4799 disp($reg); // Stack Offset
4800 %}
4801 %}
4802
4803 operand stackSlotF(sRegF reg) %{
4804 constraint(ALLOC_IN_RC(stack_slots));
4805 // No match rule because this operand is only generated in matching
4806 format %{ "[$reg]" %}
4807 interface(MEMORY_INTER) %{
4808 base(0x4); // ESP
4809 index(0x4); // No Index
4810 scale(0x0); // No Scale
4811 disp($reg); // Stack Offset
4812 %}
4813 %}
4814
4815 operand stackSlotD(sRegD reg) %{
4816 constraint(ALLOC_IN_RC(stack_slots));
4817 // No match rule because this operand is only generated in matching
4818 format %{ "[$reg]" %}
4819 interface(MEMORY_INTER) %{
4820 base(0x4); // ESP
4821 index(0x4); // No Index
4822 scale(0x0); // No Scale
4823 disp($reg); // Stack Offset
4824 %}
4825 %}
4826
4827 operand stackSlotL(sRegL reg) %{
4828 constraint(ALLOC_IN_RC(stack_slots));
4829 // No match rule because this operand is only generated in matching
4830 format %{ "[$reg]" %}
4831 interface(MEMORY_INTER) %{
4832 base(0x4); // ESP
4833 index(0x4); // No Index
4834 scale(0x0); // No Scale
4835 disp($reg); // Stack Offset
4836 %}
4837 %}
4838
4839 //----------Memory Operands - Win95 Implicit Null Variants----------------
4840 // Indirect Memory Operand
4841 operand indirect_win95_safe(eRegP_no_EBP reg)
4842 %{
4843 constraint(ALLOC_IN_RC(int_reg));
4844 match(reg);
4845
4846 op_cost(100);
4847 format %{ "[$reg]" %}
4848 interface(MEMORY_INTER) %{
4849 base($reg);
4850 index(0x4);
4851 scale(0x0);
4852 disp(0x0);
4853 %}
4854 %}
4855
4856 // Indirect Memory Plus Short Offset Operand
4857 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4858 %{
4859 match(AddP reg off);
4860
4861 op_cost(100);
4862 format %{ "[$reg + $off]" %}
4863 interface(MEMORY_INTER) %{
4864 base($reg);
4865 index(0x4);
4866 scale(0x0);
4867 disp($off);
4868 %}
4869 %}
4870
4871 // Indirect Memory Plus Long Offset Operand
4872 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4873 %{
4874 match(AddP reg off);
4875
4876 op_cost(100);
4877 format %{ "[$reg + $off]" %}
4878 interface(MEMORY_INTER) %{
4879 base($reg);
4880 index(0x4);
4881 scale(0x0);
4882 disp($off);
4883 %}
4884 %}
4885
4886 // Indirect Memory Plus Index Register Plus Offset Operand
4887 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4888 %{
4889 match(AddP (AddP reg ireg) off);
4890
4891 op_cost(100);
4892 format %{"[$reg + $off + $ireg]" %}
4893 interface(MEMORY_INTER) %{
4894 base($reg);
4895 index($ireg);
4896 scale(0x0);
4897 disp($off);
4898 %}
4899 %}
4900
4901 // Indirect Memory Times Scale Plus Index Register
4902 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4903 %{
4904 match(AddP reg (LShiftI ireg scale));
4905
4906 op_cost(100);
4907 format %{"[$reg + $ireg << $scale]" %}
4908 interface(MEMORY_INTER) %{
4909 base($reg);
4910 index($ireg);
4911 scale($scale);
4912 disp(0x0);
4913 %}
4914 %}
4915
4916 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4917 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4918 %{
4919 match(AddP (AddP reg (LShiftI ireg scale)) off);
4920
4921 op_cost(100);
4922 format %{"[$reg + $off + $ireg << $scale]" %}
4923 interface(MEMORY_INTER) %{
4924 base($reg);
4925 index($ireg);
4926 scale($scale);
4927 disp($off);
4928 %}
4929 %}
4930
4931 //----------Conditional Branch Operands----------------------------------------
4932 // Comparison Op - This is the operation of the comparison, and is limited to
4933 // the following set of codes:
4934 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4935 //
4936 // Other attributes of the comparison, such as unsignedness, are specified
4937 // by the comparison instruction that sets a condition code flags register.
4938 // That result is represented by a flags operand whose subtype is appropriate
4939 // to the unsignedness (etc.) of the comparison.
4940 //
4941 // Later, the instruction which matches both the Comparison Op (a Bool) and
4942 // the flags (produced by the Cmp) specifies the coding of the comparison op
4943 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4944
4945 // Comparision Code
4946 operand cmpOp() %{
4947 match(Bool);
4948
4949 format %{ "" %}
4950 interface(COND_INTER) %{
4951 equal(0x4, "e");
4952 not_equal(0x5, "ne");
4953 less(0xC, "l");
4954 greater_equal(0xD, "ge");
4955 less_equal(0xE, "le");
4956 greater(0xF, "g");
4957 overflow(0x0, "o");
4958 no_overflow(0x1, "no");
4959 %}
4960 %}
4961
4962 // Comparison Code, unsigned compare. Used by FP also, with
4963 // C2 (unordered) turned into GT or LT already. The other bits
4964 // C0 and C3 are turned into Carry & Zero flags.
4965 operand cmpOpU() %{
4966 match(Bool);
4967
4968 format %{ "" %}
4969 interface(COND_INTER) %{
4970 equal(0x4, "e");
4971 not_equal(0x5, "ne");
4972 less(0x2, "b");
4973 greater_equal(0x3, "nb");
4974 less_equal(0x6, "be");
4975 greater(0x7, "nbe");
4976 overflow(0x0, "o");
4977 no_overflow(0x1, "no");
4978 %}
4979 %}
4980
4981 // Floating comparisons that don't require any fixup for the unordered case
4982 operand cmpOpUCF() %{
4983 match(Bool);
4984 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4985 n->as_Bool()->_test._test == BoolTest::ge ||
4986 n->as_Bool()->_test._test == BoolTest::le ||
4987 n->as_Bool()->_test._test == BoolTest::gt);
4988 format %{ "" %}
4989 interface(COND_INTER) %{
4990 equal(0x4, "e");
4991 not_equal(0x5, "ne");
4992 less(0x2, "b");
4993 greater_equal(0x3, "nb");
4994 less_equal(0x6, "be");
4995 greater(0x7, "nbe");
4996 overflow(0x0, "o");
4997 no_overflow(0x1, "no");
4998 %}
4999 %}
5000
5001
5002 // Floating comparisons that can be fixed up with extra conditional jumps
5003 operand cmpOpUCF2() %{
5004 match(Bool);
5005 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5006 n->as_Bool()->_test._test == BoolTest::eq);
5007 format %{ "" %}
5008 interface(COND_INTER) %{
5009 equal(0x4, "e");
5010 not_equal(0x5, "ne");
5011 less(0x2, "b");
5012 greater_equal(0x3, "nb");
5013 less_equal(0x6, "be");
5014 greater(0x7, "nbe");
5015 overflow(0x0, "o");
5016 no_overflow(0x1, "no");
5017 %}
5018 %}
5019
5020 // Comparison Code for FP conditional move
5021 operand cmpOp_fcmov() %{
5022 match(Bool);
5023
5024 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5025 n->as_Bool()->_test._test != BoolTest::no_overflow);
5026 format %{ "" %}
5027 interface(COND_INTER) %{
5028 equal (0x0C8);
5029 not_equal (0x1C8);
5030 less (0x0C0);
5031 greater_equal(0x1C0);
5032 less_equal (0x0D0);
5033 greater (0x1D0);
5034 overflow(0x0, "o"); // not really supported by the instruction
5035 no_overflow(0x1, "no"); // not really supported by the instruction
5036 %}
5037 %}
5038
5039 // Comparision Code used in long compares
5040 operand cmpOp_commute() %{
5041 match(Bool);
5042
5043 format %{ "" %}
5044 interface(COND_INTER) %{
5045 equal(0x4, "e");
5046 not_equal(0x5, "ne");
5047 less(0xF, "g");
5048 greater_equal(0xE, "le");
5049 less_equal(0xD, "ge");
5050 greater(0xC, "l");
5051 overflow(0x0, "o");
5052 no_overflow(0x1, "no");
5053 %}
5054 %}
5055
5056 //----------OPERAND CLASSES----------------------------------------------------
5057 // Operand Classes are groups of operands that are used as to simplify
5058 // instruction definitions by not requiring the AD writer to specify separate
5059 // instructions for every form of operand when the instruction accepts
5060 // multiple operand types with the same basic encoding and format. The classic
5061 // case of this is memory operands.
5062
5063 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5064 indIndex, indIndexScale, indIndexScaleOffset);
5065
5066 // Long memory operations are encoded in 2 instructions and a +4 offset.
5067 // This means some kind of offset is always required and you cannot use
5068 // an oop as the offset (done when working on static globals).
5069 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5070 indIndex, indIndexScale, indIndexScaleOffset);
5071
5072
5073 //----------PIPELINE-----------------------------------------------------------
5074 // Rules which define the behavior of the target architectures pipeline.
5075 pipeline %{
5076
5077 //----------ATTRIBUTES---------------------------------------------------------
5078 attributes %{
5079 variable_size_instructions; // Fixed size instructions
5080 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5081 instruction_unit_size = 1; // An instruction is 1 bytes long
5082 instruction_fetch_unit_size = 16; // The processor fetches one line
5083 instruction_fetch_units = 1; // of 16 bytes
5084
5085 // List of nop instructions
5086 nops( MachNop );
5087 %}
5088
5089 //----------RESOURCES----------------------------------------------------------
5090 // Resources are the functional units available to the machine
5091
5092 // Generic P2/P3 pipeline
5093 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5094 // 3 instructions decoded per cycle.
5095 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5096 // 2 ALU op, only ALU0 handles mul/div instructions.
5097 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5098 MS0, MS1, MEM = MS0 | MS1,
5099 BR, FPU,
5100 ALU0, ALU1, ALU = ALU0 | ALU1 );
5101
5102 //----------PIPELINE DESCRIPTION-----------------------------------------------
5103 // Pipeline Description specifies the stages in the machine's pipeline
5104
5105 // Generic P2/P3 pipeline
5106 pipe_desc(S0, S1, S2, S3, S4, S5);
5107
5108 //----------PIPELINE CLASSES---------------------------------------------------
5109 // Pipeline Classes describe the stages in which input and output are
5110 // referenced by the hardware pipeline.
5111
5112 // Naming convention: ialu or fpu
5113 // Then: _reg
5114 // Then: _reg if there is a 2nd register
5115 // Then: _long if it's a pair of instructions implementing a long
5116 // Then: _fat if it requires the big decoder
5117 // Or: _mem if it requires the big decoder and a memory unit.
5118
5119 // Integer ALU reg operation
5120 pipe_class ialu_reg(rRegI dst) %{
5121 single_instruction;
5122 dst : S4(write);
5123 dst : S3(read);
5124 DECODE : S0; // any decoder
5125 ALU : S3; // any alu
5126 %}
5127
5128 // Long ALU reg operation
5129 pipe_class ialu_reg_long(eRegL dst) %{
5130 instruction_count(2);
5131 dst : S4(write);
5132 dst : S3(read);
5133 DECODE : S0(2); // any 2 decoders
5134 ALU : S3(2); // both alus
5135 %}
5136
5137 // Integer ALU reg operation using big decoder
5138 pipe_class ialu_reg_fat(rRegI dst) %{
5139 single_instruction;
5140 dst : S4(write);
5141 dst : S3(read);
5142 D0 : S0; // big decoder only
5143 ALU : S3; // any alu
5144 %}
5145
5146 // Long ALU reg operation using big decoder
5147 pipe_class ialu_reg_long_fat(eRegL dst) %{
5148 instruction_count(2);
5149 dst : S4(write);
5150 dst : S3(read);
5151 D0 : S0(2); // big decoder only; twice
5152 ALU : S3(2); // any 2 alus
5153 %}
5154
5155 // Integer ALU reg-reg operation
5156 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5157 single_instruction;
5158 dst : S4(write);
5159 src : S3(read);
5160 DECODE : S0; // any decoder
5161 ALU : S3; // any alu
5162 %}
5163
5164 // Long ALU reg-reg operation
5165 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5166 instruction_count(2);
5167 dst : S4(write);
5168 src : S3(read);
5169 DECODE : S0(2); // any 2 decoders
5170 ALU : S3(2); // both alus
5171 %}
5172
5173 // Integer ALU reg-reg operation
5174 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5175 single_instruction;
5176 dst : S4(write);
5177 src : S3(read);
5178 D0 : S0; // big decoder only
5179 ALU : S3; // any alu
5180 %}
5181
5182 // Long ALU reg-reg operation
5183 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5184 instruction_count(2);
5185 dst : S4(write);
5186 src : S3(read);
5187 D0 : S0(2); // big decoder only; twice
5188 ALU : S3(2); // both alus
5189 %}
5190
5191 // Integer ALU reg-mem operation
5192 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5193 single_instruction;
5194 dst : S5(write);
5195 mem : S3(read);
5196 D0 : S0; // big decoder only
5197 ALU : S4; // any alu
5198 MEM : S3; // any mem
5199 %}
5200
5201 // Long ALU reg-mem operation
5202 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5203 instruction_count(2);
5204 dst : S5(write);
5205 mem : S3(read);
5206 D0 : S0(2); // big decoder only; twice
5207 ALU : S4(2); // any 2 alus
5208 MEM : S3(2); // both mems
5209 %}
5210
5211 // Integer mem operation (prefetch)
5212 pipe_class ialu_mem(memory mem)
5213 %{
5214 single_instruction;
5215 mem : S3(read);
5216 D0 : S0; // big decoder only
5217 MEM : S3; // any mem
5218 %}
5219
5220 // Integer Store to Memory
5221 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5222 single_instruction;
5223 mem : S3(read);
5224 src : S5(read);
5225 D0 : S0; // big decoder only
5226 ALU : S4; // any alu
5227 MEM : S3;
5228 %}
5229
5230 // Long Store to Memory
5231 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5232 instruction_count(2);
5233 mem : S3(read);
5234 src : S5(read);
5235 D0 : S0(2); // big decoder only; twice
5236 ALU : S4(2); // any 2 alus
5237 MEM : S3(2); // Both mems
5238 %}
5239
5240 // Integer Store to Memory
5241 pipe_class ialu_mem_imm(memory mem) %{
5242 single_instruction;
5243 mem : S3(read);
5244 D0 : S0; // big decoder only
5245 ALU : S4; // any alu
5246 MEM : S3;
5247 %}
5248
5249 // Integer ALU0 reg-reg operation
5250 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5251 single_instruction;
5252 dst : S4(write);
5253 src : S3(read);
5254 D0 : S0; // Big decoder only
5255 ALU0 : S3; // only alu0
5256 %}
5257
5258 // Integer ALU0 reg-mem operation
5259 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5260 single_instruction;
5261 dst : S5(write);
5262 mem : S3(read);
5263 D0 : S0; // big decoder only
5264 ALU0 : S4; // ALU0 only
5265 MEM : S3; // any mem
5266 %}
5267
5268 // Integer ALU reg-reg operation
5269 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5270 single_instruction;
5271 cr : S4(write);
5272 src1 : S3(read);
5273 src2 : S3(read);
5274 DECODE : S0; // any decoder
5275 ALU : S3; // any alu
5276 %}
5277
5278 // Integer ALU reg-imm operation
5279 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5280 single_instruction;
5281 cr : S4(write);
5282 src1 : S3(read);
5283 DECODE : S0; // any decoder
5284 ALU : S3; // any alu
5285 %}
5286
5287 // Integer ALU reg-mem operation
5288 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5289 single_instruction;
5290 cr : S4(write);
5291 src1 : S3(read);
5292 src2 : S3(read);
5293 D0 : S0; // big decoder only
5294 ALU : S4; // any alu
5295 MEM : S3;
5296 %}
5297
5298 // Conditional move reg-reg
5299 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5300 instruction_count(4);
5301 y : S4(read);
5302 q : S3(read);
5303 p : S3(read);
5304 DECODE : S0(4); // any decoder
5305 %}
5306
5307 // Conditional move reg-reg
5308 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5309 single_instruction;
5310 dst : S4(write);
5311 src : S3(read);
5312 cr : S3(read);
5313 DECODE : S0; // any decoder
5314 %}
5315
5316 // Conditional move reg-mem
5317 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5318 single_instruction;
5319 dst : S4(write);
5320 src : S3(read);
5321 cr : S3(read);
5322 DECODE : S0; // any decoder
5323 MEM : S3;
5324 %}
5325
5326 // Conditional move reg-reg long
5327 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5328 single_instruction;
5329 dst : S4(write);
5330 src : S3(read);
5331 cr : S3(read);
5332 DECODE : S0(2); // any 2 decoders
5333 %}
5334
5335 // Conditional move double reg-reg
5336 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5337 single_instruction;
5338 dst : S4(write);
5339 src : S3(read);
5340 cr : S3(read);
5341 DECODE : S0; // any decoder
5342 %}
5343
5344 // Float reg-reg operation
5345 pipe_class fpu_reg(regDPR dst) %{
5346 instruction_count(2);
5347 dst : S3(read);
5348 DECODE : S0(2); // any 2 decoders
5349 FPU : S3;
5350 %}
5351
5352 // Float reg-reg operation
5353 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5354 instruction_count(2);
5355 dst : S4(write);
5356 src : S3(read);
5357 DECODE : S0(2); // any 2 decoders
5358 FPU : S3;
5359 %}
5360
5361 // Float reg-reg operation
5362 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5363 instruction_count(3);
5364 dst : S4(write);
5365 src1 : S3(read);
5366 src2 : S3(read);
5367 DECODE : S0(3); // any 3 decoders
5368 FPU : S3(2);
5369 %}
5370
5371 // Float reg-reg operation
5372 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5373 instruction_count(4);
5374 dst : S4(write);
5375 src1 : S3(read);
5376 src2 : S3(read);
5377 src3 : S3(read);
5378 DECODE : S0(4); // any 3 decoders
5379 FPU : S3(2);
5380 %}
5381
5382 // Float reg-reg operation
5383 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5384 instruction_count(4);
5385 dst : S4(write);
5386 src1 : S3(read);
5387 src2 : S3(read);
5388 src3 : S3(read);
5389 DECODE : S1(3); // any 3 decoders
5390 D0 : S0; // Big decoder only
5391 FPU : S3(2);
5392 MEM : S3;
5393 %}
5394
5395 // Float reg-mem operation
5396 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5397 instruction_count(2);
5398 dst : S5(write);
5399 mem : S3(read);
5400 D0 : S0; // big decoder only
5401 DECODE : S1; // any decoder for FPU POP
5402 FPU : S4;
5403 MEM : S3; // any mem
5404 %}
5405
5406 // Float reg-mem operation
5407 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5408 instruction_count(3);
5409 dst : S5(write);
5410 src1 : S3(read);
5411 mem : S3(read);
5412 D0 : S0; // big decoder only
5413 DECODE : S1(2); // any decoder for FPU POP
5414 FPU : S4;
5415 MEM : S3; // any mem
5416 %}
5417
5418 // Float mem-reg operation
5419 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5420 instruction_count(2);
5421 src : S5(read);
5422 mem : S3(read);
5423 DECODE : S0; // any decoder for FPU PUSH
5424 D0 : S1; // big decoder only
5425 FPU : S4;
5426 MEM : S3; // any mem
5427 %}
5428
5429 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5430 instruction_count(3);
5431 src1 : S3(read);
5432 src2 : S3(read);
5433 mem : S3(read);
5434 DECODE : S0(2); // any decoder for FPU PUSH
5435 D0 : S1; // big decoder only
5436 FPU : S4;
5437 MEM : S3; // any mem
5438 %}
5439
5440 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5441 instruction_count(3);
5442 src1 : S3(read);
5443 src2 : S3(read);
5444 mem : S4(read);
5445 DECODE : S0; // any decoder for FPU PUSH
5446 D0 : S0(2); // big decoder only
5447 FPU : S4;
5448 MEM : S3(2); // any mem
5449 %}
5450
5451 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5452 instruction_count(2);
5453 src1 : S3(read);
5454 dst : S4(read);
5455 D0 : S0(2); // big decoder only
5456 MEM : S3(2); // any mem
5457 %}
5458
5459 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5460 instruction_count(3);
5461 src1 : S3(read);
5462 src2 : S3(read);
5463 dst : S4(read);
5464 D0 : S0(3); // big decoder only
5465 FPU : S4;
5466 MEM : S3(3); // any mem
5467 %}
5468
5469 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5470 instruction_count(3);
5471 src1 : S4(read);
5472 mem : S4(read);
5473 DECODE : S0; // any decoder for FPU PUSH
5474 D0 : S0(2); // big decoder only
5475 FPU : S4;
5476 MEM : S3(2); // any mem
5477 %}
5478
5479 // Float load constant
5480 pipe_class fpu_reg_con(regDPR dst) %{
5481 instruction_count(2);
5482 dst : S5(write);
5483 D0 : S0; // big decoder only for the load
5484 DECODE : S1; // any decoder for FPU POP
5485 FPU : S4;
5486 MEM : S3; // any mem
5487 %}
5488
5489 // Float load constant
5490 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5491 instruction_count(3);
5492 dst : S5(write);
5493 src : S3(read);
5494 D0 : S0; // big decoder only for the load
5495 DECODE : S1(2); // any decoder for FPU POP
5496 FPU : S4;
5497 MEM : S3; // any mem
5498 %}
5499
5500 // UnConditional branch
5501 pipe_class pipe_jmp( label labl ) %{
5502 single_instruction;
5503 BR : S3;
5504 %}
5505
5506 // Conditional branch
5507 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5508 single_instruction;
5509 cr : S1(read);
5510 BR : S3;
5511 %}
5512
5513 // Allocation idiom
5514 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5515 instruction_count(1); force_serialization;
5516 fixed_latency(6);
5517 heap_ptr : S3(read);
5518 DECODE : S0(3);
5519 D0 : S2;
5520 MEM : S3;
5521 ALU : S3(2);
5522 dst : S5(write);
5523 BR : S5;
5524 %}
5525
5526 // Generic big/slow expanded idiom
5527 pipe_class pipe_slow( ) %{
5528 instruction_count(10); multiple_bundles; force_serialization;
5529 fixed_latency(100);
5530 D0 : S0(2);
5531 MEM : S3(2);
5532 %}
5533
5534 // The real do-nothing guy
5535 pipe_class empty( ) %{
5536 instruction_count(0);
5537 %}
5538
5539 // Define the class for the Nop node
5540 define %{
5541 MachNop = empty;
5542 %}
5543
5544 %}
5545
5546 //----------INSTRUCTIONS-------------------------------------------------------
5547 //
5548 // match -- States which machine-independent subtree may be replaced
5549 // by this instruction.
5550 // ins_cost -- The estimated cost of this instruction is used by instruction
5551 // selection to identify a minimum cost tree of machine
5552 // instructions that matches a tree of machine-independent
5553 // instructions.
5554 // format -- A string providing the disassembly for this instruction.
5555 // The value of an instruction's operand may be inserted
5556 // by referring to it with a '$' prefix.
5557 // opcode -- Three instruction opcodes may be provided. These are referred
5558 // to within an encode class as $primary, $secondary, and $tertiary
5559 // respectively. The primary opcode is commonly used to
5560 // indicate the type of machine instruction, while secondary
5561 // and tertiary are often used for prefix options or addressing
5562 // modes.
5563 // ins_encode -- A list of encode classes with parameters. The encode class
5564 // name must have been defined in an 'enc_class' specification
5565 // in the encode section of the architecture description.
5566
5567 //----------BSWAP-Instruction--------------------------------------------------
5568 instruct bytes_reverse_int(rRegI dst) %{
5569 match(Set dst (ReverseBytesI dst));
5570
5571 format %{ "BSWAP $dst" %}
5572 opcode(0x0F, 0xC8);
5573 ins_encode( OpcP, OpcSReg(dst) );
5574 ins_pipe( ialu_reg );
5575 %}
5576
5577 instruct bytes_reverse_long(eRegL dst) %{
5578 match(Set dst (ReverseBytesL dst));
5579
5580 format %{ "BSWAP $dst.lo\n\t"
5581 "BSWAP $dst.hi\n\t"
5582 "XCHG $dst.lo $dst.hi" %}
5583
5584 ins_cost(125);
5585 ins_encode( bswap_long_bytes(dst) );
5586 ins_pipe( ialu_reg_reg);
5587 %}
5588
5589 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5590 match(Set dst (ReverseBytesUS dst));
5591 effect(KILL cr);
5592
5593 format %{ "BSWAP $dst\n\t"
5594 "SHR $dst,16\n\t" %}
5595 ins_encode %{
5596 __ bswapl($dst$$Register);
5597 __ shrl($dst$$Register, 16);
5598 %}
5599 ins_pipe( ialu_reg );
5600 %}
5601
5602 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5603 match(Set dst (ReverseBytesS dst));
5604 effect(KILL cr);
5605
5606 format %{ "BSWAP $dst\n\t"
5607 "SAR $dst,16\n\t" %}
5608 ins_encode %{
5609 __ bswapl($dst$$Register);
5610 __ sarl($dst$$Register, 16);
5611 %}
5612 ins_pipe( ialu_reg );
5613 %}
5614
5615
5616 //---------- Zeros Count Instructions ------------------------------------------
5617
5618 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5619 predicate(UseCountLeadingZerosInstruction);
5620 match(Set dst (CountLeadingZerosI src));
5621 effect(KILL cr);
5622
5623 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5624 ins_encode %{
5625 __ lzcntl($dst$$Register, $src$$Register);
5626 %}
5627 ins_pipe(ialu_reg);
5628 %}
5629
5630 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5631 predicate(!UseCountLeadingZerosInstruction);
5632 match(Set dst (CountLeadingZerosI src));
5633 effect(KILL cr);
5634
5635 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5636 "JNZ skip\n\t"
5637 "MOV $dst, -1\n"
5638 "skip:\n\t"
5639 "NEG $dst\n\t"
5640 "ADD $dst, 31" %}
5641 ins_encode %{
5642 Register Rdst = $dst$$Register;
5643 Register Rsrc = $src$$Register;
5644 Label skip;
5645 __ bsrl(Rdst, Rsrc);
5646 __ jccb(Assembler::notZero, skip);
5647 __ movl(Rdst, -1);
5648 __ bind(skip);
5649 __ negl(Rdst);
5650 __ addl(Rdst, BitsPerInt - 1);
5651 %}
5652 ins_pipe(ialu_reg);
5653 %}
5654
5655 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5656 predicate(UseCountLeadingZerosInstruction);
5657 match(Set dst (CountLeadingZerosL src));
5658 effect(TEMP dst, KILL cr);
5659
5660 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5661 "JNC done\n\t"
5662 "LZCNT $dst, $src.lo\n\t"
5663 "ADD $dst, 32\n"
5664 "done:" %}
5665 ins_encode %{
5666 Register Rdst = $dst$$Register;
5667 Register Rsrc = $src$$Register;
5668 Label done;
5669 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5670 __ jccb(Assembler::carryClear, done);
5671 __ lzcntl(Rdst, Rsrc);
5672 __ addl(Rdst, BitsPerInt);
5673 __ bind(done);
5674 %}
5675 ins_pipe(ialu_reg);
5676 %}
5677
5678 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5679 predicate(!UseCountLeadingZerosInstruction);
5680 match(Set dst (CountLeadingZerosL src));
5681 effect(TEMP dst, KILL cr);
5682
5683 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5684 "JZ msw_is_zero\n\t"
5685 "ADD $dst, 32\n\t"
5686 "JMP not_zero\n"
5687 "msw_is_zero:\n\t"
5688 "BSR $dst, $src.lo\n\t"
5689 "JNZ not_zero\n\t"
5690 "MOV $dst, -1\n"
5691 "not_zero:\n\t"
5692 "NEG $dst\n\t"
5693 "ADD $dst, 63\n" %}
5694 ins_encode %{
5695 Register Rdst = $dst$$Register;
5696 Register Rsrc = $src$$Register;
5697 Label msw_is_zero;
5698 Label not_zero;
5699 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5700 __ jccb(Assembler::zero, msw_is_zero);
5701 __ addl(Rdst, BitsPerInt);
5702 __ jmpb(not_zero);
5703 __ bind(msw_is_zero);
5704 __ bsrl(Rdst, Rsrc);
5705 __ jccb(Assembler::notZero, not_zero);
5706 __ movl(Rdst, -1);
5707 __ bind(not_zero);
5708 __ negl(Rdst);
5709 __ addl(Rdst, BitsPerLong - 1);
5710 %}
5711 ins_pipe(ialu_reg);
5712 %}
5713
5714 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5715 predicate(UseCountTrailingZerosInstruction);
5716 match(Set dst (CountTrailingZerosI src));
5717 effect(KILL cr);
5718
5719 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)\n\t" %}
5720 ins_encode %{
5721 __ tzcntl($dst$$Register, $src$$Register);
5722 %}
5723 ins_pipe(ialu_reg);
5724 %}
5725
5726 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5727 predicate(!UseCountTrailingZerosInstruction);
5728 match(Set dst (CountTrailingZerosI src));
5729 effect(KILL cr);
5730
5731 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5732 "JNZ done\n\t"
5733 "MOV $dst, 32\n"
5734 "done:" %}
5735 ins_encode %{
5736 Register Rdst = $dst$$Register;
5737 Label done;
5738 __ bsfl(Rdst, $src$$Register);
5739 __ jccb(Assembler::notZero, done);
5740 __ movl(Rdst, BitsPerInt);
5741 __ bind(done);
5742 %}
5743 ins_pipe(ialu_reg);
5744 %}
5745
5746 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5747 predicate(UseCountTrailingZerosInstruction);
5748 match(Set dst (CountTrailingZerosL src));
5749 effect(TEMP dst, KILL cr);
5750
5751 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5752 "JNC done\n\t"
5753 "TZCNT $dst, $src.hi\n\t"
5754 "ADD $dst, 32\n"
5755 "done:" %}
5756 ins_encode %{
5757 Register Rdst = $dst$$Register;
5758 Register Rsrc = $src$$Register;
5759 Label done;
5760 __ tzcntl(Rdst, Rsrc);
5761 __ jccb(Assembler::carryClear, done);
5762 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5763 __ addl(Rdst, BitsPerInt);
5764 __ bind(done);
5765 %}
5766 ins_pipe(ialu_reg);
5767 %}
5768
5769 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5770 predicate(!UseCountTrailingZerosInstruction);
5771 match(Set dst (CountTrailingZerosL src));
5772 effect(TEMP dst, KILL cr);
5773
5774 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5775 "JNZ done\n\t"
5776 "BSF $dst, $src.hi\n\t"
5777 "JNZ msw_not_zero\n\t"
5778 "MOV $dst, 32\n"
5779 "msw_not_zero:\n\t"
5780 "ADD $dst, 32\n"
5781 "done:" %}
5782 ins_encode %{
5783 Register Rdst = $dst$$Register;
5784 Register Rsrc = $src$$Register;
5785 Label msw_not_zero;
5786 Label done;
5787 __ bsfl(Rdst, Rsrc);
5788 __ jccb(Assembler::notZero, done);
5789 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5790 __ jccb(Assembler::notZero, msw_not_zero);
5791 __ movl(Rdst, BitsPerInt);
5792 __ bind(msw_not_zero);
5793 __ addl(Rdst, BitsPerInt);
5794 __ bind(done);
5795 %}
5796 ins_pipe(ialu_reg);
5797 %}
5798
5799
5800 //---------- Population Count Instructions -------------------------------------
5801
5802 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5803 predicate(UsePopCountInstruction);
5804 match(Set dst (PopCountI src));
5805 effect(KILL cr);
5806
5807 format %{ "POPCNT $dst, $src" %}
5808 ins_encode %{
5809 __ popcntl($dst$$Register, $src$$Register);
5810 %}
5811 ins_pipe(ialu_reg);
5812 %}
5813
5814 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5815 predicate(UsePopCountInstruction);
5816 match(Set dst (PopCountI (LoadI mem)));
5817 effect(KILL cr);
5818
5819 format %{ "POPCNT $dst, $mem" %}
5820 ins_encode %{
5821 __ popcntl($dst$$Register, $mem$$Address);
5822 %}
5823 ins_pipe(ialu_reg);
5824 %}
5825
5826 // Note: Long.bitCount(long) returns an int.
5827 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5828 predicate(UsePopCountInstruction);
5829 match(Set dst (PopCountL src));
5830 effect(KILL cr, TEMP tmp, TEMP dst);
5831
5832 format %{ "POPCNT $dst, $src.lo\n\t"
5833 "POPCNT $tmp, $src.hi\n\t"
5834 "ADD $dst, $tmp" %}
5835 ins_encode %{
5836 __ popcntl($dst$$Register, $src$$Register);
5837 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5838 __ addl($dst$$Register, $tmp$$Register);
5839 %}
5840 ins_pipe(ialu_reg);
5841 %}
5842
5843 // Note: Long.bitCount(long) returns an int.
5844 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5845 predicate(UsePopCountInstruction);
5846 match(Set dst (PopCountL (LoadL mem)));
5847 effect(KILL cr, TEMP tmp, TEMP dst);
5848
5849 format %{ "POPCNT $dst, $mem\n\t"
5850 "POPCNT $tmp, $mem+4\n\t"
5851 "ADD $dst, $tmp" %}
5852 ins_encode %{
5853 //__ popcntl($dst$$Register, $mem$$Address$$first);
5854 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5855 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5856 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5857 __ addl($dst$$Register, $tmp$$Register);
5858 %}
5859 ins_pipe(ialu_reg);
5860 %}
5861
5862
5863 //----------Load/Store/Move Instructions---------------------------------------
5864 //----------Load Instructions--------------------------------------------------
5865 // Load Byte (8bit signed)
5866 instruct loadB(xRegI dst, memory mem) %{
5867 match(Set dst (LoadB mem));
5868
5869 ins_cost(125);
5870 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5871
5872 ins_encode %{
5873 __ movsbl($dst$$Register, $mem$$Address);
5874 %}
5875
5876 ins_pipe(ialu_reg_mem);
5877 %}
5878
5879 // Load Byte (8bit signed) into Long Register
5880 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5881 match(Set dst (ConvI2L (LoadB mem)));
5882 effect(KILL cr);
5883
5884 ins_cost(375);
5885 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5886 "MOV $dst.hi,$dst.lo\n\t"
5887 "SAR $dst.hi,7" %}
5888
5889 ins_encode %{
5890 __ movsbl($dst$$Register, $mem$$Address);
5891 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5892 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5893 %}
5894
5895 ins_pipe(ialu_reg_mem);
5896 %}
5897
5898 // Load Unsigned Byte (8bit UNsigned)
5899 instruct loadUB(xRegI dst, memory mem) %{
5900 match(Set dst (LoadUB mem));
5901
5902 ins_cost(125);
5903 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5904
5905 ins_encode %{
5906 __ movzbl($dst$$Register, $mem$$Address);
5907 %}
5908
5909 ins_pipe(ialu_reg_mem);
5910 %}
5911
5912 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5913 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5914 match(Set dst (ConvI2L (LoadUB mem)));
5915 effect(KILL cr);
5916
5917 ins_cost(250);
5918 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5919 "XOR $dst.hi,$dst.hi" %}
5920
5921 ins_encode %{
5922 Register Rdst = $dst$$Register;
5923 __ movzbl(Rdst, $mem$$Address);
5924 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5925 %}
5926
5927 ins_pipe(ialu_reg_mem);
5928 %}
5929
5930 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5931 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5932 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5933 effect(KILL cr);
5934
5935 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5936 "XOR $dst.hi,$dst.hi\n\t"
5937 "AND $dst.lo,$mask" %}
5938 ins_encode %{
5939 Register Rdst = $dst$$Register;
5940 __ movzbl(Rdst, $mem$$Address);
5941 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5942 __ andl(Rdst, $mask$$constant);
5943 %}
5944 ins_pipe(ialu_reg_mem);
5945 %}
5946
5947 // Load Short (16bit signed)
5948 instruct loadS(rRegI dst, memory mem) %{
5949 match(Set dst (LoadS mem));
5950
5951 ins_cost(125);
5952 format %{ "MOVSX $dst,$mem\t# short" %}
5953
5954 ins_encode %{
5955 __ movswl($dst$$Register, $mem$$Address);
5956 %}
5957
5958 ins_pipe(ialu_reg_mem);
5959 %}
5960
5961 // Load Short (16 bit signed) to Byte (8 bit signed)
5962 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5963 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5964
5965 ins_cost(125);
5966 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5967 ins_encode %{
5968 __ movsbl($dst$$Register, $mem$$Address);
5969 %}
5970 ins_pipe(ialu_reg_mem);
5971 %}
5972
5973 // Load Short (16bit signed) into Long Register
5974 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5975 match(Set dst (ConvI2L (LoadS mem)));
5976 effect(KILL cr);
5977
5978 ins_cost(375);
5979 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5980 "MOV $dst.hi,$dst.lo\n\t"
5981 "SAR $dst.hi,15" %}
5982
5983 ins_encode %{
5984 __ movswl($dst$$Register, $mem$$Address);
5985 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5986 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5987 %}
5988
5989 ins_pipe(ialu_reg_mem);
5990 %}
5991
5992 // Load Unsigned Short/Char (16bit unsigned)
5993 instruct loadUS(rRegI dst, memory mem) %{
5994 match(Set dst (LoadUS mem));
5995
5996 ins_cost(125);
5997 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5998
5999 ins_encode %{
6000 __ movzwl($dst$$Register, $mem$$Address);
6001 %}
6002
6003 ins_pipe(ialu_reg_mem);
6004 %}
6005
6006 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6007 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6008 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6009
6010 ins_cost(125);
6011 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6012 ins_encode %{
6013 __ movsbl($dst$$Register, $mem$$Address);
6014 %}
6015 ins_pipe(ialu_reg_mem);
6016 %}
6017
6018 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6019 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6020 match(Set dst (ConvI2L (LoadUS mem)));
6021 effect(KILL cr);
6022
6023 ins_cost(250);
6024 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6025 "XOR $dst.hi,$dst.hi" %}
6026
6027 ins_encode %{
6028 __ movzwl($dst$$Register, $mem$$Address);
6029 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6030 %}
6031
6032 ins_pipe(ialu_reg_mem);
6033 %}
6034
6035 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6036 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6037 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6038 effect(KILL cr);
6039
6040 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6041 "XOR $dst.hi,$dst.hi" %}
6042 ins_encode %{
6043 Register Rdst = $dst$$Register;
6044 __ movzbl(Rdst, $mem$$Address);
6045 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6046 %}
6047 ins_pipe(ialu_reg_mem);
6048 %}
6049
6050 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6051 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6052 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6053 effect(KILL cr);
6054
6055 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6056 "XOR $dst.hi,$dst.hi\n\t"
6057 "AND $dst.lo,$mask" %}
6058 ins_encode %{
6059 Register Rdst = $dst$$Register;
6060 __ movzwl(Rdst, $mem$$Address);
6061 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6062 __ andl(Rdst, $mask$$constant);
6063 %}
6064 ins_pipe(ialu_reg_mem);
6065 %}
6066
6067 // Load Integer
6068 instruct loadI(rRegI dst, memory mem) %{
6069 match(Set dst (LoadI mem));
6070
6071 ins_cost(125);
6072 format %{ "MOV $dst,$mem\t# int" %}
6073
6074 ins_encode %{
6075 __ movl($dst$$Register, $mem$$Address);
6076 %}
6077
6078 ins_pipe(ialu_reg_mem);
6079 %}
6080
6081 // Load Integer (32 bit signed) to Byte (8 bit signed)
6082 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6083 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6084
6085 ins_cost(125);
6086 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6087 ins_encode %{
6088 __ movsbl($dst$$Register, $mem$$Address);
6089 %}
6090 ins_pipe(ialu_reg_mem);
6091 %}
6092
6093 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6094 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6095 match(Set dst (AndI (LoadI mem) mask));
6096
6097 ins_cost(125);
6098 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6099 ins_encode %{
6100 __ movzbl($dst$$Register, $mem$$Address);
6101 %}
6102 ins_pipe(ialu_reg_mem);
6103 %}
6104
6105 // Load Integer (32 bit signed) to Short (16 bit signed)
6106 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6107 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6108
6109 ins_cost(125);
6110 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6111 ins_encode %{
6112 __ movswl($dst$$Register, $mem$$Address);
6113 %}
6114 ins_pipe(ialu_reg_mem);
6115 %}
6116
6117 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6118 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6119 match(Set dst (AndI (LoadI mem) mask));
6120
6121 ins_cost(125);
6122 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6123 ins_encode %{
6124 __ movzwl($dst$$Register, $mem$$Address);
6125 %}
6126 ins_pipe(ialu_reg_mem);
6127 %}
6128
6129 // Load Integer into Long Register
6130 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6131 match(Set dst (ConvI2L (LoadI mem)));
6132 effect(KILL cr);
6133
6134 ins_cost(375);
6135 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6136 "MOV $dst.hi,$dst.lo\n\t"
6137 "SAR $dst.hi,31" %}
6138
6139 ins_encode %{
6140 __ movl($dst$$Register, $mem$$Address);
6141 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6142 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6143 %}
6144
6145 ins_pipe(ialu_reg_mem);
6146 %}
6147
6148 // Load Integer with mask 0xFF into Long Register
6149 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6150 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6151 effect(KILL cr);
6152
6153 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6154 "XOR $dst.hi,$dst.hi" %}
6155 ins_encode %{
6156 Register Rdst = $dst$$Register;
6157 __ movzbl(Rdst, $mem$$Address);
6158 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6159 %}
6160 ins_pipe(ialu_reg_mem);
6161 %}
6162
6163 // Load Integer with mask 0xFFFF into Long Register
6164 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6165 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6166 effect(KILL cr);
6167
6168 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6169 "XOR $dst.hi,$dst.hi" %}
6170 ins_encode %{
6171 Register Rdst = $dst$$Register;
6172 __ movzwl(Rdst, $mem$$Address);
6173 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6174 %}
6175 ins_pipe(ialu_reg_mem);
6176 %}
6177
6178 // Load Integer with 31-bit mask into Long Register
6179 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
6180 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6181 effect(KILL cr);
6182
6183 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6184 "XOR $dst.hi,$dst.hi\n\t"
6185 "AND $dst.lo,$mask" %}
6186 ins_encode %{
6187 Register Rdst = $dst$$Register;
6188 __ movl(Rdst, $mem$$Address);
6189 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6190 __ andl(Rdst, $mask$$constant);
6191 %}
6192 ins_pipe(ialu_reg_mem);
6193 %}
6194
6195 // Load Unsigned Integer into Long Register
6196 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6197 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6198 effect(KILL cr);
6199
6200 ins_cost(250);
6201 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6202 "XOR $dst.hi,$dst.hi" %}
6203
6204 ins_encode %{
6205 __ movl($dst$$Register, $mem$$Address);
6206 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6207 %}
6208
6209 ins_pipe(ialu_reg_mem);
6210 %}
6211
6212 // Load Long. Cannot clobber address while loading, so restrict address
6213 // register to ESI
6214 instruct loadL(eRegL dst, load_long_memory mem) %{
6215 predicate(!((LoadLNode*)n)->require_atomic_access());
6216 match(Set dst (LoadL mem));
6217
6218 ins_cost(250);
6219 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6220 "MOV $dst.hi,$mem+4" %}
6221
6222 ins_encode %{
6223 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6224 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6225 __ movl($dst$$Register, Amemlo);
6226 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6227 %}
6228
6229 ins_pipe(ialu_reg_long_mem);
6230 %}
6231
6232 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6233 // then store it down to the stack and reload on the int
6234 // side.
6235 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6236 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6237 match(Set dst (LoadL mem));
6238
6239 ins_cost(200);
6240 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6241 "FISTp $dst" %}
6242 ins_encode(enc_loadL_volatile(mem,dst));
6243 ins_pipe( fpu_reg_mem );
6244 %}
6245
6246 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6247 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6248 match(Set dst (LoadL mem));
6249 effect(TEMP tmp);
6250 ins_cost(180);
6251 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6252 "MOVSD $dst,$tmp" %}
6253 ins_encode %{
6254 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6255 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6256 %}
6257 ins_pipe( pipe_slow );
6258 %}
6259
6260 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6261 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6262 match(Set dst (LoadL mem));
6263 effect(TEMP tmp);
6264 ins_cost(160);
6265 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6266 "MOVD $dst.lo,$tmp\n\t"
6267 "PSRLQ $tmp,32\n\t"
6268 "MOVD $dst.hi,$tmp" %}
6269 ins_encode %{
6270 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6271 __ movdl($dst$$Register, $tmp$$XMMRegister);
6272 __ psrlq($tmp$$XMMRegister, 32);
6273 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6274 %}
6275 ins_pipe( pipe_slow );
6276 %}
6277
6278 // Load Range
6279 instruct loadRange(rRegI dst, memory mem) %{
6280 match(Set dst (LoadRange mem));
6281
6282 ins_cost(125);
6283 format %{ "MOV $dst,$mem" %}
6284 opcode(0x8B);
6285 ins_encode( OpcP, RegMem(dst,mem));
6286 ins_pipe( ialu_reg_mem );
6287 %}
6288
6289
6290 // Load Pointer
6291 instruct loadP(eRegP dst, memory mem) %{
6292 match(Set dst (LoadP mem));
6293
6294 ins_cost(125);
6295 format %{ "MOV $dst,$mem" %}
6296 opcode(0x8B);
6297 ins_encode( OpcP, RegMem(dst,mem));
6298 ins_pipe( ialu_reg_mem );
6299 %}
6300
6301 // Load Klass Pointer
6302 instruct loadKlass(eRegP dst, memory mem) %{
6303 match(Set dst (LoadKlass mem));
6304
6305 ins_cost(125);
6306 format %{ "MOV $dst,$mem" %}
6307 opcode(0x8B);
6308 ins_encode( OpcP, RegMem(dst,mem));
6309 ins_pipe( ialu_reg_mem );
6310 %}
6311
6312 // Load Double
6313 instruct loadDPR(regDPR dst, memory mem) %{
6314 predicate(UseSSE<=1);
6315 match(Set dst (LoadD mem));
6316
6317 ins_cost(150);
6318 format %{ "FLD_D ST,$mem\n\t"
6319 "FSTP $dst" %}
6320 opcode(0xDD); /* DD /0 */
6321 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6322 Pop_Reg_DPR(dst) );
6323 ins_pipe( fpu_reg_mem );
6324 %}
6325
6326 // Load Double to XMM
6327 instruct loadD(regD dst, memory mem) %{
6328 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6329 match(Set dst (LoadD mem));
6330 ins_cost(145);
6331 format %{ "MOVSD $dst,$mem" %}
6332 ins_encode %{
6333 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6334 %}
6335 ins_pipe( pipe_slow );
6336 %}
6337
6338 instruct loadD_partial(regD dst, memory mem) %{
6339 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6340 match(Set dst (LoadD mem));
6341 ins_cost(145);
6342 format %{ "MOVLPD $dst,$mem" %}
6343 ins_encode %{
6344 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6345 %}
6346 ins_pipe( pipe_slow );
6347 %}
6348
6349 // Load to XMM register (single-precision floating point)
6350 // MOVSS instruction
6351 instruct loadF(regF dst, memory mem) %{
6352 predicate(UseSSE>=1);
6353 match(Set dst (LoadF mem));
6354 ins_cost(145);
6355 format %{ "MOVSS $dst,$mem" %}
6356 ins_encode %{
6357 __ movflt ($dst$$XMMRegister, $mem$$Address);
6358 %}
6359 ins_pipe( pipe_slow );
6360 %}
6361
6362 // Load Float
6363 instruct loadFPR(regFPR dst, memory mem) %{
6364 predicate(UseSSE==0);
6365 match(Set dst (LoadF mem));
6366
6367 ins_cost(150);
6368 format %{ "FLD_S ST,$mem\n\t"
6369 "FSTP $dst" %}
6370 opcode(0xD9); /* D9 /0 */
6371 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6372 Pop_Reg_FPR(dst) );
6373 ins_pipe( fpu_reg_mem );
6374 %}
6375
6376 // Load Effective Address
6377 instruct leaP8(eRegP dst, indOffset8 mem) %{
6378 match(Set dst mem);
6379
6380 ins_cost(110);
6381 format %{ "LEA $dst,$mem" %}
6382 opcode(0x8D);
6383 ins_encode( OpcP, RegMem(dst,mem));
6384 ins_pipe( ialu_reg_reg_fat );
6385 %}
6386
6387 instruct leaP32(eRegP dst, indOffset32 mem) %{
6388 match(Set dst mem);
6389
6390 ins_cost(110);
6391 format %{ "LEA $dst,$mem" %}
6392 opcode(0x8D);
6393 ins_encode( OpcP, RegMem(dst,mem));
6394 ins_pipe( ialu_reg_reg_fat );
6395 %}
6396
6397 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6398 match(Set dst mem);
6399
6400 ins_cost(110);
6401 format %{ "LEA $dst,$mem" %}
6402 opcode(0x8D);
6403 ins_encode( OpcP, RegMem(dst,mem));
6404 ins_pipe( ialu_reg_reg_fat );
6405 %}
6406
6407 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6408 match(Set dst mem);
6409
6410 ins_cost(110);
6411 format %{ "LEA $dst,$mem" %}
6412 opcode(0x8D);
6413 ins_encode( OpcP, RegMem(dst,mem));
6414 ins_pipe( ialu_reg_reg_fat );
6415 %}
6416
6417 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6418 match(Set dst mem);
6419
6420 ins_cost(110);
6421 format %{ "LEA $dst,$mem" %}
6422 opcode(0x8D);
6423 ins_encode( OpcP, RegMem(dst,mem));
6424 ins_pipe( ialu_reg_reg_fat );
6425 %}
6426
6427 // Load Constant
6428 instruct loadConI(rRegI dst, immI src) %{
6429 match(Set dst src);
6430
6431 format %{ "MOV $dst,$src" %}
6432 ins_encode( LdImmI(dst, src) );
6433 ins_pipe( ialu_reg_fat );
6434 %}
6435
6436 // Load Constant zero
6437 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6438 match(Set dst src);
6439 effect(KILL cr);
6440
6441 ins_cost(50);
6442 format %{ "XOR $dst,$dst" %}
6443 opcode(0x33); /* + rd */
6444 ins_encode( OpcP, RegReg( dst, dst ) );
6445 ins_pipe( ialu_reg );
6446 %}
6447
6448 instruct loadConP(eRegP dst, immP src) %{
6449 match(Set dst src);
6450
6451 format %{ "MOV $dst,$src" %}
6452 opcode(0xB8); /* + rd */
6453 ins_encode( LdImmP(dst, src) );
6454 ins_pipe( ialu_reg_fat );
6455 %}
6456
6457 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6458 match(Set dst src);
6459 effect(KILL cr);
6460 ins_cost(200);
6461 format %{ "MOV $dst.lo,$src.lo\n\t"
6462 "MOV $dst.hi,$src.hi" %}
6463 opcode(0xB8);
6464 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6465 ins_pipe( ialu_reg_long_fat );
6466 %}
6467
6468 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6469 match(Set dst src);
6470 effect(KILL cr);
6471 ins_cost(150);
6472 format %{ "XOR $dst.lo,$dst.lo\n\t"
6473 "XOR $dst.hi,$dst.hi" %}
6474 opcode(0x33,0x33);
6475 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6476 ins_pipe( ialu_reg_long );
6477 %}
6478
6479 // The instruction usage is guarded by predicate in operand immFPR().
6480 instruct loadConFPR(regFPR dst, immFPR con) %{
6481 match(Set dst con);
6482 ins_cost(125);
6483 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6484 "FSTP $dst" %}
6485 ins_encode %{
6486 __ fld_s($constantaddress($con));
6487 __ fstp_d($dst$$reg);
6488 %}
6489 ins_pipe(fpu_reg_con);
6490 %}
6491
6492 // The instruction usage is guarded by predicate in operand immFPR0().
6493 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6494 match(Set dst con);
6495 ins_cost(125);
6496 format %{ "FLDZ ST\n\t"
6497 "FSTP $dst" %}
6498 ins_encode %{
6499 __ fldz();
6500 __ fstp_d($dst$$reg);
6501 %}
6502 ins_pipe(fpu_reg_con);
6503 %}
6504
6505 // The instruction usage is guarded by predicate in operand immFPR1().
6506 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6507 match(Set dst con);
6508 ins_cost(125);
6509 format %{ "FLD1 ST\n\t"
6510 "FSTP $dst" %}
6511 ins_encode %{
6512 __ fld1();
6513 __ fstp_d($dst$$reg);
6514 %}
6515 ins_pipe(fpu_reg_con);
6516 %}
6517
6518 // The instruction usage is guarded by predicate in operand immF().
6519 instruct loadConF(regF dst, immF con) %{
6520 match(Set dst con);
6521 ins_cost(125);
6522 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6523 ins_encode %{
6524 __ movflt($dst$$XMMRegister, $constantaddress($con));
6525 %}
6526 ins_pipe(pipe_slow);
6527 %}
6528
6529 // The instruction usage is guarded by predicate in operand immF0().
6530 instruct loadConF0(regF dst, immF0 src) %{
6531 match(Set dst src);
6532 ins_cost(100);
6533 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6534 ins_encode %{
6535 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6536 %}
6537 ins_pipe(pipe_slow);
6538 %}
6539
6540 // The instruction usage is guarded by predicate in operand immDPR().
6541 instruct loadConDPR(regDPR dst, immDPR con) %{
6542 match(Set dst con);
6543 ins_cost(125);
6544
6545 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6546 "FSTP $dst" %}
6547 ins_encode %{
6548 __ fld_d($constantaddress($con));
6549 __ fstp_d($dst$$reg);
6550 %}
6551 ins_pipe(fpu_reg_con);
6552 %}
6553
6554 // The instruction usage is guarded by predicate in operand immDPR0().
6555 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6556 match(Set dst con);
6557 ins_cost(125);
6558
6559 format %{ "FLDZ ST\n\t"
6560 "FSTP $dst" %}
6561 ins_encode %{
6562 __ fldz();
6563 __ fstp_d($dst$$reg);
6564 %}
6565 ins_pipe(fpu_reg_con);
6566 %}
6567
6568 // The instruction usage is guarded by predicate in operand immDPR1().
6569 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6570 match(Set dst con);
6571 ins_cost(125);
6572
6573 format %{ "FLD1 ST\n\t"
6574 "FSTP $dst" %}
6575 ins_encode %{
6576 __ fld1();
6577 __ fstp_d($dst$$reg);
6578 %}
6579 ins_pipe(fpu_reg_con);
6580 %}
6581
6582 // The instruction usage is guarded by predicate in operand immD().
6583 instruct loadConD(regD dst, immD con) %{
6584 match(Set dst con);
6585 ins_cost(125);
6586 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6587 ins_encode %{
6588 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6589 %}
6590 ins_pipe(pipe_slow);
6591 %}
6592
6593 // The instruction usage is guarded by predicate in operand immD0().
6594 instruct loadConD0(regD dst, immD0 src) %{
6595 match(Set dst src);
6596 ins_cost(100);
6597 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6598 ins_encode %{
6599 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6600 %}
6601 ins_pipe( pipe_slow );
6602 %}
6603
6604 // Load Stack Slot
6605 instruct loadSSI(rRegI dst, stackSlotI src) %{
6606 match(Set dst src);
6607 ins_cost(125);
6608
6609 format %{ "MOV $dst,$src" %}
6610 opcode(0x8B);
6611 ins_encode( OpcP, RegMem(dst,src));
6612 ins_pipe( ialu_reg_mem );
6613 %}
6614
6615 instruct loadSSL(eRegL dst, stackSlotL src) %{
6616 match(Set dst src);
6617
6618 ins_cost(200);
6619 format %{ "MOV $dst,$src.lo\n\t"
6620 "MOV $dst+4,$src.hi" %}
6621 opcode(0x8B, 0x8B);
6622 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6623 ins_pipe( ialu_mem_long_reg );
6624 %}
6625
6626 // Load Stack Slot
6627 instruct loadSSP(eRegP dst, stackSlotP src) %{
6628 match(Set dst src);
6629 ins_cost(125);
6630
6631 format %{ "MOV $dst,$src" %}
6632 opcode(0x8B);
6633 ins_encode( OpcP, RegMem(dst,src));
6634 ins_pipe( ialu_reg_mem );
6635 %}
6636
6637 // Load Stack Slot
6638 instruct loadSSF(regFPR dst, stackSlotF src) %{
6639 match(Set dst src);
6640 ins_cost(125);
6641
6642 format %{ "FLD_S $src\n\t"
6643 "FSTP $dst" %}
6644 opcode(0xD9); /* D9 /0, FLD m32real */
6645 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6646 Pop_Reg_FPR(dst) );
6647 ins_pipe( fpu_reg_mem );
6648 %}
6649
6650 // Load Stack Slot
6651 instruct loadSSD(regDPR dst, stackSlotD src) %{
6652 match(Set dst src);
6653 ins_cost(125);
6654
6655 format %{ "FLD_D $src\n\t"
6656 "FSTP $dst" %}
6657 opcode(0xDD); /* DD /0, FLD m64real */
6658 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6659 Pop_Reg_DPR(dst) );
6660 ins_pipe( fpu_reg_mem );
6661 %}
6662
6663 // Prefetch instructions.
6664 // Must be safe to execute with invalid address (cannot fault).
6665
6666 instruct prefetchr0( memory mem ) %{
6667 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6668 match(PrefetchRead mem);
6669 ins_cost(0);
6670 size(0);
6671 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6672 ins_encode();
6673 ins_pipe(empty);
6674 %}
6675
6676 instruct prefetchr( memory mem ) %{
6677 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6678 match(PrefetchRead mem);
6679 ins_cost(100);
6680
6681 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6682 ins_encode %{
6683 __ prefetchr($mem$$Address);
6684 %}
6685 ins_pipe(ialu_mem);
6686 %}
6687
6688 instruct prefetchrNTA( memory mem ) %{
6689 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6690 match(PrefetchRead mem);
6691 ins_cost(100);
6692
6693 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6694 ins_encode %{
6695 __ prefetchnta($mem$$Address);
6696 %}
6697 ins_pipe(ialu_mem);
6698 %}
6699
6700 instruct prefetchrT0( memory mem ) %{
6701 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6702 match(PrefetchRead mem);
6703 ins_cost(100);
6704
6705 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6706 ins_encode %{
6707 __ prefetcht0($mem$$Address);
6708 %}
6709 ins_pipe(ialu_mem);
6710 %}
6711
6712 instruct prefetchrT2( memory mem ) %{
6713 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6714 match(PrefetchRead mem);
6715 ins_cost(100);
6716
6717 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6718 ins_encode %{
6719 __ prefetcht2($mem$$Address);
6720 %}
6721 ins_pipe(ialu_mem);
6722 %}
6723
6724 instruct prefetchw0( memory mem ) %{
6725 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6726 match(PrefetchWrite mem);
6727 ins_cost(0);
6728 size(0);
6729 format %{ "Prefetch (non-SSE is empty encoding)" %}
6730 ins_encode();
6731 ins_pipe(empty);
6732 %}
6733
6734 instruct prefetchw( memory mem ) %{
6735 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6736 match( PrefetchWrite mem );
6737 ins_cost(100);
6738
6739 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6740 ins_encode %{
6741 __ prefetchw($mem$$Address);
6742 %}
6743 ins_pipe(ialu_mem);
6744 %}
6745
6746 instruct prefetchwNTA( memory mem ) %{
6747 predicate(UseSSE>=1);
6748 match(PrefetchWrite mem);
6749 ins_cost(100);
6750
6751 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6752 ins_encode %{
6753 __ prefetchnta($mem$$Address);
6754 %}
6755 ins_pipe(ialu_mem);
6756 %}
6757
6758 // Prefetch instructions for allocation.
6759
6760 instruct prefetchAlloc0( memory mem ) %{
6761 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6762 match(PrefetchAllocation mem);
6763 ins_cost(0);
6764 size(0);
6765 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6766 ins_encode();
6767 ins_pipe(empty);
6768 %}
6769
6770 instruct prefetchAlloc( memory mem ) %{
6771 predicate(AllocatePrefetchInstr==3);
6772 match( PrefetchAllocation mem );
6773 ins_cost(100);
6774
6775 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6776 ins_encode %{
6777 __ prefetchw($mem$$Address);
6778 %}
6779 ins_pipe(ialu_mem);
6780 %}
6781
6782 instruct prefetchAllocNTA( memory mem ) %{
6783 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6784 match(PrefetchAllocation mem);
6785 ins_cost(100);
6786
6787 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6788 ins_encode %{
6789 __ prefetchnta($mem$$Address);
6790 %}
6791 ins_pipe(ialu_mem);
6792 %}
6793
6794 instruct prefetchAllocT0( memory mem ) %{
6795 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6796 match(PrefetchAllocation mem);
6797 ins_cost(100);
6798
6799 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6800 ins_encode %{
6801 __ prefetcht0($mem$$Address);
6802 %}
6803 ins_pipe(ialu_mem);
6804 %}
6805
6806 instruct prefetchAllocT2( memory mem ) %{
6807 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6808 match(PrefetchAllocation mem);
6809 ins_cost(100);
6810
6811 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6812 ins_encode %{
6813 __ prefetcht2($mem$$Address);
6814 %}
6815 ins_pipe(ialu_mem);
6816 %}
6817
6818 //----------Store Instructions-------------------------------------------------
6819
6820 // Store Byte
6821 instruct storeB(memory mem, xRegI src) %{
6822 match(Set mem (StoreB mem src));
6823
6824 ins_cost(125);
6825 format %{ "MOV8 $mem,$src" %}
6826 opcode(0x88);
6827 ins_encode( OpcP, RegMem( src, mem ) );
6828 ins_pipe( ialu_mem_reg );
6829 %}
6830
6831 // Store Char/Short
6832 instruct storeC(memory mem, rRegI src) %{
6833 match(Set mem (StoreC mem src));
6834
6835 ins_cost(125);
6836 format %{ "MOV16 $mem,$src" %}
6837 opcode(0x89, 0x66);
6838 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6839 ins_pipe( ialu_mem_reg );
6840 %}
6841
6842 // Store Integer
6843 instruct storeI(memory mem, rRegI src) %{
6844 match(Set mem (StoreI mem src));
6845
6846 ins_cost(125);
6847 format %{ "MOV $mem,$src" %}
6848 opcode(0x89);
6849 ins_encode( OpcP, RegMem( src, mem ) );
6850 ins_pipe( ialu_mem_reg );
6851 %}
6852
6853 // Store Long
6854 instruct storeL(long_memory mem, eRegL src) %{
6855 predicate(!((StoreLNode*)n)->require_atomic_access());
6856 match(Set mem (StoreL mem src));
6857
6858 ins_cost(200);
6859 format %{ "MOV $mem,$src.lo\n\t"
6860 "MOV $mem+4,$src.hi" %}
6861 opcode(0x89, 0x89);
6862 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6863 ins_pipe( ialu_mem_long_reg );
6864 %}
6865
6866 // Store Long to Integer
6867 instruct storeL2I(memory mem, eRegL src) %{
6868 match(Set mem (StoreI mem (ConvL2I src)));
6869
6870 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6871 ins_encode %{
6872 __ movl($mem$$Address, $src$$Register);
6873 %}
6874 ins_pipe(ialu_mem_reg);
6875 %}
6876
6877 // Volatile Store Long. Must be atomic, so move it into
6878 // the FP TOS and then do a 64-bit FIST. Has to probe the
6879 // target address before the store (for null-ptr checks)
6880 // so the memory operand is used twice in the encoding.
6881 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6882 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6883 match(Set mem (StoreL mem src));
6884 effect( KILL cr );
6885 ins_cost(400);
6886 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6887 "FILD $src\n\t"
6888 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6889 opcode(0x3B);
6890 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6891 ins_pipe( fpu_reg_mem );
6892 %}
6893
6894 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6895 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6896 match(Set mem (StoreL mem src));
6897 effect( TEMP tmp, KILL cr );
6898 ins_cost(380);
6899 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6900 "MOVSD $tmp,$src\n\t"
6901 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6902 ins_encode %{
6903 __ cmpl(rax, $mem$$Address);
6904 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6905 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6906 %}
6907 ins_pipe( pipe_slow );
6908 %}
6909
6910 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6911 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6912 match(Set mem (StoreL mem src));
6913 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6914 ins_cost(360);
6915 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6916 "MOVD $tmp,$src.lo\n\t"
6917 "MOVD $tmp2,$src.hi\n\t"
6918 "PUNPCKLDQ $tmp,$tmp2\n\t"
6919 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6920 ins_encode %{
6921 __ cmpl(rax, $mem$$Address);
6922 __ movdl($tmp$$XMMRegister, $src$$Register);
6923 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6924 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6925 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6926 %}
6927 ins_pipe( pipe_slow );
6928 %}
6929
6930 // Store Pointer; for storing unknown oops and raw pointers
6931 instruct storeP(memory mem, anyRegP src) %{
6932 match(Set mem (StoreP mem src));
6933
6934 ins_cost(125);
6935 format %{ "MOV $mem,$src" %}
6936 opcode(0x89);
6937 ins_encode( OpcP, RegMem( src, mem ) );
6938 ins_pipe( ialu_mem_reg );
6939 %}
6940
6941 // Store Integer Immediate
6942 instruct storeImmI(memory mem, immI src) %{
6943 match(Set mem (StoreI mem src));
6944
6945 ins_cost(150);
6946 format %{ "MOV $mem,$src" %}
6947 opcode(0xC7); /* C7 /0 */
6948 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6949 ins_pipe( ialu_mem_imm );
6950 %}
6951
6952 // Store Short/Char Immediate
6953 instruct storeImmI16(memory mem, immI16 src) %{
6954 predicate(UseStoreImmI16);
6955 match(Set mem (StoreC mem src));
6956
6957 ins_cost(150);
6958 format %{ "MOV16 $mem,$src" %}
6959 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6960 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6961 ins_pipe( ialu_mem_imm );
6962 %}
6963
6964 // Store Pointer Immediate; null pointers or constant oops that do not
6965 // need card-mark barriers.
6966 instruct storeImmP(memory mem, immP src) %{
6967 match(Set mem (StoreP mem src));
6968
6969 ins_cost(150);
6970 format %{ "MOV $mem,$src" %}
6971 opcode(0xC7); /* C7 /0 */
6972 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6973 ins_pipe( ialu_mem_imm );
6974 %}
6975
6976 // Store Byte Immediate
6977 instruct storeImmB(memory mem, immI8 src) %{
6978 match(Set mem (StoreB mem src));
6979
6980 ins_cost(150);
6981 format %{ "MOV8 $mem,$src" %}
6982 opcode(0xC6); /* C6 /0 */
6983 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6984 ins_pipe( ialu_mem_imm );
6985 %}
6986
6987 // Store CMS card-mark Immediate
6988 instruct storeImmCM(memory mem, immI8 src) %{
6989 match(Set mem (StoreCM mem src));
6990
6991 ins_cost(150);
6992 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6993 opcode(0xC6); /* C6 /0 */
6994 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6995 ins_pipe( ialu_mem_imm );
6996 %}
6997
6998 // Store Double
6999 instruct storeDPR( memory mem, regDPR1 src) %{
7000 predicate(UseSSE<=1);
7001 match(Set mem (StoreD mem src));
7002
7003 ins_cost(100);
7004 format %{ "FST_D $mem,$src" %}
7005 opcode(0xDD); /* DD /2 */
7006 ins_encode( enc_FPR_store(mem,src) );
7007 ins_pipe( fpu_mem_reg );
7008 %}
7009
7010 // Store double does rounding on x86
7011 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
7012 predicate(UseSSE<=1);
7013 match(Set mem (StoreD mem (RoundDouble src)));
7014
7015 ins_cost(100);
7016 format %{ "FST_D $mem,$src\t# round" %}
7017 opcode(0xDD); /* DD /2 */
7018 ins_encode( enc_FPR_store(mem,src) );
7019 ins_pipe( fpu_mem_reg );
7020 %}
7021
7022 // Store XMM register to memory (double-precision floating points)
7023 // MOVSD instruction
7024 instruct storeD(memory mem, regD src) %{
7025 predicate(UseSSE>=2);
7026 match(Set mem (StoreD mem src));
7027 ins_cost(95);
7028 format %{ "MOVSD $mem,$src" %}
7029 ins_encode %{
7030 __ movdbl($mem$$Address, $src$$XMMRegister);
7031 %}
7032 ins_pipe( pipe_slow );
7033 %}
7034
7035 // Store XMM register to memory (single-precision floating point)
7036 // MOVSS instruction
7037 instruct storeF(memory mem, regF src) %{
7038 predicate(UseSSE>=1);
7039 match(Set mem (StoreF mem src));
7040 ins_cost(95);
7041 format %{ "MOVSS $mem,$src" %}
7042 ins_encode %{
7043 __ movflt($mem$$Address, $src$$XMMRegister);
7044 %}
7045 ins_pipe( pipe_slow );
7046 %}
7047
7048 // Store Float
7049 instruct storeFPR( memory mem, regFPR1 src) %{
7050 predicate(UseSSE==0);
7051 match(Set mem (StoreF mem src));
7052
7053 ins_cost(100);
7054 format %{ "FST_S $mem,$src" %}
7055 opcode(0xD9); /* D9 /2 */
7056 ins_encode( enc_FPR_store(mem,src) );
7057 ins_pipe( fpu_mem_reg );
7058 %}
7059
7060 // Store Float does rounding on x86
7061 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7062 predicate(UseSSE==0);
7063 match(Set mem (StoreF mem (RoundFloat src)));
7064
7065 ins_cost(100);
7066 format %{ "FST_S $mem,$src\t# round" %}
7067 opcode(0xD9); /* D9 /2 */
7068 ins_encode( enc_FPR_store(mem,src) );
7069 ins_pipe( fpu_mem_reg );
7070 %}
7071
7072 // Store Float does rounding on x86
7073 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7074 predicate(UseSSE<=1);
7075 match(Set mem (StoreF mem (ConvD2F src)));
7076
7077 ins_cost(100);
7078 format %{ "FST_S $mem,$src\t# D-round" %}
7079 opcode(0xD9); /* D9 /2 */
7080 ins_encode( enc_FPR_store(mem,src) );
7081 ins_pipe( fpu_mem_reg );
7082 %}
7083
7084 // Store immediate Float value (it is faster than store from FPU register)
7085 // The instruction usage is guarded by predicate in operand immFPR().
7086 instruct storeFPR_imm( memory mem, immFPR src) %{
7087 match(Set mem (StoreF mem src));
7088
7089 ins_cost(50);
7090 format %{ "MOV $mem,$src\t# store float" %}
7091 opcode(0xC7); /* C7 /0 */
7092 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7093 ins_pipe( ialu_mem_imm );
7094 %}
7095
7096 // Store immediate Float value (it is faster than store from XMM register)
7097 // The instruction usage is guarded by predicate in operand immF().
7098 instruct storeF_imm( memory mem, immF src) %{
7099 match(Set mem (StoreF mem src));
7100
7101 ins_cost(50);
7102 format %{ "MOV $mem,$src\t# store float" %}
7103 opcode(0xC7); /* C7 /0 */
7104 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7105 ins_pipe( ialu_mem_imm );
7106 %}
7107
7108 // Store Integer to stack slot
7109 instruct storeSSI(stackSlotI dst, rRegI src) %{
7110 match(Set dst src);
7111
7112 ins_cost(100);
7113 format %{ "MOV $dst,$src" %}
7114 opcode(0x89);
7115 ins_encode( OpcPRegSS( dst, src ) );
7116 ins_pipe( ialu_mem_reg );
7117 %}
7118
7119 // Store Integer to stack slot
7120 instruct storeSSP(stackSlotP dst, eRegP src) %{
7121 match(Set dst src);
7122
7123 ins_cost(100);
7124 format %{ "MOV $dst,$src" %}
7125 opcode(0x89);
7126 ins_encode( OpcPRegSS( dst, src ) );
7127 ins_pipe( ialu_mem_reg );
7128 %}
7129
7130 // Store Long to stack slot
7131 instruct storeSSL(stackSlotL dst, eRegL src) %{
7132 match(Set dst src);
7133
7134 ins_cost(200);
7135 format %{ "MOV $dst,$src.lo\n\t"
7136 "MOV $dst+4,$src.hi" %}
7137 opcode(0x89, 0x89);
7138 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7139 ins_pipe( ialu_mem_long_reg );
7140 %}
7141
7142 //----------MemBar Instructions-----------------------------------------------
7143 // Memory barrier flavors
7144
7145 instruct membar_acquire() %{
7146 match(MemBarAcquire);
7147 match(LoadFence);
7148 ins_cost(400);
7149
7150 size(0);
7151 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7152 ins_encode();
7153 ins_pipe(empty);
7154 %}
7155
7156 instruct membar_acquire_lock() %{
7157 match(MemBarAcquireLock);
7158 ins_cost(0);
7159
7160 size(0);
7161 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7162 ins_encode( );
7163 ins_pipe(empty);
7164 %}
7165
7166 instruct membar_release() %{
7167 match(MemBarRelease);
7168 match(StoreFence);
7169 ins_cost(400);
7170
7171 size(0);
7172 format %{ "MEMBAR-release ! (empty encoding)" %}
7173 ins_encode( );
7174 ins_pipe(empty);
7175 %}
7176
7177 instruct membar_release_lock() %{
7178 match(MemBarReleaseLock);
7179 ins_cost(0);
7180
7181 size(0);
7182 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7183 ins_encode( );
7184 ins_pipe(empty);
7185 %}
7186
7187 instruct membar_volatile(eFlagsReg cr) %{
7188 match(MemBarVolatile);
7189 effect(KILL cr);
7190 ins_cost(400);
7191
7192 format %{
7193 $$template
7194 if (os::is_MP()) {
7195 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7196 } else {
7197 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7198 }
7199 %}
7200 ins_encode %{
7201 __ membar(Assembler::StoreLoad);
7202 %}
7203 ins_pipe(pipe_slow);
7204 %}
7205
7206 instruct unnecessary_membar_volatile() %{
7207 match(MemBarVolatile);
7208 predicate(Matcher::post_store_load_barrier(n));
7209 ins_cost(0);
7210
7211 size(0);
7212 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7213 ins_encode( );
7214 ins_pipe(empty);
7215 %}
7216
7217 instruct membar_storestore() %{
7218 match(MemBarStoreStore);
7219 ins_cost(0);
7220
7221 size(0);
7222 format %{ "MEMBAR-storestore (empty encoding)" %}
7223 ins_encode( );
7224 ins_pipe(empty);
7225 %}
7226
7227 //----------Move Instructions--------------------------------------------------
7228 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7229 match(Set dst (CastX2P src));
7230 format %{ "# X2P $dst, $src" %}
7231 ins_encode( /*empty encoding*/ );
7232 ins_cost(0);
7233 ins_pipe(empty);
7234 %}
7235
7236 instruct castP2X(rRegI dst, eRegP src ) %{
7237 match(Set dst (CastP2X src));
7238 ins_cost(50);
7239 format %{ "MOV $dst, $src\t# CastP2X" %}
7240 ins_encode( enc_Copy( dst, src) );
7241 ins_pipe( ialu_reg_reg );
7242 %}
7243
7244 //----------Conditional Move---------------------------------------------------
7245 // Conditional move
7246 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7247 predicate(!VM_Version::supports_cmov() );
7248 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7249 ins_cost(200);
7250 format %{ "J$cop,us skip\t# signed cmove\n\t"
7251 "MOV $dst,$src\n"
7252 "skip:" %}
7253 ins_encode %{
7254 Label Lskip;
7255 // Invert sense of branch from sense of CMOV
7256 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7257 __ movl($dst$$Register, $src$$Register);
7258 __ bind(Lskip);
7259 %}
7260 ins_pipe( pipe_cmov_reg );
7261 %}
7262
7263 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7264 predicate(!VM_Version::supports_cmov() );
7265 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7266 ins_cost(200);
7267 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7268 "MOV $dst,$src\n"
7269 "skip:" %}
7270 ins_encode %{
7271 Label Lskip;
7272 // Invert sense of branch from sense of CMOV
7273 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7274 __ movl($dst$$Register, $src$$Register);
7275 __ bind(Lskip);
7276 %}
7277 ins_pipe( pipe_cmov_reg );
7278 %}
7279
7280 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7281 predicate(VM_Version::supports_cmov() );
7282 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7283 ins_cost(200);
7284 format %{ "CMOV$cop $dst,$src" %}
7285 opcode(0x0F,0x40);
7286 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7287 ins_pipe( pipe_cmov_reg );
7288 %}
7289
7290 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7291 predicate(VM_Version::supports_cmov() );
7292 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7293 ins_cost(200);
7294 format %{ "CMOV$cop $dst,$src" %}
7295 opcode(0x0F,0x40);
7296 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7297 ins_pipe( pipe_cmov_reg );
7298 %}
7299
7300 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7301 predicate(VM_Version::supports_cmov() );
7302 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7303 ins_cost(200);
7304 expand %{
7305 cmovI_regU(cop, cr, dst, src);
7306 %}
7307 %}
7308
7309 // Conditional move
7310 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7311 predicate(VM_Version::supports_cmov() );
7312 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7313 ins_cost(250);
7314 format %{ "CMOV$cop $dst,$src" %}
7315 opcode(0x0F,0x40);
7316 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7317 ins_pipe( pipe_cmov_mem );
7318 %}
7319
7320 // Conditional move
7321 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7322 predicate(VM_Version::supports_cmov() );
7323 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7324 ins_cost(250);
7325 format %{ "CMOV$cop $dst,$src" %}
7326 opcode(0x0F,0x40);
7327 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7328 ins_pipe( pipe_cmov_mem );
7329 %}
7330
7331 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7332 predicate(VM_Version::supports_cmov() );
7333 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7334 ins_cost(250);
7335 expand %{
7336 cmovI_memU(cop, cr, dst, src);
7337 %}
7338 %}
7339
7340 // Conditional move
7341 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7342 predicate(VM_Version::supports_cmov() );
7343 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7344 ins_cost(200);
7345 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7346 opcode(0x0F,0x40);
7347 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7348 ins_pipe( pipe_cmov_reg );
7349 %}
7350
7351 // Conditional move (non-P6 version)
7352 // Note: a CMoveP is generated for stubs and native wrappers
7353 // regardless of whether we are on a P6, so we
7354 // emulate a cmov here
7355 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7356 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7357 ins_cost(300);
7358 format %{ "Jn$cop skip\n\t"
7359 "MOV $dst,$src\t# pointer\n"
7360 "skip:" %}
7361 opcode(0x8b);
7362 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7363 ins_pipe( pipe_cmov_reg );
7364 %}
7365
7366 // Conditional move
7367 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7368 predicate(VM_Version::supports_cmov() );
7369 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7370 ins_cost(200);
7371 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7372 opcode(0x0F,0x40);
7373 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7374 ins_pipe( pipe_cmov_reg );
7375 %}
7376
7377 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7378 predicate(VM_Version::supports_cmov() );
7379 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7380 ins_cost(200);
7381 expand %{
7382 cmovP_regU(cop, cr, dst, src);
7383 %}
7384 %}
7385
7386 // DISABLED: Requires the ADLC to emit a bottom_type call that
7387 // correctly meets the two pointer arguments; one is an incoming
7388 // register but the other is a memory operand. ALSO appears to
7389 // be buggy with implicit null checks.
7390 //
7391 //// Conditional move
7392 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7393 // predicate(VM_Version::supports_cmov() );
7394 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7395 // ins_cost(250);
7396 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7397 // opcode(0x0F,0x40);
7398 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7399 // ins_pipe( pipe_cmov_mem );
7400 //%}
7401 //
7402 //// Conditional move
7403 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7404 // predicate(VM_Version::supports_cmov() );
7405 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7406 // ins_cost(250);
7407 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7408 // opcode(0x0F,0x40);
7409 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7410 // ins_pipe( pipe_cmov_mem );
7411 //%}
7412
7413 // Conditional move
7414 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7415 predicate(UseSSE<=1);
7416 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7417 ins_cost(200);
7418 format %{ "FCMOV$cop $dst,$src\t# double" %}
7419 opcode(0xDA);
7420 ins_encode( enc_cmov_dpr(cop,src) );
7421 ins_pipe( pipe_cmovDPR_reg );
7422 %}
7423
7424 // Conditional move
7425 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7426 predicate(UseSSE==0);
7427 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7428 ins_cost(200);
7429 format %{ "FCMOV$cop $dst,$src\t# float" %}
7430 opcode(0xDA);
7431 ins_encode( enc_cmov_dpr(cop,src) );
7432 ins_pipe( pipe_cmovDPR_reg );
7433 %}
7434
7435 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7436 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7437 predicate(UseSSE<=1);
7438 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7439 ins_cost(200);
7440 format %{ "Jn$cop skip\n\t"
7441 "MOV $dst,$src\t# double\n"
7442 "skip:" %}
7443 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7444 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7445 ins_pipe( pipe_cmovDPR_reg );
7446 %}
7447
7448 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7449 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7450 predicate(UseSSE==0);
7451 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7452 ins_cost(200);
7453 format %{ "Jn$cop skip\n\t"
7454 "MOV $dst,$src\t# float\n"
7455 "skip:" %}
7456 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7457 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7458 ins_pipe( pipe_cmovDPR_reg );
7459 %}
7460
7461 // No CMOVE with SSE/SSE2
7462 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7463 predicate (UseSSE>=1);
7464 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7465 ins_cost(200);
7466 format %{ "Jn$cop skip\n\t"
7467 "MOVSS $dst,$src\t# float\n"
7468 "skip:" %}
7469 ins_encode %{
7470 Label skip;
7471 // Invert sense of branch from sense of CMOV
7472 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7473 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7474 __ bind(skip);
7475 %}
7476 ins_pipe( pipe_slow );
7477 %}
7478
7479 // No CMOVE with SSE/SSE2
7480 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7481 predicate (UseSSE>=2);
7482 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7483 ins_cost(200);
7484 format %{ "Jn$cop skip\n\t"
7485 "MOVSD $dst,$src\t# float\n"
7486 "skip:" %}
7487 ins_encode %{
7488 Label skip;
7489 // Invert sense of branch from sense of CMOV
7490 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7491 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7492 __ bind(skip);
7493 %}
7494 ins_pipe( pipe_slow );
7495 %}
7496
7497 // unsigned version
7498 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7499 predicate (UseSSE>=1);
7500 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7501 ins_cost(200);
7502 format %{ "Jn$cop skip\n\t"
7503 "MOVSS $dst,$src\t# float\n"
7504 "skip:" %}
7505 ins_encode %{
7506 Label skip;
7507 // Invert sense of branch from sense of CMOV
7508 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7509 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7510 __ bind(skip);
7511 %}
7512 ins_pipe( pipe_slow );
7513 %}
7514
7515 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7516 predicate (UseSSE>=1);
7517 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7518 ins_cost(200);
7519 expand %{
7520 fcmovF_regU(cop, cr, dst, src);
7521 %}
7522 %}
7523
7524 // unsigned version
7525 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7526 predicate (UseSSE>=2);
7527 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7528 ins_cost(200);
7529 format %{ "Jn$cop skip\n\t"
7530 "MOVSD $dst,$src\t# float\n"
7531 "skip:" %}
7532 ins_encode %{
7533 Label skip;
7534 // Invert sense of branch from sense of CMOV
7535 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7536 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7537 __ bind(skip);
7538 %}
7539 ins_pipe( pipe_slow );
7540 %}
7541
7542 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7543 predicate (UseSSE>=2);
7544 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7545 ins_cost(200);
7546 expand %{
7547 fcmovD_regU(cop, cr, dst, src);
7548 %}
7549 %}
7550
7551 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7552 predicate(VM_Version::supports_cmov() );
7553 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7554 ins_cost(200);
7555 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7556 "CMOV$cop $dst.hi,$src.hi" %}
7557 opcode(0x0F,0x40);
7558 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7559 ins_pipe( pipe_cmov_reg_long );
7560 %}
7561
7562 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7563 predicate(VM_Version::supports_cmov() );
7564 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7565 ins_cost(200);
7566 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7567 "CMOV$cop $dst.hi,$src.hi" %}
7568 opcode(0x0F,0x40);
7569 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7570 ins_pipe( pipe_cmov_reg_long );
7571 %}
7572
7573 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7574 predicate(VM_Version::supports_cmov() );
7575 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7576 ins_cost(200);
7577 expand %{
7578 cmovL_regU(cop, cr, dst, src);
7579 %}
7580 %}
7581
7582 //----------Arithmetic Instructions--------------------------------------------
7583 //----------Addition Instructions----------------------------------------------
7584
7585 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7586 %{
7587 match(AddExactI dst src);
7588 effect(DEF cr);
7589
7590 format %{ "ADD $dst, $src\t# addExact int" %}
7591 ins_encode %{
7592 __ addl($dst$$Register, $src$$Register);
7593 %}
7594 ins_pipe(ialu_reg_reg);
7595 %}
7596
7597 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7598 %{
7599 match(AddExactI dst src);
7600 effect(DEF cr);
7601
7602 format %{ "ADD $dst, $src\t# addExact int" %}
7603 ins_encode %{
7604 __ addl($dst$$Register, $src$$constant);
7605 %}
7606 ins_pipe(ialu_reg_reg);
7607 %}
7608
7609 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7610 %{
7611 match(AddExactI dst (LoadI src));
7612 effect(DEF cr);
7613
7614 ins_cost(125);
7615 format %{ "ADD $dst,$src\t# addExact int" %}
7616 ins_encode %{
7617 __ addl($dst$$Register, $src$$Address);
7618 %}
7619 ins_pipe( ialu_reg_mem );
7620 %}
7621
7622
7623 // Integer Addition Instructions
7624 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7625 match(Set dst (AddI dst src));
7626 effect(KILL cr);
7627
7628 size(2);
7629 format %{ "ADD $dst,$src" %}
7630 opcode(0x03);
7631 ins_encode( OpcP, RegReg( dst, src) );
7632 ins_pipe( ialu_reg_reg );
7633 %}
7634
7635 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7636 match(Set dst (AddI dst src));
7637 effect(KILL cr);
7638
7639 format %{ "ADD $dst,$src" %}
7640 opcode(0x81, 0x00); /* /0 id */
7641 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7642 ins_pipe( ialu_reg );
7643 %}
7644
7645 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7646 predicate(UseIncDec);
7647 match(Set dst (AddI dst src));
7648 effect(KILL cr);
7649
7650 size(1);
7651 format %{ "INC $dst" %}
7652 opcode(0x40); /* */
7653 ins_encode( Opc_plus( primary, dst ) );
7654 ins_pipe( ialu_reg );
7655 %}
7656
7657 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7658 match(Set dst (AddI src0 src1));
7659 ins_cost(110);
7660
7661 format %{ "LEA $dst,[$src0 + $src1]" %}
7662 opcode(0x8D); /* 0x8D /r */
7663 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7664 ins_pipe( ialu_reg_reg );
7665 %}
7666
7667 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7668 match(Set dst (AddP src0 src1));
7669 ins_cost(110);
7670
7671 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7672 opcode(0x8D); /* 0x8D /r */
7673 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7674 ins_pipe( ialu_reg_reg );
7675 %}
7676
7677 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7678 predicate(UseIncDec);
7679 match(Set dst (AddI dst src));
7680 effect(KILL cr);
7681
7682 size(1);
7683 format %{ "DEC $dst" %}
7684 opcode(0x48); /* */
7685 ins_encode( Opc_plus( primary, dst ) );
7686 ins_pipe( ialu_reg );
7687 %}
7688
7689 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7690 match(Set dst (AddP dst src));
7691 effect(KILL cr);
7692
7693 size(2);
7694 format %{ "ADD $dst,$src" %}
7695 opcode(0x03);
7696 ins_encode( OpcP, RegReg( dst, src) );
7697 ins_pipe( ialu_reg_reg );
7698 %}
7699
7700 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7701 match(Set dst (AddP dst src));
7702 effect(KILL cr);
7703
7704 format %{ "ADD $dst,$src" %}
7705 opcode(0x81,0x00); /* Opcode 81 /0 id */
7706 // ins_encode( RegImm( dst, src) );
7707 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7708 ins_pipe( ialu_reg );
7709 %}
7710
7711 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7712 match(Set dst (AddI dst (LoadI src)));
7713 effect(KILL cr);
7714
7715 ins_cost(125);
7716 format %{ "ADD $dst,$src" %}
7717 opcode(0x03);
7718 ins_encode( OpcP, RegMem( dst, src) );
7719 ins_pipe( ialu_reg_mem );
7720 %}
7721
7722 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7723 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7724 effect(KILL cr);
7725
7726 ins_cost(150);
7727 format %{ "ADD $dst,$src" %}
7728 opcode(0x01); /* Opcode 01 /r */
7729 ins_encode( OpcP, RegMem( src, dst ) );
7730 ins_pipe( ialu_mem_reg );
7731 %}
7732
7733 // Add Memory with Immediate
7734 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7735 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7736 effect(KILL cr);
7737
7738 ins_cost(125);
7739 format %{ "ADD $dst,$src" %}
7740 opcode(0x81); /* Opcode 81 /0 id */
7741 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7742 ins_pipe( ialu_mem_imm );
7743 %}
7744
7745 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7746 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7747 effect(KILL cr);
7748
7749 ins_cost(125);
7750 format %{ "INC $dst" %}
7751 opcode(0xFF); /* Opcode FF /0 */
7752 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7753 ins_pipe( ialu_mem_imm );
7754 %}
7755
7756 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7757 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7758 effect(KILL cr);
7759
7760 ins_cost(125);
7761 format %{ "DEC $dst" %}
7762 opcode(0xFF); /* Opcode FF /1 */
7763 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7764 ins_pipe( ialu_mem_imm );
7765 %}
7766
7767
7768 instruct checkCastPP( eRegP dst ) %{
7769 match(Set dst (CheckCastPP dst));
7770
7771 size(0);
7772 format %{ "#checkcastPP of $dst" %}
7773 ins_encode( /*empty encoding*/ );
7774 ins_pipe( empty );
7775 %}
7776
7777 instruct castPP( eRegP dst ) %{
7778 match(Set dst (CastPP dst));
7779 format %{ "#castPP of $dst" %}
7780 ins_encode( /*empty encoding*/ );
7781 ins_pipe( empty );
7782 %}
7783
7784 instruct castII( rRegI dst ) %{
7785 match(Set dst (CastII dst));
7786 format %{ "#castII of $dst" %}
7787 ins_encode( /*empty encoding*/ );
7788 ins_cost(0);
7789 ins_pipe( empty );
7790 %}
7791
7792
7793 // Load-locked - same as a regular pointer load when used with compare-swap
7794 instruct loadPLocked(eRegP dst, memory mem) %{
7795 match(Set dst (LoadPLocked mem));
7796
7797 ins_cost(125);
7798 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7799 opcode(0x8B);
7800 ins_encode( OpcP, RegMem(dst,mem));
7801 ins_pipe( ialu_reg_mem );
7802 %}
7803
7804 // Conditional-store of the updated heap-top.
7805 // Used during allocation of the shared heap.
7806 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7807 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7808 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7809 // EAX is killed if there is contention, but then it's also unused.
7810 // In the common case of no contention, EAX holds the new oop address.
7811 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7812 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7813 ins_pipe( pipe_cmpxchg );
7814 %}
7815
7816 // Conditional-store of an int value.
7817 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7818 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7819 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7820 effect(KILL oldval);
7821 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7822 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7823 ins_pipe( pipe_cmpxchg );
7824 %}
7825
7826 // Conditional-store of a long value.
7827 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7828 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7829 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7830 effect(KILL oldval);
7831 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7832 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7833 "XCHG EBX,ECX"
7834 %}
7835 ins_encode %{
7836 // Note: we need to swap rbx, and rcx before and after the
7837 // cmpxchg8 instruction because the instruction uses
7838 // rcx as the high order word of the new value to store but
7839 // our register encoding uses rbx.
7840 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7841 if( os::is_MP() )
7842 __ lock();
7843 __ cmpxchg8($mem$$Address);
7844 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7845 %}
7846 ins_pipe( pipe_cmpxchg );
7847 %}
7848
7849 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7850
7851 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7852 predicate(VM_Version::supports_cx8());
7853 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7854 effect(KILL cr, KILL oldval);
7855 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7856 "MOV $res,0\n\t"
7857 "JNE,s fail\n\t"
7858 "MOV $res,1\n"
7859 "fail:" %}
7860 ins_encode( enc_cmpxchg8(mem_ptr),
7861 enc_flags_ne_to_boolean(res) );
7862 ins_pipe( pipe_cmpxchg );
7863 %}
7864
7865 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7866 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7867 effect(KILL cr, KILL oldval);
7868 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7869 "MOV $res,0\n\t"
7870 "JNE,s fail\n\t"
7871 "MOV $res,1\n"
7872 "fail:" %}
7873 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7874 ins_pipe( pipe_cmpxchg );
7875 %}
7876
7877 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7878 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7879 effect(KILL cr, KILL oldval);
7880 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7881 "MOV $res,0\n\t"
7882 "JNE,s fail\n\t"
7883 "MOV $res,1\n"
7884 "fail:" %}
7885 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7886 ins_pipe( pipe_cmpxchg );
7887 %}
7888
7889 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7890 predicate(n->as_LoadStore()->result_not_used());
7891 match(Set dummy (GetAndAddI mem add));
7892 effect(KILL cr);
7893 format %{ "ADDL [$mem],$add" %}
7894 ins_encode %{
7895 if (os::is_MP()) { __ lock(); }
7896 __ addl($mem$$Address, $add$$constant);
7897 %}
7898 ins_pipe( pipe_cmpxchg );
7899 %}
7900
7901 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7902 match(Set newval (GetAndAddI mem newval));
7903 effect(KILL cr);
7904 format %{ "XADDL [$mem],$newval" %}
7905 ins_encode %{
7906 if (os::is_MP()) { __ lock(); }
7907 __ xaddl($mem$$Address, $newval$$Register);
7908 %}
7909 ins_pipe( pipe_cmpxchg );
7910 %}
7911
7912 instruct xchgI( memory mem, rRegI newval) %{
7913 match(Set newval (GetAndSetI mem newval));
7914 format %{ "XCHGL $newval,[$mem]" %}
7915 ins_encode %{
7916 __ xchgl($newval$$Register, $mem$$Address);
7917 %}
7918 ins_pipe( pipe_cmpxchg );
7919 %}
7920
7921 instruct xchgP( memory mem, pRegP newval) %{
7922 match(Set newval (GetAndSetP mem newval));
7923 format %{ "XCHGL $newval,[$mem]" %}
7924 ins_encode %{
7925 __ xchgl($newval$$Register, $mem$$Address);
7926 %}
7927 ins_pipe( pipe_cmpxchg );
7928 %}
7929
7930 //----------Subtraction Instructions-------------------------------------------
7931
7932 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7933 %{
7934 match(SubExactI dst src);
7935 effect(DEF cr);
7936
7937 format %{ "SUB $dst, $src\t# subExact int" %}
7938 ins_encode %{
7939 __ subl($dst$$Register, $src$$Register);
7940 %}
7941 ins_pipe(ialu_reg_reg);
7942 %}
7943
7944 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7945 %{
7946 match(SubExactI dst src);
7947 effect(DEF cr);
7948
7949 format %{ "SUB $dst, $src\t# subExact int" %}
7950 ins_encode %{
7951 __ subl($dst$$Register, $src$$constant);
7952 %}
7953 ins_pipe(ialu_reg_reg);
7954 %}
7955
7956 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7957 %{
7958 match(SubExactI dst (LoadI src));
7959 effect(DEF cr);
7960
7961 ins_cost(125);
7962 format %{ "SUB $dst,$src\t# subExact int" %}
7963 ins_encode %{
7964 __ subl($dst$$Register, $src$$Address);
7965 %}
7966 ins_pipe( ialu_reg_mem );
7967 %}
7968
7969 // Integer Subtraction Instructions
7970 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7971 match(Set dst (SubI dst src));
7972 effect(KILL cr);
7973
7974 size(2);
7975 format %{ "SUB $dst,$src" %}
7976 opcode(0x2B);
7977 ins_encode( OpcP, RegReg( dst, src) );
7978 ins_pipe( ialu_reg_reg );
7979 %}
7980
7981 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7982 match(Set dst (SubI dst src));
7983 effect(KILL cr);
7984
7985 format %{ "SUB $dst,$src" %}
7986 opcode(0x81,0x05); /* Opcode 81 /5 */
7987 // ins_encode( RegImm( dst, src) );
7988 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7989 ins_pipe( ialu_reg );
7990 %}
7991
7992 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7993 match(Set dst (SubI dst (LoadI src)));
7994 effect(KILL cr);
7995
7996 ins_cost(125);
7997 format %{ "SUB $dst,$src" %}
7998 opcode(0x2B);
7999 ins_encode( OpcP, RegMem( dst, src) );
8000 ins_pipe( ialu_reg_mem );
8001 %}
8002
8003 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8004 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8005 effect(KILL cr);
8006
8007 ins_cost(150);
8008 format %{ "SUB $dst,$src" %}
8009 opcode(0x29); /* Opcode 29 /r */
8010 ins_encode( OpcP, RegMem( src, dst ) );
8011 ins_pipe( ialu_mem_reg );
8012 %}
8013
8014 // Subtract from a pointer
8015 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
8016 match(Set dst (AddP dst (SubI zero src)));
8017 effect(KILL cr);
8018
8019 size(2);
8020 format %{ "SUB $dst,$src" %}
8021 opcode(0x2B);
8022 ins_encode( OpcP, RegReg( dst, src) );
8023 ins_pipe( ialu_reg_reg );
8024 %}
8025
8026 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
8027 match(Set dst (SubI zero dst));
8028 effect(KILL cr);
8029
8030 size(2);
8031 format %{ "NEG $dst" %}
8032 opcode(0xF7,0x03); // Opcode F7 /3
8033 ins_encode( OpcP, RegOpc( dst ) );
8034 ins_pipe( ialu_reg );
8035 %}
8036
8037 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
8038 match(NegExactI dst);
8039 effect(DEF cr);
8040
8041 format %{ "NEG $dst\t# negExact int"%}
8042 ins_encode %{
8043 __ negl($dst$$Register);
8044 %}
8045 ins_pipe(ialu_reg);
8046 %}
8047
8048 //----------Multiplication/Division Instructions-------------------------------
8049 // Integer Multiplication Instructions
8050 // Multiply Register
8051 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8052 match(Set dst (MulI dst src));
8053 effect(KILL cr);
8054
8055 size(3);
8056 ins_cost(300);
8057 format %{ "IMUL $dst,$src" %}
8058 opcode(0xAF, 0x0F);
8059 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8060 ins_pipe( ialu_reg_reg_alu0 );
8061 %}
8062
8063 // Multiply 32-bit Immediate
8064 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8065 match(Set dst (MulI src imm));
8066 effect(KILL cr);
8067
8068 ins_cost(300);
8069 format %{ "IMUL $dst,$src,$imm" %}
8070 opcode(0x69); /* 69 /r id */
8071 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8072 ins_pipe( ialu_reg_reg_alu0 );
8073 %}
8074
8075 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8076 match(Set dst src);
8077 effect(KILL cr);
8078
8079 // Note that this is artificially increased to make it more expensive than loadConL
8080 ins_cost(250);
8081 format %{ "MOV EAX,$src\t// low word only" %}
8082 opcode(0xB8);
8083 ins_encode( LdImmL_Lo(dst, src) );
8084 ins_pipe( ialu_reg_fat );
8085 %}
8086
8087 // Multiply by 32-bit Immediate, taking the shifted high order results
8088 // (special case for shift by 32)
8089 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8090 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8091 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8092 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8093 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8094 effect(USE src1, KILL cr);
8095
8096 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8097 ins_cost(0*100 + 1*400 - 150);
8098 format %{ "IMUL EDX:EAX,$src1" %}
8099 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8100 ins_pipe( pipe_slow );
8101 %}
8102
8103 // Multiply by 32-bit Immediate, taking the shifted high order results
8104 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8105 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8106 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8107 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8108 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8109 effect(USE src1, KILL cr);
8110
8111 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8112 ins_cost(1*100 + 1*400 - 150);
8113 format %{ "IMUL EDX:EAX,$src1\n\t"
8114 "SAR EDX,$cnt-32" %}
8115 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8116 ins_pipe( pipe_slow );
8117 %}
8118
8119 // Multiply Memory 32-bit Immediate
8120 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8121 match(Set dst (MulI (LoadI src) imm));
8122 effect(KILL cr);
8123
8124 ins_cost(300);
8125 format %{ "IMUL $dst,$src,$imm" %}
8126 opcode(0x69); /* 69 /r id */
8127 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8128 ins_pipe( ialu_reg_mem_alu0 );
8129 %}
8130
8131 // Multiply Memory
8132 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8133 match(Set dst (MulI dst (LoadI src)));
8134 effect(KILL cr);
8135
8136 ins_cost(350);
8137 format %{ "IMUL $dst,$src" %}
8138 opcode(0xAF, 0x0F);
8139 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8140 ins_pipe( ialu_reg_mem_alu0 );
8141 %}
8142
8143 // Multiply Register Int to Long
8144 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8145 // Basic Idea: long = (long)int * (long)int
8146 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8147 effect(DEF dst, USE src, USE src1, KILL flags);
8148
8149 ins_cost(300);
8150 format %{ "IMUL $dst,$src1" %}
8151
8152 ins_encode( long_int_multiply( dst, src1 ) );
8153 ins_pipe( ialu_reg_reg_alu0 );
8154 %}
8155
8156 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8157 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8158 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8159 effect(KILL flags);
8160
8161 ins_cost(300);
8162 format %{ "MUL $dst,$src1" %}
8163
8164 ins_encode( long_uint_multiply(dst, src1) );
8165 ins_pipe( ialu_reg_reg_alu0 );
8166 %}
8167
8168 // Multiply Register Long
8169 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8170 match(Set dst (MulL dst src));
8171 effect(KILL cr, TEMP tmp);
8172 ins_cost(4*100+3*400);
8173 // Basic idea: lo(result) = lo(x_lo * y_lo)
8174 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8175 format %{ "MOV $tmp,$src.lo\n\t"
8176 "IMUL $tmp,EDX\n\t"
8177 "MOV EDX,$src.hi\n\t"
8178 "IMUL EDX,EAX\n\t"
8179 "ADD $tmp,EDX\n\t"
8180 "MUL EDX:EAX,$src.lo\n\t"
8181 "ADD EDX,$tmp" %}
8182 ins_encode( long_multiply( dst, src, tmp ) );
8183 ins_pipe( pipe_slow );
8184 %}
8185
8186 // Multiply Register Long where the left operand's high 32 bits are zero
8187 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8188 predicate(is_operand_hi32_zero(n->in(1)));
8189 match(Set dst (MulL dst src));
8190 effect(KILL cr, TEMP tmp);
8191 ins_cost(2*100+2*400);
8192 // Basic idea: lo(result) = lo(x_lo * y_lo)
8193 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8194 format %{ "MOV $tmp,$src.hi\n\t"
8195 "IMUL $tmp,EAX\n\t"
8196 "MUL EDX:EAX,$src.lo\n\t"
8197 "ADD EDX,$tmp" %}
8198 ins_encode %{
8199 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8200 __ imull($tmp$$Register, rax);
8201 __ mull($src$$Register);
8202 __ addl(rdx, $tmp$$Register);
8203 %}
8204 ins_pipe( pipe_slow );
8205 %}
8206
8207 // Multiply Register Long where the right operand's high 32 bits are zero
8208 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8209 predicate(is_operand_hi32_zero(n->in(2)));
8210 match(Set dst (MulL dst src));
8211 effect(KILL cr, TEMP tmp);
8212 ins_cost(2*100+2*400);
8213 // Basic idea: lo(result) = lo(x_lo * y_lo)
8214 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8215 format %{ "MOV $tmp,$src.lo\n\t"
8216 "IMUL $tmp,EDX\n\t"
8217 "MUL EDX:EAX,$src.lo\n\t"
8218 "ADD EDX,$tmp" %}
8219 ins_encode %{
8220 __ movl($tmp$$Register, $src$$Register);
8221 __ imull($tmp$$Register, rdx);
8222 __ mull($src$$Register);
8223 __ addl(rdx, $tmp$$Register);
8224 %}
8225 ins_pipe( pipe_slow );
8226 %}
8227
8228 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8229 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8230 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8231 match(Set dst (MulL dst src));
8232 effect(KILL cr);
8233 ins_cost(1*400);
8234 // Basic idea: lo(result) = lo(x_lo * y_lo)
8235 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8236 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8237 ins_encode %{
8238 __ mull($src$$Register);
8239 %}
8240 ins_pipe( pipe_slow );
8241 %}
8242
8243 // Multiply Register Long by small constant
8244 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8245 match(Set dst (MulL dst src));
8246 effect(KILL cr, TEMP tmp);
8247 ins_cost(2*100+2*400);
8248 size(12);
8249 // Basic idea: lo(result) = lo(src * EAX)
8250 // hi(result) = hi(src * EAX) + lo(src * EDX)
8251 format %{ "IMUL $tmp,EDX,$src\n\t"
8252 "MOV EDX,$src\n\t"
8253 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8254 "ADD EDX,$tmp" %}
8255 ins_encode( long_multiply_con( dst, src, tmp ) );
8256 ins_pipe( pipe_slow );
8257 %}
8258
8259 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8260 %{
8261 match(MulExactI dst src);
8262 effect(DEF cr);
8263
8264 ins_cost(300);
8265 format %{ "IMUL $dst, $src\t# mulExact int" %}
8266 ins_encode %{
8267 __ imull($dst$$Register, $src$$Register);
8268 %}
8269 ins_pipe(ialu_reg_reg_alu0);
8270 %}
8271
8272 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8273 %{
8274 match(MulExactI src imm);
8275 effect(DEF cr);
8276
8277 ins_cost(300);
8278 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8279 ins_encode %{
8280 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8281 %}
8282 ins_pipe(ialu_reg_reg_alu0);
8283 %}
8284
8285 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8286 %{
8287 match(MulExactI dst (LoadI src));
8288 effect(DEF cr);
8289
8290 ins_cost(350);
8291 format %{ "IMUL $dst, $src\t# mulExact int" %}
8292 ins_encode %{
8293 __ imull($dst$$Register, $src$$Address);
8294 %}
8295 ins_pipe(ialu_reg_mem_alu0);
8296 %}
8297
8298
8299 // Integer DIV with Register
8300 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8301 match(Set rax (DivI rax div));
8302 effect(KILL rdx, KILL cr);
8303 size(26);
8304 ins_cost(30*100+10*100);
8305 format %{ "CMP EAX,0x80000000\n\t"
8306 "JNE,s normal\n\t"
8307 "XOR EDX,EDX\n\t"
8308 "CMP ECX,-1\n\t"
8309 "JE,s done\n"
8310 "normal: CDQ\n\t"
8311 "IDIV $div\n\t"
8312 "done:" %}
8313 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8314 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8315 ins_pipe( ialu_reg_reg_alu0 );
8316 %}
8317
8318 // Divide Register Long
8319 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8320 match(Set dst (DivL src1 src2));
8321 effect( KILL cr, KILL cx, KILL bx );
8322 ins_cost(10000);
8323 format %{ "PUSH $src1.hi\n\t"
8324 "PUSH $src1.lo\n\t"
8325 "PUSH $src2.hi\n\t"
8326 "PUSH $src2.lo\n\t"
8327 "CALL SharedRuntime::ldiv\n\t"
8328 "ADD ESP,16" %}
8329 ins_encode( long_div(src1,src2) );
8330 ins_pipe( pipe_slow );
8331 %}
8332
8333 // Integer DIVMOD with Register, both quotient and mod results
8334 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8335 match(DivModI rax div);
8336 effect(KILL cr);
8337 size(26);
8338 ins_cost(30*100+10*100);
8339 format %{ "CMP EAX,0x80000000\n\t"
8340 "JNE,s normal\n\t"
8341 "XOR EDX,EDX\n\t"
8342 "CMP ECX,-1\n\t"
8343 "JE,s done\n"
8344 "normal: CDQ\n\t"
8345 "IDIV $div\n\t"
8346 "done:" %}
8347 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8348 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8349 ins_pipe( pipe_slow );
8350 %}
8351
8352 // Integer MOD with Register
8353 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8354 match(Set rdx (ModI rax div));
8355 effect(KILL rax, KILL cr);
8356
8357 size(26);
8358 ins_cost(300);
8359 format %{ "CDQ\n\t"
8360 "IDIV $div" %}
8361 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8362 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8363 ins_pipe( ialu_reg_reg_alu0 );
8364 %}
8365
8366 // Remainder Register Long
8367 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8368 match(Set dst (ModL src1 src2));
8369 effect( KILL cr, KILL cx, KILL bx );
8370 ins_cost(10000);
8371 format %{ "PUSH $src1.hi\n\t"
8372 "PUSH $src1.lo\n\t"
8373 "PUSH $src2.hi\n\t"
8374 "PUSH $src2.lo\n\t"
8375 "CALL SharedRuntime::lrem\n\t"
8376 "ADD ESP,16" %}
8377 ins_encode( long_mod(src1,src2) );
8378 ins_pipe( pipe_slow );
8379 %}
8380
8381 // Divide Register Long (no special case since divisor != -1)
8382 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8383 match(Set dst (DivL dst imm));
8384 effect( TEMP tmp, TEMP tmp2, KILL cr );
8385 ins_cost(1000);
8386 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8387 "XOR $tmp2,$tmp2\n\t"
8388 "CMP $tmp,EDX\n\t"
8389 "JA,s fast\n\t"
8390 "MOV $tmp2,EAX\n\t"
8391 "MOV EAX,EDX\n\t"
8392 "MOV EDX,0\n\t"
8393 "JLE,s pos\n\t"
8394 "LNEG EAX : $tmp2\n\t"
8395 "DIV $tmp # unsigned division\n\t"
8396 "XCHG EAX,$tmp2\n\t"
8397 "DIV $tmp\n\t"
8398 "LNEG $tmp2 : EAX\n\t"
8399 "JMP,s done\n"
8400 "pos:\n\t"
8401 "DIV $tmp\n\t"
8402 "XCHG EAX,$tmp2\n"
8403 "fast:\n\t"
8404 "DIV $tmp\n"
8405 "done:\n\t"
8406 "MOV EDX,$tmp2\n\t"
8407 "NEG EDX:EAX # if $imm < 0" %}
8408 ins_encode %{
8409 int con = (int)$imm$$constant;
8410 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8411 int pcon = (con > 0) ? con : -con;
8412 Label Lfast, Lpos, Ldone;
8413
8414 __ movl($tmp$$Register, pcon);
8415 __ xorl($tmp2$$Register,$tmp2$$Register);
8416 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8417 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8418
8419 __ movl($tmp2$$Register, $dst$$Register); // save
8420 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8421 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8422 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8423
8424 // Negative dividend.
8425 // convert value to positive to use unsigned division
8426 __ lneg($dst$$Register, $tmp2$$Register);
8427 __ divl($tmp$$Register);
8428 __ xchgl($dst$$Register, $tmp2$$Register);
8429 __ divl($tmp$$Register);
8430 // revert result back to negative
8431 __ lneg($tmp2$$Register, $dst$$Register);
8432 __ jmpb(Ldone);
8433
8434 __ bind(Lpos);
8435 __ divl($tmp$$Register); // Use unsigned division
8436 __ xchgl($dst$$Register, $tmp2$$Register);
8437 // Fallthrow for final divide, tmp2 has 32 bit hi result
8438
8439 __ bind(Lfast);
8440 // fast path: src is positive
8441 __ divl($tmp$$Register); // Use unsigned division
8442
8443 __ bind(Ldone);
8444 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8445 if (con < 0) {
8446 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8447 }
8448 %}
8449 ins_pipe( pipe_slow );
8450 %}
8451
8452 // Remainder Register Long (remainder fit into 32 bits)
8453 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8454 match(Set dst (ModL dst imm));
8455 effect( TEMP tmp, TEMP tmp2, KILL cr );
8456 ins_cost(1000);
8457 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8458 "CMP $tmp,EDX\n\t"
8459 "JA,s fast\n\t"
8460 "MOV $tmp2,EAX\n\t"
8461 "MOV EAX,EDX\n\t"
8462 "MOV EDX,0\n\t"
8463 "JLE,s pos\n\t"
8464 "LNEG EAX : $tmp2\n\t"
8465 "DIV $tmp # unsigned division\n\t"
8466 "MOV EAX,$tmp2\n\t"
8467 "DIV $tmp\n\t"
8468 "NEG EDX\n\t"
8469 "JMP,s done\n"
8470 "pos:\n\t"
8471 "DIV $tmp\n\t"
8472 "MOV EAX,$tmp2\n"
8473 "fast:\n\t"
8474 "DIV $tmp\n"
8475 "done:\n\t"
8476 "MOV EAX,EDX\n\t"
8477 "SAR EDX,31\n\t" %}
8478 ins_encode %{
8479 int con = (int)$imm$$constant;
8480 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8481 int pcon = (con > 0) ? con : -con;
8482 Label Lfast, Lpos, Ldone;
8483
8484 __ movl($tmp$$Register, pcon);
8485 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8486 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8487
8488 __ movl($tmp2$$Register, $dst$$Register); // save
8489 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8490 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8491 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8492
8493 // Negative dividend.
8494 // convert value to positive to use unsigned division
8495 __ lneg($dst$$Register, $tmp2$$Register);
8496 __ divl($tmp$$Register);
8497 __ movl($dst$$Register, $tmp2$$Register);
8498 __ divl($tmp$$Register);
8499 // revert remainder back to negative
8500 __ negl(HIGH_FROM_LOW($dst$$Register));
8501 __ jmpb(Ldone);
8502
8503 __ bind(Lpos);
8504 __ divl($tmp$$Register);
8505 __ movl($dst$$Register, $tmp2$$Register);
8506
8507 __ bind(Lfast);
8508 // fast path: src is positive
8509 __ divl($tmp$$Register);
8510
8511 __ bind(Ldone);
8512 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8513 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8514
8515 %}
8516 ins_pipe( pipe_slow );
8517 %}
8518
8519 // Integer Shift Instructions
8520 // Shift Left by one
8521 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8522 match(Set dst (LShiftI dst shift));
8523 effect(KILL cr);
8524
8525 size(2);
8526 format %{ "SHL $dst,$shift" %}
8527 opcode(0xD1, 0x4); /* D1 /4 */
8528 ins_encode( OpcP, RegOpc( dst ) );
8529 ins_pipe( ialu_reg );
8530 %}
8531
8532 // Shift Left by 8-bit immediate
8533 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8534 match(Set dst (LShiftI dst shift));
8535 effect(KILL cr);
8536
8537 size(3);
8538 format %{ "SHL $dst,$shift" %}
8539 opcode(0xC1, 0x4); /* C1 /4 ib */
8540 ins_encode( RegOpcImm( dst, shift) );
8541 ins_pipe( ialu_reg );
8542 %}
8543
8544 // Shift Left by variable
8545 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8546 match(Set dst (LShiftI dst shift));
8547 effect(KILL cr);
8548
8549 size(2);
8550 format %{ "SHL $dst,$shift" %}
8551 opcode(0xD3, 0x4); /* D3 /4 */
8552 ins_encode( OpcP, RegOpc( dst ) );
8553 ins_pipe( ialu_reg_reg );
8554 %}
8555
8556 // Arithmetic shift right by one
8557 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8558 match(Set dst (RShiftI dst shift));
8559 effect(KILL cr);
8560
8561 size(2);
8562 format %{ "SAR $dst,$shift" %}
8563 opcode(0xD1, 0x7); /* D1 /7 */
8564 ins_encode( OpcP, RegOpc( dst ) );
8565 ins_pipe( ialu_reg );
8566 %}
8567
8568 // Arithmetic shift right by one
8569 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8570 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8571 effect(KILL cr);
8572 format %{ "SAR $dst,$shift" %}
8573 opcode(0xD1, 0x7); /* D1 /7 */
8574 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8575 ins_pipe( ialu_mem_imm );
8576 %}
8577
8578 // Arithmetic Shift Right by 8-bit immediate
8579 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8580 match(Set dst (RShiftI dst shift));
8581 effect(KILL cr);
8582
8583 size(3);
8584 format %{ "SAR $dst,$shift" %}
8585 opcode(0xC1, 0x7); /* C1 /7 ib */
8586 ins_encode( RegOpcImm( dst, shift ) );
8587 ins_pipe( ialu_mem_imm );
8588 %}
8589
8590 // Arithmetic Shift Right by 8-bit immediate
8591 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8592 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8593 effect(KILL cr);
8594
8595 format %{ "SAR $dst,$shift" %}
8596 opcode(0xC1, 0x7); /* C1 /7 ib */
8597 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8598 ins_pipe( ialu_mem_imm );
8599 %}
8600
8601 // Arithmetic Shift Right by variable
8602 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8603 match(Set dst (RShiftI dst shift));
8604 effect(KILL cr);
8605
8606 size(2);
8607 format %{ "SAR $dst,$shift" %}
8608 opcode(0xD3, 0x7); /* D3 /7 */
8609 ins_encode( OpcP, RegOpc( dst ) );
8610 ins_pipe( ialu_reg_reg );
8611 %}
8612
8613 // Logical shift right by one
8614 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8615 match(Set dst (URShiftI dst shift));
8616 effect(KILL cr);
8617
8618 size(2);
8619 format %{ "SHR $dst,$shift" %}
8620 opcode(0xD1, 0x5); /* D1 /5 */
8621 ins_encode( OpcP, RegOpc( dst ) );
8622 ins_pipe( ialu_reg );
8623 %}
8624
8625 // Logical Shift Right by 8-bit immediate
8626 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8627 match(Set dst (URShiftI dst shift));
8628 effect(KILL cr);
8629
8630 size(3);
8631 format %{ "SHR $dst,$shift" %}
8632 opcode(0xC1, 0x5); /* C1 /5 ib */
8633 ins_encode( RegOpcImm( dst, shift) );
8634 ins_pipe( ialu_reg );
8635 %}
8636
8637
8638 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8639 // This idiom is used by the compiler for the i2b bytecode.
8640 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8641 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8642
8643 size(3);
8644 format %{ "MOVSX $dst,$src :8" %}
8645 ins_encode %{
8646 __ movsbl($dst$$Register, $src$$Register);
8647 %}
8648 ins_pipe(ialu_reg_reg);
8649 %}
8650
8651 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8652 // This idiom is used by the compiler the i2s bytecode.
8653 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8654 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8655
8656 size(3);
8657 format %{ "MOVSX $dst,$src :16" %}
8658 ins_encode %{
8659 __ movswl($dst$$Register, $src$$Register);
8660 %}
8661 ins_pipe(ialu_reg_reg);
8662 %}
8663
8664
8665 // Logical Shift Right by variable
8666 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8667 match(Set dst (URShiftI dst shift));
8668 effect(KILL cr);
8669
8670 size(2);
8671 format %{ "SHR $dst,$shift" %}
8672 opcode(0xD3, 0x5); /* D3 /5 */
8673 ins_encode( OpcP, RegOpc( dst ) );
8674 ins_pipe( ialu_reg_reg );
8675 %}
8676
8677
8678 //----------Logical Instructions-----------------------------------------------
8679 //----------Integer Logical Instructions---------------------------------------
8680 // And Instructions
8681 // And Register with Register
8682 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8683 match(Set dst (AndI dst src));
8684 effect(KILL cr);
8685
8686 size(2);
8687 format %{ "AND $dst,$src" %}
8688 opcode(0x23);
8689 ins_encode( OpcP, RegReg( dst, src) );
8690 ins_pipe( ialu_reg_reg );
8691 %}
8692
8693 // And Register with Immediate
8694 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8695 match(Set dst (AndI dst src));
8696 effect(KILL cr);
8697
8698 format %{ "AND $dst,$src" %}
8699 opcode(0x81,0x04); /* Opcode 81 /4 */
8700 // ins_encode( RegImm( dst, src) );
8701 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8702 ins_pipe( ialu_reg );
8703 %}
8704
8705 // And Register with Memory
8706 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8707 match(Set dst (AndI dst (LoadI src)));
8708 effect(KILL cr);
8709
8710 ins_cost(125);
8711 format %{ "AND $dst,$src" %}
8712 opcode(0x23);
8713 ins_encode( OpcP, RegMem( dst, src) );
8714 ins_pipe( ialu_reg_mem );
8715 %}
8716
8717 // And Memory with Register
8718 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8719 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8720 effect(KILL cr);
8721
8722 ins_cost(150);
8723 format %{ "AND $dst,$src" %}
8724 opcode(0x21); /* Opcode 21 /r */
8725 ins_encode( OpcP, RegMem( src, dst ) );
8726 ins_pipe( ialu_mem_reg );
8727 %}
8728
8729 // And Memory with Immediate
8730 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8731 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8732 effect(KILL cr);
8733
8734 ins_cost(125);
8735 format %{ "AND $dst,$src" %}
8736 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8737 // ins_encode( MemImm( dst, src) );
8738 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8739 ins_pipe( ialu_mem_imm );
8740 %}
8741
8742 // BMI1 instructions
8743 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
8744 match(Set dst (AndI (XorI src1 minus_1) src2));
8745 predicate(UseBMI1Instructions);
8746 effect(KILL cr);
8747
8748 format %{ "ANDNL $dst, $src1, $src2" %}
8749
8750 ins_encode %{
8751 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8752 %}
8753 ins_pipe(ialu_reg);
8754 %}
8755
8756 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8757 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8758 predicate(UseBMI1Instructions);
8759 effect(KILL cr);
8760
8761 ins_cost(125);
8762 format %{ "ANDNL $dst, $src1, $src2" %}
8763
8764 ins_encode %{
8765 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8766 %}
8767 ins_pipe(ialu_reg_mem);
8768 %}
8769
8770 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8771 match(Set dst (AndI (SubI imm_zero src) src));
8772 predicate(UseBMI1Instructions);
8773 effect(KILL cr);
8774
8775 format %{ "BLSIL $dst, $src" %}
8776
8777 ins_encode %{
8778 __ blsil($dst$$Register, $src$$Register);
8779 %}
8780 ins_pipe(ialu_reg);
8781 %}
8782
8783 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8784 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8785 predicate(UseBMI1Instructions);
8786 effect(KILL cr);
8787
8788 ins_cost(125);
8789 format %{ "BLSIL $dst, $src" %}
8790
8791 ins_encode %{
8792 __ blsil($dst$$Register, $src$$Address);
8793 %}
8794 ins_pipe(ialu_reg_mem);
8795 %}
8796
8797 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8798 %{
8799 match(Set dst (XorI (AddI src minus_1) src));
8800 predicate(UseBMI1Instructions);
8801 effect(KILL cr);
8802
8803 format %{ "BLSMSKL $dst, $src" %}
8804
8805 ins_encode %{
8806 __ blsmskl($dst$$Register, $src$$Register);
8807 %}
8808
8809 ins_pipe(ialu_reg);
8810 %}
8811
8812 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8813 %{
8814 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
8815 predicate(UseBMI1Instructions);
8816 effect(KILL cr);
8817
8818 ins_cost(125);
8819 format %{ "BLSMSKL $dst, $src" %}
8820
8821 ins_encode %{
8822 __ blsmskl($dst$$Register, $src$$Address);
8823 %}
8824
8825 ins_pipe(ialu_reg_mem);
8826 %}
8827
8828 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8829 %{
8830 match(Set dst (AndI (AddI src minus_1) src) );
8831 predicate(UseBMI1Instructions);
8832 effect(KILL cr);
8833
8834 format %{ "BLSRL $dst, $src" %}
8835
8836 ins_encode %{
8837 __ blsrl($dst$$Register, $src$$Register);
8838 %}
8839
8840 ins_pipe(ialu_reg);
8841 %}
8842
8843 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8844 %{
8845 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8846 predicate(UseBMI1Instructions);
8847 effect(KILL cr);
8848
8849 ins_cost(125);
8850 format %{ "BLSRL $dst, $src" %}
8851
8852 ins_encode %{
8853 __ blsrl($dst$$Register, $src$$Address);
8854 %}
8855
8856 ins_pipe(ialu_reg_mem);
8857 %}
8858
8859 // Or Instructions
8860 // Or Register with Register
8861 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8862 match(Set dst (OrI dst src));
8863 effect(KILL cr);
8864
8865 size(2);
8866 format %{ "OR $dst,$src" %}
8867 opcode(0x0B);
8868 ins_encode( OpcP, RegReg( dst, src) );
8869 ins_pipe( ialu_reg_reg );
8870 %}
8871
8872 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8873 match(Set dst (OrI dst (CastP2X src)));
8874 effect(KILL cr);
8875
8876 size(2);
8877 format %{ "OR $dst,$src" %}
8878 opcode(0x0B);
8879 ins_encode( OpcP, RegReg( dst, src) );
8880 ins_pipe( ialu_reg_reg );
8881 %}
8882
8883
8884 // Or Register with Immediate
8885 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8886 match(Set dst (OrI dst src));
8887 effect(KILL cr);
8888
8889 format %{ "OR $dst,$src" %}
8890 opcode(0x81,0x01); /* Opcode 81 /1 id */
8891 // ins_encode( RegImm( dst, src) );
8892 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8893 ins_pipe( ialu_reg );
8894 %}
8895
8896 // Or Register with Memory
8897 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8898 match(Set dst (OrI dst (LoadI src)));
8899 effect(KILL cr);
8900
8901 ins_cost(125);
8902 format %{ "OR $dst,$src" %}
8903 opcode(0x0B);
8904 ins_encode( OpcP, RegMem( dst, src) );
8905 ins_pipe( ialu_reg_mem );
8906 %}
8907
8908 // Or Memory with Register
8909 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8910 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8911 effect(KILL cr);
8912
8913 ins_cost(150);
8914 format %{ "OR $dst,$src" %}
8915 opcode(0x09); /* Opcode 09 /r */
8916 ins_encode( OpcP, RegMem( src, dst ) );
8917 ins_pipe( ialu_mem_reg );
8918 %}
8919
8920 // Or Memory with Immediate
8921 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8922 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8923 effect(KILL cr);
8924
8925 ins_cost(125);
8926 format %{ "OR $dst,$src" %}
8927 opcode(0x81,0x1); /* Opcode 81 /1 id */
8928 // ins_encode( MemImm( dst, src) );
8929 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8930 ins_pipe( ialu_mem_imm );
8931 %}
8932
8933 // ROL/ROR
8934 // ROL expand
8935 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8936 effect(USE_DEF dst, USE shift, KILL cr);
8937
8938 format %{ "ROL $dst, $shift" %}
8939 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8940 ins_encode( OpcP, RegOpc( dst ));
8941 ins_pipe( ialu_reg );
8942 %}
8943
8944 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8945 effect(USE_DEF dst, USE shift, KILL cr);
8946
8947 format %{ "ROL $dst, $shift" %}
8948 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8949 ins_encode( RegOpcImm(dst, shift) );
8950 ins_pipe(ialu_reg);
8951 %}
8952
8953 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8954 effect(USE_DEF dst, USE shift, KILL cr);
8955
8956 format %{ "ROL $dst, $shift" %}
8957 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8958 ins_encode(OpcP, RegOpc(dst));
8959 ins_pipe( ialu_reg_reg );
8960 %}
8961 // end of ROL expand
8962
8963 // ROL 32bit by one once
8964 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8965 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8966
8967 expand %{
8968 rolI_eReg_imm1(dst, lshift, cr);
8969 %}
8970 %}
8971
8972 // ROL 32bit var by imm8 once
8973 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8974 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8975 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8976
8977 expand %{
8978 rolI_eReg_imm8(dst, lshift, cr);
8979 %}
8980 %}
8981
8982 // ROL 32bit var by var once
8983 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8984 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8985
8986 expand %{
8987 rolI_eReg_CL(dst, shift, cr);
8988 %}
8989 %}
8990
8991 // ROL 32bit var by var once
8992 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8993 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8994
8995 expand %{
8996 rolI_eReg_CL(dst, shift, cr);
8997 %}
8998 %}
8999
9000 // ROR expand
9001 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
9002 effect(USE_DEF dst, USE shift, KILL cr);
9003
9004 format %{ "ROR $dst, $shift" %}
9005 opcode(0xD1,0x1); /* Opcode D1 /1 */
9006 ins_encode( OpcP, RegOpc( dst ) );
9007 ins_pipe( ialu_reg );
9008 %}
9009
9010 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
9011 effect (USE_DEF dst, USE shift, KILL cr);
9012
9013 format %{ "ROR $dst, $shift" %}
9014 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9015 ins_encode( RegOpcImm(dst, shift) );
9016 ins_pipe( ialu_reg );
9017 %}
9018
9019 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9020 effect(USE_DEF dst, USE shift, KILL cr);
9021
9022 format %{ "ROR $dst, $shift" %}
9023 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9024 ins_encode(OpcP, RegOpc(dst));
9025 ins_pipe( ialu_reg_reg );
9026 %}
9027 // end of ROR expand
9028
9029 // ROR right once
9030 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9031 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9032
9033 expand %{
9034 rorI_eReg_imm1(dst, rshift, cr);
9035 %}
9036 %}
9037
9038 // ROR 32bit by immI8 once
9039 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9040 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9041 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9042
9043 expand %{
9044 rorI_eReg_imm8(dst, rshift, cr);
9045 %}
9046 %}
9047
9048 // ROR 32bit var by var once
9049 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9050 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9051
9052 expand %{
9053 rorI_eReg_CL(dst, shift, cr);
9054 %}
9055 %}
9056
9057 // ROR 32bit var by var once
9058 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9059 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9060
9061 expand %{
9062 rorI_eReg_CL(dst, shift, cr);
9063 %}
9064 %}
9065
9066 // Xor Instructions
9067 // Xor Register with Register
9068 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
9069 match(Set dst (XorI dst src));
9070 effect(KILL cr);
9071
9072 size(2);
9073 format %{ "XOR $dst,$src" %}
9074 opcode(0x33);
9075 ins_encode( OpcP, RegReg( dst, src) );
9076 ins_pipe( ialu_reg_reg );
9077 %}
9078
9079 // Xor Register with Immediate -1
9080 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
9081 match(Set dst (XorI dst imm));
9082
9083 size(2);
9084 format %{ "NOT $dst" %}
9085 ins_encode %{
9086 __ notl($dst$$Register);
9087 %}
9088 ins_pipe( ialu_reg );
9089 %}
9090
9091 // Xor Register with Immediate
9092 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
9093 match(Set dst (XorI dst src));
9094 effect(KILL cr);
9095
9096 format %{ "XOR $dst,$src" %}
9097 opcode(0x81,0x06); /* Opcode 81 /6 id */
9098 // ins_encode( RegImm( dst, src) );
9099 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9100 ins_pipe( ialu_reg );
9101 %}
9102
9103 // Xor Register with Memory
9104 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
9105 match(Set dst (XorI dst (LoadI src)));
9106 effect(KILL cr);
9107
9108 ins_cost(125);
9109 format %{ "XOR $dst,$src" %}
9110 opcode(0x33);
9111 ins_encode( OpcP, RegMem(dst, src) );
9112 ins_pipe( ialu_reg_mem );
9113 %}
9114
9115 // Xor Memory with Register
9116 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
9117 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9118 effect(KILL cr);
9119
9120 ins_cost(150);
9121 format %{ "XOR $dst,$src" %}
9122 opcode(0x31); /* Opcode 31 /r */
9123 ins_encode( OpcP, RegMem( src, dst ) );
9124 ins_pipe( ialu_mem_reg );
9125 %}
9126
9127 // Xor Memory with Immediate
9128 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9129 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9130 effect(KILL cr);
9131
9132 ins_cost(125);
9133 format %{ "XOR $dst,$src" %}
9134 opcode(0x81,0x6); /* Opcode 81 /6 id */
9135 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9136 ins_pipe( ialu_mem_imm );
9137 %}
9138
9139 //----------Convert Int to Boolean---------------------------------------------
9140
9141 instruct movI_nocopy(rRegI dst, rRegI src) %{
9142 effect( DEF dst, USE src );
9143 format %{ "MOV $dst,$src" %}
9144 ins_encode( enc_Copy( dst, src) );
9145 ins_pipe( ialu_reg_reg );
9146 %}
9147
9148 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
9149 effect( USE_DEF dst, USE src, KILL cr );
9150
9151 size(4);
9152 format %{ "NEG $dst\n\t"
9153 "ADC $dst,$src" %}
9154 ins_encode( neg_reg(dst),
9155 OpcRegReg(0x13,dst,src) );
9156 ins_pipe( ialu_reg_reg_long );
9157 %}
9158
9159 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
9160 match(Set dst (Conv2B src));
9161
9162 expand %{
9163 movI_nocopy(dst,src);
9164 ci2b(dst,src,cr);
9165 %}
9166 %}
9167
9168 instruct movP_nocopy(rRegI dst, eRegP src) %{
9169 effect( DEF dst, USE src );
9170 format %{ "MOV $dst,$src" %}
9171 ins_encode( enc_Copy( dst, src) );
9172 ins_pipe( ialu_reg_reg );
9173 %}
9174
9175 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
9176 effect( USE_DEF dst, USE src, KILL cr );
9177 format %{ "NEG $dst\n\t"
9178 "ADC $dst,$src" %}
9179 ins_encode( neg_reg(dst),
9180 OpcRegReg(0x13,dst,src) );
9181 ins_pipe( ialu_reg_reg_long );
9182 %}
9183
9184 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
9185 match(Set dst (Conv2B src));
9186
9187 expand %{
9188 movP_nocopy(dst,src);
9189 cp2b(dst,src,cr);
9190 %}
9191 %}
9192
9193 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
9194 match(Set dst (CmpLTMask p q));
9195 effect(KILL cr);
9196 ins_cost(400);
9197
9198 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9199 format %{ "XOR $dst,$dst\n\t"
9200 "CMP $p,$q\n\t"
9201 "SETlt $dst\n\t"
9202 "NEG $dst" %}
9203 ins_encode %{
9204 Register Rp = $p$$Register;
9205 Register Rq = $q$$Register;
9206 Register Rd = $dst$$Register;
9207 Label done;
9208 __ xorl(Rd, Rd);
9209 __ cmpl(Rp, Rq);
9210 __ setb(Assembler::less, Rd);
9211 __ negl(Rd);
9212 %}
9213
9214 ins_pipe(pipe_slow);
9215 %}
9216
9217 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
9218 match(Set dst (CmpLTMask dst zero));
9219 effect(DEF dst, KILL cr);
9220 ins_cost(100);
9221
9222 format %{ "SAR $dst,31\t# cmpLTMask0" %}
9223 ins_encode %{
9224 __ sarl($dst$$Register, 31);
9225 %}
9226 ins_pipe(ialu_reg);
9227 %}
9228
9229 /* better to save a register than avoid a branch */
9230 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9231 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9232 effect(KILL cr);
9233 ins_cost(400);
9234 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
9235 "JGE done\n\t"
9236 "ADD $p,$y\n"
9237 "done: " %}
9238 ins_encode %{
9239 Register Rp = $p$$Register;
9240 Register Rq = $q$$Register;
9241 Register Ry = $y$$Register;
9242 Label done;
9243 __ subl(Rp, Rq);
9244 __ jccb(Assembler::greaterEqual, done);
9245 __ addl(Rp, Ry);
9246 __ bind(done);
9247 %}
9248
9249 ins_pipe(pipe_cmplt);
9250 %}
9251
9252 /* better to save a register than avoid a branch */
9253 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9254 match(Set y (AndI (CmpLTMask p q) y));
9255 effect(KILL cr);
9256
9257 ins_cost(300);
9258
9259 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
9260 "JLT done\n\t"
9261 "XORL $y, $y\n"
9262 "done: " %}
9263 ins_encode %{
9264 Register Rp = $p$$Register;
9265 Register Rq = $q$$Register;
9266 Register Ry = $y$$Register;
9267 Label done;
9268 __ cmpl(Rp, Rq);
9269 __ jccb(Assembler::less, done);
9270 __ xorl(Ry, Ry);
9271 __ bind(done);
9272 %}
9273
9274 ins_pipe(pipe_cmplt);
9275 %}
9276
9277 /* If I enable this, I encourage spilling in the inner loop of compress.
9278 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9279 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9280 */
9281
9282 //----------Long Instructions------------------------------------------------
9283 // Add Long Register with Register
9284 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9285 match(Set dst (AddL dst src));
9286 effect(KILL cr);
9287 ins_cost(200);
9288 format %{ "ADD $dst.lo,$src.lo\n\t"
9289 "ADC $dst.hi,$src.hi" %}
9290 opcode(0x03, 0x13);
9291 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9292 ins_pipe( ialu_reg_reg_long );
9293 %}
9294
9295 // Add Long Register with Immediate
9296 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9297 match(Set dst (AddL dst src));
9298 effect(KILL cr);
9299 format %{ "ADD $dst.lo,$src.lo\n\t"
9300 "ADC $dst.hi,$src.hi" %}
9301 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9302 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9303 ins_pipe( ialu_reg_long );
9304 %}
9305
9306 // Add Long Register with Memory
9307 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9308 match(Set dst (AddL dst (LoadL mem)));
9309 effect(KILL cr);
9310 ins_cost(125);
9311 format %{ "ADD $dst.lo,$mem\n\t"
9312 "ADC $dst.hi,$mem+4" %}
9313 opcode(0x03, 0x13);
9314 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9315 ins_pipe( ialu_reg_long_mem );
9316 %}
9317
9318 // Subtract Long Register with Register.
9319 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9320 match(Set dst (SubL dst src));
9321 effect(KILL cr);
9322 ins_cost(200);
9323 format %{ "SUB $dst.lo,$src.lo\n\t"
9324 "SBB $dst.hi,$src.hi" %}
9325 opcode(0x2B, 0x1B);
9326 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9327 ins_pipe( ialu_reg_reg_long );
9328 %}
9329
9330 // Subtract Long Register with Immediate
9331 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9332 match(Set dst (SubL dst src));
9333 effect(KILL cr);
9334 format %{ "SUB $dst.lo,$src.lo\n\t"
9335 "SBB $dst.hi,$src.hi" %}
9336 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9337 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9338 ins_pipe( ialu_reg_long );
9339 %}
9340
9341 // Subtract Long Register with Memory
9342 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9343 match(Set dst (SubL dst (LoadL mem)));
9344 effect(KILL cr);
9345 ins_cost(125);
9346 format %{ "SUB $dst.lo,$mem\n\t"
9347 "SBB $dst.hi,$mem+4" %}
9348 opcode(0x2B, 0x1B);
9349 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9350 ins_pipe( ialu_reg_long_mem );
9351 %}
9352
9353 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9354 match(Set dst (SubL zero dst));
9355 effect(KILL cr);
9356 ins_cost(300);
9357 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9358 ins_encode( neg_long(dst) );
9359 ins_pipe( ialu_reg_reg_long );
9360 %}
9361
9362 // And Long Register with Register
9363 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9364 match(Set dst (AndL dst src));
9365 effect(KILL cr);
9366 format %{ "AND $dst.lo,$src.lo\n\t"
9367 "AND $dst.hi,$src.hi" %}
9368 opcode(0x23,0x23);
9369 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9370 ins_pipe( ialu_reg_reg_long );
9371 %}
9372
9373 // And Long Register with Immediate
9374 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9375 match(Set dst (AndL dst src));
9376 effect(KILL cr);
9377 format %{ "AND $dst.lo,$src.lo\n\t"
9378 "AND $dst.hi,$src.hi" %}
9379 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9380 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9381 ins_pipe( ialu_reg_long );
9382 %}
9383
9384 // And Long Register with Memory
9385 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9386 match(Set dst (AndL dst (LoadL mem)));
9387 effect(KILL cr);
9388 ins_cost(125);
9389 format %{ "AND $dst.lo,$mem\n\t"
9390 "AND $dst.hi,$mem+4" %}
9391 opcode(0x23, 0x23);
9392 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9393 ins_pipe( ialu_reg_long_mem );
9394 %}
9395
9396 // BMI1 instructions
9397 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
9398 match(Set dst (AndL (XorL src1 minus_1) src2));
9399 predicate(UseBMI1Instructions);
9400 effect(KILL cr, TEMP dst);
9401
9402 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
9403 "ANDNL $dst.hi, $src1.hi, $src2.hi"
9404 %}
9405
9406 ins_encode %{
9407 Register Rdst = $dst$$Register;
9408 Register Rsrc1 = $src1$$Register;
9409 Register Rsrc2 = $src2$$Register;
9410 __ andnl(Rdst, Rsrc1, Rsrc2);
9411 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
9412 %}
9413 ins_pipe(ialu_reg_reg_long);
9414 %}
9415
9416 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
9417 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
9418 predicate(UseBMI1Instructions);
9419 effect(KILL cr, TEMP dst);
9420
9421 ins_cost(125);
9422 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
9423 "ANDNL $dst.hi, $src1.hi, $src2+4"
9424 %}
9425
9426 ins_encode %{
9427 Register Rdst = $dst$$Register;
9428 Register Rsrc1 = $src1$$Register;
9429 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
9430
9431 __ andnl(Rdst, Rsrc1, $src2$$Address);
9432 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
9433 %}
9434 ins_pipe(ialu_reg_mem);
9435 %}
9436
9437 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
9438 match(Set dst (AndL (SubL imm_zero src) src));
9439 predicate(UseBMI1Instructions);
9440 effect(KILL cr, TEMP dst);
9441
9442 format %{ "MOVL $dst.hi, 0\n\t"
9443 "BLSIL $dst.lo, $src.lo\n\t"
9444 "JNZ done\n\t"
9445 "BLSIL $dst.hi, $src.hi\n"
9446 "done:"
9447 %}
9448
9449 ins_encode %{
9450 Label done;
9451 Register Rdst = $dst$$Register;
9452 Register Rsrc = $src$$Register;
9453 __ movl(HIGH_FROM_LOW(Rdst), 0);
9454 __ blsil(Rdst, Rsrc);
9455 __ jccb(Assembler::notZero, done);
9456 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9457 __ bind(done);
9458 %}
9459 ins_pipe(ialu_reg);
9460 %}
9461
9462 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
9463 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9464 predicate(UseBMI1Instructions);
9465 effect(KILL cr, TEMP dst);
9466
9467 ins_cost(125);
9468 format %{ "MOVL $dst.hi, 0\n\t"
9469 "BLSIL $dst.lo, $src\n\t"
9470 "JNZ done\n\t"
9471 "BLSIL $dst.hi, $src+4\n"
9472 "done:"
9473 %}
9474
9475 ins_encode %{
9476 Label done;
9477 Register Rdst = $dst$$Register;
9478 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9479
9480 __ movl(HIGH_FROM_LOW(Rdst), 0);
9481 __ blsil(Rdst, $src$$Address);
9482 __ jccb(Assembler::notZero, done);
9483 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
9484 __ bind(done);
9485 %}
9486 ins_pipe(ialu_reg_mem);
9487 %}
9488
9489 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
9490 %{
9491 match(Set dst (XorL (AddL src minus_1) src));
9492 predicate(UseBMI1Instructions);
9493 effect(KILL cr, TEMP dst);
9494
9495 format %{ "MOVL $dst.hi, 0\n\t"
9496 "BLSMSKL $dst.lo, $src.lo\n\t"
9497 "JNC done\n\t"
9498 "BLSMSKL $dst.hi, $src.hi\n"
9499 "done:"
9500 %}
9501
9502 ins_encode %{
9503 Label done;
9504 Register Rdst = $dst$$Register;
9505 Register Rsrc = $src$$Register;
9506 __ movl(HIGH_FROM_LOW(Rdst), 0);
9507 __ blsmskl(Rdst, Rsrc);
9508 __ jccb(Assembler::carryClear, done);
9509 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9510 __ bind(done);
9511 %}
9512
9513 ins_pipe(ialu_reg);
9514 %}
9515
9516 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
9517 %{
9518 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
9519 predicate(UseBMI1Instructions);
9520 effect(KILL cr, TEMP dst);
9521
9522 ins_cost(125);
9523 format %{ "MOVL $dst.hi, 0\n\t"
9524 "BLSMSKL $dst.lo, $src\n\t"
9525 "JNC done\n\t"
9526 "BLSMSKL $dst.hi, $src+4\n"
9527 "done:"
9528 %}
9529
9530 ins_encode %{
9531 Label done;
9532 Register Rdst = $dst$$Register;
9533 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9534
9535 __ movl(HIGH_FROM_LOW(Rdst), 0);
9536 __ blsmskl(Rdst, $src$$Address);
9537 __ jccb(Assembler::carryClear, done);
9538 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
9539 __ bind(done);
9540 %}
9541
9542 ins_pipe(ialu_reg_mem);
9543 %}
9544
9545 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
9546 %{
9547 match(Set dst (AndL (AddL src minus_1) src) );
9548 predicate(UseBMI1Instructions);
9549 effect(KILL cr, TEMP dst);
9550
9551 format %{ "MOVL $dst.hi, $src.hi\n\t"
9552 "BLSRL $dst.lo, $src.lo\n\t"
9553 "JNC done\n\t"
9554 "BLSRL $dst.hi, $src.hi\n"
9555 "done:"
9556 %}
9557
9558 ins_encode %{
9559 Label done;
9560 Register Rdst = $dst$$Register;
9561 Register Rsrc = $src$$Register;
9562 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9563 __ blsrl(Rdst, Rsrc);
9564 __ jccb(Assembler::carryClear, done);
9565 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9566 __ bind(done);
9567 %}
9568
9569 ins_pipe(ialu_reg);
9570 %}
9571
9572 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
9573 %{
9574 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
9575 predicate(UseBMI1Instructions);
9576 effect(KILL cr, TEMP dst);
9577
9578 ins_cost(125);
9579 format %{ "MOVL $dst.hi, $src+4\n\t"
9580 "BLSRL $dst.lo, $src\n\t"
9581 "JNC done\n\t"
9582 "BLSRL $dst.hi, $src+4\n"
9583 "done:"
9584 %}
9585
9586 ins_encode %{
9587 Label done;
9588 Register Rdst = $dst$$Register;
9589 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9590 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
9591 __ blsrl(Rdst, $src$$Address);
9592 __ jccb(Assembler::carryClear, done);
9593 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
9594 __ bind(done);
9595 %}
9596
9597 ins_pipe(ialu_reg_mem);
9598 %}
9599
9600 // Or Long Register with Register
9601 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9602 match(Set dst (OrL dst src));
9603 effect(KILL cr);
9604 format %{ "OR $dst.lo,$src.lo\n\t"
9605 "OR $dst.hi,$src.hi" %}
9606 opcode(0x0B,0x0B);
9607 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9608 ins_pipe( ialu_reg_reg_long );
9609 %}
9610
9611 // Or Long Register with Immediate
9612 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9613 match(Set dst (OrL dst src));
9614 effect(KILL cr);
9615 format %{ "OR $dst.lo,$src.lo\n\t"
9616 "OR $dst.hi,$src.hi" %}
9617 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9618 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9619 ins_pipe( ialu_reg_long );
9620 %}
9621
9622 // Or Long Register with Memory
9623 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9624 match(Set dst (OrL dst (LoadL mem)));
9625 effect(KILL cr);
9626 ins_cost(125);
9627 format %{ "OR $dst.lo,$mem\n\t"
9628 "OR $dst.hi,$mem+4" %}
9629 opcode(0x0B,0x0B);
9630 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9631 ins_pipe( ialu_reg_long_mem );
9632 %}
9633
9634 // Xor Long Register with Register
9635 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9636 match(Set dst (XorL dst src));
9637 effect(KILL cr);
9638 format %{ "XOR $dst.lo,$src.lo\n\t"
9639 "XOR $dst.hi,$src.hi" %}
9640 opcode(0x33,0x33);
9641 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9642 ins_pipe( ialu_reg_reg_long );
9643 %}
9644
9645 // Xor Long Register with Immediate -1
9646 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9647 match(Set dst (XorL dst imm));
9648 format %{ "NOT $dst.lo\n\t"
9649 "NOT $dst.hi" %}
9650 ins_encode %{
9651 __ notl($dst$$Register);
9652 __ notl(HIGH_FROM_LOW($dst$$Register));
9653 %}
9654 ins_pipe( ialu_reg_long );
9655 %}
9656
9657 // Xor Long Register with Immediate
9658 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9659 match(Set dst (XorL dst src));
9660 effect(KILL cr);
9661 format %{ "XOR $dst.lo,$src.lo\n\t"
9662 "XOR $dst.hi,$src.hi" %}
9663 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9664 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9665 ins_pipe( ialu_reg_long );
9666 %}
9667
9668 // Xor Long Register with Memory
9669 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9670 match(Set dst (XorL dst (LoadL mem)));
9671 effect(KILL cr);
9672 ins_cost(125);
9673 format %{ "XOR $dst.lo,$mem\n\t"
9674 "XOR $dst.hi,$mem+4" %}
9675 opcode(0x33,0x33);
9676 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9677 ins_pipe( ialu_reg_long_mem );
9678 %}
9679
9680 // Shift Left Long by 1
9681 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9682 predicate(UseNewLongLShift);
9683 match(Set dst (LShiftL dst cnt));
9684 effect(KILL cr);
9685 ins_cost(100);
9686 format %{ "ADD $dst.lo,$dst.lo\n\t"
9687 "ADC $dst.hi,$dst.hi" %}
9688 ins_encode %{
9689 __ addl($dst$$Register,$dst$$Register);
9690 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9691 %}
9692 ins_pipe( ialu_reg_long );
9693 %}
9694
9695 // Shift Left Long by 2
9696 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9697 predicate(UseNewLongLShift);
9698 match(Set dst (LShiftL dst cnt));
9699 effect(KILL cr);
9700 ins_cost(100);
9701 format %{ "ADD $dst.lo,$dst.lo\n\t"
9702 "ADC $dst.hi,$dst.hi\n\t"
9703 "ADD $dst.lo,$dst.lo\n\t"
9704 "ADC $dst.hi,$dst.hi" %}
9705 ins_encode %{
9706 __ addl($dst$$Register,$dst$$Register);
9707 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9708 __ addl($dst$$Register,$dst$$Register);
9709 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9710 %}
9711 ins_pipe( ialu_reg_long );
9712 %}
9713
9714 // Shift Left Long by 3
9715 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9716 predicate(UseNewLongLShift);
9717 match(Set dst (LShiftL dst cnt));
9718 effect(KILL cr);
9719 ins_cost(100);
9720 format %{ "ADD $dst.lo,$dst.lo\n\t"
9721 "ADC $dst.hi,$dst.hi\n\t"
9722 "ADD $dst.lo,$dst.lo\n\t"
9723 "ADC $dst.hi,$dst.hi\n\t"
9724 "ADD $dst.lo,$dst.lo\n\t"
9725 "ADC $dst.hi,$dst.hi" %}
9726 ins_encode %{
9727 __ addl($dst$$Register,$dst$$Register);
9728 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9729 __ addl($dst$$Register,$dst$$Register);
9730 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9731 __ addl($dst$$Register,$dst$$Register);
9732 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9733 %}
9734 ins_pipe( ialu_reg_long );
9735 %}
9736
9737 // Shift Left Long by 1-31
9738 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9739 match(Set dst (LShiftL dst cnt));
9740 effect(KILL cr);
9741 ins_cost(200);
9742 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9743 "SHL $dst.lo,$cnt" %}
9744 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9745 ins_encode( move_long_small_shift(dst,cnt) );
9746 ins_pipe( ialu_reg_long );
9747 %}
9748
9749 // Shift Left Long by 32-63
9750 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9751 match(Set dst (LShiftL dst cnt));
9752 effect(KILL cr);
9753 ins_cost(300);
9754 format %{ "MOV $dst.hi,$dst.lo\n"
9755 "\tSHL $dst.hi,$cnt-32\n"
9756 "\tXOR $dst.lo,$dst.lo" %}
9757 opcode(0xC1, 0x4); /* C1 /4 ib */
9758 ins_encode( move_long_big_shift_clr(dst,cnt) );
9759 ins_pipe( ialu_reg_long );
9760 %}
9761
9762 // Shift Left Long by variable
9763 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9764 match(Set dst (LShiftL dst shift));
9765 effect(KILL cr);
9766 ins_cost(500+200);
9767 size(17);
9768 format %{ "TEST $shift,32\n\t"
9769 "JEQ,s small\n\t"
9770 "MOV $dst.hi,$dst.lo\n\t"
9771 "XOR $dst.lo,$dst.lo\n"
9772 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9773 "SHL $dst.lo,$shift" %}
9774 ins_encode( shift_left_long( dst, shift ) );
9775 ins_pipe( pipe_slow );
9776 %}
9777
9778 // Shift Right Long by 1-31
9779 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9780 match(Set dst (URShiftL dst cnt));
9781 effect(KILL cr);
9782 ins_cost(200);
9783 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9784 "SHR $dst.hi,$cnt" %}
9785 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9786 ins_encode( move_long_small_shift(dst,cnt) );
9787 ins_pipe( ialu_reg_long );
9788 %}
9789
9790 // Shift Right Long by 32-63
9791 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9792 match(Set dst (URShiftL dst cnt));
9793 effect(KILL cr);
9794 ins_cost(300);
9795 format %{ "MOV $dst.lo,$dst.hi\n"
9796 "\tSHR $dst.lo,$cnt-32\n"
9797 "\tXOR $dst.hi,$dst.hi" %}
9798 opcode(0xC1, 0x5); /* C1 /5 ib */
9799 ins_encode( move_long_big_shift_clr(dst,cnt) );
9800 ins_pipe( ialu_reg_long );
9801 %}
9802
9803 // Shift Right Long by variable
9804 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9805 match(Set dst (URShiftL dst shift));
9806 effect(KILL cr);
9807 ins_cost(600);
9808 size(17);
9809 format %{ "TEST $shift,32\n\t"
9810 "JEQ,s small\n\t"
9811 "MOV $dst.lo,$dst.hi\n\t"
9812 "XOR $dst.hi,$dst.hi\n"
9813 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9814 "SHR $dst.hi,$shift" %}
9815 ins_encode( shift_right_long( dst, shift ) );
9816 ins_pipe( pipe_slow );
9817 %}
9818
9819 // Shift Right Long by 1-31
9820 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9821 match(Set dst (RShiftL dst cnt));
9822 effect(KILL cr);
9823 ins_cost(200);
9824 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9825 "SAR $dst.hi,$cnt" %}
9826 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9827 ins_encode( move_long_small_shift(dst,cnt) );
9828 ins_pipe( ialu_reg_long );
9829 %}
9830
9831 // Shift Right Long by 32-63
9832 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9833 match(Set dst (RShiftL dst cnt));
9834 effect(KILL cr);
9835 ins_cost(300);
9836 format %{ "MOV $dst.lo,$dst.hi\n"
9837 "\tSAR $dst.lo,$cnt-32\n"
9838 "\tSAR $dst.hi,31" %}
9839 opcode(0xC1, 0x7); /* C1 /7 ib */
9840 ins_encode( move_long_big_shift_sign(dst,cnt) );
9841 ins_pipe( ialu_reg_long );
9842 %}
9843
9844 // Shift Right arithmetic Long by variable
9845 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9846 match(Set dst (RShiftL dst shift));
9847 effect(KILL cr);
9848 ins_cost(600);
9849 size(18);
9850 format %{ "TEST $shift,32\n\t"
9851 "JEQ,s small\n\t"
9852 "MOV $dst.lo,$dst.hi\n\t"
9853 "SAR $dst.hi,31\n"
9854 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9855 "SAR $dst.hi,$shift" %}
9856 ins_encode( shift_right_arith_long( dst, shift ) );
9857 ins_pipe( pipe_slow );
9858 %}
9859
9860
9861 //----------Double Instructions------------------------------------------------
9862 // Double Math
9863
9864 // Compare & branch
9865
9866 // P6 version of float compare, sets condition codes in EFLAGS
9867 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9868 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9869 match(Set cr (CmpD src1 src2));
9870 effect(KILL rax);
9871 ins_cost(150);
9872 format %{ "FLD $src1\n\t"
9873 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9874 "JNP exit\n\t"
9875 "MOV ah,1 // saw a NaN, set CF\n\t"
9876 "SAHF\n"
9877 "exit:\tNOP // avoid branch to branch" %}
9878 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9879 ins_encode( Push_Reg_DPR(src1),
9880 OpcP, RegOpc(src2),
9881 cmpF_P6_fixup );
9882 ins_pipe( pipe_slow );
9883 %}
9884
9885 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9886 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9887 match(Set cr (CmpD src1 src2));
9888 ins_cost(150);
9889 format %{ "FLD $src1\n\t"
9890 "FUCOMIP ST,$src2 // P6 instruction" %}
9891 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9892 ins_encode( Push_Reg_DPR(src1),
9893 OpcP, RegOpc(src2));
9894 ins_pipe( pipe_slow );
9895 %}
9896
9897 // Compare & branch
9898 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9899 predicate(UseSSE<=1);
9900 match(Set cr (CmpD src1 src2));
9901 effect(KILL rax);
9902 ins_cost(200);
9903 format %{ "FLD $src1\n\t"
9904 "FCOMp $src2\n\t"
9905 "FNSTSW AX\n\t"
9906 "TEST AX,0x400\n\t"
9907 "JZ,s flags\n\t"
9908 "MOV AH,1\t# unordered treat as LT\n"
9909 "flags:\tSAHF" %}
9910 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9911 ins_encode( Push_Reg_DPR(src1),
9912 OpcP, RegOpc(src2),
9913 fpu_flags);
9914 ins_pipe( pipe_slow );
9915 %}
9916
9917 // Compare vs zero into -1,0,1
9918 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9919 predicate(UseSSE<=1);
9920 match(Set dst (CmpD3 src1 zero));
9921 effect(KILL cr, KILL rax);
9922 ins_cost(280);
9923 format %{ "FTSTD $dst,$src1" %}
9924 opcode(0xE4, 0xD9);
9925 ins_encode( Push_Reg_DPR(src1),
9926 OpcS, OpcP, PopFPU,
9927 CmpF_Result(dst));
9928 ins_pipe( pipe_slow );
9929 %}
9930
9931 // Compare into -1,0,1
9932 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9933 predicate(UseSSE<=1);
9934 match(Set dst (CmpD3 src1 src2));
9935 effect(KILL cr, KILL rax);
9936 ins_cost(300);
9937 format %{ "FCMPD $dst,$src1,$src2" %}
9938 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9939 ins_encode( Push_Reg_DPR(src1),
9940 OpcP, RegOpc(src2),
9941 CmpF_Result(dst));
9942 ins_pipe( pipe_slow );
9943 %}
9944
9945 // float compare and set condition codes in EFLAGS by XMM regs
9946 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9947 predicate(UseSSE>=2);
9948 match(Set cr (CmpD src1 src2));
9949 ins_cost(145);
9950 format %{ "UCOMISD $src1,$src2\n\t"
9951 "JNP,s exit\n\t"
9952 "PUSHF\t# saw NaN, set CF\n\t"
9953 "AND [rsp], #0xffffff2b\n\t"
9954 "POPF\n"
9955 "exit:" %}
9956 ins_encode %{
9957 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9958 emit_cmpfp_fixup(_masm);
9959 %}
9960 ins_pipe( pipe_slow );
9961 %}
9962
9963 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9964 predicate(UseSSE>=2);
9965 match(Set cr (CmpD src1 src2));
9966 ins_cost(100);
9967 format %{ "UCOMISD $src1,$src2" %}
9968 ins_encode %{
9969 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9970 %}
9971 ins_pipe( pipe_slow );
9972 %}
9973
9974 // float compare and set condition codes in EFLAGS by XMM regs
9975 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9976 predicate(UseSSE>=2);
9977 match(Set cr (CmpD src1 (LoadD src2)));
9978 ins_cost(145);
9979 format %{ "UCOMISD $src1,$src2\n\t"
9980 "JNP,s exit\n\t"
9981 "PUSHF\t# saw NaN, set CF\n\t"
9982 "AND [rsp], #0xffffff2b\n\t"
9983 "POPF\n"
9984 "exit:" %}
9985 ins_encode %{
9986 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9987 emit_cmpfp_fixup(_masm);
9988 %}
9989 ins_pipe( pipe_slow );
9990 %}
9991
9992 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9993 predicate(UseSSE>=2);
9994 match(Set cr (CmpD src1 (LoadD src2)));
9995 ins_cost(100);
9996 format %{ "UCOMISD $src1,$src2" %}
9997 ins_encode %{
9998 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9999 %}
10000 ins_pipe( pipe_slow );
10001 %}
10002
10003 // Compare into -1,0,1 in XMM
10004 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
10005 predicate(UseSSE>=2);
10006 match(Set dst (CmpD3 src1 src2));
10007 effect(KILL cr);
10008 ins_cost(255);
10009 format %{ "UCOMISD $src1, $src2\n\t"
10010 "MOV $dst, #-1\n\t"
10011 "JP,s done\n\t"
10012 "JB,s done\n\t"
10013 "SETNE $dst\n\t"
10014 "MOVZB $dst, $dst\n"
10015 "done:" %}
10016 ins_encode %{
10017 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10018 emit_cmpfp3(_masm, $dst$$Register);
10019 %}
10020 ins_pipe( pipe_slow );
10021 %}
10022
10023 // Compare into -1,0,1 in XMM and memory
10024 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
10025 predicate(UseSSE>=2);
10026 match(Set dst (CmpD3 src1 (LoadD src2)));
10027 effect(KILL cr);
10028 ins_cost(275);
10029 format %{ "UCOMISD $src1, $src2\n\t"
10030 "MOV $dst, #-1\n\t"
10031 "JP,s done\n\t"
10032 "JB,s done\n\t"
10033 "SETNE $dst\n\t"
10034 "MOVZB $dst, $dst\n"
10035 "done:" %}
10036 ins_encode %{
10037 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10038 emit_cmpfp3(_masm, $dst$$Register);
10039 %}
10040 ins_pipe( pipe_slow );
10041 %}
10042
10043
10044 instruct subDPR_reg(regDPR dst, regDPR src) %{
10045 predicate (UseSSE <=1);
10046 match(Set dst (SubD dst src));
10047
10048 format %{ "FLD $src\n\t"
10049 "DSUBp $dst,ST" %}
10050 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10051 ins_cost(150);
10052 ins_encode( Push_Reg_DPR(src),
10053 OpcP, RegOpc(dst) );
10054 ins_pipe( fpu_reg_reg );
10055 %}
10056
10057 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
10058 predicate (UseSSE <=1);
10059 match(Set dst (RoundDouble (SubD src1 src2)));
10060 ins_cost(250);
10061
10062 format %{ "FLD $src2\n\t"
10063 "DSUB ST,$src1\n\t"
10064 "FSTP_D $dst\t# D-round" %}
10065 opcode(0xD8, 0x5);
10066 ins_encode( Push_Reg_DPR(src2),
10067 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
10068 ins_pipe( fpu_mem_reg_reg );
10069 %}
10070
10071
10072 instruct subDPR_reg_mem(regDPR dst, memory src) %{
10073 predicate (UseSSE <=1);
10074 match(Set dst (SubD dst (LoadD src)));
10075 ins_cost(150);
10076
10077 format %{ "FLD $src\n\t"
10078 "DSUBp $dst,ST" %}
10079 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10080 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10081 OpcP, RegOpc(dst) );
10082 ins_pipe( fpu_reg_mem );
10083 %}
10084
10085 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
10086 predicate (UseSSE<=1);
10087 match(Set dst (AbsD src));
10088 ins_cost(100);
10089 format %{ "FABS" %}
10090 opcode(0xE1, 0xD9);
10091 ins_encode( OpcS, OpcP );
10092 ins_pipe( fpu_reg_reg );
10093 %}
10094
10095 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
10096 predicate(UseSSE<=1);
10097 match(Set dst (NegD src));
10098 ins_cost(100);
10099 format %{ "FCHS" %}
10100 opcode(0xE0, 0xD9);
10101 ins_encode( OpcS, OpcP );
10102 ins_pipe( fpu_reg_reg );
10103 %}
10104
10105 instruct addDPR_reg(regDPR dst, regDPR src) %{
10106 predicate(UseSSE<=1);
10107 match(Set dst (AddD dst src));
10108 format %{ "FLD $src\n\t"
10109 "DADD $dst,ST" %}
10110 size(4);
10111 ins_cost(150);
10112 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10113 ins_encode( Push_Reg_DPR(src),
10114 OpcP, RegOpc(dst) );
10115 ins_pipe( fpu_reg_reg );
10116 %}
10117
10118
10119 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
10120 predicate(UseSSE<=1);
10121 match(Set dst (RoundDouble (AddD src1 src2)));
10122 ins_cost(250);
10123
10124 format %{ "FLD $src2\n\t"
10125 "DADD ST,$src1\n\t"
10126 "FSTP_D $dst\t# D-round" %}
10127 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10128 ins_encode( Push_Reg_DPR(src2),
10129 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
10130 ins_pipe( fpu_mem_reg_reg );
10131 %}
10132
10133
10134 instruct addDPR_reg_mem(regDPR dst, memory src) %{
10135 predicate(UseSSE<=1);
10136 match(Set dst (AddD dst (LoadD src)));
10137 ins_cost(150);
10138
10139 format %{ "FLD $src\n\t"
10140 "DADDp $dst,ST" %}
10141 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10142 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10143 OpcP, RegOpc(dst) );
10144 ins_pipe( fpu_reg_mem );
10145 %}
10146
10147 // add-to-memory
10148 instruct addDPR_mem_reg(memory dst, regDPR src) %{
10149 predicate(UseSSE<=1);
10150 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10151 ins_cost(150);
10152
10153 format %{ "FLD_D $dst\n\t"
10154 "DADD ST,$src\n\t"
10155 "FST_D $dst" %}
10156 opcode(0xDD, 0x0);
10157 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10158 Opcode(0xD8), RegOpc(src),
10159 set_instruction_start,
10160 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10161 ins_pipe( fpu_reg_mem );
10162 %}
10163
10164 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
10165 predicate(UseSSE<=1);
10166 match(Set dst (AddD dst con));
10167 ins_cost(125);
10168 format %{ "FLD1\n\t"
10169 "DADDp $dst,ST" %}
10170 ins_encode %{
10171 __ fld1();
10172 __ faddp($dst$$reg);
10173 %}
10174 ins_pipe(fpu_reg);
10175 %}
10176
10177 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
10178 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10179 match(Set dst (AddD dst con));
10180 ins_cost(200);
10181 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10182 "DADDp $dst,ST" %}
10183 ins_encode %{
10184 __ fld_d($constantaddress($con));
10185 __ faddp($dst$$reg);
10186 %}
10187 ins_pipe(fpu_reg_mem);
10188 %}
10189
10190 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
10191 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10192 match(Set dst (RoundDouble (AddD src con)));
10193 ins_cost(200);
10194 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10195 "DADD ST,$src\n\t"
10196 "FSTP_D $dst\t# D-round" %}
10197 ins_encode %{
10198 __ fld_d($constantaddress($con));
10199 __ fadd($src$$reg);
10200 __ fstp_d(Address(rsp, $dst$$disp));
10201 %}
10202 ins_pipe(fpu_mem_reg_con);
10203 %}
10204
10205 instruct mulDPR_reg(regDPR dst, regDPR src) %{
10206 predicate(UseSSE<=1);
10207 match(Set dst (MulD dst src));
10208 format %{ "FLD $src\n\t"
10209 "DMULp $dst,ST" %}
10210 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10211 ins_cost(150);
10212 ins_encode( Push_Reg_DPR(src),
10213 OpcP, RegOpc(dst) );
10214 ins_pipe( fpu_reg_reg );
10215 %}
10216
10217 // Strict FP instruction biases argument before multiply then
10218 // biases result to avoid double rounding of subnormals.
10219 //
10220 // scale arg1 by multiplying arg1 by 2^(-15360)
10221 // load arg2
10222 // multiply scaled arg1 by arg2
10223 // rescale product by 2^(15360)
10224 //
10225 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
10226 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10227 match(Set dst (MulD dst src));
10228 ins_cost(1); // Select this instruction for all strict FP double multiplies
10229
10230 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10231 "DMULp $dst,ST\n\t"
10232 "FLD $src\n\t"
10233 "DMULp $dst,ST\n\t"
10234 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10235 "DMULp $dst,ST\n\t" %}
10236 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10237 ins_encode( strictfp_bias1(dst),
10238 Push_Reg_DPR(src),
10239 OpcP, RegOpc(dst),
10240 strictfp_bias2(dst) );
10241 ins_pipe( fpu_reg_reg );
10242 %}
10243
10244 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
10245 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10246 match(Set dst (MulD dst con));
10247 ins_cost(200);
10248 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10249 "DMULp $dst,ST" %}
10250 ins_encode %{
10251 __ fld_d($constantaddress($con));
10252 __ fmulp($dst$$reg);
10253 %}
10254 ins_pipe(fpu_reg_mem);
10255 %}
10256
10257
10258 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
10259 predicate( UseSSE<=1 );
10260 match(Set dst (MulD dst (LoadD src)));
10261 ins_cost(200);
10262 format %{ "FLD_D $src\n\t"
10263 "DMULp $dst,ST" %}
10264 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10265 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10266 OpcP, RegOpc(dst) );
10267 ins_pipe( fpu_reg_mem );
10268 %}
10269
10270 //
10271 // Cisc-alternate to reg-reg multiply
10272 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
10273 predicate( UseSSE<=1 );
10274 match(Set dst (MulD src (LoadD mem)));
10275 ins_cost(250);
10276 format %{ "FLD_D $mem\n\t"
10277 "DMUL ST,$src\n\t"
10278 "FSTP_D $dst" %}
10279 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10280 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10281 OpcReg_FPR(src),
10282 Pop_Reg_DPR(dst) );
10283 ins_pipe( fpu_reg_reg_mem );
10284 %}
10285
10286
10287 // MACRO3 -- addDPR a mulDPR
10288 // This instruction is a '2-address' instruction in that the result goes
10289 // back to src2. This eliminates a move from the macro; possibly the
10290 // register allocator will have to add it back (and maybe not).
10291 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
10292 predicate( UseSSE<=1 );
10293 match(Set src2 (AddD (MulD src0 src1) src2));
10294 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10295 "DMUL ST,$src1\n\t"
10296 "DADDp $src2,ST" %}
10297 ins_cost(250);
10298 opcode(0xDD); /* LoadD DD /0 */
10299 ins_encode( Push_Reg_FPR(src0),
10300 FMul_ST_reg(src1),
10301 FAddP_reg_ST(src2) );
10302 ins_pipe( fpu_reg_reg_reg );
10303 %}
10304
10305
10306 // MACRO3 -- subDPR a mulDPR
10307 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
10308 predicate( UseSSE<=1 );
10309 match(Set src2 (SubD (MulD src0 src1) src2));
10310 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10311 "DMUL ST,$src1\n\t"
10312 "DSUBRp $src2,ST" %}
10313 ins_cost(250);
10314 ins_encode( Push_Reg_FPR(src0),
10315 FMul_ST_reg(src1),
10316 Opcode(0xDE), Opc_plus(0xE0,src2));
10317 ins_pipe( fpu_reg_reg_reg );
10318 %}
10319
10320
10321 instruct divDPR_reg(regDPR dst, regDPR src) %{
10322 predicate( UseSSE<=1 );
10323 match(Set dst (DivD dst src));
10324
10325 format %{ "FLD $src\n\t"
10326 "FDIVp $dst,ST" %}
10327 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10328 ins_cost(150);
10329 ins_encode( Push_Reg_DPR(src),
10330 OpcP, RegOpc(dst) );
10331 ins_pipe( fpu_reg_reg );
10332 %}
10333
10334 // Strict FP instruction biases argument before division then
10335 // biases result, to avoid double rounding of subnormals.
10336 //
10337 // scale dividend by multiplying dividend by 2^(-15360)
10338 // load divisor
10339 // divide scaled dividend by divisor
10340 // rescale quotient by 2^(15360)
10341 //
10342 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
10343 predicate (UseSSE<=1);
10344 match(Set dst (DivD dst src));
10345 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10346 ins_cost(01);
10347
10348 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10349 "DMULp $dst,ST\n\t"
10350 "FLD $src\n\t"
10351 "FDIVp $dst,ST\n\t"
10352 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10353 "DMULp $dst,ST\n\t" %}
10354 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10355 ins_encode( strictfp_bias1(dst),
10356 Push_Reg_DPR(src),
10357 OpcP, RegOpc(dst),
10358 strictfp_bias2(dst) );
10359 ins_pipe( fpu_reg_reg );
10360 %}
10361
10362 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
10363 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10364 match(Set dst (RoundDouble (DivD src1 src2)));
10365
10366 format %{ "FLD $src1\n\t"
10367 "FDIV ST,$src2\n\t"
10368 "FSTP_D $dst\t# D-round" %}
10369 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10370 ins_encode( Push_Reg_DPR(src1),
10371 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
10372 ins_pipe( fpu_mem_reg_reg );
10373 %}
10374
10375
10376 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
10377 predicate(UseSSE<=1);
10378 match(Set dst (ModD dst src));
10379 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10380
10381 format %{ "DMOD $dst,$src" %}
10382 ins_cost(250);
10383 ins_encode(Push_Reg_Mod_DPR(dst, src),
10384 emitModDPR(),
10385 Push_Result_Mod_DPR(src),
10386 Pop_Reg_DPR(dst));
10387 ins_pipe( pipe_slow );
10388 %}
10389
10390 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
10391 predicate(UseSSE>=2);
10392 match(Set dst (ModD src0 src1));
10393 effect(KILL rax, KILL cr);
10394
10395 format %{ "SUB ESP,8\t # DMOD\n"
10396 "\tMOVSD [ESP+0],$src1\n"
10397 "\tFLD_D [ESP+0]\n"
10398 "\tMOVSD [ESP+0],$src0\n"
10399 "\tFLD_D [ESP+0]\n"
10400 "loop:\tFPREM\n"
10401 "\tFWAIT\n"
10402 "\tFNSTSW AX\n"
10403 "\tSAHF\n"
10404 "\tJP loop\n"
10405 "\tFSTP_D [ESP+0]\n"
10406 "\tMOVSD $dst,[ESP+0]\n"
10407 "\tADD ESP,8\n"
10408 "\tFSTP ST0\t # Restore FPU Stack"
10409 %}
10410 ins_cost(250);
10411 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10412 ins_pipe( pipe_slow );
10413 %}
10414
10415 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10416 predicate (UseSSE<=1);
10417 match(Set dst (SinD src));
10418 ins_cost(1800);
10419 format %{ "DSIN $dst" %}
10420 opcode(0xD9, 0xFE);
10421 ins_encode( OpcP, OpcS );
10422 ins_pipe( pipe_slow );
10423 %}
10424
10425 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10426 predicate (UseSSE>=2);
10427 match(Set dst (SinD dst));
10428 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10429 ins_cost(1800);
10430 format %{ "DSIN $dst" %}
10431 opcode(0xD9, 0xFE);
10432 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10433 ins_pipe( pipe_slow );
10434 %}
10435
10436 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10437 predicate (UseSSE<=1);
10438 match(Set dst (CosD src));
10439 ins_cost(1800);
10440 format %{ "DCOS $dst" %}
10441 opcode(0xD9, 0xFF);
10442 ins_encode( OpcP, OpcS );
10443 ins_pipe( pipe_slow );
10444 %}
10445
10446 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10447 predicate (UseSSE>=2);
10448 match(Set dst (CosD dst));
10449 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10450 ins_cost(1800);
10451 format %{ "DCOS $dst" %}
10452 opcode(0xD9, 0xFF);
10453 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10454 ins_pipe( pipe_slow );
10455 %}
10456
10457 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10458 predicate (UseSSE<=1);
10459 match(Set dst(TanD src));
10460 format %{ "DTAN $dst" %}
10461 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10462 Opcode(0xDD), Opcode(0xD8)); // fstp st
10463 ins_pipe( pipe_slow );
10464 %}
10465
10466 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10467 predicate (UseSSE>=2);
10468 match(Set dst(TanD dst));
10469 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10470 format %{ "DTAN $dst" %}
10471 ins_encode( Push_SrcD(dst),
10472 Opcode(0xD9), Opcode(0xF2), // fptan
10473 Opcode(0xDD), Opcode(0xD8), // fstp st
10474 Push_ResultD(dst) );
10475 ins_pipe( pipe_slow );
10476 %}
10477
10478 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10479 predicate (UseSSE<=1);
10480 match(Set dst(AtanD dst src));
10481 format %{ "DATA $dst,$src" %}
10482 opcode(0xD9, 0xF3);
10483 ins_encode( Push_Reg_DPR(src),
10484 OpcP, OpcS, RegOpc(dst) );
10485 ins_pipe( pipe_slow );
10486 %}
10487
10488 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10489 predicate (UseSSE>=2);
10490 match(Set dst(AtanD dst src));
10491 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10492 format %{ "DATA $dst,$src" %}
10493 opcode(0xD9, 0xF3);
10494 ins_encode( Push_SrcD(src),
10495 OpcP, OpcS, Push_ResultD(dst) );
10496 ins_pipe( pipe_slow );
10497 %}
10498
10499 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10500 predicate (UseSSE<=1);
10501 match(Set dst (SqrtD src));
10502 format %{ "DSQRT $dst,$src" %}
10503 opcode(0xFA, 0xD9);
10504 ins_encode( Push_Reg_DPR(src),
10505 OpcS, OpcP, Pop_Reg_DPR(dst) );
10506 ins_pipe( pipe_slow );
10507 %}
10508
10509 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10510 predicate (UseSSE<=1);
10511 match(Set Y (PowD X Y)); // Raise X to the Yth power
10512 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10513 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10514 ins_encode %{
10515 __ subptr(rsp, 8);
10516 __ fld_s($X$$reg - 1);
10517 __ fast_pow();
10518 __ addptr(rsp, 8);
10519 %}
10520 ins_pipe( pipe_slow );
10521 %}
10522
10523 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10524 predicate (UseSSE>=2);
10525 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10526 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10527 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10528 ins_encode %{
10529 __ subptr(rsp, 8);
10530 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10531 __ fld_d(Address(rsp, 0));
10532 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10533 __ fld_d(Address(rsp, 0));
10534 __ fast_pow();
10535 __ fstp_d(Address(rsp, 0));
10536 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10537 __ addptr(rsp, 8);
10538 %}
10539 ins_pipe( pipe_slow );
10540 %}
10541
10542
10543 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10544 predicate (UseSSE<=1);
10545 match(Set dpr1 (ExpD dpr1));
10546 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10547 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10548 ins_encode %{
10549 __ fast_exp();
10550 %}
10551 ins_pipe( pipe_slow );
10552 %}
10553
10554 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10555 predicate (UseSSE>=2);
10556 match(Set dst (ExpD src));
10557 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10558 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10559 ins_encode %{
10560 __ subptr(rsp, 8);
10561 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10562 __ fld_d(Address(rsp, 0));
10563 __ fast_exp();
10564 __ fstp_d(Address(rsp, 0));
10565 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10566 __ addptr(rsp, 8);
10567 %}
10568 ins_pipe( pipe_slow );
10569 %}
10570
10571 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10572 predicate (UseSSE<=1);
10573 // The source Double operand on FPU stack
10574 match(Set dst (Log10D src));
10575 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10576 // fxch ; swap ST(0) with ST(1)
10577 // fyl2x ; compute log_10(2) * log_2(x)
10578 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10579 "FXCH \n\t"
10580 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10581 %}
10582 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10583 Opcode(0xD9), Opcode(0xC9), // fxch
10584 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10585
10586 ins_pipe( pipe_slow );
10587 %}
10588
10589 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10590 predicate (UseSSE>=2);
10591 effect(KILL cr);
10592 match(Set dst (Log10D src));
10593 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10594 // fyl2x ; compute log_10(2) * log_2(x)
10595 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10596 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10597 %}
10598 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10599 Push_SrcD(src),
10600 Opcode(0xD9), Opcode(0xF1), // fyl2x
10601 Push_ResultD(dst));
10602
10603 ins_pipe( pipe_slow );
10604 %}
10605
10606 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10607 predicate (UseSSE<=1);
10608 // The source Double operand on FPU stack
10609 match(Set dst (LogD src));
10610 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10611 // fxch ; swap ST(0) with ST(1)
10612 // fyl2x ; compute log_e(2) * log_2(x)
10613 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10614 "FXCH \n\t"
10615 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10616 %}
10617 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10618 Opcode(0xD9), Opcode(0xC9), // fxch
10619 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10620
10621 ins_pipe( pipe_slow );
10622 %}
10623
10624 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10625 predicate (UseSSE>=2);
10626 effect(KILL cr);
10627 // The source and result Double operands in XMM registers
10628 match(Set dst (LogD src));
10629 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10630 // fyl2x ; compute log_e(2) * log_2(x)
10631 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10632 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10633 %}
10634 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10635 Push_SrcD(src),
10636 Opcode(0xD9), Opcode(0xF1), // fyl2x
10637 Push_ResultD(dst));
10638 ins_pipe( pipe_slow );
10639 %}
10640
10641 //-------------Float Instructions-------------------------------
10642 // Float Math
10643
10644 // Code for float compare:
10645 // fcompp();
10646 // fwait(); fnstsw_ax();
10647 // sahf();
10648 // movl(dst, unordered_result);
10649 // jcc(Assembler::parity, exit);
10650 // movl(dst, less_result);
10651 // jcc(Assembler::below, exit);
10652 // movl(dst, equal_result);
10653 // jcc(Assembler::equal, exit);
10654 // movl(dst, greater_result);
10655 // exit:
10656
10657 // P6 version of float compare, sets condition codes in EFLAGS
10658 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10659 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10660 match(Set cr (CmpF src1 src2));
10661 effect(KILL rax);
10662 ins_cost(150);
10663 format %{ "FLD $src1\n\t"
10664 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10665 "JNP exit\n\t"
10666 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10667 "SAHF\n"
10668 "exit:\tNOP // avoid branch to branch" %}
10669 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10670 ins_encode( Push_Reg_DPR(src1),
10671 OpcP, RegOpc(src2),
10672 cmpF_P6_fixup );
10673 ins_pipe( pipe_slow );
10674 %}
10675
10676 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10677 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10678 match(Set cr (CmpF src1 src2));
10679 ins_cost(100);
10680 format %{ "FLD $src1\n\t"
10681 "FUCOMIP ST,$src2 // P6 instruction" %}
10682 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10683 ins_encode( Push_Reg_DPR(src1),
10684 OpcP, RegOpc(src2));
10685 ins_pipe( pipe_slow );
10686 %}
10687
10688
10689 // Compare & branch
10690 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10691 predicate(UseSSE == 0);
10692 match(Set cr (CmpF src1 src2));
10693 effect(KILL rax);
10694 ins_cost(200);
10695 format %{ "FLD $src1\n\t"
10696 "FCOMp $src2\n\t"
10697 "FNSTSW AX\n\t"
10698 "TEST AX,0x400\n\t"
10699 "JZ,s flags\n\t"
10700 "MOV AH,1\t# unordered treat as LT\n"
10701 "flags:\tSAHF" %}
10702 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10703 ins_encode( Push_Reg_DPR(src1),
10704 OpcP, RegOpc(src2),
10705 fpu_flags);
10706 ins_pipe( pipe_slow );
10707 %}
10708
10709 // Compare vs zero into -1,0,1
10710 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10711 predicate(UseSSE == 0);
10712 match(Set dst (CmpF3 src1 zero));
10713 effect(KILL cr, KILL rax);
10714 ins_cost(280);
10715 format %{ "FTSTF $dst,$src1" %}
10716 opcode(0xE4, 0xD9);
10717 ins_encode( Push_Reg_DPR(src1),
10718 OpcS, OpcP, PopFPU,
10719 CmpF_Result(dst));
10720 ins_pipe( pipe_slow );
10721 %}
10722
10723 // Compare into -1,0,1
10724 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10725 predicate(UseSSE == 0);
10726 match(Set dst (CmpF3 src1 src2));
10727 effect(KILL cr, KILL rax);
10728 ins_cost(300);
10729 format %{ "FCMPF $dst,$src1,$src2" %}
10730 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10731 ins_encode( Push_Reg_DPR(src1),
10732 OpcP, RegOpc(src2),
10733 CmpF_Result(dst));
10734 ins_pipe( pipe_slow );
10735 %}
10736
10737 // float compare and set condition codes in EFLAGS by XMM regs
10738 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10739 predicate(UseSSE>=1);
10740 match(Set cr (CmpF src1 src2));
10741 ins_cost(145);
10742 format %{ "UCOMISS $src1,$src2\n\t"
10743 "JNP,s exit\n\t"
10744 "PUSHF\t# saw NaN, set CF\n\t"
10745 "AND [rsp], #0xffffff2b\n\t"
10746 "POPF\n"
10747 "exit:" %}
10748 ins_encode %{
10749 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10750 emit_cmpfp_fixup(_masm);
10751 %}
10752 ins_pipe( pipe_slow );
10753 %}
10754
10755 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10756 predicate(UseSSE>=1);
10757 match(Set cr (CmpF src1 src2));
10758 ins_cost(100);
10759 format %{ "UCOMISS $src1,$src2" %}
10760 ins_encode %{
10761 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10762 %}
10763 ins_pipe( pipe_slow );
10764 %}
10765
10766 // float compare and set condition codes in EFLAGS by XMM regs
10767 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10768 predicate(UseSSE>=1);
10769 match(Set cr (CmpF src1 (LoadF src2)));
10770 ins_cost(165);
10771 format %{ "UCOMISS $src1,$src2\n\t"
10772 "JNP,s exit\n\t"
10773 "PUSHF\t# saw NaN, set CF\n\t"
10774 "AND [rsp], #0xffffff2b\n\t"
10775 "POPF\n"
10776 "exit:" %}
10777 ins_encode %{
10778 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10779 emit_cmpfp_fixup(_masm);
10780 %}
10781 ins_pipe( pipe_slow );
10782 %}
10783
10784 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10785 predicate(UseSSE>=1);
10786 match(Set cr (CmpF src1 (LoadF src2)));
10787 ins_cost(100);
10788 format %{ "UCOMISS $src1,$src2" %}
10789 ins_encode %{
10790 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10791 %}
10792 ins_pipe( pipe_slow );
10793 %}
10794
10795 // Compare into -1,0,1 in XMM
10796 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10797 predicate(UseSSE>=1);
10798 match(Set dst (CmpF3 src1 src2));
10799 effect(KILL cr);
10800 ins_cost(255);
10801 format %{ "UCOMISS $src1, $src2\n\t"
10802 "MOV $dst, #-1\n\t"
10803 "JP,s done\n\t"
10804 "JB,s done\n\t"
10805 "SETNE $dst\n\t"
10806 "MOVZB $dst, $dst\n"
10807 "done:" %}
10808 ins_encode %{
10809 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10810 emit_cmpfp3(_masm, $dst$$Register);
10811 %}
10812 ins_pipe( pipe_slow );
10813 %}
10814
10815 // Compare into -1,0,1 in XMM and memory
10816 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10817 predicate(UseSSE>=1);
10818 match(Set dst (CmpF3 src1 (LoadF src2)));
10819 effect(KILL cr);
10820 ins_cost(275);
10821 format %{ "UCOMISS $src1, $src2\n\t"
10822 "MOV $dst, #-1\n\t"
10823 "JP,s done\n\t"
10824 "JB,s done\n\t"
10825 "SETNE $dst\n\t"
10826 "MOVZB $dst, $dst\n"
10827 "done:" %}
10828 ins_encode %{
10829 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10830 emit_cmpfp3(_masm, $dst$$Register);
10831 %}
10832 ins_pipe( pipe_slow );
10833 %}
10834
10835 // Spill to obtain 24-bit precision
10836 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10837 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10838 match(Set dst (SubF src1 src2));
10839
10840 format %{ "FSUB $dst,$src1 - $src2" %}
10841 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10842 ins_encode( Push_Reg_FPR(src1),
10843 OpcReg_FPR(src2),
10844 Pop_Mem_FPR(dst) );
10845 ins_pipe( fpu_mem_reg_reg );
10846 %}
10847 //
10848 // This instruction does not round to 24-bits
10849 instruct subFPR_reg(regFPR dst, regFPR src) %{
10850 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10851 match(Set dst (SubF dst src));
10852
10853 format %{ "FSUB $dst,$src" %}
10854 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10855 ins_encode( Push_Reg_FPR(src),
10856 OpcP, RegOpc(dst) );
10857 ins_pipe( fpu_reg_reg );
10858 %}
10859
10860 // Spill to obtain 24-bit precision
10861 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10862 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10863 match(Set dst (AddF src1 src2));
10864
10865 format %{ "FADD $dst,$src1,$src2" %}
10866 opcode(0xD8, 0x0); /* D8 C0+i */
10867 ins_encode( Push_Reg_FPR(src2),
10868 OpcReg_FPR(src1),
10869 Pop_Mem_FPR(dst) );
10870 ins_pipe( fpu_mem_reg_reg );
10871 %}
10872 //
10873 // This instruction does not round to 24-bits
10874 instruct addFPR_reg(regFPR dst, regFPR src) %{
10875 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10876 match(Set dst (AddF dst src));
10877
10878 format %{ "FLD $src\n\t"
10879 "FADDp $dst,ST" %}
10880 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10881 ins_encode( Push_Reg_FPR(src),
10882 OpcP, RegOpc(dst) );
10883 ins_pipe( fpu_reg_reg );
10884 %}
10885
10886 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10887 predicate(UseSSE==0);
10888 match(Set dst (AbsF src));
10889 ins_cost(100);
10890 format %{ "FABS" %}
10891 opcode(0xE1, 0xD9);
10892 ins_encode( OpcS, OpcP );
10893 ins_pipe( fpu_reg_reg );
10894 %}
10895
10896 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10897 predicate(UseSSE==0);
10898 match(Set dst (NegF src));
10899 ins_cost(100);
10900 format %{ "FCHS" %}
10901 opcode(0xE0, 0xD9);
10902 ins_encode( OpcS, OpcP );
10903 ins_pipe( fpu_reg_reg );
10904 %}
10905
10906 // Cisc-alternate to addFPR_reg
10907 // Spill to obtain 24-bit precision
10908 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10909 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10910 match(Set dst (AddF src1 (LoadF src2)));
10911
10912 format %{ "FLD $src2\n\t"
10913 "FADD ST,$src1\n\t"
10914 "FSTP_S $dst" %}
10915 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10916 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10917 OpcReg_FPR(src1),
10918 Pop_Mem_FPR(dst) );
10919 ins_pipe( fpu_mem_reg_mem );
10920 %}
10921 //
10922 // Cisc-alternate to addFPR_reg
10923 // This instruction does not round to 24-bits
10924 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10925 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10926 match(Set dst (AddF dst (LoadF src)));
10927
10928 format %{ "FADD $dst,$src" %}
10929 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10930 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10931 OpcP, RegOpc(dst) );
10932 ins_pipe( fpu_reg_mem );
10933 %}
10934
10935 // // Following two instructions for _222_mpegaudio
10936 // Spill to obtain 24-bit precision
10937 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10938 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10939 match(Set dst (AddF src1 src2));
10940
10941 format %{ "FADD $dst,$src1,$src2" %}
10942 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10943 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10944 OpcReg_FPR(src2),
10945 Pop_Mem_FPR(dst) );
10946 ins_pipe( fpu_mem_reg_mem );
10947 %}
10948
10949 // Cisc-spill variant
10950 // Spill to obtain 24-bit precision
10951 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10952 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10953 match(Set dst (AddF src1 (LoadF src2)));
10954
10955 format %{ "FADD $dst,$src1,$src2 cisc" %}
10956 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10957 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10958 set_instruction_start,
10959 OpcP, RMopc_Mem(secondary,src1),
10960 Pop_Mem_FPR(dst) );
10961 ins_pipe( fpu_mem_mem_mem );
10962 %}
10963
10964 // Spill to obtain 24-bit precision
10965 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10966 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10967 match(Set dst (AddF src1 src2));
10968
10969 format %{ "FADD $dst,$src1,$src2" %}
10970 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10971 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10972 set_instruction_start,
10973 OpcP, RMopc_Mem(secondary,src1),
10974 Pop_Mem_FPR(dst) );
10975 ins_pipe( fpu_mem_mem_mem );
10976 %}
10977
10978
10979 // Spill to obtain 24-bit precision
10980 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10981 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10982 match(Set dst (AddF src con));
10983 format %{ "FLD $src\n\t"
10984 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10985 "FSTP_S $dst" %}
10986 ins_encode %{
10987 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10988 __ fadd_s($constantaddress($con));
10989 __ fstp_s(Address(rsp, $dst$$disp));
10990 %}
10991 ins_pipe(fpu_mem_reg_con);
10992 %}
10993 //
10994 // This instruction does not round to 24-bits
10995 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10996 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10997 match(Set dst (AddF src con));
10998 format %{ "FLD $src\n\t"
10999 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11000 "FSTP $dst" %}
11001 ins_encode %{
11002 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11003 __ fadd_s($constantaddress($con));
11004 __ fstp_d($dst$$reg);
11005 %}
11006 ins_pipe(fpu_reg_reg_con);
11007 %}
11008
11009 // Spill to obtain 24-bit precision
11010 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
11011 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11012 match(Set dst (MulF src1 src2));
11013
11014 format %{ "FLD $src1\n\t"
11015 "FMUL $src2\n\t"
11016 "FSTP_S $dst" %}
11017 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11018 ins_encode( Push_Reg_FPR(src1),
11019 OpcReg_FPR(src2),
11020 Pop_Mem_FPR(dst) );
11021 ins_pipe( fpu_mem_reg_reg );
11022 %}
11023 //
11024 // This instruction does not round to 24-bits
11025 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
11026 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11027 match(Set dst (MulF src1 src2));
11028
11029 format %{ "FLD $src1\n\t"
11030 "FMUL $src2\n\t"
11031 "FSTP_S $dst" %}
11032 opcode(0xD8, 0x1); /* D8 C8+i */
11033 ins_encode( Push_Reg_FPR(src2),
11034 OpcReg_FPR(src1),
11035 Pop_Reg_FPR(dst) );
11036 ins_pipe( fpu_reg_reg_reg );
11037 %}
11038
11039
11040 // Spill to obtain 24-bit precision
11041 // Cisc-alternate to reg-reg multiply
11042 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
11043 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11044 match(Set dst (MulF src1 (LoadF src2)));
11045
11046 format %{ "FLD_S $src2\n\t"
11047 "FMUL $src1\n\t"
11048 "FSTP_S $dst" %}
11049 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11050 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11051 OpcReg_FPR(src1),
11052 Pop_Mem_FPR(dst) );
11053 ins_pipe( fpu_mem_reg_mem );
11054 %}
11055 //
11056 // This instruction does not round to 24-bits
11057 // Cisc-alternate to reg-reg multiply
11058 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
11059 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11060 match(Set dst (MulF src1 (LoadF src2)));
11061
11062 format %{ "FMUL $dst,$src1,$src2" %}
11063 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11064 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11065 OpcReg_FPR(src1),
11066 Pop_Reg_FPR(dst) );
11067 ins_pipe( fpu_reg_reg_mem );
11068 %}
11069
11070 // Spill to obtain 24-bit precision
11071 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11072 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11073 match(Set dst (MulF src1 src2));
11074
11075 format %{ "FMUL $dst,$src1,$src2" %}
11076 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11077 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11078 set_instruction_start,
11079 OpcP, RMopc_Mem(secondary,src1),
11080 Pop_Mem_FPR(dst) );
11081 ins_pipe( fpu_mem_mem_mem );
11082 %}
11083
11084 // Spill to obtain 24-bit precision
11085 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
11086 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11087 match(Set dst (MulF src con));
11088
11089 format %{ "FLD $src\n\t"
11090 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11091 "FSTP_S $dst" %}
11092 ins_encode %{
11093 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11094 __ fmul_s($constantaddress($con));
11095 __ fstp_s(Address(rsp, $dst$$disp));
11096 %}
11097 ins_pipe(fpu_mem_reg_con);
11098 %}
11099 //
11100 // This instruction does not round to 24-bits
11101 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
11102 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11103 match(Set dst (MulF src con));
11104
11105 format %{ "FLD $src\n\t"
11106 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11107 "FSTP $dst" %}
11108 ins_encode %{
11109 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11110 __ fmul_s($constantaddress($con));
11111 __ fstp_d($dst$$reg);
11112 %}
11113 ins_pipe(fpu_reg_reg_con);
11114 %}
11115
11116
11117 //
11118 // MACRO1 -- subsume unshared load into mulFPR
11119 // This instruction does not round to 24-bits
11120 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
11121 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11122 match(Set dst (MulF (LoadF mem1) src));
11123
11124 format %{ "FLD $mem1 ===MACRO1===\n\t"
11125 "FMUL ST,$src\n\t"
11126 "FSTP $dst" %}
11127 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11128 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11129 OpcReg_FPR(src),
11130 Pop_Reg_FPR(dst) );
11131 ins_pipe( fpu_reg_reg_mem );
11132 %}
11133 //
11134 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
11135 // This instruction does not round to 24-bits
11136 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
11137 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11138 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11139 ins_cost(95);
11140
11141 format %{ "FLD $mem1 ===MACRO2===\n\t"
11142 "FMUL ST,$src1 subsume mulFPR left load\n\t"
11143 "FADD ST,$src2\n\t"
11144 "FSTP $dst" %}
11145 opcode(0xD9); /* LoadF D9 /0 */
11146 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11147 FMul_ST_reg(src1),
11148 FAdd_ST_reg(src2),
11149 Pop_Reg_FPR(dst) );
11150 ins_pipe( fpu_reg_mem_reg_reg );
11151 %}
11152
11153 // MACRO3 -- addFPR a mulFPR
11154 // This instruction does not round to 24-bits. It is a '2-address'
11155 // instruction in that the result goes back to src2. This eliminates
11156 // a move from the macro; possibly the register allocator will have
11157 // to add it back (and maybe not).
11158 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
11159 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11160 match(Set src2 (AddF (MulF src0 src1) src2));
11161
11162 format %{ "FLD $src0 ===MACRO3===\n\t"
11163 "FMUL ST,$src1\n\t"
11164 "FADDP $src2,ST" %}
11165 opcode(0xD9); /* LoadF D9 /0 */
11166 ins_encode( Push_Reg_FPR(src0),
11167 FMul_ST_reg(src1),
11168 FAddP_reg_ST(src2) );
11169 ins_pipe( fpu_reg_reg_reg );
11170 %}
11171
11172 // MACRO4 -- divFPR subFPR
11173 // This instruction does not round to 24-bits
11174 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
11175 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11176 match(Set dst (DivF (SubF src2 src1) src3));
11177
11178 format %{ "FLD $src2 ===MACRO4===\n\t"
11179 "FSUB ST,$src1\n\t"
11180 "FDIV ST,$src3\n\t"
11181 "FSTP $dst" %}
11182 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11183 ins_encode( Push_Reg_FPR(src2),
11184 subFPR_divFPR_encode(src1,src3),
11185 Pop_Reg_FPR(dst) );
11186 ins_pipe( fpu_reg_reg_reg_reg );
11187 %}
11188
11189 // Spill to obtain 24-bit precision
11190 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
11191 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11192 match(Set dst (DivF src1 src2));
11193
11194 format %{ "FDIV $dst,$src1,$src2" %}
11195 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11196 ins_encode( Push_Reg_FPR(src1),
11197 OpcReg_FPR(src2),
11198 Pop_Mem_FPR(dst) );
11199 ins_pipe( fpu_mem_reg_reg );
11200 %}
11201 //
11202 // This instruction does not round to 24-bits
11203 instruct divFPR_reg(regFPR dst, regFPR src) %{
11204 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11205 match(Set dst (DivF dst src));
11206
11207 format %{ "FDIV $dst,$src" %}
11208 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11209 ins_encode( Push_Reg_FPR(src),
11210 OpcP, RegOpc(dst) );
11211 ins_pipe( fpu_reg_reg );
11212 %}
11213
11214
11215 // Spill to obtain 24-bit precision
11216 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
11217 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11218 match(Set dst (ModF src1 src2));
11219 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
11220
11221 format %{ "FMOD $dst,$src1,$src2" %}
11222 ins_encode( Push_Reg_Mod_DPR(src1, src2),
11223 emitModDPR(),
11224 Push_Result_Mod_DPR(src2),
11225 Pop_Mem_FPR(dst));
11226 ins_pipe( pipe_slow );
11227 %}
11228 //
11229 // This instruction does not round to 24-bits
11230 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
11231 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11232 match(Set dst (ModF dst src));
11233 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
11234
11235 format %{ "FMOD $dst,$src" %}
11236 ins_encode(Push_Reg_Mod_DPR(dst, src),
11237 emitModDPR(),
11238 Push_Result_Mod_DPR(src),
11239 Pop_Reg_FPR(dst));
11240 ins_pipe( pipe_slow );
11241 %}
11242
11243 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
11244 predicate(UseSSE>=1);
11245 match(Set dst (ModF src0 src1));
11246 effect(KILL rax, KILL cr);
11247 format %{ "SUB ESP,4\t # FMOD\n"
11248 "\tMOVSS [ESP+0],$src1\n"
11249 "\tFLD_S [ESP+0]\n"
11250 "\tMOVSS [ESP+0],$src0\n"
11251 "\tFLD_S [ESP+0]\n"
11252 "loop:\tFPREM\n"
11253 "\tFWAIT\n"
11254 "\tFNSTSW AX\n"
11255 "\tSAHF\n"
11256 "\tJP loop\n"
11257 "\tFSTP_S [ESP+0]\n"
11258 "\tMOVSS $dst,[ESP+0]\n"
11259 "\tADD ESP,4\n"
11260 "\tFSTP ST0\t # Restore FPU Stack"
11261 %}
11262 ins_cost(250);
11263 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
11264 ins_pipe( pipe_slow );
11265 %}
11266
11267
11268 //----------Arithmetic Conversion Instructions---------------------------------
11269 // The conversions operations are all Alpha sorted. Please keep it that way!
11270
11271 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
11272 predicate(UseSSE==0);
11273 match(Set dst (RoundFloat src));
11274 ins_cost(125);
11275 format %{ "FST_S $dst,$src\t# F-round" %}
11276 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11277 ins_pipe( fpu_mem_reg );
11278 %}
11279
11280 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
11281 predicate(UseSSE<=1);
11282 match(Set dst (RoundDouble src));
11283 ins_cost(125);
11284 format %{ "FST_D $dst,$src\t# D-round" %}
11285 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11286 ins_pipe( fpu_mem_reg );
11287 %}
11288
11289 // Force rounding to 24-bit precision and 6-bit exponent
11290 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
11291 predicate(UseSSE==0);
11292 match(Set dst (ConvD2F src));
11293 format %{ "FST_S $dst,$src\t# F-round" %}
11294 expand %{
11295 roundFloat_mem_reg(dst,src);
11296 %}
11297 %}
11298
11299 // Force rounding to 24-bit precision and 6-bit exponent
11300 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
11301 predicate(UseSSE==1);
11302 match(Set dst (ConvD2F src));
11303 effect( KILL cr );
11304 format %{ "SUB ESP,4\n\t"
11305 "FST_S [ESP],$src\t# F-round\n\t"
11306 "MOVSS $dst,[ESP]\n\t"
11307 "ADD ESP,4" %}
11308 ins_encode %{
11309 __ subptr(rsp, 4);
11310 if ($src$$reg != FPR1L_enc) {
11311 __ fld_s($src$$reg-1);
11312 __ fstp_s(Address(rsp, 0));
11313 } else {
11314 __ fst_s(Address(rsp, 0));
11315 }
11316 __ movflt($dst$$XMMRegister, Address(rsp, 0));
11317 __ addptr(rsp, 4);
11318 %}
11319 ins_pipe( pipe_slow );
11320 %}
11321
11322 // Force rounding double precision to single precision
11323 instruct convD2F_reg(regF dst, regD src) %{
11324 predicate(UseSSE>=2);
11325 match(Set dst (ConvD2F src));
11326 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11327 ins_encode %{
11328 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11329 %}
11330 ins_pipe( pipe_slow );
11331 %}
11332
11333 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
11334 predicate(UseSSE==0);
11335 match(Set dst (ConvF2D src));
11336 format %{ "FST_S $dst,$src\t# D-round" %}
11337 ins_encode( Pop_Reg_Reg_DPR(dst, src));
11338 ins_pipe( fpu_reg_reg );
11339 %}
11340
11341 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
11342 predicate(UseSSE==1);
11343 match(Set dst (ConvF2D src));
11344 format %{ "FST_D $dst,$src\t# D-round" %}
11345 expand %{
11346 roundDouble_mem_reg(dst,src);
11347 %}
11348 %}
11349
11350 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
11351 predicate(UseSSE==1);
11352 match(Set dst (ConvF2D src));
11353 effect( KILL cr );
11354 format %{ "SUB ESP,4\n\t"
11355 "MOVSS [ESP] $src\n\t"
11356 "FLD_S [ESP]\n\t"
11357 "ADD ESP,4\n\t"
11358 "FSTP $dst\t# D-round" %}
11359 ins_encode %{
11360 __ subptr(rsp, 4);
11361 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11362 __ fld_s(Address(rsp, 0));
11363 __ addptr(rsp, 4);
11364 __ fstp_d($dst$$reg);
11365 %}
11366 ins_pipe( pipe_slow );
11367 %}
11368
11369 instruct convF2D_reg(regD dst, regF src) %{
11370 predicate(UseSSE>=2);
11371 match(Set dst (ConvF2D src));
11372 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11373 ins_encode %{
11374 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11375 %}
11376 ins_pipe( pipe_slow );
11377 %}
11378
11379 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11380 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11381 predicate(UseSSE<=1);
11382 match(Set dst (ConvD2I src));
11383 effect( KILL tmp, KILL cr );
11384 format %{ "FLD $src\t# Convert double to int \n\t"
11385 "FLDCW trunc mode\n\t"
11386 "SUB ESP,4\n\t"
11387 "FISTp [ESP + #0]\n\t"
11388 "FLDCW std/24-bit mode\n\t"
11389 "POP EAX\n\t"
11390 "CMP EAX,0x80000000\n\t"
11391 "JNE,s fast\n\t"
11392 "FLD_D $src\n\t"
11393 "CALL d2i_wrapper\n"
11394 "fast:" %}
11395 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11396 ins_pipe( pipe_slow );
11397 %}
11398
11399 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11400 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11401 predicate(UseSSE>=2);
11402 match(Set dst (ConvD2I src));
11403 effect( KILL tmp, KILL cr );
11404 format %{ "CVTTSD2SI $dst, $src\n\t"
11405 "CMP $dst,0x80000000\n\t"
11406 "JNE,s fast\n\t"
11407 "SUB ESP, 8\n\t"
11408 "MOVSD [ESP], $src\n\t"
11409 "FLD_D [ESP]\n\t"
11410 "ADD ESP, 8\n\t"
11411 "CALL d2i_wrapper\n"
11412 "fast:" %}
11413 ins_encode %{
11414 Label fast;
11415 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11416 __ cmpl($dst$$Register, 0x80000000);
11417 __ jccb(Assembler::notEqual, fast);
11418 __ subptr(rsp, 8);
11419 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11420 __ fld_d(Address(rsp, 0));
11421 __ addptr(rsp, 8);
11422 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11423 __ bind(fast);
11424 %}
11425 ins_pipe( pipe_slow );
11426 %}
11427
11428 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11429 predicate(UseSSE<=1);
11430 match(Set dst (ConvD2L src));
11431 effect( KILL cr );
11432 format %{ "FLD $src\t# Convert double to long\n\t"
11433 "FLDCW trunc mode\n\t"
11434 "SUB ESP,8\n\t"
11435 "FISTp [ESP + #0]\n\t"
11436 "FLDCW std/24-bit mode\n\t"
11437 "POP EAX\n\t"
11438 "POP EDX\n\t"
11439 "CMP EDX,0x80000000\n\t"
11440 "JNE,s fast\n\t"
11441 "TEST EAX,EAX\n\t"
11442 "JNE,s fast\n\t"
11443 "FLD $src\n\t"
11444 "CALL d2l_wrapper\n"
11445 "fast:" %}
11446 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11447 ins_pipe( pipe_slow );
11448 %}
11449
11450 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11451 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11452 predicate (UseSSE>=2);
11453 match(Set dst (ConvD2L src));
11454 effect( KILL cr );
11455 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11456 "MOVSD [ESP],$src\n\t"
11457 "FLD_D [ESP]\n\t"
11458 "FLDCW trunc mode\n\t"
11459 "FISTp [ESP + #0]\n\t"
11460 "FLDCW std/24-bit mode\n\t"
11461 "POP EAX\n\t"
11462 "POP EDX\n\t"
11463 "CMP EDX,0x80000000\n\t"
11464 "JNE,s fast\n\t"
11465 "TEST EAX,EAX\n\t"
11466 "JNE,s fast\n\t"
11467 "SUB ESP,8\n\t"
11468 "MOVSD [ESP],$src\n\t"
11469 "FLD_D [ESP]\n\t"
11470 "ADD ESP,8\n\t"
11471 "CALL d2l_wrapper\n"
11472 "fast:" %}
11473 ins_encode %{
11474 Label fast;
11475 __ subptr(rsp, 8);
11476 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11477 __ fld_d(Address(rsp, 0));
11478 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11479 __ fistp_d(Address(rsp, 0));
11480 // Restore the rounding mode, mask the exception
11481 if (Compile::current()->in_24_bit_fp_mode()) {
11482 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11483 } else {
11484 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11485 }
11486 // Load the converted long, adjust CPU stack
11487 __ pop(rax);
11488 __ pop(rdx);
11489 __ cmpl(rdx, 0x80000000);
11490 __ jccb(Assembler::notEqual, fast);
11491 __ testl(rax, rax);
11492 __ jccb(Assembler::notEqual, fast);
11493 __ subptr(rsp, 8);
11494 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11495 __ fld_d(Address(rsp, 0));
11496 __ addptr(rsp, 8);
11497 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11498 __ bind(fast);
11499 %}
11500 ins_pipe( pipe_slow );
11501 %}
11502
11503 // Convert a double to an int. Java semantics require we do complex
11504 // manglations in the corner cases. So we set the rounding mode to
11505 // 'zero', store the darned double down as an int, and reset the
11506 // rounding mode to 'nearest'. The hardware stores a flag value down
11507 // if we would overflow or converted a NAN; we check for this and
11508 // and go the slow path if needed.
11509 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11510 predicate(UseSSE==0);
11511 match(Set dst (ConvF2I src));
11512 effect( KILL tmp, KILL cr );
11513 format %{ "FLD $src\t# Convert float to int \n\t"
11514 "FLDCW trunc mode\n\t"
11515 "SUB ESP,4\n\t"
11516 "FISTp [ESP + #0]\n\t"
11517 "FLDCW std/24-bit mode\n\t"
11518 "POP EAX\n\t"
11519 "CMP EAX,0x80000000\n\t"
11520 "JNE,s fast\n\t"
11521 "FLD $src\n\t"
11522 "CALL d2i_wrapper\n"
11523 "fast:" %}
11524 // DPR2I_encoding works for FPR2I
11525 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11526 ins_pipe( pipe_slow );
11527 %}
11528
11529 // Convert a float in xmm to an int reg.
11530 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11531 predicate(UseSSE>=1);
11532 match(Set dst (ConvF2I src));
11533 effect( KILL tmp, KILL cr );
11534 format %{ "CVTTSS2SI $dst, $src\n\t"
11535 "CMP $dst,0x80000000\n\t"
11536 "JNE,s fast\n\t"
11537 "SUB ESP, 4\n\t"
11538 "MOVSS [ESP], $src\n\t"
11539 "FLD [ESP]\n\t"
11540 "ADD ESP, 4\n\t"
11541 "CALL d2i_wrapper\n"
11542 "fast:" %}
11543 ins_encode %{
11544 Label fast;
11545 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11546 __ cmpl($dst$$Register, 0x80000000);
11547 __ jccb(Assembler::notEqual, fast);
11548 __ subptr(rsp, 4);
11549 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11550 __ fld_s(Address(rsp, 0));
11551 __ addptr(rsp, 4);
11552 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11553 __ bind(fast);
11554 %}
11555 ins_pipe( pipe_slow );
11556 %}
11557
11558 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11559 predicate(UseSSE==0);
11560 match(Set dst (ConvF2L src));
11561 effect( KILL cr );
11562 format %{ "FLD $src\t# Convert float to long\n\t"
11563 "FLDCW trunc mode\n\t"
11564 "SUB ESP,8\n\t"
11565 "FISTp [ESP + #0]\n\t"
11566 "FLDCW std/24-bit mode\n\t"
11567 "POP EAX\n\t"
11568 "POP EDX\n\t"
11569 "CMP EDX,0x80000000\n\t"
11570 "JNE,s fast\n\t"
11571 "TEST EAX,EAX\n\t"
11572 "JNE,s fast\n\t"
11573 "FLD $src\n\t"
11574 "CALL d2l_wrapper\n"
11575 "fast:" %}
11576 // DPR2L_encoding works for FPR2L
11577 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11578 ins_pipe( pipe_slow );
11579 %}
11580
11581 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11582 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11583 predicate (UseSSE>=1);
11584 match(Set dst (ConvF2L src));
11585 effect( KILL cr );
11586 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11587 "MOVSS [ESP],$src\n\t"
11588 "FLD_S [ESP]\n\t"
11589 "FLDCW trunc mode\n\t"
11590 "FISTp [ESP + #0]\n\t"
11591 "FLDCW std/24-bit mode\n\t"
11592 "POP EAX\n\t"
11593 "POP EDX\n\t"
11594 "CMP EDX,0x80000000\n\t"
11595 "JNE,s fast\n\t"
11596 "TEST EAX,EAX\n\t"
11597 "JNE,s fast\n\t"
11598 "SUB ESP,4\t# Convert float to long\n\t"
11599 "MOVSS [ESP],$src\n\t"
11600 "FLD_S [ESP]\n\t"
11601 "ADD ESP,4\n\t"
11602 "CALL d2l_wrapper\n"
11603 "fast:" %}
11604 ins_encode %{
11605 Label fast;
11606 __ subptr(rsp, 8);
11607 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11608 __ fld_s(Address(rsp, 0));
11609 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11610 __ fistp_d(Address(rsp, 0));
11611 // Restore the rounding mode, mask the exception
11612 if (Compile::current()->in_24_bit_fp_mode()) {
11613 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11614 } else {
11615 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11616 }
11617 // Load the converted long, adjust CPU stack
11618 __ pop(rax);
11619 __ pop(rdx);
11620 __ cmpl(rdx, 0x80000000);
11621 __ jccb(Assembler::notEqual, fast);
11622 __ testl(rax, rax);
11623 __ jccb(Assembler::notEqual, fast);
11624 __ subptr(rsp, 4);
11625 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11626 __ fld_s(Address(rsp, 0));
11627 __ addptr(rsp, 4);
11628 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11629 __ bind(fast);
11630 %}
11631 ins_pipe( pipe_slow );
11632 %}
11633
11634 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11635 predicate( UseSSE<=1 );
11636 match(Set dst (ConvI2D src));
11637 format %{ "FILD $src\n\t"
11638 "FSTP $dst" %}
11639 opcode(0xDB, 0x0); /* DB /0 */
11640 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11641 ins_pipe( fpu_reg_mem );
11642 %}
11643
11644 instruct convI2D_reg(regD dst, rRegI src) %{
11645 predicate( UseSSE>=2 && !UseXmmI2D );
11646 match(Set dst (ConvI2D src));
11647 format %{ "CVTSI2SD $dst,$src" %}
11648 ins_encode %{
11649 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11650 %}
11651 ins_pipe( pipe_slow );
11652 %}
11653
11654 instruct convI2D_mem(regD dst, memory mem) %{
11655 predicate( UseSSE>=2 );
11656 match(Set dst (ConvI2D (LoadI mem)));
11657 format %{ "CVTSI2SD $dst,$mem" %}
11658 ins_encode %{
11659 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11660 %}
11661 ins_pipe( pipe_slow );
11662 %}
11663
11664 instruct convXI2D_reg(regD dst, rRegI src)
11665 %{
11666 predicate( UseSSE>=2 && UseXmmI2D );
11667 match(Set dst (ConvI2D src));
11668
11669 format %{ "MOVD $dst,$src\n\t"
11670 "CVTDQ2PD $dst,$dst\t# i2d" %}
11671 ins_encode %{
11672 __ movdl($dst$$XMMRegister, $src$$Register);
11673 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11674 %}
11675 ins_pipe(pipe_slow); // XXX
11676 %}
11677
11678 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11679 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11680 match(Set dst (ConvI2D (LoadI mem)));
11681 format %{ "FILD $mem\n\t"
11682 "FSTP $dst" %}
11683 opcode(0xDB); /* DB /0 */
11684 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11685 Pop_Reg_DPR(dst));
11686 ins_pipe( fpu_reg_mem );
11687 %}
11688
11689 // Convert a byte to a float; no rounding step needed.
11690 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11691 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11692 match(Set dst (ConvI2F src));
11693 format %{ "FILD $src\n\t"
11694 "FSTP $dst" %}
11695
11696 opcode(0xDB, 0x0); /* DB /0 */
11697 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11698 ins_pipe( fpu_reg_mem );
11699 %}
11700
11701 // In 24-bit mode, force exponent rounding by storing back out
11702 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11703 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11704 match(Set dst (ConvI2F src));
11705 ins_cost(200);
11706 format %{ "FILD $src\n\t"
11707 "FSTP_S $dst" %}
11708 opcode(0xDB, 0x0); /* DB /0 */
11709 ins_encode( Push_Mem_I(src),
11710 Pop_Mem_FPR(dst));
11711 ins_pipe( fpu_mem_mem );
11712 %}
11713
11714 // In 24-bit mode, force exponent rounding by storing back out
11715 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11716 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11717 match(Set dst (ConvI2F (LoadI mem)));
11718 ins_cost(200);
11719 format %{ "FILD $mem\n\t"
11720 "FSTP_S $dst" %}
11721 opcode(0xDB); /* DB /0 */
11722 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11723 Pop_Mem_FPR(dst));
11724 ins_pipe( fpu_mem_mem );
11725 %}
11726
11727 // This instruction does not round to 24-bits
11728 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11729 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11730 match(Set dst (ConvI2F src));
11731 format %{ "FILD $src\n\t"
11732 "FSTP $dst" %}
11733 opcode(0xDB, 0x0); /* DB /0 */
11734 ins_encode( Push_Mem_I(src),
11735 Pop_Reg_FPR(dst));
11736 ins_pipe( fpu_reg_mem );
11737 %}
11738
11739 // This instruction does not round to 24-bits
11740 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11741 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11742 match(Set dst (ConvI2F (LoadI mem)));
11743 format %{ "FILD $mem\n\t"
11744 "FSTP $dst" %}
11745 opcode(0xDB); /* DB /0 */
11746 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11747 Pop_Reg_FPR(dst));
11748 ins_pipe( fpu_reg_mem );
11749 %}
11750
11751 // Convert an int to a float in xmm; no rounding step needed.
11752 instruct convI2F_reg(regF dst, rRegI src) %{
11753 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11754 match(Set dst (ConvI2F src));
11755 format %{ "CVTSI2SS $dst, $src" %}
11756 ins_encode %{
11757 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11758 %}
11759 ins_pipe( pipe_slow );
11760 %}
11761
11762 instruct convXI2F_reg(regF dst, rRegI src)
11763 %{
11764 predicate( UseSSE>=2 && UseXmmI2F );
11765 match(Set dst (ConvI2F src));
11766
11767 format %{ "MOVD $dst,$src\n\t"
11768 "CVTDQ2PS $dst,$dst\t# i2f" %}
11769 ins_encode %{
11770 __ movdl($dst$$XMMRegister, $src$$Register);
11771 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11772 %}
11773 ins_pipe(pipe_slow); // XXX
11774 %}
11775
11776 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11777 match(Set dst (ConvI2L src));
11778 effect(KILL cr);
11779 ins_cost(375);
11780 format %{ "MOV $dst.lo,$src\n\t"
11781 "MOV $dst.hi,$src\n\t"
11782 "SAR $dst.hi,31" %}
11783 ins_encode(convert_int_long(dst,src));
11784 ins_pipe( ialu_reg_reg_long );
11785 %}
11786
11787 // Zero-extend convert int to long
11788 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11789 match(Set dst (AndL (ConvI2L src) mask) );
11790 effect( KILL flags );
11791 ins_cost(250);
11792 format %{ "MOV $dst.lo,$src\n\t"
11793 "XOR $dst.hi,$dst.hi" %}
11794 opcode(0x33); // XOR
11795 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11796 ins_pipe( ialu_reg_reg_long );
11797 %}
11798
11799 // Zero-extend long
11800 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11801 match(Set dst (AndL src mask) );
11802 effect( KILL flags );
11803 ins_cost(250);
11804 format %{ "MOV $dst.lo,$src.lo\n\t"
11805 "XOR $dst.hi,$dst.hi\n\t" %}
11806 opcode(0x33); // XOR
11807 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11808 ins_pipe( ialu_reg_reg_long );
11809 %}
11810
11811 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11812 predicate (UseSSE<=1);
11813 match(Set dst (ConvL2D src));
11814 effect( KILL cr );
11815 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11816 "PUSH $src.lo\n\t"
11817 "FILD ST,[ESP + #0]\n\t"
11818 "ADD ESP,8\n\t"
11819 "FSTP_D $dst\t# D-round" %}
11820 opcode(0xDF, 0x5); /* DF /5 */
11821 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11822 ins_pipe( pipe_slow );
11823 %}
11824
11825 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11826 predicate (UseSSE>=2);
11827 match(Set dst (ConvL2D src));
11828 effect( KILL cr );
11829 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11830 "PUSH $src.lo\n\t"
11831 "FILD_D [ESP]\n\t"
11832 "FSTP_D [ESP]\n\t"
11833 "MOVSD $dst,[ESP]\n\t"
11834 "ADD ESP,8" %}
11835 opcode(0xDF, 0x5); /* DF /5 */
11836 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11837 ins_pipe( pipe_slow );
11838 %}
11839
11840 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11841 predicate (UseSSE>=1);
11842 match(Set dst (ConvL2F src));
11843 effect( KILL cr );
11844 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11845 "PUSH $src.lo\n\t"
11846 "FILD_D [ESP]\n\t"
11847 "FSTP_S [ESP]\n\t"
11848 "MOVSS $dst,[ESP]\n\t"
11849 "ADD ESP,8" %}
11850 opcode(0xDF, 0x5); /* DF /5 */
11851 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11852 ins_pipe( pipe_slow );
11853 %}
11854
11855 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11856 match(Set dst (ConvL2F src));
11857 effect( KILL cr );
11858 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11859 "PUSH $src.lo\n\t"
11860 "FILD ST,[ESP + #0]\n\t"
11861 "ADD ESP,8\n\t"
11862 "FSTP_S $dst\t# F-round" %}
11863 opcode(0xDF, 0x5); /* DF /5 */
11864 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11865 ins_pipe( pipe_slow );
11866 %}
11867
11868 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11869 match(Set dst (ConvL2I src));
11870 effect( DEF dst, USE src );
11871 format %{ "MOV $dst,$src.lo" %}
11872 ins_encode(enc_CopyL_Lo(dst,src));
11873 ins_pipe( ialu_reg_reg );
11874 %}
11875
11876
11877 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11878 match(Set dst (MoveF2I src));
11879 effect( DEF dst, USE src );
11880 ins_cost(100);
11881 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11882 ins_encode %{
11883 __ movl($dst$$Register, Address(rsp, $src$$disp));
11884 %}
11885 ins_pipe( ialu_reg_mem );
11886 %}
11887
11888 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11889 predicate(UseSSE==0);
11890 match(Set dst (MoveF2I src));
11891 effect( DEF dst, USE src );
11892
11893 ins_cost(125);
11894 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11895 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11896 ins_pipe( fpu_mem_reg );
11897 %}
11898
11899 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11900 predicate(UseSSE>=1);
11901 match(Set dst (MoveF2I src));
11902 effect( DEF dst, USE src );
11903
11904 ins_cost(95);
11905 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11906 ins_encode %{
11907 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11908 %}
11909 ins_pipe( pipe_slow );
11910 %}
11911
11912 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11913 predicate(UseSSE>=2);
11914 match(Set dst (MoveF2I src));
11915 effect( DEF dst, USE src );
11916 ins_cost(85);
11917 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11918 ins_encode %{
11919 __ movdl($dst$$Register, $src$$XMMRegister);
11920 %}
11921 ins_pipe( pipe_slow );
11922 %}
11923
11924 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11925 match(Set dst (MoveI2F src));
11926 effect( DEF dst, USE src );
11927
11928 ins_cost(100);
11929 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11930 ins_encode %{
11931 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11932 %}
11933 ins_pipe( ialu_mem_reg );
11934 %}
11935
11936
11937 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11938 predicate(UseSSE==0);
11939 match(Set dst (MoveI2F src));
11940 effect(DEF dst, USE src);
11941
11942 ins_cost(125);
11943 format %{ "FLD_S $src\n\t"
11944 "FSTP $dst\t# MoveI2F_stack_reg" %}
11945 opcode(0xD9); /* D9 /0, FLD m32real */
11946 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11947 Pop_Reg_FPR(dst) );
11948 ins_pipe( fpu_reg_mem );
11949 %}
11950
11951 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11952 predicate(UseSSE>=1);
11953 match(Set dst (MoveI2F src));
11954 effect( DEF dst, USE src );
11955
11956 ins_cost(95);
11957 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11958 ins_encode %{
11959 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11960 %}
11961 ins_pipe( pipe_slow );
11962 %}
11963
11964 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11965 predicate(UseSSE>=2);
11966 match(Set dst (MoveI2F src));
11967 effect( DEF dst, USE src );
11968
11969 ins_cost(85);
11970 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11971 ins_encode %{
11972 __ movdl($dst$$XMMRegister, $src$$Register);
11973 %}
11974 ins_pipe( pipe_slow );
11975 %}
11976
11977 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11978 match(Set dst (MoveD2L src));
11979 effect(DEF dst, USE src);
11980
11981 ins_cost(250);
11982 format %{ "MOV $dst.lo,$src\n\t"
11983 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11984 opcode(0x8B, 0x8B);
11985 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11986 ins_pipe( ialu_mem_long_reg );
11987 %}
11988
11989 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11990 predicate(UseSSE<=1);
11991 match(Set dst (MoveD2L src));
11992 effect(DEF dst, USE src);
11993
11994 ins_cost(125);
11995 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11996 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11997 ins_pipe( fpu_mem_reg );
11998 %}
11999
12000 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
12001 predicate(UseSSE>=2);
12002 match(Set dst (MoveD2L src));
12003 effect(DEF dst, USE src);
12004 ins_cost(95);
12005 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12006 ins_encode %{
12007 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
12008 %}
12009 ins_pipe( pipe_slow );
12010 %}
12011
12012 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
12013 predicate(UseSSE>=2);
12014 match(Set dst (MoveD2L src));
12015 effect(DEF dst, USE src, TEMP tmp);
12016 ins_cost(85);
12017 format %{ "MOVD $dst.lo,$src\n\t"
12018 "PSHUFLW $tmp,$src,0x4E\n\t"
12019 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12020 ins_encode %{
12021 __ movdl($dst$$Register, $src$$XMMRegister);
12022 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
12023 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
12024 %}
12025 ins_pipe( pipe_slow );
12026 %}
12027
12028 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12029 match(Set dst (MoveL2D src));
12030 effect(DEF dst, USE src);
12031
12032 ins_cost(200);
12033 format %{ "MOV $dst,$src.lo\n\t"
12034 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12035 opcode(0x89, 0x89);
12036 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12037 ins_pipe( ialu_mem_long_reg );
12038 %}
12039
12040
12041 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
12042 predicate(UseSSE<=1);
12043 match(Set dst (MoveL2D src));
12044 effect(DEF dst, USE src);
12045 ins_cost(125);
12046
12047 format %{ "FLD_D $src\n\t"
12048 "FSTP $dst\t# MoveL2D_stack_reg" %}
12049 opcode(0xDD); /* DD /0, FLD m64real */
12050 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12051 Pop_Reg_DPR(dst) );
12052 ins_pipe( fpu_reg_mem );
12053 %}
12054
12055
12056 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
12057 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12058 match(Set dst (MoveL2D src));
12059 effect(DEF dst, USE src);
12060
12061 ins_cost(95);
12062 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12063 ins_encode %{
12064 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12065 %}
12066 ins_pipe( pipe_slow );
12067 %}
12068
12069 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
12070 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12071 match(Set dst (MoveL2D src));
12072 effect(DEF dst, USE src);
12073
12074 ins_cost(95);
12075 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12076 ins_encode %{
12077 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12078 %}
12079 ins_pipe( pipe_slow );
12080 %}
12081
12082 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
12083 predicate(UseSSE>=2);
12084 match(Set dst (MoveL2D src));
12085 effect(TEMP dst, USE src, TEMP tmp);
12086 ins_cost(85);
12087 format %{ "MOVD $dst,$src.lo\n\t"
12088 "MOVD $tmp,$src.hi\n\t"
12089 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12090 ins_encode %{
12091 __ movdl($dst$$XMMRegister, $src$$Register);
12092 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
12093 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
12094 %}
12095 ins_pipe( pipe_slow );
12096 %}
12097
12098
12099 // =======================================================================
12100 // fast clearing of an array
12101 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12102 predicate(!UseFastStosb);
12103 match(Set dummy (ClearArray cnt base));
12104 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12105 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
12106 "SHL ECX,1\t# Convert doublewords to words\n\t"
12107 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12108 ins_encode %{
12109 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
12110 %}
12111 ins_pipe( pipe_slow );
12112 %}
12113
12114 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12115 predicate(UseFastStosb);
12116 match(Set dummy (ClearArray cnt base));
12117 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12118 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
12119 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
12120 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
12121 ins_encode %{
12122 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
12123 %}
12124 ins_pipe( pipe_slow );
12125 %}
12126
12127 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
12128 eAXRegI result, regD tmp1, eFlagsReg cr) %{
12129 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12130 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12131
12132 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12133 ins_encode %{
12134 __ string_compare($str1$$Register, $str2$$Register,
12135 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12136 $tmp1$$XMMRegister);
12137 %}
12138 ins_pipe( pipe_slow );
12139 %}
12140
12141 // fast string equals
12142 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12143 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12144 match(Set result (StrEquals (Binary str1 str2) cnt));
12145 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12146
12147 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12148 ins_encode %{
12149 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12150 $cnt$$Register, $result$$Register, $tmp3$$Register,
12151 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12152 %}
12153 ins_pipe( pipe_slow );
12154 %}
12155
12156 // fast search of substring with known size.
12157 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
12158 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
12159 predicate(UseSSE42Intrinsics);
12160 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12161 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12162
12163 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
12164 ins_encode %{
12165 int icnt2 = (int)$int_cnt2$$constant;
12166 if (icnt2 >= 8) {
12167 // IndexOf for constant substrings with size >= 8 elements
12168 // which don't need to be loaded through stack.
12169 __ string_indexofC8($str1$$Register, $str2$$Register,
12170 $cnt1$$Register, $cnt2$$Register,
12171 icnt2, $result$$Register,
12172 $vec$$XMMRegister, $tmp$$Register);
12173 } else {
12174 // Small strings are loaded through stack if they cross page boundary.
12175 __ string_indexof($str1$$Register, $str2$$Register,
12176 $cnt1$$Register, $cnt2$$Register,
12177 icnt2, $result$$Register,
12178 $vec$$XMMRegister, $tmp$$Register);
12179 }
12180 %}
12181 ins_pipe( pipe_slow );
12182 %}
12183
12184 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12185 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
12186 predicate(UseSSE42Intrinsics);
12187 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12188 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12189
12190 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12191 ins_encode %{
12192 __ string_indexof($str1$$Register, $str2$$Register,
12193 $cnt1$$Register, $cnt2$$Register,
12194 (-1), $result$$Register,
12195 $vec$$XMMRegister, $tmp$$Register);
12196 %}
12197 ins_pipe( pipe_slow );
12198 %}
12199
12200 // fast array equals
12201 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12202 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12203 %{
12204 match(Set result (AryEq ary1 ary2));
12205 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12206 //ins_cost(300);
12207
12208 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12209 ins_encode %{
12210 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12211 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12212 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12213 %}
12214 ins_pipe( pipe_slow );
12215 %}
12216
12217 // encode char[] to byte[] in ISO_8859_1
12218 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
12219 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
12220 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
12221 match(Set result (EncodeISOArray src (Binary dst len)));
12222 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12223
12224 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
12225 ins_encode %{
12226 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12227 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12228 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
12229 %}
12230 ins_pipe( pipe_slow );
12231 %}
12232
12233
12234 //----------Control Flow Instructions------------------------------------------
12235 // Signed compare Instructions
12236 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
12237 match(Set cr (CmpI op1 op2));
12238 effect( DEF cr, USE op1, USE op2 );
12239 format %{ "CMP $op1,$op2" %}
12240 opcode(0x3B); /* Opcode 3B /r */
12241 ins_encode( OpcP, RegReg( op1, op2) );
12242 ins_pipe( ialu_cr_reg_reg );
12243 %}
12244
12245 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
12246 match(Set cr (CmpI op1 op2));
12247 effect( DEF cr, USE op1 );
12248 format %{ "CMP $op1,$op2" %}
12249 opcode(0x81,0x07); /* Opcode 81 /7 */
12250 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12251 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12252 ins_pipe( ialu_cr_reg_imm );
12253 %}
12254
12255 // Cisc-spilled version of cmpI_eReg
12256 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
12257 match(Set cr (CmpI op1 (LoadI op2)));
12258
12259 format %{ "CMP $op1,$op2" %}
12260 ins_cost(500);
12261 opcode(0x3B); /* Opcode 3B /r */
12262 ins_encode( OpcP, RegMem( op1, op2) );
12263 ins_pipe( ialu_cr_reg_mem );
12264 %}
12265
12266 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
12267 match(Set cr (CmpI src zero));
12268 effect( DEF cr, USE src );
12269
12270 format %{ "TEST $src,$src" %}
12271 opcode(0x85);
12272 ins_encode( OpcP, RegReg( src, src ) );
12273 ins_pipe( ialu_cr_reg_imm );
12274 %}
12275
12276 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
12277 match(Set cr (CmpI (AndI src con) zero));
12278
12279 format %{ "TEST $src,$con" %}
12280 opcode(0xF7,0x00);
12281 ins_encode( OpcP, RegOpc(src), Con32(con) );
12282 ins_pipe( ialu_cr_reg_imm );
12283 %}
12284
12285 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
12286 match(Set cr (CmpI (AndI src mem) zero));
12287
12288 format %{ "TEST $src,$mem" %}
12289 opcode(0x85);
12290 ins_encode( OpcP, RegMem( src, mem ) );
12291 ins_pipe( ialu_cr_reg_mem );
12292 %}
12293
12294 // Unsigned compare Instructions; really, same as signed except they
12295 // produce an eFlagsRegU instead of eFlagsReg.
12296 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
12297 match(Set cr (CmpU op1 op2));
12298
12299 format %{ "CMPu $op1,$op2" %}
12300 opcode(0x3B); /* Opcode 3B /r */
12301 ins_encode( OpcP, RegReg( op1, op2) );
12302 ins_pipe( ialu_cr_reg_reg );
12303 %}
12304
12305 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
12306 match(Set cr (CmpU op1 op2));
12307
12308 format %{ "CMPu $op1,$op2" %}
12309 opcode(0x81,0x07); /* Opcode 81 /7 */
12310 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12311 ins_pipe( ialu_cr_reg_imm );
12312 %}
12313
12314 // // Cisc-spilled version of cmpU_eReg
12315 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
12316 match(Set cr (CmpU op1 (LoadI op2)));
12317
12318 format %{ "CMPu $op1,$op2" %}
12319 ins_cost(500);
12320 opcode(0x3B); /* Opcode 3B /r */
12321 ins_encode( OpcP, RegMem( op1, op2) );
12322 ins_pipe( ialu_cr_reg_mem );
12323 %}
12324
12325 // // Cisc-spilled version of cmpU_eReg
12326 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
12327 // match(Set cr (CmpU (LoadI op1) op2));
12328 //
12329 // format %{ "CMPu $op1,$op2" %}
12330 // ins_cost(500);
12331 // opcode(0x39); /* Opcode 39 /r */
12332 // ins_encode( OpcP, RegMem( op1, op2) );
12333 //%}
12334
12335 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
12336 match(Set cr (CmpU src zero));
12337
12338 format %{ "TESTu $src,$src" %}
12339 opcode(0x85);
12340 ins_encode( OpcP, RegReg( src, src ) );
12341 ins_pipe( ialu_cr_reg_imm );
12342 %}
12343
12344 // Unsigned pointer compare Instructions
12345 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12346 match(Set cr (CmpP op1 op2));
12347
12348 format %{ "CMPu $op1,$op2" %}
12349 opcode(0x3B); /* Opcode 3B /r */
12350 ins_encode( OpcP, RegReg( op1, op2) );
12351 ins_pipe( ialu_cr_reg_reg );
12352 %}
12353
12354 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12355 match(Set cr (CmpP op1 op2));
12356
12357 format %{ "CMPu $op1,$op2" %}
12358 opcode(0x81,0x07); /* Opcode 81 /7 */
12359 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12360 ins_pipe( ialu_cr_reg_imm );
12361 %}
12362
12363 // // Cisc-spilled version of cmpP_eReg
12364 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12365 match(Set cr (CmpP op1 (LoadP op2)));
12366
12367 format %{ "CMPu $op1,$op2" %}
12368 ins_cost(500);
12369 opcode(0x3B); /* Opcode 3B /r */
12370 ins_encode( OpcP, RegMem( op1, op2) );
12371 ins_pipe( ialu_cr_reg_mem );
12372 %}
12373
12374 // // Cisc-spilled version of cmpP_eReg
12375 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12376 // match(Set cr (CmpP (LoadP op1) op2));
12377 //
12378 // format %{ "CMPu $op1,$op2" %}
12379 // ins_cost(500);
12380 // opcode(0x39); /* Opcode 39 /r */
12381 // ins_encode( OpcP, RegMem( op1, op2) );
12382 //%}
12383
12384 // Compare raw pointer (used in out-of-heap check).
12385 // Only works because non-oop pointers must be raw pointers
12386 // and raw pointers have no anti-dependencies.
12387 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12388 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
12389 match(Set cr (CmpP op1 (LoadP op2)));
12390
12391 format %{ "CMPu $op1,$op2" %}
12392 opcode(0x3B); /* Opcode 3B /r */
12393 ins_encode( OpcP, RegMem( op1, op2) );
12394 ins_pipe( ialu_cr_reg_mem );
12395 %}
12396
12397 //
12398 // This will generate a signed flags result. This should be ok
12399 // since any compare to a zero should be eq/neq.
12400 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12401 match(Set cr (CmpP src zero));
12402
12403 format %{ "TEST $src,$src" %}
12404 opcode(0x85);
12405 ins_encode( OpcP, RegReg( src, src ) );
12406 ins_pipe( ialu_cr_reg_imm );
12407 %}
12408
12409 // Cisc-spilled version of testP_reg
12410 // This will generate a signed flags result. This should be ok
12411 // since any compare to a zero should be eq/neq.
12412 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12413 match(Set cr (CmpP (LoadP op) zero));
12414
12415 format %{ "TEST $op,0xFFFFFFFF" %}
12416 ins_cost(500);
12417 opcode(0xF7); /* Opcode F7 /0 */
12418 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12419 ins_pipe( ialu_cr_reg_imm );
12420 %}
12421
12422 // Yanked all unsigned pointer compare operations.
12423 // Pointer compares are done with CmpP which is already unsigned.
12424
12425 //----------Max and Min--------------------------------------------------------
12426 // Min Instructions
12427 ////
12428 // *** Min and Max using the conditional move are slower than the
12429 // *** branch version on a Pentium III.
12430 // // Conditional move for min
12431 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12432 // effect( USE_DEF op2, USE op1, USE cr );
12433 // format %{ "CMOVlt $op2,$op1\t! min" %}
12434 // opcode(0x4C,0x0F);
12435 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12436 // ins_pipe( pipe_cmov_reg );
12437 //%}
12438 //
12439 //// Min Register with Register (P6 version)
12440 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12441 // predicate(VM_Version::supports_cmov() );
12442 // match(Set op2 (MinI op1 op2));
12443 // ins_cost(200);
12444 // expand %{
12445 // eFlagsReg cr;
12446 // compI_eReg(cr,op1,op2);
12447 // cmovI_reg_lt(op2,op1,cr);
12448 // %}
12449 //%}
12450
12451 // Min Register with Register (generic version)
12452 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12453 match(Set dst (MinI dst src));
12454 effect(KILL flags);
12455 ins_cost(300);
12456
12457 format %{ "MIN $dst,$src" %}
12458 opcode(0xCC);
12459 ins_encode( min_enc(dst,src) );
12460 ins_pipe( pipe_slow );
12461 %}
12462
12463 // Max Register with Register
12464 // *** Min and Max using the conditional move are slower than the
12465 // *** branch version on a Pentium III.
12466 // // Conditional move for max
12467 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12468 // effect( USE_DEF op2, USE op1, USE cr );
12469 // format %{ "CMOVgt $op2,$op1\t! max" %}
12470 // opcode(0x4F,0x0F);
12471 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12472 // ins_pipe( pipe_cmov_reg );
12473 //%}
12474 //
12475 // // Max Register with Register (P6 version)
12476 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12477 // predicate(VM_Version::supports_cmov() );
12478 // match(Set op2 (MaxI op1 op2));
12479 // ins_cost(200);
12480 // expand %{
12481 // eFlagsReg cr;
12482 // compI_eReg(cr,op1,op2);
12483 // cmovI_reg_gt(op2,op1,cr);
12484 // %}
12485 //%}
12486
12487 // Max Register with Register (generic version)
12488 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12489 match(Set dst (MaxI dst src));
12490 effect(KILL flags);
12491 ins_cost(300);
12492
12493 format %{ "MAX $dst,$src" %}
12494 opcode(0xCC);
12495 ins_encode( max_enc(dst,src) );
12496 ins_pipe( pipe_slow );
12497 %}
12498
12499 // ============================================================================
12500 // Counted Loop limit node which represents exact final iterator value.
12501 // Note: the resulting value should fit into integer range since
12502 // counted loops have limit check on overflow.
12503 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12504 match(Set limit (LoopLimit (Binary init limit) stride));
12505 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12506 ins_cost(300);
12507
12508 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12509 ins_encode %{
12510 int strd = (int)$stride$$constant;
12511 assert(strd != 1 && strd != -1, "sanity");
12512 int m1 = (strd > 0) ? 1 : -1;
12513 // Convert limit to long (EAX:EDX)
12514 __ cdql();
12515 // Convert init to long (init:tmp)
12516 __ movl($tmp$$Register, $init$$Register);
12517 __ sarl($tmp$$Register, 31);
12518 // $limit - $init
12519 __ subl($limit$$Register, $init$$Register);
12520 __ sbbl($limit_hi$$Register, $tmp$$Register);
12521 // + ($stride - 1)
12522 if (strd > 0) {
12523 __ addl($limit$$Register, (strd - 1));
12524 __ adcl($limit_hi$$Register, 0);
12525 __ movl($tmp$$Register, strd);
12526 } else {
12527 __ addl($limit$$Register, (strd + 1));
12528 __ adcl($limit_hi$$Register, -1);
12529 __ lneg($limit_hi$$Register, $limit$$Register);
12530 __ movl($tmp$$Register, -strd);
12531 }
12532 // signed devision: (EAX:EDX) / pos_stride
12533 __ idivl($tmp$$Register);
12534 if (strd < 0) {
12535 // restore sign
12536 __ negl($tmp$$Register);
12537 }
12538 // (EAX) * stride
12539 __ mull($tmp$$Register);
12540 // + init (ignore upper bits)
12541 __ addl($limit$$Register, $init$$Register);
12542 %}
12543 ins_pipe( pipe_slow );
12544 %}
12545
12546 // ============================================================================
12547 // Branch Instructions
12548 // Jump Table
12549 instruct jumpXtnd(rRegI switch_val) %{
12550 match(Jump switch_val);
12551 ins_cost(350);
12552 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12553 ins_encode %{
12554 // Jump to Address(table_base + switch_reg)
12555 Address index(noreg, $switch_val$$Register, Address::times_1);
12556 __ jump(ArrayAddress($constantaddress, index));
12557 %}
12558 ins_pipe(pipe_jmp);
12559 %}
12560
12561 // Jump Direct - Label defines a relative address from JMP+1
12562 instruct jmpDir(label labl) %{
12563 match(Goto);
12564 effect(USE labl);
12565
12566 ins_cost(300);
12567 format %{ "JMP $labl" %}
12568 size(5);
12569 ins_encode %{
12570 Label* L = $labl$$label;
12571 __ jmp(*L, false); // Always long jump
12572 %}
12573 ins_pipe( pipe_jmp );
12574 %}
12575
12576 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12577 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12578 match(If cop cr);
12579 effect(USE labl);
12580
12581 ins_cost(300);
12582 format %{ "J$cop $labl" %}
12583 size(6);
12584 ins_encode %{
12585 Label* L = $labl$$label;
12586 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12587 %}
12588 ins_pipe( pipe_jcc );
12589 %}
12590
12591 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12592 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12593 match(CountedLoopEnd cop cr);
12594 effect(USE labl);
12595
12596 ins_cost(300);
12597 format %{ "J$cop $labl\t# Loop end" %}
12598 size(6);
12599 ins_encode %{
12600 Label* L = $labl$$label;
12601 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12602 %}
12603 ins_pipe( pipe_jcc );
12604 %}
12605
12606 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12607 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12608 match(CountedLoopEnd cop cmp);
12609 effect(USE labl);
12610
12611 ins_cost(300);
12612 format %{ "J$cop,u $labl\t# Loop end" %}
12613 size(6);
12614 ins_encode %{
12615 Label* L = $labl$$label;
12616 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12617 %}
12618 ins_pipe( pipe_jcc );
12619 %}
12620
12621 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12622 match(CountedLoopEnd cop cmp);
12623 effect(USE labl);
12624
12625 ins_cost(200);
12626 format %{ "J$cop,u $labl\t# Loop end" %}
12627 size(6);
12628 ins_encode %{
12629 Label* L = $labl$$label;
12630 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12631 %}
12632 ins_pipe( pipe_jcc );
12633 %}
12634
12635 // Jump Direct Conditional - using unsigned comparison
12636 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12637 match(If cop cmp);
12638 effect(USE labl);
12639
12640 ins_cost(300);
12641 format %{ "J$cop,u $labl" %}
12642 size(6);
12643 ins_encode %{
12644 Label* L = $labl$$label;
12645 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12646 %}
12647 ins_pipe(pipe_jcc);
12648 %}
12649
12650 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12651 match(If cop cmp);
12652 effect(USE labl);
12653
12654 ins_cost(200);
12655 format %{ "J$cop,u $labl" %}
12656 size(6);
12657 ins_encode %{
12658 Label* L = $labl$$label;
12659 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12660 %}
12661 ins_pipe(pipe_jcc);
12662 %}
12663
12664 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12665 match(If cop cmp);
12666 effect(USE labl);
12667
12668 ins_cost(200);
12669 format %{ $$template
12670 if ($cop$$cmpcode == Assembler::notEqual) {
12671 $$emit$$"JP,u $labl\n\t"
12672 $$emit$$"J$cop,u $labl"
12673 } else {
12674 $$emit$$"JP,u done\n\t"
12675 $$emit$$"J$cop,u $labl\n\t"
12676 $$emit$$"done:"
12677 }
12678 %}
12679 ins_encode %{
12680 Label* l = $labl$$label;
12681 if ($cop$$cmpcode == Assembler::notEqual) {
12682 __ jcc(Assembler::parity, *l, false);
12683 __ jcc(Assembler::notEqual, *l, false);
12684 } else if ($cop$$cmpcode == Assembler::equal) {
12685 Label done;
12686 __ jccb(Assembler::parity, done);
12687 __ jcc(Assembler::equal, *l, false);
12688 __ bind(done);
12689 } else {
12690 ShouldNotReachHere();
12691 }
12692 %}
12693 ins_pipe(pipe_jcc);
12694 %}
12695
12696 // ============================================================================
12697 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12698 // array for an instance of the superklass. Set a hidden internal cache on a
12699 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12700 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12701 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12702 match(Set result (PartialSubtypeCheck sub super));
12703 effect( KILL rcx, KILL cr );
12704
12705 ins_cost(1100); // slightly larger than the next version
12706 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12707 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12708 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12709 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12710 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12711 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12712 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12713 "miss:\t" %}
12714
12715 opcode(0x1); // Force a XOR of EDI
12716 ins_encode( enc_PartialSubtypeCheck() );
12717 ins_pipe( pipe_slow );
12718 %}
12719
12720 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12721 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12722 effect( KILL rcx, KILL result );
12723
12724 ins_cost(1000);
12725 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12726 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12727 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12728 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12729 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12730 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12731 "miss:\t" %}
12732
12733 opcode(0x0); // No need to XOR EDI
12734 ins_encode( enc_PartialSubtypeCheck() );
12735 ins_pipe( pipe_slow );
12736 %}
12737
12738 // ============================================================================
12739 // Branch Instructions -- short offset versions
12740 //
12741 // These instructions are used to replace jumps of a long offset (the default
12742 // match) with jumps of a shorter offset. These instructions are all tagged
12743 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12744 // match rules in general matching. Instead, the ADLC generates a conversion
12745 // method in the MachNode which can be used to do in-place replacement of the
12746 // long variant with the shorter variant. The compiler will determine if a
12747 // branch can be taken by the is_short_branch_offset() predicate in the machine
12748 // specific code section of the file.
12749
12750 // Jump Direct - Label defines a relative address from JMP+1
12751 instruct jmpDir_short(label labl) %{
12752 match(Goto);
12753 effect(USE labl);
12754
12755 ins_cost(300);
12756 format %{ "JMP,s $labl" %}
12757 size(2);
12758 ins_encode %{
12759 Label* L = $labl$$label;
12760 __ jmpb(*L);
12761 %}
12762 ins_pipe( pipe_jmp );
12763 ins_short_branch(1);
12764 %}
12765
12766 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12767 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12768 match(If cop cr);
12769 effect(USE labl);
12770
12771 ins_cost(300);
12772 format %{ "J$cop,s $labl" %}
12773 size(2);
12774 ins_encode %{
12775 Label* L = $labl$$label;
12776 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12777 %}
12778 ins_pipe( pipe_jcc );
12779 ins_short_branch(1);
12780 %}
12781
12782 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12783 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12784 match(CountedLoopEnd cop cr);
12785 effect(USE labl);
12786
12787 ins_cost(300);
12788 format %{ "J$cop,s $labl\t# Loop end" %}
12789 size(2);
12790 ins_encode %{
12791 Label* L = $labl$$label;
12792 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12793 %}
12794 ins_pipe( pipe_jcc );
12795 ins_short_branch(1);
12796 %}
12797
12798 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12799 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12800 match(CountedLoopEnd cop cmp);
12801 effect(USE labl);
12802
12803 ins_cost(300);
12804 format %{ "J$cop,us $labl\t# Loop end" %}
12805 size(2);
12806 ins_encode %{
12807 Label* L = $labl$$label;
12808 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12809 %}
12810 ins_pipe( pipe_jcc );
12811 ins_short_branch(1);
12812 %}
12813
12814 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12815 match(CountedLoopEnd cop cmp);
12816 effect(USE labl);
12817
12818 ins_cost(300);
12819 format %{ "J$cop,us $labl\t# Loop end" %}
12820 size(2);
12821 ins_encode %{
12822 Label* L = $labl$$label;
12823 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12824 %}
12825 ins_pipe( pipe_jcc );
12826 ins_short_branch(1);
12827 %}
12828
12829 // Jump Direct Conditional - using unsigned comparison
12830 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12831 match(If cop cmp);
12832 effect(USE labl);
12833
12834 ins_cost(300);
12835 format %{ "J$cop,us $labl" %}
12836 size(2);
12837 ins_encode %{
12838 Label* L = $labl$$label;
12839 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12840 %}
12841 ins_pipe( pipe_jcc );
12842 ins_short_branch(1);
12843 %}
12844
12845 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12846 match(If cop cmp);
12847 effect(USE labl);
12848
12849 ins_cost(300);
12850 format %{ "J$cop,us $labl" %}
12851 size(2);
12852 ins_encode %{
12853 Label* L = $labl$$label;
12854 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12855 %}
12856 ins_pipe( pipe_jcc );
12857 ins_short_branch(1);
12858 %}
12859
12860 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12861 match(If cop cmp);
12862 effect(USE labl);
12863
12864 ins_cost(300);
12865 format %{ $$template
12866 if ($cop$$cmpcode == Assembler::notEqual) {
12867 $$emit$$"JP,u,s $labl\n\t"
12868 $$emit$$"J$cop,u,s $labl"
12869 } else {
12870 $$emit$$"JP,u,s done\n\t"
12871 $$emit$$"J$cop,u,s $labl\n\t"
12872 $$emit$$"done:"
12873 }
12874 %}
12875 size(4);
12876 ins_encode %{
12877 Label* l = $labl$$label;
12878 if ($cop$$cmpcode == Assembler::notEqual) {
12879 __ jccb(Assembler::parity, *l);
12880 __ jccb(Assembler::notEqual, *l);
12881 } else if ($cop$$cmpcode == Assembler::equal) {
12882 Label done;
12883 __ jccb(Assembler::parity, done);
12884 __ jccb(Assembler::equal, *l);
12885 __ bind(done);
12886 } else {
12887 ShouldNotReachHere();
12888 }
12889 %}
12890 ins_pipe(pipe_jcc);
12891 ins_short_branch(1);
12892 %}
12893
12894 // ============================================================================
12895 // Long Compare
12896 //
12897 // Currently we hold longs in 2 registers. Comparing such values efficiently
12898 // is tricky. The flavor of compare used depends on whether we are testing
12899 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12900 // The GE test is the negated LT test. The LE test can be had by commuting
12901 // the operands (yielding a GE test) and then negating; negate again for the
12902 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12903 // NE test is negated from that.
12904
12905 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12906 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12907 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12908 // are collapsed internally in the ADLC's dfa-gen code. The match for
12909 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12910 // foo match ends up with the wrong leaf. One fix is to not match both
12911 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12912 // both forms beat the trinary form of long-compare and both are very useful
12913 // on Intel which has so few registers.
12914
12915 // Manifest a CmpL result in an integer register. Very painful.
12916 // This is the test to avoid.
12917 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12918 match(Set dst (CmpL3 src1 src2));
12919 effect( KILL flags );
12920 ins_cost(1000);
12921 format %{ "XOR $dst,$dst\n\t"
12922 "CMP $src1.hi,$src2.hi\n\t"
12923 "JLT,s m_one\n\t"
12924 "JGT,s p_one\n\t"
12925 "CMP $src1.lo,$src2.lo\n\t"
12926 "JB,s m_one\n\t"
12927 "JEQ,s done\n"
12928 "p_one:\tINC $dst\n\t"
12929 "JMP,s done\n"
12930 "m_one:\tDEC $dst\n"
12931 "done:" %}
12932 ins_encode %{
12933 Label p_one, m_one, done;
12934 __ xorptr($dst$$Register, $dst$$Register);
12935 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12936 __ jccb(Assembler::less, m_one);
12937 __ jccb(Assembler::greater, p_one);
12938 __ cmpl($src1$$Register, $src2$$Register);
12939 __ jccb(Assembler::below, m_one);
12940 __ jccb(Assembler::equal, done);
12941 __ bind(p_one);
12942 __ incrementl($dst$$Register);
12943 __ jmpb(done);
12944 __ bind(m_one);
12945 __ decrementl($dst$$Register);
12946 __ bind(done);
12947 %}
12948 ins_pipe( pipe_slow );
12949 %}
12950
12951 //======
12952 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12953 // compares. Can be used for LE or GT compares by reversing arguments.
12954 // NOT GOOD FOR EQ/NE tests.
12955 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12956 match( Set flags (CmpL src zero ));
12957 ins_cost(100);
12958 format %{ "TEST $src.hi,$src.hi" %}
12959 opcode(0x85);
12960 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12961 ins_pipe( ialu_cr_reg_reg );
12962 %}
12963
12964 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12965 // compares. Can be used for LE or GT compares by reversing arguments.
12966 // NOT GOOD FOR EQ/NE tests.
12967 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12968 match( Set flags (CmpL src1 src2 ));
12969 effect( TEMP tmp );
12970 ins_cost(300);
12971 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12972 "MOV $tmp,$src1.hi\n\t"
12973 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12974 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12975 ins_pipe( ialu_cr_reg_reg );
12976 %}
12977
12978 // Long compares reg < zero/req OR reg >= zero/req.
12979 // Just a wrapper for a normal branch, plus the predicate test.
12980 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12981 match(If cmp flags);
12982 effect(USE labl);
12983 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12984 expand %{
12985 jmpCon(cmp,flags,labl); // JLT or JGE...
12986 %}
12987 %}
12988
12989 // Compare 2 longs and CMOVE longs.
12990 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12991 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12992 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12993 ins_cost(400);
12994 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12995 "CMOV$cmp $dst.hi,$src.hi" %}
12996 opcode(0x0F,0x40);
12997 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12998 ins_pipe( pipe_cmov_reg_long );
12999 %}
13000
13001 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13002 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13003 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13004 ins_cost(500);
13005 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13006 "CMOV$cmp $dst.hi,$src.hi" %}
13007 opcode(0x0F,0x40);
13008 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13009 ins_pipe( pipe_cmov_reg_long );
13010 %}
13011
13012 // Compare 2 longs and CMOVE ints.
13013 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
13014 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13015 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13016 ins_cost(200);
13017 format %{ "CMOV$cmp $dst,$src" %}
13018 opcode(0x0F,0x40);
13019 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13020 ins_pipe( pipe_cmov_reg );
13021 %}
13022
13023 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
13024 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13025 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13026 ins_cost(250);
13027 format %{ "CMOV$cmp $dst,$src" %}
13028 opcode(0x0F,0x40);
13029 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13030 ins_pipe( pipe_cmov_mem );
13031 %}
13032
13033 // Compare 2 longs and CMOVE ints.
13034 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13035 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13036 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13037 ins_cost(200);
13038 format %{ "CMOV$cmp $dst,$src" %}
13039 opcode(0x0F,0x40);
13040 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13041 ins_pipe( pipe_cmov_reg );
13042 %}
13043
13044 // Compare 2 longs and CMOVE doubles
13045 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
13046 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13047 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13048 ins_cost(200);
13049 expand %{
13050 fcmovDPR_regS(cmp,flags,dst,src);
13051 %}
13052 %}
13053
13054 // Compare 2 longs and CMOVE doubles
13055 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13056 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13057 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13058 ins_cost(200);
13059 expand %{
13060 fcmovD_regS(cmp,flags,dst,src);
13061 %}
13062 %}
13063
13064 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
13065 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13066 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13067 ins_cost(200);
13068 expand %{
13069 fcmovFPR_regS(cmp,flags,dst,src);
13070 %}
13071 %}
13072
13073 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13074 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13075 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13076 ins_cost(200);
13077 expand %{
13078 fcmovF_regS(cmp,flags,dst,src);
13079 %}
13080 %}
13081
13082 //======
13083 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13084 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
13085 match( Set flags (CmpL src zero ));
13086 effect(TEMP tmp);
13087 ins_cost(200);
13088 format %{ "MOV $tmp,$src.lo\n\t"
13089 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13090 ins_encode( long_cmp_flags0( src, tmp ) );
13091 ins_pipe( ialu_reg_reg_long );
13092 %}
13093
13094 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13095 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13096 match( Set flags (CmpL src1 src2 ));
13097 ins_cost(200+300);
13098 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13099 "JNE,s skip\n\t"
13100 "CMP $src1.hi,$src2.hi\n\t"
13101 "skip:\t" %}
13102 ins_encode( long_cmp_flags1( src1, src2 ) );
13103 ins_pipe( ialu_cr_reg_reg );
13104 %}
13105
13106 // Long compare reg == zero/reg OR reg != zero/reg
13107 // Just a wrapper for a normal branch, plus the predicate test.
13108 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13109 match(If cmp flags);
13110 effect(USE labl);
13111 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13112 expand %{
13113 jmpCon(cmp,flags,labl); // JEQ or JNE...
13114 %}
13115 %}
13116
13117 // Compare 2 longs and CMOVE longs.
13118 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13119 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13120 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13121 ins_cost(400);
13122 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13123 "CMOV$cmp $dst.hi,$src.hi" %}
13124 opcode(0x0F,0x40);
13125 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13126 ins_pipe( pipe_cmov_reg_long );
13127 %}
13128
13129 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13130 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13131 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13132 ins_cost(500);
13133 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13134 "CMOV$cmp $dst.hi,$src.hi" %}
13135 opcode(0x0F,0x40);
13136 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13137 ins_pipe( pipe_cmov_reg_long );
13138 %}
13139
13140 // Compare 2 longs and CMOVE ints.
13141 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
13142 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13143 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13144 ins_cost(200);
13145 format %{ "CMOV$cmp $dst,$src" %}
13146 opcode(0x0F,0x40);
13147 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13148 ins_pipe( pipe_cmov_reg );
13149 %}
13150
13151 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
13152 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13153 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13154 ins_cost(250);
13155 format %{ "CMOV$cmp $dst,$src" %}
13156 opcode(0x0F,0x40);
13157 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13158 ins_pipe( pipe_cmov_mem );
13159 %}
13160
13161 // Compare 2 longs and CMOVE ints.
13162 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13163 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13164 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13165 ins_cost(200);
13166 format %{ "CMOV$cmp $dst,$src" %}
13167 opcode(0x0F,0x40);
13168 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13169 ins_pipe( pipe_cmov_reg );
13170 %}
13171
13172 // Compare 2 longs and CMOVE doubles
13173 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
13174 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13175 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13176 ins_cost(200);
13177 expand %{
13178 fcmovDPR_regS(cmp,flags,dst,src);
13179 %}
13180 %}
13181
13182 // Compare 2 longs and CMOVE doubles
13183 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13184 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13185 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13186 ins_cost(200);
13187 expand %{
13188 fcmovD_regS(cmp,flags,dst,src);
13189 %}
13190 %}
13191
13192 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
13193 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13194 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13195 ins_cost(200);
13196 expand %{
13197 fcmovFPR_regS(cmp,flags,dst,src);
13198 %}
13199 %}
13200
13201 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13202 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13203 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13204 ins_cost(200);
13205 expand %{
13206 fcmovF_regS(cmp,flags,dst,src);
13207 %}
13208 %}
13209
13210 //======
13211 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13212 // Same as cmpL_reg_flags_LEGT except must negate src
13213 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
13214 match( Set flags (CmpL src zero ));
13215 effect( TEMP tmp );
13216 ins_cost(300);
13217 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13218 "CMP $tmp,$src.lo\n\t"
13219 "SBB $tmp,$src.hi\n\t" %}
13220 ins_encode( long_cmp_flags3(src, tmp) );
13221 ins_pipe( ialu_reg_reg_long );
13222 %}
13223
13224 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13225 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13226 // requires a commuted test to get the same result.
13227 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
13228 match( Set flags (CmpL src1 src2 ));
13229 effect( TEMP tmp );
13230 ins_cost(300);
13231 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13232 "MOV $tmp,$src2.hi\n\t"
13233 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13234 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13235 ins_pipe( ialu_cr_reg_reg );
13236 %}
13237
13238 // Long compares reg < zero/req OR reg >= zero/req.
13239 // Just a wrapper for a normal branch, plus the predicate test
13240 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13241 match(If cmp flags);
13242 effect(USE labl);
13243 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13244 ins_cost(300);
13245 expand %{
13246 jmpCon(cmp,flags,labl); // JGT or JLE...
13247 %}
13248 %}
13249
13250 // Compare 2 longs and CMOVE longs.
13251 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13252 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13253 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13254 ins_cost(400);
13255 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13256 "CMOV$cmp $dst.hi,$src.hi" %}
13257 opcode(0x0F,0x40);
13258 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13259 ins_pipe( pipe_cmov_reg_long );
13260 %}
13261
13262 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13263 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13264 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13265 ins_cost(500);
13266 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13267 "CMOV$cmp $dst.hi,$src.hi+4" %}
13268 opcode(0x0F,0x40);
13269 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13270 ins_pipe( pipe_cmov_reg_long );
13271 %}
13272
13273 // Compare 2 longs and CMOVE ints.
13274 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
13275 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13276 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13277 ins_cost(200);
13278 format %{ "CMOV$cmp $dst,$src" %}
13279 opcode(0x0F,0x40);
13280 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13281 ins_pipe( pipe_cmov_reg );
13282 %}
13283
13284 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
13285 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13286 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13287 ins_cost(250);
13288 format %{ "CMOV$cmp $dst,$src" %}
13289 opcode(0x0F,0x40);
13290 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13291 ins_pipe( pipe_cmov_mem );
13292 %}
13293
13294 // Compare 2 longs and CMOVE ptrs.
13295 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13296 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13297 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13298 ins_cost(200);
13299 format %{ "CMOV$cmp $dst,$src" %}
13300 opcode(0x0F,0x40);
13301 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13302 ins_pipe( pipe_cmov_reg );
13303 %}
13304
13305 // Compare 2 longs and CMOVE doubles
13306 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
13307 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13308 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13309 ins_cost(200);
13310 expand %{
13311 fcmovDPR_regS(cmp,flags,dst,src);
13312 %}
13313 %}
13314
13315 // Compare 2 longs and CMOVE doubles
13316 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13317 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13318 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13319 ins_cost(200);
13320 expand %{
13321 fcmovD_regS(cmp,flags,dst,src);
13322 %}
13323 %}
13324
13325 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
13326 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13327 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13328 ins_cost(200);
13329 expand %{
13330 fcmovFPR_regS(cmp,flags,dst,src);
13331 %}
13332 %}
13333
13334
13335 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13336 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13337 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13338 ins_cost(200);
13339 expand %{
13340 fcmovF_regS(cmp,flags,dst,src);
13341 %}
13342 %}
13343
13344
13345 // ============================================================================
13346 // Procedure Call/Return Instructions
13347 // Call Java Static Instruction
13348 // Note: If this code changes, the corresponding ret_addr_offset() and
13349 // compute_padding() functions will have to be adjusted.
13350 instruct CallStaticJavaDirect(method meth) %{
13351 match(CallStaticJava);
13352 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13353 effect(USE meth);
13354
13355 ins_cost(300);
13356 format %{ "CALL,static " %}
13357 opcode(0xE8); /* E8 cd */
13358 ins_encode( pre_call_resets,
13359 Java_Static_Call( meth ),
13360 call_epilog,
13361 post_call_FPU );
13362 ins_pipe( pipe_slow );
13363 ins_alignment(4);
13364 %}
13365
13366 // Call Java Static Instruction (method handle version)
13367 // Note: If this code changes, the corresponding ret_addr_offset() and
13368 // compute_padding() functions will have to be adjusted.
13369 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13370 match(CallStaticJava);
13371 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13372 effect(USE meth);
13373 // EBP is saved by all callees (for interpreter stack correction).
13374 // We use it here for a similar purpose, in {preserve,restore}_SP.
13375
13376 ins_cost(300);
13377 format %{ "CALL,static/MethodHandle " %}
13378 opcode(0xE8); /* E8 cd */
13379 ins_encode( pre_call_resets,
13380 preserve_SP,
13381 Java_Static_Call( meth ),
13382 restore_SP,
13383 call_epilog,
13384 post_call_FPU );
13385 ins_pipe( pipe_slow );
13386 ins_alignment(4);
13387 %}
13388
13389 // Call Java Dynamic Instruction
13390 // Note: If this code changes, the corresponding ret_addr_offset() and
13391 // compute_padding() functions will have to be adjusted.
13392 instruct CallDynamicJavaDirect(method meth) %{
13393 match(CallDynamicJava);
13394 effect(USE meth);
13395
13396 ins_cost(300);
13397 format %{ "MOV EAX,(oop)-1\n\t"
13398 "CALL,dynamic" %}
13399 opcode(0xE8); /* E8 cd */
13400 ins_encode( pre_call_resets,
13401 Java_Dynamic_Call( meth ),
13402 call_epilog,
13403 post_call_FPU );
13404 ins_pipe( pipe_slow );
13405 ins_alignment(4);
13406 %}
13407
13408 // Call Runtime Instruction
13409 instruct CallRuntimeDirect(method meth) %{
13410 match(CallRuntime );
13411 effect(USE meth);
13412
13413 ins_cost(300);
13414 format %{ "CALL,runtime " %}
13415 opcode(0xE8); /* E8 cd */
13416 // Use FFREEs to clear entries in float stack
13417 ins_encode( pre_call_resets,
13418 FFree_Float_Stack_All,
13419 Java_To_Runtime( meth ),
13420 post_call_FPU );
13421 ins_pipe( pipe_slow );
13422 %}
13423
13424 // Call runtime without safepoint
13425 instruct CallLeafDirect(method meth) %{
13426 match(CallLeaf);
13427 effect(USE meth);
13428
13429 ins_cost(300);
13430 format %{ "CALL_LEAF,runtime " %}
13431 opcode(0xE8); /* E8 cd */
13432 ins_encode( pre_call_resets,
13433 FFree_Float_Stack_All,
13434 Java_To_Runtime( meth ),
13435 Verify_FPU_For_Leaf, post_call_FPU );
13436 ins_pipe( pipe_slow );
13437 %}
13438
13439 instruct CallLeafNoFPDirect(method meth) %{
13440 match(CallLeafNoFP);
13441 effect(USE meth);
13442
13443 ins_cost(300);
13444 format %{ "CALL_LEAF_NOFP,runtime " %}
13445 opcode(0xE8); /* E8 cd */
13446 ins_encode(Java_To_Runtime(meth));
13447 ins_pipe( pipe_slow );
13448 %}
13449
13450
13451 // Return Instruction
13452 // Remove the return address & jump to it.
13453 instruct Ret() %{
13454 match(Return);
13455 format %{ "RET" %}
13456 opcode(0xC3);
13457 ins_encode(OpcP);
13458 ins_pipe( pipe_jmp );
13459 %}
13460
13461 // Tail Call; Jump from runtime stub to Java code.
13462 // Also known as an 'interprocedural jump'.
13463 // Target of jump will eventually return to caller.
13464 // TailJump below removes the return address.
13465 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13466 match(TailCall jump_target method_oop );
13467 ins_cost(300);
13468 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13469 opcode(0xFF, 0x4); /* Opcode FF /4 */
13470 ins_encode( OpcP, RegOpc(jump_target) );
13471 ins_pipe( pipe_jmp );
13472 %}
13473
13474
13475 // Tail Jump; remove the return address; jump to target.
13476 // TailCall above leaves the return address around.
13477 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13478 match( TailJump jump_target ex_oop );
13479 ins_cost(300);
13480 format %{ "POP EDX\t# pop return address into dummy\n\t"
13481 "JMP $jump_target " %}
13482 opcode(0xFF, 0x4); /* Opcode FF /4 */
13483 ins_encode( enc_pop_rdx,
13484 OpcP, RegOpc(jump_target) );
13485 ins_pipe( pipe_jmp );
13486 %}
13487
13488 // Create exception oop: created by stack-crawling runtime code.
13489 // Created exception is now available to this handler, and is setup
13490 // just prior to jumping to this handler. No code emitted.
13491 instruct CreateException( eAXRegP ex_oop )
13492 %{
13493 match(Set ex_oop (CreateEx));
13494
13495 size(0);
13496 // use the following format syntax
13497 format %{ "# exception oop is in EAX; no code emitted" %}
13498 ins_encode();
13499 ins_pipe( empty );
13500 %}
13501
13502
13503 // Rethrow exception:
13504 // The exception oop will come in the first argument position.
13505 // Then JUMP (not call) to the rethrow stub code.
13506 instruct RethrowException()
13507 %{
13508 match(Rethrow);
13509
13510 // use the following format syntax
13511 format %{ "JMP rethrow_stub" %}
13512 ins_encode(enc_rethrow);
13513 ins_pipe( pipe_jmp );
13514 %}
13515
13516 // inlined locking and unlocking
13517
13518
13519 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13520 match( Set cr (FastLock object box) );
13521 effect( TEMP tmp, TEMP scr, USE_KILL box );
13522 ins_cost(300);
13523 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13524 ins_encode( Fast_Lock(object,box,tmp,scr) );
13525 ins_pipe( pipe_slow );
13526 %}
13527
13528 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13529 match( Set cr (FastUnlock object box) );
13530 effect( TEMP tmp, USE_KILL box );
13531 ins_cost(300);
13532 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13533 ins_encode( Fast_Unlock(object,box,tmp) );
13534 ins_pipe( pipe_slow );
13535 %}
13536
13537
13538
13539 // ============================================================================
13540 // Safepoint Instruction
13541 instruct safePoint_poll(eFlagsReg cr) %{
13542 match(SafePoint);
13543 effect(KILL cr);
13544
13545 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13546 // On SPARC that might be acceptable as we can generate the address with
13547 // just a sethi, saving an or. By polling at offset 0 we can end up
13548 // putting additional pressure on the index-0 in the D$. Because of
13549 // alignment (just like the situation at hand) the lower indices tend
13550 // to see more traffic. It'd be better to change the polling address
13551 // to offset 0 of the last $line in the polling page.
13552
13553 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13554 ins_cost(125);
13555 size(6) ;
13556 ins_encode( Safepoint_Poll() );
13557 ins_pipe( ialu_reg_mem );
13558 %}
13559
13560
13561 // ============================================================================
13562 // This name is KNOWN by the ADLC and cannot be changed.
13563 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13564 // for this guy.
13565 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13566 match(Set dst (ThreadLocal));
13567 effect(DEF dst, KILL cr);
13568
13569 format %{ "MOV $dst, Thread::current()" %}
13570 ins_encode %{
13571 Register dstReg = as_Register($dst$$reg);
13572 __ get_thread(dstReg);
13573 %}
13574 ins_pipe( ialu_reg_fat );
13575 %}
13576
13577
13578
13579 //----------PEEPHOLE RULES-----------------------------------------------------
13580 // These must follow all instruction definitions as they use the names
13581 // defined in the instructions definitions.
13582 //
13583 // peepmatch ( root_instr_name [preceding_instruction]* );
13584 //
13585 // peepconstraint %{
13586 // (instruction_number.operand_name relational_op instruction_number.operand_name
13587 // [, ...] );
13588 // // instruction numbers are zero-based using left to right order in peepmatch
13589 //
13590 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13591 // // provide an instruction_number.operand_name for each operand that appears
13592 // // in the replacement instruction's match rule
13593 //
13594 // ---------VM FLAGS---------------------------------------------------------
13595 //
13596 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13597 //
13598 // Each peephole rule is given an identifying number starting with zero and
13599 // increasing by one in the order seen by the parser. An individual peephole
13600 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13601 // on the command-line.
13602 //
13603 // ---------CURRENT LIMITATIONS----------------------------------------------
13604 //
13605 // Only match adjacent instructions in same basic block
13606 // Only equality constraints
13607 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13608 // Only one replacement instruction
13609 //
13610 // ---------EXAMPLE----------------------------------------------------------
13611 //
13612 // // pertinent parts of existing instructions in architecture description
13613 // instruct movI(rRegI dst, rRegI src) %{
13614 // match(Set dst (CopyI src));
13615 // %}
13616 //
13617 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13618 // match(Set dst (AddI dst src));
13619 // effect(KILL cr);
13620 // %}
13621 //
13622 // // Change (inc mov) to lea
13623 // peephole %{
13624 // // increment preceeded by register-register move
13625 // peepmatch ( incI_eReg movI );
13626 // // require that the destination register of the increment
13627 // // match the destination register of the move
13628 // peepconstraint ( 0.dst == 1.dst );
13629 // // construct a replacement instruction that sets
13630 // // the destination to ( move's source register + one )
13631 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13632 // %}
13633 //
13634 // Implementation no longer uses movX instructions since
13635 // machine-independent system no longer uses CopyX nodes.
13636 //
13637 // peephole %{
13638 // peepmatch ( incI_eReg movI );
13639 // peepconstraint ( 0.dst == 1.dst );
13640 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13641 // %}
13642 //
13643 // peephole %{
13644 // peepmatch ( decI_eReg movI );
13645 // peepconstraint ( 0.dst == 1.dst );
13646 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13647 // %}
13648 //
13649 // peephole %{
13650 // peepmatch ( addI_eReg_imm movI );
13651 // peepconstraint ( 0.dst == 1.dst );
13652 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13653 // %}
13654 //
13655 // peephole %{
13656 // peepmatch ( addP_eReg_imm movP );
13657 // peepconstraint ( 0.dst == 1.dst );
13658 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13659 // %}
13660
13661 // // Change load of spilled value to only a spill
13662 // instruct storeI(memory mem, rRegI src) %{
13663 // match(Set mem (StoreI mem src));
13664 // %}
13665 //
13666 // instruct loadI(rRegI dst, memory mem) %{
13667 // match(Set dst (LoadI mem));
13668 // %}
13669 //
13670 peephole %{
13671 peepmatch ( loadI storeI );
13672 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13673 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13674 %}
13675
13676 //----------SMARTSPILL RULES---------------------------------------------------
13677 // These must follow all instruction definitions as they use the names
13678 // defined in the instructions definitions.