5695 Register Rdst = $dst$$Register;
5696 Register Rsrc = $src$$Register;
5697 Label msw_is_zero;
5698 Label not_zero;
5699 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5700 __ jccb(Assembler::zero, msw_is_zero);
5701 __ addl(Rdst, BitsPerInt);
5702 __ jmpb(not_zero);
5703 __ bind(msw_is_zero);
5704 __ bsrl(Rdst, Rsrc);
5705 __ jccb(Assembler::notZero, not_zero);
5706 __ movl(Rdst, -1);
5707 __ bind(not_zero);
5708 __ negl(Rdst);
5709 __ addl(Rdst, BitsPerLong - 1);
5710 %}
5711 ins_pipe(ialu_reg);
5712 %}
5713
5714 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5715 match(Set dst (CountTrailingZerosI src));
5716 effect(KILL cr);
5717
5718 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5719 "JNZ done\n\t"
5720 "MOV $dst, 32\n"
5721 "done:" %}
5722 ins_encode %{
5723 Register Rdst = $dst$$Register;
5724 Label done;
5725 __ bsfl(Rdst, $src$$Register);
5726 __ jccb(Assembler::notZero, done);
5727 __ movl(Rdst, BitsPerInt);
5728 __ bind(done);
5729 %}
5730 ins_pipe(ialu_reg);
5731 %}
5732
5733 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5734 match(Set dst (CountTrailingZerosL src));
5735 effect(TEMP dst, KILL cr);
5736
5737 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5738 "JNZ done\n\t"
5739 "BSF $dst, $src.hi\n\t"
5740 "JNZ msw_not_zero\n\t"
5741 "MOV $dst, 32\n"
5742 "msw_not_zero:\n\t"
5743 "ADD $dst, 32\n"
5744 "done:" %}
5745 ins_encode %{
5746 Register Rdst = $dst$$Register;
5747 Register Rsrc = $src$$Register;
5748 Label msw_not_zero;
5749 Label done;
5750 __ bsfl(Rdst, Rsrc);
5751 __ jccb(Assembler::notZero, done);
5752 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5753 __ jccb(Assembler::notZero, msw_not_zero);
8685 ins_cost(150);
8686 format %{ "AND $dst,$src" %}
8687 opcode(0x21); /* Opcode 21 /r */
8688 ins_encode( OpcP, RegMem( src, dst ) );
8689 ins_pipe( ialu_mem_reg );
8690 %}
8691
8692 // And Memory with Immediate
8693 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8694 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8695 effect(KILL cr);
8696
8697 ins_cost(125);
8698 format %{ "AND $dst,$src" %}
8699 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8700 // ins_encode( MemImm( dst, src) );
8701 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8702 ins_pipe( ialu_mem_imm );
8703 %}
8704
8705 // Or Instructions
8706 // Or Register with Register
8707 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8708 match(Set dst (OrI dst src));
8709 effect(KILL cr);
8710
8711 size(2);
8712 format %{ "OR $dst,$src" %}
8713 opcode(0x0B);
8714 ins_encode( OpcP, RegReg( dst, src) );
8715 ins_pipe( ialu_reg_reg );
8716 %}
8717
8718 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8719 match(Set dst (OrI dst (CastP2X src)));
8720 effect(KILL cr);
8721
8722 size(2);
8723 format %{ "OR $dst,$src" %}
8724 opcode(0x0B);
9222 effect(KILL cr);
9223 format %{ "AND $dst.lo,$src.lo\n\t"
9224 "AND $dst.hi,$src.hi" %}
9225 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9226 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9227 ins_pipe( ialu_reg_long );
9228 %}
9229
9230 // And Long Register with Memory
9231 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9232 match(Set dst (AndL dst (LoadL mem)));
9233 effect(KILL cr);
9234 ins_cost(125);
9235 format %{ "AND $dst.lo,$mem\n\t"
9236 "AND $dst.hi,$mem+4" %}
9237 opcode(0x23, 0x23);
9238 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9239 ins_pipe( ialu_reg_long_mem );
9240 %}
9241
9242 // Or Long Register with Register
9243 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9244 match(Set dst (OrL dst src));
9245 effect(KILL cr);
9246 format %{ "OR $dst.lo,$src.lo\n\t"
9247 "OR $dst.hi,$src.hi" %}
9248 opcode(0x0B,0x0B);
9249 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9250 ins_pipe( ialu_reg_reg_long );
9251 %}
9252
9253 // Or Long Register with Immediate
9254 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9255 match(Set dst (OrL dst src));
9256 effect(KILL cr);
9257 format %{ "OR $dst.lo,$src.lo\n\t"
9258 "OR $dst.hi,$src.hi" %}
9259 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9260 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9261 ins_pipe( ialu_reg_long );
|
5695 Register Rdst = $dst$$Register;
5696 Register Rsrc = $src$$Register;
5697 Label msw_is_zero;
5698 Label not_zero;
5699 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5700 __ jccb(Assembler::zero, msw_is_zero);
5701 __ addl(Rdst, BitsPerInt);
5702 __ jmpb(not_zero);
5703 __ bind(msw_is_zero);
5704 __ bsrl(Rdst, Rsrc);
5705 __ jccb(Assembler::notZero, not_zero);
5706 __ movl(Rdst, -1);
5707 __ bind(not_zero);
5708 __ negl(Rdst);
5709 __ addl(Rdst, BitsPerLong - 1);
5710 %}
5711 ins_pipe(ialu_reg);
5712 %}
5713
5714 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5715 predicate(UseCountTrailingZerosInstruction);
5716 match(Set dst (CountTrailingZerosI src));
5717 effect(KILL cr);
5718
5719 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %}
5720 ins_encode %{
5721 __ tzcntl($dst$$Register, $src$$Register);
5722 %}
5723 ins_pipe(ialu_reg);
5724 %}
5725
5726 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5727 predicate(!UseCountTrailingZerosInstruction);
5728 match(Set dst (CountTrailingZerosI src));
5729 effect(KILL cr);
5730
5731 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5732 "JNZ done\n\t"
5733 "MOV $dst, 32\n"
5734 "done:" %}
5735 ins_encode %{
5736 Register Rdst = $dst$$Register;
5737 Label done;
5738 __ bsfl(Rdst, $src$$Register);
5739 __ jccb(Assembler::notZero, done);
5740 __ movl(Rdst, BitsPerInt);
5741 __ bind(done);
5742 %}
5743 ins_pipe(ialu_reg);
5744 %}
5745
5746 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5747 predicate(UseCountTrailingZerosInstruction);
5748 match(Set dst (CountTrailingZerosL src));
5749 effect(TEMP dst, KILL cr);
5750
5751 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5752 "JNC done\n\t"
5753 "TZCNT $dst, $src.hi\n\t"
5754 "ADD $dst, 32\n"
5755 "done:" %}
5756 ins_encode %{
5757 Register Rdst = $dst$$Register;
5758 Register Rsrc = $src$$Register;
5759 Label done;
5760 __ tzcntl(Rdst, Rsrc);
5761 __ jccb(Assembler::carryClear, done);
5762 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5763 __ addl(Rdst, BitsPerInt);
5764 __ bind(done);
5765 %}
5766 ins_pipe(ialu_reg);
5767 %}
5768
5769 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5770 predicate(!UseCountTrailingZerosInstruction);
5771 match(Set dst (CountTrailingZerosL src));
5772 effect(TEMP dst, KILL cr);
5773
5774 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5775 "JNZ done\n\t"
5776 "BSF $dst, $src.hi\n\t"
5777 "JNZ msw_not_zero\n\t"
5778 "MOV $dst, 32\n"
5779 "msw_not_zero:\n\t"
5780 "ADD $dst, 32\n"
5781 "done:" %}
5782 ins_encode %{
5783 Register Rdst = $dst$$Register;
5784 Register Rsrc = $src$$Register;
5785 Label msw_not_zero;
5786 Label done;
5787 __ bsfl(Rdst, Rsrc);
5788 __ jccb(Assembler::notZero, done);
5789 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5790 __ jccb(Assembler::notZero, msw_not_zero);
8722 ins_cost(150);
8723 format %{ "AND $dst,$src" %}
8724 opcode(0x21); /* Opcode 21 /r */
8725 ins_encode( OpcP, RegMem( src, dst ) );
8726 ins_pipe( ialu_mem_reg );
8727 %}
8728
8729 // And Memory with Immediate
8730 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8731 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8732 effect(KILL cr);
8733
8734 ins_cost(125);
8735 format %{ "AND $dst,$src" %}
8736 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8737 // ins_encode( MemImm( dst, src) );
8738 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8739 ins_pipe( ialu_mem_imm );
8740 %}
8741
8742 // BMI1 instructions
8743 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
8744 match(Set dst (AndI (XorI src1 minus_1) src2));
8745 predicate(UseBMI1Instructions);
8746 effect(KILL cr);
8747
8748 format %{ "ANDNL $dst, $src1, $src2" %}
8749
8750 ins_encode %{
8751 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8752 %}
8753 ins_pipe(ialu_reg);
8754 %}
8755
8756 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8757 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8758 predicate(UseBMI1Instructions);
8759 effect(KILL cr);
8760
8761 ins_cost(125);
8762 format %{ "ANDNL $dst, $src1, $src2" %}
8763
8764 ins_encode %{
8765 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8766 %}
8767 ins_pipe(ialu_reg_mem);
8768 %}
8769
8770 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8771 match(Set dst (AndI (SubI imm_zero src) src));
8772 predicate(UseBMI1Instructions);
8773 effect(KILL cr);
8774
8775 format %{ "BLSIL $dst, $src" %}
8776
8777 ins_encode %{
8778 __ blsil($dst$$Register, $src$$Register);
8779 %}
8780 ins_pipe(ialu_reg);
8781 %}
8782
8783 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8784 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8785 predicate(UseBMI1Instructions);
8786 effect(KILL cr);
8787
8788 ins_cost(125);
8789 format %{ "BLSIL $dst, $src" %}
8790
8791 ins_encode %{
8792 __ blsil($dst$$Register, $src$$Address);
8793 %}
8794 ins_pipe(ialu_reg_mem);
8795 %}
8796
8797 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8798 %{
8799 match(Set dst (XorI (AddI src minus_1) src));
8800 predicate(UseBMI1Instructions);
8801 effect(KILL cr);
8802
8803 format %{ "BLSMSKL $dst, $src" %}
8804
8805 ins_encode %{
8806 __ blsmskl($dst$$Register, $src$$Register);
8807 %}
8808
8809 ins_pipe(ialu_reg);
8810 %}
8811
8812 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8813 %{
8814 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
8815 predicate(UseBMI1Instructions);
8816 effect(KILL cr);
8817
8818 ins_cost(125);
8819 format %{ "BLSMSKL $dst, $src" %}
8820
8821 ins_encode %{
8822 __ blsmskl($dst$$Register, $src$$Address);
8823 %}
8824
8825 ins_pipe(ialu_reg_mem);
8826 %}
8827
8828 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8829 %{
8830 match(Set dst (AndI (AddI src minus_1) src) );
8831 predicate(UseBMI1Instructions);
8832 effect(KILL cr);
8833
8834 format %{ "BLSRL $dst, $src" %}
8835
8836 ins_encode %{
8837 __ blsrl($dst$$Register, $src$$Register);
8838 %}
8839
8840 ins_pipe(ialu_reg);
8841 %}
8842
8843 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8844 %{
8845 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8846 predicate(UseBMI1Instructions);
8847 effect(KILL cr);
8848
8849 ins_cost(125);
8850 format %{ "BLSRL $dst, $src" %}
8851
8852 ins_encode %{
8853 __ blsrl($dst$$Register, $src$$Address);
8854 %}
8855
8856 ins_pipe(ialu_reg_mem);
8857 %}
8858
8859 // Or Instructions
8860 // Or Register with Register
8861 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8862 match(Set dst (OrI dst src));
8863 effect(KILL cr);
8864
8865 size(2);
8866 format %{ "OR $dst,$src" %}
8867 opcode(0x0B);
8868 ins_encode( OpcP, RegReg( dst, src) );
8869 ins_pipe( ialu_reg_reg );
8870 %}
8871
8872 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8873 match(Set dst (OrI dst (CastP2X src)));
8874 effect(KILL cr);
8875
8876 size(2);
8877 format %{ "OR $dst,$src" %}
8878 opcode(0x0B);
9376 effect(KILL cr);
9377 format %{ "AND $dst.lo,$src.lo\n\t"
9378 "AND $dst.hi,$src.hi" %}
9379 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9380 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9381 ins_pipe( ialu_reg_long );
9382 %}
9383
9384 // And Long Register with Memory
9385 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9386 match(Set dst (AndL dst (LoadL mem)));
9387 effect(KILL cr);
9388 ins_cost(125);
9389 format %{ "AND $dst.lo,$mem\n\t"
9390 "AND $dst.hi,$mem+4" %}
9391 opcode(0x23, 0x23);
9392 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9393 ins_pipe( ialu_reg_long_mem );
9394 %}
9395
9396 // BMI1 instructions
9397 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
9398 match(Set dst (AndL (XorL src1 minus_1) src2));
9399 predicate(UseBMI1Instructions);
9400 effect(KILL cr, TEMP dst);
9401
9402 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
9403 "ANDNL $dst.hi, $src1.hi, $src2.hi"
9404 %}
9405
9406 ins_encode %{
9407 Register Rdst = $dst$$Register;
9408 Register Rsrc1 = $src1$$Register;
9409 Register Rsrc2 = $src2$$Register;
9410 __ andnl(Rdst, Rsrc1, Rsrc2);
9411 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
9412 %}
9413 ins_pipe(ialu_reg_reg_long);
9414 %}
9415
9416 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
9417 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
9418 predicate(UseBMI1Instructions);
9419 effect(KILL cr, TEMP dst);
9420
9421 ins_cost(125);
9422 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
9423 "ANDNL $dst.hi, $src1.hi, $src2+4"
9424 %}
9425
9426 ins_encode %{
9427 Register Rdst = $dst$$Register;
9428 Register Rsrc1 = $src1$$Register;
9429 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
9430
9431 __ andnl(Rdst, Rsrc1, $src2$$Address);
9432 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
9433 %}
9434 ins_pipe(ialu_reg_mem);
9435 %}
9436
9437 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
9438 match(Set dst (AndL (SubL imm_zero src) src));
9439 predicate(UseBMI1Instructions);
9440 effect(KILL cr, TEMP dst);
9441
9442 format %{ "MOVL $dst.hi, 0\n\t"
9443 "BLSIL $dst.lo, $src.lo\n\t"
9444 "JNZ done\n\t"
9445 "BLSIL $dst.hi, $src.hi\n"
9446 "done:"
9447 %}
9448
9449 ins_encode %{
9450 Label done;
9451 Register Rdst = $dst$$Register;
9452 Register Rsrc = $src$$Register;
9453 __ movl(HIGH_FROM_LOW(Rdst), 0);
9454 __ blsil(Rdst, Rsrc);
9455 __ jccb(Assembler::notZero, done);
9456 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9457 __ bind(done);
9458 %}
9459 ins_pipe(ialu_reg);
9460 %}
9461
9462 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
9463 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9464 predicate(UseBMI1Instructions);
9465 effect(KILL cr, TEMP dst);
9466
9467 ins_cost(125);
9468 format %{ "MOVL $dst.hi, 0\n\t"
9469 "BLSIL $dst.lo, $src\n\t"
9470 "JNZ done\n\t"
9471 "BLSIL $dst.hi, $src+4\n"
9472 "done:"
9473 %}
9474
9475 ins_encode %{
9476 Label done;
9477 Register Rdst = $dst$$Register;
9478 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9479
9480 __ movl(HIGH_FROM_LOW(Rdst), 0);
9481 __ blsil(Rdst, $src$$Address);
9482 __ jccb(Assembler::notZero, done);
9483 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
9484 __ bind(done);
9485 %}
9486 ins_pipe(ialu_reg_mem);
9487 %}
9488
9489 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
9490 %{
9491 match(Set dst (XorL (AddL src minus_1) src));
9492 predicate(UseBMI1Instructions);
9493 effect(KILL cr, TEMP dst);
9494
9495 format %{ "MOVL $dst.hi, 0\n\t"
9496 "BLSMSKL $dst.lo, $src.lo\n\t"
9497 "JNC done\n\t"
9498 "BLSMSKL $dst.hi, $src.hi\n"
9499 "done:"
9500 %}
9501
9502 ins_encode %{
9503 Label done;
9504 Register Rdst = $dst$$Register;
9505 Register Rsrc = $src$$Register;
9506 __ movl(HIGH_FROM_LOW(Rdst), 0);
9507 __ blsmskl(Rdst, Rsrc);
9508 __ jccb(Assembler::carryClear, done);
9509 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9510 __ bind(done);
9511 %}
9512
9513 ins_pipe(ialu_reg);
9514 %}
9515
9516 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
9517 %{
9518 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
9519 predicate(UseBMI1Instructions);
9520 effect(KILL cr, TEMP dst);
9521
9522 ins_cost(125);
9523 format %{ "MOVL $dst.hi, 0\n\t"
9524 "BLSMSKL $dst.lo, $src\n\t"
9525 "JNC done\n\t"
9526 "BLSMSKL $dst.hi, $src+4\n"
9527 "done:"
9528 %}
9529
9530 ins_encode %{
9531 Label done;
9532 Register Rdst = $dst$$Register;
9533 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9534
9535 __ movl(HIGH_FROM_LOW(Rdst), 0);
9536 __ blsmskl(Rdst, $src$$Address);
9537 __ jccb(Assembler::carryClear, done);
9538 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
9539 __ bind(done);
9540 %}
9541
9542 ins_pipe(ialu_reg_mem);
9543 %}
9544
9545 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
9546 %{
9547 match(Set dst (AndL (AddL src minus_1) src) );
9548 predicate(UseBMI1Instructions);
9549 effect(KILL cr, TEMP dst);
9550
9551 format %{ "MOVL $dst.hi, $src.hi\n\t"
9552 "BLSRL $dst.lo, $src.lo\n\t"
9553 "JNC done\n\t"
9554 "BLSRL $dst.hi, $src.hi\n"
9555 "done:"
9556 %}
9557
9558 ins_encode %{
9559 Label done;
9560 Register Rdst = $dst$$Register;
9561 Register Rsrc = $src$$Register;
9562 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9563 __ blsrl(Rdst, Rsrc);
9564 __ jccb(Assembler::carryClear, done);
9565 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
9566 __ bind(done);
9567 %}
9568
9569 ins_pipe(ialu_reg);
9570 %}
9571
9572 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
9573 %{
9574 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
9575 predicate(UseBMI1Instructions);
9576 effect(KILL cr, TEMP dst);
9577
9578 ins_cost(125);
9579 format %{ "MOVL $dst.hi, $src+4\n\t"
9580 "BLSRL $dst.lo, $src\n\t"
9581 "JNC done\n\t"
9582 "BLSRL $dst.hi, $src+4\n"
9583 "done:"
9584 %}
9585
9586 ins_encode %{
9587 Label done;
9588 Register Rdst = $dst$$Register;
9589 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9590 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
9591 __ blsrl(Rdst, $src$$Address);
9592 __ jccb(Assembler::carryClear, done);
9593 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
9594 __ bind(done);
9595 %}
9596
9597 ins_pipe(ialu_reg_mem);
9598 %}
9599
9600 // Or Long Register with Register
9601 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9602 match(Set dst (OrL dst src));
9603 effect(KILL cr);
9604 format %{ "OR $dst.lo,$src.lo\n\t"
9605 "OR $dst.hi,$src.hi" %}
9606 opcode(0x0B,0x0B);
9607 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9608 ins_pipe( ialu_reg_reg_long );
9609 %}
9610
9611 // Or Long Register with Immediate
9612 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9613 match(Set dst (OrL dst src));
9614 effect(KILL cr);
9615 format %{ "OR $dst.lo,$src.lo\n\t"
9616 "OR $dst.hi,$src.hi" %}
9617 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9618 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9619 ins_pipe( ialu_reg_long );
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