1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
94
95 // Implementation of Address
96
97 #ifdef _LP64
98
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
105
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
134
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
143
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
152
153 #endif // _LP64
154
155
156
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
176
177 // Implementation of Assembler
178
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
182
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
189
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
199
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
208
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
216
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
226
227
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
242
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
252
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
267
268
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
274
275
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
281
282 // Encode the registers as needed in the fields they are used in
283
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
287
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
366
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
370
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
382
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
393
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
399
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
402
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
406
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
413
414 // If "which" is end_pc_operand, find the end of the instruction.
415
416 address ip = inst;
417 bool is_64bit = false;
418
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
421
422 again_after_prefix:
423 switch (0xFF & *ip++) {
424
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
431
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
442
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
454
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
466
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
475
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
482
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
519
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
530 #endif // _LP64
531 return ip;
532
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
538
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
547
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
553
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
567
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
583
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
589
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
594
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
603
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
610
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
616
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
626
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
641
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
649
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
665
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
668
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
688
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
700
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
706
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
710
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
737
738 default:
739 ShouldNotReachHere();
740
741 #undef REP8
742 #undef REP16
743 }
744
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
753
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
765
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
773
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
780
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
787
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
796
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
801
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
805
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
813
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
818
819
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
825
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
843
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
850
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
857
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
862
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
868
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
874
875
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
882
883
884 // Now the Assembler instructions (identical for 32/64 bits)
885
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
891
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
898
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
903
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
910
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
915
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
921
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
928
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
933
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
940
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
945
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
954
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
964
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
985
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
990
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1013
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1020
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1028
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1035
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1043
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1050
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1058
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1065
1066
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1116 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1117 emit_int8(0x0F);
1118 emit_int8((unsigned char)0xBD);
1119 emit_int8((unsigned char)(0xC0 | encode));
1120 }
1121
1122 void Assembler::bswapl(Register reg) { // bswap
1123 int encode = prefix_and_encode(reg->encoding());
1124 emit_int8(0x0F);
1125 emit_int8((unsigned char)(0xC8 | encode));
1126 }
1127
1128 void Assembler::blsil(Register dst, Register src) {
1129 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1130 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1131 emit_int8((unsigned char)0xF3);
1132 emit_int8((unsigned char)(0xC0 | encode));
1133 }
1134
1135 void Assembler::blsil(Register dst, Address src) {
1136 InstructionMark im(this);
1137 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1138 vex_prefix_0F38(rbx, dst, src);
1139 emit_int8((unsigned char)0xF3);
1140 emit_operand(rbx, src);
1141 }
1142
1143 void Assembler::blsmskl(Register dst, Register src) {
1144 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1145 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1146 emit_int8((unsigned char)0xF3);
1147 emit_int8((unsigned char)(0xC0 | encode));
1148 }
1149
1150 void Assembler::blsmskl(Register dst, Address src) {
1151 InstructionMark im(this);
1152 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1153 vex_prefix_0F38(rdx, dst, src);
1154 emit_int8((unsigned char)0xF3);
1155 emit_operand(rdx, src);
1156 }
1157
1158 void Assembler::blsrl(Register dst, Register src) {
1159 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1160 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1161 emit_int8((unsigned char)0xF3);
1162 emit_int8((unsigned char)(0xC0 | encode));
1163 }
1164
1165 void Assembler::blsrl(Register dst, Address src) {
1166 InstructionMark im(this);
1167 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1168 vex_prefix_0F38(rcx, dst, src);
1169 emit_int8((unsigned char)0xF3);
1170 emit_operand(rcx, src);
1171 }
1172
1173 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1174 // suspect disp32 is always good
1175 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1176
1177 if (L.is_bound()) {
1178 const int long_size = 5;
1179 int offs = (int)( target(L) - pc() );
1180 assert(offs <= 0, "assembler error");
1181 InstructionMark im(this);
1182 // 1110 1000 #32-bit disp
1183 emit_int8((unsigned char)0xE8);
1184 emit_data(offs - long_size, rtype, operand);
1185 } else {
1186 InstructionMark im(this);
1187 // 1110 1000 #32-bit disp
1188 L.add_patch_at(code(), locator());
1189
1190 emit_int8((unsigned char)0xE8);
1191 emit_data(int(0), rtype, operand);
1192 }
1193 }
1194
1195 void Assembler::call(Register dst) {
1196 int encode = prefix_and_encode(dst->encoding());
1197 emit_int8((unsigned char)0xFF);
1198 emit_int8((unsigned char)(0xD0 | encode));
1199 }
1200
1201
1202 void Assembler::call(Address adr) {
1203 InstructionMark im(this);
1204 prefix(adr);
1205 emit_int8((unsigned char)0xFF);
1206 emit_operand(rdx, adr);
1207 }
1208
1209 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1210 assert(entry != NULL, "call most probably wrong");
1211 InstructionMark im(this);
1212 emit_int8((unsigned char)0xE8);
1213 intptr_t disp = entry - (pc() + sizeof(int32_t));
1214 assert(is_simm32(disp), "must be 32bit offset (call2)");
1215 // Technically, should use call32_operand, but this format is
1216 // implied by the fact that we're emitting a call instruction.
1217
1218 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1219 emit_data((int) disp, rspec, operand);
1220 }
1221
1222 void Assembler::cdql() {
1223 emit_int8((unsigned char)0x99);
1224 }
1225
1226 void Assembler::cld() {
1227 emit_int8((unsigned char)0xFC);
1228 }
1229
1230 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1231 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1232 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1233 emit_int8(0x0F);
1234 emit_int8(0x40 | cc);
1235 emit_int8((unsigned char)(0xC0 | encode));
1236 }
1237
1238
1239 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1240 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1241 prefix(src, dst);
1242 emit_int8(0x0F);
1243 emit_int8(0x40 | cc);
1244 emit_operand(dst, src);
1245 }
1246
1247 void Assembler::cmpb(Address dst, int imm8) {
1248 InstructionMark im(this);
1249 prefix(dst);
1250 emit_int8((unsigned char)0x80);
1251 emit_operand(rdi, dst, 1);
1252 emit_int8(imm8);
1253 }
1254
1255 void Assembler::cmpl(Address dst, int32_t imm32) {
1256 InstructionMark im(this);
1257 prefix(dst);
1258 emit_int8((unsigned char)0x81);
1259 emit_operand(rdi, dst, 4);
1260 emit_int32(imm32);
1261 }
1262
1263 void Assembler::cmpl(Register dst, int32_t imm32) {
1264 prefix(dst);
1265 emit_arith(0x81, 0xF8, dst, imm32);
1266 }
1267
1268 void Assembler::cmpl(Register dst, Register src) {
1269 (void) prefix_and_encode(dst->encoding(), src->encoding());
1270 emit_arith(0x3B, 0xC0, dst, src);
1271 }
1272
1273
1274 void Assembler::cmpl(Register dst, Address src) {
1275 InstructionMark im(this);
1276 prefix(src, dst);
1277 emit_int8((unsigned char)0x3B);
1278 emit_operand(dst, src);
1279 }
1280
1281 void Assembler::cmpw(Address dst, int imm16) {
1282 InstructionMark im(this);
1283 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1284 emit_int8(0x66);
1285 emit_int8((unsigned char)0x81);
1286 emit_operand(rdi, dst, 2);
1287 emit_int16(imm16);
1288 }
1289
1290 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1291 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1292 // The ZF is set if the compared values were equal, and cleared otherwise.
1293 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1294 InstructionMark im(this);
1295 prefix(adr, reg);
1296 emit_int8(0x0F);
1297 emit_int8((unsigned char)0xB1);
1298 emit_operand(reg, adr);
1299 }
1300
1301 void Assembler::comisd(XMMRegister dst, Address src) {
1302 // NOTE: dbx seems to decode this as comiss even though the
1303 // 0x66 is there. Strangly ucomisd comes out correct
1304 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1305 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1306 }
1307
1308 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1309 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1310 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1311 }
1312
1313 void Assembler::comiss(XMMRegister dst, Address src) {
1314 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1315 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1316 }
1317
1318 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1319 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1320 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1321 }
1322
1323 void Assembler::cpuid() {
1324 emit_int8(0x0F);
1325 emit_int8((unsigned char)0xA2);
1326 }
1327
1328 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1330 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1331 }
1332
1333 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1335 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1336 }
1337
1338 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1340 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1341 }
1342
1343 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1345 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1346 }
1347
1348 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1351 emit_int8(0x2A);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1356 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1357 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1358 }
1359
1360 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1361 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1362 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1363 emit_int8(0x2A);
1364 emit_int8((unsigned char)(0xC0 | encode));
1365 }
1366
1367 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1368 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1369 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1370 }
1371
1372 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1374 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1375 }
1376
1377 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1379 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1380 }
1381
1382
1383 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1385 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1386 emit_int8(0x2C);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1391 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1392 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1393 emit_int8(0x2C);
1394 emit_int8((unsigned char)(0xC0 | encode));
1395 }
1396
1397 void Assembler::decl(Address dst) {
1398 // Don't use it directly. Use MacroAssembler::decrement() instead.
1399 InstructionMark im(this);
1400 prefix(dst);
1401 emit_int8((unsigned char)0xFF);
1402 emit_operand(rcx, dst);
1403 }
1404
1405 void Assembler::divsd(XMMRegister dst, Address src) {
1406 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1407 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1408 }
1409
1410 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1412 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1413 }
1414
1415 void Assembler::divss(XMMRegister dst, Address src) {
1416 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1417 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1418 }
1419
1420 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1421 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1422 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1423 }
1424
1425 void Assembler::emms() {
1426 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1427 emit_int8(0x0F);
1428 emit_int8(0x77);
1429 }
1430
1431 void Assembler::hlt() {
1432 emit_int8((unsigned char)0xF4);
1433 }
1434
1435 void Assembler::idivl(Register src) {
1436 int encode = prefix_and_encode(src->encoding());
1437 emit_int8((unsigned char)0xF7);
1438 emit_int8((unsigned char)(0xF8 | encode));
1439 }
1440
1441 void Assembler::divl(Register src) { // Unsigned
1442 int encode = prefix_and_encode(src->encoding());
1443 emit_int8((unsigned char)0xF7);
1444 emit_int8((unsigned char)(0xF0 | encode));
1445 }
1446
1447 void Assembler::imull(Register dst, Register src) {
1448 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1449 emit_int8(0x0F);
1450 emit_int8((unsigned char)0xAF);
1451 emit_int8((unsigned char)(0xC0 | encode));
1452 }
1453
1454
1455 void Assembler::imull(Register dst, Register src, int value) {
1456 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1457 if (is8bit(value)) {
1458 emit_int8(0x6B);
1459 emit_int8((unsigned char)(0xC0 | encode));
1460 emit_int8(value & 0xFF);
1461 } else {
1462 emit_int8(0x69);
1463 emit_int8((unsigned char)(0xC0 | encode));
1464 emit_int32(value);
1465 }
1466 }
1467
1468 void Assembler::imull(Register dst, Address src) {
1469 InstructionMark im(this);
1470 prefix(src, dst);
1471 emit_int8(0x0F);
1472 emit_int8((unsigned char) 0xAF);
1473 emit_operand(dst, src);
1474 }
1475
1476
1477 void Assembler::incl(Address dst) {
1478 // Don't use it directly. Use MacroAssembler::increment() instead.
1479 InstructionMark im(this);
1480 prefix(dst);
1481 emit_int8((unsigned char)0xFF);
1482 emit_operand(rax, dst);
1483 }
1484
1485 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1486 InstructionMark im(this);
1487 assert((0 <= cc) && (cc < 16), "illegal cc");
1488 if (L.is_bound()) {
1489 address dst = target(L);
1490 assert(dst != NULL, "jcc most probably wrong");
1491
1492 const int short_size = 2;
1493 const int long_size = 6;
1494 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1495 if (maybe_short && is8bit(offs - short_size)) {
1496 // 0111 tttn #8-bit disp
1497 emit_int8(0x70 | cc);
1498 emit_int8((offs - short_size) & 0xFF);
1499 } else {
1500 // 0000 1111 1000 tttn #32-bit disp
1501 assert(is_simm32(offs - long_size),
1502 "must be 32bit offset (call4)");
1503 emit_int8(0x0F);
1504 emit_int8((unsigned char)(0x80 | cc));
1505 emit_int32(offs - long_size);
1506 }
1507 } else {
1508 // Note: could eliminate cond. jumps to this jump if condition
1509 // is the same however, seems to be rather unlikely case.
1510 // Note: use jccb() if label to be bound is very close to get
1511 // an 8-bit displacement
1512 L.add_patch_at(code(), locator());
1513 emit_int8(0x0F);
1514 emit_int8((unsigned char)(0x80 | cc));
1515 emit_int32(0);
1516 }
1517 }
1518
1519 void Assembler::jccb(Condition cc, Label& L) {
1520 if (L.is_bound()) {
1521 const int short_size = 2;
1522 address entry = target(L);
1523 #ifdef ASSERT
1524 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1525 intptr_t delta = short_branch_delta();
1526 if (delta != 0) {
1527 dist += (dist < 0 ? (-delta) :delta);
1528 }
1529 assert(is8bit(dist), "Dispacement too large for a short jmp");
1530 #endif
1531 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1532 // 0111 tttn #8-bit disp
1533 emit_int8(0x70 | cc);
1534 emit_int8((offs - short_size) & 0xFF);
1535 } else {
1536 InstructionMark im(this);
1537 L.add_patch_at(code(), locator());
1538 emit_int8(0x70 | cc);
1539 emit_int8(0);
1540 }
1541 }
1542
1543 void Assembler::jmp(Address adr) {
1544 InstructionMark im(this);
1545 prefix(adr);
1546 emit_int8((unsigned char)0xFF);
1547 emit_operand(rsp, adr);
1548 }
1549
1550 void Assembler::jmp(Label& L, bool maybe_short) {
1551 if (L.is_bound()) {
1552 address entry = target(L);
1553 assert(entry != NULL, "jmp most probably wrong");
1554 InstructionMark im(this);
1555 const int short_size = 2;
1556 const int long_size = 5;
1557 intptr_t offs = entry - pc();
1558 if (maybe_short && is8bit(offs - short_size)) {
1559 emit_int8((unsigned char)0xEB);
1560 emit_int8((offs - short_size) & 0xFF);
1561 } else {
1562 emit_int8((unsigned char)0xE9);
1563 emit_int32(offs - long_size);
1564 }
1565 } else {
1566 // By default, forward jumps are always 32-bit displacements, since
1567 // we can't yet know where the label will be bound. If you're sure that
1568 // the forward jump will not run beyond 256 bytes, use jmpb to
1569 // force an 8-bit displacement.
1570 InstructionMark im(this);
1571 L.add_patch_at(code(), locator());
1572 emit_int8((unsigned char)0xE9);
1573 emit_int32(0);
1574 }
1575 }
1576
1577 void Assembler::jmp(Register entry) {
1578 int encode = prefix_and_encode(entry->encoding());
1579 emit_int8((unsigned char)0xFF);
1580 emit_int8((unsigned char)(0xE0 | encode));
1581 }
1582
1583 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1584 InstructionMark im(this);
1585 emit_int8((unsigned char)0xE9);
1586 assert(dest != NULL, "must have a target");
1587 intptr_t disp = dest - (pc() + sizeof(int32_t));
1588 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1589 emit_data(disp, rspec.reloc(), call32_operand);
1590 }
1591
1592 void Assembler::jmpb(Label& L) {
1593 if (L.is_bound()) {
1594 const int short_size = 2;
1595 address entry = target(L);
1596 assert(entry != NULL, "jmp most probably wrong");
1597 #ifdef ASSERT
1598 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1599 intptr_t delta = short_branch_delta();
1600 if (delta != 0) {
1601 dist += (dist < 0 ? (-delta) :delta);
1602 }
1603 assert(is8bit(dist), "Dispacement too large for a short jmp");
1604 #endif
1605 intptr_t offs = entry - pc();
1606 emit_int8((unsigned char)0xEB);
1607 emit_int8((offs - short_size) & 0xFF);
1608 } else {
1609 InstructionMark im(this);
1610 L.add_patch_at(code(), locator());
1611 emit_int8((unsigned char)0xEB);
1612 emit_int8(0);
1613 }
1614 }
1615
1616 void Assembler::ldmxcsr( Address src) {
1617 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1618 InstructionMark im(this);
1619 prefix(src);
1620 emit_int8(0x0F);
1621 emit_int8((unsigned char)0xAE);
1622 emit_operand(as_Register(2), src);
1623 }
1624
1625 void Assembler::leal(Register dst, Address src) {
1626 InstructionMark im(this);
1627 #ifdef _LP64
1628 emit_int8(0x67); // addr32
1629 prefix(src, dst);
1630 #endif // LP64
1631 emit_int8((unsigned char)0x8D);
1632 emit_operand(dst, src);
1633 }
1634
1635 void Assembler::lfence() {
1636 emit_int8(0x0F);
1637 emit_int8((unsigned char)0xAE);
1638 emit_int8((unsigned char)0xE8);
1639 }
1640
1641 void Assembler::lock() {
1642 emit_int8((unsigned char)0xF0);
1643 }
1644
1645 void Assembler::lzcntl(Register dst, Register src) {
1646 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1647 emit_int8((unsigned char)0xF3);
1648 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1649 emit_int8(0x0F);
1650 emit_int8((unsigned char)0xBD);
1651 emit_int8((unsigned char)(0xC0 | encode));
1652 }
1653
1654 // Emit mfence instruction
1655 void Assembler::mfence() {
1656 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1657 emit_int8(0x0F);
1658 emit_int8((unsigned char)0xAE);
1659 emit_int8((unsigned char)0xF0);
1660 }
1661
1662 void Assembler::mov(Register dst, Register src) {
1663 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1664 }
1665
1666 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1668 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1669 }
1670
1671 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1673 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1674 }
1675
1676 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1677 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1678 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1679 emit_int8(0x16);
1680 emit_int8((unsigned char)(0xC0 | encode));
1681 }
1682
1683 void Assembler::movb(Register dst, Address src) {
1684 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1685 InstructionMark im(this);
1686 prefix(src, dst, true);
1687 emit_int8((unsigned char)0x8A);
1688 emit_operand(dst, src);
1689 }
1690
1691
1692 void Assembler::movb(Address dst, int imm8) {
1693 InstructionMark im(this);
1694 prefix(dst);
1695 emit_int8((unsigned char)0xC6);
1696 emit_operand(rax, dst, 1);
1697 emit_int8(imm8);
1698 }
1699
1700
1701 void Assembler::movb(Address dst, Register src) {
1702 assert(src->has_byte_register(), "must have byte register");
1703 InstructionMark im(this);
1704 prefix(dst, src, true);
1705 emit_int8((unsigned char)0x88);
1706 emit_operand(src, dst);
1707 }
1708
1709 void Assembler::movdl(XMMRegister dst, Register src) {
1710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1711 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1712 emit_int8(0x6E);
1713 emit_int8((unsigned char)(0xC0 | encode));
1714 }
1715
1716 void Assembler::movdl(Register dst, XMMRegister src) {
1717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1718 // swap src/dst to get correct prefix
1719 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1720 emit_int8(0x7E);
1721 emit_int8((unsigned char)(0xC0 | encode));
1722 }
1723
1724 void Assembler::movdl(XMMRegister dst, Address src) {
1725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1726 InstructionMark im(this);
1727 simd_prefix(dst, src, VEX_SIMD_66);
1728 emit_int8(0x6E);
1729 emit_operand(dst, src);
1730 }
1731
1732 void Assembler::movdl(Address dst, XMMRegister src) {
1733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1734 InstructionMark im(this);
1735 simd_prefix(dst, src, VEX_SIMD_66);
1736 emit_int8(0x7E);
1737 emit_operand(src, dst);
1738 }
1739
1740 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1742 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1743 }
1744
1745 void Assembler::movdqa(XMMRegister dst, Address src) {
1746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1747 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1748 }
1749
1750 void Assembler::movdqu(XMMRegister dst, Address src) {
1751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1752 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1753 }
1754
1755 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1757 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1758 }
1759
1760 void Assembler::movdqu(Address dst, XMMRegister src) {
1761 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1762 InstructionMark im(this);
1763 simd_prefix(dst, src, VEX_SIMD_F3);
1764 emit_int8(0x7F);
1765 emit_operand(src, dst);
1766 }
1767
1768 // Move Unaligned 256bit Vector
1769 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1770 assert(UseAVX, "");
1771 bool vector256 = true;
1772 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1773 emit_int8(0x6F);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1778 assert(UseAVX, "");
1779 InstructionMark im(this);
1780 bool vector256 = true;
1781 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1782 emit_int8(0x6F);
1783 emit_operand(dst, src);
1784 }
1785
1786 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1787 assert(UseAVX, "");
1788 InstructionMark im(this);
1789 bool vector256 = true;
1790 // swap src<->dst for encoding
1791 assert(src != xnoreg, "sanity");
1792 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1793 emit_int8(0x7F);
1794 emit_operand(src, dst);
1795 }
1796
1797 // Uses zero extension on 64bit
1798
1799 void Assembler::movl(Register dst, int32_t imm32) {
1800 int encode = prefix_and_encode(dst->encoding());
1801 emit_int8((unsigned char)(0xB8 | encode));
1802 emit_int32(imm32);
1803 }
1804
1805 void Assembler::movl(Register dst, Register src) {
1806 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1807 emit_int8((unsigned char)0x8B);
1808 emit_int8((unsigned char)(0xC0 | encode));
1809 }
1810
1811 void Assembler::movl(Register dst, Address src) {
1812 InstructionMark im(this);
1813 prefix(src, dst);
1814 emit_int8((unsigned char)0x8B);
1815 emit_operand(dst, src);
1816 }
1817
1818 void Assembler::movl(Address dst, int32_t imm32) {
1819 InstructionMark im(this);
1820 prefix(dst);
1821 emit_int8((unsigned char)0xC7);
1822 emit_operand(rax, dst, 4);
1823 emit_int32(imm32);
1824 }
1825
1826 void Assembler::movl(Address dst, Register src) {
1827 InstructionMark im(this);
1828 prefix(dst, src);
1829 emit_int8((unsigned char)0x89);
1830 emit_operand(src, dst);
1831 }
1832
1833 // New cpus require to use movsd and movss to avoid partial register stall
1834 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1835 // The selection is done in MacroAssembler::movdbl() and movflt().
1836 void Assembler::movlpd(XMMRegister dst, Address src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1839 }
1840
1841 void Assembler::movq( MMXRegister dst, Address src ) {
1842 assert( VM_Version::supports_mmx(), "" );
1843 emit_int8(0x0F);
1844 emit_int8(0x6F);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::movq( Address dst, MMXRegister src ) {
1849 assert( VM_Version::supports_mmx(), "" );
1850 emit_int8(0x0F);
1851 emit_int8(0x7F);
1852 // workaround gcc (3.2.1-7a) bug
1853 // In that version of gcc with only an emit_operand(MMX, Address)
1854 // gcc will tail jump and try and reverse the parameters completely
1855 // obliterating dst in the process. By having a version available
1856 // that doesn't need to swap the args at the tail jump the bug is
1857 // avoided.
1858 emit_operand(dst, src);
1859 }
1860
1861 void Assembler::movq(XMMRegister dst, Address src) {
1862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1863 InstructionMark im(this);
1864 simd_prefix(dst, src, VEX_SIMD_F3);
1865 emit_int8(0x7E);
1866 emit_operand(dst, src);
1867 }
1868
1869 void Assembler::movq(Address dst, XMMRegister src) {
1870 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1871 InstructionMark im(this);
1872 simd_prefix(dst, src, VEX_SIMD_66);
1873 emit_int8((unsigned char)0xD6);
1874 emit_operand(src, dst);
1875 }
1876
1877 void Assembler::movsbl(Register dst, Address src) { // movsxb
1878 InstructionMark im(this);
1879 prefix(src, dst);
1880 emit_int8(0x0F);
1881 emit_int8((unsigned char)0xBE);
1882 emit_operand(dst, src);
1883 }
1884
1885 void Assembler::movsbl(Register dst, Register src) { // movsxb
1886 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1887 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1888 emit_int8(0x0F);
1889 emit_int8((unsigned char)0xBE);
1890 emit_int8((unsigned char)(0xC0 | encode));
1891 }
1892
1893 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1894 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1895 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1896 }
1897
1898 void Assembler::movsd(XMMRegister dst, Address src) {
1899 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1900 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1901 }
1902
1903 void Assembler::movsd(Address dst, XMMRegister src) {
1904 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1905 InstructionMark im(this);
1906 simd_prefix(dst, src, VEX_SIMD_F2);
1907 emit_int8(0x11);
1908 emit_operand(src, dst);
1909 }
1910
1911 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1912 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1913 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1914 }
1915
1916 void Assembler::movss(XMMRegister dst, Address src) {
1917 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1918 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1919 }
1920
1921 void Assembler::movss(Address dst, XMMRegister src) {
1922 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1923 InstructionMark im(this);
1924 simd_prefix(dst, src, VEX_SIMD_F3);
1925 emit_int8(0x11);
1926 emit_operand(src, dst);
1927 }
1928
1929 void Assembler::movswl(Register dst, Address src) { // movsxw
1930 InstructionMark im(this);
1931 prefix(src, dst);
1932 emit_int8(0x0F);
1933 emit_int8((unsigned char)0xBF);
1934 emit_operand(dst, src);
1935 }
1936
1937 void Assembler::movswl(Register dst, Register src) { // movsxw
1938 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1939 emit_int8(0x0F);
1940 emit_int8((unsigned char)0xBF);
1941 emit_int8((unsigned char)(0xC0 | encode));
1942 }
1943
1944 void Assembler::movw(Address dst, int imm16) {
1945 InstructionMark im(this);
1946
1947 emit_int8(0x66); // switch to 16-bit mode
1948 prefix(dst);
1949 emit_int8((unsigned char)0xC7);
1950 emit_operand(rax, dst, 2);
1951 emit_int16(imm16);
1952 }
1953
1954 void Assembler::movw(Register dst, Address src) {
1955 InstructionMark im(this);
1956 emit_int8(0x66);
1957 prefix(src, dst);
1958 emit_int8((unsigned char)0x8B);
1959 emit_operand(dst, src);
1960 }
1961
1962 void Assembler::movw(Address dst, Register src) {
1963 InstructionMark im(this);
1964 emit_int8(0x66);
1965 prefix(dst, src);
1966 emit_int8((unsigned char)0x89);
1967 emit_operand(src, dst);
1968 }
1969
1970 void Assembler::movzbl(Register dst, Address src) { // movzxb
1971 InstructionMark im(this);
1972 prefix(src, dst);
1973 emit_int8(0x0F);
1974 emit_int8((unsigned char)0xB6);
1975 emit_operand(dst, src);
1976 }
1977
1978 void Assembler::movzbl(Register dst, Register src) { // movzxb
1979 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1980 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1981 emit_int8(0x0F);
1982 emit_int8((unsigned char)0xB6);
1983 emit_int8(0xC0 | encode);
1984 }
1985
1986 void Assembler::movzwl(Register dst, Address src) { // movzxw
1987 InstructionMark im(this);
1988 prefix(src, dst);
1989 emit_int8(0x0F);
1990 emit_int8((unsigned char)0xB7);
1991 emit_operand(dst, src);
1992 }
1993
1994 void Assembler::movzwl(Register dst, Register src) { // movzxw
1995 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1996 emit_int8(0x0F);
1997 emit_int8((unsigned char)0xB7);
1998 emit_int8(0xC0 | encode);
1999 }
2000
2001 void Assembler::mull(Address src) {
2002 InstructionMark im(this);
2003 prefix(src);
2004 emit_int8((unsigned char)0xF7);
2005 emit_operand(rsp, src);
2006 }
2007
2008 void Assembler::mull(Register src) {
2009 int encode = prefix_and_encode(src->encoding());
2010 emit_int8((unsigned char)0xF7);
2011 emit_int8((unsigned char)(0xE0 | encode));
2012 }
2013
2014 void Assembler::mulsd(XMMRegister dst, Address src) {
2015 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2016 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2017 }
2018
2019 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2020 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2021 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2022 }
2023
2024 void Assembler::mulss(XMMRegister dst, Address src) {
2025 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2026 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2027 }
2028
2029 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2030 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2031 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2032 }
2033
2034 void Assembler::negl(Register dst) {
2035 int encode = prefix_and_encode(dst->encoding());
2036 emit_int8((unsigned char)0xF7);
2037 emit_int8((unsigned char)(0xD8 | encode));
2038 }
2039
2040 void Assembler::nop(int i) {
2041 #ifdef ASSERT
2042 assert(i > 0, " ");
2043 // The fancy nops aren't currently recognized by debuggers making it a
2044 // pain to disassemble code while debugging. If asserts are on clearly
2045 // speed is not an issue so simply use the single byte traditional nop
2046 // to do alignment.
2047
2048 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2049 return;
2050
2051 #endif // ASSERT
2052
2053 if (UseAddressNop && VM_Version::is_intel()) {
2054 //
2055 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2056 // 1: 0x90
2057 // 2: 0x66 0x90
2058 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2059 // 4: 0x0F 0x1F 0x40 0x00
2060 // 5: 0x0F 0x1F 0x44 0x00 0x00
2061 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2062 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2063 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2064 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2065 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2066 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2067
2068 // The rest coding is Intel specific - don't use consecutive address nops
2069
2070 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2071 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2072 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2073 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2074
2075 while(i >= 15) {
2076 // For Intel don't generate consecutive addess nops (mix with regular nops)
2077 i -= 15;
2078 emit_int8(0x66); // size prefix
2079 emit_int8(0x66); // size prefix
2080 emit_int8(0x66); // size prefix
2081 addr_nop_8();
2082 emit_int8(0x66); // size prefix
2083 emit_int8(0x66); // size prefix
2084 emit_int8(0x66); // size prefix
2085 emit_int8((unsigned char)0x90);
2086 // nop
2087 }
2088 switch (i) {
2089 case 14:
2090 emit_int8(0x66); // size prefix
2091 case 13:
2092 emit_int8(0x66); // size prefix
2093 case 12:
2094 addr_nop_8();
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 emit_int8(0x66); // size prefix
2098 emit_int8((unsigned char)0x90);
2099 // nop
2100 break;
2101 case 11:
2102 emit_int8(0x66); // size prefix
2103 case 10:
2104 emit_int8(0x66); // size prefix
2105 case 9:
2106 emit_int8(0x66); // size prefix
2107 case 8:
2108 addr_nop_8();
2109 break;
2110 case 7:
2111 addr_nop_7();
2112 break;
2113 case 6:
2114 emit_int8(0x66); // size prefix
2115 case 5:
2116 addr_nop_5();
2117 break;
2118 case 4:
2119 addr_nop_4();
2120 break;
2121 case 3:
2122 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2123 emit_int8(0x66); // size prefix
2124 case 2:
2125 emit_int8(0x66); // size prefix
2126 case 1:
2127 emit_int8((unsigned char)0x90);
2128 // nop
2129 break;
2130 default:
2131 assert(i == 0, " ");
2132 }
2133 return;
2134 }
2135 if (UseAddressNop && VM_Version::is_amd()) {
2136 //
2137 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2138 // 1: 0x90
2139 // 2: 0x66 0x90
2140 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2141 // 4: 0x0F 0x1F 0x40 0x00
2142 // 5: 0x0F 0x1F 0x44 0x00 0x00
2143 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2144 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2145 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2146 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2147 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2148 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2149
2150 // The rest coding is AMD specific - use consecutive address nops
2151
2152 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2153 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2154 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2155 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2156 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2157 // Size prefixes (0x66) are added for larger sizes
2158
2159 while(i >= 22) {
2160 i -= 11;
2161 emit_int8(0x66); // size prefix
2162 emit_int8(0x66); // size prefix
2163 emit_int8(0x66); // size prefix
2164 addr_nop_8();
2165 }
2166 // Generate first nop for size between 21-12
2167 switch (i) {
2168 case 21:
2169 i -= 1;
2170 emit_int8(0x66); // size prefix
2171 case 20:
2172 case 19:
2173 i -= 1;
2174 emit_int8(0x66); // size prefix
2175 case 18:
2176 case 17:
2177 i -= 1;
2178 emit_int8(0x66); // size prefix
2179 case 16:
2180 case 15:
2181 i -= 8;
2182 addr_nop_8();
2183 break;
2184 case 14:
2185 case 13:
2186 i -= 7;
2187 addr_nop_7();
2188 break;
2189 case 12:
2190 i -= 6;
2191 emit_int8(0x66); // size prefix
2192 addr_nop_5();
2193 break;
2194 default:
2195 assert(i < 12, " ");
2196 }
2197
2198 // Generate second nop for size between 11-1
2199 switch (i) {
2200 case 11:
2201 emit_int8(0x66); // size prefix
2202 case 10:
2203 emit_int8(0x66); // size prefix
2204 case 9:
2205 emit_int8(0x66); // size prefix
2206 case 8:
2207 addr_nop_8();
2208 break;
2209 case 7:
2210 addr_nop_7();
2211 break;
2212 case 6:
2213 emit_int8(0x66); // size prefix
2214 case 5:
2215 addr_nop_5();
2216 break;
2217 case 4:
2218 addr_nop_4();
2219 break;
2220 case 3:
2221 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2222 emit_int8(0x66); // size prefix
2223 case 2:
2224 emit_int8(0x66); // size prefix
2225 case 1:
2226 emit_int8((unsigned char)0x90);
2227 // nop
2228 break;
2229 default:
2230 assert(i == 0, " ");
2231 }
2232 return;
2233 }
2234
2235 // Using nops with size prefixes "0x66 0x90".
2236 // From AMD Optimization Guide:
2237 // 1: 0x90
2238 // 2: 0x66 0x90
2239 // 3: 0x66 0x66 0x90
2240 // 4: 0x66 0x66 0x66 0x90
2241 // 5: 0x66 0x66 0x90 0x66 0x90
2242 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2243 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2244 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2245 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2246 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2247 //
2248 while(i > 12) {
2249 i -= 4;
2250 emit_int8(0x66); // size prefix
2251 emit_int8(0x66);
2252 emit_int8(0x66);
2253 emit_int8((unsigned char)0x90);
2254 // nop
2255 }
2256 // 1 - 12 nops
2257 if(i > 8) {
2258 if(i > 9) {
2259 i -= 1;
2260 emit_int8(0x66);
2261 }
2262 i -= 3;
2263 emit_int8(0x66);
2264 emit_int8(0x66);
2265 emit_int8((unsigned char)0x90);
2266 }
2267 // 1 - 8 nops
2268 if(i > 4) {
2269 if(i > 6) {
2270 i -= 1;
2271 emit_int8(0x66);
2272 }
2273 i -= 3;
2274 emit_int8(0x66);
2275 emit_int8(0x66);
2276 emit_int8((unsigned char)0x90);
2277 }
2278 switch (i) {
2279 case 4:
2280 emit_int8(0x66);
2281 case 3:
2282 emit_int8(0x66);
2283 case 2:
2284 emit_int8(0x66);
2285 case 1:
2286 emit_int8((unsigned char)0x90);
2287 break;
2288 default:
2289 assert(i == 0, " ");
2290 }
2291 }
2292
2293 void Assembler::notl(Register dst) {
2294 int encode = prefix_and_encode(dst->encoding());
2295 emit_int8((unsigned char)0xF7);
2296 emit_int8((unsigned char)(0xD0 | encode));
2297 }
2298
2299 void Assembler::orl(Address dst, int32_t imm32) {
2300 InstructionMark im(this);
2301 prefix(dst);
2302 emit_arith_operand(0x81, rcx, dst, imm32);
2303 }
2304
2305 void Assembler::orl(Register dst, int32_t imm32) {
2306 prefix(dst);
2307 emit_arith(0x81, 0xC8, dst, imm32);
2308 }
2309
2310 void Assembler::orl(Register dst, Address src) {
2311 InstructionMark im(this);
2312 prefix(src, dst);
2313 emit_int8(0x0B);
2314 emit_operand(dst, src);
2315 }
2316
2317 void Assembler::orl(Register dst, Register src) {
2318 (void) prefix_and_encode(dst->encoding(), src->encoding());
2319 emit_arith(0x0B, 0xC0, dst, src);
2320 }
2321
2322 void Assembler::packuswb(XMMRegister dst, Address src) {
2323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2324 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2325 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2326 }
2327
2328 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2330 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2331 }
2332
2333 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2334 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2335 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2336 }
2337
2338 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2339 assert(VM_Version::supports_avx2(), "");
2340 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2341 emit_int8(0x00);
2342 emit_int8(0xC0 | encode);
2343 emit_int8(imm8);
2344 }
2345
2346 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2347 assert(VM_Version::supports_sse4_2(), "");
2348 InstructionMark im(this);
2349 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2350 emit_int8(0x61);
2351 emit_operand(dst, src);
2352 emit_int8(imm8);
2353 }
2354
2355 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2356 assert(VM_Version::supports_sse4_2(), "");
2357 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2358 emit_int8(0x61);
2359 emit_int8((unsigned char)(0xC0 | encode));
2360 emit_int8(imm8);
2361 }
2362
2363 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2364 assert(VM_Version::supports_sse4_1(), "");
2365 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2366 emit_int8(0x16);
2367 emit_int8((unsigned char)(0xC0 | encode));
2368 emit_int8(imm8);
2369 }
2370
2371 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2372 assert(VM_Version::supports_sse4_1(), "");
2373 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2374 emit_int8(0x16);
2375 emit_int8((unsigned char)(0xC0 | encode));
2376 emit_int8(imm8);
2377 }
2378
2379 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2380 assert(VM_Version::supports_sse4_1(), "");
2381 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2382 emit_int8(0x22);
2383 emit_int8((unsigned char)(0xC0 | encode));
2384 emit_int8(imm8);
2385 }
2386
2387 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2388 assert(VM_Version::supports_sse4_1(), "");
2389 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2390 emit_int8(0x22);
2391 emit_int8((unsigned char)(0xC0 | encode));
2392 emit_int8(imm8);
2393 }
2394
2395 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2396 assert(VM_Version::supports_sse4_1(), "");
2397 InstructionMark im(this);
2398 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2399 emit_int8(0x30);
2400 emit_operand(dst, src);
2401 }
2402
2403 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2404 assert(VM_Version::supports_sse4_1(), "");
2405 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2406 emit_int8(0x30);
2407 emit_int8((unsigned char)(0xC0 | encode));
2408 }
2409
2410 // generic
2411 void Assembler::pop(Register dst) {
2412 int encode = prefix_and_encode(dst->encoding());
2413 emit_int8(0x58 | encode);
2414 }
2415
2416 void Assembler::popcntl(Register dst, Address src) {
2417 assert(VM_Version::supports_popcnt(), "must support");
2418 InstructionMark im(this);
2419 emit_int8((unsigned char)0xF3);
2420 prefix(src, dst);
2421 emit_int8(0x0F);
2422 emit_int8((unsigned char)0xB8);
2423 emit_operand(dst, src);
2424 }
2425
2426 void Assembler::popcntl(Register dst, Register src) {
2427 assert(VM_Version::supports_popcnt(), "must support");
2428 emit_int8((unsigned char)0xF3);
2429 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2430 emit_int8(0x0F);
2431 emit_int8((unsigned char)0xB8);
2432 emit_int8((unsigned char)(0xC0 | encode));
2433 }
2434
2435 void Assembler::popf() {
2436 emit_int8((unsigned char)0x9D);
2437 }
2438
2439 #ifndef _LP64 // no 32bit push/pop on amd64
2440 void Assembler::popl(Address dst) {
2441 // NOTE: this will adjust stack by 8byte on 64bits
2442 InstructionMark im(this);
2443 prefix(dst);
2444 emit_int8((unsigned char)0x8F);
2445 emit_operand(rax, dst);
2446 }
2447 #endif
2448
2449 void Assembler::prefetch_prefix(Address src) {
2450 prefix(src);
2451 emit_int8(0x0F);
2452 }
2453
2454 void Assembler::prefetchnta(Address src) {
2455 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2456 InstructionMark im(this);
2457 prefetch_prefix(src);
2458 emit_int8(0x18);
2459 emit_operand(rax, src); // 0, src
2460 }
2461
2462 void Assembler::prefetchr(Address src) {
2463 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2464 InstructionMark im(this);
2465 prefetch_prefix(src);
2466 emit_int8(0x0D);
2467 emit_operand(rax, src); // 0, src
2468 }
2469
2470 void Assembler::prefetcht0(Address src) {
2471 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2472 InstructionMark im(this);
2473 prefetch_prefix(src);
2474 emit_int8(0x18);
2475 emit_operand(rcx, src); // 1, src
2476 }
2477
2478 void Assembler::prefetcht1(Address src) {
2479 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2480 InstructionMark im(this);
2481 prefetch_prefix(src);
2482 emit_int8(0x18);
2483 emit_operand(rdx, src); // 2, src
2484 }
2485
2486 void Assembler::prefetcht2(Address src) {
2487 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2488 InstructionMark im(this);
2489 prefetch_prefix(src);
2490 emit_int8(0x18);
2491 emit_operand(rbx, src); // 3, src
2492 }
2493
2494 void Assembler::prefetchw(Address src) {
2495 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2496 InstructionMark im(this);
2497 prefetch_prefix(src);
2498 emit_int8(0x0D);
2499 emit_operand(rcx, src); // 1, src
2500 }
2501
2502 void Assembler::prefix(Prefix p) {
2503 emit_int8(p);
2504 }
2505
2506 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2507 assert(VM_Version::supports_ssse3(), "");
2508 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2509 emit_int8(0x00);
2510 emit_int8((unsigned char)(0xC0 | encode));
2511 }
2512
2513 void Assembler::pshufb(XMMRegister dst, Address src) {
2514 assert(VM_Version::supports_ssse3(), "");
2515 InstructionMark im(this);
2516 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2517 emit_int8(0x00);
2518 emit_operand(dst, src);
2519 }
2520
2521 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2522 assert(isByte(mode), "invalid value");
2523 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2524 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2525 emit_int8(mode & 0xFF);
2526
2527 }
2528
2529 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2530 assert(isByte(mode), "invalid value");
2531 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2532 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2533 InstructionMark im(this);
2534 simd_prefix(dst, src, VEX_SIMD_66);
2535 emit_int8(0x70);
2536 emit_operand(dst, src);
2537 emit_int8(mode & 0xFF);
2538 }
2539
2540 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2541 assert(isByte(mode), "invalid value");
2542 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2543 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2544 emit_int8(mode & 0xFF);
2545 }
2546
2547 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2548 assert(isByte(mode), "invalid value");
2549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2550 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2551 InstructionMark im(this);
2552 simd_prefix(dst, src, VEX_SIMD_F2);
2553 emit_int8(0x70);
2554 emit_operand(dst, src);
2555 emit_int8(mode & 0xFF);
2556 }
2557
2558 void Assembler::psrldq(XMMRegister dst, int shift) {
2559 // Shift 128 bit value in xmm register by number of bytes.
2560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2561 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2562 emit_int8(0x73);
2563 emit_int8((unsigned char)(0xC0 | encode));
2564 emit_int8(shift);
2565 }
2566
2567 void Assembler::ptest(XMMRegister dst, Address src) {
2568 assert(VM_Version::supports_sse4_1(), "");
2569 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2570 InstructionMark im(this);
2571 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2572 emit_int8(0x17);
2573 emit_operand(dst, src);
2574 }
2575
2576 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2577 assert(VM_Version::supports_sse4_1(), "");
2578 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2579 emit_int8(0x17);
2580 emit_int8((unsigned char)(0xC0 | encode));
2581 }
2582
2583 void Assembler::vptest(XMMRegister dst, Address src) {
2584 assert(VM_Version::supports_avx(), "");
2585 InstructionMark im(this);
2586 bool vector256 = true;
2587 assert(dst != xnoreg, "sanity");
2588 int dst_enc = dst->encoding();
2589 // swap src<->dst for encoding
2590 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2591 emit_int8(0x17);
2592 emit_operand(dst, src);
2593 }
2594
2595 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2596 assert(VM_Version::supports_avx(), "");
2597 bool vector256 = true;
2598 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2599 emit_int8(0x17);
2600 emit_int8((unsigned char)(0xC0 | encode));
2601 }
2602
2603 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2605 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2606 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2607 }
2608
2609 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2610 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2611 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2612 }
2613
2614 void Assembler::punpckldq(XMMRegister dst, Address src) {
2615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2616 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2617 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2618 }
2619
2620 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2622 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2623 }
2624
2625 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2627 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2628 }
2629
2630 void Assembler::push(int32_t imm32) {
2631 // in 64bits we push 64bits onto the stack but only
2632 // take a 32bit immediate
2633 emit_int8(0x68);
2634 emit_int32(imm32);
2635 }
2636
2637 void Assembler::push(Register src) {
2638 int encode = prefix_and_encode(src->encoding());
2639
2640 emit_int8(0x50 | encode);
2641 }
2642
2643 void Assembler::pushf() {
2644 emit_int8((unsigned char)0x9C);
2645 }
2646
2647 #ifndef _LP64 // no 32bit push/pop on amd64
2648 void Assembler::pushl(Address src) {
2649 // Note this will push 64bit on 64bit
2650 InstructionMark im(this);
2651 prefix(src);
2652 emit_int8((unsigned char)0xFF);
2653 emit_operand(rsi, src);
2654 }
2655 #endif
2656
2657 void Assembler::rcll(Register dst, int imm8) {
2658 assert(isShiftCount(imm8), "illegal shift count");
2659 int encode = prefix_and_encode(dst->encoding());
2660 if (imm8 == 1) {
2661 emit_int8((unsigned char)0xD1);
2662 emit_int8((unsigned char)(0xD0 | encode));
2663 } else {
2664 emit_int8((unsigned char)0xC1);
2665 emit_int8((unsigned char)0xD0 | encode);
2666 emit_int8(imm8);
2667 }
2668 }
2669
2670 // copies data from [esi] to [edi] using rcx pointer sized words
2671 // generic
2672 void Assembler::rep_mov() {
2673 emit_int8((unsigned char)0xF3);
2674 // MOVSQ
2675 LP64_ONLY(prefix(REX_W));
2676 emit_int8((unsigned char)0xA5);
2677 }
2678
2679 // sets rcx bytes with rax, value at [edi]
2680 void Assembler::rep_stosb() {
2681 emit_int8((unsigned char)0xF3); // REP
2682 LP64_ONLY(prefix(REX_W));
2683 emit_int8((unsigned char)0xAA); // STOSB
2684 }
2685
2686 // sets rcx pointer sized words with rax, value at [edi]
2687 // generic
2688 void Assembler::rep_stos() {
2689 emit_int8((unsigned char)0xF3); // REP
2690 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2691 emit_int8((unsigned char)0xAB);
2692 }
2693
2694 // scans rcx pointer sized words at [edi] for occurance of rax,
2695 // generic
2696 void Assembler::repne_scan() { // repne_scan
2697 emit_int8((unsigned char)0xF2);
2698 // SCASQ
2699 LP64_ONLY(prefix(REX_W));
2700 emit_int8((unsigned char)0xAF);
2701 }
2702
2703 #ifdef _LP64
2704 // scans rcx 4 byte words at [edi] for occurance of rax,
2705 // generic
2706 void Assembler::repne_scanl() { // repne_scan
2707 emit_int8((unsigned char)0xF2);
2708 // SCASL
2709 emit_int8((unsigned char)0xAF);
2710 }
2711 #endif
2712
2713 void Assembler::ret(int imm16) {
2714 if (imm16 == 0) {
2715 emit_int8((unsigned char)0xC3);
2716 } else {
2717 emit_int8((unsigned char)0xC2);
2718 emit_int16(imm16);
2719 }
2720 }
2721
2722 void Assembler::sahf() {
2723 #ifdef _LP64
2724 // Not supported in 64bit mode
2725 ShouldNotReachHere();
2726 #endif
2727 emit_int8((unsigned char)0x9E);
2728 }
2729
2730 void Assembler::sarl(Register dst, int imm8) {
2731 int encode = prefix_and_encode(dst->encoding());
2732 assert(isShiftCount(imm8), "illegal shift count");
2733 if (imm8 == 1) {
2734 emit_int8((unsigned char)0xD1);
2735 emit_int8((unsigned char)(0xF8 | encode));
2736 } else {
2737 emit_int8((unsigned char)0xC1);
2738 emit_int8((unsigned char)(0xF8 | encode));
2739 emit_int8(imm8);
2740 }
2741 }
2742
2743 void Assembler::sarl(Register dst) {
2744 int encode = prefix_and_encode(dst->encoding());
2745 emit_int8((unsigned char)0xD3);
2746 emit_int8((unsigned char)(0xF8 | encode));
2747 }
2748
2749 void Assembler::sbbl(Address dst, int32_t imm32) {
2750 InstructionMark im(this);
2751 prefix(dst);
2752 emit_arith_operand(0x81, rbx, dst, imm32);
2753 }
2754
2755 void Assembler::sbbl(Register dst, int32_t imm32) {
2756 prefix(dst);
2757 emit_arith(0x81, 0xD8, dst, imm32);
2758 }
2759
2760
2761 void Assembler::sbbl(Register dst, Address src) {
2762 InstructionMark im(this);
2763 prefix(src, dst);
2764 emit_int8(0x1B);
2765 emit_operand(dst, src);
2766 }
2767
2768 void Assembler::sbbl(Register dst, Register src) {
2769 (void) prefix_and_encode(dst->encoding(), src->encoding());
2770 emit_arith(0x1B, 0xC0, dst, src);
2771 }
2772
2773 void Assembler::setb(Condition cc, Register dst) {
2774 assert(0 <= cc && cc < 16, "illegal cc");
2775 int encode = prefix_and_encode(dst->encoding(), true);
2776 emit_int8(0x0F);
2777 emit_int8((unsigned char)0x90 | cc);
2778 emit_int8((unsigned char)(0xC0 | encode));
2779 }
2780
2781 void Assembler::shll(Register dst, int imm8) {
2782 assert(isShiftCount(imm8), "illegal shift count");
2783 int encode = prefix_and_encode(dst->encoding());
2784 if (imm8 == 1 ) {
2785 emit_int8((unsigned char)0xD1);
2786 emit_int8((unsigned char)(0xE0 | encode));
2787 } else {
2788 emit_int8((unsigned char)0xC1);
2789 emit_int8((unsigned char)(0xE0 | encode));
2790 emit_int8(imm8);
2791 }
2792 }
2793
2794 void Assembler::shll(Register dst) {
2795 int encode = prefix_and_encode(dst->encoding());
2796 emit_int8((unsigned char)0xD3);
2797 emit_int8((unsigned char)(0xE0 | encode));
2798 }
2799
2800 void Assembler::shrl(Register dst, int imm8) {
2801 assert(isShiftCount(imm8), "illegal shift count");
2802 int encode = prefix_and_encode(dst->encoding());
2803 emit_int8((unsigned char)0xC1);
2804 emit_int8((unsigned char)(0xE8 | encode));
2805 emit_int8(imm8);
2806 }
2807
2808 void Assembler::shrl(Register dst) {
2809 int encode = prefix_and_encode(dst->encoding());
2810 emit_int8((unsigned char)0xD3);
2811 emit_int8((unsigned char)(0xE8 | encode));
2812 }
2813
2814 // copies a single word from [esi] to [edi]
2815 void Assembler::smovl() {
2816 emit_int8((unsigned char)0xA5);
2817 }
2818
2819 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2821 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2822 }
2823
2824 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2825 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2826 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2827 }
2828
2829 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2830 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2831 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2832 }
2833
2834 void Assembler::std() {
2835 emit_int8((unsigned char)0xFD);
2836 }
2837
2838 void Assembler::sqrtss(XMMRegister dst, Address src) {
2839 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2840 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2841 }
2842
2843 void Assembler::stmxcsr( Address dst) {
2844 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2845 InstructionMark im(this);
2846 prefix(dst);
2847 emit_int8(0x0F);
2848 emit_int8((unsigned char)0xAE);
2849 emit_operand(as_Register(3), dst);
2850 }
2851
2852 void Assembler::subl(Address dst, int32_t imm32) {
2853 InstructionMark im(this);
2854 prefix(dst);
2855 emit_arith_operand(0x81, rbp, dst, imm32);
2856 }
2857
2858 void Assembler::subl(Address dst, Register src) {
2859 InstructionMark im(this);
2860 prefix(dst, src);
2861 emit_int8(0x29);
2862 emit_operand(src, dst);
2863 }
2864
2865 void Assembler::subl(Register dst, int32_t imm32) {
2866 prefix(dst);
2867 emit_arith(0x81, 0xE8, dst, imm32);
2868 }
2869
2870 // Force generation of a 4 byte immediate value even if it fits into 8bit
2871 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2872 prefix(dst);
2873 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2874 }
2875
2876 void Assembler::subl(Register dst, Address src) {
2877 InstructionMark im(this);
2878 prefix(src, dst);
2879 emit_int8(0x2B);
2880 emit_operand(dst, src);
2881 }
2882
2883 void Assembler::subl(Register dst, Register src) {
2884 (void) prefix_and_encode(dst->encoding(), src->encoding());
2885 emit_arith(0x2B, 0xC0, dst, src);
2886 }
2887
2888 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2889 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2890 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2891 }
2892
2893 void Assembler::subsd(XMMRegister dst, Address src) {
2894 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2895 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2896 }
2897
2898 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2899 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2900 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2901 }
2902
2903 void Assembler::subss(XMMRegister dst, Address src) {
2904 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2905 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2906 }
2907
2908 void Assembler::testb(Register dst, int imm8) {
2909 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2910 (void) prefix_and_encode(dst->encoding(), true);
2911 emit_arith_b(0xF6, 0xC0, dst, imm8);
2912 }
2913
2914 void Assembler::testl(Register dst, int32_t imm32) {
2915 // not using emit_arith because test
2916 // doesn't support sign-extension of
2917 // 8bit operands
2918 int encode = dst->encoding();
2919 if (encode == 0) {
2920 emit_int8((unsigned char)0xA9);
2921 } else {
2922 encode = prefix_and_encode(encode);
2923 emit_int8((unsigned char)0xF7);
2924 emit_int8((unsigned char)(0xC0 | encode));
2925 }
2926 emit_int32(imm32);
2927 }
2928
2929 void Assembler::testl(Register dst, Register src) {
2930 (void) prefix_and_encode(dst->encoding(), src->encoding());
2931 emit_arith(0x85, 0xC0, dst, src);
2932 }
2933
2934 void Assembler::testl(Register dst, Address src) {
2935 InstructionMark im(this);
2936 prefix(src, dst);
2937 emit_int8((unsigned char)0x85);
2938 emit_operand(dst, src);
2939 }
2940
2941 void Assembler::tzcntl(Register dst, Register src) {
2942 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2943 emit_int8((unsigned char)0xF3);
2944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2945 emit_int8(0x0F);
2946 emit_int8((unsigned char)0xBC);
2947 emit_int8((unsigned char)0xC0 | encode);
2948 }
2949
2950 void Assembler::tzcntq(Register dst, Register src) {
2951 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2952 emit_int8((unsigned char)0xF3);
2953 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2954 emit_int8(0x0F);
2955 emit_int8((unsigned char)0xBC);
2956 emit_int8((unsigned char)(0xC0 | encode));
2957 }
2958
2959 void Assembler::ucomisd(XMMRegister dst, Address src) {
2960 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2961 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2962 }
2963
2964 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2965 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2966 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2967 }
2968
2969 void Assembler::ucomiss(XMMRegister dst, Address src) {
2970 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2971 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2972 }
2973
2974 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2975 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2976 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2977 }
2978
2979
2980 void Assembler::xaddl(Address dst, Register src) {
2981 InstructionMark im(this);
2982 prefix(dst, src);
2983 emit_int8(0x0F);
2984 emit_int8((unsigned char)0xC1);
2985 emit_operand(src, dst);
2986 }
2987
2988 void Assembler::xchgl(Register dst, Address src) { // xchg
2989 InstructionMark im(this);
2990 prefix(src, dst);
2991 emit_int8((unsigned char)0x87);
2992 emit_operand(dst, src);
2993 }
2994
2995 void Assembler::xchgl(Register dst, Register src) {
2996 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2997 emit_int8((unsigned char)0x87);
2998 emit_int8((unsigned char)(0xC0 | encode));
2999 }
3000
3001 void Assembler::xgetbv() {
3002 emit_int8(0x0F);
3003 emit_int8(0x01);
3004 emit_int8((unsigned char)0xD0);
3005 }
3006
3007 void Assembler::xorl(Register dst, int32_t imm32) {
3008 prefix(dst);
3009 emit_arith(0x81, 0xF0, dst, imm32);
3010 }
3011
3012 void Assembler::xorl(Register dst, Address src) {
3013 InstructionMark im(this);
3014 prefix(src, dst);
3015 emit_int8(0x33);
3016 emit_operand(dst, src);
3017 }
3018
3019 void Assembler::xorl(Register dst, Register src) {
3020 (void) prefix_and_encode(dst->encoding(), src->encoding());
3021 emit_arith(0x33, 0xC0, dst, src);
3022 }
3023
3024
3025 // AVX 3-operands scalar float-point arithmetic instructions
3026
3027 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3028 assert(VM_Version::supports_avx(), "");
3029 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3030 }
3031
3032 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3033 assert(VM_Version::supports_avx(), "");
3034 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3035 }
3036
3037 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3038 assert(VM_Version::supports_avx(), "");
3039 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3040 }
3041
3042 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3043 assert(VM_Version::supports_avx(), "");
3044 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3045 }
3046
3047 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3048 assert(VM_Version::supports_avx(), "");
3049 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3050 }
3051
3052 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3053 assert(VM_Version::supports_avx(), "");
3054 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3055 }
3056
3057 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3058 assert(VM_Version::supports_avx(), "");
3059 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3060 }
3061
3062 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3063 assert(VM_Version::supports_avx(), "");
3064 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3065 }
3066
3067 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3068 assert(VM_Version::supports_avx(), "");
3069 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3070 }
3071
3072 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3073 assert(VM_Version::supports_avx(), "");
3074 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3075 }
3076
3077 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3078 assert(VM_Version::supports_avx(), "");
3079 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3080 }
3081
3082 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3083 assert(VM_Version::supports_avx(), "");
3084 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3085 }
3086
3087 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3088 assert(VM_Version::supports_avx(), "");
3089 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3090 }
3091
3092 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3093 assert(VM_Version::supports_avx(), "");
3094 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3095 }
3096
3097 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3098 assert(VM_Version::supports_avx(), "");
3099 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3100 }
3101
3102 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3103 assert(VM_Version::supports_avx(), "");
3104 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3105 }
3106
3107 //====================VECTOR ARITHMETIC=====================================
3108
3109 // Float-point vector arithmetic
3110
3111 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3112 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3113 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3114 }
3115
3116 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3117 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3118 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3119 }
3120
3121 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3122 assert(VM_Version::supports_avx(), "");
3123 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3124 }
3125
3126 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3127 assert(VM_Version::supports_avx(), "");
3128 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3129 }
3130
3131 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3132 assert(VM_Version::supports_avx(), "");
3133 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3134 }
3135
3136 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3137 assert(VM_Version::supports_avx(), "");
3138 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3139 }
3140
3141 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3142 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3143 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3144 }
3145
3146 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3147 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3148 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3149 }
3150
3151 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3152 assert(VM_Version::supports_avx(), "");
3153 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3154 }
3155
3156 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3157 assert(VM_Version::supports_avx(), "");
3158 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3159 }
3160
3161 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3162 assert(VM_Version::supports_avx(), "");
3163 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3164 }
3165
3166 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3167 assert(VM_Version::supports_avx(), "");
3168 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3169 }
3170
3171 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3173 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3174 }
3175
3176 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3178 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3179 }
3180
3181 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3182 assert(VM_Version::supports_avx(), "");
3183 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3184 }
3185
3186 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3187 assert(VM_Version::supports_avx(), "");
3188 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3189 }
3190
3191 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3192 assert(VM_Version::supports_avx(), "");
3193 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3194 }
3195
3196 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3197 assert(VM_Version::supports_avx(), "");
3198 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3199 }
3200
3201 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3202 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3203 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3204 }
3205
3206 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3207 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3208 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3209 }
3210
3211 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3212 assert(VM_Version::supports_avx(), "");
3213 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3214 }
3215
3216 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3217 assert(VM_Version::supports_avx(), "");
3218 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3219 }
3220
3221 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3222 assert(VM_Version::supports_avx(), "");
3223 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3224 }
3225
3226 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3227 assert(VM_Version::supports_avx(), "");
3228 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3229 }
3230
3231 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3232 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3233 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3234 }
3235
3236 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3237 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3238 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3239 }
3240
3241 void Assembler::andps(XMMRegister dst, Address src) {
3242 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3243 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3244 }
3245
3246 void Assembler::andpd(XMMRegister dst, Address src) {
3247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3248 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3249 }
3250
3251 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3252 assert(VM_Version::supports_avx(), "");
3253 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3254 }
3255
3256 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3257 assert(VM_Version::supports_avx(), "");
3258 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3259 }
3260
3261 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3262 assert(VM_Version::supports_avx(), "");
3263 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3264 }
3265
3266 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3267 assert(VM_Version::supports_avx(), "");
3268 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3269 }
3270
3271 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3272 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3273 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3274 }
3275
3276 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3277 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3278 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3279 }
3280
3281 void Assembler::xorpd(XMMRegister dst, Address src) {
3282 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3283 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3284 }
3285
3286 void Assembler::xorps(XMMRegister dst, Address src) {
3287 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3288 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3289 }
3290
3291 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3292 assert(VM_Version::supports_avx(), "");
3293 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3294 }
3295
3296 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3297 assert(VM_Version::supports_avx(), "");
3298 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3299 }
3300
3301 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3302 assert(VM_Version::supports_avx(), "");
3303 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3304 }
3305
3306 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3307 assert(VM_Version::supports_avx(), "");
3308 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3309 }
3310
3311
3312 // Integer vector arithmetic
3313 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3314 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3315 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3316 }
3317
3318 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3320 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3321 }
3322
3323 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3324 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3325 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3326 }
3327
3328 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3330 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3331 }
3332
3333 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3334 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3335 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3336 }
3337
3338 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3339 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3340 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3341 }
3342
3343 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3344 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3345 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3346 }
3347
3348 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3349 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3350 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3351 }
3352
3353 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3354 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3355 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3356 }
3357
3358 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3359 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3360 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3361 }
3362
3363 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3364 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3365 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3366 }
3367
3368 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3369 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3370 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3371 }
3372
3373 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3375 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3376 }
3377
3378 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3379 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3380 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3381 }
3382
3383 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3385 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3386 }
3387
3388 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3389 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3390 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3391 }
3392
3393 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3394 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3395 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3396 }
3397
3398 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3399 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3400 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3401 }
3402
3403 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3404 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3405 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3406 }
3407
3408 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3409 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3410 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3411 }
3412
3413 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3414 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3415 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3416 }
3417
3418 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3419 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3420 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3421 }
3422
3423 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3424 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3425 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3426 }
3427
3428 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3429 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3430 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3431 }
3432
3433 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3434 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3435 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3436 }
3437
3438 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3439 assert(VM_Version::supports_sse4_1(), "");
3440 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3441 emit_int8(0x40);
3442 emit_int8((unsigned char)(0xC0 | encode));
3443 }
3444
3445 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3446 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3447 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3448 }
3449
3450 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3451 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3452 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3453 emit_int8(0x40);
3454 emit_int8((unsigned char)(0xC0 | encode));
3455 }
3456
3457 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3458 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3459 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3460 }
3461
3462 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3463 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3464 InstructionMark im(this);
3465 int dst_enc = dst->encoding();
3466 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3467 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3468 emit_int8(0x40);
3469 emit_operand(dst, src);
3470 }
3471
3472 // Shift packed integers left by specified number of bits.
3473 void Assembler::psllw(XMMRegister dst, int shift) {
3474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3475 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3476 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3477 emit_int8(0x71);
3478 emit_int8((unsigned char)(0xC0 | encode));
3479 emit_int8(shift & 0xFF);
3480 }
3481
3482 void Assembler::pslld(XMMRegister dst, int shift) {
3483 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3484 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3485 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3486 emit_int8(0x72);
3487 emit_int8((unsigned char)(0xC0 | encode));
3488 emit_int8(shift & 0xFF);
3489 }
3490
3491 void Assembler::psllq(XMMRegister dst, int shift) {
3492 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3493 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3494 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3495 emit_int8(0x73);
3496 emit_int8((unsigned char)(0xC0 | encode));
3497 emit_int8(shift & 0xFF);
3498 }
3499
3500 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3501 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3502 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3503 }
3504
3505 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3507 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3508 }
3509
3510 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3511 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3512 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3513 }
3514
3515 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3516 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3517 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3518 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3519 emit_int8(shift & 0xFF);
3520 }
3521
3522 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3523 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3524 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3525 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3526 emit_int8(shift & 0xFF);
3527 }
3528
3529 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3530 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3531 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3532 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3533 emit_int8(shift & 0xFF);
3534 }
3535
3536 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3537 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3538 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3539 }
3540
3541 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3542 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3543 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3544 }
3545
3546 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3547 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3548 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3549 }
3550
3551 // Shift packed integers logically right by specified number of bits.
3552 void Assembler::psrlw(XMMRegister dst, int shift) {
3553 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3554 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3555 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3556 emit_int8(0x71);
3557 emit_int8((unsigned char)(0xC0 | encode));
3558 emit_int8(shift & 0xFF);
3559 }
3560
3561 void Assembler::psrld(XMMRegister dst, int shift) {
3562 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3563 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3564 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3565 emit_int8(0x72);
3566 emit_int8((unsigned char)(0xC0 | encode));
3567 emit_int8(shift & 0xFF);
3568 }
3569
3570 void Assembler::psrlq(XMMRegister dst, int shift) {
3571 // Do not confuse it with psrldq SSE2 instruction which
3572 // shifts 128 bit value in xmm register by number of bytes.
3573 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3574 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3575 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3576 emit_int8(0x73);
3577 emit_int8((unsigned char)(0xC0 | encode));
3578 emit_int8(shift & 0xFF);
3579 }
3580
3581 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3582 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3583 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3584 }
3585
3586 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3587 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3588 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3589 }
3590
3591 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3592 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3593 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3594 }
3595
3596 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3597 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3598 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3599 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3600 emit_int8(shift & 0xFF);
3601 }
3602
3603 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3604 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3605 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3606 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3607 emit_int8(shift & 0xFF);
3608 }
3609
3610 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3611 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3612 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3613 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3614 emit_int8(shift & 0xFF);
3615 }
3616
3617 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3618 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3619 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3620 }
3621
3622 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3623 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3624 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3625 }
3626
3627 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3628 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3629 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3630 }
3631
3632 // Shift packed integers arithmetically right by specified number of bits.
3633 void Assembler::psraw(XMMRegister dst, int shift) {
3634 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3635 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3636 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3637 emit_int8(0x71);
3638 emit_int8((unsigned char)(0xC0 | encode));
3639 emit_int8(shift & 0xFF);
3640 }
3641
3642 void Assembler::psrad(XMMRegister dst, int shift) {
3643 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3644 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3645 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3646 emit_int8(0x72);
3647 emit_int8((unsigned char)(0xC0 | encode));
3648 emit_int8(shift & 0xFF);
3649 }
3650
3651 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3653 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3654 }
3655
3656 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3658 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3659 }
3660
3661 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3662 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3663 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3664 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3665 emit_int8(shift & 0xFF);
3666 }
3667
3668 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3669 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3670 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3671 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3672 emit_int8(shift & 0xFF);
3673 }
3674
3675 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3676 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3677 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3678 }
3679
3680 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3681 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3682 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3683 }
3684
3685
3686 // AND packed integers
3687 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3688 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3689 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3690 }
3691
3692 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3693 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3694 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3695 }
3696
3697 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3698 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3699 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3700 }
3701
3702 void Assembler::por(XMMRegister dst, XMMRegister src) {
3703 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3704 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3705 }
3706
3707 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3708 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3709 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3710 }
3711
3712 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3713 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3714 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3715 }
3716
3717 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3719 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3720 }
3721
3722 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3723 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3724 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3725 }
3726
3727 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3728 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3729 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3730 }
3731
3732
3733 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3734 assert(VM_Version::supports_avx(), "");
3735 bool vector256 = true;
3736 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3737 emit_int8(0x18);
3738 emit_int8((unsigned char)(0xC0 | encode));
3739 // 0x00 - insert into lower 128 bits
3740 // 0x01 - insert into upper 128 bits
3741 emit_int8(0x01);
3742 }
3743
3744 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3745 assert(VM_Version::supports_avx(), "");
3746 InstructionMark im(this);
3747 bool vector256 = true;
3748 assert(dst != xnoreg, "sanity");
3749 int dst_enc = dst->encoding();
3750 // swap src<->dst for encoding
3751 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3752 emit_int8(0x18);
3753 emit_operand(dst, src);
3754 // 0x01 - insert into upper 128 bits
3755 emit_int8(0x01);
3756 }
3757
3758 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3759 assert(VM_Version::supports_avx(), "");
3760 InstructionMark im(this);
3761 bool vector256 = true;
3762 assert(src != xnoreg, "sanity");
3763 int src_enc = src->encoding();
3764 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3765 emit_int8(0x19);
3766 emit_operand(src, dst);
3767 // 0x01 - extract from upper 128 bits
3768 emit_int8(0x01);
3769 }
3770
3771 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3772 assert(VM_Version::supports_avx2(), "");
3773 bool vector256 = true;
3774 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3775 emit_int8(0x38);
3776 emit_int8((unsigned char)(0xC0 | encode));
3777 // 0x00 - insert into lower 128 bits
3778 // 0x01 - insert into upper 128 bits
3779 emit_int8(0x01);
3780 }
3781
3782 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3783 assert(VM_Version::supports_avx2(), "");
3784 InstructionMark im(this);
3785 bool vector256 = true;
3786 assert(dst != xnoreg, "sanity");
3787 int dst_enc = dst->encoding();
3788 // swap src<->dst for encoding
3789 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3790 emit_int8(0x38);
3791 emit_operand(dst, src);
3792 // 0x01 - insert into upper 128 bits
3793 emit_int8(0x01);
3794 }
3795
3796 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3797 assert(VM_Version::supports_avx2(), "");
3798 InstructionMark im(this);
3799 bool vector256 = true;
3800 assert(src != xnoreg, "sanity");
3801 int src_enc = src->encoding();
3802 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3803 emit_int8(0x39);
3804 emit_operand(src, dst);
3805 // 0x01 - extract from upper 128 bits
3806 emit_int8(0x01);
3807 }
3808
3809 // duplicate 4-bytes integer data from src into 8 locations in dest
3810 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3811 assert(VM_Version::supports_avx2(), "");
3812 bool vector256 = true;
3813 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3814 emit_int8(0x58);
3815 emit_int8((unsigned char)(0xC0 | encode));
3816 }
3817
3818 // Carry-Less Multiplication Quadword
3819 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3820 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3821 bool vector256 = false;
3822 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3823 emit_int8(0x44);
3824 emit_int8((unsigned char)(0xC0 | encode));
3825 emit_int8((unsigned char)mask);
3826 }
3827
3828 void Assembler::vzeroupper() {
3829 assert(VM_Version::supports_avx(), "");
3830 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3831 emit_int8(0x77);
3832 }
3833
3834
3835 #ifndef _LP64
3836 // 32bit only pieces of the assembler
3837
3838 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3839 // NO PREFIX AS NEVER 64BIT
3840 InstructionMark im(this);
3841 emit_int8((unsigned char)0x81);
3842 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3843 emit_data(imm32, rspec, 0);
3844 }
3845
3846 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3847 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3848 InstructionMark im(this);
3849 emit_int8((unsigned char)0x81);
3850 emit_operand(rdi, src1);
3851 emit_data(imm32, rspec, 0);
3852 }
3853
3854 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3855 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3856 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3857 void Assembler::cmpxchg8(Address adr) {
3858 InstructionMark im(this);
3859 emit_int8(0x0F);
3860 emit_int8((unsigned char)0xC7);
3861 emit_operand(rcx, adr);
3862 }
3863
3864 void Assembler::decl(Register dst) {
3865 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3866 emit_int8(0x48 | dst->encoding());
3867 }
3868
3869 #endif // _LP64
3870
3871 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3872
3873 void Assembler::fabs() {
3874 emit_int8((unsigned char)0xD9);
3875 emit_int8((unsigned char)0xE1);
3876 }
3877
3878 void Assembler::fadd(int i) {
3879 emit_farith(0xD8, 0xC0, i);
3880 }
3881
3882 void Assembler::fadd_d(Address src) {
3883 InstructionMark im(this);
3884 emit_int8((unsigned char)0xDC);
3885 emit_operand32(rax, src);
3886 }
3887
3888 void Assembler::fadd_s(Address src) {
3889 InstructionMark im(this);
3890 emit_int8((unsigned char)0xD8);
3891 emit_operand32(rax, src);
3892 }
3893
3894 void Assembler::fadda(int i) {
3895 emit_farith(0xDC, 0xC0, i);
3896 }
3897
3898 void Assembler::faddp(int i) {
3899 emit_farith(0xDE, 0xC0, i);
3900 }
3901
3902 void Assembler::fchs() {
3903 emit_int8((unsigned char)0xD9);
3904 emit_int8((unsigned char)0xE0);
3905 }
3906
3907 void Assembler::fcom(int i) {
3908 emit_farith(0xD8, 0xD0, i);
3909 }
3910
3911 void Assembler::fcomp(int i) {
3912 emit_farith(0xD8, 0xD8, i);
3913 }
3914
3915 void Assembler::fcomp_d(Address src) {
3916 InstructionMark im(this);
3917 emit_int8((unsigned char)0xDC);
3918 emit_operand32(rbx, src);
3919 }
3920
3921 void Assembler::fcomp_s(Address src) {
3922 InstructionMark im(this);
3923 emit_int8((unsigned char)0xD8);
3924 emit_operand32(rbx, src);
3925 }
3926
3927 void Assembler::fcompp() {
3928 emit_int8((unsigned char)0xDE);
3929 emit_int8((unsigned char)0xD9);
3930 }
3931
3932 void Assembler::fcos() {
3933 emit_int8((unsigned char)0xD9);
3934 emit_int8((unsigned char)0xFF);
3935 }
3936
3937 void Assembler::fdecstp() {
3938 emit_int8((unsigned char)0xD9);
3939 emit_int8((unsigned char)0xF6);
3940 }
3941
3942 void Assembler::fdiv(int i) {
3943 emit_farith(0xD8, 0xF0, i);
3944 }
3945
3946 void Assembler::fdiv_d(Address src) {
3947 InstructionMark im(this);
3948 emit_int8((unsigned char)0xDC);
3949 emit_operand32(rsi, src);
3950 }
3951
3952 void Assembler::fdiv_s(Address src) {
3953 InstructionMark im(this);
3954 emit_int8((unsigned char)0xD8);
3955 emit_operand32(rsi, src);
3956 }
3957
3958 void Assembler::fdiva(int i) {
3959 emit_farith(0xDC, 0xF8, i);
3960 }
3961
3962 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3963 // is erroneous for some of the floating-point instructions below.
3964
3965 void Assembler::fdivp(int i) {
3966 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3967 }
3968
3969 void Assembler::fdivr(int i) {
3970 emit_farith(0xD8, 0xF8, i);
3971 }
3972
3973 void Assembler::fdivr_d(Address src) {
3974 InstructionMark im(this);
3975 emit_int8((unsigned char)0xDC);
3976 emit_operand32(rdi, src);
3977 }
3978
3979 void Assembler::fdivr_s(Address src) {
3980 InstructionMark im(this);
3981 emit_int8((unsigned char)0xD8);
3982 emit_operand32(rdi, src);
3983 }
3984
3985 void Assembler::fdivra(int i) {
3986 emit_farith(0xDC, 0xF0, i);
3987 }
3988
3989 void Assembler::fdivrp(int i) {
3990 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3991 }
3992
3993 void Assembler::ffree(int i) {
3994 emit_farith(0xDD, 0xC0, i);
3995 }
3996
3997 void Assembler::fild_d(Address adr) {
3998 InstructionMark im(this);
3999 emit_int8((unsigned char)0xDF);
4000 emit_operand32(rbp, adr);
4001 }
4002
4003 void Assembler::fild_s(Address adr) {
4004 InstructionMark im(this);
4005 emit_int8((unsigned char)0xDB);
4006 emit_operand32(rax, adr);
4007 }
4008
4009 void Assembler::fincstp() {
4010 emit_int8((unsigned char)0xD9);
4011 emit_int8((unsigned char)0xF7);
4012 }
4013
4014 void Assembler::finit() {
4015 emit_int8((unsigned char)0x9B);
4016 emit_int8((unsigned char)0xDB);
4017 emit_int8((unsigned char)0xE3);
4018 }
4019
4020 void Assembler::fist_s(Address adr) {
4021 InstructionMark im(this);
4022 emit_int8((unsigned char)0xDB);
4023 emit_operand32(rdx, adr);
4024 }
4025
4026 void Assembler::fistp_d(Address adr) {
4027 InstructionMark im(this);
4028 emit_int8((unsigned char)0xDF);
4029 emit_operand32(rdi, adr);
4030 }
4031
4032 void Assembler::fistp_s(Address adr) {
4033 InstructionMark im(this);
4034 emit_int8((unsigned char)0xDB);
4035 emit_operand32(rbx, adr);
4036 }
4037
4038 void Assembler::fld1() {
4039 emit_int8((unsigned char)0xD9);
4040 emit_int8((unsigned char)0xE8);
4041 }
4042
4043 void Assembler::fld_d(Address adr) {
4044 InstructionMark im(this);
4045 emit_int8((unsigned char)0xDD);
4046 emit_operand32(rax, adr);
4047 }
4048
4049 void Assembler::fld_s(Address adr) {
4050 InstructionMark im(this);
4051 emit_int8((unsigned char)0xD9);
4052 emit_operand32(rax, adr);
4053 }
4054
4055
4056 void Assembler::fld_s(int index) {
4057 emit_farith(0xD9, 0xC0, index);
4058 }
4059
4060 void Assembler::fld_x(Address adr) {
4061 InstructionMark im(this);
4062 emit_int8((unsigned char)0xDB);
4063 emit_operand32(rbp, adr);
4064 }
4065
4066 void Assembler::fldcw(Address src) {
4067 InstructionMark im(this);
4068 emit_int8((unsigned char)0xD9);
4069 emit_operand32(rbp, src);
4070 }
4071
4072 void Assembler::fldenv(Address src) {
4073 InstructionMark im(this);
4074 emit_int8((unsigned char)0xD9);
4075 emit_operand32(rsp, src);
4076 }
4077
4078 void Assembler::fldlg2() {
4079 emit_int8((unsigned char)0xD9);
4080 emit_int8((unsigned char)0xEC);
4081 }
4082
4083 void Assembler::fldln2() {
4084 emit_int8((unsigned char)0xD9);
4085 emit_int8((unsigned char)0xED);
4086 }
4087
4088 void Assembler::fldz() {
4089 emit_int8((unsigned char)0xD9);
4090 emit_int8((unsigned char)0xEE);
4091 }
4092
4093 void Assembler::flog() {
4094 fldln2();
4095 fxch();
4096 fyl2x();
4097 }
4098
4099 void Assembler::flog10() {
4100 fldlg2();
4101 fxch();
4102 fyl2x();
4103 }
4104
4105 void Assembler::fmul(int i) {
4106 emit_farith(0xD8, 0xC8, i);
4107 }
4108
4109 void Assembler::fmul_d(Address src) {
4110 InstructionMark im(this);
4111 emit_int8((unsigned char)0xDC);
4112 emit_operand32(rcx, src);
4113 }
4114
4115 void Assembler::fmul_s(Address src) {
4116 InstructionMark im(this);
4117 emit_int8((unsigned char)0xD8);
4118 emit_operand32(rcx, src);
4119 }
4120
4121 void Assembler::fmula(int i) {
4122 emit_farith(0xDC, 0xC8, i);
4123 }
4124
4125 void Assembler::fmulp(int i) {
4126 emit_farith(0xDE, 0xC8, i);
4127 }
4128
4129 void Assembler::fnsave(Address dst) {
4130 InstructionMark im(this);
4131 emit_int8((unsigned char)0xDD);
4132 emit_operand32(rsi, dst);
4133 }
4134
4135 void Assembler::fnstcw(Address src) {
4136 InstructionMark im(this);
4137 emit_int8((unsigned char)0x9B);
4138 emit_int8((unsigned char)0xD9);
4139 emit_operand32(rdi, src);
4140 }
4141
4142 void Assembler::fnstsw_ax() {
4143 emit_int8((unsigned char)0xDF);
4144 emit_int8((unsigned char)0xE0);
4145 }
4146
4147 void Assembler::fprem() {
4148 emit_int8((unsigned char)0xD9);
4149 emit_int8((unsigned char)0xF8);
4150 }
4151
4152 void Assembler::fprem1() {
4153 emit_int8((unsigned char)0xD9);
4154 emit_int8((unsigned char)0xF5);
4155 }
4156
4157 void Assembler::frstor(Address src) {
4158 InstructionMark im(this);
4159 emit_int8((unsigned char)0xDD);
4160 emit_operand32(rsp, src);
4161 }
4162
4163 void Assembler::fsin() {
4164 emit_int8((unsigned char)0xD9);
4165 emit_int8((unsigned char)0xFE);
4166 }
4167
4168 void Assembler::fsqrt() {
4169 emit_int8((unsigned char)0xD9);
4170 emit_int8((unsigned char)0xFA);
4171 }
4172
4173 void Assembler::fst_d(Address adr) {
4174 InstructionMark im(this);
4175 emit_int8((unsigned char)0xDD);
4176 emit_operand32(rdx, adr);
4177 }
4178
4179 void Assembler::fst_s(Address adr) {
4180 InstructionMark im(this);
4181 emit_int8((unsigned char)0xD9);
4182 emit_operand32(rdx, adr);
4183 }
4184
4185 void Assembler::fstp_d(Address adr) {
4186 InstructionMark im(this);
4187 emit_int8((unsigned char)0xDD);
4188 emit_operand32(rbx, adr);
4189 }
4190
4191 void Assembler::fstp_d(int index) {
4192 emit_farith(0xDD, 0xD8, index);
4193 }
4194
4195 void Assembler::fstp_s(Address adr) {
4196 InstructionMark im(this);
4197 emit_int8((unsigned char)0xD9);
4198 emit_operand32(rbx, adr);
4199 }
4200
4201 void Assembler::fstp_x(Address adr) {
4202 InstructionMark im(this);
4203 emit_int8((unsigned char)0xDB);
4204 emit_operand32(rdi, adr);
4205 }
4206
4207 void Assembler::fsub(int i) {
4208 emit_farith(0xD8, 0xE0, i);
4209 }
4210
4211 void Assembler::fsub_d(Address src) {
4212 InstructionMark im(this);
4213 emit_int8((unsigned char)0xDC);
4214 emit_operand32(rsp, src);
4215 }
4216
4217 void Assembler::fsub_s(Address src) {
4218 InstructionMark im(this);
4219 emit_int8((unsigned char)0xD8);
4220 emit_operand32(rsp, src);
4221 }
4222
4223 void Assembler::fsuba(int i) {
4224 emit_farith(0xDC, 0xE8, i);
4225 }
4226
4227 void Assembler::fsubp(int i) {
4228 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4229 }
4230
4231 void Assembler::fsubr(int i) {
4232 emit_farith(0xD8, 0xE8, i);
4233 }
4234
4235 void Assembler::fsubr_d(Address src) {
4236 InstructionMark im(this);
4237 emit_int8((unsigned char)0xDC);
4238 emit_operand32(rbp, src);
4239 }
4240
4241 void Assembler::fsubr_s(Address src) {
4242 InstructionMark im(this);
4243 emit_int8((unsigned char)0xD8);
4244 emit_operand32(rbp, src);
4245 }
4246
4247 void Assembler::fsubra(int i) {
4248 emit_farith(0xDC, 0xE0, i);
4249 }
4250
4251 void Assembler::fsubrp(int i) {
4252 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4253 }
4254
4255 void Assembler::ftan() {
4256 emit_int8((unsigned char)0xD9);
4257 emit_int8((unsigned char)0xF2);
4258 emit_int8((unsigned char)0xDD);
4259 emit_int8((unsigned char)0xD8);
4260 }
4261
4262 void Assembler::ftst() {
4263 emit_int8((unsigned char)0xD9);
4264 emit_int8((unsigned char)0xE4);
4265 }
4266
4267 void Assembler::fucomi(int i) {
4268 // make sure the instruction is supported (introduced for P6, together with cmov)
4269 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4270 emit_farith(0xDB, 0xE8, i);
4271 }
4272
4273 void Assembler::fucomip(int i) {
4274 // make sure the instruction is supported (introduced for P6, together with cmov)
4275 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4276 emit_farith(0xDF, 0xE8, i);
4277 }
4278
4279 void Assembler::fwait() {
4280 emit_int8((unsigned char)0x9B);
4281 }
4282
4283 void Assembler::fxch(int i) {
4284 emit_farith(0xD9, 0xC8, i);
4285 }
4286
4287 void Assembler::fyl2x() {
4288 emit_int8((unsigned char)0xD9);
4289 emit_int8((unsigned char)0xF1);
4290 }
4291
4292 void Assembler::frndint() {
4293 emit_int8((unsigned char)0xD9);
4294 emit_int8((unsigned char)0xFC);
4295 }
4296
4297 void Assembler::f2xm1() {
4298 emit_int8((unsigned char)0xD9);
4299 emit_int8((unsigned char)0xF0);
4300 }
4301
4302 void Assembler::fldl2e() {
4303 emit_int8((unsigned char)0xD9);
4304 emit_int8((unsigned char)0xEA);
4305 }
4306
4307 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4308 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4309 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4310 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4311
4312 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4313 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4314 if (pre > 0) {
4315 emit_int8(simd_pre[pre]);
4316 }
4317 if (rex_w) {
4318 prefixq(adr, xreg);
4319 } else {
4320 prefix(adr, xreg);
4321 }
4322 if (opc > 0) {
4323 emit_int8(0x0F);
4324 int opc2 = simd_opc[opc];
4325 if (opc2 > 0) {
4326 emit_int8(opc2);
4327 }
4328 }
4329 }
4330
4331 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4332 if (pre > 0) {
4333 emit_int8(simd_pre[pre]);
4334 }
4335 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4336 prefix_and_encode(dst_enc, src_enc);
4337 if (opc > 0) {
4338 emit_int8(0x0F);
4339 int opc2 = simd_opc[opc];
4340 if (opc2 > 0) {
4341 emit_int8(opc2);
4342 }
4343 }
4344 return encode;
4345 }
4346
4347
4348 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4349 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4350 prefix(VEX_3bytes);
4351
4352 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4353 byte1 = (~byte1) & 0xE0;
4354 byte1 |= opc;
4355 emit_int8(byte1);
4356
4357 int byte2 = ((~nds_enc) & 0xf) << 3;
4358 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4359 emit_int8(byte2);
4360 } else {
4361 prefix(VEX_2bytes);
4362
4363 int byte1 = vex_r ? VEX_R : 0;
4364 byte1 = (~byte1) & 0x80;
4365 byte1 |= ((~nds_enc) & 0xf) << 3;
4366 byte1 |= (vector256 ? 4 : 0) | pre;
4367 emit_int8(byte1);
4368 }
4369 }
4370
4371 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4372 bool vex_r = (xreg_enc >= 8);
4373 bool vex_b = adr.base_needs_rex();
4374 bool vex_x = adr.index_needs_rex();
4375 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4376 }
4377
4378 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4379 bool vex_r = (dst_enc >= 8);
4380 bool vex_b = (src_enc >= 8);
4381 bool vex_x = false;
4382 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4383 return (((dst_enc & 7) << 3) | (src_enc & 7));
4384 }
4385
4386
4387 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4388 if (UseAVX > 0) {
4389 int xreg_enc = xreg->encoding();
4390 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4391 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4392 } else {
4393 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4394 rex_prefix(adr, xreg, pre, opc, rex_w);
4395 }
4396 }
4397
4398 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4399 int dst_enc = dst->encoding();
4400 int src_enc = src->encoding();
4401 if (UseAVX > 0) {
4402 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4403 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4404 } else {
4405 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4406 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4407 }
4408 }
4409
4410 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4411 InstructionMark im(this);
4412 simd_prefix(dst, dst, src, pre);
4413 emit_int8(opcode);
4414 emit_operand(dst, src);
4415 }
4416
4417 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4418 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4419 emit_int8(opcode);
4420 emit_int8((unsigned char)(0xC0 | encode));
4421 }
4422
4423 // Versions with no second source register (non-destructive source).
4424 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4425 InstructionMark im(this);
4426 simd_prefix(dst, xnoreg, src, pre);
4427 emit_int8(opcode);
4428 emit_operand(dst, src);
4429 }
4430
4431 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4432 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4433 emit_int8(opcode);
4434 emit_int8((unsigned char)(0xC0 | encode));
4435 }
4436
4437 // 3-operands AVX instructions
4438 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4439 Address src, VexSimdPrefix pre, bool vector256) {
4440 InstructionMark im(this);
4441 vex_prefix(dst, nds, src, pre, vector256);
4442 emit_int8(opcode);
4443 emit_operand(dst, src);
4444 }
4445
4446 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4447 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4448 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4449 emit_int8(opcode);
4450 emit_int8((unsigned char)(0xC0 | encode));
4451 }
4452
4453 #ifndef _LP64
4454
4455 void Assembler::incl(Register dst) {
4456 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4457 emit_int8(0x40 | dst->encoding());
4458 }
4459
4460 void Assembler::lea(Register dst, Address src) {
4461 leal(dst, src);
4462 }
4463
4464 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4465 InstructionMark im(this);
4466 emit_int8((unsigned char)0xC7);
4467 emit_operand(rax, dst);
4468 emit_data((int)imm32, rspec, 0);
4469 }
4470
4471 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4472 InstructionMark im(this);
4473 int encode = prefix_and_encode(dst->encoding());
4474 emit_int8((unsigned char)(0xB8 | encode));
4475 emit_data((int)imm32, rspec, 0);
4476 }
4477
4478 void Assembler::popa() { // 32bit
4479 emit_int8(0x61);
4480 }
4481
4482 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4483 InstructionMark im(this);
4484 emit_int8(0x68);
4485 emit_data(imm32, rspec, 0);
4486 }
4487
4488 void Assembler::pusha() { // 32bit
4489 emit_int8(0x60);
4490 }
4491
4492 void Assembler::set_byte_if_not_zero(Register dst) {
4493 emit_int8(0x0F);
4494 emit_int8((unsigned char)0x95);
4495 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4496 }
4497
4498 void Assembler::shldl(Register dst, Register src) {
4499 emit_int8(0x0F);
4500 emit_int8((unsigned char)0xA5);
4501 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4502 }
4503
4504 void Assembler::shrdl(Register dst, Register src) {
4505 emit_int8(0x0F);
4506 emit_int8((unsigned char)0xAD);
4507 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4508 }
4509
4510 #else // LP64
4511
4512 void Assembler::set_byte_if_not_zero(Register dst) {
4513 int enc = prefix_and_encode(dst->encoding(), true);
4514 emit_int8(0x0F);
4515 emit_int8((unsigned char)0x95);
4516 emit_int8((unsigned char)(0xE0 | enc));
4517 }
4518
4519 // 64bit only pieces of the assembler
4520 // This should only be used by 64bit instructions that can use rip-relative
4521 // it cannot be used by instructions that want an immediate value.
4522
4523 bool Assembler::reachable(AddressLiteral adr) {
4524 int64_t disp;
4525 // None will force a 64bit literal to the code stream. Likely a placeholder
4526 // for something that will be patched later and we need to certain it will
4527 // always be reachable.
4528 if (adr.reloc() == relocInfo::none) {
4529 return false;
4530 }
4531 if (adr.reloc() == relocInfo::internal_word_type) {
4532 // This should be rip relative and easily reachable.
4533 return true;
4534 }
4535 if (adr.reloc() == relocInfo::virtual_call_type ||
4536 adr.reloc() == relocInfo::opt_virtual_call_type ||
4537 adr.reloc() == relocInfo::static_call_type ||
4538 adr.reloc() == relocInfo::static_stub_type ) {
4539 // This should be rip relative within the code cache and easily
4540 // reachable until we get huge code caches. (At which point
4541 // ic code is going to have issues).
4542 return true;
4543 }
4544 if (adr.reloc() != relocInfo::external_word_type &&
4545 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4546 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4547 adr.reloc() != relocInfo::runtime_call_type ) {
4548 return false;
4549 }
4550
4551 // Stress the correction code
4552 if (ForceUnreachable) {
4553 // Must be runtimecall reloc, see if it is in the codecache
4554 // Flipping stuff in the codecache to be unreachable causes issues
4555 // with things like inline caches where the additional instructions
4556 // are not handled.
4557 if (CodeCache::find_blob(adr._target) == NULL) {
4558 return false;
4559 }
4560 }
4561 // For external_word_type/runtime_call_type if it is reachable from where we
4562 // are now (possibly a temp buffer) and where we might end up
4563 // anywhere in the codeCache then we are always reachable.
4564 // This would have to change if we ever save/restore shared code
4565 // to be more pessimistic.
4566 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4567 if (!is_simm32(disp)) return false;
4568 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4569 if (!is_simm32(disp)) return false;
4570
4571 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4572
4573 // Because rip relative is a disp + address_of_next_instruction and we
4574 // don't know the value of address_of_next_instruction we apply a fudge factor
4575 // to make sure we will be ok no matter the size of the instruction we get placed into.
4576 // We don't have to fudge the checks above here because they are already worst case.
4577
4578 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4579 // + 4 because better safe than sorry.
4580 const int fudge = 12 + 4;
4581 if (disp < 0) {
4582 disp -= fudge;
4583 } else {
4584 disp += fudge;
4585 }
4586 return is_simm32(disp);
4587 }
4588
4589 // Check if the polling page is not reachable from the code cache using rip-relative
4590 // addressing.
4591 bool Assembler::is_polling_page_far() {
4592 intptr_t addr = (intptr_t)os::get_polling_page();
4593 return ForceUnreachable ||
4594 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4595 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4596 }
4597
4598 void Assembler::emit_data64(jlong data,
4599 relocInfo::relocType rtype,
4600 int format) {
4601 if (rtype == relocInfo::none) {
4602 emit_int64(data);
4603 } else {
4604 emit_data64(data, Relocation::spec_simple(rtype), format);
4605 }
4606 }
4607
4608 void Assembler::emit_data64(jlong data,
4609 RelocationHolder const& rspec,
4610 int format) {
4611 assert(imm_operand == 0, "default format must be immediate in this file");
4612 assert(imm_operand == format, "must be immediate");
4613 assert(inst_mark() != NULL, "must be inside InstructionMark");
4614 // Do not use AbstractAssembler::relocate, which is not intended for
4615 // embedded words. Instead, relocate to the enclosing instruction.
4616 code_section()->relocate(inst_mark(), rspec, format);
4617 #ifdef ASSERT
4618 check_relocation(rspec, format);
4619 #endif
4620 emit_int64(data);
4621 }
4622
4623 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4624 if (reg_enc >= 8) {
4625 prefix(REX_B);
4626 reg_enc -= 8;
4627 } else if (byteinst && reg_enc >= 4) {
4628 prefix(REX);
4629 }
4630 return reg_enc;
4631 }
4632
4633 int Assembler::prefixq_and_encode(int reg_enc) {
4634 if (reg_enc < 8) {
4635 prefix(REX_W);
4636 } else {
4637 prefix(REX_WB);
4638 reg_enc -= 8;
4639 }
4640 return reg_enc;
4641 }
4642
4643 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4644 if (dst_enc < 8) {
4645 if (src_enc >= 8) {
4646 prefix(REX_B);
4647 src_enc -= 8;
4648 } else if (byteinst && src_enc >= 4) {
4649 prefix(REX);
4650 }
4651 } else {
4652 if (src_enc < 8) {
4653 prefix(REX_R);
4654 } else {
4655 prefix(REX_RB);
4656 src_enc -= 8;
4657 }
4658 dst_enc -= 8;
4659 }
4660 return dst_enc << 3 | src_enc;
4661 }
4662
4663 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4664 if (dst_enc < 8) {
4665 if (src_enc < 8) {
4666 prefix(REX_W);
4667 } else {
4668 prefix(REX_WB);
4669 src_enc -= 8;
4670 }
4671 } else {
4672 if (src_enc < 8) {
4673 prefix(REX_WR);
4674 } else {
4675 prefix(REX_WRB);
4676 src_enc -= 8;
4677 }
4678 dst_enc -= 8;
4679 }
4680 return dst_enc << 3 | src_enc;
4681 }
4682
4683 void Assembler::prefix(Register reg) {
4684 if (reg->encoding() >= 8) {
4685 prefix(REX_B);
4686 }
4687 }
4688
4689 void Assembler::prefix(Address adr) {
4690 if (adr.base_needs_rex()) {
4691 if (adr.index_needs_rex()) {
4692 prefix(REX_XB);
4693 } else {
4694 prefix(REX_B);
4695 }
4696 } else {
4697 if (adr.index_needs_rex()) {
4698 prefix(REX_X);
4699 }
4700 }
4701 }
4702
4703 void Assembler::prefixq(Address adr) {
4704 if (adr.base_needs_rex()) {
4705 if (adr.index_needs_rex()) {
4706 prefix(REX_WXB);
4707 } else {
4708 prefix(REX_WB);
4709 }
4710 } else {
4711 if (adr.index_needs_rex()) {
4712 prefix(REX_WX);
4713 } else {
4714 prefix(REX_W);
4715 }
4716 }
4717 }
4718
4719
4720 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4721 if (reg->encoding() < 8) {
4722 if (adr.base_needs_rex()) {
4723 if (adr.index_needs_rex()) {
4724 prefix(REX_XB);
4725 } else {
4726 prefix(REX_B);
4727 }
4728 } else {
4729 if (adr.index_needs_rex()) {
4730 prefix(REX_X);
4731 } else if (byteinst && reg->encoding() >= 4 ) {
4732 prefix(REX);
4733 }
4734 }
4735 } else {
4736 if (adr.base_needs_rex()) {
4737 if (adr.index_needs_rex()) {
4738 prefix(REX_RXB);
4739 } else {
4740 prefix(REX_RB);
4741 }
4742 } else {
4743 if (adr.index_needs_rex()) {
4744 prefix(REX_RX);
4745 } else {
4746 prefix(REX_R);
4747 }
4748 }
4749 }
4750 }
4751
4752 void Assembler::prefixq(Address adr, Register src) {
4753 if (src->encoding() < 8) {
4754 if (adr.base_needs_rex()) {
4755 if (adr.index_needs_rex()) {
4756 prefix(REX_WXB);
4757 } else {
4758 prefix(REX_WB);
4759 }
4760 } else {
4761 if (adr.index_needs_rex()) {
4762 prefix(REX_WX);
4763 } else {
4764 prefix(REX_W);
4765 }
4766 }
4767 } else {
4768 if (adr.base_needs_rex()) {
4769 if (adr.index_needs_rex()) {
4770 prefix(REX_WRXB);
4771 } else {
4772 prefix(REX_WRB);
4773 }
4774 } else {
4775 if (adr.index_needs_rex()) {
4776 prefix(REX_WRX);
4777 } else {
4778 prefix(REX_WR);
4779 }
4780 }
4781 }
4782 }
4783
4784 void Assembler::prefix(Address adr, XMMRegister reg) {
4785 if (reg->encoding() < 8) {
4786 if (adr.base_needs_rex()) {
4787 if (adr.index_needs_rex()) {
4788 prefix(REX_XB);
4789 } else {
4790 prefix(REX_B);
4791 }
4792 } else {
4793 if (adr.index_needs_rex()) {
4794 prefix(REX_X);
4795 }
4796 }
4797 } else {
4798 if (adr.base_needs_rex()) {
4799 if (adr.index_needs_rex()) {
4800 prefix(REX_RXB);
4801 } else {
4802 prefix(REX_RB);
4803 }
4804 } else {
4805 if (adr.index_needs_rex()) {
4806 prefix(REX_RX);
4807 } else {
4808 prefix(REX_R);
4809 }
4810 }
4811 }
4812 }
4813
4814 void Assembler::prefixq(Address adr, XMMRegister src) {
4815 if (src->encoding() < 8) {
4816 if (adr.base_needs_rex()) {
4817 if (adr.index_needs_rex()) {
4818 prefix(REX_WXB);
4819 } else {
4820 prefix(REX_WB);
4821 }
4822 } else {
4823 if (adr.index_needs_rex()) {
4824 prefix(REX_WX);
4825 } else {
4826 prefix(REX_W);
4827 }
4828 }
4829 } else {
4830 if (adr.base_needs_rex()) {
4831 if (adr.index_needs_rex()) {
4832 prefix(REX_WRXB);
4833 } else {
4834 prefix(REX_WRB);
4835 }
4836 } else {
4837 if (adr.index_needs_rex()) {
4838 prefix(REX_WRX);
4839 } else {
4840 prefix(REX_WR);
4841 }
4842 }
4843 }
4844 }
4845
4846 void Assembler::adcq(Register dst, int32_t imm32) {
4847 (void) prefixq_and_encode(dst->encoding());
4848 emit_arith(0x81, 0xD0, dst, imm32);
4849 }
4850
4851 void Assembler::adcq(Register dst, Address src) {
4852 InstructionMark im(this);
4853 prefixq(src, dst);
4854 emit_int8(0x13);
4855 emit_operand(dst, src);
4856 }
4857
4858 void Assembler::adcq(Register dst, Register src) {
4859 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4860 emit_arith(0x13, 0xC0, dst, src);
4861 }
4862
4863 void Assembler::addq(Address dst, int32_t imm32) {
4864 InstructionMark im(this);
4865 prefixq(dst);
4866 emit_arith_operand(0x81, rax, dst,imm32);
4867 }
4868
4869 void Assembler::addq(Address dst, Register src) {
4870 InstructionMark im(this);
4871 prefixq(dst, src);
4872 emit_int8(0x01);
4873 emit_operand(src, dst);
4874 }
4875
4876 void Assembler::addq(Register dst, int32_t imm32) {
4877 (void) prefixq_and_encode(dst->encoding());
4878 emit_arith(0x81, 0xC0, dst, imm32);
4879 }
4880
4881 void Assembler::addq(Register dst, Address src) {
4882 InstructionMark im(this);
4883 prefixq(src, dst);
4884 emit_int8(0x03);
4885 emit_operand(dst, src);
4886 }
4887
4888 void Assembler::addq(Register dst, Register src) {
4889 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4890 emit_arith(0x03, 0xC0, dst, src);
4891 }
4892
4893 void Assembler::andq(Address dst, int32_t imm32) {
4894 InstructionMark im(this);
4895 prefixq(dst);
4896 emit_int8((unsigned char)0x81);
4897 emit_operand(rsp, dst, 4);
4898 emit_int32(imm32);
4899 }
4900
4901 void Assembler::andq(Register dst, int32_t imm32) {
4902 (void) prefixq_and_encode(dst->encoding());
4903 emit_arith(0x81, 0xE0, dst, imm32);
4904 }
4905
4906 void Assembler::andq(Register dst, Address src) {
4907 InstructionMark im(this);
4908 prefixq(src, dst);
4909 emit_int8(0x23);
4910 emit_operand(dst, src);
4911 }
4912
4913 void Assembler::andq(Register dst, Register src) {
4914 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4915 emit_arith(0x23, 0xC0, dst, src);
4916 }
4917
4918 void Assembler::andnq(Register dst, Register src1, Register src2) {
4919 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4920 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4921 emit_int8((unsigned char)0xF2);
4922 emit_int8((unsigned char)(0xC0 | encode));
4923 }
4924
4925 void Assembler::andnq(Register dst, Register src1, Address src2) {
4926 InstructionMark im(this);
4927 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4928 vex_prefix_0F38_q(dst, src1, src2);
4929 emit_int8((unsigned char)0xF2);
4930 emit_operand(dst, src2);
4931 }
4932
4933 void Assembler::bsfq(Register dst, Register src) {
4934 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4935 emit_int8(0x0F);
4936 emit_int8((unsigned char)0xBC);
4937 emit_int8((unsigned char)(0xC0 | encode));
4938 }
4939
4940 void Assembler::bsrq(Register dst, Register src) {
4941 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4942 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4943 emit_int8(0x0F);
4944 emit_int8((unsigned char)0xBD);
4945 emit_int8((unsigned char)(0xC0 | encode));
4946 }
4947
4948 void Assembler::bswapq(Register reg) {
4949 int encode = prefixq_and_encode(reg->encoding());
4950 emit_int8(0x0F);
4951 emit_int8((unsigned char)(0xC8 | encode));
4952 }
4953
4954 void Assembler::blsiq(Register dst, Register src) {
4955 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4956 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4957 emit_int8((unsigned char)0xF3);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 }
4960
4961 void Assembler::blsiq(Register dst, Address src) {
4962 InstructionMark im(this);
4963 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4964 vex_prefix_0F38_q(rbx, dst, src);
4965 emit_int8((unsigned char)0xF3);
4966 emit_operand(rbx, src);
4967 }
4968
4969 void Assembler::blsmskq(Register dst, Register src) {
4970 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4971 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
4972 emit_int8((unsigned char)0xF3);
4973 emit_int8((unsigned char)(0xC0 | encode));
4974 }
4975
4976 void Assembler::blsmskq(Register dst, Address src) {
4977 InstructionMark im(this);
4978 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4979 vex_prefix_0F38_q(rdx, dst, src);
4980 emit_int8((unsigned char)0xF3);
4981 emit_operand(rdx, src);
4982 }
4983
4984 void Assembler::blsrq(Register dst, Register src) {
4985 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4986 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
4987 emit_int8((unsigned char)0xF3);
4988 emit_int8((unsigned char)(0xC0 | encode));
4989 }
4990
4991 void Assembler::blsrq(Register dst, Address src) {
4992 InstructionMark im(this);
4993 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4994 vex_prefix_0F38_q(rcx, dst, src);
4995 emit_int8((unsigned char)0xF3);
4996 emit_operand(rcx, src);
4997 }
4998
4999 void Assembler::cdqq() {
5000 prefix(REX_W);
5001 emit_int8((unsigned char)0x99);
5002 }
5003
5004 void Assembler::clflush(Address adr) {
5005 prefix(adr);
5006 emit_int8(0x0F);
5007 emit_int8((unsigned char)0xAE);
5008 emit_operand(rdi, adr);
5009 }
5010
5011 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5012 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5013 emit_int8(0x0F);
5014 emit_int8(0x40 | cc);
5015 emit_int8((unsigned char)(0xC0 | encode));
5016 }
5017
5018 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5019 InstructionMark im(this);
5020 prefixq(src, dst);
5021 emit_int8(0x0F);
5022 emit_int8(0x40 | cc);
5023 emit_operand(dst, src);
5024 }
5025
5026 void Assembler::cmpq(Address dst, int32_t imm32) {
5027 InstructionMark im(this);
5028 prefixq(dst);
5029 emit_int8((unsigned char)0x81);
5030 emit_operand(rdi, dst, 4);
5031 emit_int32(imm32);
5032 }
5033
5034 void Assembler::cmpq(Register dst, int32_t imm32) {
5035 (void) prefixq_and_encode(dst->encoding());
5036 emit_arith(0x81, 0xF8, dst, imm32);
5037 }
5038
5039 void Assembler::cmpq(Address dst, Register src) {
5040 InstructionMark im(this);
5041 prefixq(dst, src);
5042 emit_int8(0x3B);
5043 emit_operand(src, dst);
5044 }
5045
5046 void Assembler::cmpq(Register dst, Register src) {
5047 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5048 emit_arith(0x3B, 0xC0, dst, src);
5049 }
5050
5051 void Assembler::cmpq(Register dst, Address src) {
5052 InstructionMark im(this);
5053 prefixq(src, dst);
5054 emit_int8(0x3B);
5055 emit_operand(dst, src);
5056 }
5057
5058 void Assembler::cmpxchgq(Register reg, Address adr) {
5059 InstructionMark im(this);
5060 prefixq(adr, reg);
5061 emit_int8(0x0F);
5062 emit_int8((unsigned char)0xB1);
5063 emit_operand(reg, adr);
5064 }
5065
5066 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5067 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5068 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5069 emit_int8(0x2A);
5070 emit_int8((unsigned char)(0xC0 | encode));
5071 }
5072
5073 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5074 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5075 InstructionMark im(this);
5076 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5077 emit_int8(0x2A);
5078 emit_operand(dst, src);
5079 }
5080
5081 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5082 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5083 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5084 emit_int8(0x2A);
5085 emit_int8((unsigned char)(0xC0 | encode));
5086 }
5087
5088 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5089 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5090 InstructionMark im(this);
5091 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5092 emit_int8(0x2A);
5093 emit_operand(dst, src);
5094 }
5095
5096 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5098 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5099 emit_int8(0x2C);
5100 emit_int8((unsigned char)(0xC0 | encode));
5101 }
5102
5103 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5104 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5105 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5106 emit_int8(0x2C);
5107 emit_int8((unsigned char)(0xC0 | encode));
5108 }
5109
5110 void Assembler::decl(Register dst) {
5111 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5112 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5113 int encode = prefix_and_encode(dst->encoding());
5114 emit_int8((unsigned char)0xFF);
5115 emit_int8((unsigned char)(0xC8 | encode));
5116 }
5117
5118 void Assembler::decq(Register dst) {
5119 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5120 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5121 int encode = prefixq_and_encode(dst->encoding());
5122 emit_int8((unsigned char)0xFF);
5123 emit_int8(0xC8 | encode);
5124 }
5125
5126 void Assembler::decq(Address dst) {
5127 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5128 InstructionMark im(this);
5129 prefixq(dst);
5130 emit_int8((unsigned char)0xFF);
5131 emit_operand(rcx, dst);
5132 }
5133
5134 void Assembler::fxrstor(Address src) {
5135 prefixq(src);
5136 emit_int8(0x0F);
5137 emit_int8((unsigned char)0xAE);
5138 emit_operand(as_Register(1), src);
5139 }
5140
5141 void Assembler::fxsave(Address dst) {
5142 prefixq(dst);
5143 emit_int8(0x0F);
5144 emit_int8((unsigned char)0xAE);
5145 emit_operand(as_Register(0), dst);
5146 }
5147
5148 void Assembler::idivq(Register src) {
5149 int encode = prefixq_and_encode(src->encoding());
5150 emit_int8((unsigned char)0xF7);
5151 emit_int8((unsigned char)(0xF8 | encode));
5152 }
5153
5154 void Assembler::imulq(Register dst, Register src) {
5155 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5156 emit_int8(0x0F);
5157 emit_int8((unsigned char)0xAF);
5158 emit_int8((unsigned char)(0xC0 | encode));
5159 }
5160
5161 void Assembler::imulq(Register dst, Register src, int value) {
5162 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5163 if (is8bit(value)) {
5164 emit_int8(0x6B);
5165 emit_int8((unsigned char)(0xC0 | encode));
5166 emit_int8(value & 0xFF);
5167 } else {
5168 emit_int8(0x69);
5169 emit_int8((unsigned char)(0xC0 | encode));
5170 emit_int32(value);
5171 }
5172 }
5173
5174 void Assembler::imulq(Register dst, Address src) {
5175 InstructionMark im(this);
5176 prefixq(src, dst);
5177 emit_int8(0x0F);
5178 emit_int8((unsigned char) 0xAF);
5179 emit_operand(dst, src);
5180 }
5181
5182 void Assembler::incl(Register dst) {
5183 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5184 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5185 int encode = prefix_and_encode(dst->encoding());
5186 emit_int8((unsigned char)0xFF);
5187 emit_int8((unsigned char)(0xC0 | encode));
5188 }
5189
5190 void Assembler::incq(Register dst) {
5191 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5192 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5193 int encode = prefixq_and_encode(dst->encoding());
5194 emit_int8((unsigned char)0xFF);
5195 emit_int8((unsigned char)(0xC0 | encode));
5196 }
5197
5198 void Assembler::incq(Address dst) {
5199 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5200 InstructionMark im(this);
5201 prefixq(dst);
5202 emit_int8((unsigned char)0xFF);
5203 emit_operand(rax, dst);
5204 }
5205
5206 void Assembler::lea(Register dst, Address src) {
5207 leaq(dst, src);
5208 }
5209
5210 void Assembler::leaq(Register dst, Address src) {
5211 InstructionMark im(this);
5212 prefixq(src, dst);
5213 emit_int8((unsigned char)0x8D);
5214 emit_operand(dst, src);
5215 }
5216
5217 void Assembler::mov64(Register dst, int64_t imm64) {
5218 InstructionMark im(this);
5219 int encode = prefixq_and_encode(dst->encoding());
5220 emit_int8((unsigned char)(0xB8 | encode));
5221 emit_int64(imm64);
5222 }
5223
5224 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5225 InstructionMark im(this);
5226 int encode = prefixq_and_encode(dst->encoding());
5227 emit_int8(0xB8 | encode);
5228 emit_data64(imm64, rspec);
5229 }
5230
5231 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5232 InstructionMark im(this);
5233 int encode = prefix_and_encode(dst->encoding());
5234 emit_int8((unsigned char)(0xB8 | encode));
5235 emit_data((int)imm32, rspec, narrow_oop_operand);
5236 }
5237
5238 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5239 InstructionMark im(this);
5240 prefix(dst);
5241 emit_int8((unsigned char)0xC7);
5242 emit_operand(rax, dst, 4);
5243 emit_data((int)imm32, rspec, narrow_oop_operand);
5244 }
5245
5246 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5247 InstructionMark im(this);
5248 int encode = prefix_and_encode(src1->encoding());
5249 emit_int8((unsigned char)0x81);
5250 emit_int8((unsigned char)(0xF8 | encode));
5251 emit_data((int)imm32, rspec, narrow_oop_operand);
5252 }
5253
5254 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5255 InstructionMark im(this);
5256 prefix(src1);
5257 emit_int8((unsigned char)0x81);
5258 emit_operand(rax, src1, 4);
5259 emit_data((int)imm32, rspec, narrow_oop_operand);
5260 }
5261
5262 void Assembler::lzcntq(Register dst, Register src) {
5263 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5264 emit_int8((unsigned char)0xF3);
5265 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5266 emit_int8(0x0F);
5267 emit_int8((unsigned char)0xBD);
5268 emit_int8((unsigned char)(0xC0 | encode));
5269 }
5270
5271 void Assembler::movdq(XMMRegister dst, Register src) {
5272 // table D-1 says MMX/SSE2
5273 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5274 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5275 emit_int8(0x6E);
5276 emit_int8((unsigned char)(0xC0 | encode));
5277 }
5278
5279 void Assembler::movdq(Register dst, XMMRegister src) {
5280 // table D-1 says MMX/SSE2
5281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5282 // swap src/dst to get correct prefix
5283 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5284 emit_int8(0x7E);
5285 emit_int8((unsigned char)(0xC0 | encode));
5286 }
5287
5288 void Assembler::movq(Register dst, Register src) {
5289 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5290 emit_int8((unsigned char)0x8B);
5291 emit_int8((unsigned char)(0xC0 | encode));
5292 }
5293
5294 void Assembler::movq(Register dst, Address src) {
5295 InstructionMark im(this);
5296 prefixq(src, dst);
5297 emit_int8((unsigned char)0x8B);
5298 emit_operand(dst, src);
5299 }
5300
5301 void Assembler::movq(Address dst, Register src) {
5302 InstructionMark im(this);
5303 prefixq(dst, src);
5304 emit_int8((unsigned char)0x89);
5305 emit_operand(src, dst);
5306 }
5307
5308 void Assembler::movsbq(Register dst, Address src) {
5309 InstructionMark im(this);
5310 prefixq(src, dst);
5311 emit_int8(0x0F);
5312 emit_int8((unsigned char)0xBE);
5313 emit_operand(dst, src);
5314 }
5315
5316 void Assembler::movsbq(Register dst, Register src) {
5317 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5318 emit_int8(0x0F);
5319 emit_int8((unsigned char)0xBE);
5320 emit_int8((unsigned char)(0xC0 | encode));
5321 }
5322
5323 void Assembler::movslq(Register dst, int32_t imm32) {
5324 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5325 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5326 // as a result we shouldn't use until tested at runtime...
5327 ShouldNotReachHere();
5328 InstructionMark im(this);
5329 int encode = prefixq_and_encode(dst->encoding());
5330 emit_int8((unsigned char)(0xC7 | encode));
5331 emit_int32(imm32);
5332 }
5333
5334 void Assembler::movslq(Address dst, int32_t imm32) {
5335 assert(is_simm32(imm32), "lost bits");
5336 InstructionMark im(this);
5337 prefixq(dst);
5338 emit_int8((unsigned char)0xC7);
5339 emit_operand(rax, dst, 4);
5340 emit_int32(imm32);
5341 }
5342
5343 void Assembler::movslq(Register dst, Address src) {
5344 InstructionMark im(this);
5345 prefixq(src, dst);
5346 emit_int8(0x63);
5347 emit_operand(dst, src);
5348 }
5349
5350 void Assembler::movslq(Register dst, Register src) {
5351 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5352 emit_int8(0x63);
5353 emit_int8((unsigned char)(0xC0 | encode));
5354 }
5355
5356 void Assembler::movswq(Register dst, Address src) {
5357 InstructionMark im(this);
5358 prefixq(src, dst);
5359 emit_int8(0x0F);
5360 emit_int8((unsigned char)0xBF);
5361 emit_operand(dst, src);
5362 }
5363
5364 void Assembler::movswq(Register dst, Register src) {
5365 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5366 emit_int8((unsigned char)0x0F);
5367 emit_int8((unsigned char)0xBF);
5368 emit_int8((unsigned char)(0xC0 | encode));
5369 }
5370
5371 void Assembler::movzbq(Register dst, Address src) {
5372 InstructionMark im(this);
5373 prefixq(src, dst);
5374 emit_int8((unsigned char)0x0F);
5375 emit_int8((unsigned char)0xB6);
5376 emit_operand(dst, src);
5377 }
5378
5379 void Assembler::movzbq(Register dst, Register src) {
5380 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5381 emit_int8(0x0F);
5382 emit_int8((unsigned char)0xB6);
5383 emit_int8(0xC0 | encode);
5384 }
5385
5386 void Assembler::movzwq(Register dst, Address src) {
5387 InstructionMark im(this);
5388 prefixq(src, dst);
5389 emit_int8((unsigned char)0x0F);
5390 emit_int8((unsigned char)0xB7);
5391 emit_operand(dst, src);
5392 }
5393
5394 void Assembler::movzwq(Register dst, Register src) {
5395 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5396 emit_int8((unsigned char)0x0F);
5397 emit_int8((unsigned char)0xB7);
5398 emit_int8((unsigned char)(0xC0 | encode));
5399 }
5400
5401 void Assembler::negq(Register dst) {
5402 int encode = prefixq_and_encode(dst->encoding());
5403 emit_int8((unsigned char)0xF7);
5404 emit_int8((unsigned char)(0xD8 | encode));
5405 }
5406
5407 void Assembler::notq(Register dst) {
5408 int encode = prefixq_and_encode(dst->encoding());
5409 emit_int8((unsigned char)0xF7);
5410 emit_int8((unsigned char)(0xD0 | encode));
5411 }
5412
5413 void Assembler::orq(Address dst, int32_t imm32) {
5414 InstructionMark im(this);
5415 prefixq(dst);
5416 emit_int8((unsigned char)0x81);
5417 emit_operand(rcx, dst, 4);
5418 emit_int32(imm32);
5419 }
5420
5421 void Assembler::orq(Register dst, int32_t imm32) {
5422 (void) prefixq_and_encode(dst->encoding());
5423 emit_arith(0x81, 0xC8, dst, imm32);
5424 }
5425
5426 void Assembler::orq(Register dst, Address src) {
5427 InstructionMark im(this);
5428 prefixq(src, dst);
5429 emit_int8(0x0B);
5430 emit_operand(dst, src);
5431 }
5432
5433 void Assembler::orq(Register dst, Register src) {
5434 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5435 emit_arith(0x0B, 0xC0, dst, src);
5436 }
5437
5438 void Assembler::popa() { // 64bit
5439 movq(r15, Address(rsp, 0));
5440 movq(r14, Address(rsp, wordSize));
5441 movq(r13, Address(rsp, 2 * wordSize));
5442 movq(r12, Address(rsp, 3 * wordSize));
5443 movq(r11, Address(rsp, 4 * wordSize));
5444 movq(r10, Address(rsp, 5 * wordSize));
5445 movq(r9, Address(rsp, 6 * wordSize));
5446 movq(r8, Address(rsp, 7 * wordSize));
5447 movq(rdi, Address(rsp, 8 * wordSize));
5448 movq(rsi, Address(rsp, 9 * wordSize));
5449 movq(rbp, Address(rsp, 10 * wordSize));
5450 // skip rsp
5451 movq(rbx, Address(rsp, 12 * wordSize));
5452 movq(rdx, Address(rsp, 13 * wordSize));
5453 movq(rcx, Address(rsp, 14 * wordSize));
5454 movq(rax, Address(rsp, 15 * wordSize));
5455
5456 addq(rsp, 16 * wordSize);
5457 }
5458
5459 void Assembler::popcntq(Register dst, Address src) {
5460 assert(VM_Version::supports_popcnt(), "must support");
5461 InstructionMark im(this);
5462 emit_int8((unsigned char)0xF3);
5463 prefixq(src, dst);
5464 emit_int8((unsigned char)0x0F);
5465 emit_int8((unsigned char)0xB8);
5466 emit_operand(dst, src);
5467 }
5468
5469 void Assembler::popcntq(Register dst, Register src) {
5470 assert(VM_Version::supports_popcnt(), "must support");
5471 emit_int8((unsigned char)0xF3);
5472 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5473 emit_int8((unsigned char)0x0F);
5474 emit_int8((unsigned char)0xB8);
5475 emit_int8((unsigned char)(0xC0 | encode));
5476 }
5477
5478 void Assembler::popq(Address dst) {
5479 InstructionMark im(this);
5480 prefixq(dst);
5481 emit_int8((unsigned char)0x8F);
5482 emit_operand(rax, dst);
5483 }
5484
5485 void Assembler::pusha() { // 64bit
5486 // we have to store original rsp. ABI says that 128 bytes
5487 // below rsp are local scratch.
5488 movq(Address(rsp, -5 * wordSize), rsp);
5489
5490 subq(rsp, 16 * wordSize);
5491
5492 movq(Address(rsp, 15 * wordSize), rax);
5493 movq(Address(rsp, 14 * wordSize), rcx);
5494 movq(Address(rsp, 13 * wordSize), rdx);
5495 movq(Address(rsp, 12 * wordSize), rbx);
5496 // skip rsp
5497 movq(Address(rsp, 10 * wordSize), rbp);
5498 movq(Address(rsp, 9 * wordSize), rsi);
5499 movq(Address(rsp, 8 * wordSize), rdi);
5500 movq(Address(rsp, 7 * wordSize), r8);
5501 movq(Address(rsp, 6 * wordSize), r9);
5502 movq(Address(rsp, 5 * wordSize), r10);
5503 movq(Address(rsp, 4 * wordSize), r11);
5504 movq(Address(rsp, 3 * wordSize), r12);
5505 movq(Address(rsp, 2 * wordSize), r13);
5506 movq(Address(rsp, wordSize), r14);
5507 movq(Address(rsp, 0), r15);
5508 }
5509
5510 void Assembler::pushq(Address src) {
5511 InstructionMark im(this);
5512 prefixq(src);
5513 emit_int8((unsigned char)0xFF);
5514 emit_operand(rsi, src);
5515 }
5516
5517 void Assembler::rclq(Register dst, int imm8) {
5518 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5519 int encode = prefixq_and_encode(dst->encoding());
5520 if (imm8 == 1) {
5521 emit_int8((unsigned char)0xD1);
5522 emit_int8((unsigned char)(0xD0 | encode));
5523 } else {
5524 emit_int8((unsigned char)0xC1);
5525 emit_int8((unsigned char)(0xD0 | encode));
5526 emit_int8(imm8);
5527 }
5528 }
5529 void Assembler::sarq(Register dst, int imm8) {
5530 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5531 int encode = prefixq_and_encode(dst->encoding());
5532 if (imm8 == 1) {
5533 emit_int8((unsigned char)0xD1);
5534 emit_int8((unsigned char)(0xF8 | encode));
5535 } else {
5536 emit_int8((unsigned char)0xC1);
5537 emit_int8((unsigned char)(0xF8 | encode));
5538 emit_int8(imm8);
5539 }
5540 }
5541
5542 void Assembler::sarq(Register dst) {
5543 int encode = prefixq_and_encode(dst->encoding());
5544 emit_int8((unsigned char)0xD3);
5545 emit_int8((unsigned char)(0xF8 | encode));
5546 }
5547
5548 void Assembler::sbbq(Address dst, int32_t imm32) {
5549 InstructionMark im(this);
5550 prefixq(dst);
5551 emit_arith_operand(0x81, rbx, dst, imm32);
5552 }
5553
5554 void Assembler::sbbq(Register dst, int32_t imm32) {
5555 (void) prefixq_and_encode(dst->encoding());
5556 emit_arith(0x81, 0xD8, dst, imm32);
5557 }
5558
5559 void Assembler::sbbq(Register dst, Address src) {
5560 InstructionMark im(this);
5561 prefixq(src, dst);
5562 emit_int8(0x1B);
5563 emit_operand(dst, src);
5564 }
5565
5566 void Assembler::sbbq(Register dst, Register src) {
5567 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5568 emit_arith(0x1B, 0xC0, dst, src);
5569 }
5570
5571 void Assembler::shlq(Register dst, int imm8) {
5572 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5573 int encode = prefixq_and_encode(dst->encoding());
5574 if (imm8 == 1) {
5575 emit_int8((unsigned char)0xD1);
5576 emit_int8((unsigned char)(0xE0 | encode));
5577 } else {
5578 emit_int8((unsigned char)0xC1);
5579 emit_int8((unsigned char)(0xE0 | encode));
5580 emit_int8(imm8);
5581 }
5582 }
5583
5584 void Assembler::shlq(Register dst) {
5585 int encode = prefixq_and_encode(dst->encoding());
5586 emit_int8((unsigned char)0xD3);
5587 emit_int8((unsigned char)(0xE0 | encode));
5588 }
5589
5590 void Assembler::shrq(Register dst, int imm8) {
5591 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5592 int encode = prefixq_and_encode(dst->encoding());
5593 emit_int8((unsigned char)0xC1);
5594 emit_int8((unsigned char)(0xE8 | encode));
5595 emit_int8(imm8);
5596 }
5597
5598 void Assembler::shrq(Register dst) {
5599 int encode = prefixq_and_encode(dst->encoding());
5600 emit_int8((unsigned char)0xD3);
5601 emit_int8(0xE8 | encode);
5602 }
5603
5604 void Assembler::subq(Address dst, int32_t imm32) {
5605 InstructionMark im(this);
5606 prefixq(dst);
5607 emit_arith_operand(0x81, rbp, dst, imm32);
5608 }
5609
5610 void Assembler::subq(Address dst, Register src) {
5611 InstructionMark im(this);
5612 prefixq(dst, src);
5613 emit_int8(0x29);
5614 emit_operand(src, dst);
5615 }
5616
5617 void Assembler::subq(Register dst, int32_t imm32) {
5618 (void) prefixq_and_encode(dst->encoding());
5619 emit_arith(0x81, 0xE8, dst, imm32);
5620 }
5621
5622 // Force generation of a 4 byte immediate value even if it fits into 8bit
5623 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5624 (void) prefixq_and_encode(dst->encoding());
5625 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5626 }
5627
5628 void Assembler::subq(Register dst, Address src) {
5629 InstructionMark im(this);
5630 prefixq(src, dst);
5631 emit_int8(0x2B);
5632 emit_operand(dst, src);
5633 }
5634
5635 void Assembler::subq(Register dst, Register src) {
5636 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5637 emit_arith(0x2B, 0xC0, dst, src);
5638 }
5639
5640 void Assembler::testq(Register dst, int32_t imm32) {
5641 // not using emit_arith because test
5642 // doesn't support sign-extension of
5643 // 8bit operands
5644 int encode = dst->encoding();
5645 if (encode == 0) {
5646 prefix(REX_W);
5647 emit_int8((unsigned char)0xA9);
5648 } else {
5649 encode = prefixq_and_encode(encode);
5650 emit_int8((unsigned char)0xF7);
5651 emit_int8((unsigned char)(0xC0 | encode));
5652 }
5653 emit_int32(imm32);
5654 }
5655
5656 void Assembler::testq(Register dst, Register src) {
5657 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5658 emit_arith(0x85, 0xC0, dst, src);
5659 }
5660
5661 void Assembler::xaddq(Address dst, Register src) {
5662 InstructionMark im(this);
5663 prefixq(dst, src);
5664 emit_int8(0x0F);
5665 emit_int8((unsigned char)0xC1);
5666 emit_operand(src, dst);
5667 }
5668
5669 void Assembler::xchgq(Register dst, Address src) {
5670 InstructionMark im(this);
5671 prefixq(src, dst);
5672 emit_int8((unsigned char)0x87);
5673 emit_operand(dst, src);
5674 }
5675
5676 void Assembler::xchgq(Register dst, Register src) {
5677 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5678 emit_int8((unsigned char)0x87);
5679 emit_int8((unsigned char)(0xc0 | encode));
5680 }
5681
5682 void Assembler::xorq(Register dst, Register src) {
5683 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5684 emit_arith(0x33, 0xC0, dst, src);
5685 }
5686
5687 void Assembler::xorq(Register dst, Address src) {
5688 InstructionMark im(this);
5689 prefixq(src, dst);
5690 emit_int8(0x33);
5691 emit_operand(dst, src);
5692 }
5693
5694 #endif // !LP64