1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::bsfl(Register dst, Register src) {
1093 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1094 emit_int8(0x0F);
1095 emit_int8((unsigned char)0xBC);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::bsrl(Register dst, Register src) {
1100 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1101 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1102 emit_int8(0x0F);
1103 emit_int8((unsigned char)0xBD);
1104 emit_int8((unsigned char)(0xC0 | encode));
1105 }
1106
1107 void Assembler::bswapl(Register reg) { // bswap
1108 int encode = prefix_and_encode(reg->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)(0xC8 | encode));
1111 }
1112
1113 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1114 // suspect disp32 is always good
1115 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1116
1117 if (L.is_bound()) {
1118 const int long_size = 5;
1119 int offs = (int)( target(L) - pc() );
1120 assert(offs <= 0, "assembler error");
1121 InstructionMark im(this);
1122 // 1110 1000 #32-bit disp
1123 emit_int8((unsigned char)0xE8);
1124 emit_data(offs - long_size, rtype, operand);
1125 } else {
1126 InstructionMark im(this);
1127 // 1110 1000 #32-bit disp
1128 L.add_patch_at(code(), locator());
1129
1130 emit_int8((unsigned char)0xE8);
1131 emit_data(int(0), rtype, operand);
1132 }
2861 } else {
2862 encode = prefix_and_encode(encode);
2863 emit_int8((unsigned char)0xF7);
2864 emit_int8((unsigned char)(0xC0 | encode));
2865 }
2866 emit_int32(imm32);
2867 }
2868
2869 void Assembler::testl(Register dst, Register src) {
2870 (void) prefix_and_encode(dst->encoding(), src->encoding());
2871 emit_arith(0x85, 0xC0, dst, src);
2872 }
2873
2874 void Assembler::testl(Register dst, Address src) {
2875 InstructionMark im(this);
2876 prefix(src, dst);
2877 emit_int8((unsigned char)0x85);
2878 emit_operand(dst, src);
2879 }
2880
2881 void Assembler::ucomisd(XMMRegister dst, Address src) {
2882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2883 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2884 }
2885
2886 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2887 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2888 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2889 }
2890
2891 void Assembler::ucomiss(XMMRegister dst, Address src) {
2892 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2893 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2894 }
2895
2896 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2897 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2898 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2899 }
2900
4820 emit_int32(imm32);
4821 }
4822
4823 void Assembler::andq(Register dst, int32_t imm32) {
4824 (void) prefixq_and_encode(dst->encoding());
4825 emit_arith(0x81, 0xE0, dst, imm32);
4826 }
4827
4828 void Assembler::andq(Register dst, Address src) {
4829 InstructionMark im(this);
4830 prefixq(src, dst);
4831 emit_int8(0x23);
4832 emit_operand(dst, src);
4833 }
4834
4835 void Assembler::andq(Register dst, Register src) {
4836 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4837 emit_arith(0x23, 0xC0, dst, src);
4838 }
4839
4840 void Assembler::bsfq(Register dst, Register src) {
4841 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4842 emit_int8(0x0F);
4843 emit_int8((unsigned char)0xBC);
4844 emit_int8((unsigned char)(0xC0 | encode));
4845 }
4846
4847 void Assembler::bsrq(Register dst, Register src) {
4848 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4849 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4850 emit_int8(0x0F);
4851 emit_int8((unsigned char)0xBD);
4852 emit_int8((unsigned char)(0xC0 | encode));
4853 }
4854
4855 void Assembler::bswapq(Register reg) {
4856 int encode = prefixq_and_encode(reg->encoding());
4857 emit_int8(0x0F);
4858 emit_int8((unsigned char)(0xC8 | encode));
4859 }
4860
4861 void Assembler::cdqq() {
4862 prefix(REX_W);
4863 emit_int8((unsigned char)0x99);
4864 }
4865
4866 void Assembler::clflush(Address adr) {
4867 prefix(adr);
4868 emit_int8(0x0F);
4869 emit_int8((unsigned char)0xAE);
4870 emit_operand(rdi, adr);
4871 }
4872
4873 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4874 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4875 emit_int8(0x0F);
4876 emit_int8(0x40 | cc);
4877 emit_int8((unsigned char)(0xC0 | encode));
4878 }
4879
4880 void Assembler::cmovq(Condition cc, Register dst, Address src) {
|
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1116 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1117 emit_int8(0x0F);
1118 emit_int8((unsigned char)0xBD);
1119 emit_int8((unsigned char)(0xC0 | encode));
1120 }
1121
1122 void Assembler::bswapl(Register reg) { // bswap
1123 int encode = prefix_and_encode(reg->encoding());
1124 emit_int8(0x0F);
1125 emit_int8((unsigned char)(0xC8 | encode));
1126 }
1127
1128 void Assembler::blsil(Register dst, Register src) {
1129 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1130 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1131 emit_int8((unsigned char)0xF3);
1132 emit_int8((unsigned char)(0xC0 | encode));
1133 }
1134
1135 void Assembler::blsil(Register dst, Address src) {
1136 InstructionMark im(this);
1137 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1138 vex_prefix_0F38(rbx, dst, src);
1139 emit_int8((unsigned char)0xF3);
1140 emit_operand(rbx, src);
1141 }
1142
1143 void Assembler::blsmskl(Register dst, Register src) {
1144 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1145 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1146 emit_int8((unsigned char)0xF3);
1147 emit_int8((unsigned char)(0xC0 | encode));
1148 }
1149
1150 void Assembler::blsmskl(Register dst, Address src) {
1151 InstructionMark im(this);
1152 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1153 vex_prefix_0F38(rdx, dst, src);
1154 emit_int8((unsigned char)0xF3);
1155 emit_operand(rdx, src);
1156 }
1157
1158 void Assembler::blsrl(Register dst, Register src) {
1159 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1160 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1161 emit_int8((unsigned char)0xF3);
1162 emit_int8((unsigned char)(0xC0 | encode));
1163 }
1164
1165 void Assembler::blsrl(Register dst, Address src) {
1166 InstructionMark im(this);
1167 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1168 vex_prefix_0F38(rcx, dst, src);
1169 emit_int8((unsigned char)0xF3);
1170 emit_operand(rcx, src);
1171 }
1172
1173 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1174 // suspect disp32 is always good
1175 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1176
1177 if (L.is_bound()) {
1178 const int long_size = 5;
1179 int offs = (int)( target(L) - pc() );
1180 assert(offs <= 0, "assembler error");
1181 InstructionMark im(this);
1182 // 1110 1000 #32-bit disp
1183 emit_int8((unsigned char)0xE8);
1184 emit_data(offs - long_size, rtype, operand);
1185 } else {
1186 InstructionMark im(this);
1187 // 1110 1000 #32-bit disp
1188 L.add_patch_at(code(), locator());
1189
1190 emit_int8((unsigned char)0xE8);
1191 emit_data(int(0), rtype, operand);
1192 }
2921 } else {
2922 encode = prefix_and_encode(encode);
2923 emit_int8((unsigned char)0xF7);
2924 emit_int8((unsigned char)(0xC0 | encode));
2925 }
2926 emit_int32(imm32);
2927 }
2928
2929 void Assembler::testl(Register dst, Register src) {
2930 (void) prefix_and_encode(dst->encoding(), src->encoding());
2931 emit_arith(0x85, 0xC0, dst, src);
2932 }
2933
2934 void Assembler::testl(Register dst, Address src) {
2935 InstructionMark im(this);
2936 prefix(src, dst);
2937 emit_int8((unsigned char)0x85);
2938 emit_operand(dst, src);
2939 }
2940
2941 void Assembler::tzcntl(Register dst, Register src) {
2942 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2943 emit_int8((unsigned char)0xF3);
2944 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2945 emit_int8(0x0F);
2946 emit_int8((unsigned char)0xBC);
2947 emit_int8((unsigned char)0xC0 | encode);
2948 }
2949
2950 void Assembler::tzcntq(Register dst, Register src) {
2951 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2952 emit_int8((unsigned char)0xF3);
2953 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2954 emit_int8(0x0F);
2955 emit_int8((unsigned char)0xBC);
2956 emit_int8((unsigned char)(0xC0 | encode));
2957 }
2958
2959 void Assembler::ucomisd(XMMRegister dst, Address src) {
2960 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2961 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2962 }
2963
2964 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2965 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2966 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2967 }
2968
2969 void Assembler::ucomiss(XMMRegister dst, Address src) {
2970 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2971 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2972 }
2973
2974 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2975 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2976 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2977 }
2978
4898 emit_int32(imm32);
4899 }
4900
4901 void Assembler::andq(Register dst, int32_t imm32) {
4902 (void) prefixq_and_encode(dst->encoding());
4903 emit_arith(0x81, 0xE0, dst, imm32);
4904 }
4905
4906 void Assembler::andq(Register dst, Address src) {
4907 InstructionMark im(this);
4908 prefixq(src, dst);
4909 emit_int8(0x23);
4910 emit_operand(dst, src);
4911 }
4912
4913 void Assembler::andq(Register dst, Register src) {
4914 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4915 emit_arith(0x23, 0xC0, dst, src);
4916 }
4917
4918 void Assembler::andnq(Register dst, Register src1, Register src2) {
4919 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4920 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4921 emit_int8((unsigned char)0xF2);
4922 emit_int8((unsigned char)(0xC0 | encode));
4923 }
4924
4925 void Assembler::andnq(Register dst, Register src1, Address src2) {
4926 InstructionMark im(this);
4927 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4928 vex_prefix_0F38_q(dst, src1, src2);
4929 emit_int8((unsigned char)0xF2);
4930 emit_operand(dst, src2);
4931 }
4932
4933 void Assembler::bsfq(Register dst, Register src) {
4934 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4935 emit_int8(0x0F);
4936 emit_int8((unsigned char)0xBC);
4937 emit_int8((unsigned char)(0xC0 | encode));
4938 }
4939
4940 void Assembler::bsrq(Register dst, Register src) {
4941 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4942 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4943 emit_int8(0x0F);
4944 emit_int8((unsigned char)0xBD);
4945 emit_int8((unsigned char)(0xC0 | encode));
4946 }
4947
4948 void Assembler::bswapq(Register reg) {
4949 int encode = prefixq_and_encode(reg->encoding());
4950 emit_int8(0x0F);
4951 emit_int8((unsigned char)(0xC8 | encode));
4952 }
4953
4954 void Assembler::blsiq(Register dst, Register src) {
4955 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4956 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4957 emit_int8((unsigned char)0xF3);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 }
4960
4961 void Assembler::blsiq(Register dst, Address src) {
4962 InstructionMark im(this);
4963 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4964 vex_prefix_0F38_q(rbx, dst, src);
4965 emit_int8((unsigned char)0xF3);
4966 emit_operand(rbx, src);
4967 }
4968
4969 void Assembler::blsmskq(Register dst, Register src) {
4970 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4971 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
4972 emit_int8((unsigned char)0xF3);
4973 emit_int8((unsigned char)(0xC0 | encode));
4974 }
4975
4976 void Assembler::blsmskq(Register dst, Address src) {
4977 InstructionMark im(this);
4978 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4979 vex_prefix_0F38_q(rdx, dst, src);
4980 emit_int8((unsigned char)0xF3);
4981 emit_operand(rdx, src);
4982 }
4983
4984 void Assembler::blsrq(Register dst, Register src) {
4985 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4986 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
4987 emit_int8((unsigned char)0xF3);
4988 emit_int8((unsigned char)(0xC0 | encode));
4989 }
4990
4991 void Assembler::blsrq(Register dst, Address src) {
4992 InstructionMark im(this);
4993 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4994 vex_prefix_0F38_q(rcx, dst, src);
4995 emit_int8((unsigned char)0xF3);
4996 emit_operand(rcx, src);
4997 }
4998
4999 void Assembler::cdqq() {
5000 prefix(REX_W);
5001 emit_int8((unsigned char)0x99);
5002 }
5003
5004 void Assembler::clflush(Address adr) {
5005 prefix(adr);
5006 emit_int8(0x0F);
5007 emit_int8((unsigned char)0xAE);
5008 emit_operand(rdi, adr);
5009 }
5010
5011 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5012 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5013 emit_int8(0x0F);
5014 emit_int8(0x40 | cc);
5015 emit_int8((unsigned char)(0xC0 | encode));
5016 }
5017
5018 void Assembler::cmovq(Condition cc, Register dst, Address src) {
|