6242 "jnz skip\n\t"
6243 "movl $dst, -1\n"
6244 "skip:\n\t"
6245 "negl $dst\n\t"
6246 "addl $dst, 63" %}
6247 ins_encode %{
6248 Register Rdst = $dst$$Register;
6249 Register Rsrc = $src$$Register;
6250 Label skip;
6251 __ bsrq(Rdst, Rsrc);
6252 __ jccb(Assembler::notZero, skip);
6253 __ movl(Rdst, -1);
6254 __ bind(skip);
6255 __ negl(Rdst);
6256 __ addl(Rdst, BitsPerLong - 1);
6257 %}
6258 ins_pipe(ialu_reg);
6259 %}
6260
6261 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6262 match(Set dst (CountTrailingZerosI src));
6263 effect(KILL cr);
6264
6265 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6266 "jnz done\n\t"
6267 "movl $dst, 32\n"
6268 "done:" %}
6269 ins_encode %{
6270 Register Rdst = $dst$$Register;
6271 Label done;
6272 __ bsfl(Rdst, $src$$Register);
6273 __ jccb(Assembler::notZero, done);
6274 __ movl(Rdst, BitsPerInt);
6275 __ bind(done);
6276 %}
6277 ins_pipe(ialu_reg);
6278 %}
6279
6280 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6281 match(Set dst (CountTrailingZerosL src));
6282 effect(KILL cr);
6283
6284 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6285 "jnz done\n\t"
6286 "movl $dst, 64\n"
6287 "done:" %}
6288 ins_encode %{
6289 Register Rdst = $dst$$Register;
6290 Label done;
6291 __ bsfq(Rdst, $src$$Register);
6292 __ jccb(Assembler::notZero, done);
6293 __ movl(Rdst, BitsPerLong);
6294 __ bind(done);
6295 %}
6296 ins_pipe(ialu_reg);
6297 %}
6298
6299
6300 //---------- Population Count Instructions -------------------------------------
9097 format %{ "andl $dst, $src\t# int" %}
9098 opcode(0x21); /* Opcode 21 /r */
9099 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9100 ins_pipe(ialu_mem_reg);
9101 %}
9102
9103 // And Memory with Immediate
9104 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9105 %{
9106 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9107 effect(KILL cr);
9108
9109 ins_cost(125);
9110 format %{ "andl $dst, $src\t# int" %}
9111 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9112 ins_encode(REX_mem(dst), OpcSE(src),
9113 RM_opc_mem(secondary, dst), Con8or32(src));
9114 ins_pipe(ialu_mem_imm);
9115 %}
9116
9117 // Or Instructions
9118 // Or Register with Register
9119 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9120 %{
9121 match(Set dst (OrI dst src));
9122 effect(KILL cr);
9123
9124 format %{ "orl $dst, $src\t# int" %}
9125 opcode(0x0B);
9126 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9127 ins_pipe(ialu_reg_reg);
9128 %}
9129
9130 // Or Register with Immediate
9131 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9132 %{
9133 match(Set dst (OrI dst src));
9134 effect(KILL cr);
9135
9136 format %{ "orl $dst, $src\t# int" %}
9328 format %{ "andq $dst, $src\t# long" %}
9329 opcode(0x21); /* Opcode 21 /r */
9330 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9331 ins_pipe(ialu_mem_reg);
9332 %}
9333
9334 // And Memory with Immediate
9335 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9336 %{
9337 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9338 effect(KILL cr);
9339
9340 ins_cost(125);
9341 format %{ "andq $dst, $src\t# long" %}
9342 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9343 ins_encode(REX_mem_wide(dst), OpcSE(src),
9344 RM_opc_mem(secondary, dst), Con8or32(src));
9345 ins_pipe(ialu_mem_imm);
9346 %}
9347
9348 // Or Instructions
9349 // Or Register with Register
9350 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9351 %{
9352 match(Set dst (OrL dst src));
9353 effect(KILL cr);
9354
9355 format %{ "orq $dst, $src\t# long" %}
9356 opcode(0x0B);
9357 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9358 ins_pipe(ialu_reg_reg);
9359 %}
9360
9361 // Use any_RegP to match R15 (TLS register) without spilling.
9362 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9363 match(Set dst (OrL dst (CastP2X src)));
9364 effect(KILL cr);
9365
9366 format %{ "orq $dst, $src\t# long" %}
9367 opcode(0x0B);
|
6242 "jnz skip\n\t"
6243 "movl $dst, -1\n"
6244 "skip:\n\t"
6245 "negl $dst\n\t"
6246 "addl $dst, 63" %}
6247 ins_encode %{
6248 Register Rdst = $dst$$Register;
6249 Register Rsrc = $src$$Register;
6250 Label skip;
6251 __ bsrq(Rdst, Rsrc);
6252 __ jccb(Assembler::notZero, skip);
6253 __ movl(Rdst, -1);
6254 __ bind(skip);
6255 __ negl(Rdst);
6256 __ addl(Rdst, BitsPerLong - 1);
6257 %}
6258 ins_pipe(ialu_reg);
6259 %}
6260
6261 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6262 predicate(UseCountTrailingZerosInstruction);
6263 match(Set dst (CountTrailingZerosI src));
6264 effect(KILL cr);
6265
6266 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6267 ins_encode %{
6268 __ tzcntl($dst$$Register, $src$$Register);
6269 %}
6270 ins_pipe(ialu_reg);
6271 %}
6272
6273 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6274 predicate(!UseCountTrailingZerosInstruction);
6275 match(Set dst (CountTrailingZerosI src));
6276 effect(KILL cr);
6277
6278 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6279 "jnz done\n\t"
6280 "movl $dst, 32\n"
6281 "done:" %}
6282 ins_encode %{
6283 Register Rdst = $dst$$Register;
6284 Label done;
6285 __ bsfl(Rdst, $src$$Register);
6286 __ jccb(Assembler::notZero, done);
6287 __ movl(Rdst, BitsPerInt);
6288 __ bind(done);
6289 %}
6290 ins_pipe(ialu_reg);
6291 %}
6292
6293 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6294 predicate(UseCountTrailingZerosInstruction);
6295 match(Set dst (CountTrailingZerosL src));
6296 effect(KILL cr);
6297
6298 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6299 ins_encode %{
6300 __ tzcntq($dst$$Register, $src$$Register);
6301 %}
6302 ins_pipe(ialu_reg);
6303 %}
6304
6305 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6306 predicate(!UseCountTrailingZerosInstruction);
6307 match(Set dst (CountTrailingZerosL src));
6308 effect(KILL cr);
6309
6310 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6311 "jnz done\n\t"
6312 "movl $dst, 64\n"
6313 "done:" %}
6314 ins_encode %{
6315 Register Rdst = $dst$$Register;
6316 Label done;
6317 __ bsfq(Rdst, $src$$Register);
6318 __ jccb(Assembler::notZero, done);
6319 __ movl(Rdst, BitsPerLong);
6320 __ bind(done);
6321 %}
6322 ins_pipe(ialu_reg);
6323 %}
6324
6325
6326 //---------- Population Count Instructions -------------------------------------
9123 format %{ "andl $dst, $src\t# int" %}
9124 opcode(0x21); /* Opcode 21 /r */
9125 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9126 ins_pipe(ialu_mem_reg);
9127 %}
9128
9129 // And Memory with Immediate
9130 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9131 %{
9132 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9133 effect(KILL cr);
9134
9135 ins_cost(125);
9136 format %{ "andl $dst, $src\t# int" %}
9137 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9138 ins_encode(REX_mem(dst), OpcSE(src),
9139 RM_opc_mem(secondary, dst), Con8or32(src));
9140 ins_pipe(ialu_mem_imm);
9141 %}
9142
9143 // BMI1 instructions
9144 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9145 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9146 predicate(UseBMI1Instructions);
9147 effect(KILL cr);
9148
9149 ins_cost(125);
9150 format %{ "andnl $dst, $src1, $src2" %}
9151
9152 ins_encode %{
9153 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9154 %}
9155 ins_pipe(ialu_reg_mem);
9156 %}
9157
9158 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9159 match(Set dst (AndI (XorI src1 minus_1) src2));
9160 predicate(UseBMI1Instructions);
9161 effect(KILL cr);
9162
9163 format %{ "andnl $dst, $src1, $src2" %}
9164
9165 ins_encode %{
9166 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9167 %}
9168 ins_pipe(ialu_reg);
9169 %}
9170
9171 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9172 match(Set dst (AndI (SubI imm_zero src) src));
9173 predicate(UseBMI1Instructions);
9174 effect(KILL cr);
9175
9176 format %{ "blsil $dst, $src" %}
9177
9178 ins_encode %{
9179 __ blsil($dst$$Register, $src$$Register);
9180 %}
9181 ins_pipe(ialu_reg);
9182 %}
9183
9184 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9185 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9186 predicate(UseBMI1Instructions);
9187 effect(KILL cr);
9188
9189 ins_cost(125);
9190 format %{ "blsil $dst, $src" %}
9191
9192 ins_encode %{
9193 __ blsil($dst$$Register, $src$$Address);
9194 %}
9195 ins_pipe(ialu_reg_mem);
9196 %}
9197
9198 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9199 %{
9200 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9201 predicate(UseBMI1Instructions);
9202 effect(KILL cr);
9203
9204 ins_cost(125);
9205 format %{ "blsmskl $dst, $src" %}
9206
9207 ins_encode %{
9208 __ blsmskl($dst$$Register, $src$$Address);
9209 %}
9210 ins_pipe(ialu_reg_mem);
9211 %}
9212
9213 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9214 %{
9215 match(Set dst (XorI (AddI src minus_1) src));
9216 predicate(UseBMI1Instructions);
9217 effect(KILL cr);
9218
9219 format %{ "blsmskl $dst, $src" %}
9220
9221 ins_encode %{
9222 __ blsmskl($dst$$Register, $src$$Register);
9223 %}
9224
9225 ins_pipe(ialu_reg);
9226 %}
9227
9228 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9229 %{
9230 match(Set dst (AndI (AddI src minus_1) src) );
9231 predicate(UseBMI1Instructions);
9232 effect(KILL cr);
9233
9234 format %{ "blsrl $dst, $src" %}
9235
9236 ins_encode %{
9237 __ blsrl($dst$$Register, $src$$Register);
9238 %}
9239
9240 ins_pipe(ialu_reg_mem);
9241 %}
9242
9243 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9244 %{
9245 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9246 predicate(UseBMI1Instructions);
9247 effect(KILL cr);
9248
9249 ins_cost(125);
9250 format %{ "blsrl $dst, $src" %}
9251
9252 ins_encode %{
9253 __ blsrl($dst$$Register, $src$$Address);
9254 %}
9255
9256 ins_pipe(ialu_reg);
9257 %}
9258
9259 // Or Instructions
9260 // Or Register with Register
9261 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9262 %{
9263 match(Set dst (OrI dst src));
9264 effect(KILL cr);
9265
9266 format %{ "orl $dst, $src\t# int" %}
9267 opcode(0x0B);
9268 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9269 ins_pipe(ialu_reg_reg);
9270 %}
9271
9272 // Or Register with Immediate
9273 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9274 %{
9275 match(Set dst (OrI dst src));
9276 effect(KILL cr);
9277
9278 format %{ "orl $dst, $src\t# int" %}
9470 format %{ "andq $dst, $src\t# long" %}
9471 opcode(0x21); /* Opcode 21 /r */
9472 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9473 ins_pipe(ialu_mem_reg);
9474 %}
9475
9476 // And Memory with Immediate
9477 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9478 %{
9479 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9480 effect(KILL cr);
9481
9482 ins_cost(125);
9483 format %{ "andq $dst, $src\t# long" %}
9484 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9485 ins_encode(REX_mem_wide(dst), OpcSE(src),
9486 RM_opc_mem(secondary, dst), Con8or32(src));
9487 ins_pipe(ialu_mem_imm);
9488 %}
9489
9490 // BMI1 instructions
9491 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9492 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9493 predicate(UseBMI1Instructions);
9494 effect(KILL cr);
9495
9496 ins_cost(125);
9497 format %{ "andnq $dst, $src1, $src2" %}
9498
9499 ins_encode %{
9500 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9501 %}
9502 ins_pipe(ialu_reg_mem);
9503 %}
9504
9505 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9506 match(Set dst (AndL (XorL src1 minus_1) src2));
9507 predicate(UseBMI1Instructions);
9508 effect(KILL cr);
9509
9510 format %{ "andnq $dst, $src1, $src2" %}
9511
9512 ins_encode %{
9513 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9514 %}
9515 ins_pipe(ialu_reg_mem);
9516 %}
9517
9518 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9519 match(Set dst (AndL (SubL imm_zero src) src));
9520 predicate(UseBMI1Instructions);
9521 effect(KILL cr);
9522
9523 format %{ "blsiq $dst, $src" %}
9524
9525 ins_encode %{
9526 __ blsiq($dst$$Register, $src$$Register);
9527 %}
9528 ins_pipe(ialu_reg);
9529 %}
9530
9531 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9532 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9533 predicate(UseBMI1Instructions);
9534 effect(KILL cr);
9535
9536 ins_cost(125);
9537 format %{ "blsiq $dst, $src" %}
9538
9539 ins_encode %{
9540 __ blsiq($dst$$Register, $src$$Address);
9541 %}
9542 ins_pipe(ialu_reg_mem);
9543 %}
9544
9545 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9546 %{
9547 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9548 predicate(UseBMI1Instructions);
9549 effect(KILL cr);
9550
9551 ins_cost(125);
9552 format %{ "blsmskq $dst, $src" %}
9553
9554 ins_encode %{
9555 __ blsmskq($dst$$Register, $src$$Address);
9556 %}
9557 ins_pipe(ialu_reg_mem);
9558 %}
9559
9560 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9561 %{
9562 match(Set dst (XorL (AddL src minus_1) src));
9563 predicate(UseBMI1Instructions);
9564 effect(KILL cr);
9565
9566 format %{ "blsmskq $dst, $src" %}
9567
9568 ins_encode %{
9569 __ blsmskq($dst$$Register, $src$$Register);
9570 %}
9571
9572 ins_pipe(ialu_reg);
9573 %}
9574
9575 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9576 %{
9577 match(Set dst (AndL (AddL src minus_1) src) );
9578 predicate(UseBMI1Instructions);
9579 effect(KILL cr);
9580
9581 format %{ "blsrq $dst, $src" %}
9582
9583 ins_encode %{
9584 __ blsrq($dst$$Register, $src$$Register);
9585 %}
9586
9587 ins_pipe(ialu_reg);
9588 %}
9589
9590 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9591 %{
9592 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9593 predicate(UseBMI1Instructions);
9594 effect(KILL cr);
9595
9596 ins_cost(125);
9597 format %{ "blsrq $dst, $src" %}
9598
9599 ins_encode %{
9600 __ blsrq($dst$$Register, $src$$Address);
9601 %}
9602
9603 ins_pipe(ialu_reg);
9604 %}
9605
9606 // Or Instructions
9607 // Or Register with Register
9608 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9609 %{
9610 match(Set dst (OrL dst src));
9611 effect(KILL cr);
9612
9613 format %{ "orq $dst, $src\t# long" %}
9614 opcode(0x0B);
9615 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9616 ins_pipe(ialu_reg_reg);
9617 %}
9618
9619 // Use any_RegP to match R15 (TLS register) without spilling.
9620 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9621 match(Set dst (OrL dst (CastP2X src)));
9622 effect(KILL cr);
9623
9624 format %{ "orq $dst, $src\t# long" %}
9625 opcode(0x0B);
|