1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
577
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
589
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
595
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
601
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
607
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
611
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
615
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
623
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
631
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
636
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
641
642
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
645
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
656
657
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
660
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
675
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
688
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
697
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
710
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
721
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
732
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
744
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
749
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
758
759
760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
762
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
773
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
780
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
797
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
809
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
830
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
865
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
905
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
911
912 uint index = src2_enc;
913 int disp = disp32;
914
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
923
924 // We should have a compiler bailout here rather than a guarantee.
925 // Better yet would be some mechanism to handle variable-size matches correctly.
926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
927
928 if( disp == 0 ) {
929 // use reg-reg form
930 // bit 13 is already zero
931 instr |= index;
932 } else {
933 // use reg-imm form
934 instr |= 0x00002000; // set bit 13 to one
935 instr |= disp & 0x1FFF;
936 }
937
938 cbuf.insts()->emit_int32(instr);
939
940 #ifdef ASSERT
941 {
942 MacroAssembler _masm(&cbuf);
943 if (is_verified_oop_base) {
944 __ verify_oop(reg_to_register_object(src1_enc));
945 }
946 if (is_verified_oop_store) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 if (tmp_enc != -1) {
950 __ mov(O7, reg_to_register_object(tmp_enc));
951 }
952 if (is_verified_oop_load) {
953 __ verify_oop(reg_to_register_object(dst_enc));
954 }
955 }
956 #endif
957 }
958
959 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
960 // The method which records debug information at every safepoint
961 // expects the call to be the first instruction in the snippet as
962 // it creates a PcDesc structure which tracks the offset of a call
963 // from the start of the codeBlob. This offset is computed as
964 // code_end() - code_begin() of the code which has been emitted
965 // so far.
966 // In this particular case we have skirted around the problem by
967 // putting the "mov" instruction in the delay slot but the problem
968 // may bite us again at some other point and a cleaner/generic
969 // solution using relocations would be needed.
970 MacroAssembler _masm(&cbuf);
971 __ set_inst_mark();
972
973 // We flush the current window just so that there is a valid stack copy
974 // the fact that the current window becomes active again instantly is
975 // not a problem there is nothing live in it.
976
977 #ifdef ASSERT
978 int startpos = __ offset();
979 #endif /* ASSERT */
980
981 __ call((address)entry_point, rtype);
982
983 if (preserve_g2) __ delayed()->mov(G2, L7);
984 else __ delayed()->nop();
985
986 if (preserve_g2) __ mov(L7, G2);
987
988 #ifdef ASSERT
989 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
990 #ifdef _LP64
991 // Trash argument dump slots.
992 __ set(0xb0b8ac0db0b8ac0d, G1);
993 __ mov(G1, G5);
994 __ stx(G1, SP, STACK_BIAS + 0x80);
995 __ stx(G1, SP, STACK_BIAS + 0x88);
996 __ stx(G1, SP, STACK_BIAS + 0x90);
997 __ stx(G1, SP, STACK_BIAS + 0x98);
998 __ stx(G1, SP, STACK_BIAS + 0xA0);
999 __ stx(G1, SP, STACK_BIAS + 0xA8);
1000 #else // _LP64
1001 // this is also a native call, so smash the first 7 stack locations,
1002 // and the various registers
1003
1004 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1005 // while [SP+0x44..0x58] are the argument dump slots.
1006 __ set((intptr_t)0xbaadf00d, G1);
1007 __ mov(G1, G5);
1008 __ sllx(G1, 32, G1);
1009 __ or3(G1, G5, G1);
1010 __ mov(G1, G5);
1011 __ stx(G1, SP, 0x40);
1012 __ stx(G1, SP, 0x48);
1013 __ stx(G1, SP, 0x50);
1014 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1015 #endif // _LP64
1016 }
1017 #endif /*ASSERT*/
1018 }
1019
1020 //=============================================================================
1021 // REQUIRED FUNCTIONALITY for encoding
1022 void emit_lo(CodeBuffer &cbuf, int val) { }
1023 void emit_hi(CodeBuffer &cbuf, int val) { }
1024
1025
1026 //=============================================================================
1027 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1028
1029 int Compile::ConstantTable::calculate_table_base_offset() const {
1030 if (UseRDPCForConstantTableBase) {
1031 // The table base offset might be less but then it fits into
1032 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1033 return Assembler::min_simm13();
1034 } else {
1035 int offset = -(size() / 2);
1036 if (!Assembler::is_simm13(offset)) {
1037 offset = Assembler::min_simm13();
1038 }
1039 return offset;
1040 }
1041 }
1042
1043 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1044 Compile* C = ra_->C;
1045 Compile::ConstantTable& constant_table = C->constant_table();
1046 MacroAssembler _masm(&cbuf);
1047
1048 Register r = as_Register(ra_->get_encode(this));
1049 CodeSection* consts_section = __ code()->consts();
1050 int consts_size = consts_section->align_at_start(consts_section->size());
1051 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1052
1053 if (UseRDPCForConstantTableBase) {
1054 // For the following RDPC logic to work correctly the consts
1055 // section must be allocated right before the insts section. This
1056 // assert checks for that. The layout and the SECT_* constants
1057 // are defined in src/share/vm/asm/codeBuffer.hpp.
1058 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1059 int insts_offset = __ offset();
1060
1061 // Layout:
1062 //
1063 // |----------- consts section ------------|----------- insts section -----------...
1064 // |------ constant table -----|- padding -|------------------x----
1065 // \ current PC (RDPC instruction)
1066 // |<------------- consts_size ----------->|<- insts_offset ->|
1067 // \ table base
1068 // The table base offset is later added to the load displacement
1069 // so it has to be negative.
1070 int table_base_offset = -(consts_size + insts_offset);
1071 int disp;
1072
1073 // If the displacement from the current PC to the constant table
1074 // base fits into simm13 we set the constant table base to the
1075 // current PC.
1076 if (Assembler::is_simm13(table_base_offset)) {
1077 constant_table.set_table_base_offset(table_base_offset);
1078 disp = 0;
1079 } else {
1080 // Otherwise we set the constant table base offset to the
1081 // maximum negative displacement of load instructions to keep
1082 // the disp as small as possible:
1083 //
1084 // |<------------- consts_size ----------->|<- insts_offset ->|
1085 // |<--------- min_simm13 --------->|<-------- disp --------->|
1086 // \ table base
1087 table_base_offset = Assembler::min_simm13();
1088 constant_table.set_table_base_offset(table_base_offset);
1089 disp = (consts_size + insts_offset) + table_base_offset;
1090 }
1091
1092 __ rdpc(r);
1093
1094 if (disp != 0) {
1095 assert(r != O7, "need temporary");
1096 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1097 }
1098 }
1099 else {
1100 // Materialize the constant table base.
1101 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1102 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1103 AddressLiteral base(baseaddr, rspec);
1104 __ set(base, r);
1105 }
1106 }
1107
1108 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1109 if (UseRDPCForConstantTableBase) {
1110 // This is really the worst case but generally it's only 1 instruction.
1111 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1112 } else {
1113 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1114 }
1115 }
1116
1117 #ifndef PRODUCT
1118 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1119 char reg[128];
1120 ra_->dump_register(this, reg);
1121 if (UseRDPCForConstantTableBase) {
1122 st->print("RDPC %s\t! constant table base", reg);
1123 } else {
1124 st->print("SET &constanttable,%s\t! constant table base", reg);
1125 }
1126 }
1127 #endif
1128
1129
1130 //=============================================================================
1131
1132 #ifndef PRODUCT
1133 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1134 Compile* C = ra_->C;
1135
1136 for (int i = 0; i < OptoPrologueNops; i++) {
1137 st->print_cr("NOP"); st->print("\t");
1138 }
1139
1140 if( VerifyThread ) {
1141 st->print_cr("Verify_Thread"); st->print("\t");
1142 }
1143
1144 size_t framesize = C->frame_slots() << LogBytesPerInt;
1145
1146 // Calls to C2R adapters often do not accept exceptional returns.
1147 // We require that their callers must bang for them. But be careful, because
1148 // some VM calls (such as call site linkage) can use several kilobytes of
1149 // stack. But the stack safety zone should account for that.
1150 // See bugs 4446381, 4468289, 4497237.
1151 if (C->need_stack_bang(framesize)) {
1152 st->print_cr("! stack bang"); st->print("\t");
1153 }
1154
1155 if (Assembler::is_simm13(-framesize)) {
1156 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1157 } else {
1158 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1159 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1160 st->print ("SAVE R_SP,R_G3,R_SP");
1161 }
1162
1163 }
1164 #endif
1165
1166 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1167 Compile* C = ra_->C;
1168 MacroAssembler _masm(&cbuf);
1169
1170 for (int i = 0; i < OptoPrologueNops; i++) {
1171 __ nop();
1172 }
1173
1174 __ verify_thread();
1175
1176 size_t framesize = C->frame_slots() << LogBytesPerInt;
1177 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1178 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1179
1180 // Calls to C2R adapters often do not accept exceptional returns.
1181 // We require that their callers must bang for them. But be careful, because
1182 // some VM calls (such as call site linkage) can use several kilobytes of
1183 // stack. But the stack safety zone should account for that.
1184 // See bugs 4446381, 4468289, 4497237.
1185 if (C->need_stack_bang(framesize)) {
1186 __ generate_stack_overflow_check(framesize);
1187 }
1188
1189 if (Assembler::is_simm13(-framesize)) {
1190 __ save(SP, -framesize, SP);
1191 } else {
1192 __ sethi(-framesize & ~0x3ff, G3);
1193 __ add(G3, -framesize & 0x3ff, G3);
1194 __ save(SP, G3, SP);
1195 }
1196 C->set_frame_complete( __ offset() );
1197
1198 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1199 // NOTE: We set the table base offset here because users might be
1200 // emitted before MachConstantBaseNode.
1201 Compile::ConstantTable& constant_table = C->constant_table();
1202 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1203 }
1204 }
1205
1206 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1207 return MachNode::size(ra_);
1208 }
1209
1210 int MachPrologNode::reloc() const {
1211 return 10; // a large enough number
1212 }
1213
1214 //=============================================================================
1215 #ifndef PRODUCT
1216 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1217 Compile* C = ra_->C;
1218
1219 if( do_polling() && ra_->C->is_method_compilation() ) {
1220 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1221 #ifdef _LP64
1222 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1223 #else
1224 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1225 #endif
1226 }
1227
1228 if( do_polling() )
1229 st->print("RET\n\t");
1230
1231 st->print("RESTORE");
1232 }
1233 #endif
1234
1235 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1236 MacroAssembler _masm(&cbuf);
1237 Compile* C = ra_->C;
1238
1239 __ verify_thread();
1240
1241 // If this does safepoint polling, then do it here
1242 if( do_polling() && ra_->C->is_method_compilation() ) {
1243 AddressLiteral polling_page(os::get_polling_page());
1244 __ sethi(polling_page, L0);
1245 __ relocate(relocInfo::poll_return_type);
1246 __ ld_ptr( L0, 0, G0 );
1247 }
1248
1249 // If this is a return, then stuff the restore in the delay slot
1250 if( do_polling() ) {
1251 __ ret();
1252 __ delayed()->restore();
1253 } else {
1254 __ restore();
1255 }
1256 }
1257
1258 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachEpilogNode::reloc() const {
1263 return 16; // a large enough number
1264 }
1265
1266 const Pipeline * MachEpilogNode::pipeline() const {
1267 return MachNode::pipeline_class();
1268 }
1269
1270 int MachEpilogNode::safepoint_offset() const {
1271 assert( do_polling(), "no return for this epilog node");
1272 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1273 }
1274
1275 //=============================================================================
1276
1277 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1278 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1279 static enum RC rc_class( OptoReg::Name reg ) {
1280 if( !OptoReg::is_valid(reg) ) return rc_bad;
1281 if (OptoReg::is_stack(reg)) return rc_stack;
1282 VMReg r = OptoReg::as_VMReg(reg);
1283 if (r->is_Register()) return rc_int;
1284 assert(r->is_FloatRegister(), "must be");
1285 return rc_float;
1286 }
1287
1288 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1289 if (cbuf) {
1290 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1291 }
1292 #ifndef PRODUCT
1293 else if (!do_size) {
1294 if (size != 0) st->print("\n\t");
1295 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1296 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1297 }
1298 #endif
1299 return size+4;
1300 }
1301
1302 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1303 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1304 #ifndef PRODUCT
1305 else if( !do_size ) {
1306 if( size != 0 ) st->print("\n\t");
1307 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1308 }
1309 #endif
1310 return size+4;
1311 }
1312
1313 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1314 PhaseRegAlloc *ra_,
1315 bool do_size,
1316 outputStream* st ) const {
1317 // Get registers to move
1318 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1319 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1320 OptoReg::Name dst_second = ra_->get_reg_second(this );
1321 OptoReg::Name dst_first = ra_->get_reg_first(this );
1322
1323 enum RC src_second_rc = rc_class(src_second);
1324 enum RC src_first_rc = rc_class(src_first);
1325 enum RC dst_second_rc = rc_class(dst_second);
1326 enum RC dst_first_rc = rc_class(dst_first);
1327
1328 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1329
1330 // Generate spill code!
1331 int size = 0;
1332
1333 if( src_first == dst_first && src_second == dst_second )
1334 return size; // Self copy, no move
1335
1336 // --------------------------------------
1337 // Check for mem-mem move. Load into unused float registers and fall into
1338 // the float-store case.
1339 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1340 int offset = ra_->reg2offset(src_first);
1341 // Further check for aligned-adjacent pair, so we can use a double load
1342 if( (src_first&1)==0 && src_first+1 == src_second ) {
1343 src_second = OptoReg::Name(R_F31_num);
1344 src_second_rc = rc_float;
1345 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1346 } else {
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1348 }
1349 src_first = OptoReg::Name(R_F30_num);
1350 src_first_rc = rc_float;
1351 }
1352
1353 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1354 int offset = ra_->reg2offset(src_second);
1355 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1356 src_second = OptoReg::Name(R_F31_num);
1357 src_second_rc = rc_float;
1358 }
1359
1360 // --------------------------------------
1361 // Check for float->int copy; requires a trip through memory
1362 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1363 int offset = frame::register_save_words*wordSize;
1364 if (cbuf) {
1365 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1366 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1367 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1368 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1369 }
1370 #ifndef PRODUCT
1371 else if (!do_size) {
1372 if (size != 0) st->print("\n\t");
1373 st->print( "SUB R_SP,16,R_SP\n");
1374 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1375 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1376 st->print("\tADD R_SP,16,R_SP\n");
1377 }
1378 #endif
1379 size += 16;
1380 }
1381
1382 // Check for float->int copy on T4
1383 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1384 // Further check for aligned-adjacent pair, so we can use a double move
1385 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1386 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1387 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1388 }
1389 // Check for int->float copy on T4
1390 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1391 // Further check for aligned-adjacent pair, so we can use a double move
1392 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1393 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1394 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1395 }
1396
1397 // --------------------------------------
1398 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1399 // In such cases, I have to do the big-endian swap. For aligned targets, the
1400 // hardware does the flop for me. Doubles are always aligned, so no problem
1401 // there. Misaligned sources only come from native-long-returns (handled
1402 // special below).
1403 #ifndef _LP64
1404 if( src_first_rc == rc_int && // source is already big-endian
1405 src_second_rc != rc_bad && // 64-bit move
1406 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1407 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1408 // Do the big-endian flop.
1409 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1410 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1411 }
1412 #endif
1413
1414 // --------------------------------------
1415 // Check for integer reg-reg copy
1416 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1417 #ifndef _LP64
1418 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1419 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1420 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1421 // operand contains the least significant word of the 64-bit value and vice versa.
1422 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1423 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1424 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1425 if( cbuf ) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1427 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1428 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1429 #ifndef PRODUCT
1430 } else if( !do_size ) {
1431 if( size != 0 ) st->print("\n\t");
1432 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1433 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1434 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1435 #endif
1436 }
1437 return size+12;
1438 }
1439 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1440 // returning a long value in I0/I1
1441 // a SpillCopy must be able to target a return instruction's reg_class
1442 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1443 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1444 // operand contains the least significant word of the 64-bit value and vice versa.
1445 OptoReg::Name tdest = dst_first;
1446
1447 if (src_first == dst_first) {
1448 tdest = OptoReg::Name(R_O7_num);
1449 size += 4;
1450 }
1451
1452 if( cbuf ) {
1453 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1454 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1455 // ShrL_reg_imm6
1456 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1457 // ShrR_reg_imm6 src, 0, dst
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1459 if (tdest != dst_first) {
1460 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1461 }
1462 }
1463 #ifndef PRODUCT
1464 else if( !do_size ) {
1465 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1466 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1467 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1468 if (tdest != dst_first) {
1469 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1470 }
1471 }
1472 #endif // PRODUCT
1473 return size+8;
1474 }
1475 #endif // !_LP64
1476 // Else normal reg-reg copy
1477 assert( src_second != dst_first, "smashed second before evacuating it" );
1478 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1479 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1480 // This moves an aligned adjacent pair.
1481 // See if we are done.
1482 if( src_first+1 == src_second && dst_first+1 == dst_second )
1483 return size;
1484 }
1485
1486 // Check for integer store
1487 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1488 int offset = ra_->reg2offset(dst_first);
1489 // Further check for aligned-adjacent pair, so we can use a double store
1490 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1491 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1492 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1493 }
1494
1495 // Check for integer load
1496 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1497 int offset = ra_->reg2offset(src_first);
1498 // Further check for aligned-adjacent pair, so we can use a double load
1499 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1500 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1501 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1502 }
1503
1504 // Check for float reg-reg copy
1505 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1506 // Further check for aligned-adjacent pair, so we can use a double move
1507 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1508 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1509 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1510 }
1511
1512 // Check for float store
1513 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1514 int offset = ra_->reg2offset(dst_first);
1515 // Further check for aligned-adjacent pair, so we can use a double store
1516 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1517 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1518 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1519 }
1520
1521 // Check for float load
1522 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1523 int offset = ra_->reg2offset(src_first);
1524 // Further check for aligned-adjacent pair, so we can use a double load
1525 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1526 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1527 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1528 }
1529
1530 // --------------------------------------------------------------------
1531 // Check for hi bits still needing moving. Only happens for misaligned
1532 // arguments to native calls.
1533 if( src_second == dst_second )
1534 return size; // Self copy; no move
1535 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1536
1537 #ifndef _LP64
1538 // In the LP64 build, all registers can be moved as aligned/adjacent
1539 // pairs, so there's never any need to move the high bits separately.
1540 // The 32-bit builds have to deal with the 32-bit ABI which can force
1541 // all sorts of silly alignment problems.
1542
1543 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1544 // 32-bits of a 64-bit register, but are needed in low bits of another
1545 // register (else it's a hi-bits-to-hi-bits copy which should have
1546 // happened already as part of a 64-bit move)
1547 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1548 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1549 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1550 // Shift src_second down to dst_second's low bits.
1551 if( cbuf ) {
1552 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1553 #ifndef PRODUCT
1554 } else if( !do_size ) {
1555 if( size != 0 ) st->print("\n\t");
1556 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1557 #endif
1558 }
1559 return size+4;
1560 }
1561
1562 // Check for high word integer store. Must down-shift the hi bits
1563 // into a temp register, then fall into the case of storing int bits.
1564 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1565 // Shift src_second down to dst_second's low bits.
1566 if( cbuf ) {
1567 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1568 #ifndef PRODUCT
1569 } else if( !do_size ) {
1570 if( size != 0 ) st->print("\n\t");
1571 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1572 #endif
1573 }
1574 size+=4;
1575 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1576 }
1577
1578 // Check for high word integer load
1579 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1580 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1581
1582 // Check for high word integer store
1583 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1584 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1585
1586 // Check for high word float store
1587 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1588 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1589
1590 #endif // !_LP64
1591
1592 Unimplemented();
1593 }
1594
1595 #ifndef PRODUCT
1596 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1597 implementation( NULL, ra_, false, st );
1598 }
1599 #endif
1600
1601 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1602 implementation( &cbuf, ra_, false, NULL );
1603 }
1604
1605 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1606 return implementation( NULL, ra_, true, NULL );
1607 }
1608
1609 //=============================================================================
1610 #ifndef PRODUCT
1611 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1612 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1613 }
1614 #endif
1615
1616 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1617 MacroAssembler _masm(&cbuf);
1618 for(int i = 0; i < _count; i += 1) {
1619 __ nop();
1620 }
1621 }
1622
1623 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1624 return 4 * _count;
1625 }
1626
1627
1628 //=============================================================================
1629 #ifndef PRODUCT
1630 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1631 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1632 int reg = ra_->get_reg_first(this);
1633 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1634 }
1635 #endif
1636
1637 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1638 MacroAssembler _masm(&cbuf);
1639 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1640 int reg = ra_->get_encode(this);
1641
1642 if (Assembler::is_simm13(offset)) {
1643 __ add(SP, offset, reg_to_register_object(reg));
1644 } else {
1645 __ set(offset, O7);
1646 __ add(SP, O7, reg_to_register_object(reg));
1647 }
1648 }
1649
1650 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1651 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1652 assert(ra_ == ra_->C->regalloc(), "sanity");
1653 return ra_->C->scratch_emit_size(this);
1654 }
1655
1656 //=============================================================================
1657 #ifndef PRODUCT
1658 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1659 st->print_cr("\nUEP:");
1660 #ifdef _LP64
1661 if (UseCompressedClassPointers) {
1662 assert(Universe::heap() != NULL, "java heap should be initialized");
1663 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1664 if (Universe::narrow_klass_base() != 0) {
1665 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1666 if (Universe::narrow_klass_shift() != 0) {
1667 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1668 }
1669 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1670 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1671 } else {
1672 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1673 }
1674 } else {
1675 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1676 }
1677 st->print_cr("\tCMP R_G5,R_G3" );
1678 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1679 #else // _LP64
1680 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1681 st->print_cr("\tCMP R_G5,R_G3" );
1682 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1683 #endif // _LP64
1684 }
1685 #endif
1686
1687 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1688 MacroAssembler _masm(&cbuf);
1689 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1690 Register temp_reg = G3;
1691 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1692
1693 // Load klass from receiver
1694 __ load_klass(O0, temp_reg);
1695 // Compare against expected klass
1696 __ cmp(temp_reg, G5_ic_reg);
1697 // Branch to miss code, checks xcc or icc depending
1698 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1699 }
1700
1701 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1702 return MachNode::size(ra_);
1703 }
1704
1705
1706 //=============================================================================
1707
1708 uint size_exception_handler() {
1709 if (TraceJumps) {
1710 return (400); // just a guess
1711 }
1712 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1713 }
1714
1715 uint size_deopt_handler() {
1716 if (TraceJumps) {
1717 return (400); // just a guess
1718 }
1719 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1720 }
1721
1722 // Emit exception handler code.
1723 int emit_exception_handler(CodeBuffer& cbuf) {
1724 Register temp_reg = G3;
1725 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1726 MacroAssembler _masm(&cbuf);
1727
1728 address base =
1729 __ start_a_stub(size_exception_handler());
1730 if (base == NULL) return 0; // CodeBuffer::expand failed
1731
1732 int offset = __ offset();
1733
1734 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1735 __ delayed()->nop();
1736
1737 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1738
1739 __ end_a_stub();
1740
1741 return offset;
1742 }
1743
1744 int emit_deopt_handler(CodeBuffer& cbuf) {
1745 // Can't use any of the current frame's registers as we may have deopted
1746 // at a poll and everything (including G3) can be live.
1747 Register temp_reg = L0;
1748 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1749 MacroAssembler _masm(&cbuf);
1750
1751 address base =
1752 __ start_a_stub(size_deopt_handler());
1753 if (base == NULL) return 0; // CodeBuffer::expand failed
1754
1755 int offset = __ offset();
1756 __ save_frame(0);
1757 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1758 __ delayed()->restore();
1759
1760 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1761
1762 __ end_a_stub();
1763 return offset;
1764
1765 }
1766
1767 // Given a register encoding, produce a Integer Register object
1768 static Register reg_to_register_object(int register_encoding) {
1769 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1770 return as_Register(register_encoding);
1771 }
1772
1773 // Given a register encoding, produce a single-precision Float Register object
1774 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1775 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1776 return as_SingleFloatRegister(register_encoding);
1777 }
1778
1779 // Given a register encoding, produce a double-precision Float Register object
1780 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1781 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1782 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1783 return as_DoubleFloatRegister(register_encoding);
1784 }
1785
1786 const bool Matcher::match_rule_supported(int opcode) {
1787 if (!has_match_rule(opcode))
1788 return false;
1789
1790 switch (opcode) {
1791 case Op_CountLeadingZerosI:
1792 case Op_CountLeadingZerosL:
1793 case Op_CountTrailingZerosI:
1794 case Op_CountTrailingZerosL:
1795 case Op_PopCountI:
1796 case Op_PopCountL:
1797 if (!UsePopCountInstruction)
1798 return false;
1799 case Op_CompareAndSwapL:
1800 #ifdef _LP64
1801 case Op_CompareAndSwapP:
1802 #endif
1803 if (!VM_Version::supports_cx8())
1804 return false;
1805 break;
1806 }
1807
1808 return true; // Per default match rules are supported.
1809 }
1810
1811 int Matcher::regnum_to_fpu_offset(int regnum) {
1812 return regnum - 32; // The FP registers are in the second chunk
1813 }
1814
1815 #ifdef ASSERT
1816 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1817 #endif
1818
1819 // Vector width in bytes
1820 const int Matcher::vector_width_in_bytes(BasicType bt) {
1821 assert(MaxVectorSize == 8, "");
1822 return 8;
1823 }
1824
1825 // Vector ideal reg
1826 const int Matcher::vector_ideal_reg(int size) {
1827 assert(MaxVectorSize == 8, "");
1828 return Op_RegD;
1829 }
1830
1831 const int Matcher::vector_shift_count_ideal_reg(int size) {
1832 fatal("vector shift is not supported");
1833 return Node::NotAMachineReg;
1834 }
1835
1836 // Limits on vector size (number of elements) loaded into vector.
1837 const int Matcher::max_vector_size(const BasicType bt) {
1838 assert(is_java_primitive(bt), "only primitive type vectors");
1839 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1840 }
1841
1842 const int Matcher::min_vector_size(const BasicType bt) {
1843 return max_vector_size(bt); // Same as max.
1844 }
1845
1846 // SPARC doesn't support misaligned vectors store/load.
1847 const bool Matcher::misaligned_vectors_ok() {
1848 return false;
1849 }
1850
1851 // Current (2013) SPARC platforms need to read original key
1852 // to construct decryption expanded key
1853 const bool Matcher::pass_original_key_for_aes() {
1854 return true;
1855 }
1856
1857 // USII supports fxtof through the whole range of number, USIII doesn't
1858 const bool Matcher::convL2FSupported(void) {
1859 return VM_Version::has_fast_fxtof();
1860 }
1861
1862 // Is this branch offset short enough that a short branch can be used?
1863 //
1864 // NOTE: If the platform does not provide any short branch variants, then
1865 // this method should return false for offset 0.
1866 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1867 // The passed offset is relative to address of the branch.
1868 // Don't need to adjust the offset.
1869 return UseCBCond && Assembler::is_simm12(offset);
1870 }
1871
1872 const bool Matcher::isSimpleConstant64(jlong value) {
1873 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1874 // Depends on optimizations in MacroAssembler::setx.
1875 int hi = (int)(value >> 32);
1876 int lo = (int)(value & ~0);
1877 return (hi == 0) || (hi == -1) || (lo == 0);
1878 }
1879
1880 // No scaling for the parameter the ClearArray node.
1881 const bool Matcher::init_array_count_is_in_bytes = true;
1882
1883 // Threshold size for cleararray.
1884 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1885
1886 // No additional cost for CMOVL.
1887 const int Matcher::long_cmove_cost() { return 0; }
1888
1889 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1890 const int Matcher::float_cmove_cost() {
1891 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1892 }
1893
1894 // Should the Matcher clone shifts on addressing modes, expecting them to
1895 // be subsumed into complex addressing expressions or compute them into
1896 // registers? True for Intel but false for most RISCs
1897 const bool Matcher::clone_shift_expressions = false;
1898
1899 // Do we need to mask the count passed to shift instructions or does
1900 // the cpu only look at the lower 5/6 bits anyway?
1901 const bool Matcher::need_masked_shift_count = false;
1902
1903 bool Matcher::narrow_oop_use_complex_address() {
1904 NOT_LP64(ShouldNotCallThis());
1905 assert(UseCompressedOops, "only for compressed oops code");
1906 return false;
1907 }
1908
1909 bool Matcher::narrow_klass_use_complex_address() {
1910 NOT_LP64(ShouldNotCallThis());
1911 assert(UseCompressedClassPointers, "only for compressed klass code");
1912 return false;
1913 }
1914
1915 // Is it better to copy float constants, or load them directly from memory?
1916 // Intel can load a float constant from a direct address, requiring no
1917 // extra registers. Most RISCs will have to materialize an address into a
1918 // register first, so they would do better to copy the constant from stack.
1919 const bool Matcher::rematerialize_float_constants = false;
1920
1921 // If CPU can load and store mis-aligned doubles directly then no fixup is
1922 // needed. Else we split the double into 2 integer pieces and move it
1923 // piece-by-piece. Only happens when passing doubles into C code as the
1924 // Java calling convention forces doubles to be aligned.
1925 #ifdef _LP64
1926 const bool Matcher::misaligned_doubles_ok = true;
1927 #else
1928 const bool Matcher::misaligned_doubles_ok = false;
1929 #endif
1930
1931 // No-op on SPARC.
1932 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1933 }
1934
1935 // Advertise here if the CPU requires explicit rounding operations
1936 // to implement the UseStrictFP mode.
1937 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1938
1939 // Are floats conerted to double when stored to stack during deoptimization?
1940 // Sparc does not handle callee-save floats.
1941 bool Matcher::float_in_double() { return false; }
1942
1943 // Do ints take an entire long register or just half?
1944 // Note that we if-def off of _LP64.
1945 // The relevant question is how the int is callee-saved. In _LP64
1946 // the whole long is written but de-opt'ing will have to extract
1947 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1948 #ifdef _LP64
1949 const bool Matcher::int_in_long = true;
1950 #else
1951 const bool Matcher::int_in_long = false;
1952 #endif
1953
1954 // Return whether or not this register is ever used as an argument. This
1955 // function is used on startup to build the trampoline stubs in generateOptoStub.
1956 // Registers not mentioned will be killed by the VM call in the trampoline, and
1957 // arguments in those registers not be available to the callee.
1958 bool Matcher::can_be_java_arg( int reg ) {
1959 // Standard sparc 6 args in registers
1960 if( reg == R_I0_num ||
1961 reg == R_I1_num ||
1962 reg == R_I2_num ||
1963 reg == R_I3_num ||
1964 reg == R_I4_num ||
1965 reg == R_I5_num ) return true;
1966 #ifdef _LP64
1967 // 64-bit builds can pass 64-bit pointers and longs in
1968 // the high I registers
1969 if( reg == R_I0H_num ||
1970 reg == R_I1H_num ||
1971 reg == R_I2H_num ||
1972 reg == R_I3H_num ||
1973 reg == R_I4H_num ||
1974 reg == R_I5H_num ) return true;
1975
1976 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1977 return true;
1978 }
1979
1980 #else
1981 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1982 // Longs cannot be passed in O regs, because O regs become I regs
1983 // after a 'save' and I regs get their high bits chopped off on
1984 // interrupt.
1985 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1986 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1987 #endif
1988 // A few float args in registers
1989 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1990
1991 return false;
1992 }
1993
1994 bool Matcher::is_spillable_arg( int reg ) {
1995 return can_be_java_arg(reg);
1996 }
1997
1998 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1999 // Use hardware SDIVX instruction when it is
2000 // faster than a code which use multiply.
2001 return VM_Version::has_fast_idiv();
2002 }
2003
2004 // Register for DIVI projection of divmodI
2005 RegMask Matcher::divI_proj_mask() {
2006 ShouldNotReachHere();
2007 return RegMask();
2008 }
2009
2010 // Register for MODI projection of divmodI
2011 RegMask Matcher::modI_proj_mask() {
2012 ShouldNotReachHere();
2013 return RegMask();
2014 }
2015
2016 // Register for DIVL projection of divmodL
2017 RegMask Matcher::divL_proj_mask() {
2018 ShouldNotReachHere();
2019 return RegMask();
2020 }
2021
2022 // Register for MODL projection of divmodL
2023 RegMask Matcher::modL_proj_mask() {
2024 ShouldNotReachHere();
2025 return RegMask();
2026 }
2027
2028 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2029 return L7_REGP_mask();
2030 }
2031
2032 const RegMask Matcher::mathExactI_result_proj_mask() {
2033 return G1_REGI_mask();
2034 }
2035
2036 const RegMask Matcher::mathExactL_result_proj_mask() {
2037 return G1_REGL_mask();
2038 }
2039
2040 const RegMask Matcher::mathExactI_flags_proj_mask() {
2041 return INT_FLAGS_mask();
2042 }
2043
2044
2045 %}
2046
2047
2048 // The intptr_t operand types, defined by textual substitution.
2049 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2050 #ifdef _LP64
2051 #define immX immL
2052 #define immX13 immL13
2053 #define immX13m7 immL13m7
2054 #define iRegX iRegL
2055 #define g1RegX g1RegL
2056 #else
2057 #define immX immI
2058 #define immX13 immI13
2059 #define immX13m7 immI13m7
2060 #define iRegX iRegI
2061 #define g1RegX g1RegI
2062 #endif
2063
2064 //----------ENCODING BLOCK-----------------------------------------------------
2065 // This block specifies the encoding classes used by the compiler to output
2066 // byte streams. Encoding classes are parameterized macros used by
2067 // Machine Instruction Nodes in order to generate the bit encoding of the
2068 // instruction. Operands specify their base encoding interface with the
2069 // interface keyword. There are currently supported four interfaces,
2070 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2071 // operand to generate a function which returns its register number when
2072 // queried. CONST_INTER causes an operand to generate a function which
2073 // returns the value of the constant when queried. MEMORY_INTER causes an
2074 // operand to generate four functions which return the Base Register, the
2075 // Index Register, the Scale Value, and the Offset Value of the operand when
2076 // queried. COND_INTER causes an operand to generate six functions which
2077 // return the encoding code (ie - encoding bits for the instruction)
2078 // associated with each basic boolean condition for a conditional instruction.
2079 //
2080 // Instructions specify two basic values for encoding. Again, a function
2081 // is available to check if the constant displacement is an oop. They use the
2082 // ins_encode keyword to specify their encoding classes (which must be
2083 // a sequence of enc_class names, and their parameters, specified in
2084 // the encoding block), and they use the
2085 // opcode keyword to specify, in order, their primary, secondary, and
2086 // tertiary opcode. Only the opcode sections which a particular instruction
2087 // needs for encoding need to be specified.
2088 encode %{
2089 enc_class enc_untested %{
2090 #ifdef ASSERT
2091 MacroAssembler _masm(&cbuf);
2092 __ untested("encoding");
2093 #endif
2094 %}
2095
2096 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2097 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2098 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2099 %}
2100
2101 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2102 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2103 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2104 %}
2105
2106 enc_class form3_mem_prefetch_read( memory mem ) %{
2107 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2108 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2109 %}
2110
2111 enc_class form3_mem_prefetch_write( memory mem ) %{
2112 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2113 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2114 %}
2115
2116 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2117 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2118 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2119 guarantee($mem$$index == R_G0_enc, "double index?");
2120 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2121 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2122 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2123 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2124 %}
2125
2126 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2127 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2128 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2129 guarantee($mem$$index == R_G0_enc, "double index?");
2130 // Load long with 2 instructions
2131 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2132 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2133 %}
2134
2135 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2136 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2137 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2138 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2139 %}
2140
2141 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2142 // Encode a reg-reg copy. If it is useless, then empty encoding.
2143 if( $rs2$$reg != $rd$$reg )
2144 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2145 %}
2146
2147 // Target lo half of long
2148 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2149 // Encode a reg-reg copy. If it is useless, then empty encoding.
2150 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2151 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2152 %}
2153
2154 // Source lo half of long
2155 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2156 // Encode a reg-reg copy. If it is useless, then empty encoding.
2157 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2158 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2159 %}
2160
2161 // Target hi half of long
2162 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2163 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2164 %}
2165
2166 // Source lo half of long, and leave it sign extended.
2167 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2168 // Sign extend low half
2169 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2170 %}
2171
2172 // Source hi half of long, and leave it sign extended.
2173 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2174 // Shift high half to low half
2175 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2176 %}
2177
2178 // Source hi half of long
2179 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2180 // Encode a reg-reg copy. If it is useless, then empty encoding.
2181 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2182 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2183 %}
2184
2185 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2186 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2187 %}
2188
2189 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2190 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2191 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2192 %}
2193
2194 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2195 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2196 // clear if nothing else is happening
2197 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2198 // blt,a,pn done
2199 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2200 // mov dst,-1 in delay slot
2201 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2202 %}
2203
2204 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2205 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2206 %}
2207
2208 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2209 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2210 %}
2211
2212 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2213 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2214 %}
2215
2216 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2217 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2218 %}
2219
2220 enc_class move_return_pc_to_o1() %{
2221 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2222 %}
2223
2224 #ifdef _LP64
2225 /* %%% merge with enc_to_bool */
2226 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2227 MacroAssembler _masm(&cbuf);
2228
2229 Register src_reg = reg_to_register_object($src$$reg);
2230 Register dst_reg = reg_to_register_object($dst$$reg);
2231 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2232 %}
2233 #endif
2234
2235 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2236 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2237 MacroAssembler _masm(&cbuf);
2238
2239 Register p_reg = reg_to_register_object($p$$reg);
2240 Register q_reg = reg_to_register_object($q$$reg);
2241 Register y_reg = reg_to_register_object($y$$reg);
2242 Register tmp_reg = reg_to_register_object($tmp$$reg);
2243
2244 __ subcc( p_reg, q_reg, p_reg );
2245 __ add ( p_reg, y_reg, tmp_reg );
2246 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2247 %}
2248
2249 enc_class form_d2i_helper(regD src, regF dst) %{
2250 // fcmp %fcc0,$src,$src
2251 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2252 // branch %fcc0 not-nan, predict taken
2253 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2254 // fdtoi $src,$dst
2255 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2256 // fitos $dst,$dst (if nan)
2257 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2258 // clear $dst (if nan)
2259 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2260 // carry on here...
2261 %}
2262
2263 enc_class form_d2l_helper(regD src, regD dst) %{
2264 // fcmp %fcc0,$src,$src check for NAN
2265 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2266 // branch %fcc0 not-nan, predict taken
2267 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2268 // fdtox $src,$dst convert in delay slot
2269 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2270 // fxtod $dst,$dst (if nan)
2271 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2272 // clear $dst (if nan)
2273 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2274 // carry on here...
2275 %}
2276
2277 enc_class form_f2i_helper(regF src, regF dst) %{
2278 // fcmps %fcc0,$src,$src
2279 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2280 // branch %fcc0 not-nan, predict taken
2281 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2282 // fstoi $src,$dst
2283 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2284 // fitos $dst,$dst (if nan)
2285 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2286 // clear $dst (if nan)
2287 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2288 // carry on here...
2289 %}
2290
2291 enc_class form_f2l_helper(regF src, regD dst) %{
2292 // fcmps %fcc0,$src,$src
2293 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2294 // branch %fcc0 not-nan, predict taken
2295 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2296 // fstox $src,$dst
2297 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2298 // fxtod $dst,$dst (if nan)
2299 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2300 // clear $dst (if nan)
2301 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2302 // carry on here...
2303 %}
2304
2305 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2306 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2307 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2308 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2309
2310 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2311
2312 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2313 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2314
2315 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2316 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2317 %}
2318
2319 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2320 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2321 %}
2322
2323 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2324 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2325 %}
2326
2327 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2328 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2329 %}
2330
2331 enc_class form3_convI2F(regF rs2, regF rd) %{
2332 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2333 %}
2334
2335 // Encloding class for traceable jumps
2336 enc_class form_jmpl(g3RegP dest) %{
2337 emit_jmpl(cbuf, $dest$$reg);
2338 %}
2339
2340 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2341 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2342 %}
2343
2344 enc_class form2_nop() %{
2345 emit_nop(cbuf);
2346 %}
2347
2348 enc_class form2_illtrap() %{
2349 emit_illtrap(cbuf);
2350 %}
2351
2352
2353 // Compare longs and convert into -1, 0, 1.
2354 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2355 // CMP $src1,$src2
2356 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2357 // blt,a,pn done
2358 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2359 // mov dst,-1 in delay slot
2360 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2361 // bgt,a,pn done
2362 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2363 // mov dst,1 in delay slot
2364 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2365 // CLR $dst
2366 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2367 %}
2368
2369 enc_class enc_PartialSubtypeCheck() %{
2370 MacroAssembler _masm(&cbuf);
2371 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2372 __ delayed()->nop();
2373 %}
2374
2375 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2376 MacroAssembler _masm(&cbuf);
2377 Label* L = $labl$$label;
2378 Assembler::Predict predict_taken =
2379 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2380
2381 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2382 __ delayed()->nop();
2383 %}
2384
2385 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2386 MacroAssembler _masm(&cbuf);
2387 Label* L = $labl$$label;
2388 Assembler::Predict predict_taken =
2389 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2390
2391 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2392 __ delayed()->nop();
2393 %}
2394
2395 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2396 int op = (Assembler::arith_op << 30) |
2397 ($dst$$reg << 25) |
2398 (Assembler::movcc_op3 << 19) |
2399 (1 << 18) | // cc2 bit for 'icc'
2400 ($cmp$$cmpcode << 14) |
2401 (0 << 13) | // select register move
2402 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2403 ($src$$reg << 0);
2404 cbuf.insts()->emit_int32(op);
2405 %}
2406
2407 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2408 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2409 int op = (Assembler::arith_op << 30) |
2410 ($dst$$reg << 25) |
2411 (Assembler::movcc_op3 << 19) |
2412 (1 << 18) | // cc2 bit for 'icc'
2413 ($cmp$$cmpcode << 14) |
2414 (1 << 13) | // select immediate move
2415 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2416 (simm11 << 0);
2417 cbuf.insts()->emit_int32(op);
2418 %}
2419
2420 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2421 int op = (Assembler::arith_op << 30) |
2422 ($dst$$reg << 25) |
2423 (Assembler::movcc_op3 << 19) |
2424 (0 << 18) | // cc2 bit for 'fccX'
2425 ($cmp$$cmpcode << 14) |
2426 (0 << 13) | // select register move
2427 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2428 ($src$$reg << 0);
2429 cbuf.insts()->emit_int32(op);
2430 %}
2431
2432 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2433 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2434 int op = (Assembler::arith_op << 30) |
2435 ($dst$$reg << 25) |
2436 (Assembler::movcc_op3 << 19) |
2437 (0 << 18) | // cc2 bit for 'fccX'
2438 ($cmp$$cmpcode << 14) |
2439 (1 << 13) | // select immediate move
2440 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2441 (simm11 << 0);
2442 cbuf.insts()->emit_int32(op);
2443 %}
2444
2445 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2446 int op = (Assembler::arith_op << 30) |
2447 ($dst$$reg << 25) |
2448 (Assembler::fpop2_op3 << 19) |
2449 (0 << 18) |
2450 ($cmp$$cmpcode << 14) |
2451 (1 << 13) | // select register move
2452 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2453 ($primary << 5) | // select single, double or quad
2454 ($src$$reg << 0);
2455 cbuf.insts()->emit_int32(op);
2456 %}
2457
2458 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2459 int op = (Assembler::arith_op << 30) |
2460 ($dst$$reg << 25) |
2461 (Assembler::fpop2_op3 << 19) |
2462 (0 << 18) |
2463 ($cmp$$cmpcode << 14) |
2464 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2465 ($primary << 5) | // select single, double or quad
2466 ($src$$reg << 0);
2467 cbuf.insts()->emit_int32(op);
2468 %}
2469
2470 // Used by the MIN/MAX encodings. Same as a CMOV, but
2471 // the condition comes from opcode-field instead of an argument.
2472 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2473 int op = (Assembler::arith_op << 30) |
2474 ($dst$$reg << 25) |
2475 (Assembler::movcc_op3 << 19) |
2476 (1 << 18) | // cc2 bit for 'icc'
2477 ($primary << 14) |
2478 (0 << 13) | // select register move
2479 (0 << 11) | // cc1, cc0 bits for 'icc'
2480 ($src$$reg << 0);
2481 cbuf.insts()->emit_int32(op);
2482 %}
2483
2484 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2485 int op = (Assembler::arith_op << 30) |
2486 ($dst$$reg << 25) |
2487 (Assembler::movcc_op3 << 19) |
2488 (6 << 16) | // cc2 bit for 'xcc'
2489 ($primary << 14) |
2490 (0 << 13) | // select register move
2491 (0 << 11) | // cc1, cc0 bits for 'icc'
2492 ($src$$reg << 0);
2493 cbuf.insts()->emit_int32(op);
2494 %}
2495
2496 enc_class Set13( immI13 src, iRegI rd ) %{
2497 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2498 %}
2499
2500 enc_class SetHi22( immI src, iRegI rd ) %{
2501 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2502 %}
2503
2504 enc_class Set32( immI src, iRegI rd ) %{
2505 MacroAssembler _masm(&cbuf);
2506 __ set($src$$constant, reg_to_register_object($rd$$reg));
2507 %}
2508
2509 enc_class call_epilog %{
2510 if( VerifyStackAtCalls ) {
2511 MacroAssembler _masm(&cbuf);
2512 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2513 Register temp_reg = G3;
2514 __ add(SP, framesize, temp_reg);
2515 __ cmp(temp_reg, FP);
2516 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2517 }
2518 %}
2519
2520 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2521 // to G1 so the register allocator will not have to deal with the misaligned register
2522 // pair.
2523 enc_class adjust_long_from_native_call %{
2524 #ifndef _LP64
2525 if (returns_long()) {
2526 // sllx O0,32,O0
2527 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2528 // srl O1,0,O1
2529 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2530 // or O0,O1,G1
2531 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2532 }
2533 #endif
2534 %}
2535
2536 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2537 // CALL directly to the runtime
2538 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2539 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2540 /*preserve_g2=*/true);
2541 %}
2542
2543 enc_class preserve_SP %{
2544 MacroAssembler _masm(&cbuf);
2545 __ mov(SP, L7_mh_SP_save);
2546 %}
2547
2548 enc_class restore_SP %{
2549 MacroAssembler _masm(&cbuf);
2550 __ mov(L7_mh_SP_save, SP);
2551 %}
2552
2553 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2554 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2555 // who we intended to call.
2556 if (!_method) {
2557 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2558 } else if (_optimized_virtual) {
2559 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2560 } else {
2561 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2562 }
2563 if (_method) { // Emit stub for static call.
2564 CompiledStaticCall::emit_to_interp_stub(cbuf);
2565 }
2566 %}
2567
2568 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2569 MacroAssembler _masm(&cbuf);
2570 __ set_inst_mark();
2571 int vtable_index = this->_vtable_index;
2572 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2573 if (vtable_index < 0) {
2574 // must be invalid_vtable_index, not nonvirtual_vtable_index
2575 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2576 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2577 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2578 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2579 __ ic_call((address)$meth$$method);
2580 } else {
2581 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2582 // Just go thru the vtable
2583 // get receiver klass (receiver already checked for non-null)
2584 // If we end up going thru a c2i adapter interpreter expects method in G5
2585 int off = __ offset();
2586 __ load_klass(O0, G3_scratch);
2587 int klass_load_size;
2588 if (UseCompressedClassPointers) {
2589 assert(Universe::heap() != NULL, "java heap should be initialized");
2590 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2591 } else {
2592 klass_load_size = 1*BytesPerInstWord;
2593 }
2594 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2595 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2596 if (Assembler::is_simm13(v_off)) {
2597 __ ld_ptr(G3, v_off, G5_method);
2598 } else {
2599 // Generate 2 instructions
2600 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2601 __ or3(G5_method, v_off & 0x3ff, G5_method);
2602 // ld_ptr, set_hi, set
2603 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2604 "Unexpected instruction size(s)");
2605 __ ld_ptr(G3, G5_method, G5_method);
2606 }
2607 // NOTE: for vtable dispatches, the vtable entry will never be null.
2608 // However it may very well end up in handle_wrong_method if the
2609 // method is abstract for the particular class.
2610 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2611 // jump to target (either compiled code or c2iadapter)
2612 __ jmpl(G3_scratch, G0, O7);
2613 __ delayed()->nop();
2614 }
2615 %}
2616
2617 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2618 MacroAssembler _masm(&cbuf);
2619
2620 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2621 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2622 // we might be calling a C2I adapter which needs it.
2623
2624 assert(temp_reg != G5_ic_reg, "conflicting registers");
2625 // Load nmethod
2626 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2627
2628 // CALL to compiled java, indirect the contents of G3
2629 __ set_inst_mark();
2630 __ callr(temp_reg, G0);
2631 __ delayed()->nop();
2632 %}
2633
2634 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2635 MacroAssembler _masm(&cbuf);
2636 Register Rdividend = reg_to_register_object($src1$$reg);
2637 Register Rdivisor = reg_to_register_object($src2$$reg);
2638 Register Rresult = reg_to_register_object($dst$$reg);
2639
2640 __ sra(Rdivisor, 0, Rdivisor);
2641 __ sra(Rdividend, 0, Rdividend);
2642 __ sdivx(Rdividend, Rdivisor, Rresult);
2643 %}
2644
2645 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2646 MacroAssembler _masm(&cbuf);
2647
2648 Register Rdividend = reg_to_register_object($src1$$reg);
2649 int divisor = $imm$$constant;
2650 Register Rresult = reg_to_register_object($dst$$reg);
2651
2652 __ sra(Rdividend, 0, Rdividend);
2653 __ sdivx(Rdividend, divisor, Rresult);
2654 %}
2655
2656 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2657 MacroAssembler _masm(&cbuf);
2658 Register Rsrc1 = reg_to_register_object($src1$$reg);
2659 Register Rsrc2 = reg_to_register_object($src2$$reg);
2660 Register Rdst = reg_to_register_object($dst$$reg);
2661
2662 __ sra( Rsrc1, 0, Rsrc1 );
2663 __ sra( Rsrc2, 0, Rsrc2 );
2664 __ mulx( Rsrc1, Rsrc2, Rdst );
2665 __ srlx( Rdst, 32, Rdst );
2666 %}
2667
2668 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2669 MacroAssembler _masm(&cbuf);
2670 Register Rdividend = reg_to_register_object($src1$$reg);
2671 Register Rdivisor = reg_to_register_object($src2$$reg);
2672 Register Rresult = reg_to_register_object($dst$$reg);
2673 Register Rscratch = reg_to_register_object($scratch$$reg);
2674
2675 assert(Rdividend != Rscratch, "");
2676 assert(Rdivisor != Rscratch, "");
2677
2678 __ sra(Rdividend, 0, Rdividend);
2679 __ sra(Rdivisor, 0, Rdivisor);
2680 __ sdivx(Rdividend, Rdivisor, Rscratch);
2681 __ mulx(Rscratch, Rdivisor, Rscratch);
2682 __ sub(Rdividend, Rscratch, Rresult);
2683 %}
2684
2685 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2686 MacroAssembler _masm(&cbuf);
2687
2688 Register Rdividend = reg_to_register_object($src1$$reg);
2689 int divisor = $imm$$constant;
2690 Register Rresult = reg_to_register_object($dst$$reg);
2691 Register Rscratch = reg_to_register_object($scratch$$reg);
2692
2693 assert(Rdividend != Rscratch, "");
2694
2695 __ sra(Rdividend, 0, Rdividend);
2696 __ sdivx(Rdividend, divisor, Rscratch);
2697 __ mulx(Rscratch, divisor, Rscratch);
2698 __ sub(Rdividend, Rscratch, Rresult);
2699 %}
2700
2701 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2702 MacroAssembler _masm(&cbuf);
2703
2704 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2705 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2706
2707 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2708 %}
2709
2710 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2711 MacroAssembler _masm(&cbuf);
2712
2713 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2714 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2715
2716 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2717 %}
2718
2719 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2720 MacroAssembler _masm(&cbuf);
2721
2722 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2723 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2724
2725 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2726 %}
2727
2728 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2729 MacroAssembler _masm(&cbuf);
2730
2731 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2732 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2733
2734 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2735 %}
2736
2737 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2738 MacroAssembler _masm(&cbuf);
2739
2740 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2741 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2742
2743 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2744 %}
2745
2746 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2747 MacroAssembler _masm(&cbuf);
2748
2749 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2750 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2751
2752 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2753 %}
2754
2755 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2756 MacroAssembler _masm(&cbuf);
2757
2758 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2759 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2760
2761 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2762 %}
2763
2764 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2765 MacroAssembler _masm(&cbuf);
2766
2767 Register Roop = reg_to_register_object($oop$$reg);
2768 Register Rbox = reg_to_register_object($box$$reg);
2769 Register Rscratch = reg_to_register_object($scratch$$reg);
2770 Register Rmark = reg_to_register_object($scratch2$$reg);
2771
2772 assert(Roop != Rscratch, "");
2773 assert(Roop != Rmark, "");
2774 assert(Rbox != Rscratch, "");
2775 assert(Rbox != Rmark, "");
2776
2777 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2778 %}
2779
2780 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2781 MacroAssembler _masm(&cbuf);
2782
2783 Register Roop = reg_to_register_object($oop$$reg);
2784 Register Rbox = reg_to_register_object($box$$reg);
2785 Register Rscratch = reg_to_register_object($scratch$$reg);
2786 Register Rmark = reg_to_register_object($scratch2$$reg);
2787
2788 assert(Roop != Rscratch, "");
2789 assert(Roop != Rmark, "");
2790 assert(Rbox != Rscratch, "");
2791 assert(Rbox != Rmark, "");
2792
2793 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2794 %}
2795
2796 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2797 MacroAssembler _masm(&cbuf);
2798 Register Rmem = reg_to_register_object($mem$$reg);
2799 Register Rold = reg_to_register_object($old$$reg);
2800 Register Rnew = reg_to_register_object($new$$reg);
2801
2802 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2803 __ cmp( Rold, Rnew );
2804 %}
2805
2806 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2807 Register Rmem = reg_to_register_object($mem$$reg);
2808 Register Rold = reg_to_register_object($old$$reg);
2809 Register Rnew = reg_to_register_object($new$$reg);
2810
2811 MacroAssembler _masm(&cbuf);
2812 __ mov(Rnew, O7);
2813 __ casx(Rmem, Rold, O7);
2814 __ cmp( Rold, O7 );
2815 %}
2816
2817 // raw int cas, used for compareAndSwap
2818 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2819 Register Rmem = reg_to_register_object($mem$$reg);
2820 Register Rold = reg_to_register_object($old$$reg);
2821 Register Rnew = reg_to_register_object($new$$reg);
2822
2823 MacroAssembler _masm(&cbuf);
2824 __ mov(Rnew, O7);
2825 __ cas(Rmem, Rold, O7);
2826 __ cmp( Rold, O7 );
2827 %}
2828
2829 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2830 Register Rres = reg_to_register_object($res$$reg);
2831
2832 MacroAssembler _masm(&cbuf);
2833 __ mov(1, Rres);
2834 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2835 %}
2836
2837 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2838 Register Rres = reg_to_register_object($res$$reg);
2839
2840 MacroAssembler _masm(&cbuf);
2841 __ mov(1, Rres);
2842 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2843 %}
2844
2845 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2846 MacroAssembler _masm(&cbuf);
2847 Register Rdst = reg_to_register_object($dst$$reg);
2848 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2849 : reg_to_DoubleFloatRegister_object($src1$$reg);
2850 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2851 : reg_to_DoubleFloatRegister_object($src2$$reg);
2852
2853 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2854 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2855 %}
2856
2857
2858 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2859 Label Ldone, Lloop;
2860 MacroAssembler _masm(&cbuf);
2861
2862 Register str1_reg = reg_to_register_object($str1$$reg);
2863 Register str2_reg = reg_to_register_object($str2$$reg);
2864 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2865 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2866 Register result_reg = reg_to_register_object($result$$reg);
2867
2868 assert(result_reg != str1_reg &&
2869 result_reg != str2_reg &&
2870 result_reg != cnt1_reg &&
2871 result_reg != cnt2_reg ,
2872 "need different registers");
2873
2874 // Compute the minimum of the string lengths(str1_reg) and the
2875 // difference of the string lengths (stack)
2876
2877 // See if the lengths are different, and calculate min in str1_reg.
2878 // Stash diff in O7 in case we need it for a tie-breaker.
2879 Label Lskip;
2880 __ subcc(cnt1_reg, cnt2_reg, O7);
2881 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2882 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2883 // cnt2 is shorter, so use its count:
2884 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2885 __ bind(Lskip);
2886
2887 // reallocate cnt1_reg, cnt2_reg, result_reg
2888 // Note: limit_reg holds the string length pre-scaled by 2
2889 Register limit_reg = cnt1_reg;
2890 Register chr2_reg = cnt2_reg;
2891 Register chr1_reg = result_reg;
2892 // str{12} are the base pointers
2893
2894 // Is the minimum length zero?
2895 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2896 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2897 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2898
2899 // Load first characters
2900 __ lduh(str1_reg, 0, chr1_reg);
2901 __ lduh(str2_reg, 0, chr2_reg);
2902
2903 // Compare first characters
2904 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2905 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2906 assert(chr1_reg == result_reg, "result must be pre-placed");
2907 __ delayed()->nop();
2908
2909 {
2910 // Check after comparing first character to see if strings are equivalent
2911 Label LSkip2;
2912 // Check if the strings start at same location
2913 __ cmp(str1_reg, str2_reg);
2914 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2915 __ delayed()->nop();
2916
2917 // Check if the length difference is zero (in O7)
2918 __ cmp(G0, O7);
2919 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2920 __ delayed()->mov(G0, result_reg); // result is zero
2921
2922 // Strings might not be equal
2923 __ bind(LSkip2);
2924 }
2925
2926 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2927 __ signx(limit_reg);
2928
2929 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2930 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2931 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2932
2933 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2934 __ add(str1_reg, limit_reg, str1_reg);
2935 __ add(str2_reg, limit_reg, str2_reg);
2936 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2937
2938 // Compare the rest of the characters
2939 __ lduh(str1_reg, limit_reg, chr1_reg);
2940 __ bind(Lloop);
2941 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2942 __ lduh(str2_reg, limit_reg, chr2_reg);
2943 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2944 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2945 assert(chr1_reg == result_reg, "result must be pre-placed");
2946 __ delayed()->inccc(limit_reg, sizeof(jchar));
2947 // annul LDUH if branch is not taken to prevent access past end of string
2948 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2949 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2950
2951 // If strings are equal up to min length, return the length difference.
2952 __ mov(O7, result_reg);
2953
2954 // Otherwise, return the difference between the first mismatched chars.
2955 __ bind(Ldone);
2956 %}
2957
2958 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2959 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2960 MacroAssembler _masm(&cbuf);
2961
2962 Register str1_reg = reg_to_register_object($str1$$reg);
2963 Register str2_reg = reg_to_register_object($str2$$reg);
2964 Register cnt_reg = reg_to_register_object($cnt$$reg);
2965 Register tmp1_reg = O7;
2966 Register result_reg = reg_to_register_object($result$$reg);
2967
2968 assert(result_reg != str1_reg &&
2969 result_reg != str2_reg &&
2970 result_reg != cnt_reg &&
2971 result_reg != tmp1_reg ,
2972 "need different registers");
2973
2974 __ cmp(str1_reg, str2_reg); //same char[] ?
2975 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2976 __ delayed()->add(G0, 1, result_reg);
2977
2978 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2979 __ delayed()->add(G0, 1, result_reg); // count == 0
2980
2981 //rename registers
2982 Register limit_reg = cnt_reg;
2983 Register chr1_reg = result_reg;
2984 Register chr2_reg = tmp1_reg;
2985
2986 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2987 __ signx(limit_reg);
2988
2989 //check for alignment and position the pointers to the ends
2990 __ or3(str1_reg, str2_reg, chr1_reg);
2991 __ andcc(chr1_reg, 0x3, chr1_reg);
2992 // notZero means at least one not 4-byte aligned.
2993 // We could optimize the case when both arrays are not aligned
2994 // but it is not frequent case and it requires additional checks.
2995 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2996 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2997
2998 // Compare char[] arrays aligned to 4 bytes.
2999 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3000 chr1_reg, chr2_reg, Ldone);
3001 __ ba(Ldone);
3002 __ delayed()->add(G0, 1, result_reg);
3003
3004 // char by char compare
3005 __ bind(Lchar);
3006 __ add(str1_reg, limit_reg, str1_reg);
3007 __ add(str2_reg, limit_reg, str2_reg);
3008 __ neg(limit_reg); //negate count
3009
3010 __ lduh(str1_reg, limit_reg, chr1_reg);
3011 // Lchar_loop
3012 __ bind(Lchar_loop);
3013 __ lduh(str2_reg, limit_reg, chr2_reg);
3014 __ cmp(chr1_reg, chr2_reg);
3015 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3016 __ delayed()->mov(G0, result_reg); //not equal
3017 __ inccc(limit_reg, sizeof(jchar));
3018 // annul LDUH if branch is not taken to prevent access past end of string
3019 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3020 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3021
3022 __ add(G0, 1, result_reg); //equal
3023
3024 __ bind(Ldone);
3025 %}
3026
3027 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3028 Label Lvector, Ldone, Lloop;
3029 MacroAssembler _masm(&cbuf);
3030
3031 Register ary1_reg = reg_to_register_object($ary1$$reg);
3032 Register ary2_reg = reg_to_register_object($ary2$$reg);
3033 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3034 Register tmp2_reg = O7;
3035 Register result_reg = reg_to_register_object($result$$reg);
3036
3037 int length_offset = arrayOopDesc::length_offset_in_bytes();
3038 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3039
3040 // return true if the same array
3041 __ cmp(ary1_reg, ary2_reg);
3042 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3043 __ delayed()->add(G0, 1, result_reg); // equal
3044
3045 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3046 __ delayed()->mov(G0, result_reg); // not equal
3047
3048 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3049 __ delayed()->mov(G0, result_reg); // not equal
3050
3051 //load the lengths of arrays
3052 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3053 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3054
3055 // return false if the two arrays are not equal length
3056 __ cmp(tmp1_reg, tmp2_reg);
3057 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3058 __ delayed()->mov(G0, result_reg); // not equal
3059
3060 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3061 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3062
3063 // load array addresses
3064 __ add(ary1_reg, base_offset, ary1_reg);
3065 __ add(ary2_reg, base_offset, ary2_reg);
3066
3067 // renaming registers
3068 Register chr1_reg = result_reg; // for characters in ary1
3069 Register chr2_reg = tmp2_reg; // for characters in ary2
3070 Register limit_reg = tmp1_reg; // length
3071
3072 // set byte count
3073 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3074
3075 // Compare char[] arrays aligned to 4 bytes.
3076 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3077 chr1_reg, chr2_reg, Ldone);
3078 __ add(G0, 1, result_reg); // equals
3079
3080 __ bind(Ldone);
3081 %}
3082
3083 enc_class enc_rethrow() %{
3084 cbuf.set_insts_mark();
3085 Register temp_reg = G3;
3086 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3087 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3088 MacroAssembler _masm(&cbuf);
3089 #ifdef ASSERT
3090 __ save_frame(0);
3091 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3092 __ sethi(last_rethrow_addrlit, L1);
3093 Address addr(L1, last_rethrow_addrlit.low10());
3094 __ rdpc(L2);
3095 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3096 __ st_ptr(L2, addr);
3097 __ restore();
3098 #endif
3099 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3100 __ delayed()->nop();
3101 %}
3102
3103 enc_class emit_mem_nop() %{
3104 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3105 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3106 %}
3107
3108 enc_class emit_fadd_nop() %{
3109 // Generates the instruction FMOVS f31,f31
3110 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3111 %}
3112
3113 enc_class emit_br_nop() %{
3114 // Generates the instruction BPN,PN .
3115 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3116 %}
3117
3118 enc_class enc_membar_acquire %{
3119 MacroAssembler _masm(&cbuf);
3120 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3121 %}
3122
3123 enc_class enc_membar_release %{
3124 MacroAssembler _masm(&cbuf);
3125 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3126 %}
3127
3128 enc_class enc_membar_volatile %{
3129 MacroAssembler _masm(&cbuf);
3130 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3131 %}
3132
3133 %}
3134
3135 //----------FRAME--------------------------------------------------------------
3136 // Definition of frame structure and management information.
3137 //
3138 // S T A C K L A Y O U T Allocators stack-slot number
3139 // | (to get allocators register number
3140 // G Owned by | | v add VMRegImpl::stack0)
3141 // r CALLER | |
3142 // o | +--------+ pad to even-align allocators stack-slot
3143 // w V | pad0 | numbers; owned by CALLER
3144 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3145 // h ^ | in | 5
3146 // | | args | 4 Holes in incoming args owned by SELF
3147 // | | | | 3
3148 // | | +--------+
3149 // V | | old out| Empty on Intel, window on Sparc
3150 // | old |preserve| Must be even aligned.
3151 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3152 // | | in | 3 area for Intel ret address
3153 // Owned by |preserve| Empty on Sparc.
3154 // SELF +--------+
3155 // | | pad2 | 2 pad to align old SP
3156 // | +--------+ 1
3157 // | | locks | 0
3158 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3159 // | | pad1 | 11 pad to align new SP
3160 // | +--------+
3161 // | | | 10
3162 // | | spills | 9 spills
3163 // V | | 8 (pad0 slot for callee)
3164 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3165 // ^ | out | 7
3166 // | | args | 6 Holes in outgoing args owned by CALLEE
3167 // Owned by +--------+
3168 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3169 // | new |preserve| Must be even-aligned.
3170 // | SP-+--------+----> Matcher::_new_SP, even aligned
3171 // | | |
3172 //
3173 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3174 // known from SELF's arguments and the Java calling convention.
3175 // Region 6-7 is determined per call site.
3176 // Note 2: If the calling convention leaves holes in the incoming argument
3177 // area, those holes are owned by SELF. Holes in the outgoing area
3178 // are owned by the CALLEE. Holes should not be nessecary in the
3179 // incoming area, as the Java calling convention is completely under
3180 // the control of the AD file. Doubles can be sorted and packed to
3181 // avoid holes. Holes in the outgoing arguments may be nessecary for
3182 // varargs C calling conventions.
3183 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3184 // even aligned with pad0 as needed.
3185 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3186 // region 6-11 is even aligned; it may be padded out more so that
3187 // the region from SP to FP meets the minimum stack alignment.
3188
3189 frame %{
3190 // What direction does stack grow in (assumed to be same for native & Java)
3191 stack_direction(TOWARDS_LOW);
3192
3193 // These two registers define part of the calling convention
3194 // between compiled code and the interpreter.
3195 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3196 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3197
3198 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3199 cisc_spilling_operand_name(indOffset);
3200
3201 // Number of stack slots consumed by a Monitor enter
3202 #ifdef _LP64
3203 sync_stack_slots(2);
3204 #else
3205 sync_stack_slots(1);
3206 #endif
3207
3208 // Compiled code's Frame Pointer
3209 frame_pointer(R_SP);
3210
3211 // Stack alignment requirement
3212 stack_alignment(StackAlignmentInBytes);
3213 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3214 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3215
3216 // Number of stack slots between incoming argument block and the start of
3217 // a new frame. The PROLOG must add this many slots to the stack. The
3218 // EPILOG must remove this many slots.
3219 in_preserve_stack_slots(0);
3220
3221 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3222 // for calls to C. Supports the var-args backing area for register parms.
3223 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3224 #ifdef _LP64
3225 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3226 varargs_C_out_slots_killed(12);
3227 #else
3228 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3229 varargs_C_out_slots_killed( 7);
3230 #endif
3231
3232 // The after-PROLOG location of the return address. Location of
3233 // return address specifies a type (REG or STACK) and a number
3234 // representing the register number (i.e. - use a register name) or
3235 // stack slot.
3236 return_addr(REG R_I7); // Ret Addr is in register I7
3237
3238 // Body of function which returns an OptoRegs array locating
3239 // arguments either in registers or in stack slots for calling
3240 // java
3241 calling_convention %{
3242 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3243
3244 %}
3245
3246 // Body of function which returns an OptoRegs array locating
3247 // arguments either in registers or in stack slots for callin
3248 // C.
3249 c_calling_convention %{
3250 // This is obviously always outgoing
3251 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3252 %}
3253
3254 // Location of native (C/C++) and interpreter return values. This is specified to
3255 // be the same as Java. In the 32-bit VM, long values are actually returned from
3256 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3257 // to and from the register pairs is done by the appropriate call and epilog
3258 // opcodes. This simplifies the register allocator.
3259 c_return_value %{
3260 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3261 #ifdef _LP64
3262 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3263 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3264 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3265 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3266 #else // !_LP64
3267 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3268 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3269 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3270 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3271 #endif
3272 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3273 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3274 %}
3275
3276 // Location of compiled Java return values. Same as C
3277 return_value %{
3278 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3279 #ifdef _LP64
3280 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3281 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3282 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3283 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3284 #else // !_LP64
3285 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3286 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3287 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3288 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3289 #endif
3290 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3291 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3292 %}
3293
3294 %}
3295
3296
3297 //----------ATTRIBUTES---------------------------------------------------------
3298 //----------Operand Attributes-------------------------------------------------
3299 op_attrib op_cost(1); // Required cost attribute
3300
3301 //----------Instruction Attributes---------------------------------------------
3302 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3303 ins_attrib ins_size(32); // Required size attribute (in bits)
3304 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3305 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3306 // non-matching short branch variant of some
3307 // long branch?
3308
3309 //----------OPERANDS-----------------------------------------------------------
3310 // Operand definitions must precede instruction definitions for correct parsing
3311 // in the ADLC because operands constitute user defined types which are used in
3312 // instruction definitions.
3313
3314 //----------Simple Operands----------------------------------------------------
3315 // Immediate Operands
3316 // Integer Immediate: 32-bit
3317 operand immI() %{
3318 match(ConI);
3319
3320 op_cost(0);
3321 // formats are generated automatically for constants and base registers
3322 format %{ %}
3323 interface(CONST_INTER);
3324 %}
3325
3326 // Integer Immediate: 8-bit
3327 operand immI8() %{
3328 predicate(Assembler::is_simm8(n->get_int()));
3329 match(ConI);
3330 op_cost(0);
3331 format %{ %}
3332 interface(CONST_INTER);
3333 %}
3334
3335 // Integer Immediate: 13-bit
3336 operand immI13() %{
3337 predicate(Assembler::is_simm13(n->get_int()));
3338 match(ConI);
3339 op_cost(0);
3340
3341 format %{ %}
3342 interface(CONST_INTER);
3343 %}
3344
3345 // Integer Immediate: 13-bit minus 7
3346 operand immI13m7() %{
3347 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3348 match(ConI);
3349 op_cost(0);
3350
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 // Integer Immediate: 16-bit
3356 operand immI16() %{
3357 predicate(Assembler::is_simm16(n->get_int()));
3358 match(ConI);
3359 op_cost(0);
3360 format %{ %}
3361 interface(CONST_INTER);
3362 %}
3363
3364 // Unsigned (positive) Integer Immediate: 13-bit
3365 operand immU13() %{
3366 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3367 match(ConI);
3368 op_cost(0);
3369
3370 format %{ %}
3371 interface(CONST_INTER);
3372 %}
3373
3374 // Integer Immediate: 6-bit
3375 operand immU6() %{
3376 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3377 match(ConI);
3378 op_cost(0);
3379 format %{ %}
3380 interface(CONST_INTER);
3381 %}
3382
3383 // Integer Immediate: 11-bit
3384 operand immI11() %{
3385 predicate(Assembler::is_simm11(n->get_int()));
3386 match(ConI);
3387 op_cost(0);
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Integer Immediate: 5-bit
3393 operand immI5() %{
3394 predicate(Assembler::is_simm5(n->get_int()));
3395 match(ConI);
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Int Immediate positive
3402 operand immU32()
3403 %{
3404 predicate(n->get_int() >= 0);
3405 match(ConI);
3406
3407 op_cost(0);
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3411
3412 // Integer Immediate: 0-bit
3413 operand immI0() %{
3414 predicate(n->get_int() == 0);
3415 match(ConI);
3416 op_cost(0);
3417
3418 format %{ %}
3419 interface(CONST_INTER);
3420 %}
3421
3422 // Integer Immediate: the value 10
3423 operand immI10() %{
3424 predicate(n->get_int() == 10);
3425 match(ConI);
3426 op_cost(0);
3427
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3431
3432 // Integer Immediate: the values 0-31
3433 operand immU5() %{
3434 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3435 match(ConI);
3436 op_cost(0);
3437
3438 format %{ %}
3439 interface(CONST_INTER);
3440 %}
3441
3442 // Integer Immediate: the values 1-31
3443 operand immI_1_31() %{
3444 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3445 match(ConI);
3446 op_cost(0);
3447
3448 format %{ %}
3449 interface(CONST_INTER);
3450 %}
3451
3452 // Integer Immediate: the values 32-63
3453 operand immI_32_63() %{
3454 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3455 match(ConI);
3456 op_cost(0);
3457
3458 format %{ %}
3459 interface(CONST_INTER);
3460 %}
3461
3462 // Immediates for special shifts (sign extend)
3463
3464 // Integer Immediate: the value 16
3465 operand immI_16() %{
3466 predicate(n->get_int() == 16);
3467 match(ConI);
3468 op_cost(0);
3469
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3473
3474 // Integer Immediate: the value 24
3475 operand immI_24() %{
3476 predicate(n->get_int() == 24);
3477 match(ConI);
3478 op_cost(0);
3479
3480 format %{ %}
3481 interface(CONST_INTER);
3482 %}
3483
3484 // Integer Immediate: the value 255
3485 operand immI_255() %{
3486 predicate( n->get_int() == 255 );
3487 match(ConI);
3488 op_cost(0);
3489
3490 format %{ %}
3491 interface(CONST_INTER);
3492 %}
3493
3494 // Integer Immediate: the value 65535
3495 operand immI_65535() %{
3496 predicate(n->get_int() == 65535);
3497 match(ConI);
3498 op_cost(0);
3499
3500 format %{ %}
3501 interface(CONST_INTER);
3502 %}
3503
3504 // Long Immediate: the value FF
3505 operand immL_FF() %{
3506 predicate( n->get_long() == 0xFFL );
3507 match(ConL);
3508 op_cost(0);
3509
3510 format %{ %}
3511 interface(CONST_INTER);
3512 %}
3513
3514 // Long Immediate: the value FFFF
3515 operand immL_FFFF() %{
3516 predicate( n->get_long() == 0xFFFFL );
3517 match(ConL);
3518 op_cost(0);
3519
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3523
3524 // Pointer Immediate: 32 or 64-bit
3525 operand immP() %{
3526 match(ConP);
3527
3528 op_cost(5);
3529 // formats are generated automatically for constants and base registers
3530 format %{ %}
3531 interface(CONST_INTER);
3532 %}
3533
3534 #ifdef _LP64
3535 // Pointer Immediate: 64-bit
3536 operand immP_set() %{
3537 predicate(!VM_Version::is_niagara_plus());
3538 match(ConP);
3539
3540 op_cost(5);
3541 // formats are generated automatically for constants and base registers
3542 format %{ %}
3543 interface(CONST_INTER);
3544 %}
3545
3546 // Pointer Immediate: 64-bit
3547 // From Niagara2 processors on a load should be better than materializing.
3548 operand immP_load() %{
3549 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3550 match(ConP);
3551
3552 op_cost(5);
3553 // formats are generated automatically for constants and base registers
3554 format %{ %}
3555 interface(CONST_INTER);
3556 %}
3557
3558 // Pointer Immediate: 64-bit
3559 operand immP_no_oop_cheap() %{
3560 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3561 match(ConP);
3562
3563 op_cost(5);
3564 // formats are generated automatically for constants and base registers
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568 #endif
3569
3570 operand immP13() %{
3571 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3572 match(ConP);
3573 op_cost(0);
3574
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 operand immP0() %{
3580 predicate(n->get_ptr() == 0);
3581 match(ConP);
3582 op_cost(0);
3583
3584 format %{ %}
3585 interface(CONST_INTER);
3586 %}
3587
3588 operand immP_poll() %{
3589 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3590 match(ConP);
3591
3592 // formats are generated automatically for constants and base registers
3593 format %{ %}
3594 interface(CONST_INTER);
3595 %}
3596
3597 // Pointer Immediate
3598 operand immN()
3599 %{
3600 match(ConN);
3601
3602 op_cost(10);
3603 format %{ %}
3604 interface(CONST_INTER);
3605 %}
3606
3607 operand immNKlass()
3608 %{
3609 match(ConNKlass);
3610
3611 op_cost(10);
3612 format %{ %}
3613 interface(CONST_INTER);
3614 %}
3615
3616 // NULL Pointer Immediate
3617 operand immN0()
3618 %{
3619 predicate(n->get_narrowcon() == 0);
3620 match(ConN);
3621
3622 op_cost(0);
3623 format %{ %}
3624 interface(CONST_INTER);
3625 %}
3626
3627 operand immL() %{
3628 match(ConL);
3629 op_cost(40);
3630 // formats are generated automatically for constants and base registers
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3634
3635 operand immL0() %{
3636 predicate(n->get_long() == 0L);
3637 match(ConL);
3638 op_cost(0);
3639 // formats are generated automatically for constants and base registers
3640 format %{ %}
3641 interface(CONST_INTER);
3642 %}
3643
3644 // Integer Immediate: 5-bit
3645 operand immL5() %{
3646 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3647 match(ConL);
3648 op_cost(0);
3649 format %{ %}
3650 interface(CONST_INTER);
3651 %}
3652
3653 // Long Immediate: 13-bit
3654 operand immL13() %{
3655 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3656 match(ConL);
3657 op_cost(0);
3658
3659 format %{ %}
3660 interface(CONST_INTER);
3661 %}
3662
3663 // Long Immediate: 13-bit minus 7
3664 operand immL13m7() %{
3665 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3666 match(ConL);
3667 op_cost(0);
3668
3669 format %{ %}
3670 interface(CONST_INTER);
3671 %}
3672
3673 // Long Immediate: low 32-bit mask
3674 operand immL_32bits() %{
3675 predicate(n->get_long() == 0xFFFFFFFFL);
3676 match(ConL);
3677 op_cost(0);
3678
3679 format %{ %}
3680 interface(CONST_INTER);
3681 %}
3682
3683 // Long Immediate: cheap (materialize in <= 3 instructions)
3684 operand immL_cheap() %{
3685 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3686 match(ConL);
3687 op_cost(0);
3688
3689 format %{ %}
3690 interface(CONST_INTER);
3691 %}
3692
3693 // Long Immediate: expensive (materialize in > 3 instructions)
3694 operand immL_expensive() %{
3695 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3696 match(ConL);
3697 op_cost(0);
3698
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3702
3703 // Double Immediate
3704 operand immD() %{
3705 match(ConD);
3706
3707 op_cost(40);
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3711
3712 operand immD0() %{
3713 #ifdef _LP64
3714 // on 64-bit architectures this comparision is faster
3715 predicate(jlong_cast(n->getd()) == 0);
3716 #else
3717 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3718 #endif
3719 match(ConD);
3720
3721 op_cost(0);
3722 format %{ %}
3723 interface(CONST_INTER);
3724 %}
3725
3726 // Float Immediate
3727 operand immF() %{
3728 match(ConF);
3729
3730 op_cost(20);
3731 format %{ %}
3732 interface(CONST_INTER);
3733 %}
3734
3735 // Float Immediate: 0
3736 operand immF0() %{
3737 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3738 match(ConF);
3739
3740 op_cost(0);
3741 format %{ %}
3742 interface(CONST_INTER);
3743 %}
3744
3745 // Integer Register Operands
3746 // Integer Register
3747 operand iRegI() %{
3748 constraint(ALLOC_IN_RC(int_reg));
3749 match(RegI);
3750
3751 match(notemp_iRegI);
3752 match(g1RegI);
3753 match(o0RegI);
3754 match(iRegIsafe);
3755
3756 format %{ %}
3757 interface(REG_INTER);
3758 %}
3759
3760 operand notemp_iRegI() %{
3761 constraint(ALLOC_IN_RC(notemp_int_reg));
3762 match(RegI);
3763
3764 match(o0RegI);
3765
3766 format %{ %}
3767 interface(REG_INTER);
3768 %}
3769
3770 operand o0RegI() %{
3771 constraint(ALLOC_IN_RC(o0_regI));
3772 match(iRegI);
3773
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 // Pointer Register
3779 operand iRegP() %{
3780 constraint(ALLOC_IN_RC(ptr_reg));
3781 match(RegP);
3782
3783 match(lock_ptr_RegP);
3784 match(g1RegP);
3785 match(g2RegP);
3786 match(g3RegP);
3787 match(g4RegP);
3788 match(i0RegP);
3789 match(o0RegP);
3790 match(o1RegP);
3791 match(l7RegP);
3792
3793 format %{ %}
3794 interface(REG_INTER);
3795 %}
3796
3797 operand sp_ptr_RegP() %{
3798 constraint(ALLOC_IN_RC(sp_ptr_reg));
3799 match(RegP);
3800 match(iRegP);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand lock_ptr_RegP() %{
3807 constraint(ALLOC_IN_RC(lock_ptr_reg));
3808 match(RegP);
3809 match(i0RegP);
3810 match(o0RegP);
3811 match(o1RegP);
3812 match(l7RegP);
3813
3814 format %{ %}
3815 interface(REG_INTER);
3816 %}
3817
3818 operand g1RegP() %{
3819 constraint(ALLOC_IN_RC(g1_regP));
3820 match(iRegP);
3821
3822 format %{ %}
3823 interface(REG_INTER);
3824 %}
3825
3826 operand g2RegP() %{
3827 constraint(ALLOC_IN_RC(g2_regP));
3828 match(iRegP);
3829
3830 format %{ %}
3831 interface(REG_INTER);
3832 %}
3833
3834 operand g3RegP() %{
3835 constraint(ALLOC_IN_RC(g3_regP));
3836 match(iRegP);
3837
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 operand g1RegI() %{
3843 constraint(ALLOC_IN_RC(g1_regI));
3844 match(iRegI);
3845
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 operand g3RegI() %{
3851 constraint(ALLOC_IN_RC(g3_regI));
3852 match(iRegI);
3853
3854 format %{ %}
3855 interface(REG_INTER);
3856 %}
3857
3858 operand g4RegI() %{
3859 constraint(ALLOC_IN_RC(g4_regI));
3860 match(iRegI);
3861
3862 format %{ %}
3863 interface(REG_INTER);
3864 %}
3865
3866 operand g4RegP() %{
3867 constraint(ALLOC_IN_RC(g4_regP));
3868 match(iRegP);
3869
3870 format %{ %}
3871 interface(REG_INTER);
3872 %}
3873
3874 operand i0RegP() %{
3875 constraint(ALLOC_IN_RC(i0_regP));
3876 match(iRegP);
3877
3878 format %{ %}
3879 interface(REG_INTER);
3880 %}
3881
3882 operand o0RegP() %{
3883 constraint(ALLOC_IN_RC(o0_regP));
3884 match(iRegP);
3885
3886 format %{ %}
3887 interface(REG_INTER);
3888 %}
3889
3890 operand o1RegP() %{
3891 constraint(ALLOC_IN_RC(o1_regP));
3892 match(iRegP);
3893
3894 format %{ %}
3895 interface(REG_INTER);
3896 %}
3897
3898 operand o2RegP() %{
3899 constraint(ALLOC_IN_RC(o2_regP));
3900 match(iRegP);
3901
3902 format %{ %}
3903 interface(REG_INTER);
3904 %}
3905
3906 operand o7RegP() %{
3907 constraint(ALLOC_IN_RC(o7_regP));
3908 match(iRegP);
3909
3910 format %{ %}
3911 interface(REG_INTER);
3912 %}
3913
3914 operand l7RegP() %{
3915 constraint(ALLOC_IN_RC(l7_regP));
3916 match(iRegP);
3917
3918 format %{ %}
3919 interface(REG_INTER);
3920 %}
3921
3922 operand o7RegI() %{
3923 constraint(ALLOC_IN_RC(o7_regI));
3924 match(iRegI);
3925
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3929
3930 operand iRegN() %{
3931 constraint(ALLOC_IN_RC(int_reg));
3932 match(RegN);
3933
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3937
3938 // Long Register
3939 operand iRegL() %{
3940 constraint(ALLOC_IN_RC(long_reg));
3941 match(RegL);
3942
3943 format %{ %}
3944 interface(REG_INTER);
3945 %}
3946
3947 operand o2RegL() %{
3948 constraint(ALLOC_IN_RC(o2_regL));
3949 match(iRegL);
3950
3951 format %{ %}
3952 interface(REG_INTER);
3953 %}
3954
3955 operand o7RegL() %{
3956 constraint(ALLOC_IN_RC(o7_regL));
3957 match(iRegL);
3958
3959 format %{ %}
3960 interface(REG_INTER);
3961 %}
3962
3963 operand g1RegL() %{
3964 constraint(ALLOC_IN_RC(g1_regL));
3965 match(iRegL);
3966
3967 format %{ %}
3968 interface(REG_INTER);
3969 %}
3970
3971 operand g3RegL() %{
3972 constraint(ALLOC_IN_RC(g3_regL));
3973 match(iRegL);
3974
3975 format %{ %}
3976 interface(REG_INTER);
3977 %}
3978
3979 // Int Register safe
3980 // This is 64bit safe
3981 operand iRegIsafe() %{
3982 constraint(ALLOC_IN_RC(long_reg));
3983
3984 match(iRegI);
3985
3986 format %{ %}
3987 interface(REG_INTER);
3988 %}
3989
3990 // Condition Code Flag Register
3991 operand flagsReg() %{
3992 constraint(ALLOC_IN_RC(int_flags));
3993 match(RegFlags);
3994
3995 format %{ "ccr" %} // both ICC and XCC
3996 interface(REG_INTER);
3997 %}
3998
3999 // Condition Code Register, unsigned comparisons.
4000 operand flagsRegU() %{
4001 constraint(ALLOC_IN_RC(int_flags));
4002 match(RegFlags);
4003
4004 format %{ "icc_U" %}
4005 interface(REG_INTER);
4006 %}
4007
4008 // Condition Code Register, pointer comparisons.
4009 operand flagsRegP() %{
4010 constraint(ALLOC_IN_RC(int_flags));
4011 match(RegFlags);
4012
4013 #ifdef _LP64
4014 format %{ "xcc_P" %}
4015 #else
4016 format %{ "icc_P" %}
4017 #endif
4018 interface(REG_INTER);
4019 %}
4020
4021 // Condition Code Register, long comparisons.
4022 operand flagsRegL() %{
4023 constraint(ALLOC_IN_RC(int_flags));
4024 match(RegFlags);
4025
4026 format %{ "xcc_L" %}
4027 interface(REG_INTER);
4028 %}
4029
4030 // Condition Code Register, floating comparisons, unordered same as "less".
4031 operand flagsRegF() %{
4032 constraint(ALLOC_IN_RC(float_flags));
4033 match(RegFlags);
4034 match(flagsRegF0);
4035
4036 format %{ %}
4037 interface(REG_INTER);
4038 %}
4039
4040 operand flagsRegF0() %{
4041 constraint(ALLOC_IN_RC(float_flag0));
4042 match(RegFlags);
4043
4044 format %{ %}
4045 interface(REG_INTER);
4046 %}
4047
4048
4049 // Condition Code Flag Register used by long compare
4050 operand flagsReg_long_LTGE() %{
4051 constraint(ALLOC_IN_RC(int_flags));
4052 match(RegFlags);
4053 format %{ "icc_LTGE" %}
4054 interface(REG_INTER);
4055 %}
4056 operand flagsReg_long_EQNE() %{
4057 constraint(ALLOC_IN_RC(int_flags));
4058 match(RegFlags);
4059 format %{ "icc_EQNE" %}
4060 interface(REG_INTER);
4061 %}
4062 operand flagsReg_long_LEGT() %{
4063 constraint(ALLOC_IN_RC(int_flags));
4064 match(RegFlags);
4065 format %{ "icc_LEGT" %}
4066 interface(REG_INTER);
4067 %}
4068
4069
4070 operand regD() %{
4071 constraint(ALLOC_IN_RC(dflt_reg));
4072 match(RegD);
4073
4074 match(regD_low);
4075
4076 format %{ %}
4077 interface(REG_INTER);
4078 %}
4079
4080 operand regF() %{
4081 constraint(ALLOC_IN_RC(sflt_reg));
4082 match(RegF);
4083
4084 format %{ %}
4085 interface(REG_INTER);
4086 %}
4087
4088 operand regD_low() %{
4089 constraint(ALLOC_IN_RC(dflt_low_reg));
4090 match(regD);
4091
4092 format %{ %}
4093 interface(REG_INTER);
4094 %}
4095
4096 // Special Registers
4097
4098 // Method Register
4099 operand inline_cache_regP(iRegP reg) %{
4100 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4101 match(reg);
4102 format %{ %}
4103 interface(REG_INTER);
4104 %}
4105
4106 operand interpreter_method_oop_regP(iRegP reg) %{
4107 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4108 match(reg);
4109 format %{ %}
4110 interface(REG_INTER);
4111 %}
4112
4113
4114 //----------Complex Operands---------------------------------------------------
4115 // Indirect Memory Reference
4116 operand indirect(sp_ptr_RegP reg) %{
4117 constraint(ALLOC_IN_RC(sp_ptr_reg));
4118 match(reg);
4119
4120 op_cost(100);
4121 format %{ "[$reg]" %}
4122 interface(MEMORY_INTER) %{
4123 base($reg);
4124 index(0x0);
4125 scale(0x0);
4126 disp(0x0);
4127 %}
4128 %}
4129
4130 // Indirect with simm13 Offset
4131 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4132 constraint(ALLOC_IN_RC(sp_ptr_reg));
4133 match(AddP reg offset);
4134
4135 op_cost(100);
4136 format %{ "[$reg + $offset]" %}
4137 interface(MEMORY_INTER) %{
4138 base($reg);
4139 index(0x0);
4140 scale(0x0);
4141 disp($offset);
4142 %}
4143 %}
4144
4145 // Indirect with simm13 Offset minus 7
4146 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4147 constraint(ALLOC_IN_RC(sp_ptr_reg));
4148 match(AddP reg offset);
4149
4150 op_cost(100);
4151 format %{ "[$reg + $offset]" %}
4152 interface(MEMORY_INTER) %{
4153 base($reg);
4154 index(0x0);
4155 scale(0x0);
4156 disp($offset);
4157 %}
4158 %}
4159
4160 // Note: Intel has a swapped version also, like this:
4161 //operand indOffsetX(iRegI reg, immP offset) %{
4162 // constraint(ALLOC_IN_RC(int_reg));
4163 // match(AddP offset reg);
4164 //
4165 // op_cost(100);
4166 // format %{ "[$reg + $offset]" %}
4167 // interface(MEMORY_INTER) %{
4168 // base($reg);
4169 // index(0x0);
4170 // scale(0x0);
4171 // disp($offset);
4172 // %}
4173 //%}
4174 //// However, it doesn't make sense for SPARC, since
4175 // we have no particularly good way to embed oops in
4176 // single instructions.
4177
4178 // Indirect with Register Index
4179 operand indIndex(iRegP addr, iRegX index) %{
4180 constraint(ALLOC_IN_RC(ptr_reg));
4181 match(AddP addr index);
4182
4183 op_cost(100);
4184 format %{ "[$addr + $index]" %}
4185 interface(MEMORY_INTER) %{
4186 base($addr);
4187 index($index);
4188 scale(0x0);
4189 disp(0x0);
4190 %}
4191 %}
4192
4193 //----------Special Memory Operands--------------------------------------------
4194 // Stack Slot Operand - This operand is used for loading and storing temporary
4195 // values on the stack where a match requires a value to
4196 // flow through memory.
4197 operand stackSlotI(sRegI reg) %{
4198 constraint(ALLOC_IN_RC(stack_slots));
4199 op_cost(100);
4200 //match(RegI);
4201 format %{ "[$reg]" %}
4202 interface(MEMORY_INTER) %{
4203 base(0xE); // R_SP
4204 index(0x0);
4205 scale(0x0);
4206 disp($reg); // Stack Offset
4207 %}
4208 %}
4209
4210 operand stackSlotP(sRegP reg) %{
4211 constraint(ALLOC_IN_RC(stack_slots));
4212 op_cost(100);
4213 //match(RegP);
4214 format %{ "[$reg]" %}
4215 interface(MEMORY_INTER) %{
4216 base(0xE); // R_SP
4217 index(0x0);
4218 scale(0x0);
4219 disp($reg); // Stack Offset
4220 %}
4221 %}
4222
4223 operand stackSlotF(sRegF reg) %{
4224 constraint(ALLOC_IN_RC(stack_slots));
4225 op_cost(100);
4226 //match(RegF);
4227 format %{ "[$reg]" %}
4228 interface(MEMORY_INTER) %{
4229 base(0xE); // R_SP
4230 index(0x0);
4231 scale(0x0);
4232 disp($reg); // Stack Offset
4233 %}
4234 %}
4235 operand stackSlotD(sRegD reg) %{
4236 constraint(ALLOC_IN_RC(stack_slots));
4237 op_cost(100);
4238 //match(RegD);
4239 format %{ "[$reg]" %}
4240 interface(MEMORY_INTER) %{
4241 base(0xE); // R_SP
4242 index(0x0);
4243 scale(0x0);
4244 disp($reg); // Stack Offset
4245 %}
4246 %}
4247 operand stackSlotL(sRegL reg) %{
4248 constraint(ALLOC_IN_RC(stack_slots));
4249 op_cost(100);
4250 //match(RegL);
4251 format %{ "[$reg]" %}
4252 interface(MEMORY_INTER) %{
4253 base(0xE); // R_SP
4254 index(0x0);
4255 scale(0x0);
4256 disp($reg); // Stack Offset
4257 %}
4258 %}
4259
4260 // Operands for expressing Control Flow
4261 // NOTE: Label is a predefined operand which should not be redefined in
4262 // the AD file. It is generically handled within the ADLC.
4263
4264 //----------Conditional Branch Operands----------------------------------------
4265 // Comparison Op - This is the operation of the comparison, and is limited to
4266 // the following set of codes:
4267 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4268 //
4269 // Other attributes of the comparison, such as unsignedness, are specified
4270 // by the comparison instruction that sets a condition code flags register.
4271 // That result is represented by a flags operand whose subtype is appropriate
4272 // to the unsignedness (etc.) of the comparison.
4273 //
4274 // Later, the instruction which matches both the Comparison Op (a Bool) and
4275 // the flags (produced by the Cmp) specifies the coding of the comparison op
4276 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4277
4278 operand cmpOp() %{
4279 match(Bool);
4280
4281 format %{ "" %}
4282 interface(COND_INTER) %{
4283 equal(0x1);
4284 not_equal(0x9);
4285 less(0x3);
4286 greater_equal(0xB);
4287 less_equal(0x2);
4288 greater(0xA);
4289 overflow(0x7);
4290 no_overflow(0xF);
4291 %}
4292 %}
4293
4294 // Comparison Op, unsigned
4295 operand cmpOpU() %{
4296 match(Bool);
4297 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4298 n->as_Bool()->_test._test != BoolTest::no_overflow);
4299
4300 format %{ "u" %}
4301 interface(COND_INTER) %{
4302 equal(0x1);
4303 not_equal(0x9);
4304 less(0x5);
4305 greater_equal(0xD);
4306 less_equal(0x4);
4307 greater(0xC);
4308 overflow(0x7);
4309 no_overflow(0xF);
4310 %}
4311 %}
4312
4313 // Comparison Op, pointer (same as unsigned)
4314 operand cmpOpP() %{
4315 match(Bool);
4316 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4317 n->as_Bool()->_test._test != BoolTest::no_overflow);
4318
4319 format %{ "p" %}
4320 interface(COND_INTER) %{
4321 equal(0x1);
4322 not_equal(0x9);
4323 less(0x5);
4324 greater_equal(0xD);
4325 less_equal(0x4);
4326 greater(0xC);
4327 overflow(0x7);
4328 no_overflow(0xF);
4329 %}
4330 %}
4331
4332 // Comparison Op, branch-register encoding
4333 operand cmpOp_reg() %{
4334 match(Bool);
4335 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4336 n->as_Bool()->_test._test != BoolTest::no_overflow);
4337
4338 format %{ "" %}
4339 interface(COND_INTER) %{
4340 equal (0x1);
4341 not_equal (0x5);
4342 less (0x3);
4343 greater_equal(0x7);
4344 less_equal (0x2);
4345 greater (0x6);
4346 overflow(0x7); // not supported
4347 no_overflow(0xF); // not supported
4348 %}
4349 %}
4350
4351 // Comparison Code, floating, unordered same as less
4352 operand cmpOpF() %{
4353 match(Bool);
4354 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4355 n->as_Bool()->_test._test != BoolTest::no_overflow);
4356
4357 format %{ "fl" %}
4358 interface(COND_INTER) %{
4359 equal(0x9);
4360 not_equal(0x1);
4361 less(0x3);
4362 greater_equal(0xB);
4363 less_equal(0xE);
4364 greater(0x6);
4365
4366 overflow(0x7); // not supported
4367 no_overflow(0xF); // not supported
4368 %}
4369 %}
4370
4371 // Used by long compare
4372 operand cmpOp_commute() %{
4373 match(Bool);
4374 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4375 n->as_Bool()->_test._test != BoolTest::no_overflow);
4376
4377 format %{ "" %}
4378 interface(COND_INTER) %{
4379 equal(0x1);
4380 not_equal(0x9);
4381 less(0xA);
4382 greater_equal(0x2);
4383 less_equal(0xB);
4384 greater(0x3);
4385 overflow(0x7);
4386 no_overflow(0xF);
4387 %}
4388 %}
4389
4390 //----------OPERAND CLASSES----------------------------------------------------
4391 // Operand Classes are groups of operands that are used to simplify
4392 // instruction definitions by not requiring the AD writer to specify separate
4393 // instructions for every form of operand when the instruction accepts
4394 // multiple operand types with the same basic encoding and format. The classic
4395 // case of this is memory operands.
4396 opclass memory( indirect, indOffset13, indIndex );
4397 opclass indIndexMemory( indIndex );
4398
4399 //----------PIPELINE-----------------------------------------------------------
4400 pipeline %{
4401
4402 //----------ATTRIBUTES---------------------------------------------------------
4403 attributes %{
4404 fixed_size_instructions; // Fixed size instructions
4405 branch_has_delay_slot; // Branch has delay slot following
4406 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4407 instruction_unit_size = 4; // An instruction is 4 bytes long
4408 instruction_fetch_unit_size = 16; // The processor fetches one line
4409 instruction_fetch_units = 1; // of 16 bytes
4410
4411 // List of nop instructions
4412 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4413 %}
4414
4415 //----------RESOURCES----------------------------------------------------------
4416 // Resources are the functional units available to the machine
4417 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4418
4419 //----------PIPELINE DESCRIPTION-----------------------------------------------
4420 // Pipeline Description specifies the stages in the machine's pipeline
4421
4422 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4423
4424 //----------PIPELINE CLASSES---------------------------------------------------
4425 // Pipeline Classes describe the stages in which input and output are
4426 // referenced by the hardware pipeline.
4427
4428 // Integer ALU reg-reg operation
4429 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4430 single_instruction;
4431 dst : E(write);
4432 src1 : R(read);
4433 src2 : R(read);
4434 IALU : R;
4435 %}
4436
4437 // Integer ALU reg-reg long operation
4438 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4439 instruction_count(2);
4440 dst : E(write);
4441 src1 : R(read);
4442 src2 : R(read);
4443 IALU : R;
4444 IALU : R;
4445 %}
4446
4447 // Integer ALU reg-reg long dependent operation
4448 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4449 instruction_count(1); multiple_bundles;
4450 dst : E(write);
4451 src1 : R(read);
4452 src2 : R(read);
4453 cr : E(write);
4454 IALU : R(2);
4455 %}
4456
4457 // Integer ALU reg-imm operaion
4458 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4459 single_instruction;
4460 dst : E(write);
4461 src1 : R(read);
4462 IALU : R;
4463 %}
4464
4465 // Integer ALU reg-reg operation with condition code
4466 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4467 single_instruction;
4468 dst : E(write);
4469 cr : E(write);
4470 src1 : R(read);
4471 src2 : R(read);
4472 IALU : R;
4473 %}
4474
4475 // Integer ALU reg-imm operation with condition code
4476 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4477 single_instruction;
4478 dst : E(write);
4479 cr : E(write);
4480 src1 : R(read);
4481 IALU : R;
4482 %}
4483
4484 // Integer ALU zero-reg operation
4485 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4486 single_instruction;
4487 dst : E(write);
4488 src2 : R(read);
4489 IALU : R;
4490 %}
4491
4492 // Integer ALU zero-reg operation with condition code only
4493 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4494 single_instruction;
4495 cr : E(write);
4496 src : R(read);
4497 IALU : R;
4498 %}
4499
4500 // Integer ALU reg-reg operation with condition code only
4501 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4502 single_instruction;
4503 cr : E(write);
4504 src1 : R(read);
4505 src2 : R(read);
4506 IALU : R;
4507 %}
4508
4509 // Integer ALU reg-imm operation with condition code only
4510 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4511 single_instruction;
4512 cr : E(write);
4513 src1 : R(read);
4514 IALU : R;
4515 %}
4516
4517 // Integer ALU reg-reg-zero operation with condition code only
4518 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4519 single_instruction;
4520 cr : E(write);
4521 src1 : R(read);
4522 src2 : R(read);
4523 IALU : R;
4524 %}
4525
4526 // Integer ALU reg-imm-zero operation with condition code only
4527 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4528 single_instruction;
4529 cr : E(write);
4530 src1 : R(read);
4531 IALU : R;
4532 %}
4533
4534 // Integer ALU reg-reg operation with condition code, src1 modified
4535 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4536 single_instruction;
4537 cr : E(write);
4538 src1 : E(write);
4539 src1 : R(read);
4540 src2 : R(read);
4541 IALU : R;
4542 %}
4543
4544 // Integer ALU reg-imm operation with condition code, src1 modified
4545 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4546 single_instruction;
4547 cr : E(write);
4548 src1 : E(write);
4549 src1 : R(read);
4550 IALU : R;
4551 %}
4552
4553 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4554 multiple_bundles;
4555 dst : E(write)+4;
4556 cr : E(write);
4557 src1 : R(read);
4558 src2 : R(read);
4559 IALU : R(3);
4560 BR : R(2);
4561 %}
4562
4563 // Integer ALU operation
4564 pipe_class ialu_none(iRegI dst) %{
4565 single_instruction;
4566 dst : E(write);
4567 IALU : R;
4568 %}
4569
4570 // Integer ALU reg operation
4571 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4572 single_instruction; may_have_no_code;
4573 dst : E(write);
4574 src : R(read);
4575 IALU : R;
4576 %}
4577
4578 // Integer ALU reg conditional operation
4579 // This instruction has a 1 cycle stall, and cannot execute
4580 // in the same cycle as the instruction setting the condition
4581 // code. We kludge this by pretending to read the condition code
4582 // 1 cycle earlier, and by marking the functional units as busy
4583 // for 2 cycles with the result available 1 cycle later than
4584 // is really the case.
4585 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4586 single_instruction;
4587 op2_out : C(write);
4588 op1 : R(read);
4589 cr : R(read); // This is really E, with a 1 cycle stall
4590 BR : R(2);
4591 MS : R(2);
4592 %}
4593
4594 #ifdef _LP64
4595 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4596 instruction_count(1); multiple_bundles;
4597 dst : C(write)+1;
4598 src : R(read)+1;
4599 IALU : R(1);
4600 BR : E(2);
4601 MS : E(2);
4602 %}
4603 #endif
4604
4605 // Integer ALU reg operation
4606 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4607 single_instruction; may_have_no_code;
4608 dst : E(write);
4609 src : R(read);
4610 IALU : R;
4611 %}
4612 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4613 single_instruction; may_have_no_code;
4614 dst : E(write);
4615 src : R(read);
4616 IALU : R;
4617 %}
4618
4619 // Two integer ALU reg operations
4620 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4621 instruction_count(2);
4622 dst : E(write);
4623 src : R(read);
4624 A0 : R;
4625 A1 : R;
4626 %}
4627
4628 // Two integer ALU reg operations
4629 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4630 instruction_count(2); may_have_no_code;
4631 dst : E(write);
4632 src : R(read);
4633 A0 : R;
4634 A1 : R;
4635 %}
4636
4637 // Integer ALU imm operation
4638 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4639 single_instruction;
4640 dst : E(write);
4641 IALU : R;
4642 %}
4643
4644 // Integer ALU reg-reg with carry operation
4645 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4646 single_instruction;
4647 dst : E(write);
4648 src1 : R(read);
4649 src2 : R(read);
4650 IALU : R;
4651 %}
4652
4653 // Integer ALU cc operation
4654 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4655 single_instruction;
4656 dst : E(write);
4657 cc : R(read);
4658 IALU : R;
4659 %}
4660
4661 // Integer ALU cc / second IALU operation
4662 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4663 instruction_count(1); multiple_bundles;
4664 dst : E(write)+1;
4665 src : R(read);
4666 IALU : R;
4667 %}
4668
4669 // Integer ALU cc / second IALU operation
4670 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4671 instruction_count(1); multiple_bundles;
4672 dst : E(write)+1;
4673 p : R(read);
4674 q : R(read);
4675 IALU : R;
4676 %}
4677
4678 // Integer ALU hi-lo-reg operation
4679 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4680 instruction_count(1); multiple_bundles;
4681 dst : E(write)+1;
4682 IALU : R(2);
4683 %}
4684
4685 // Float ALU hi-lo-reg operation (with temp)
4686 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4687 instruction_count(1); multiple_bundles;
4688 dst : E(write)+1;
4689 IALU : R(2);
4690 %}
4691
4692 // Long Constant
4693 pipe_class loadConL( iRegL dst, immL src ) %{
4694 instruction_count(2); multiple_bundles;
4695 dst : E(write)+1;
4696 IALU : R(2);
4697 IALU : R(2);
4698 %}
4699
4700 // Pointer Constant
4701 pipe_class loadConP( iRegP dst, immP src ) %{
4702 instruction_count(0); multiple_bundles;
4703 fixed_latency(6);
4704 %}
4705
4706 // Polling Address
4707 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4708 #ifdef _LP64
4709 instruction_count(0); multiple_bundles;
4710 fixed_latency(6);
4711 #else
4712 dst : E(write);
4713 IALU : R;
4714 #endif
4715 %}
4716
4717 // Long Constant small
4718 pipe_class loadConLlo( iRegL dst, immL src ) %{
4719 instruction_count(2);
4720 dst : E(write);
4721 IALU : R;
4722 IALU : R;
4723 %}
4724
4725 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4726 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4727 instruction_count(1); multiple_bundles;
4728 src : R(read);
4729 dst : M(write)+1;
4730 IALU : R;
4731 MS : E;
4732 %}
4733
4734 // Integer ALU nop operation
4735 pipe_class ialu_nop() %{
4736 single_instruction;
4737 IALU : R;
4738 %}
4739
4740 // Integer ALU nop operation
4741 pipe_class ialu_nop_A0() %{
4742 single_instruction;
4743 A0 : R;
4744 %}
4745
4746 // Integer ALU nop operation
4747 pipe_class ialu_nop_A1() %{
4748 single_instruction;
4749 A1 : R;
4750 %}
4751
4752 // Integer Multiply reg-reg operation
4753 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4754 single_instruction;
4755 dst : E(write);
4756 src1 : R(read);
4757 src2 : R(read);
4758 MS : R(5);
4759 %}
4760
4761 // Integer Multiply reg-imm operation
4762 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4763 single_instruction;
4764 dst : E(write);
4765 src1 : R(read);
4766 MS : R(5);
4767 %}
4768
4769 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4770 single_instruction;
4771 dst : E(write)+4;
4772 src1 : R(read);
4773 src2 : R(read);
4774 MS : R(6);
4775 %}
4776
4777 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4778 single_instruction;
4779 dst : E(write)+4;
4780 src1 : R(read);
4781 MS : R(6);
4782 %}
4783
4784 // Integer Divide reg-reg
4785 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4786 instruction_count(1); multiple_bundles;
4787 dst : E(write);
4788 temp : E(write);
4789 src1 : R(read);
4790 src2 : R(read);
4791 temp : R(read);
4792 MS : R(38);
4793 %}
4794
4795 // Integer Divide reg-imm
4796 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4797 instruction_count(1); multiple_bundles;
4798 dst : E(write);
4799 temp : E(write);
4800 src1 : R(read);
4801 temp : R(read);
4802 MS : R(38);
4803 %}
4804
4805 // Long Divide
4806 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4807 dst : E(write)+71;
4808 src1 : R(read);
4809 src2 : R(read)+1;
4810 MS : R(70);
4811 %}
4812
4813 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4814 dst : E(write)+71;
4815 src1 : R(read);
4816 MS : R(70);
4817 %}
4818
4819 // Floating Point Add Float
4820 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4821 single_instruction;
4822 dst : X(write);
4823 src1 : E(read);
4824 src2 : E(read);
4825 FA : R;
4826 %}
4827
4828 // Floating Point Add Double
4829 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4830 single_instruction;
4831 dst : X(write);
4832 src1 : E(read);
4833 src2 : E(read);
4834 FA : R;
4835 %}
4836
4837 // Floating Point Conditional Move based on integer flags
4838 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4839 single_instruction;
4840 dst : X(write);
4841 src : E(read);
4842 cr : R(read);
4843 FA : R(2);
4844 BR : R(2);
4845 %}
4846
4847 // Floating Point Conditional Move based on integer flags
4848 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4849 single_instruction;
4850 dst : X(write);
4851 src : E(read);
4852 cr : R(read);
4853 FA : R(2);
4854 BR : R(2);
4855 %}
4856
4857 // Floating Point Multiply Float
4858 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4859 single_instruction;
4860 dst : X(write);
4861 src1 : E(read);
4862 src2 : E(read);
4863 FM : R;
4864 %}
4865
4866 // Floating Point Multiply Double
4867 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4868 single_instruction;
4869 dst : X(write);
4870 src1 : E(read);
4871 src2 : E(read);
4872 FM : R;
4873 %}
4874
4875 // Floating Point Divide Float
4876 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4877 single_instruction;
4878 dst : X(write);
4879 src1 : E(read);
4880 src2 : E(read);
4881 FM : R;
4882 FDIV : C(14);
4883 %}
4884
4885 // Floating Point Divide Double
4886 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4887 single_instruction;
4888 dst : X(write);
4889 src1 : E(read);
4890 src2 : E(read);
4891 FM : R;
4892 FDIV : C(17);
4893 %}
4894
4895 // Floating Point Move/Negate/Abs Float
4896 pipe_class faddF_reg(regF dst, regF src) %{
4897 single_instruction;
4898 dst : W(write);
4899 src : E(read);
4900 FA : R(1);
4901 %}
4902
4903 // Floating Point Move/Negate/Abs Double
4904 pipe_class faddD_reg(regD dst, regD src) %{
4905 single_instruction;
4906 dst : W(write);
4907 src : E(read);
4908 FA : R;
4909 %}
4910
4911 // Floating Point Convert F->D
4912 pipe_class fcvtF2D(regD dst, regF src) %{
4913 single_instruction;
4914 dst : X(write);
4915 src : E(read);
4916 FA : R;
4917 %}
4918
4919 // Floating Point Convert I->D
4920 pipe_class fcvtI2D(regD dst, regF src) %{
4921 single_instruction;
4922 dst : X(write);
4923 src : E(read);
4924 FA : R;
4925 %}
4926
4927 // Floating Point Convert LHi->D
4928 pipe_class fcvtLHi2D(regD dst, regD src) %{
4929 single_instruction;
4930 dst : X(write);
4931 src : E(read);
4932 FA : R;
4933 %}
4934
4935 // Floating Point Convert L->D
4936 pipe_class fcvtL2D(regD dst, regF src) %{
4937 single_instruction;
4938 dst : X(write);
4939 src : E(read);
4940 FA : R;
4941 %}
4942
4943 // Floating Point Convert L->F
4944 pipe_class fcvtL2F(regD dst, regF src) %{
4945 single_instruction;
4946 dst : X(write);
4947 src : E(read);
4948 FA : R;
4949 %}
4950
4951 // Floating Point Convert D->F
4952 pipe_class fcvtD2F(regD dst, regF src) %{
4953 single_instruction;
4954 dst : X(write);
4955 src : E(read);
4956 FA : R;
4957 %}
4958
4959 // Floating Point Convert I->L
4960 pipe_class fcvtI2L(regD dst, regF src) %{
4961 single_instruction;
4962 dst : X(write);
4963 src : E(read);
4964 FA : R;
4965 %}
4966
4967 // Floating Point Convert D->F
4968 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4969 instruction_count(1); multiple_bundles;
4970 dst : X(write)+6;
4971 src : E(read);
4972 FA : R;
4973 %}
4974
4975 // Floating Point Convert D->L
4976 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4977 instruction_count(1); multiple_bundles;
4978 dst : X(write)+6;
4979 src : E(read);
4980 FA : R;
4981 %}
4982
4983 // Floating Point Convert F->I
4984 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4985 instruction_count(1); multiple_bundles;
4986 dst : X(write)+6;
4987 src : E(read);
4988 FA : R;
4989 %}
4990
4991 // Floating Point Convert F->L
4992 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4993 instruction_count(1); multiple_bundles;
4994 dst : X(write)+6;
4995 src : E(read);
4996 FA : R;
4997 %}
4998
4999 // Floating Point Convert I->F
5000 pipe_class fcvtI2F(regF dst, regF src) %{
5001 single_instruction;
5002 dst : X(write);
5003 src : E(read);
5004 FA : R;
5005 %}
5006
5007 // Floating Point Compare
5008 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5009 single_instruction;
5010 cr : X(write);
5011 src1 : E(read);
5012 src2 : E(read);
5013 FA : R;
5014 %}
5015
5016 // Floating Point Compare
5017 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5018 single_instruction;
5019 cr : X(write);
5020 src1 : E(read);
5021 src2 : E(read);
5022 FA : R;
5023 %}
5024
5025 // Floating Add Nop
5026 pipe_class fadd_nop() %{
5027 single_instruction;
5028 FA : R;
5029 %}
5030
5031 // Integer Store to Memory
5032 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5033 single_instruction;
5034 mem : R(read);
5035 src : C(read);
5036 MS : R;
5037 %}
5038
5039 // Integer Store to Memory
5040 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5041 single_instruction;
5042 mem : R(read);
5043 src : C(read);
5044 MS : R;
5045 %}
5046
5047 // Integer Store Zero to Memory
5048 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5049 single_instruction;
5050 mem : R(read);
5051 MS : R;
5052 %}
5053
5054 // Special Stack Slot Store
5055 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5056 single_instruction;
5057 stkSlot : R(read);
5058 src : C(read);
5059 MS : R;
5060 %}
5061
5062 // Special Stack Slot Store
5063 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5064 instruction_count(2); multiple_bundles;
5065 stkSlot : R(read);
5066 src : C(read);
5067 MS : R(2);
5068 %}
5069
5070 // Float Store
5071 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5072 single_instruction;
5073 mem : R(read);
5074 src : C(read);
5075 MS : R;
5076 %}
5077
5078 // Float Store
5079 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5080 single_instruction;
5081 mem : R(read);
5082 MS : R;
5083 %}
5084
5085 // Double Store
5086 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5087 instruction_count(1);
5088 mem : R(read);
5089 src : C(read);
5090 MS : R;
5091 %}
5092
5093 // Double Store
5094 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5095 single_instruction;
5096 mem : R(read);
5097 MS : R;
5098 %}
5099
5100 // Special Stack Slot Float Store
5101 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5102 single_instruction;
5103 stkSlot : R(read);
5104 src : C(read);
5105 MS : R;
5106 %}
5107
5108 // Special Stack Slot Double Store
5109 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5110 single_instruction;
5111 stkSlot : R(read);
5112 src : C(read);
5113 MS : R;
5114 %}
5115
5116 // Integer Load (when sign bit propagation not needed)
5117 pipe_class iload_mem(iRegI dst, memory mem) %{
5118 single_instruction;
5119 mem : R(read);
5120 dst : C(write);
5121 MS : R;
5122 %}
5123
5124 // Integer Load from stack operand
5125 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5126 single_instruction;
5127 mem : R(read);
5128 dst : C(write);
5129 MS : R;
5130 %}
5131
5132 // Integer Load (when sign bit propagation or masking is needed)
5133 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5134 single_instruction;
5135 mem : R(read);
5136 dst : M(write);
5137 MS : R;
5138 %}
5139
5140 // Float Load
5141 pipe_class floadF_mem(regF dst, memory mem) %{
5142 single_instruction;
5143 mem : R(read);
5144 dst : M(write);
5145 MS : R;
5146 %}
5147
5148 // Float Load
5149 pipe_class floadD_mem(regD dst, memory mem) %{
5150 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5151 mem : R(read);
5152 dst : M(write);
5153 MS : R;
5154 %}
5155
5156 // Float Load
5157 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5158 single_instruction;
5159 stkSlot : R(read);
5160 dst : M(write);
5161 MS : R;
5162 %}
5163
5164 // Float Load
5165 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5166 single_instruction;
5167 stkSlot : R(read);
5168 dst : M(write);
5169 MS : R;
5170 %}
5171
5172 // Memory Nop
5173 pipe_class mem_nop() %{
5174 single_instruction;
5175 MS : R;
5176 %}
5177
5178 pipe_class sethi(iRegP dst, immI src) %{
5179 single_instruction;
5180 dst : E(write);
5181 IALU : R;
5182 %}
5183
5184 pipe_class loadPollP(iRegP poll) %{
5185 single_instruction;
5186 poll : R(read);
5187 MS : R;
5188 %}
5189
5190 pipe_class br(Universe br, label labl) %{
5191 single_instruction_with_delay_slot;
5192 BR : R;
5193 %}
5194
5195 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5196 single_instruction_with_delay_slot;
5197 cr : E(read);
5198 BR : R;
5199 %}
5200
5201 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5202 single_instruction_with_delay_slot;
5203 op1 : E(read);
5204 BR : R;
5205 MS : R;
5206 %}
5207
5208 // Compare and branch
5209 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5210 instruction_count(2); has_delay_slot;
5211 cr : E(write);
5212 src1 : R(read);
5213 src2 : R(read);
5214 IALU : R;
5215 BR : R;
5216 %}
5217
5218 // Compare and branch
5219 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5220 instruction_count(2); has_delay_slot;
5221 cr : E(write);
5222 src1 : R(read);
5223 IALU : R;
5224 BR : R;
5225 %}
5226
5227 // Compare and branch using cbcond
5228 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5229 single_instruction;
5230 src1 : E(read);
5231 src2 : E(read);
5232 IALU : R;
5233 BR : R;
5234 %}
5235
5236 // Compare and branch using cbcond
5237 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5238 single_instruction;
5239 src1 : E(read);
5240 IALU : R;
5241 BR : R;
5242 %}
5243
5244 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5245 single_instruction_with_delay_slot;
5246 cr : E(read);
5247 BR : R;
5248 %}
5249
5250 pipe_class br_nop() %{
5251 single_instruction;
5252 BR : R;
5253 %}
5254
5255 pipe_class simple_call(method meth) %{
5256 instruction_count(2); multiple_bundles; force_serialization;
5257 fixed_latency(100);
5258 BR : R(1);
5259 MS : R(1);
5260 A0 : R(1);
5261 %}
5262
5263 pipe_class compiled_call(method meth) %{
5264 instruction_count(1); multiple_bundles; force_serialization;
5265 fixed_latency(100);
5266 MS : R(1);
5267 %}
5268
5269 pipe_class call(method meth) %{
5270 instruction_count(0); multiple_bundles; force_serialization;
5271 fixed_latency(100);
5272 %}
5273
5274 pipe_class tail_call(Universe ignore, label labl) %{
5275 single_instruction; has_delay_slot;
5276 fixed_latency(100);
5277 BR : R(1);
5278 MS : R(1);
5279 %}
5280
5281 pipe_class ret(Universe ignore) %{
5282 single_instruction; has_delay_slot;
5283 BR : R(1);
5284 MS : R(1);
5285 %}
5286
5287 pipe_class ret_poll(g3RegP poll) %{
5288 instruction_count(3); has_delay_slot;
5289 poll : E(read);
5290 MS : R;
5291 %}
5292
5293 // The real do-nothing guy
5294 pipe_class empty( ) %{
5295 instruction_count(0);
5296 %}
5297
5298 pipe_class long_memory_op() %{
5299 instruction_count(0); multiple_bundles; force_serialization;
5300 fixed_latency(25);
5301 MS : R(1);
5302 %}
5303
5304 // Check-cast
5305 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5306 array : R(read);
5307 match : R(read);
5308 IALU : R(2);
5309 BR : R(2);
5310 MS : R;
5311 %}
5312
5313 // Convert FPU flags into +1,0,-1
5314 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5315 src1 : E(read);
5316 src2 : E(read);
5317 dst : E(write);
5318 FA : R;
5319 MS : R(2);
5320 BR : R(2);
5321 %}
5322
5323 // Compare for p < q, and conditionally add y
5324 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5325 p : E(read);
5326 q : E(read);
5327 y : E(read);
5328 IALU : R(3)
5329 %}
5330
5331 // Perform a compare, then move conditionally in a branch delay slot.
5332 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5333 src2 : E(read);
5334 srcdst : E(read);
5335 IALU : R;
5336 BR : R;
5337 %}
5338
5339 // Define the class for the Nop node
5340 define %{
5341 MachNop = ialu_nop;
5342 %}
5343
5344 %}
5345
5346 //----------INSTRUCTIONS-------------------------------------------------------
5347
5348 //------------Special Stack Slot instructions - no match rules-----------------
5349 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5350 // No match rule to avoid chain rule match.
5351 effect(DEF dst, USE src);
5352 ins_cost(MEMORY_REF_COST);
5353 size(4);
5354 format %{ "LDF $src,$dst\t! stkI to regF" %}
5355 opcode(Assembler::ldf_op3);
5356 ins_encode(simple_form3_mem_reg(src, dst));
5357 ins_pipe(floadF_stk);
5358 %}
5359
5360 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5361 // No match rule to avoid chain rule match.
5362 effect(DEF dst, USE src);
5363 ins_cost(MEMORY_REF_COST);
5364 size(4);
5365 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5366 opcode(Assembler::lddf_op3);
5367 ins_encode(simple_form3_mem_reg(src, dst));
5368 ins_pipe(floadD_stk);
5369 %}
5370
5371 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5372 // No match rule to avoid chain rule match.
5373 effect(DEF dst, USE src);
5374 ins_cost(MEMORY_REF_COST);
5375 size(4);
5376 format %{ "STF $src,$dst\t! regF to stkI" %}
5377 opcode(Assembler::stf_op3);
5378 ins_encode(simple_form3_mem_reg(dst, src));
5379 ins_pipe(fstoreF_stk_reg);
5380 %}
5381
5382 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5383 // No match rule to avoid chain rule match.
5384 effect(DEF dst, USE src);
5385 ins_cost(MEMORY_REF_COST);
5386 size(4);
5387 format %{ "STDF $src,$dst\t! regD to stkL" %}
5388 opcode(Assembler::stdf_op3);
5389 ins_encode(simple_form3_mem_reg(dst, src));
5390 ins_pipe(fstoreD_stk_reg);
5391 %}
5392
5393 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5394 effect(DEF dst, USE src);
5395 ins_cost(MEMORY_REF_COST*2);
5396 size(8);
5397 format %{ "STW $src,$dst.hi\t! long\n\t"
5398 "STW R_G0,$dst.lo" %}
5399 opcode(Assembler::stw_op3);
5400 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5401 ins_pipe(lstoreI_stk_reg);
5402 %}
5403
5404 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5405 // No match rule to avoid chain rule match.
5406 effect(DEF dst, USE src);
5407 ins_cost(MEMORY_REF_COST);
5408 size(4);
5409 format %{ "STX $src,$dst\t! regL to stkD" %}
5410 opcode(Assembler::stx_op3);
5411 ins_encode(simple_form3_mem_reg( dst, src ) );
5412 ins_pipe(istore_stk_reg);
5413 %}
5414
5415 //---------- Chain stack slots between similar types --------
5416
5417 // Load integer from stack slot
5418 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5419 match(Set dst src);
5420 ins_cost(MEMORY_REF_COST);
5421
5422 size(4);
5423 format %{ "LDUW $src,$dst\t!stk" %}
5424 opcode(Assembler::lduw_op3);
5425 ins_encode(simple_form3_mem_reg( src, dst ) );
5426 ins_pipe(iload_mem);
5427 %}
5428
5429 // Store integer to stack slot
5430 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5431 match(Set dst src);
5432 ins_cost(MEMORY_REF_COST);
5433
5434 size(4);
5435 format %{ "STW $src,$dst\t!stk" %}
5436 opcode(Assembler::stw_op3);
5437 ins_encode(simple_form3_mem_reg( dst, src ) );
5438 ins_pipe(istore_mem_reg);
5439 %}
5440
5441 // Load long from stack slot
5442 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5443 match(Set dst src);
5444
5445 ins_cost(MEMORY_REF_COST);
5446 size(4);
5447 format %{ "LDX $src,$dst\t! long" %}
5448 opcode(Assembler::ldx_op3);
5449 ins_encode(simple_form3_mem_reg( src, dst ) );
5450 ins_pipe(iload_mem);
5451 %}
5452
5453 // Store long to stack slot
5454 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5455 match(Set dst src);
5456
5457 ins_cost(MEMORY_REF_COST);
5458 size(4);
5459 format %{ "STX $src,$dst\t! long" %}
5460 opcode(Assembler::stx_op3);
5461 ins_encode(simple_form3_mem_reg( dst, src ) );
5462 ins_pipe(istore_mem_reg);
5463 %}
5464
5465 #ifdef _LP64
5466 // Load pointer from stack slot, 64-bit encoding
5467 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5468 match(Set dst src);
5469 ins_cost(MEMORY_REF_COST);
5470 size(4);
5471 format %{ "LDX $src,$dst\t!ptr" %}
5472 opcode(Assembler::ldx_op3);
5473 ins_encode(simple_form3_mem_reg( src, dst ) );
5474 ins_pipe(iload_mem);
5475 %}
5476
5477 // Store pointer to stack slot
5478 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5479 match(Set dst src);
5480 ins_cost(MEMORY_REF_COST);
5481 size(4);
5482 format %{ "STX $src,$dst\t!ptr" %}
5483 opcode(Assembler::stx_op3);
5484 ins_encode(simple_form3_mem_reg( dst, src ) );
5485 ins_pipe(istore_mem_reg);
5486 %}
5487 #else // _LP64
5488 // Load pointer from stack slot, 32-bit encoding
5489 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5490 match(Set dst src);
5491 ins_cost(MEMORY_REF_COST);
5492 format %{ "LDUW $src,$dst\t!ptr" %}
5493 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5494 ins_encode(simple_form3_mem_reg( src, dst ) );
5495 ins_pipe(iload_mem);
5496 %}
5497
5498 // Store pointer to stack slot
5499 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5500 match(Set dst src);
5501 ins_cost(MEMORY_REF_COST);
5502 format %{ "STW $src,$dst\t!ptr" %}
5503 opcode(Assembler::stw_op3, Assembler::ldst_op);
5504 ins_encode(simple_form3_mem_reg( dst, src ) );
5505 ins_pipe(istore_mem_reg);
5506 %}
5507 #endif // _LP64
5508
5509 //------------Special Nop instructions for bundling - no match rules-----------
5510 // Nop using the A0 functional unit
5511 instruct Nop_A0() %{
5512 ins_cost(0);
5513
5514 format %{ "NOP ! Alu Pipeline" %}
5515 opcode(Assembler::or_op3, Assembler::arith_op);
5516 ins_encode( form2_nop() );
5517 ins_pipe(ialu_nop_A0);
5518 %}
5519
5520 // Nop using the A1 functional unit
5521 instruct Nop_A1( ) %{
5522 ins_cost(0);
5523
5524 format %{ "NOP ! Alu Pipeline" %}
5525 opcode(Assembler::or_op3, Assembler::arith_op);
5526 ins_encode( form2_nop() );
5527 ins_pipe(ialu_nop_A1);
5528 %}
5529
5530 // Nop using the memory functional unit
5531 instruct Nop_MS( ) %{
5532 ins_cost(0);
5533
5534 format %{ "NOP ! Memory Pipeline" %}
5535 ins_encode( emit_mem_nop );
5536 ins_pipe(mem_nop);
5537 %}
5538
5539 // Nop using the floating add functional unit
5540 instruct Nop_FA( ) %{
5541 ins_cost(0);
5542
5543 format %{ "NOP ! Floating Add Pipeline" %}
5544 ins_encode( emit_fadd_nop );
5545 ins_pipe(fadd_nop);
5546 %}
5547
5548 // Nop using the branch functional unit
5549 instruct Nop_BR( ) %{
5550 ins_cost(0);
5551
5552 format %{ "NOP ! Branch Pipeline" %}
5553 ins_encode( emit_br_nop );
5554 ins_pipe(br_nop);
5555 %}
5556
5557 //----------Load/Store/Move Instructions---------------------------------------
5558 //----------Load Instructions--------------------------------------------------
5559 // Load Byte (8bit signed)
5560 instruct loadB(iRegI dst, memory mem) %{
5561 match(Set dst (LoadB mem));
5562 ins_cost(MEMORY_REF_COST);
5563
5564 size(4);
5565 format %{ "LDSB $mem,$dst\t! byte" %}
5566 ins_encode %{
5567 __ ldsb($mem$$Address, $dst$$Register);
5568 %}
5569 ins_pipe(iload_mask_mem);
5570 %}
5571
5572 // Load Byte (8bit signed) into a Long Register
5573 instruct loadB2L(iRegL dst, memory mem) %{
5574 match(Set dst (ConvI2L (LoadB mem)));
5575 ins_cost(MEMORY_REF_COST);
5576
5577 size(4);
5578 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5579 ins_encode %{
5580 __ ldsb($mem$$Address, $dst$$Register);
5581 %}
5582 ins_pipe(iload_mask_mem);
5583 %}
5584
5585 // Load Unsigned Byte (8bit UNsigned) into an int reg
5586 instruct loadUB(iRegI dst, memory mem) %{
5587 match(Set dst (LoadUB mem));
5588 ins_cost(MEMORY_REF_COST);
5589
5590 size(4);
5591 format %{ "LDUB $mem,$dst\t! ubyte" %}
5592 ins_encode %{
5593 __ ldub($mem$$Address, $dst$$Register);
5594 %}
5595 ins_pipe(iload_mem);
5596 %}
5597
5598 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5599 instruct loadUB2L(iRegL dst, memory mem) %{
5600 match(Set dst (ConvI2L (LoadUB mem)));
5601 ins_cost(MEMORY_REF_COST);
5602
5603 size(4);
5604 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5605 ins_encode %{
5606 __ ldub($mem$$Address, $dst$$Register);
5607 %}
5608 ins_pipe(iload_mem);
5609 %}
5610
5611 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5612 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5613 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5614 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5615
5616 size(2*4);
5617 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5618 "AND $dst,$mask,$dst" %}
5619 ins_encode %{
5620 __ ldub($mem$$Address, $dst$$Register);
5621 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5622 %}
5623 ins_pipe(iload_mem);
5624 %}
5625
5626 // Load Short (16bit signed)
5627 instruct loadS(iRegI dst, memory mem) %{
5628 match(Set dst (LoadS mem));
5629 ins_cost(MEMORY_REF_COST);
5630
5631 size(4);
5632 format %{ "LDSH $mem,$dst\t! short" %}
5633 ins_encode %{
5634 __ ldsh($mem$$Address, $dst$$Register);
5635 %}
5636 ins_pipe(iload_mask_mem);
5637 %}
5638
5639 // Load Short (16 bit signed) to Byte (8 bit signed)
5640 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5641 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5642 ins_cost(MEMORY_REF_COST);
5643
5644 size(4);
5645
5646 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5647 ins_encode %{
5648 __ ldsb($mem$$Address, $dst$$Register, 1);
5649 %}
5650 ins_pipe(iload_mask_mem);
5651 %}
5652
5653 // Load Short (16bit signed) into a Long Register
5654 instruct loadS2L(iRegL dst, memory mem) %{
5655 match(Set dst (ConvI2L (LoadS mem)));
5656 ins_cost(MEMORY_REF_COST);
5657
5658 size(4);
5659 format %{ "LDSH $mem,$dst\t! short -> long" %}
5660 ins_encode %{
5661 __ ldsh($mem$$Address, $dst$$Register);
5662 %}
5663 ins_pipe(iload_mask_mem);
5664 %}
5665
5666 // Load Unsigned Short/Char (16bit UNsigned)
5667 instruct loadUS(iRegI dst, memory mem) %{
5668 match(Set dst (LoadUS mem));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 size(4);
5672 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5673 ins_encode %{
5674 __ lduh($mem$$Address, $dst$$Register);
5675 %}
5676 ins_pipe(iload_mem);
5677 %}
5678
5679 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5680 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5681 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5682 ins_cost(MEMORY_REF_COST);
5683
5684 size(4);
5685 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5686 ins_encode %{
5687 __ ldsb($mem$$Address, $dst$$Register, 1);
5688 %}
5689 ins_pipe(iload_mask_mem);
5690 %}
5691
5692 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5693 instruct loadUS2L(iRegL dst, memory mem) %{
5694 match(Set dst (ConvI2L (LoadUS mem)));
5695 ins_cost(MEMORY_REF_COST);
5696
5697 size(4);
5698 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5699 ins_encode %{
5700 __ lduh($mem$$Address, $dst$$Register);
5701 %}
5702 ins_pipe(iload_mem);
5703 %}
5704
5705 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5706 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5707 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5708 ins_cost(MEMORY_REF_COST);
5709
5710 size(4);
5711 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5712 ins_encode %{
5713 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5714 %}
5715 ins_pipe(iload_mem);
5716 %}
5717
5718 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5719 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5720 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5721 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5722
5723 size(2*4);
5724 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5725 "AND $dst,$mask,$dst" %}
5726 ins_encode %{
5727 Register Rdst = $dst$$Register;
5728 __ lduh($mem$$Address, Rdst);
5729 __ and3(Rdst, $mask$$constant, Rdst);
5730 %}
5731 ins_pipe(iload_mem);
5732 %}
5733
5734 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5735 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5736 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5737 effect(TEMP dst, TEMP tmp);
5738 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5739
5740 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5741 "SET $mask,$tmp\n\t"
5742 "AND $dst,$tmp,$dst" %}
5743 ins_encode %{
5744 Register Rdst = $dst$$Register;
5745 Register Rtmp = $tmp$$Register;
5746 __ lduh($mem$$Address, Rdst);
5747 __ set($mask$$constant, Rtmp);
5748 __ and3(Rdst, Rtmp, Rdst);
5749 %}
5750 ins_pipe(iload_mem);
5751 %}
5752
5753 // Load Integer
5754 instruct loadI(iRegI dst, memory mem) %{
5755 match(Set dst (LoadI mem));
5756 ins_cost(MEMORY_REF_COST);
5757
5758 size(4);
5759 format %{ "LDUW $mem,$dst\t! int" %}
5760 ins_encode %{
5761 __ lduw($mem$$Address, $dst$$Register);
5762 %}
5763 ins_pipe(iload_mem);
5764 %}
5765
5766 // Load Integer to Byte (8 bit signed)
5767 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5768 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5769 ins_cost(MEMORY_REF_COST);
5770
5771 size(4);
5772
5773 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5774 ins_encode %{
5775 __ ldsb($mem$$Address, $dst$$Register, 3);
5776 %}
5777 ins_pipe(iload_mask_mem);
5778 %}
5779
5780 // Load Integer to Unsigned Byte (8 bit UNsigned)
5781 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5782 match(Set dst (AndI (LoadI mem) mask));
5783 ins_cost(MEMORY_REF_COST);
5784
5785 size(4);
5786
5787 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5788 ins_encode %{
5789 __ ldub($mem$$Address, $dst$$Register, 3);
5790 %}
5791 ins_pipe(iload_mask_mem);
5792 %}
5793
5794 // Load Integer to Short (16 bit signed)
5795 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5796 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5797 ins_cost(MEMORY_REF_COST);
5798
5799 size(4);
5800
5801 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5802 ins_encode %{
5803 __ ldsh($mem$$Address, $dst$$Register, 2);
5804 %}
5805 ins_pipe(iload_mask_mem);
5806 %}
5807
5808 // Load Integer to Unsigned Short (16 bit UNsigned)
5809 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5810 match(Set dst (AndI (LoadI mem) mask));
5811 ins_cost(MEMORY_REF_COST);
5812
5813 size(4);
5814
5815 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5816 ins_encode %{
5817 __ lduh($mem$$Address, $dst$$Register, 2);
5818 %}
5819 ins_pipe(iload_mask_mem);
5820 %}
5821
5822 // Load Integer into a Long Register
5823 instruct loadI2L(iRegL dst, memory mem) %{
5824 match(Set dst (ConvI2L (LoadI mem)));
5825 ins_cost(MEMORY_REF_COST);
5826
5827 size(4);
5828 format %{ "LDSW $mem,$dst\t! int -> long" %}
5829 ins_encode %{
5830 __ ldsw($mem$$Address, $dst$$Register);
5831 %}
5832 ins_pipe(iload_mask_mem);
5833 %}
5834
5835 // Load Integer with mask 0xFF into a Long Register
5836 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5837 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5838 ins_cost(MEMORY_REF_COST);
5839
5840 size(4);
5841 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5842 ins_encode %{
5843 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5844 %}
5845 ins_pipe(iload_mem);
5846 %}
5847
5848 // Load Integer with mask 0xFFFF into a Long Register
5849 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5851 ins_cost(MEMORY_REF_COST);
5852
5853 size(4);
5854 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5855 ins_encode %{
5856 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5857 %}
5858 ins_pipe(iload_mem);
5859 %}
5860
5861 // Load Integer with a 12-bit mask into a Long Register
5862 instruct loadI2L_immU13(iRegL dst, memory mem, immU13 mask) %{
5863 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5864 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5865
5866 size(2*4);
5867 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5868 "AND $dst,$mask,$dst" %}
5869 ins_encode %{
5870 Register Rdst = $dst$$Register;
5871 __ lduw($mem$$Address, Rdst);
5872 __ and3(Rdst, $mask$$constant, Rdst);
5873 %}
5874 ins_pipe(iload_mem);
5875 %}
5876
5877 // Load Integer with a 31-bit mask into a Long Register
5878 instruct loadI2L_immU32(iRegL dst, memory mem, immU32 mask, iRegL tmp) %{
5879 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5880 effect(TEMP dst, TEMP tmp);
5881 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5882
5883 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5884 "SET $mask,$tmp\n\t"
5885 "AND $dst,$tmp,$dst" %}
5886 ins_encode %{
5887 Register Rdst = $dst$$Register;
5888 Register Rtmp = $tmp$$Register;
5889 __ lduw($mem$$Address, Rdst);
5890 __ set($mask$$constant, Rtmp);
5891 __ and3(Rdst, Rtmp, Rdst);
5892 %}
5893 ins_pipe(iload_mem);
5894 %}
5895
5896 // Load Unsigned Integer into a Long Register
5897 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5898 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5899 ins_cost(MEMORY_REF_COST);
5900
5901 size(4);
5902 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5903 ins_encode %{
5904 __ lduw($mem$$Address, $dst$$Register);
5905 %}
5906 ins_pipe(iload_mem);
5907 %}
5908
5909 // Load Long - aligned
5910 instruct loadL(iRegL dst, memory mem ) %{
5911 match(Set dst (LoadL mem));
5912 ins_cost(MEMORY_REF_COST);
5913
5914 size(4);
5915 format %{ "LDX $mem,$dst\t! long" %}
5916 ins_encode %{
5917 __ ldx($mem$$Address, $dst$$Register);
5918 %}
5919 ins_pipe(iload_mem);
5920 %}
5921
5922 // Load Long - UNaligned
5923 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5924 match(Set dst (LoadL_unaligned mem));
5925 effect(KILL tmp);
5926 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5927 size(16);
5928 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5929 "\tLDUW $mem ,$dst\n"
5930 "\tSLLX #32, $dst, $dst\n"
5931 "\tOR $dst, R_O7, $dst" %}
5932 opcode(Assembler::lduw_op3);
5933 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5934 ins_pipe(iload_mem);
5935 %}
5936
5937 // Load Range
5938 instruct loadRange(iRegI dst, memory mem) %{
5939 match(Set dst (LoadRange mem));
5940 ins_cost(MEMORY_REF_COST);
5941
5942 size(4);
5943 format %{ "LDUW $mem,$dst\t! range" %}
5944 opcode(Assembler::lduw_op3);
5945 ins_encode(simple_form3_mem_reg( mem, dst ) );
5946 ins_pipe(iload_mem);
5947 %}
5948
5949 // Load Integer into %f register (for fitos/fitod)
5950 instruct loadI_freg(regF dst, memory mem) %{
5951 match(Set dst (LoadI mem));
5952 ins_cost(MEMORY_REF_COST);
5953 size(4);
5954
5955 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5956 opcode(Assembler::ldf_op3);
5957 ins_encode(simple_form3_mem_reg( mem, dst ) );
5958 ins_pipe(floadF_mem);
5959 %}
5960
5961 // Load Pointer
5962 instruct loadP(iRegP dst, memory mem) %{
5963 match(Set dst (LoadP mem));
5964 ins_cost(MEMORY_REF_COST);
5965 size(4);
5966
5967 #ifndef _LP64
5968 format %{ "LDUW $mem,$dst\t! ptr" %}
5969 ins_encode %{
5970 __ lduw($mem$$Address, $dst$$Register);
5971 %}
5972 #else
5973 format %{ "LDX $mem,$dst\t! ptr" %}
5974 ins_encode %{
5975 __ ldx($mem$$Address, $dst$$Register);
5976 %}
5977 #endif
5978 ins_pipe(iload_mem);
5979 %}
5980
5981 // Load Compressed Pointer
5982 instruct loadN(iRegN dst, memory mem) %{
5983 match(Set dst (LoadN mem));
5984 ins_cost(MEMORY_REF_COST);
5985 size(4);
5986
5987 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5988 ins_encode %{
5989 __ lduw($mem$$Address, $dst$$Register);
5990 %}
5991 ins_pipe(iload_mem);
5992 %}
5993
5994 // Load Klass Pointer
5995 instruct loadKlass(iRegP dst, memory mem) %{
5996 match(Set dst (LoadKlass mem));
5997 ins_cost(MEMORY_REF_COST);
5998 size(4);
5999
6000 #ifndef _LP64
6001 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6002 ins_encode %{
6003 __ lduw($mem$$Address, $dst$$Register);
6004 %}
6005 #else
6006 format %{ "LDX $mem,$dst\t! klass ptr" %}
6007 ins_encode %{
6008 __ ldx($mem$$Address, $dst$$Register);
6009 %}
6010 #endif
6011 ins_pipe(iload_mem);
6012 %}
6013
6014 // Load narrow Klass Pointer
6015 instruct loadNKlass(iRegN dst, memory mem) %{
6016 match(Set dst (LoadNKlass mem));
6017 ins_cost(MEMORY_REF_COST);
6018 size(4);
6019
6020 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6021 ins_encode %{
6022 __ lduw($mem$$Address, $dst$$Register);
6023 %}
6024 ins_pipe(iload_mem);
6025 %}
6026
6027 // Load Double
6028 instruct loadD(regD dst, memory mem) %{
6029 match(Set dst (LoadD mem));
6030 ins_cost(MEMORY_REF_COST);
6031
6032 size(4);
6033 format %{ "LDDF $mem,$dst" %}
6034 opcode(Assembler::lddf_op3);
6035 ins_encode(simple_form3_mem_reg( mem, dst ) );
6036 ins_pipe(floadD_mem);
6037 %}
6038
6039 // Load Double - UNaligned
6040 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6041 match(Set dst (LoadD_unaligned mem));
6042 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6043 size(8);
6044 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6045 "\tLDF $mem+4,$dst.lo\t!" %}
6046 opcode(Assembler::ldf_op3);
6047 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6048 ins_pipe(iload_mem);
6049 %}
6050
6051 // Load Float
6052 instruct loadF(regF dst, memory mem) %{
6053 match(Set dst (LoadF mem));
6054 ins_cost(MEMORY_REF_COST);
6055
6056 size(4);
6057 format %{ "LDF $mem,$dst" %}
6058 opcode(Assembler::ldf_op3);
6059 ins_encode(simple_form3_mem_reg( mem, dst ) );
6060 ins_pipe(floadF_mem);
6061 %}
6062
6063 // Load Constant
6064 instruct loadConI( iRegI dst, immI src ) %{
6065 match(Set dst src);
6066 ins_cost(DEFAULT_COST * 3/2);
6067 format %{ "SET $src,$dst" %}
6068 ins_encode( Set32(src, dst) );
6069 ins_pipe(ialu_hi_lo_reg);
6070 %}
6071
6072 instruct loadConI13( iRegI dst, immI13 src ) %{
6073 match(Set dst src);
6074
6075 size(4);
6076 format %{ "MOV $src,$dst" %}
6077 ins_encode( Set13( src, dst ) );
6078 ins_pipe(ialu_imm);
6079 %}
6080
6081 #ifndef _LP64
6082 instruct loadConP(iRegP dst, immP con) %{
6083 match(Set dst con);
6084 ins_cost(DEFAULT_COST * 3/2);
6085 format %{ "SET $con,$dst\t!ptr" %}
6086 ins_encode %{
6087 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6088 intptr_t val = $con$$constant;
6089 if (constant_reloc == relocInfo::oop_type) {
6090 __ set_oop_constant((jobject) val, $dst$$Register);
6091 } else if (constant_reloc == relocInfo::metadata_type) {
6092 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6093 } else { // non-oop pointers, e.g. card mark base, heap top
6094 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6095 __ set(val, $dst$$Register);
6096 }
6097 %}
6098 ins_pipe(loadConP);
6099 %}
6100 #else
6101 instruct loadConP_set(iRegP dst, immP_set con) %{
6102 match(Set dst con);
6103 ins_cost(DEFAULT_COST * 3/2);
6104 format %{ "SET $con,$dst\t! ptr" %}
6105 ins_encode %{
6106 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6107 intptr_t val = $con$$constant;
6108 if (constant_reloc == relocInfo::oop_type) {
6109 __ set_oop_constant((jobject) val, $dst$$Register);
6110 } else if (constant_reloc == relocInfo::metadata_type) {
6111 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6112 } else { // non-oop pointers, e.g. card mark base, heap top
6113 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6114 __ set(val, $dst$$Register);
6115 }
6116 %}
6117 ins_pipe(loadConP);
6118 %}
6119
6120 instruct loadConP_load(iRegP dst, immP_load con) %{
6121 match(Set dst con);
6122 ins_cost(MEMORY_REF_COST);
6123 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6124 ins_encode %{
6125 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6126 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6127 %}
6128 ins_pipe(loadConP);
6129 %}
6130
6131 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6132 match(Set dst con);
6133 ins_cost(DEFAULT_COST * 3/2);
6134 format %{ "SET $con,$dst\t! non-oop ptr" %}
6135 ins_encode %{
6136 __ set($con$$constant, $dst$$Register);
6137 %}
6138 ins_pipe(loadConP);
6139 %}
6140 #endif // _LP64
6141
6142 instruct loadConP0(iRegP dst, immP0 src) %{
6143 match(Set dst src);
6144
6145 size(4);
6146 format %{ "CLR $dst\t!ptr" %}
6147 ins_encode %{
6148 __ clr($dst$$Register);
6149 %}
6150 ins_pipe(ialu_imm);
6151 %}
6152
6153 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6154 match(Set dst src);
6155 ins_cost(DEFAULT_COST);
6156 format %{ "SET $src,$dst\t!ptr" %}
6157 ins_encode %{
6158 AddressLiteral polling_page(os::get_polling_page());
6159 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6160 %}
6161 ins_pipe(loadConP_poll);
6162 %}
6163
6164 instruct loadConN0(iRegN dst, immN0 src) %{
6165 match(Set dst src);
6166
6167 size(4);
6168 format %{ "CLR $dst\t! compressed NULL ptr" %}
6169 ins_encode %{
6170 __ clr($dst$$Register);
6171 %}
6172 ins_pipe(ialu_imm);
6173 %}
6174
6175 instruct loadConN(iRegN dst, immN src) %{
6176 match(Set dst src);
6177 ins_cost(DEFAULT_COST * 3/2);
6178 format %{ "SET $src,$dst\t! compressed ptr" %}
6179 ins_encode %{
6180 Register dst = $dst$$Register;
6181 __ set_narrow_oop((jobject)$src$$constant, dst);
6182 %}
6183 ins_pipe(ialu_hi_lo_reg);
6184 %}
6185
6186 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6187 match(Set dst src);
6188 ins_cost(DEFAULT_COST * 3/2);
6189 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6190 ins_encode %{
6191 Register dst = $dst$$Register;
6192 __ set_narrow_klass((Klass*)$src$$constant, dst);
6193 %}
6194 ins_pipe(ialu_hi_lo_reg);
6195 %}
6196
6197 // Materialize long value (predicated by immL_cheap).
6198 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6199 match(Set dst con);
6200 effect(KILL tmp);
6201 ins_cost(DEFAULT_COST * 3);
6202 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6203 ins_encode %{
6204 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6205 %}
6206 ins_pipe(loadConL);
6207 %}
6208
6209 // Load long value from constant table (predicated by immL_expensive).
6210 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6211 match(Set dst con);
6212 ins_cost(MEMORY_REF_COST);
6213 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6214 ins_encode %{
6215 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6216 __ ldx($constanttablebase, con_offset, $dst$$Register);
6217 %}
6218 ins_pipe(loadConL);
6219 %}
6220
6221 instruct loadConL0( iRegL dst, immL0 src ) %{
6222 match(Set dst src);
6223 ins_cost(DEFAULT_COST);
6224 size(4);
6225 format %{ "CLR $dst\t! long" %}
6226 ins_encode( Set13( src, dst ) );
6227 ins_pipe(ialu_imm);
6228 %}
6229
6230 instruct loadConL13( iRegL dst, immL13 src ) %{
6231 match(Set dst src);
6232 ins_cost(DEFAULT_COST * 2);
6233
6234 size(4);
6235 format %{ "MOV $src,$dst\t! long" %}
6236 ins_encode( Set13( src, dst ) );
6237 ins_pipe(ialu_imm);
6238 %}
6239
6240 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6241 match(Set dst con);
6242 effect(KILL tmp);
6243 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6244 ins_encode %{
6245 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6246 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6247 %}
6248 ins_pipe(loadConFD);
6249 %}
6250
6251 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6252 match(Set dst con);
6253 effect(KILL tmp);
6254 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6255 ins_encode %{
6256 // XXX This is a quick fix for 6833573.
6257 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6258 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6259 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6260 %}
6261 ins_pipe(loadConFD);
6262 %}
6263
6264 // Prefetch instructions.
6265 // Must be safe to execute with invalid address (cannot fault).
6266
6267 instruct prefetchr( memory mem ) %{
6268 match( PrefetchRead mem );
6269 ins_cost(MEMORY_REF_COST);
6270 size(4);
6271
6272 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6273 opcode(Assembler::prefetch_op3);
6274 ins_encode( form3_mem_prefetch_read( mem ) );
6275 ins_pipe(iload_mem);
6276 %}
6277
6278 instruct prefetchw( memory mem ) %{
6279 match( PrefetchWrite mem );
6280 ins_cost(MEMORY_REF_COST);
6281 size(4);
6282
6283 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6284 opcode(Assembler::prefetch_op3);
6285 ins_encode( form3_mem_prefetch_write( mem ) );
6286 ins_pipe(iload_mem);
6287 %}
6288
6289 // Prefetch instructions for allocation.
6290
6291 instruct prefetchAlloc( memory mem ) %{
6292 predicate(AllocatePrefetchInstr == 0);
6293 match( PrefetchAllocation mem );
6294 ins_cost(MEMORY_REF_COST);
6295 size(4);
6296
6297 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6298 opcode(Assembler::prefetch_op3);
6299 ins_encode( form3_mem_prefetch_write( mem ) );
6300 ins_pipe(iload_mem);
6301 %}
6302
6303 // Use BIS instruction to prefetch for allocation.
6304 // Could fault, need space at the end of TLAB.
6305 instruct prefetchAlloc_bis( iRegP dst ) %{
6306 predicate(AllocatePrefetchInstr == 1);
6307 match( PrefetchAllocation dst );
6308 ins_cost(MEMORY_REF_COST);
6309 size(4);
6310
6311 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6312 ins_encode %{
6313 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6314 %}
6315 ins_pipe(istore_mem_reg);
6316 %}
6317
6318 // Next code is used for finding next cache line address to prefetch.
6319 #ifndef _LP64
6320 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6321 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6322 ins_cost(DEFAULT_COST);
6323 size(4);
6324
6325 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6326 ins_encode %{
6327 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6328 %}
6329 ins_pipe(ialu_reg_imm);
6330 %}
6331 #else
6332 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6333 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6334 ins_cost(DEFAULT_COST);
6335 size(4);
6336
6337 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6338 ins_encode %{
6339 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6340 %}
6341 ins_pipe(ialu_reg_imm);
6342 %}
6343 #endif
6344
6345 //----------Store Instructions-------------------------------------------------
6346 // Store Byte
6347 instruct storeB(memory mem, iRegI src) %{
6348 match(Set mem (StoreB mem src));
6349 ins_cost(MEMORY_REF_COST);
6350
6351 size(4);
6352 format %{ "STB $src,$mem\t! byte" %}
6353 opcode(Assembler::stb_op3);
6354 ins_encode(simple_form3_mem_reg( mem, src ) );
6355 ins_pipe(istore_mem_reg);
6356 %}
6357
6358 instruct storeB0(memory mem, immI0 src) %{
6359 match(Set mem (StoreB mem src));
6360 ins_cost(MEMORY_REF_COST);
6361
6362 size(4);
6363 format %{ "STB $src,$mem\t! byte" %}
6364 opcode(Assembler::stb_op3);
6365 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6366 ins_pipe(istore_mem_zero);
6367 %}
6368
6369 instruct storeCM0(memory mem, immI0 src) %{
6370 match(Set mem (StoreCM mem src));
6371 ins_cost(MEMORY_REF_COST);
6372
6373 size(4);
6374 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6375 opcode(Assembler::stb_op3);
6376 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6377 ins_pipe(istore_mem_zero);
6378 %}
6379
6380 // Store Char/Short
6381 instruct storeC(memory mem, iRegI src) %{
6382 match(Set mem (StoreC mem src));
6383 ins_cost(MEMORY_REF_COST);
6384
6385 size(4);
6386 format %{ "STH $src,$mem\t! short" %}
6387 opcode(Assembler::sth_op3);
6388 ins_encode(simple_form3_mem_reg( mem, src ) );
6389 ins_pipe(istore_mem_reg);
6390 %}
6391
6392 instruct storeC0(memory mem, immI0 src) %{
6393 match(Set mem (StoreC mem src));
6394 ins_cost(MEMORY_REF_COST);
6395
6396 size(4);
6397 format %{ "STH $src,$mem\t! short" %}
6398 opcode(Assembler::sth_op3);
6399 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6400 ins_pipe(istore_mem_zero);
6401 %}
6402
6403 // Store Integer
6404 instruct storeI(memory mem, iRegI src) %{
6405 match(Set mem (StoreI mem src));
6406 ins_cost(MEMORY_REF_COST);
6407
6408 size(4);
6409 format %{ "STW $src,$mem" %}
6410 opcode(Assembler::stw_op3);
6411 ins_encode(simple_form3_mem_reg( mem, src ) );
6412 ins_pipe(istore_mem_reg);
6413 %}
6414
6415 // Store Long
6416 instruct storeL(memory mem, iRegL src) %{
6417 match(Set mem (StoreL mem src));
6418 ins_cost(MEMORY_REF_COST);
6419 size(4);
6420 format %{ "STX $src,$mem\t! long" %}
6421 opcode(Assembler::stx_op3);
6422 ins_encode(simple_form3_mem_reg( mem, src ) );
6423 ins_pipe(istore_mem_reg);
6424 %}
6425
6426 instruct storeI0(memory mem, immI0 src) %{
6427 match(Set mem (StoreI mem src));
6428 ins_cost(MEMORY_REF_COST);
6429
6430 size(4);
6431 format %{ "STW $src,$mem" %}
6432 opcode(Assembler::stw_op3);
6433 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6434 ins_pipe(istore_mem_zero);
6435 %}
6436
6437 instruct storeL0(memory mem, immL0 src) %{
6438 match(Set mem (StoreL mem src));
6439 ins_cost(MEMORY_REF_COST);
6440
6441 size(4);
6442 format %{ "STX $src,$mem" %}
6443 opcode(Assembler::stx_op3);
6444 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6445 ins_pipe(istore_mem_zero);
6446 %}
6447
6448 // Store Integer from float register (used after fstoi)
6449 instruct storeI_Freg(memory mem, regF src) %{
6450 match(Set mem (StoreI mem src));
6451 ins_cost(MEMORY_REF_COST);
6452
6453 size(4);
6454 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6455 opcode(Assembler::stf_op3);
6456 ins_encode(simple_form3_mem_reg( mem, src ) );
6457 ins_pipe(fstoreF_mem_reg);
6458 %}
6459
6460 // Store Pointer
6461 instruct storeP(memory dst, sp_ptr_RegP src) %{
6462 match(Set dst (StoreP dst src));
6463 ins_cost(MEMORY_REF_COST);
6464 size(4);
6465
6466 #ifndef _LP64
6467 format %{ "STW $src,$dst\t! ptr" %}
6468 opcode(Assembler::stw_op3, 0, REGP_OP);
6469 #else
6470 format %{ "STX $src,$dst\t! ptr" %}
6471 opcode(Assembler::stx_op3, 0, REGP_OP);
6472 #endif
6473 ins_encode( form3_mem_reg( dst, src ) );
6474 ins_pipe(istore_mem_spORreg);
6475 %}
6476
6477 instruct storeP0(memory dst, immP0 src) %{
6478 match(Set dst (StoreP dst src));
6479 ins_cost(MEMORY_REF_COST);
6480 size(4);
6481
6482 #ifndef _LP64
6483 format %{ "STW $src,$dst\t! ptr" %}
6484 opcode(Assembler::stw_op3, 0, REGP_OP);
6485 #else
6486 format %{ "STX $src,$dst\t! ptr" %}
6487 opcode(Assembler::stx_op3, 0, REGP_OP);
6488 #endif
6489 ins_encode( form3_mem_reg( dst, R_G0 ) );
6490 ins_pipe(istore_mem_zero);
6491 %}
6492
6493 // Store Compressed Pointer
6494 instruct storeN(memory dst, iRegN src) %{
6495 match(Set dst (StoreN dst src));
6496 ins_cost(MEMORY_REF_COST);
6497 size(4);
6498
6499 format %{ "STW $src,$dst\t! compressed ptr" %}
6500 ins_encode %{
6501 Register base = as_Register($dst$$base);
6502 Register index = as_Register($dst$$index);
6503 Register src = $src$$Register;
6504 if (index != G0) {
6505 __ stw(src, base, index);
6506 } else {
6507 __ stw(src, base, $dst$$disp);
6508 }
6509 %}
6510 ins_pipe(istore_mem_spORreg);
6511 %}
6512
6513 instruct storeNKlass(memory dst, iRegN src) %{
6514 match(Set dst (StoreNKlass dst src));
6515 ins_cost(MEMORY_REF_COST);
6516 size(4);
6517
6518 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6519 ins_encode %{
6520 Register base = as_Register($dst$$base);
6521 Register index = as_Register($dst$$index);
6522 Register src = $src$$Register;
6523 if (index != G0) {
6524 __ stw(src, base, index);
6525 } else {
6526 __ stw(src, base, $dst$$disp);
6527 }
6528 %}
6529 ins_pipe(istore_mem_spORreg);
6530 %}
6531
6532 instruct storeN0(memory dst, immN0 src) %{
6533 match(Set dst (StoreN dst src));
6534 ins_cost(MEMORY_REF_COST);
6535 size(4);
6536
6537 format %{ "STW $src,$dst\t! compressed ptr" %}
6538 ins_encode %{
6539 Register base = as_Register($dst$$base);
6540 Register index = as_Register($dst$$index);
6541 if (index != G0) {
6542 __ stw(0, base, index);
6543 } else {
6544 __ stw(0, base, $dst$$disp);
6545 }
6546 %}
6547 ins_pipe(istore_mem_zero);
6548 %}
6549
6550 // Store Double
6551 instruct storeD( memory mem, regD src) %{
6552 match(Set mem (StoreD mem src));
6553 ins_cost(MEMORY_REF_COST);
6554
6555 size(4);
6556 format %{ "STDF $src,$mem" %}
6557 opcode(Assembler::stdf_op3);
6558 ins_encode(simple_form3_mem_reg( mem, src ) );
6559 ins_pipe(fstoreD_mem_reg);
6560 %}
6561
6562 instruct storeD0( memory mem, immD0 src) %{
6563 match(Set mem (StoreD mem src));
6564 ins_cost(MEMORY_REF_COST);
6565
6566 size(4);
6567 format %{ "STX $src,$mem" %}
6568 opcode(Assembler::stx_op3);
6569 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6570 ins_pipe(fstoreD_mem_zero);
6571 %}
6572
6573 // Store Float
6574 instruct storeF( memory mem, regF src) %{
6575 match(Set mem (StoreF mem src));
6576 ins_cost(MEMORY_REF_COST);
6577
6578 size(4);
6579 format %{ "STF $src,$mem" %}
6580 opcode(Assembler::stf_op3);
6581 ins_encode(simple_form3_mem_reg( mem, src ) );
6582 ins_pipe(fstoreF_mem_reg);
6583 %}
6584
6585 instruct storeF0( memory mem, immF0 src) %{
6586 match(Set mem (StoreF mem src));
6587 ins_cost(MEMORY_REF_COST);
6588
6589 size(4);
6590 format %{ "STW $src,$mem\t! storeF0" %}
6591 opcode(Assembler::stw_op3);
6592 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6593 ins_pipe(fstoreF_mem_zero);
6594 %}
6595
6596 // Convert oop pointer into compressed form
6597 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6598 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6599 match(Set dst (EncodeP src));
6600 format %{ "encode_heap_oop $src, $dst" %}
6601 ins_encode %{
6602 __ encode_heap_oop($src$$Register, $dst$$Register);
6603 %}
6604 ins_pipe(ialu_reg);
6605 %}
6606
6607 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6608 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6609 match(Set dst (EncodeP src));
6610 format %{ "encode_heap_oop_not_null $src, $dst" %}
6611 ins_encode %{
6612 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6613 %}
6614 ins_pipe(ialu_reg);
6615 %}
6616
6617 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6618 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6619 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6620 match(Set dst (DecodeN src));
6621 format %{ "decode_heap_oop $src, $dst" %}
6622 ins_encode %{
6623 __ decode_heap_oop($src$$Register, $dst$$Register);
6624 %}
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6629 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6630 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6631 match(Set dst (DecodeN src));
6632 format %{ "decode_heap_oop_not_null $src, $dst" %}
6633 ins_encode %{
6634 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6635 %}
6636 ins_pipe(ialu_reg);
6637 %}
6638
6639 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6640 match(Set dst (EncodePKlass src));
6641 format %{ "encode_klass_not_null $src, $dst" %}
6642 ins_encode %{
6643 __ encode_klass_not_null($src$$Register, $dst$$Register);
6644 %}
6645 ins_pipe(ialu_reg);
6646 %}
6647
6648 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6649 match(Set dst (DecodeNKlass src));
6650 format %{ "decode_klass_not_null $src, $dst" %}
6651 ins_encode %{
6652 __ decode_klass_not_null($src$$Register, $dst$$Register);
6653 %}
6654 ins_pipe(ialu_reg);
6655 %}
6656
6657 //----------MemBar Instructions-----------------------------------------------
6658 // Memory barrier flavors
6659
6660 instruct membar_acquire() %{
6661 match(MemBarAcquire);
6662 ins_cost(4*MEMORY_REF_COST);
6663
6664 size(0);
6665 format %{ "MEMBAR-acquire" %}
6666 ins_encode( enc_membar_acquire );
6667 ins_pipe(long_memory_op);
6668 %}
6669
6670 instruct membar_acquire_lock() %{
6671 match(MemBarAcquireLock);
6672 ins_cost(0);
6673
6674 size(0);
6675 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6676 ins_encode( );
6677 ins_pipe(empty);
6678 %}
6679
6680 instruct membar_release() %{
6681 match(MemBarRelease);
6682 ins_cost(4*MEMORY_REF_COST);
6683
6684 size(0);
6685 format %{ "MEMBAR-release" %}
6686 ins_encode( enc_membar_release );
6687 ins_pipe(long_memory_op);
6688 %}
6689
6690 instruct membar_release_lock() %{
6691 match(MemBarReleaseLock);
6692 ins_cost(0);
6693
6694 size(0);
6695 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6696 ins_encode( );
6697 ins_pipe(empty);
6698 %}
6699
6700 instruct membar_volatile() %{
6701 match(MemBarVolatile);
6702 ins_cost(4*MEMORY_REF_COST);
6703
6704 size(4);
6705 format %{ "MEMBAR-volatile" %}
6706 ins_encode( enc_membar_volatile );
6707 ins_pipe(long_memory_op);
6708 %}
6709
6710 instruct unnecessary_membar_volatile() %{
6711 match(MemBarVolatile);
6712 predicate(Matcher::post_store_load_barrier(n));
6713 ins_cost(0);
6714
6715 size(0);
6716 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6717 ins_encode( );
6718 ins_pipe(empty);
6719 %}
6720
6721 instruct membar_storestore() %{
6722 match(MemBarStoreStore);
6723 ins_cost(0);
6724
6725 size(0);
6726 format %{ "!MEMBAR-storestore (empty encoding)" %}
6727 ins_encode( );
6728 ins_pipe(empty);
6729 %}
6730
6731 //----------Register Move Instructions-----------------------------------------
6732 instruct roundDouble_nop(regD dst) %{
6733 match(Set dst (RoundDouble dst));
6734 ins_cost(0);
6735 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6736 ins_encode( );
6737 ins_pipe(empty);
6738 %}
6739
6740
6741 instruct roundFloat_nop(regF dst) %{
6742 match(Set dst (RoundFloat dst));
6743 ins_cost(0);
6744 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6745 ins_encode( );
6746 ins_pipe(empty);
6747 %}
6748
6749
6750 // Cast Index to Pointer for unsafe natives
6751 instruct castX2P(iRegX src, iRegP dst) %{
6752 match(Set dst (CastX2P src));
6753
6754 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6755 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6756 ins_pipe(ialu_reg);
6757 %}
6758
6759 // Cast Pointer to Index for unsafe natives
6760 instruct castP2X(iRegP src, iRegX dst) %{
6761 match(Set dst (CastP2X src));
6762
6763 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6764 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6765 ins_pipe(ialu_reg);
6766 %}
6767
6768 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6769 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6770 match(Set stkSlot src); // chain rule
6771 ins_cost(MEMORY_REF_COST);
6772 format %{ "STDF $src,$stkSlot\t!stk" %}
6773 opcode(Assembler::stdf_op3);
6774 ins_encode(simple_form3_mem_reg(stkSlot, src));
6775 ins_pipe(fstoreD_stk_reg);
6776 %}
6777
6778 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6779 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6780 match(Set dst stkSlot); // chain rule
6781 ins_cost(MEMORY_REF_COST);
6782 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6783 opcode(Assembler::lddf_op3);
6784 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6785 ins_pipe(floadD_stk);
6786 %}
6787
6788 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6789 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6790 match(Set stkSlot src); // chain rule
6791 ins_cost(MEMORY_REF_COST);
6792 format %{ "STF $src,$stkSlot\t!stk" %}
6793 opcode(Assembler::stf_op3);
6794 ins_encode(simple_form3_mem_reg(stkSlot, src));
6795 ins_pipe(fstoreF_stk_reg);
6796 %}
6797
6798 //----------Conditional Move---------------------------------------------------
6799 // Conditional move
6800 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6801 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6802 ins_cost(150);
6803 format %{ "MOV$cmp $pcc,$src,$dst" %}
6804 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6805 ins_pipe(ialu_reg);
6806 %}
6807
6808 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6809 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6810 ins_cost(140);
6811 format %{ "MOV$cmp $pcc,$src,$dst" %}
6812 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6813 ins_pipe(ialu_imm);
6814 %}
6815
6816 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6817 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6818 ins_cost(150);
6819 size(4);
6820 format %{ "MOV$cmp $icc,$src,$dst" %}
6821 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6822 ins_pipe(ialu_reg);
6823 %}
6824
6825 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6826 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6827 ins_cost(140);
6828 size(4);
6829 format %{ "MOV$cmp $icc,$src,$dst" %}
6830 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6831 ins_pipe(ialu_imm);
6832 %}
6833
6834 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6835 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6836 ins_cost(150);
6837 size(4);
6838 format %{ "MOV$cmp $icc,$src,$dst" %}
6839 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6840 ins_pipe(ialu_reg);
6841 %}
6842
6843 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6844 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6845 ins_cost(140);
6846 size(4);
6847 format %{ "MOV$cmp $icc,$src,$dst" %}
6848 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6849 ins_pipe(ialu_imm);
6850 %}
6851
6852 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6853 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6854 ins_cost(150);
6855 size(4);
6856 format %{ "MOV$cmp $fcc,$src,$dst" %}
6857 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6858 ins_pipe(ialu_reg);
6859 %}
6860
6861 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6862 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6863 ins_cost(140);
6864 size(4);
6865 format %{ "MOV$cmp $fcc,$src,$dst" %}
6866 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6867 ins_pipe(ialu_imm);
6868 %}
6869
6870 // Conditional move for RegN. Only cmov(reg,reg).
6871 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6872 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6873 ins_cost(150);
6874 format %{ "MOV$cmp $pcc,$src,$dst" %}
6875 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6876 ins_pipe(ialu_reg);
6877 %}
6878
6879 // This instruction also works with CmpN so we don't need cmovNN_reg.
6880 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6881 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6882 ins_cost(150);
6883 size(4);
6884 format %{ "MOV$cmp $icc,$src,$dst" %}
6885 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6886 ins_pipe(ialu_reg);
6887 %}
6888
6889 // This instruction also works with CmpN so we don't need cmovNN_reg.
6890 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6891 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6892 ins_cost(150);
6893 size(4);
6894 format %{ "MOV$cmp $icc,$src,$dst" %}
6895 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6896 ins_pipe(ialu_reg);
6897 %}
6898
6899 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6900 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6901 ins_cost(150);
6902 size(4);
6903 format %{ "MOV$cmp $fcc,$src,$dst" %}
6904 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6905 ins_pipe(ialu_reg);
6906 %}
6907
6908 // Conditional move
6909 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6910 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6911 ins_cost(150);
6912 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6913 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6914 ins_pipe(ialu_reg);
6915 %}
6916
6917 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6918 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6919 ins_cost(140);
6920 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6921 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6922 ins_pipe(ialu_imm);
6923 %}
6924
6925 // This instruction also works with CmpN so we don't need cmovPN_reg.
6926 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6927 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6928 ins_cost(150);
6929
6930 size(4);
6931 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6932 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6933 ins_pipe(ialu_reg);
6934 %}
6935
6936 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6937 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6938 ins_cost(150);
6939
6940 size(4);
6941 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6942 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6943 ins_pipe(ialu_reg);
6944 %}
6945
6946 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6947 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6948 ins_cost(140);
6949
6950 size(4);
6951 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6952 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6953 ins_pipe(ialu_imm);
6954 %}
6955
6956 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6957 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6958 ins_cost(140);
6959
6960 size(4);
6961 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6962 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6963 ins_pipe(ialu_imm);
6964 %}
6965
6966 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6967 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6968 ins_cost(150);
6969 size(4);
6970 format %{ "MOV$cmp $fcc,$src,$dst" %}
6971 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6972 ins_pipe(ialu_imm);
6973 %}
6974
6975 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6976 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6977 ins_cost(140);
6978 size(4);
6979 format %{ "MOV$cmp $fcc,$src,$dst" %}
6980 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6981 ins_pipe(ialu_imm);
6982 %}
6983
6984 // Conditional move
6985 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6986 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6987 ins_cost(150);
6988 opcode(0x101);
6989 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6990 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6991 ins_pipe(int_conditional_float_move);
6992 %}
6993
6994 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6995 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6996 ins_cost(150);
6997
6998 size(4);
6999 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7000 opcode(0x101);
7001 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7002 ins_pipe(int_conditional_float_move);
7003 %}
7004
7005 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7006 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7007 ins_cost(150);
7008
7009 size(4);
7010 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7011 opcode(0x101);
7012 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7013 ins_pipe(int_conditional_float_move);
7014 %}
7015
7016 // Conditional move,
7017 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7018 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7019 ins_cost(150);
7020 size(4);
7021 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7022 opcode(0x1);
7023 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7024 ins_pipe(int_conditional_double_move);
7025 %}
7026
7027 // Conditional move
7028 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7029 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7030 ins_cost(150);
7031 size(4);
7032 opcode(0x102);
7033 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7034 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7035 ins_pipe(int_conditional_double_move);
7036 %}
7037
7038 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7039 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7040 ins_cost(150);
7041
7042 size(4);
7043 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7044 opcode(0x102);
7045 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7046 ins_pipe(int_conditional_double_move);
7047 %}
7048
7049 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7050 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7051 ins_cost(150);
7052
7053 size(4);
7054 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7055 opcode(0x102);
7056 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7057 ins_pipe(int_conditional_double_move);
7058 %}
7059
7060 // Conditional move,
7061 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7062 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7063 ins_cost(150);
7064 size(4);
7065 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7066 opcode(0x2);
7067 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7068 ins_pipe(int_conditional_double_move);
7069 %}
7070
7071 // Conditional move
7072 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7073 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7074 ins_cost(150);
7075 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7076 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7077 ins_pipe(ialu_reg);
7078 %}
7079
7080 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7081 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7082 ins_cost(140);
7083 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7084 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7085 ins_pipe(ialu_imm);
7086 %}
7087
7088 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7089 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7090 ins_cost(150);
7091
7092 size(4);
7093 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7094 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7095 ins_pipe(ialu_reg);
7096 %}
7097
7098
7099 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7100 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7101 ins_cost(150);
7102
7103 size(4);
7104 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7105 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7106 ins_pipe(ialu_reg);
7107 %}
7108
7109
7110 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7111 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7112 ins_cost(150);
7113
7114 size(4);
7115 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7116 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7117 ins_pipe(ialu_reg);
7118 %}
7119
7120
7121
7122 //----------OS and Locking Instructions----------------------------------------
7123
7124 // This name is KNOWN by the ADLC and cannot be changed.
7125 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7126 // for this guy.
7127 instruct tlsLoadP(g2RegP dst) %{
7128 match(Set dst (ThreadLocal));
7129
7130 size(0);
7131 ins_cost(0);
7132 format %{ "# TLS is in G2" %}
7133 ins_encode( /*empty encoding*/ );
7134 ins_pipe(ialu_none);
7135 %}
7136
7137 instruct checkCastPP( iRegP dst ) %{
7138 match(Set dst (CheckCastPP dst));
7139
7140 size(0);
7141 format %{ "# checkcastPP of $dst" %}
7142 ins_encode( /*empty encoding*/ );
7143 ins_pipe(empty);
7144 %}
7145
7146
7147 instruct castPP( iRegP dst ) %{
7148 match(Set dst (CastPP dst));
7149 format %{ "# castPP of $dst" %}
7150 ins_encode( /*empty encoding*/ );
7151 ins_pipe(empty);
7152 %}
7153
7154 instruct castII( iRegI dst ) %{
7155 match(Set dst (CastII dst));
7156 format %{ "# castII of $dst" %}
7157 ins_encode( /*empty encoding*/ );
7158 ins_cost(0);
7159 ins_pipe(empty);
7160 %}
7161
7162 //----------Arithmetic Instructions--------------------------------------------
7163 // Addition Instructions
7164 // Register Addition
7165 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7166 match(Set dst (AddI src1 src2));
7167
7168 size(4);
7169 format %{ "ADD $src1,$src2,$dst" %}
7170 ins_encode %{
7171 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7172 %}
7173 ins_pipe(ialu_reg_reg);
7174 %}
7175
7176 // Immediate Addition
7177 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7178 match(Set dst (AddI src1 src2));
7179
7180 size(4);
7181 format %{ "ADD $src1,$src2,$dst" %}
7182 opcode(Assembler::add_op3, Assembler::arith_op);
7183 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7184 ins_pipe(ialu_reg_imm);
7185 %}
7186
7187 // Pointer Register Addition
7188 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7189 match(Set dst (AddP src1 src2));
7190
7191 size(4);
7192 format %{ "ADD $src1,$src2,$dst" %}
7193 opcode(Assembler::add_op3, Assembler::arith_op);
7194 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7195 ins_pipe(ialu_reg_reg);
7196 %}
7197
7198 // Pointer Immediate Addition
7199 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7200 match(Set dst (AddP src1 src2));
7201
7202 size(4);
7203 format %{ "ADD $src1,$src2,$dst" %}
7204 opcode(Assembler::add_op3, Assembler::arith_op);
7205 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7206 ins_pipe(ialu_reg_imm);
7207 %}
7208
7209 // Long Addition
7210 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7211 match(Set dst (AddL src1 src2));
7212
7213 size(4);
7214 format %{ "ADD $src1,$src2,$dst\t! long" %}
7215 opcode(Assembler::add_op3, Assembler::arith_op);
7216 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7217 ins_pipe(ialu_reg_reg);
7218 %}
7219
7220 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7221 match(Set dst (AddL src1 con));
7222
7223 size(4);
7224 format %{ "ADD $src1,$con,$dst" %}
7225 opcode(Assembler::add_op3, Assembler::arith_op);
7226 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7227 ins_pipe(ialu_reg_imm);
7228 %}
7229
7230 //----------Conditional_store--------------------------------------------------
7231 // Conditional-store of the updated heap-top.
7232 // Used during allocation of the shared heap.
7233 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7234
7235 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7236 instruct loadPLocked(iRegP dst, memory mem) %{
7237 match(Set dst (LoadPLocked mem));
7238 ins_cost(MEMORY_REF_COST);
7239
7240 #ifndef _LP64
7241 size(4);
7242 format %{ "LDUW $mem,$dst\t! ptr" %}
7243 opcode(Assembler::lduw_op3, 0, REGP_OP);
7244 #else
7245 format %{ "LDX $mem,$dst\t! ptr" %}
7246 opcode(Assembler::ldx_op3, 0, REGP_OP);
7247 #endif
7248 ins_encode( form3_mem_reg( mem, dst ) );
7249 ins_pipe(iload_mem);
7250 %}
7251
7252 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7253 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7254 effect( KILL newval );
7255 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7256 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7257 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7258 ins_pipe( long_memory_op );
7259 %}
7260
7261 // Conditional-store of an int value.
7262 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7263 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7264 effect( KILL newval );
7265 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7266 "CMP $oldval,$newval\t\t! See if we made progress" %}
7267 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7268 ins_pipe( long_memory_op );
7269 %}
7270
7271 // Conditional-store of a long value.
7272 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7273 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7274 effect( KILL newval );
7275 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7276 "CMP $oldval,$newval\t\t! See if we made progress" %}
7277 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7278 ins_pipe( long_memory_op );
7279 %}
7280
7281 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7282
7283 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7284 predicate(VM_Version::supports_cx8());
7285 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7286 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7287 format %{
7288 "MOV $newval,O7\n\t"
7289 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7290 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7291 "MOV 1,$res\n\t"
7292 "MOVne xcc,R_G0,$res"
7293 %}
7294 ins_encode( enc_casx(mem_ptr, oldval, newval),
7295 enc_lflags_ne_to_boolean(res) );
7296 ins_pipe( long_memory_op );
7297 %}
7298
7299
7300 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7301 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7302 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7303 format %{
7304 "MOV $newval,O7\n\t"
7305 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7306 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7307 "MOV 1,$res\n\t"
7308 "MOVne icc,R_G0,$res"
7309 %}
7310 ins_encode( enc_casi(mem_ptr, oldval, newval),
7311 enc_iflags_ne_to_boolean(res) );
7312 ins_pipe( long_memory_op );
7313 %}
7314
7315 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7316 #ifdef _LP64
7317 predicate(VM_Version::supports_cx8());
7318 #endif
7319 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7320 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7321 format %{
7322 "MOV $newval,O7\n\t"
7323 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7324 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7325 "MOV 1,$res\n\t"
7326 "MOVne xcc,R_G0,$res"
7327 %}
7328 #ifdef _LP64
7329 ins_encode( enc_casx(mem_ptr, oldval, newval),
7330 enc_lflags_ne_to_boolean(res) );
7331 #else
7332 ins_encode( enc_casi(mem_ptr, oldval, newval),
7333 enc_iflags_ne_to_boolean(res) );
7334 #endif
7335 ins_pipe( long_memory_op );
7336 %}
7337
7338 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7339 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7340 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7341 format %{
7342 "MOV $newval,O7\n\t"
7343 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7344 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7345 "MOV 1,$res\n\t"
7346 "MOVne icc,R_G0,$res"
7347 %}
7348 ins_encode( enc_casi(mem_ptr, oldval, newval),
7349 enc_iflags_ne_to_boolean(res) );
7350 ins_pipe( long_memory_op );
7351 %}
7352
7353 instruct xchgI( memory mem, iRegI newval) %{
7354 match(Set newval (GetAndSetI mem newval));
7355 format %{ "SWAP [$mem],$newval" %}
7356 size(4);
7357 ins_encode %{
7358 __ swap($mem$$Address, $newval$$Register);
7359 %}
7360 ins_pipe( long_memory_op );
7361 %}
7362
7363 #ifndef _LP64
7364 instruct xchgP( memory mem, iRegP newval) %{
7365 match(Set newval (GetAndSetP mem newval));
7366 format %{ "SWAP [$mem],$newval" %}
7367 size(4);
7368 ins_encode %{
7369 __ swap($mem$$Address, $newval$$Register);
7370 %}
7371 ins_pipe( long_memory_op );
7372 %}
7373 #endif
7374
7375 instruct xchgN( memory mem, iRegN newval) %{
7376 match(Set newval (GetAndSetN mem newval));
7377 format %{ "SWAP [$mem],$newval" %}
7378 size(4);
7379 ins_encode %{
7380 __ swap($mem$$Address, $newval$$Register);
7381 %}
7382 ins_pipe( long_memory_op );
7383 %}
7384
7385 //---------------------
7386 // Subtraction Instructions
7387 // Register Subtraction
7388 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7389 match(Set dst (SubI src1 src2));
7390
7391 size(4);
7392 format %{ "SUB $src1,$src2,$dst" %}
7393 opcode(Assembler::sub_op3, Assembler::arith_op);
7394 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7395 ins_pipe(ialu_reg_reg);
7396 %}
7397
7398 // Immediate Subtraction
7399 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7400 match(Set dst (SubI src1 src2));
7401
7402 size(4);
7403 format %{ "SUB $src1,$src2,$dst" %}
7404 opcode(Assembler::sub_op3, Assembler::arith_op);
7405 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7406 ins_pipe(ialu_reg_imm);
7407 %}
7408
7409 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7410 match(Set dst (SubI zero src2));
7411
7412 size(4);
7413 format %{ "NEG $src2,$dst" %}
7414 opcode(Assembler::sub_op3, Assembler::arith_op);
7415 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7416 ins_pipe(ialu_zero_reg);
7417 %}
7418
7419 // Long subtraction
7420 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7421 match(Set dst (SubL src1 src2));
7422
7423 size(4);
7424 format %{ "SUB $src1,$src2,$dst\t! long" %}
7425 opcode(Assembler::sub_op3, Assembler::arith_op);
7426 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7427 ins_pipe(ialu_reg_reg);
7428 %}
7429
7430 // Immediate Subtraction
7431 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7432 match(Set dst (SubL src1 con));
7433
7434 size(4);
7435 format %{ "SUB $src1,$con,$dst\t! long" %}
7436 opcode(Assembler::sub_op3, Assembler::arith_op);
7437 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7438 ins_pipe(ialu_reg_imm);
7439 %}
7440
7441 // Long negation
7442 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7443 match(Set dst (SubL zero src2));
7444
7445 size(4);
7446 format %{ "NEG $src2,$dst\t! long" %}
7447 opcode(Assembler::sub_op3, Assembler::arith_op);
7448 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7449 ins_pipe(ialu_zero_reg);
7450 %}
7451
7452 // Multiplication Instructions
7453 // Integer Multiplication
7454 // Register Multiplication
7455 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7456 match(Set dst (MulI src1 src2));
7457
7458 size(4);
7459 format %{ "MULX $src1,$src2,$dst" %}
7460 opcode(Assembler::mulx_op3, Assembler::arith_op);
7461 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7462 ins_pipe(imul_reg_reg);
7463 %}
7464
7465 // Immediate Multiplication
7466 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7467 match(Set dst (MulI src1 src2));
7468
7469 size(4);
7470 format %{ "MULX $src1,$src2,$dst" %}
7471 opcode(Assembler::mulx_op3, Assembler::arith_op);
7472 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7473 ins_pipe(imul_reg_imm);
7474 %}
7475
7476 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7477 match(Set dst (MulL src1 src2));
7478 ins_cost(DEFAULT_COST * 5);
7479 size(4);
7480 format %{ "MULX $src1,$src2,$dst\t! long" %}
7481 opcode(Assembler::mulx_op3, Assembler::arith_op);
7482 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7483 ins_pipe(mulL_reg_reg);
7484 %}
7485
7486 // Immediate Multiplication
7487 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7488 match(Set dst (MulL src1 src2));
7489 ins_cost(DEFAULT_COST * 5);
7490 size(4);
7491 format %{ "MULX $src1,$src2,$dst" %}
7492 opcode(Assembler::mulx_op3, Assembler::arith_op);
7493 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7494 ins_pipe(mulL_reg_imm);
7495 %}
7496
7497 // Integer Division
7498 // Register Division
7499 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7500 match(Set dst (DivI src1 src2));
7501 ins_cost((2+71)*DEFAULT_COST);
7502
7503 format %{ "SRA $src2,0,$src2\n\t"
7504 "SRA $src1,0,$src1\n\t"
7505 "SDIVX $src1,$src2,$dst" %}
7506 ins_encode( idiv_reg( src1, src2, dst ) );
7507 ins_pipe(sdiv_reg_reg);
7508 %}
7509
7510 // Immediate Division
7511 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7512 match(Set dst (DivI src1 src2));
7513 ins_cost((2+71)*DEFAULT_COST);
7514
7515 format %{ "SRA $src1,0,$src1\n\t"
7516 "SDIVX $src1,$src2,$dst" %}
7517 ins_encode( idiv_imm( src1, src2, dst ) );
7518 ins_pipe(sdiv_reg_imm);
7519 %}
7520
7521 //----------Div-By-10-Expansion------------------------------------------------
7522 // Extract hi bits of a 32x32->64 bit multiply.
7523 // Expand rule only, not matched
7524 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7525 effect( DEF dst, USE src1, USE src2 );
7526 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7527 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7528 ins_encode( enc_mul_hi(dst,src1,src2));
7529 ins_pipe(sdiv_reg_reg);
7530 %}
7531
7532 // Magic constant, reciprocal of 10
7533 instruct loadConI_x66666667(iRegIsafe dst) %{
7534 effect( DEF dst );
7535
7536 size(8);
7537 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7538 ins_encode( Set32(0x66666667, dst) );
7539 ins_pipe(ialu_hi_lo_reg);
7540 %}
7541
7542 // Register Shift Right Arithmetic Long by 32-63
7543 instruct sra_31( iRegI dst, iRegI src ) %{
7544 effect( DEF dst, USE src );
7545 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7546 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7547 ins_pipe(ialu_reg_reg);
7548 %}
7549
7550 // Arithmetic Shift Right by 8-bit immediate
7551 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7552 effect( DEF dst, USE src );
7553 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7554 opcode(Assembler::sra_op3, Assembler::arith_op);
7555 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7556 ins_pipe(ialu_reg_imm);
7557 %}
7558
7559 // Integer DIV with 10
7560 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7561 match(Set dst (DivI src div));
7562 ins_cost((6+6)*DEFAULT_COST);
7563 expand %{
7564 iRegIsafe tmp1; // Killed temps;
7565 iRegIsafe tmp2; // Killed temps;
7566 iRegI tmp3; // Killed temps;
7567 iRegI tmp4; // Killed temps;
7568 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7569 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7570 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7571 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7572 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7573 %}
7574 %}
7575
7576 // Register Long Division
7577 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7578 match(Set dst (DivL src1 src2));
7579 ins_cost(DEFAULT_COST*71);
7580 size(4);
7581 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7582 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7583 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7584 ins_pipe(divL_reg_reg);
7585 %}
7586
7587 // Register Long Division
7588 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7589 match(Set dst (DivL src1 src2));
7590 ins_cost(DEFAULT_COST*71);
7591 size(4);
7592 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7593 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7594 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7595 ins_pipe(divL_reg_imm);
7596 %}
7597
7598 // Integer Remainder
7599 // Register Remainder
7600 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7601 match(Set dst (ModI src1 src2));
7602 effect( KILL ccr, KILL temp);
7603
7604 format %{ "SREM $src1,$src2,$dst" %}
7605 ins_encode( irem_reg(src1, src2, dst, temp) );
7606 ins_pipe(sdiv_reg_reg);
7607 %}
7608
7609 // Immediate Remainder
7610 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7611 match(Set dst (ModI src1 src2));
7612 effect( KILL ccr, KILL temp);
7613
7614 format %{ "SREM $src1,$src2,$dst" %}
7615 ins_encode( irem_imm(src1, src2, dst, temp) );
7616 ins_pipe(sdiv_reg_imm);
7617 %}
7618
7619 // Register Long Remainder
7620 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7621 effect(DEF dst, USE src1, USE src2);
7622 size(4);
7623 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7624 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7625 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7626 ins_pipe(divL_reg_reg);
7627 %}
7628
7629 // Register Long Division
7630 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7631 effect(DEF dst, USE src1, USE src2);
7632 size(4);
7633 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7634 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7635 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7636 ins_pipe(divL_reg_imm);
7637 %}
7638
7639 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7640 effect(DEF dst, USE src1, USE src2);
7641 size(4);
7642 format %{ "MULX $src1,$src2,$dst\t! long" %}
7643 opcode(Assembler::mulx_op3, Assembler::arith_op);
7644 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7645 ins_pipe(mulL_reg_reg);
7646 %}
7647
7648 // Immediate Multiplication
7649 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7650 effect(DEF dst, USE src1, USE src2);
7651 size(4);
7652 format %{ "MULX $src1,$src2,$dst" %}
7653 opcode(Assembler::mulx_op3, Assembler::arith_op);
7654 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7655 ins_pipe(mulL_reg_imm);
7656 %}
7657
7658 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7659 effect(DEF dst, USE src1, USE src2);
7660 size(4);
7661 format %{ "SUB $src1,$src2,$dst\t! long" %}
7662 opcode(Assembler::sub_op3, Assembler::arith_op);
7663 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7664 ins_pipe(ialu_reg_reg);
7665 %}
7666
7667 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7668 effect(DEF dst, USE src1, USE src2);
7669 size(4);
7670 format %{ "SUB $src1,$src2,$dst\t! long" %}
7671 opcode(Assembler::sub_op3, Assembler::arith_op);
7672 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7673 ins_pipe(ialu_reg_reg);
7674 %}
7675
7676 // Register Long Remainder
7677 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7678 match(Set dst (ModL src1 src2));
7679 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7680 expand %{
7681 iRegL tmp1;
7682 iRegL tmp2;
7683 divL_reg_reg_1(tmp1, src1, src2);
7684 mulL_reg_reg_1(tmp2, tmp1, src2);
7685 subL_reg_reg_1(dst, src1, tmp2);
7686 %}
7687 %}
7688
7689 // Register Long Remainder
7690 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7691 match(Set dst (ModL src1 src2));
7692 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7693 expand %{
7694 iRegL tmp1;
7695 iRegL tmp2;
7696 divL_reg_imm13_1(tmp1, src1, src2);
7697 mulL_reg_imm13_1(tmp2, tmp1, src2);
7698 subL_reg_reg_2 (dst, src1, tmp2);
7699 %}
7700 %}
7701
7702 // Integer Shift Instructions
7703 // Register Shift Left
7704 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7705 match(Set dst (LShiftI src1 src2));
7706
7707 size(4);
7708 format %{ "SLL $src1,$src2,$dst" %}
7709 opcode(Assembler::sll_op3, Assembler::arith_op);
7710 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7711 ins_pipe(ialu_reg_reg);
7712 %}
7713
7714 // Register Shift Left Immediate
7715 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7716 match(Set dst (LShiftI src1 src2));
7717
7718 size(4);
7719 format %{ "SLL $src1,$src2,$dst" %}
7720 opcode(Assembler::sll_op3, Assembler::arith_op);
7721 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7722 ins_pipe(ialu_reg_imm);
7723 %}
7724
7725 // Register Shift Left
7726 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7727 match(Set dst (LShiftL src1 src2));
7728
7729 size(4);
7730 format %{ "SLLX $src1,$src2,$dst" %}
7731 opcode(Assembler::sllx_op3, Assembler::arith_op);
7732 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7733 ins_pipe(ialu_reg_reg);
7734 %}
7735
7736 // Register Shift Left Immediate
7737 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7738 match(Set dst (LShiftL src1 src2));
7739
7740 size(4);
7741 format %{ "SLLX $src1,$src2,$dst" %}
7742 opcode(Assembler::sllx_op3, Assembler::arith_op);
7743 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7744 ins_pipe(ialu_reg_imm);
7745 %}
7746
7747 // Register Arithmetic Shift Right
7748 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7749 match(Set dst (RShiftI src1 src2));
7750 size(4);
7751 format %{ "SRA $src1,$src2,$dst" %}
7752 opcode(Assembler::sra_op3, Assembler::arith_op);
7753 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7754 ins_pipe(ialu_reg_reg);
7755 %}
7756
7757 // Register Arithmetic Shift Right Immediate
7758 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7759 match(Set dst (RShiftI src1 src2));
7760
7761 size(4);
7762 format %{ "SRA $src1,$src2,$dst" %}
7763 opcode(Assembler::sra_op3, Assembler::arith_op);
7764 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7765 ins_pipe(ialu_reg_imm);
7766 %}
7767
7768 // Register Shift Right Arithmatic Long
7769 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7770 match(Set dst (RShiftL src1 src2));
7771
7772 size(4);
7773 format %{ "SRAX $src1,$src2,$dst" %}
7774 opcode(Assembler::srax_op3, Assembler::arith_op);
7775 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7776 ins_pipe(ialu_reg_reg);
7777 %}
7778
7779 // Register Shift Left Immediate
7780 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7781 match(Set dst (RShiftL src1 src2));
7782
7783 size(4);
7784 format %{ "SRAX $src1,$src2,$dst" %}
7785 opcode(Assembler::srax_op3, Assembler::arith_op);
7786 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7787 ins_pipe(ialu_reg_imm);
7788 %}
7789
7790 // Register Shift Right
7791 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7792 match(Set dst (URShiftI src1 src2));
7793
7794 size(4);
7795 format %{ "SRL $src1,$src2,$dst" %}
7796 opcode(Assembler::srl_op3, Assembler::arith_op);
7797 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7798 ins_pipe(ialu_reg_reg);
7799 %}
7800
7801 // Register Shift Right Immediate
7802 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7803 match(Set dst (URShiftI src1 src2));
7804
7805 size(4);
7806 format %{ "SRL $src1,$src2,$dst" %}
7807 opcode(Assembler::srl_op3, Assembler::arith_op);
7808 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7809 ins_pipe(ialu_reg_imm);
7810 %}
7811
7812 // Register Shift Right
7813 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7814 match(Set dst (URShiftL src1 src2));
7815
7816 size(4);
7817 format %{ "SRLX $src1,$src2,$dst" %}
7818 opcode(Assembler::srlx_op3, Assembler::arith_op);
7819 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7820 ins_pipe(ialu_reg_reg);
7821 %}
7822
7823 // Register Shift Right Immediate
7824 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7825 match(Set dst (URShiftL src1 src2));
7826
7827 size(4);
7828 format %{ "SRLX $src1,$src2,$dst" %}
7829 opcode(Assembler::srlx_op3, Assembler::arith_op);
7830 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7831 ins_pipe(ialu_reg_imm);
7832 %}
7833
7834 // Register Shift Right Immediate with a CastP2X
7835 #ifdef _LP64
7836 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7837 match(Set dst (URShiftL (CastP2X src1) src2));
7838 size(4);
7839 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7840 opcode(Assembler::srlx_op3, Assembler::arith_op);
7841 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7842 ins_pipe(ialu_reg_imm);
7843 %}
7844 #else
7845 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7846 match(Set dst (URShiftI (CastP2X src1) src2));
7847 size(4);
7848 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7849 opcode(Assembler::srl_op3, Assembler::arith_op);
7850 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7851 ins_pipe(ialu_reg_imm);
7852 %}
7853 #endif
7854
7855
7856 //----------Floating Point Arithmetic Instructions-----------------------------
7857
7858 // Add float single precision
7859 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7860 match(Set dst (AddF src1 src2));
7861
7862 size(4);
7863 format %{ "FADDS $src1,$src2,$dst" %}
7864 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7865 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7866 ins_pipe(faddF_reg_reg);
7867 %}
7868
7869 // Add float double precision
7870 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7871 match(Set dst (AddD src1 src2));
7872
7873 size(4);
7874 format %{ "FADDD $src1,$src2,$dst" %}
7875 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7876 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7877 ins_pipe(faddD_reg_reg);
7878 %}
7879
7880 // Sub float single precision
7881 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7882 match(Set dst (SubF src1 src2));
7883
7884 size(4);
7885 format %{ "FSUBS $src1,$src2,$dst" %}
7886 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7887 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7888 ins_pipe(faddF_reg_reg);
7889 %}
7890
7891 // Sub float double precision
7892 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7893 match(Set dst (SubD src1 src2));
7894
7895 size(4);
7896 format %{ "FSUBD $src1,$src2,$dst" %}
7897 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7898 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7899 ins_pipe(faddD_reg_reg);
7900 %}
7901
7902 // Mul float single precision
7903 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7904 match(Set dst (MulF src1 src2));
7905
7906 size(4);
7907 format %{ "FMULS $src1,$src2,$dst" %}
7908 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7909 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7910 ins_pipe(fmulF_reg_reg);
7911 %}
7912
7913 // Mul float double precision
7914 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7915 match(Set dst (MulD src1 src2));
7916
7917 size(4);
7918 format %{ "FMULD $src1,$src2,$dst" %}
7919 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7920 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7921 ins_pipe(fmulD_reg_reg);
7922 %}
7923
7924 // Div float single precision
7925 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7926 match(Set dst (DivF src1 src2));
7927
7928 size(4);
7929 format %{ "FDIVS $src1,$src2,$dst" %}
7930 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7931 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7932 ins_pipe(fdivF_reg_reg);
7933 %}
7934
7935 // Div float double precision
7936 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7937 match(Set dst (DivD src1 src2));
7938
7939 size(4);
7940 format %{ "FDIVD $src1,$src2,$dst" %}
7941 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7942 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7943 ins_pipe(fdivD_reg_reg);
7944 %}
7945
7946 // Absolute float double precision
7947 instruct absD_reg(regD dst, regD src) %{
7948 match(Set dst (AbsD src));
7949
7950 format %{ "FABSd $src,$dst" %}
7951 ins_encode(fabsd(dst, src));
7952 ins_pipe(faddD_reg);
7953 %}
7954
7955 // Absolute float single precision
7956 instruct absF_reg(regF dst, regF src) %{
7957 match(Set dst (AbsF src));
7958
7959 format %{ "FABSs $src,$dst" %}
7960 ins_encode(fabss(dst, src));
7961 ins_pipe(faddF_reg);
7962 %}
7963
7964 instruct negF_reg(regF dst, regF src) %{
7965 match(Set dst (NegF src));
7966
7967 size(4);
7968 format %{ "FNEGs $src,$dst" %}
7969 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7970 ins_encode(form3_opf_rs2F_rdF(src, dst));
7971 ins_pipe(faddF_reg);
7972 %}
7973
7974 instruct negD_reg(regD dst, regD src) %{
7975 match(Set dst (NegD src));
7976
7977 format %{ "FNEGd $src,$dst" %}
7978 ins_encode(fnegd(dst, src));
7979 ins_pipe(faddD_reg);
7980 %}
7981
7982 // Sqrt float double precision
7983 instruct sqrtF_reg_reg(regF dst, regF src) %{
7984 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7985
7986 size(4);
7987 format %{ "FSQRTS $src,$dst" %}
7988 ins_encode(fsqrts(dst, src));
7989 ins_pipe(fdivF_reg_reg);
7990 %}
7991
7992 // Sqrt float double precision
7993 instruct sqrtD_reg_reg(regD dst, regD src) %{
7994 match(Set dst (SqrtD src));
7995
7996 size(4);
7997 format %{ "FSQRTD $src,$dst" %}
7998 ins_encode(fsqrtd(dst, src));
7999 ins_pipe(fdivD_reg_reg);
8000 %}
8001
8002 //----------Logical Instructions-----------------------------------------------
8003 // And Instructions
8004 // Register And
8005 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8006 match(Set dst (AndI src1 src2));
8007
8008 size(4);
8009 format %{ "AND $src1,$src2,$dst" %}
8010 opcode(Assembler::and_op3, Assembler::arith_op);
8011 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8012 ins_pipe(ialu_reg_reg);
8013 %}
8014
8015 // Immediate And
8016 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8017 match(Set dst (AndI src1 src2));
8018
8019 size(4);
8020 format %{ "AND $src1,$src2,$dst" %}
8021 opcode(Assembler::and_op3, Assembler::arith_op);
8022 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8023 ins_pipe(ialu_reg_imm);
8024 %}
8025
8026 // Register And Long
8027 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8028 match(Set dst (AndL src1 src2));
8029
8030 ins_cost(DEFAULT_COST);
8031 size(4);
8032 format %{ "AND $src1,$src2,$dst\t! long" %}
8033 opcode(Assembler::and_op3, Assembler::arith_op);
8034 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8035 ins_pipe(ialu_reg_reg);
8036 %}
8037
8038 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8039 match(Set dst (AndL src1 con));
8040
8041 ins_cost(DEFAULT_COST);
8042 size(4);
8043 format %{ "AND $src1,$con,$dst\t! long" %}
8044 opcode(Assembler::and_op3, Assembler::arith_op);
8045 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8046 ins_pipe(ialu_reg_imm);
8047 %}
8048
8049 // Or Instructions
8050 // Register Or
8051 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8052 match(Set dst (OrI src1 src2));
8053
8054 size(4);
8055 format %{ "OR $src1,$src2,$dst" %}
8056 opcode(Assembler::or_op3, Assembler::arith_op);
8057 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8058 ins_pipe(ialu_reg_reg);
8059 %}
8060
8061 // Immediate Or
8062 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8063 match(Set dst (OrI src1 src2));
8064
8065 size(4);
8066 format %{ "OR $src1,$src2,$dst" %}
8067 opcode(Assembler::or_op3, Assembler::arith_op);
8068 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8069 ins_pipe(ialu_reg_imm);
8070 %}
8071
8072 // Register Or Long
8073 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8074 match(Set dst (OrL src1 src2));
8075
8076 ins_cost(DEFAULT_COST);
8077 size(4);
8078 format %{ "OR $src1,$src2,$dst\t! long" %}
8079 opcode(Assembler::or_op3, Assembler::arith_op);
8080 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8081 ins_pipe(ialu_reg_reg);
8082 %}
8083
8084 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8085 match(Set dst (OrL src1 con));
8086 ins_cost(DEFAULT_COST*2);
8087
8088 ins_cost(DEFAULT_COST);
8089 size(4);
8090 format %{ "OR $src1,$con,$dst\t! long" %}
8091 opcode(Assembler::or_op3, Assembler::arith_op);
8092 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8093 ins_pipe(ialu_reg_imm);
8094 %}
8095
8096 #ifndef _LP64
8097
8098 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8099 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8100 match(Set dst (OrI src1 (CastP2X src2)));
8101
8102 size(4);
8103 format %{ "OR $src1,$src2,$dst" %}
8104 opcode(Assembler::or_op3, Assembler::arith_op);
8105 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8106 ins_pipe(ialu_reg_reg);
8107 %}
8108
8109 #else
8110
8111 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8112 match(Set dst (OrL src1 (CastP2X src2)));
8113
8114 ins_cost(DEFAULT_COST);
8115 size(4);
8116 format %{ "OR $src1,$src2,$dst\t! long" %}
8117 opcode(Assembler::or_op3, Assembler::arith_op);
8118 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8119 ins_pipe(ialu_reg_reg);
8120 %}
8121
8122 #endif
8123
8124 // Xor Instructions
8125 // Register Xor
8126 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8127 match(Set dst (XorI src1 src2));
8128
8129 size(4);
8130 format %{ "XOR $src1,$src2,$dst" %}
8131 opcode(Assembler::xor_op3, Assembler::arith_op);
8132 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8133 ins_pipe(ialu_reg_reg);
8134 %}
8135
8136 // Immediate Xor
8137 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8138 match(Set dst (XorI src1 src2));
8139
8140 size(4);
8141 format %{ "XOR $src1,$src2,$dst" %}
8142 opcode(Assembler::xor_op3, Assembler::arith_op);
8143 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8144 ins_pipe(ialu_reg_imm);
8145 %}
8146
8147 // Register Xor Long
8148 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8149 match(Set dst (XorL src1 src2));
8150
8151 ins_cost(DEFAULT_COST);
8152 size(4);
8153 format %{ "XOR $src1,$src2,$dst\t! long" %}
8154 opcode(Assembler::xor_op3, Assembler::arith_op);
8155 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8156 ins_pipe(ialu_reg_reg);
8157 %}
8158
8159 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8160 match(Set dst (XorL src1 con));
8161
8162 ins_cost(DEFAULT_COST);
8163 size(4);
8164 format %{ "XOR $src1,$con,$dst\t! long" %}
8165 opcode(Assembler::xor_op3, Assembler::arith_op);
8166 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8167 ins_pipe(ialu_reg_imm);
8168 %}
8169
8170 //----------Convert to Boolean-------------------------------------------------
8171 // Nice hack for 32-bit tests but doesn't work for
8172 // 64-bit pointers.
8173 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8174 match(Set dst (Conv2B src));
8175 effect( KILL ccr );
8176 ins_cost(DEFAULT_COST*2);
8177 format %{ "CMP R_G0,$src\n\t"
8178 "ADDX R_G0,0,$dst" %}
8179 ins_encode( enc_to_bool( src, dst ) );
8180 ins_pipe(ialu_reg_ialu);
8181 %}
8182
8183 #ifndef _LP64
8184 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8185 match(Set dst (Conv2B src));
8186 effect( KILL ccr );
8187 ins_cost(DEFAULT_COST*2);
8188 format %{ "CMP R_G0,$src\n\t"
8189 "ADDX R_G0,0,$dst" %}
8190 ins_encode( enc_to_bool( src, dst ) );
8191 ins_pipe(ialu_reg_ialu);
8192 %}
8193 #else
8194 instruct convP2B( iRegI dst, iRegP src ) %{
8195 match(Set dst (Conv2B src));
8196 ins_cost(DEFAULT_COST*2);
8197 format %{ "MOV $src,$dst\n\t"
8198 "MOVRNZ $src,1,$dst" %}
8199 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8200 ins_pipe(ialu_clr_and_mover);
8201 %}
8202 #endif
8203
8204 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8205 match(Set dst (CmpLTMask src zero));
8206 effect(KILL ccr);
8207 size(4);
8208 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8209 ins_encode %{
8210 __ sra($src$$Register, 31, $dst$$Register);
8211 %}
8212 ins_pipe(ialu_reg_imm);
8213 %}
8214
8215 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8216 match(Set dst (CmpLTMask p q));
8217 effect( KILL ccr );
8218 ins_cost(DEFAULT_COST*4);
8219 format %{ "CMP $p,$q\n\t"
8220 "MOV #0,$dst\n\t"
8221 "BLT,a .+8\n\t"
8222 "MOV #-1,$dst" %}
8223 ins_encode( enc_ltmask(p,q,dst) );
8224 ins_pipe(ialu_reg_reg_ialu);
8225 %}
8226
8227 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8228 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8229 effect(KILL ccr, TEMP tmp);
8230 ins_cost(DEFAULT_COST*3);
8231
8232 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8233 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8234 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8235 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8236 ins_pipe(cadd_cmpltmask);
8237 %}
8238
8239 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8240 match(Set p (AndI (CmpLTMask p q) y));
8241 effect(KILL ccr);
8242 ins_cost(DEFAULT_COST*3);
8243
8244 format %{ "CMP $p,$q\n\t"
8245 "MOV $y,$p\n\t"
8246 "MOVge G0,$p" %}
8247 ins_encode %{
8248 __ cmp($p$$Register, $q$$Register);
8249 __ mov($y$$Register, $p$$Register);
8250 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8251 %}
8252 ins_pipe(ialu_reg_reg_ialu);
8253 %}
8254
8255 //-----------------------------------------------------------------
8256 // Direct raw moves between float and general registers using VIS3.
8257
8258 // ins_pipe(faddF_reg);
8259 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8260 predicate(UseVIS >= 3);
8261 match(Set dst (MoveF2I src));
8262
8263 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8264 ins_encode %{
8265 __ movstouw($src$$FloatRegister, $dst$$Register);
8266 %}
8267 ins_pipe(ialu_reg_reg);
8268 %}
8269
8270 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8271 predicate(UseVIS >= 3);
8272 match(Set dst (MoveI2F src));
8273
8274 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8275 ins_encode %{
8276 __ movwtos($src$$Register, $dst$$FloatRegister);
8277 %}
8278 ins_pipe(ialu_reg_reg);
8279 %}
8280
8281 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8282 predicate(UseVIS >= 3);
8283 match(Set dst (MoveD2L src));
8284
8285 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8286 ins_encode %{
8287 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8288 %}
8289 ins_pipe(ialu_reg_reg);
8290 %}
8291
8292 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8293 predicate(UseVIS >= 3);
8294 match(Set dst (MoveL2D src));
8295
8296 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8297 ins_encode %{
8298 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8299 %}
8300 ins_pipe(ialu_reg_reg);
8301 %}
8302
8303
8304 // Raw moves between float and general registers using stack.
8305
8306 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8307 match(Set dst (MoveF2I src));
8308 effect(DEF dst, USE src);
8309 ins_cost(MEMORY_REF_COST);
8310
8311 size(4);
8312 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8313 opcode(Assembler::lduw_op3);
8314 ins_encode(simple_form3_mem_reg( src, dst ) );
8315 ins_pipe(iload_mem);
8316 %}
8317
8318 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8319 match(Set dst (MoveI2F src));
8320 effect(DEF dst, USE src);
8321 ins_cost(MEMORY_REF_COST);
8322
8323 size(4);
8324 format %{ "LDF $src,$dst\t! MoveI2F" %}
8325 opcode(Assembler::ldf_op3);
8326 ins_encode(simple_form3_mem_reg(src, dst));
8327 ins_pipe(floadF_stk);
8328 %}
8329
8330 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8331 match(Set dst (MoveD2L src));
8332 effect(DEF dst, USE src);
8333 ins_cost(MEMORY_REF_COST);
8334
8335 size(4);
8336 format %{ "LDX $src,$dst\t! MoveD2L" %}
8337 opcode(Assembler::ldx_op3);
8338 ins_encode(simple_form3_mem_reg( src, dst ) );
8339 ins_pipe(iload_mem);
8340 %}
8341
8342 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8343 match(Set dst (MoveL2D src));
8344 effect(DEF dst, USE src);
8345 ins_cost(MEMORY_REF_COST);
8346
8347 size(4);
8348 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8349 opcode(Assembler::lddf_op3);
8350 ins_encode(simple_form3_mem_reg(src, dst));
8351 ins_pipe(floadD_stk);
8352 %}
8353
8354 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8355 match(Set dst (MoveF2I src));
8356 effect(DEF dst, USE src);
8357 ins_cost(MEMORY_REF_COST);
8358
8359 size(4);
8360 format %{ "STF $src,$dst\t! MoveF2I" %}
8361 opcode(Assembler::stf_op3);
8362 ins_encode(simple_form3_mem_reg(dst, src));
8363 ins_pipe(fstoreF_stk_reg);
8364 %}
8365
8366 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8367 match(Set dst (MoveI2F src));
8368 effect(DEF dst, USE src);
8369 ins_cost(MEMORY_REF_COST);
8370
8371 size(4);
8372 format %{ "STW $src,$dst\t! MoveI2F" %}
8373 opcode(Assembler::stw_op3);
8374 ins_encode(simple_form3_mem_reg( dst, src ) );
8375 ins_pipe(istore_mem_reg);
8376 %}
8377
8378 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8379 match(Set dst (MoveD2L src));
8380 effect(DEF dst, USE src);
8381 ins_cost(MEMORY_REF_COST);
8382
8383 size(4);
8384 format %{ "STDF $src,$dst\t! MoveD2L" %}
8385 opcode(Assembler::stdf_op3);
8386 ins_encode(simple_form3_mem_reg(dst, src));
8387 ins_pipe(fstoreD_stk_reg);
8388 %}
8389
8390 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8391 match(Set dst (MoveL2D src));
8392 effect(DEF dst, USE src);
8393 ins_cost(MEMORY_REF_COST);
8394
8395 size(4);
8396 format %{ "STX $src,$dst\t! MoveL2D" %}
8397 opcode(Assembler::stx_op3);
8398 ins_encode(simple_form3_mem_reg( dst, src ) );
8399 ins_pipe(istore_mem_reg);
8400 %}
8401
8402
8403 //----------Arithmetic Conversion Instructions---------------------------------
8404 // The conversions operations are all Alpha sorted. Please keep it that way!
8405
8406 instruct convD2F_reg(regF dst, regD src) %{
8407 match(Set dst (ConvD2F src));
8408 size(4);
8409 format %{ "FDTOS $src,$dst" %}
8410 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8411 ins_encode(form3_opf_rs2D_rdF(src, dst));
8412 ins_pipe(fcvtD2F);
8413 %}
8414
8415
8416 // Convert a double to an int in a float register.
8417 // If the double is a NAN, stuff a zero in instead.
8418 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8419 effect(DEF dst, USE src, KILL fcc0);
8420 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8421 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8422 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8423 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8424 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8425 "skip:" %}
8426 ins_encode(form_d2i_helper(src,dst));
8427 ins_pipe(fcvtD2I);
8428 %}
8429
8430 instruct convD2I_stk(stackSlotI dst, regD src) %{
8431 match(Set dst (ConvD2I src));
8432 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8433 expand %{
8434 regF tmp;
8435 convD2I_helper(tmp, src);
8436 regF_to_stkI(dst, tmp);
8437 %}
8438 %}
8439
8440 instruct convD2I_reg(iRegI dst, regD src) %{
8441 predicate(UseVIS >= 3);
8442 match(Set dst (ConvD2I src));
8443 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8444 expand %{
8445 regF tmp;
8446 convD2I_helper(tmp, src);
8447 MoveF2I_reg_reg(dst, tmp);
8448 %}
8449 %}
8450
8451
8452 // Convert a double to a long in a double register.
8453 // If the double is a NAN, stuff a zero in instead.
8454 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8455 effect(DEF dst, USE src, KILL fcc0);
8456 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8457 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8458 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8459 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8460 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8461 "skip:" %}
8462 ins_encode(form_d2l_helper(src,dst));
8463 ins_pipe(fcvtD2L);
8464 %}
8465
8466 instruct convD2L_stk(stackSlotL dst, regD src) %{
8467 match(Set dst (ConvD2L src));
8468 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8469 expand %{
8470 regD tmp;
8471 convD2L_helper(tmp, src);
8472 regD_to_stkL(dst, tmp);
8473 %}
8474 %}
8475
8476 instruct convD2L_reg(iRegL dst, regD src) %{
8477 predicate(UseVIS >= 3);
8478 match(Set dst (ConvD2L src));
8479 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8480 expand %{
8481 regD tmp;
8482 convD2L_helper(tmp, src);
8483 MoveD2L_reg_reg(dst, tmp);
8484 %}
8485 %}
8486
8487
8488 instruct convF2D_reg(regD dst, regF src) %{
8489 match(Set dst (ConvF2D src));
8490 format %{ "FSTOD $src,$dst" %}
8491 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8492 ins_encode(form3_opf_rs2F_rdD(src, dst));
8493 ins_pipe(fcvtF2D);
8494 %}
8495
8496
8497 // Convert a float to an int in a float register.
8498 // If the float is a NAN, stuff a zero in instead.
8499 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8500 effect(DEF dst, USE src, KILL fcc0);
8501 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8502 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8503 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8504 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8505 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8506 "skip:" %}
8507 ins_encode(form_f2i_helper(src,dst));
8508 ins_pipe(fcvtF2I);
8509 %}
8510
8511 instruct convF2I_stk(stackSlotI dst, regF src) %{
8512 match(Set dst (ConvF2I src));
8513 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8514 expand %{
8515 regF tmp;
8516 convF2I_helper(tmp, src);
8517 regF_to_stkI(dst, tmp);
8518 %}
8519 %}
8520
8521 instruct convF2I_reg(iRegI dst, regF src) %{
8522 predicate(UseVIS >= 3);
8523 match(Set dst (ConvF2I src));
8524 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8525 expand %{
8526 regF tmp;
8527 convF2I_helper(tmp, src);
8528 MoveF2I_reg_reg(dst, tmp);
8529 %}
8530 %}
8531
8532
8533 // Convert a float to a long in a float register.
8534 // If the float is a NAN, stuff a zero in instead.
8535 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8536 effect(DEF dst, USE src, KILL fcc0);
8537 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8538 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8539 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8540 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8541 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8542 "skip:" %}
8543 ins_encode(form_f2l_helper(src,dst));
8544 ins_pipe(fcvtF2L);
8545 %}
8546
8547 instruct convF2L_stk(stackSlotL dst, regF src) %{
8548 match(Set dst (ConvF2L src));
8549 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8550 expand %{
8551 regD tmp;
8552 convF2L_helper(tmp, src);
8553 regD_to_stkL(dst, tmp);
8554 %}
8555 %}
8556
8557 instruct convF2L_reg(iRegL dst, regF src) %{
8558 predicate(UseVIS >= 3);
8559 match(Set dst (ConvF2L src));
8560 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8561 expand %{
8562 regD tmp;
8563 convF2L_helper(tmp, src);
8564 MoveD2L_reg_reg(dst, tmp);
8565 %}
8566 %}
8567
8568
8569 instruct convI2D_helper(regD dst, regF tmp) %{
8570 effect(USE tmp, DEF dst);
8571 format %{ "FITOD $tmp,$dst" %}
8572 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8573 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8574 ins_pipe(fcvtI2D);
8575 %}
8576
8577 instruct convI2D_stk(stackSlotI src, regD dst) %{
8578 match(Set dst (ConvI2D src));
8579 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8580 expand %{
8581 regF tmp;
8582 stkI_to_regF(tmp, src);
8583 convI2D_helper(dst, tmp);
8584 %}
8585 %}
8586
8587 instruct convI2D_reg(regD_low dst, iRegI src) %{
8588 predicate(UseVIS >= 3);
8589 match(Set dst (ConvI2D src));
8590 expand %{
8591 regF tmp;
8592 MoveI2F_reg_reg(tmp, src);
8593 convI2D_helper(dst, tmp);
8594 %}
8595 %}
8596
8597 instruct convI2D_mem(regD_low dst, memory mem) %{
8598 match(Set dst (ConvI2D (LoadI mem)));
8599 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8600 size(8);
8601 format %{ "LDF $mem,$dst\n\t"
8602 "FITOD $dst,$dst" %}
8603 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8604 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8605 ins_pipe(floadF_mem);
8606 %}
8607
8608
8609 instruct convI2F_helper(regF dst, regF tmp) %{
8610 effect(DEF dst, USE tmp);
8611 format %{ "FITOS $tmp,$dst" %}
8612 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8613 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8614 ins_pipe(fcvtI2F);
8615 %}
8616
8617 instruct convI2F_stk(regF dst, stackSlotI src) %{
8618 match(Set dst (ConvI2F src));
8619 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8620 expand %{
8621 regF tmp;
8622 stkI_to_regF(tmp,src);
8623 convI2F_helper(dst, tmp);
8624 %}
8625 %}
8626
8627 instruct convI2F_reg(regF dst, iRegI src) %{
8628 predicate(UseVIS >= 3);
8629 match(Set dst (ConvI2F src));
8630 ins_cost(DEFAULT_COST);
8631 expand %{
8632 regF tmp;
8633 MoveI2F_reg_reg(tmp, src);
8634 convI2F_helper(dst, tmp);
8635 %}
8636 %}
8637
8638 instruct convI2F_mem( regF dst, memory mem ) %{
8639 match(Set dst (ConvI2F (LoadI mem)));
8640 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8641 size(8);
8642 format %{ "LDF $mem,$dst\n\t"
8643 "FITOS $dst,$dst" %}
8644 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8645 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8646 ins_pipe(floadF_mem);
8647 %}
8648
8649
8650 instruct convI2L_reg(iRegL dst, iRegI src) %{
8651 match(Set dst (ConvI2L src));
8652 size(4);
8653 format %{ "SRA $src,0,$dst\t! int->long" %}
8654 opcode(Assembler::sra_op3, Assembler::arith_op);
8655 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8656 ins_pipe(ialu_reg_reg);
8657 %}
8658
8659 // Zero-extend convert int to long
8660 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8661 match(Set dst (AndL (ConvI2L src) mask) );
8662 size(4);
8663 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8664 opcode(Assembler::srl_op3, Assembler::arith_op);
8665 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8666 ins_pipe(ialu_reg_reg);
8667 %}
8668
8669 // Zero-extend long
8670 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8671 match(Set dst (AndL src mask) );
8672 size(4);
8673 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8674 opcode(Assembler::srl_op3, Assembler::arith_op);
8675 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8676 ins_pipe(ialu_reg_reg);
8677 %}
8678
8679
8680 //-----------
8681 // Long to Double conversion using V8 opcodes.
8682 // Still useful because cheetah traps and becomes
8683 // amazingly slow for some common numbers.
8684
8685 // Magic constant, 0x43300000
8686 instruct loadConI_x43300000(iRegI dst) %{
8687 effect(DEF dst);
8688 size(4);
8689 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8690 ins_encode(SetHi22(0x43300000, dst));
8691 ins_pipe(ialu_none);
8692 %}
8693
8694 // Magic constant, 0x41f00000
8695 instruct loadConI_x41f00000(iRegI dst) %{
8696 effect(DEF dst);
8697 size(4);
8698 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8699 ins_encode(SetHi22(0x41f00000, dst));
8700 ins_pipe(ialu_none);
8701 %}
8702
8703 // Construct a double from two float halves
8704 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8705 effect(DEF dst, USE src1, USE src2);
8706 size(8);
8707 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8708 "FMOVS $src2.lo,$dst.lo" %}
8709 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8710 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8711 ins_pipe(faddD_reg_reg);
8712 %}
8713
8714 // Convert integer in high half of a double register (in the lower half of
8715 // the double register file) to double
8716 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8717 effect(DEF dst, USE src);
8718 size(4);
8719 format %{ "FITOD $src,$dst" %}
8720 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8721 ins_encode(form3_opf_rs2D_rdD(src, dst));
8722 ins_pipe(fcvtLHi2D);
8723 %}
8724
8725 // Add float double precision
8726 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8727 effect(DEF dst, USE src1, USE src2);
8728 size(4);
8729 format %{ "FADDD $src1,$src2,$dst" %}
8730 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8731 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8732 ins_pipe(faddD_reg_reg);
8733 %}
8734
8735 // Sub float double precision
8736 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8737 effect(DEF dst, USE src1, USE src2);
8738 size(4);
8739 format %{ "FSUBD $src1,$src2,$dst" %}
8740 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8741 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8742 ins_pipe(faddD_reg_reg);
8743 %}
8744
8745 // Mul float double precision
8746 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8747 effect(DEF dst, USE src1, USE src2);
8748 size(4);
8749 format %{ "FMULD $src1,$src2,$dst" %}
8750 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8751 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8752 ins_pipe(fmulD_reg_reg);
8753 %}
8754
8755 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8756 match(Set dst (ConvL2D src));
8757 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8758
8759 expand %{
8760 regD_low tmpsrc;
8761 iRegI ix43300000;
8762 iRegI ix41f00000;
8763 stackSlotL lx43300000;
8764 stackSlotL lx41f00000;
8765 regD_low dx43300000;
8766 regD dx41f00000;
8767 regD tmp1;
8768 regD_low tmp2;
8769 regD tmp3;
8770 regD tmp4;
8771
8772 stkL_to_regD(tmpsrc, src);
8773
8774 loadConI_x43300000(ix43300000);
8775 loadConI_x41f00000(ix41f00000);
8776 regI_to_stkLHi(lx43300000, ix43300000);
8777 regI_to_stkLHi(lx41f00000, ix41f00000);
8778 stkL_to_regD(dx43300000, lx43300000);
8779 stkL_to_regD(dx41f00000, lx41f00000);
8780
8781 convI2D_regDHi_regD(tmp1, tmpsrc);
8782 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8783 subD_regD_regD(tmp3, tmp2, dx43300000);
8784 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8785 addD_regD_regD(dst, tmp3, tmp4);
8786 %}
8787 %}
8788
8789 // Long to Double conversion using fast fxtof
8790 instruct convL2D_helper(regD dst, regD tmp) %{
8791 effect(DEF dst, USE tmp);
8792 size(4);
8793 format %{ "FXTOD $tmp,$dst" %}
8794 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8795 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8796 ins_pipe(fcvtL2D);
8797 %}
8798
8799 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8800 predicate(VM_Version::has_fast_fxtof());
8801 match(Set dst (ConvL2D src));
8802 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8803 expand %{
8804 regD tmp;
8805 stkL_to_regD(tmp, src);
8806 convL2D_helper(dst, tmp);
8807 %}
8808 %}
8809
8810 instruct convL2D_reg(regD dst, iRegL src) %{
8811 predicate(UseVIS >= 3);
8812 match(Set dst (ConvL2D src));
8813 expand %{
8814 regD tmp;
8815 MoveL2D_reg_reg(tmp, src);
8816 convL2D_helper(dst, tmp);
8817 %}
8818 %}
8819
8820 // Long to Float conversion using fast fxtof
8821 instruct convL2F_helper(regF dst, regD tmp) %{
8822 effect(DEF dst, USE tmp);
8823 size(4);
8824 format %{ "FXTOS $tmp,$dst" %}
8825 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8826 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8827 ins_pipe(fcvtL2F);
8828 %}
8829
8830 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8831 match(Set dst (ConvL2F src));
8832 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8833 expand %{
8834 regD tmp;
8835 stkL_to_regD(tmp, src);
8836 convL2F_helper(dst, tmp);
8837 %}
8838 %}
8839
8840 instruct convL2F_reg(regF dst, iRegL src) %{
8841 predicate(UseVIS >= 3);
8842 match(Set dst (ConvL2F src));
8843 ins_cost(DEFAULT_COST);
8844 expand %{
8845 regD tmp;
8846 MoveL2D_reg_reg(tmp, src);
8847 convL2F_helper(dst, tmp);
8848 %}
8849 %}
8850
8851 //-----------
8852
8853 instruct convL2I_reg(iRegI dst, iRegL src) %{
8854 match(Set dst (ConvL2I src));
8855 #ifndef _LP64
8856 format %{ "MOV $src.lo,$dst\t! long->int" %}
8857 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8858 ins_pipe(ialu_move_reg_I_to_L);
8859 #else
8860 size(4);
8861 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8862 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8863 ins_pipe(ialu_reg);
8864 #endif
8865 %}
8866
8867 // Register Shift Right Immediate
8868 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8869 match(Set dst (ConvL2I (RShiftL src cnt)));
8870
8871 size(4);
8872 format %{ "SRAX $src,$cnt,$dst" %}
8873 opcode(Assembler::srax_op3, Assembler::arith_op);
8874 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8875 ins_pipe(ialu_reg_imm);
8876 %}
8877
8878 //----------Control Flow Instructions------------------------------------------
8879 // Compare Instructions
8880 // Compare Integers
8881 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8882 match(Set icc (CmpI op1 op2));
8883 effect( DEF icc, USE op1, USE op2 );
8884
8885 size(4);
8886 format %{ "CMP $op1,$op2" %}
8887 opcode(Assembler::subcc_op3, Assembler::arith_op);
8888 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8889 ins_pipe(ialu_cconly_reg_reg);
8890 %}
8891
8892 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8893 match(Set icc (CmpU op1 op2));
8894
8895 size(4);
8896 format %{ "CMP $op1,$op2\t! unsigned" %}
8897 opcode(Assembler::subcc_op3, Assembler::arith_op);
8898 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8899 ins_pipe(ialu_cconly_reg_reg);
8900 %}
8901
8902 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8903 match(Set icc (CmpI op1 op2));
8904 effect( DEF icc, USE op1 );
8905
8906 size(4);
8907 format %{ "CMP $op1,$op2" %}
8908 opcode(Assembler::subcc_op3, Assembler::arith_op);
8909 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8910 ins_pipe(ialu_cconly_reg_imm);
8911 %}
8912
8913 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8914 match(Set icc (CmpI (AndI op1 op2) zero));
8915
8916 size(4);
8917 format %{ "BTST $op2,$op1" %}
8918 opcode(Assembler::andcc_op3, Assembler::arith_op);
8919 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8920 ins_pipe(ialu_cconly_reg_reg_zero);
8921 %}
8922
8923 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8924 match(Set icc (CmpI (AndI op1 op2) zero));
8925
8926 size(4);
8927 format %{ "BTST $op2,$op1" %}
8928 opcode(Assembler::andcc_op3, Assembler::arith_op);
8929 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8930 ins_pipe(ialu_cconly_reg_imm_zero);
8931 %}
8932
8933 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8934 match(Set xcc (CmpL op1 op2));
8935 effect( DEF xcc, USE op1, USE op2 );
8936
8937 size(4);
8938 format %{ "CMP $op1,$op2\t\t! long" %}
8939 opcode(Assembler::subcc_op3, Assembler::arith_op);
8940 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8941 ins_pipe(ialu_cconly_reg_reg);
8942 %}
8943
8944 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8945 match(Set xcc (CmpL op1 con));
8946 effect( DEF xcc, USE op1, USE con );
8947
8948 size(4);
8949 format %{ "CMP $op1,$con\t\t! long" %}
8950 opcode(Assembler::subcc_op3, Assembler::arith_op);
8951 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8952 ins_pipe(ialu_cconly_reg_reg);
8953 %}
8954
8955 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8956 match(Set xcc (CmpL (AndL op1 op2) zero));
8957 effect( DEF xcc, USE op1, USE op2 );
8958
8959 size(4);
8960 format %{ "BTST $op1,$op2\t\t! long" %}
8961 opcode(Assembler::andcc_op3, Assembler::arith_op);
8962 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8963 ins_pipe(ialu_cconly_reg_reg);
8964 %}
8965
8966 // useful for checking the alignment of a pointer:
8967 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8968 match(Set xcc (CmpL (AndL op1 con) zero));
8969 effect( DEF xcc, USE op1, USE con );
8970
8971 size(4);
8972 format %{ "BTST $op1,$con\t\t! long" %}
8973 opcode(Assembler::andcc_op3, Assembler::arith_op);
8974 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8975 ins_pipe(ialu_cconly_reg_reg);
8976 %}
8977
8978 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8979 match(Set icc (CmpU op1 op2));
8980
8981 size(4);
8982 format %{ "CMP $op1,$op2\t! unsigned" %}
8983 opcode(Assembler::subcc_op3, Assembler::arith_op);
8984 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8985 ins_pipe(ialu_cconly_reg_imm);
8986 %}
8987
8988 // Compare Pointers
8989 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8990 match(Set pcc (CmpP op1 op2));
8991
8992 size(4);
8993 format %{ "CMP $op1,$op2\t! ptr" %}
8994 opcode(Assembler::subcc_op3, Assembler::arith_op);
8995 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8996 ins_pipe(ialu_cconly_reg_reg);
8997 %}
8998
8999 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9000 match(Set pcc (CmpP op1 op2));
9001
9002 size(4);
9003 format %{ "CMP $op1,$op2\t! ptr" %}
9004 opcode(Assembler::subcc_op3, Assembler::arith_op);
9005 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9006 ins_pipe(ialu_cconly_reg_imm);
9007 %}
9008
9009 // Compare Narrow oops
9010 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9011 match(Set icc (CmpN op1 op2));
9012
9013 size(4);
9014 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9015 opcode(Assembler::subcc_op3, Assembler::arith_op);
9016 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9017 ins_pipe(ialu_cconly_reg_reg);
9018 %}
9019
9020 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9021 match(Set icc (CmpN op1 op2));
9022
9023 size(4);
9024 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9025 opcode(Assembler::subcc_op3, Assembler::arith_op);
9026 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9027 ins_pipe(ialu_cconly_reg_imm);
9028 %}
9029
9030 //----------Max and Min--------------------------------------------------------
9031 // Min Instructions
9032 // Conditional move for min
9033 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9034 effect( USE_DEF op2, USE op1, USE icc );
9035
9036 size(4);
9037 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9038 opcode(Assembler::less);
9039 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9040 ins_pipe(ialu_reg_flags);
9041 %}
9042
9043 // Min Register with Register.
9044 instruct minI_eReg(iRegI op1, iRegI op2) %{
9045 match(Set op2 (MinI op1 op2));
9046 ins_cost(DEFAULT_COST*2);
9047 expand %{
9048 flagsReg icc;
9049 compI_iReg(icc,op1,op2);
9050 cmovI_reg_lt(op2,op1,icc);
9051 %}
9052 %}
9053
9054 // Max Instructions
9055 // Conditional move for max
9056 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9057 effect( USE_DEF op2, USE op1, USE icc );
9058 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9059 opcode(Assembler::greater);
9060 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9061 ins_pipe(ialu_reg_flags);
9062 %}
9063
9064 // Max Register with Register
9065 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9066 match(Set op2 (MaxI op1 op2));
9067 ins_cost(DEFAULT_COST*2);
9068 expand %{
9069 flagsReg icc;
9070 compI_iReg(icc,op1,op2);
9071 cmovI_reg_gt(op2,op1,icc);
9072 %}
9073 %}
9074
9075
9076 //----------Float Compares----------------------------------------------------
9077 // Compare floating, generate condition code
9078 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9079 match(Set fcc (CmpF src1 src2));
9080
9081 size(4);
9082 format %{ "FCMPs $fcc,$src1,$src2" %}
9083 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9084 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9085 ins_pipe(faddF_fcc_reg_reg_zero);
9086 %}
9087
9088 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9089 match(Set fcc (CmpD src1 src2));
9090
9091 size(4);
9092 format %{ "FCMPd $fcc,$src1,$src2" %}
9093 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9094 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9095 ins_pipe(faddD_fcc_reg_reg_zero);
9096 %}
9097
9098
9099 // Compare floating, generate -1,0,1
9100 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9101 match(Set dst (CmpF3 src1 src2));
9102 effect(KILL fcc0);
9103 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9104 format %{ "fcmpl $dst,$src1,$src2" %}
9105 // Primary = float
9106 opcode( true );
9107 ins_encode( floating_cmp( dst, src1, src2 ) );
9108 ins_pipe( floating_cmp );
9109 %}
9110
9111 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9112 match(Set dst (CmpD3 src1 src2));
9113 effect(KILL fcc0);
9114 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9115 format %{ "dcmpl $dst,$src1,$src2" %}
9116 // Primary = double (not float)
9117 opcode( false );
9118 ins_encode( floating_cmp( dst, src1, src2 ) );
9119 ins_pipe( floating_cmp );
9120 %}
9121
9122 //----------Branches---------------------------------------------------------
9123 // Jump
9124 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9125 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9126 match(Jump switch_val);
9127 effect(TEMP table);
9128
9129 ins_cost(350);
9130
9131 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9132 "LD [O7 + $switch_val], O7\n\t"
9133 "JUMP O7" %}
9134 ins_encode %{
9135 // Calculate table address into a register.
9136 Register table_reg;
9137 Register label_reg = O7;
9138 // If we are calculating the size of this instruction don't trust
9139 // zero offsets because they might change when
9140 // MachConstantBaseNode decides to optimize the constant table
9141 // base.
9142 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9143 table_reg = $constanttablebase;
9144 } else {
9145 table_reg = O7;
9146 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9147 __ add($constanttablebase, con_offset, table_reg);
9148 }
9149
9150 // Jump to base address + switch value
9151 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9152 __ jmp(label_reg, G0);
9153 __ delayed()->nop();
9154 %}
9155 ins_pipe(ialu_reg_reg);
9156 %}
9157
9158 // Direct Branch. Use V8 version with longer range.
9159 instruct branch(label labl) %{
9160 match(Goto);
9161 effect(USE labl);
9162
9163 size(8);
9164 ins_cost(BRANCH_COST);
9165 format %{ "BA $labl" %}
9166 ins_encode %{
9167 Label* L = $labl$$label;
9168 __ ba(*L);
9169 __ delayed()->nop();
9170 %}
9171 ins_pipe(br);
9172 %}
9173
9174 // Direct Branch, short with no delay slot
9175 instruct branch_short(label labl) %{
9176 match(Goto);
9177 predicate(UseCBCond);
9178 effect(USE labl);
9179
9180 size(4);
9181 ins_cost(BRANCH_COST);
9182 format %{ "BA $labl\t! short branch" %}
9183 ins_encode %{
9184 Label* L = $labl$$label;
9185 assert(__ use_cbcond(*L), "back to back cbcond");
9186 __ ba_short(*L);
9187 %}
9188 ins_short_branch(1);
9189 ins_avoid_back_to_back(1);
9190 ins_pipe(cbcond_reg_imm);
9191 %}
9192
9193 // Conditional Direct Branch
9194 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9195 match(If cmp icc);
9196 effect(USE labl);
9197
9198 size(8);
9199 ins_cost(BRANCH_COST);
9200 format %{ "BP$cmp $icc,$labl" %}
9201 // Prim = bits 24-22, Secnd = bits 31-30
9202 ins_encode( enc_bp( labl, cmp, icc ) );
9203 ins_pipe(br_cc);
9204 %}
9205
9206 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9207 match(If cmp icc);
9208 effect(USE labl);
9209
9210 ins_cost(BRANCH_COST);
9211 format %{ "BP$cmp $icc,$labl" %}
9212 // Prim = bits 24-22, Secnd = bits 31-30
9213 ins_encode( enc_bp( labl, cmp, icc ) );
9214 ins_pipe(br_cc);
9215 %}
9216
9217 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9218 match(If cmp pcc);
9219 effect(USE labl);
9220
9221 size(8);
9222 ins_cost(BRANCH_COST);
9223 format %{ "BP$cmp $pcc,$labl" %}
9224 ins_encode %{
9225 Label* L = $labl$$label;
9226 Assembler::Predict predict_taken =
9227 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9228
9229 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9230 __ delayed()->nop();
9231 %}
9232 ins_pipe(br_cc);
9233 %}
9234
9235 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9236 match(If cmp fcc);
9237 effect(USE labl);
9238
9239 size(8);
9240 ins_cost(BRANCH_COST);
9241 format %{ "FBP$cmp $fcc,$labl" %}
9242 ins_encode %{
9243 Label* L = $labl$$label;
9244 Assembler::Predict predict_taken =
9245 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9246
9247 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9248 __ delayed()->nop();
9249 %}
9250 ins_pipe(br_fcc);
9251 %}
9252
9253 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9254 match(CountedLoopEnd cmp icc);
9255 effect(USE labl);
9256
9257 size(8);
9258 ins_cost(BRANCH_COST);
9259 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9260 // Prim = bits 24-22, Secnd = bits 31-30
9261 ins_encode( enc_bp( labl, cmp, icc ) );
9262 ins_pipe(br_cc);
9263 %}
9264
9265 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9266 match(CountedLoopEnd cmp icc);
9267 effect(USE labl);
9268
9269 size(8);
9270 ins_cost(BRANCH_COST);
9271 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9272 // Prim = bits 24-22, Secnd = bits 31-30
9273 ins_encode( enc_bp( labl, cmp, icc ) );
9274 ins_pipe(br_cc);
9275 %}
9276
9277 // Compare and branch instructions
9278 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9279 match(If cmp (CmpI op1 op2));
9280 effect(USE labl, KILL icc);
9281
9282 size(12);
9283 ins_cost(BRANCH_COST);
9284 format %{ "CMP $op1,$op2\t! int\n\t"
9285 "BP$cmp $labl" %}
9286 ins_encode %{
9287 Label* L = $labl$$label;
9288 Assembler::Predict predict_taken =
9289 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9290 __ cmp($op1$$Register, $op2$$Register);
9291 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9292 __ delayed()->nop();
9293 %}
9294 ins_pipe(cmp_br_reg_reg);
9295 %}
9296
9297 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9298 match(If cmp (CmpI op1 op2));
9299 effect(USE labl, KILL icc);
9300
9301 size(12);
9302 ins_cost(BRANCH_COST);
9303 format %{ "CMP $op1,$op2\t! int\n\t"
9304 "BP$cmp $labl" %}
9305 ins_encode %{
9306 Label* L = $labl$$label;
9307 Assembler::Predict predict_taken =
9308 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9309 __ cmp($op1$$Register, $op2$$constant);
9310 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9311 __ delayed()->nop();
9312 %}
9313 ins_pipe(cmp_br_reg_imm);
9314 %}
9315
9316 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9317 match(If cmp (CmpU op1 op2));
9318 effect(USE labl, KILL icc);
9319
9320 size(12);
9321 ins_cost(BRANCH_COST);
9322 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9323 "BP$cmp $labl" %}
9324 ins_encode %{
9325 Label* L = $labl$$label;
9326 Assembler::Predict predict_taken =
9327 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9328 __ cmp($op1$$Register, $op2$$Register);
9329 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9330 __ delayed()->nop();
9331 %}
9332 ins_pipe(cmp_br_reg_reg);
9333 %}
9334
9335 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9336 match(If cmp (CmpU op1 op2));
9337 effect(USE labl, KILL icc);
9338
9339 size(12);
9340 ins_cost(BRANCH_COST);
9341 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9342 "BP$cmp $labl" %}
9343 ins_encode %{
9344 Label* L = $labl$$label;
9345 Assembler::Predict predict_taken =
9346 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9347 __ cmp($op1$$Register, $op2$$constant);
9348 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9349 __ delayed()->nop();
9350 %}
9351 ins_pipe(cmp_br_reg_imm);
9352 %}
9353
9354 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9355 match(If cmp (CmpL op1 op2));
9356 effect(USE labl, KILL xcc);
9357
9358 size(12);
9359 ins_cost(BRANCH_COST);
9360 format %{ "CMP $op1,$op2\t! long\n\t"
9361 "BP$cmp $labl" %}
9362 ins_encode %{
9363 Label* L = $labl$$label;
9364 Assembler::Predict predict_taken =
9365 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9366 __ cmp($op1$$Register, $op2$$Register);
9367 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9368 __ delayed()->nop();
9369 %}
9370 ins_pipe(cmp_br_reg_reg);
9371 %}
9372
9373 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9374 match(If cmp (CmpL op1 op2));
9375 effect(USE labl, KILL xcc);
9376
9377 size(12);
9378 ins_cost(BRANCH_COST);
9379 format %{ "CMP $op1,$op2\t! long\n\t"
9380 "BP$cmp $labl" %}
9381 ins_encode %{
9382 Label* L = $labl$$label;
9383 Assembler::Predict predict_taken =
9384 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9385 __ cmp($op1$$Register, $op2$$constant);
9386 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9387 __ delayed()->nop();
9388 %}
9389 ins_pipe(cmp_br_reg_imm);
9390 %}
9391
9392 // Compare Pointers and branch
9393 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9394 match(If cmp (CmpP op1 op2));
9395 effect(USE labl, KILL pcc);
9396
9397 size(12);
9398 ins_cost(BRANCH_COST);
9399 format %{ "CMP $op1,$op2\t! ptr\n\t"
9400 "B$cmp $labl" %}
9401 ins_encode %{
9402 Label* L = $labl$$label;
9403 Assembler::Predict predict_taken =
9404 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9405 __ cmp($op1$$Register, $op2$$Register);
9406 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9407 __ delayed()->nop();
9408 %}
9409 ins_pipe(cmp_br_reg_reg);
9410 %}
9411
9412 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9413 match(If cmp (CmpP op1 null));
9414 effect(USE labl, KILL pcc);
9415
9416 size(12);
9417 ins_cost(BRANCH_COST);
9418 format %{ "CMP $op1,0\t! ptr\n\t"
9419 "B$cmp $labl" %}
9420 ins_encode %{
9421 Label* L = $labl$$label;
9422 Assembler::Predict predict_taken =
9423 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9424 __ cmp($op1$$Register, G0);
9425 // bpr() is not used here since it has shorter distance.
9426 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9427 __ delayed()->nop();
9428 %}
9429 ins_pipe(cmp_br_reg_reg);
9430 %}
9431
9432 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9433 match(If cmp (CmpN op1 op2));
9434 effect(USE labl, KILL icc);
9435
9436 size(12);
9437 ins_cost(BRANCH_COST);
9438 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9439 "BP$cmp $labl" %}
9440 ins_encode %{
9441 Label* L = $labl$$label;
9442 Assembler::Predict predict_taken =
9443 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9444 __ cmp($op1$$Register, $op2$$Register);
9445 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9446 __ delayed()->nop();
9447 %}
9448 ins_pipe(cmp_br_reg_reg);
9449 %}
9450
9451 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9452 match(If cmp (CmpN op1 null));
9453 effect(USE labl, KILL icc);
9454
9455 size(12);
9456 ins_cost(BRANCH_COST);
9457 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9458 "BP$cmp $labl" %}
9459 ins_encode %{
9460 Label* L = $labl$$label;
9461 Assembler::Predict predict_taken =
9462 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9463 __ cmp($op1$$Register, G0);
9464 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9465 __ delayed()->nop();
9466 %}
9467 ins_pipe(cmp_br_reg_reg);
9468 %}
9469
9470 // Loop back branch
9471 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9472 match(CountedLoopEnd cmp (CmpI op1 op2));
9473 effect(USE labl, KILL icc);
9474
9475 size(12);
9476 ins_cost(BRANCH_COST);
9477 format %{ "CMP $op1,$op2\t! int\n\t"
9478 "BP$cmp $labl\t! Loop end" %}
9479 ins_encode %{
9480 Label* L = $labl$$label;
9481 Assembler::Predict predict_taken =
9482 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9483 __ cmp($op1$$Register, $op2$$Register);
9484 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9485 __ delayed()->nop();
9486 %}
9487 ins_pipe(cmp_br_reg_reg);
9488 %}
9489
9490 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9491 match(CountedLoopEnd cmp (CmpI op1 op2));
9492 effect(USE labl, KILL icc);
9493
9494 size(12);
9495 ins_cost(BRANCH_COST);
9496 format %{ "CMP $op1,$op2\t! int\n\t"
9497 "BP$cmp $labl\t! Loop end" %}
9498 ins_encode %{
9499 Label* L = $labl$$label;
9500 Assembler::Predict predict_taken =
9501 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9502 __ cmp($op1$$Register, $op2$$constant);
9503 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9504 __ delayed()->nop();
9505 %}
9506 ins_pipe(cmp_br_reg_imm);
9507 %}
9508
9509 // Short compare and branch instructions
9510 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9511 match(If cmp (CmpI op1 op2));
9512 predicate(UseCBCond);
9513 effect(USE labl, KILL icc);
9514
9515 size(4);
9516 ins_cost(BRANCH_COST);
9517 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9518 ins_encode %{
9519 Label* L = $labl$$label;
9520 assert(__ use_cbcond(*L), "back to back cbcond");
9521 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9522 %}
9523 ins_short_branch(1);
9524 ins_avoid_back_to_back(1);
9525 ins_pipe(cbcond_reg_reg);
9526 %}
9527
9528 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9529 match(If cmp (CmpI op1 op2));
9530 predicate(UseCBCond);
9531 effect(USE labl, KILL icc);
9532
9533 size(4);
9534 ins_cost(BRANCH_COST);
9535 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9536 ins_encode %{
9537 Label* L = $labl$$label;
9538 assert(__ use_cbcond(*L), "back to back cbcond");
9539 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9540 %}
9541 ins_short_branch(1);
9542 ins_avoid_back_to_back(1);
9543 ins_pipe(cbcond_reg_imm);
9544 %}
9545
9546 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9547 match(If cmp (CmpU op1 op2));
9548 predicate(UseCBCond);
9549 effect(USE labl, KILL icc);
9550
9551 size(4);
9552 ins_cost(BRANCH_COST);
9553 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9554 ins_encode %{
9555 Label* L = $labl$$label;
9556 assert(__ use_cbcond(*L), "back to back cbcond");
9557 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9558 %}
9559 ins_short_branch(1);
9560 ins_avoid_back_to_back(1);
9561 ins_pipe(cbcond_reg_reg);
9562 %}
9563
9564 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9565 match(If cmp (CmpU op1 op2));
9566 predicate(UseCBCond);
9567 effect(USE labl, KILL icc);
9568
9569 size(4);
9570 ins_cost(BRANCH_COST);
9571 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9572 ins_encode %{
9573 Label* L = $labl$$label;
9574 assert(__ use_cbcond(*L), "back to back cbcond");
9575 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9576 %}
9577 ins_short_branch(1);
9578 ins_avoid_back_to_back(1);
9579 ins_pipe(cbcond_reg_imm);
9580 %}
9581
9582 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9583 match(If cmp (CmpL op1 op2));
9584 predicate(UseCBCond);
9585 effect(USE labl, KILL xcc);
9586
9587 size(4);
9588 ins_cost(BRANCH_COST);
9589 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9590 ins_encode %{
9591 Label* L = $labl$$label;
9592 assert(__ use_cbcond(*L), "back to back cbcond");
9593 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9594 %}
9595 ins_short_branch(1);
9596 ins_avoid_back_to_back(1);
9597 ins_pipe(cbcond_reg_reg);
9598 %}
9599
9600 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9601 match(If cmp (CmpL op1 op2));
9602 predicate(UseCBCond);
9603 effect(USE labl, KILL xcc);
9604
9605 size(4);
9606 ins_cost(BRANCH_COST);
9607 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9608 ins_encode %{
9609 Label* L = $labl$$label;
9610 assert(__ use_cbcond(*L), "back to back cbcond");
9611 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9612 %}
9613 ins_short_branch(1);
9614 ins_avoid_back_to_back(1);
9615 ins_pipe(cbcond_reg_imm);
9616 %}
9617
9618 // Compare Pointers and branch
9619 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9620 match(If cmp (CmpP op1 op2));
9621 predicate(UseCBCond);
9622 effect(USE labl, KILL pcc);
9623
9624 size(4);
9625 ins_cost(BRANCH_COST);
9626 #ifdef _LP64
9627 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9628 #else
9629 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9630 #endif
9631 ins_encode %{
9632 Label* L = $labl$$label;
9633 assert(__ use_cbcond(*L), "back to back cbcond");
9634 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9635 %}
9636 ins_short_branch(1);
9637 ins_avoid_back_to_back(1);
9638 ins_pipe(cbcond_reg_reg);
9639 %}
9640
9641 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9642 match(If cmp (CmpP op1 null));
9643 predicate(UseCBCond);
9644 effect(USE labl, KILL pcc);
9645
9646 size(4);
9647 ins_cost(BRANCH_COST);
9648 #ifdef _LP64
9649 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9650 #else
9651 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9652 #endif
9653 ins_encode %{
9654 Label* L = $labl$$label;
9655 assert(__ use_cbcond(*L), "back to back cbcond");
9656 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9657 %}
9658 ins_short_branch(1);
9659 ins_avoid_back_to_back(1);
9660 ins_pipe(cbcond_reg_reg);
9661 %}
9662
9663 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9664 match(If cmp (CmpN op1 op2));
9665 predicate(UseCBCond);
9666 effect(USE labl, KILL icc);
9667
9668 size(4);
9669 ins_cost(BRANCH_COST);
9670 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9671 ins_encode %{
9672 Label* L = $labl$$label;
9673 assert(__ use_cbcond(*L), "back to back cbcond");
9674 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9675 %}
9676 ins_short_branch(1);
9677 ins_avoid_back_to_back(1);
9678 ins_pipe(cbcond_reg_reg);
9679 %}
9680
9681 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9682 match(If cmp (CmpN op1 null));
9683 predicate(UseCBCond);
9684 effect(USE labl, KILL icc);
9685
9686 size(4);
9687 ins_cost(BRANCH_COST);
9688 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9689 ins_encode %{
9690 Label* L = $labl$$label;
9691 assert(__ use_cbcond(*L), "back to back cbcond");
9692 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9693 %}
9694 ins_short_branch(1);
9695 ins_avoid_back_to_back(1);
9696 ins_pipe(cbcond_reg_reg);
9697 %}
9698
9699 // Loop back branch
9700 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9701 match(CountedLoopEnd cmp (CmpI op1 op2));
9702 predicate(UseCBCond);
9703 effect(USE labl, KILL icc);
9704
9705 size(4);
9706 ins_cost(BRANCH_COST);
9707 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9708 ins_encode %{
9709 Label* L = $labl$$label;
9710 assert(__ use_cbcond(*L), "back to back cbcond");
9711 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9712 %}
9713 ins_short_branch(1);
9714 ins_avoid_back_to_back(1);
9715 ins_pipe(cbcond_reg_reg);
9716 %}
9717
9718 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9719 match(CountedLoopEnd cmp (CmpI op1 op2));
9720 predicate(UseCBCond);
9721 effect(USE labl, KILL icc);
9722
9723 size(4);
9724 ins_cost(BRANCH_COST);
9725 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9726 ins_encode %{
9727 Label* L = $labl$$label;
9728 assert(__ use_cbcond(*L), "back to back cbcond");
9729 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9730 %}
9731 ins_short_branch(1);
9732 ins_avoid_back_to_back(1);
9733 ins_pipe(cbcond_reg_imm);
9734 %}
9735
9736 // Branch-on-register tests all 64 bits. We assume that values
9737 // in 64-bit registers always remains zero or sign extended
9738 // unless our code munges the high bits. Interrupts can chop
9739 // the high order bits to zero or sign at any time.
9740 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9741 match(If cmp (CmpI op1 zero));
9742 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9743 effect(USE labl);
9744
9745 size(8);
9746 ins_cost(BRANCH_COST);
9747 format %{ "BR$cmp $op1,$labl" %}
9748 ins_encode( enc_bpr( labl, cmp, op1 ) );
9749 ins_pipe(br_reg);
9750 %}
9751
9752 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9753 match(If cmp (CmpP op1 null));
9754 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9755 effect(USE labl);
9756
9757 size(8);
9758 ins_cost(BRANCH_COST);
9759 format %{ "BR$cmp $op1,$labl" %}
9760 ins_encode( enc_bpr( labl, cmp, op1 ) );
9761 ins_pipe(br_reg);
9762 %}
9763
9764 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9765 match(If cmp (CmpL op1 zero));
9766 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9767 effect(USE labl);
9768
9769 size(8);
9770 ins_cost(BRANCH_COST);
9771 format %{ "BR$cmp $op1,$labl" %}
9772 ins_encode( enc_bpr( labl, cmp, op1 ) );
9773 ins_pipe(br_reg);
9774 %}
9775
9776
9777 // ============================================================================
9778 // Long Compare
9779 //
9780 // Currently we hold longs in 2 registers. Comparing such values efficiently
9781 // is tricky. The flavor of compare used depends on whether we are testing
9782 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9783 // The GE test is the negated LT test. The LE test can be had by commuting
9784 // the operands (yielding a GE test) and then negating; negate again for the
9785 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9786 // NE test is negated from that.
9787
9788 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9789 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9790 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9791 // are collapsed internally in the ADLC's dfa-gen code. The match for
9792 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9793 // foo match ends up with the wrong leaf. One fix is to not match both
9794 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9795 // both forms beat the trinary form of long-compare and both are very useful
9796 // on Intel which has so few registers.
9797
9798 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9799 match(If cmp xcc);
9800 effect(USE labl);
9801
9802 size(8);
9803 ins_cost(BRANCH_COST);
9804 format %{ "BP$cmp $xcc,$labl" %}
9805 ins_encode %{
9806 Label* L = $labl$$label;
9807 Assembler::Predict predict_taken =
9808 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9809
9810 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9811 __ delayed()->nop();
9812 %}
9813 ins_pipe(br_cc);
9814 %}
9815
9816 // Manifest a CmpL3 result in an integer register. Very painful.
9817 // This is the test to avoid.
9818 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9819 match(Set dst (CmpL3 src1 src2) );
9820 effect( KILL ccr );
9821 ins_cost(6*DEFAULT_COST);
9822 size(24);
9823 format %{ "CMP $src1,$src2\t\t! long\n"
9824 "\tBLT,a,pn done\n"
9825 "\tMOV -1,$dst\t! delay slot\n"
9826 "\tBGT,a,pn done\n"
9827 "\tMOV 1,$dst\t! delay slot\n"
9828 "\tCLR $dst\n"
9829 "done:" %}
9830 ins_encode( cmpl_flag(src1,src2,dst) );
9831 ins_pipe(cmpL_reg);
9832 %}
9833
9834 // Conditional move
9835 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9836 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9837 ins_cost(150);
9838 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9839 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9840 ins_pipe(ialu_reg);
9841 %}
9842
9843 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9844 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9845 ins_cost(140);
9846 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9847 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9848 ins_pipe(ialu_imm);
9849 %}
9850
9851 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9852 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9853 ins_cost(150);
9854 format %{ "MOV$cmp $xcc,$src,$dst" %}
9855 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9856 ins_pipe(ialu_reg);
9857 %}
9858
9859 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9860 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9861 ins_cost(140);
9862 format %{ "MOV$cmp $xcc,$src,$dst" %}
9863 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9864 ins_pipe(ialu_imm);
9865 %}
9866
9867 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9868 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9869 ins_cost(150);
9870 format %{ "MOV$cmp $xcc,$src,$dst" %}
9871 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9872 ins_pipe(ialu_reg);
9873 %}
9874
9875 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9876 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9877 ins_cost(150);
9878 format %{ "MOV$cmp $xcc,$src,$dst" %}
9879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9880 ins_pipe(ialu_reg);
9881 %}
9882
9883 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9884 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9885 ins_cost(140);
9886 format %{ "MOV$cmp $xcc,$src,$dst" %}
9887 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9888 ins_pipe(ialu_imm);
9889 %}
9890
9891 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9892 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9893 ins_cost(150);
9894 opcode(0x101);
9895 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9896 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9897 ins_pipe(int_conditional_float_move);
9898 %}
9899
9900 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9901 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9902 ins_cost(150);
9903 opcode(0x102);
9904 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9905 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9906 ins_pipe(int_conditional_float_move);
9907 %}
9908
9909 // ============================================================================
9910 // Safepoint Instruction
9911 instruct safePoint_poll(iRegP poll) %{
9912 match(SafePoint poll);
9913 effect(USE poll);
9914
9915 size(4);
9916 #ifdef _LP64
9917 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9918 #else
9919 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9920 #endif
9921 ins_encode %{
9922 __ relocate(relocInfo::poll_type);
9923 __ ld_ptr($poll$$Register, 0, G0);
9924 %}
9925 ins_pipe(loadPollP);
9926 %}
9927
9928 // ============================================================================
9929 // Call Instructions
9930 // Call Java Static Instruction
9931 instruct CallStaticJavaDirect( method meth ) %{
9932 match(CallStaticJava);
9933 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9934 effect(USE meth);
9935
9936 size(8);
9937 ins_cost(CALL_COST);
9938 format %{ "CALL,static ; NOP ==> " %}
9939 ins_encode( Java_Static_Call( meth ), call_epilog );
9940 ins_pipe(simple_call);
9941 %}
9942
9943 // Call Java Static Instruction (method handle version)
9944 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9945 match(CallStaticJava);
9946 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9947 effect(USE meth, KILL l7_mh_SP_save);
9948
9949 size(16);
9950 ins_cost(CALL_COST);
9951 format %{ "CALL,static/MethodHandle" %}
9952 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9953 ins_pipe(simple_call);
9954 %}
9955
9956 // Call Java Dynamic Instruction
9957 instruct CallDynamicJavaDirect( method meth ) %{
9958 match(CallDynamicJava);
9959 effect(USE meth);
9960
9961 ins_cost(CALL_COST);
9962 format %{ "SET (empty),R_G5\n\t"
9963 "CALL,dynamic ; NOP ==> " %}
9964 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9965 ins_pipe(call);
9966 %}
9967
9968 // Call Runtime Instruction
9969 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9970 match(CallRuntime);
9971 effect(USE meth, KILL l7);
9972 ins_cost(CALL_COST);
9973 format %{ "CALL,runtime" %}
9974 ins_encode( Java_To_Runtime( meth ),
9975 call_epilog, adjust_long_from_native_call );
9976 ins_pipe(simple_call);
9977 %}
9978
9979 // Call runtime without safepoint - same as CallRuntime
9980 instruct CallLeafDirect(method meth, l7RegP l7) %{
9981 match(CallLeaf);
9982 effect(USE meth, KILL l7);
9983 ins_cost(CALL_COST);
9984 format %{ "CALL,runtime leaf" %}
9985 ins_encode( Java_To_Runtime( meth ),
9986 call_epilog,
9987 adjust_long_from_native_call );
9988 ins_pipe(simple_call);
9989 %}
9990
9991 // Call runtime without safepoint - same as CallLeaf
9992 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9993 match(CallLeafNoFP);
9994 effect(USE meth, KILL l7);
9995 ins_cost(CALL_COST);
9996 format %{ "CALL,runtime leaf nofp" %}
9997 ins_encode( Java_To_Runtime( meth ),
9998 call_epilog,
9999 adjust_long_from_native_call );
10000 ins_pipe(simple_call);
10001 %}
10002
10003 // Tail Call; Jump from runtime stub to Java code.
10004 // Also known as an 'interprocedural jump'.
10005 // Target of jump will eventually return to caller.
10006 // TailJump below removes the return address.
10007 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10008 match(TailCall jump_target method_oop );
10009
10010 ins_cost(CALL_COST);
10011 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10012 ins_encode(form_jmpl(jump_target));
10013 ins_pipe(tail_call);
10014 %}
10015
10016
10017 // Return Instruction
10018 instruct Ret() %{
10019 match(Return);
10020
10021 // The epilogue node did the ret already.
10022 size(0);
10023 format %{ "! return" %}
10024 ins_encode();
10025 ins_pipe(empty);
10026 %}
10027
10028
10029 // Tail Jump; remove the return address; jump to target.
10030 // TailCall above leaves the return address around.
10031 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10032 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10033 // "restore" before this instruction (in Epilogue), we need to materialize it
10034 // in %i0.
10035 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10036 match( TailJump jump_target ex_oop );
10037 ins_cost(CALL_COST);
10038 format %{ "! discard R_O7\n\t"
10039 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10040 ins_encode(form_jmpl_set_exception_pc(jump_target));
10041 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10042 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10043 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10044 ins_pipe(tail_call);
10045 %}
10046
10047 // Create exception oop: created by stack-crawling runtime code.
10048 // Created exception is now available to this handler, and is setup
10049 // just prior to jumping to this handler. No code emitted.
10050 instruct CreateException( o0RegP ex_oop )
10051 %{
10052 match(Set ex_oop (CreateEx));
10053 ins_cost(0);
10054
10055 size(0);
10056 // use the following format syntax
10057 format %{ "! exception oop is in R_O0; no code emitted" %}
10058 ins_encode();
10059 ins_pipe(empty);
10060 %}
10061
10062
10063 // Rethrow exception:
10064 // The exception oop will come in the first argument position.
10065 // Then JUMP (not call) to the rethrow stub code.
10066 instruct RethrowException()
10067 %{
10068 match(Rethrow);
10069 ins_cost(CALL_COST);
10070
10071 // use the following format syntax
10072 format %{ "Jmp rethrow_stub" %}
10073 ins_encode(enc_rethrow);
10074 ins_pipe(tail_call);
10075 %}
10076
10077
10078 // Die now
10079 instruct ShouldNotReachHere( )
10080 %{
10081 match(Halt);
10082 ins_cost(CALL_COST);
10083
10084 size(4);
10085 // Use the following format syntax
10086 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10087 ins_encode( form2_illtrap() );
10088 ins_pipe(tail_call);
10089 %}
10090
10091 // ============================================================================
10092 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10093 // array for an instance of the superklass. Set a hidden internal cache on a
10094 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10095 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10096 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10097 match(Set index (PartialSubtypeCheck sub super));
10098 effect( KILL pcc, KILL o7 );
10099 ins_cost(DEFAULT_COST*10);
10100 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10101 ins_encode( enc_PartialSubtypeCheck() );
10102 ins_pipe(partial_subtype_check_pipe);
10103 %}
10104
10105 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10106 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10107 effect( KILL idx, KILL o7 );
10108 ins_cost(DEFAULT_COST*10);
10109 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10110 ins_encode( enc_PartialSubtypeCheck() );
10111 ins_pipe(partial_subtype_check_pipe);
10112 %}
10113
10114
10115 // ============================================================================
10116 // inlined locking and unlocking
10117
10118 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10119 match(Set pcc (FastLock object box));
10120
10121 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10122 ins_cost(100);
10123
10124 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10125 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10126 ins_pipe(long_memory_op);
10127 %}
10128
10129
10130 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10131 match(Set pcc (FastUnlock object box));
10132 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10133 ins_cost(100);
10134
10135 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10136 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10137 ins_pipe(long_memory_op);
10138 %}
10139
10140 // The encodings are generic.
10141 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10142 predicate(!use_block_zeroing(n->in(2)) );
10143 match(Set dummy (ClearArray cnt base));
10144 effect(TEMP temp, KILL ccr);
10145 ins_cost(300);
10146 format %{ "MOV $cnt,$temp\n"
10147 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10148 " BRge loop\t\t! Clearing loop\n"
10149 " STX G0,[$base+$temp]\t! delay slot" %}
10150
10151 ins_encode %{
10152 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10153 Register nof_bytes_arg = $cnt$$Register;
10154 Register nof_bytes_tmp = $temp$$Register;
10155 Register base_pointer_arg = $base$$Register;
10156
10157 Label loop;
10158 __ mov(nof_bytes_arg, nof_bytes_tmp);
10159
10160 // Loop and clear, walking backwards through the array.
10161 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10162 __ bind(loop);
10163 __ deccc(nof_bytes_tmp, 8);
10164 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10165 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10166 // %%%% this mini-loop must not cross a cache boundary!
10167 %}
10168 ins_pipe(long_memory_op);
10169 %}
10170
10171 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10172 predicate(use_block_zeroing(n->in(2)));
10173 match(Set dummy (ClearArray cnt base));
10174 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10175 ins_cost(300);
10176 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10177
10178 ins_encode %{
10179
10180 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10181 Register to = $base$$Register;
10182 Register count = $cnt$$Register;
10183
10184 Label Ldone;
10185 __ nop(); // Separate short branches
10186 // Use BIS for zeroing (temp is not used).
10187 __ bis_zeroing(to, count, G0, Ldone);
10188 __ bind(Ldone);
10189
10190 %}
10191 ins_pipe(long_memory_op);
10192 %}
10193
10194 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10195 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10196 match(Set dummy (ClearArray cnt base));
10197 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10198 ins_cost(300);
10199 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10200
10201 ins_encode %{
10202
10203 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10204 Register to = $base$$Register;
10205 Register count = $cnt$$Register;
10206 Register temp = $tmp$$Register;
10207
10208 Label Ldone;
10209 __ nop(); // Separate short branches
10210 // Use BIS for zeroing
10211 __ bis_zeroing(to, count, temp, Ldone);
10212 __ bind(Ldone);
10213
10214 %}
10215 ins_pipe(long_memory_op);
10216 %}
10217
10218 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10219 o7RegI tmp, flagsReg ccr) %{
10220 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10221 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10222 ins_cost(300);
10223 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10224 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10225 ins_pipe(long_memory_op);
10226 %}
10227
10228 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10229 o7RegI tmp, flagsReg ccr) %{
10230 match(Set result (StrEquals (Binary str1 str2) cnt));
10231 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10232 ins_cost(300);
10233 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10234 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10235 ins_pipe(long_memory_op);
10236 %}
10237
10238 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10239 o7RegI tmp2, flagsReg ccr) %{
10240 match(Set result (AryEq ary1 ary2));
10241 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10242 ins_cost(300);
10243 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10244 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10245 ins_pipe(long_memory_op);
10246 %}
10247
10248
10249 //---------- Zeros Count Instructions ------------------------------------------
10250
10251 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10252 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10253 match(Set dst (CountLeadingZerosI src));
10254 effect(TEMP dst, TEMP tmp, KILL cr);
10255
10256 // x |= (x >> 1);
10257 // x |= (x >> 2);
10258 // x |= (x >> 4);
10259 // x |= (x >> 8);
10260 // x |= (x >> 16);
10261 // return (WORDBITS - popc(x));
10262 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10263 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10264 "OR $dst,$tmp,$dst\n\t"
10265 "SRL $dst,2,$tmp\n\t"
10266 "OR $dst,$tmp,$dst\n\t"
10267 "SRL $dst,4,$tmp\n\t"
10268 "OR $dst,$tmp,$dst\n\t"
10269 "SRL $dst,8,$tmp\n\t"
10270 "OR $dst,$tmp,$dst\n\t"
10271 "SRL $dst,16,$tmp\n\t"
10272 "OR $dst,$tmp,$dst\n\t"
10273 "POPC $dst,$dst\n\t"
10274 "MOV 32,$tmp\n\t"
10275 "SUB $tmp,$dst,$dst" %}
10276 ins_encode %{
10277 Register Rdst = $dst$$Register;
10278 Register Rsrc = $src$$Register;
10279 Register Rtmp = $tmp$$Register;
10280 __ srl(Rsrc, 1, Rtmp);
10281 __ srl(Rsrc, 0, Rdst);
10282 __ or3(Rdst, Rtmp, Rdst);
10283 __ srl(Rdst, 2, Rtmp);
10284 __ or3(Rdst, Rtmp, Rdst);
10285 __ srl(Rdst, 4, Rtmp);
10286 __ or3(Rdst, Rtmp, Rdst);
10287 __ srl(Rdst, 8, Rtmp);
10288 __ or3(Rdst, Rtmp, Rdst);
10289 __ srl(Rdst, 16, Rtmp);
10290 __ or3(Rdst, Rtmp, Rdst);
10291 __ popc(Rdst, Rdst);
10292 __ mov(BitsPerInt, Rtmp);
10293 __ sub(Rtmp, Rdst, Rdst);
10294 %}
10295 ins_pipe(ialu_reg);
10296 %}
10297
10298 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10299 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10300 match(Set dst (CountLeadingZerosL src));
10301 effect(TEMP dst, TEMP tmp, KILL cr);
10302
10303 // x |= (x >> 1);
10304 // x |= (x >> 2);
10305 // x |= (x >> 4);
10306 // x |= (x >> 8);
10307 // x |= (x >> 16);
10308 // x |= (x >> 32);
10309 // return (WORDBITS - popc(x));
10310 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10311 "OR $src,$tmp,$dst\n\t"
10312 "SRLX $dst,2,$tmp\n\t"
10313 "OR $dst,$tmp,$dst\n\t"
10314 "SRLX $dst,4,$tmp\n\t"
10315 "OR $dst,$tmp,$dst\n\t"
10316 "SRLX $dst,8,$tmp\n\t"
10317 "OR $dst,$tmp,$dst\n\t"
10318 "SRLX $dst,16,$tmp\n\t"
10319 "OR $dst,$tmp,$dst\n\t"
10320 "SRLX $dst,32,$tmp\n\t"
10321 "OR $dst,$tmp,$dst\n\t"
10322 "POPC $dst,$dst\n\t"
10323 "MOV 64,$tmp\n\t"
10324 "SUB $tmp,$dst,$dst" %}
10325 ins_encode %{
10326 Register Rdst = $dst$$Register;
10327 Register Rsrc = $src$$Register;
10328 Register Rtmp = $tmp$$Register;
10329 __ srlx(Rsrc, 1, Rtmp);
10330 __ or3( Rsrc, Rtmp, Rdst);
10331 __ srlx(Rdst, 2, Rtmp);
10332 __ or3( Rdst, Rtmp, Rdst);
10333 __ srlx(Rdst, 4, Rtmp);
10334 __ or3( Rdst, Rtmp, Rdst);
10335 __ srlx(Rdst, 8, Rtmp);
10336 __ or3( Rdst, Rtmp, Rdst);
10337 __ srlx(Rdst, 16, Rtmp);
10338 __ or3( Rdst, Rtmp, Rdst);
10339 __ srlx(Rdst, 32, Rtmp);
10340 __ or3( Rdst, Rtmp, Rdst);
10341 __ popc(Rdst, Rdst);
10342 __ mov(BitsPerLong, Rtmp);
10343 __ sub(Rtmp, Rdst, Rdst);
10344 %}
10345 ins_pipe(ialu_reg);
10346 %}
10347
10348 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10349 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10350 match(Set dst (CountTrailingZerosI src));
10351 effect(TEMP dst, KILL cr);
10352
10353 // return popc(~x & (x - 1));
10354 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10355 "ANDN $dst,$src,$dst\n\t"
10356 "SRL $dst,R_G0,$dst\n\t"
10357 "POPC $dst,$dst" %}
10358 ins_encode %{
10359 Register Rdst = $dst$$Register;
10360 Register Rsrc = $src$$Register;
10361 __ sub(Rsrc, 1, Rdst);
10362 __ andn(Rdst, Rsrc, Rdst);
10363 __ srl(Rdst, G0, Rdst);
10364 __ popc(Rdst, Rdst);
10365 %}
10366 ins_pipe(ialu_reg);
10367 %}
10368
10369 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10370 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10371 match(Set dst (CountTrailingZerosL src));
10372 effect(TEMP dst, KILL cr);
10373
10374 // return popc(~x & (x - 1));
10375 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10376 "ANDN $dst,$src,$dst\n\t"
10377 "POPC $dst,$dst" %}
10378 ins_encode %{
10379 Register Rdst = $dst$$Register;
10380 Register Rsrc = $src$$Register;
10381 __ sub(Rsrc, 1, Rdst);
10382 __ andn(Rdst, Rsrc, Rdst);
10383 __ popc(Rdst, Rdst);
10384 %}
10385 ins_pipe(ialu_reg);
10386 %}
10387
10388
10389 //---------- Population Count Instructions -------------------------------------
10390
10391 instruct popCountI(iRegIsafe dst, iRegI src) %{
10392 predicate(UsePopCountInstruction);
10393 match(Set dst (PopCountI src));
10394
10395 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10396 "POPC $dst, $dst" %}
10397 ins_encode %{
10398 __ srl($src$$Register, G0, $dst$$Register);
10399 __ popc($dst$$Register, $dst$$Register);
10400 %}
10401 ins_pipe(ialu_reg);
10402 %}
10403
10404 // Note: Long.bitCount(long) returns an int.
10405 instruct popCountL(iRegIsafe dst, iRegL src) %{
10406 predicate(UsePopCountInstruction);
10407 match(Set dst (PopCountL src));
10408
10409 format %{ "POPC $src, $dst" %}
10410 ins_encode %{
10411 __ popc($src$$Register, $dst$$Register);
10412 %}
10413 ins_pipe(ialu_reg);
10414 %}
10415
10416
10417 // ============================================================================
10418 //------------Bytes reverse--------------------------------------------------
10419
10420 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10421 match(Set dst (ReverseBytesI src));
10422
10423 // Op cost is artificially doubled to make sure that load or store
10424 // instructions are preferred over this one which requires a spill
10425 // onto a stack slot.
10426 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10427 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10428
10429 ins_encode %{
10430 __ set($src$$disp + STACK_BIAS, O7);
10431 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10432 %}
10433 ins_pipe( iload_mem );
10434 %}
10435
10436 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10437 match(Set dst (ReverseBytesL src));
10438
10439 // Op cost is artificially doubled to make sure that load or store
10440 // instructions are preferred over this one which requires a spill
10441 // onto a stack slot.
10442 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10443 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10444
10445 ins_encode %{
10446 __ set($src$$disp + STACK_BIAS, O7);
10447 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10448 %}
10449 ins_pipe( iload_mem );
10450 %}
10451
10452 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10453 match(Set dst (ReverseBytesUS src));
10454
10455 // Op cost is artificially doubled to make sure that load or store
10456 // instructions are preferred over this one which requires a spill
10457 // onto a stack slot.
10458 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10459 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10460
10461 ins_encode %{
10462 // the value was spilled as an int so bias the load
10463 __ set($src$$disp + STACK_BIAS + 2, O7);
10464 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10465 %}
10466 ins_pipe( iload_mem );
10467 %}
10468
10469 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10470 match(Set dst (ReverseBytesS src));
10471
10472 // Op cost is artificially doubled to make sure that load or store
10473 // instructions are preferred over this one which requires a spill
10474 // onto a stack slot.
10475 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10476 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10477
10478 ins_encode %{
10479 // the value was spilled as an int so bias the load
10480 __ set($src$$disp + STACK_BIAS + 2, O7);
10481 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10482 %}
10483 ins_pipe( iload_mem );
10484 %}
10485
10486 // Load Integer reversed byte order
10487 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10488 match(Set dst (ReverseBytesI (LoadI src)));
10489
10490 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10491 size(4);
10492 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10493
10494 ins_encode %{
10495 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10496 %}
10497 ins_pipe(iload_mem);
10498 %}
10499
10500 // Load Long - aligned and reversed
10501 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10502 match(Set dst (ReverseBytesL (LoadL src)));
10503
10504 ins_cost(MEMORY_REF_COST);
10505 size(4);
10506 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10507
10508 ins_encode %{
10509 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10510 %}
10511 ins_pipe(iload_mem);
10512 %}
10513
10514 // Load unsigned short / char reversed byte order
10515 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10516 match(Set dst (ReverseBytesUS (LoadUS src)));
10517
10518 ins_cost(MEMORY_REF_COST);
10519 size(4);
10520 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10521
10522 ins_encode %{
10523 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10524 %}
10525 ins_pipe(iload_mem);
10526 %}
10527
10528 // Load short reversed byte order
10529 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10530 match(Set dst (ReverseBytesS (LoadS src)));
10531
10532 ins_cost(MEMORY_REF_COST);
10533 size(4);
10534 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10535
10536 ins_encode %{
10537 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10538 %}
10539 ins_pipe(iload_mem);
10540 %}
10541
10542 // Store Integer reversed byte order
10543 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10544 match(Set dst (StoreI dst (ReverseBytesI src)));
10545
10546 ins_cost(MEMORY_REF_COST);
10547 size(4);
10548 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10549
10550 ins_encode %{
10551 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10552 %}
10553 ins_pipe(istore_mem_reg);
10554 %}
10555
10556 // Store Long reversed byte order
10557 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10558 match(Set dst (StoreL dst (ReverseBytesL src)));
10559
10560 ins_cost(MEMORY_REF_COST);
10561 size(4);
10562 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10563
10564 ins_encode %{
10565 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10566 %}
10567 ins_pipe(istore_mem_reg);
10568 %}
10569
10570 // Store unsighed short/char reversed byte order
10571 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10572 match(Set dst (StoreC dst (ReverseBytesUS src)));
10573
10574 ins_cost(MEMORY_REF_COST);
10575 size(4);
10576 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10577
10578 ins_encode %{
10579 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10580 %}
10581 ins_pipe(istore_mem_reg);
10582 %}
10583
10584 // Store short reversed byte order
10585 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10586 match(Set dst (StoreC dst (ReverseBytesS src)));
10587
10588 ins_cost(MEMORY_REF_COST);
10589 size(4);
10590 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10591
10592 ins_encode %{
10593 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10594 %}
10595 ins_pipe(istore_mem_reg);
10596 %}
10597
10598 // ====================VECTOR INSTRUCTIONS=====================================
10599
10600 // Load Aligned Packed values into a Double Register
10601 instruct loadV8(regD dst, memory mem) %{
10602 predicate(n->as_LoadVector()->memory_size() == 8);
10603 match(Set dst (LoadVector mem));
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10607 ins_encode %{
10608 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10609 %}
10610 ins_pipe(floadD_mem);
10611 %}
10612
10613 // Store Vector in Double register to memory
10614 instruct storeV8(memory mem, regD src) %{
10615 predicate(n->as_StoreVector()->memory_size() == 8);
10616 match(Set mem (StoreVector mem src));
10617 ins_cost(MEMORY_REF_COST);
10618 size(4);
10619 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10620 ins_encode %{
10621 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10622 %}
10623 ins_pipe(fstoreD_mem_reg);
10624 %}
10625
10626 // Store Zero into vector in memory
10627 instruct storeV8B_zero(memory mem, immI0 zero) %{
10628 predicate(n->as_StoreVector()->memory_size() == 8);
10629 match(Set mem (StoreVector mem (ReplicateB zero)));
10630 ins_cost(MEMORY_REF_COST);
10631 size(4);
10632 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10633 ins_encode %{
10634 __ stx(G0, $mem$$Address);
10635 %}
10636 ins_pipe(fstoreD_mem_zero);
10637 %}
10638
10639 instruct storeV4S_zero(memory mem, immI0 zero) %{
10640 predicate(n->as_StoreVector()->memory_size() == 8);
10641 match(Set mem (StoreVector mem (ReplicateS zero)));
10642 ins_cost(MEMORY_REF_COST);
10643 size(4);
10644 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10645 ins_encode %{
10646 __ stx(G0, $mem$$Address);
10647 %}
10648 ins_pipe(fstoreD_mem_zero);
10649 %}
10650
10651 instruct storeV2I_zero(memory mem, immI0 zero) %{
10652 predicate(n->as_StoreVector()->memory_size() == 8);
10653 match(Set mem (StoreVector mem (ReplicateI zero)));
10654 ins_cost(MEMORY_REF_COST);
10655 size(4);
10656 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10657 ins_encode %{
10658 __ stx(G0, $mem$$Address);
10659 %}
10660 ins_pipe(fstoreD_mem_zero);
10661 %}
10662
10663 instruct storeV2F_zero(memory mem, immF0 zero) %{
10664 predicate(n->as_StoreVector()->memory_size() == 8);
10665 match(Set mem (StoreVector mem (ReplicateF zero)));
10666 ins_cost(MEMORY_REF_COST);
10667 size(4);
10668 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10669 ins_encode %{
10670 __ stx(G0, $mem$$Address);
10671 %}
10672 ins_pipe(fstoreD_mem_zero);
10673 %}
10674
10675 // Replicate scalar to packed byte values into Double register
10676 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10677 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10678 match(Set dst (ReplicateB src));
10679 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10680 format %{ "SLLX $src,56,$tmp\n\t"
10681 "SRLX $tmp, 8,$tmp2\n\t"
10682 "OR $tmp,$tmp2,$tmp\n\t"
10683 "SRLX $tmp,16,$tmp2\n\t"
10684 "OR $tmp,$tmp2,$tmp\n\t"
10685 "SRLX $tmp,32,$tmp2\n\t"
10686 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10687 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10688 ins_encode %{
10689 Register Rsrc = $src$$Register;
10690 Register Rtmp = $tmp$$Register;
10691 Register Rtmp2 = $tmp2$$Register;
10692 __ sllx(Rsrc, 56, Rtmp);
10693 __ srlx(Rtmp, 8, Rtmp2);
10694 __ or3 (Rtmp, Rtmp2, Rtmp);
10695 __ srlx(Rtmp, 16, Rtmp2);
10696 __ or3 (Rtmp, Rtmp2, Rtmp);
10697 __ srlx(Rtmp, 32, Rtmp2);
10698 __ or3 (Rtmp, Rtmp2, Rtmp);
10699 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10700 %}
10701 ins_pipe(ialu_reg);
10702 %}
10703
10704 // Replicate scalar to packed byte values into Double stack
10705 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10706 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10707 match(Set dst (ReplicateB src));
10708 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10709 format %{ "SLLX $src,56,$tmp\n\t"
10710 "SRLX $tmp, 8,$tmp2\n\t"
10711 "OR $tmp,$tmp2,$tmp\n\t"
10712 "SRLX $tmp,16,$tmp2\n\t"
10713 "OR $tmp,$tmp2,$tmp\n\t"
10714 "SRLX $tmp,32,$tmp2\n\t"
10715 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10716 "STX $tmp,$dst\t! regL to stkD" %}
10717 ins_encode %{
10718 Register Rsrc = $src$$Register;
10719 Register Rtmp = $tmp$$Register;
10720 Register Rtmp2 = $tmp2$$Register;
10721 __ sllx(Rsrc, 56, Rtmp);
10722 __ srlx(Rtmp, 8, Rtmp2);
10723 __ or3 (Rtmp, Rtmp2, Rtmp);
10724 __ srlx(Rtmp, 16, Rtmp2);
10725 __ or3 (Rtmp, Rtmp2, Rtmp);
10726 __ srlx(Rtmp, 32, Rtmp2);
10727 __ or3 (Rtmp, Rtmp2, Rtmp);
10728 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10729 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10730 %}
10731 ins_pipe(ialu_reg);
10732 %}
10733
10734 // Replicate scalar constant to packed byte values in Double register
10735 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10736 predicate(n->as_Vector()->length() == 8);
10737 match(Set dst (ReplicateB con));
10738 effect(KILL tmp);
10739 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10740 ins_encode %{
10741 // XXX This is a quick fix for 6833573.
10742 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10743 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10744 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10745 %}
10746 ins_pipe(loadConFD);
10747 %}
10748
10749 // Replicate scalar to packed char/short values into Double register
10750 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10751 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10752 match(Set dst (ReplicateS src));
10753 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10754 format %{ "SLLX $src,48,$tmp\n\t"
10755 "SRLX $tmp,16,$tmp2\n\t"
10756 "OR $tmp,$tmp2,$tmp\n\t"
10757 "SRLX $tmp,32,$tmp2\n\t"
10758 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10759 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10760 ins_encode %{
10761 Register Rsrc = $src$$Register;
10762 Register Rtmp = $tmp$$Register;
10763 Register Rtmp2 = $tmp2$$Register;
10764 __ sllx(Rsrc, 48, Rtmp);
10765 __ srlx(Rtmp, 16, Rtmp2);
10766 __ or3 (Rtmp, Rtmp2, Rtmp);
10767 __ srlx(Rtmp, 32, Rtmp2);
10768 __ or3 (Rtmp, Rtmp2, Rtmp);
10769 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10770 %}
10771 ins_pipe(ialu_reg);
10772 %}
10773
10774 // Replicate scalar to packed char/short values into Double stack
10775 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10776 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10777 match(Set dst (ReplicateS src));
10778 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10779 format %{ "SLLX $src,48,$tmp\n\t"
10780 "SRLX $tmp,16,$tmp2\n\t"
10781 "OR $tmp,$tmp2,$tmp\n\t"
10782 "SRLX $tmp,32,$tmp2\n\t"
10783 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10784 "STX $tmp,$dst\t! regL to stkD" %}
10785 ins_encode %{
10786 Register Rsrc = $src$$Register;
10787 Register Rtmp = $tmp$$Register;
10788 Register Rtmp2 = $tmp2$$Register;
10789 __ sllx(Rsrc, 48, Rtmp);
10790 __ srlx(Rtmp, 16, Rtmp2);
10791 __ or3 (Rtmp, Rtmp2, Rtmp);
10792 __ srlx(Rtmp, 32, Rtmp2);
10793 __ or3 (Rtmp, Rtmp2, Rtmp);
10794 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10795 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10796 %}
10797 ins_pipe(ialu_reg);
10798 %}
10799
10800 // Replicate scalar constant to packed char/short values in Double register
10801 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10802 predicate(n->as_Vector()->length() == 4);
10803 match(Set dst (ReplicateS con));
10804 effect(KILL tmp);
10805 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10806 ins_encode %{
10807 // XXX This is a quick fix for 6833573.
10808 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10809 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10810 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10811 %}
10812 ins_pipe(loadConFD);
10813 %}
10814
10815 // Replicate scalar to packed int values into Double register
10816 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10817 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10818 match(Set dst (ReplicateI src));
10819 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10820 format %{ "SLLX $src,32,$tmp\n\t"
10821 "SRLX $tmp,32,$tmp2\n\t"
10822 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10823 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10824 ins_encode %{
10825 Register Rsrc = $src$$Register;
10826 Register Rtmp = $tmp$$Register;
10827 Register Rtmp2 = $tmp2$$Register;
10828 __ sllx(Rsrc, 32, Rtmp);
10829 __ srlx(Rtmp, 32, Rtmp2);
10830 __ or3 (Rtmp, Rtmp2, Rtmp);
10831 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10832 %}
10833 ins_pipe(ialu_reg);
10834 %}
10835
10836 // Replicate scalar to packed int values into Double stack
10837 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10838 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10839 match(Set dst (ReplicateI src));
10840 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10841 format %{ "SLLX $src,32,$tmp\n\t"
10842 "SRLX $tmp,32,$tmp2\n\t"
10843 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10844 "STX $tmp,$dst\t! regL to stkD" %}
10845 ins_encode %{
10846 Register Rsrc = $src$$Register;
10847 Register Rtmp = $tmp$$Register;
10848 Register Rtmp2 = $tmp2$$Register;
10849 __ sllx(Rsrc, 32, Rtmp);
10850 __ srlx(Rtmp, 32, Rtmp2);
10851 __ or3 (Rtmp, Rtmp2, Rtmp);
10852 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10853 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10854 %}
10855 ins_pipe(ialu_reg);
10856 %}
10857
10858 // Replicate scalar zero constant to packed int values in Double register
10859 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10860 predicate(n->as_Vector()->length() == 2);
10861 match(Set dst (ReplicateI con));
10862 effect(KILL tmp);
10863 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10864 ins_encode %{
10865 // XXX This is a quick fix for 6833573.
10866 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10867 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10868 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10869 %}
10870 ins_pipe(loadConFD);
10871 %}
10872
10873 // Replicate scalar to packed float values into Double stack
10874 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10875 predicate(n->as_Vector()->length() == 2);
10876 match(Set dst (ReplicateF src));
10877 ins_cost(MEMORY_REF_COST*2);
10878 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10879 "STF $src,$dst.lo" %}
10880 opcode(Assembler::stf_op3);
10881 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10882 ins_pipe(fstoreF_stk_reg);
10883 %}
10884
10885 // Replicate scalar zero constant to packed float values in Double register
10886 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10887 predicate(n->as_Vector()->length() == 2);
10888 match(Set dst (ReplicateF con));
10889 effect(KILL tmp);
10890 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10891 ins_encode %{
10892 // XXX This is a quick fix for 6833573.
10893 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10894 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10895 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10896 %}
10897 ins_pipe(loadConFD);
10898 %}
10899
10900 //----------PEEPHOLE RULES-----------------------------------------------------
10901 // These must follow all instruction definitions as they use the names
10902 // defined in the instructions definitions.
10903 //
10904 // peepmatch ( root_instr_name [preceding_instruction]* );
10905 //
10906 // peepconstraint %{
10907 // (instruction_number.operand_name relational_op instruction_number.operand_name
10908 // [, ...] );
10909 // // instruction numbers are zero-based using left to right order in peepmatch
10910 //
10911 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10912 // // provide an instruction_number.operand_name for each operand that appears
10913 // // in the replacement instruction's match rule
10914 //
10915 // ---------VM FLAGS---------------------------------------------------------
10916 //
10917 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10918 //
10919 // Each peephole rule is given an identifying number starting with zero and
10920 // increasing by one in the order seen by the parser. An individual peephole
10921 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10922 // on the command-line.
10923 //
10924 // ---------CURRENT LIMITATIONS----------------------------------------------
10925 //
10926 // Only match adjacent instructions in same basic block
10927 // Only equality constraints
10928 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10929 // Only one replacement instruction
10930 //
10931 // ---------EXAMPLE----------------------------------------------------------
10932 //
10933 // // pertinent parts of existing instructions in architecture description
10934 // instruct movI(eRegI dst, eRegI src) %{
10935 // match(Set dst (CopyI src));
10936 // %}
10937 //
10938 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10939 // match(Set dst (AddI dst src));
10940 // effect(KILL cr);
10941 // %}
10942 //
10943 // // Change (inc mov) to lea
10944 // peephole %{
10945 // // increment preceeded by register-register move
10946 // peepmatch ( incI_eReg movI );
10947 // // require that the destination register of the increment
10948 // // match the destination register of the move
10949 // peepconstraint ( 0.dst == 1.dst );
10950 // // construct a replacement instruction that sets
10951 // // the destination to ( move's source register + one )
10952 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10953 // %}
10954 //
10955
10956 // // Change load of spilled value to only a spill
10957 // instruct storeI(memory mem, eRegI src) %{
10958 // match(Set mem (StoreI mem src));
10959 // %}
10960 //
10961 // instruct loadI(eRegI dst, memory mem) %{
10962 // match(Set dst (LoadI mem));
10963 // %}
10964 //
10965 // peephole %{
10966 // peepmatch ( loadI storeI );
10967 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10968 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10969 // %}
10970
10971 //----------SMARTSPILL RULES---------------------------------------------------
10972 // These must follow all instruction definitions as they use the names
10973 // defined in the instructions definitions.
10974 //
10975 // SPARC will probably not have any of these rules due to RISC instruction set.
10976
10977 //----------PIPELINE-----------------------------------------------------------
10978 // Rules which define the behavior of the target architectures pipeline.