3381 %}
3382
3383 // Integer Immediate: 11-bit
3384 operand immI11() %{
3385 predicate(Assembler::is_simm11(n->get_int()));
3386 match(ConI);
3387 op_cost(0);
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Integer Immediate: 5-bit
3393 operand immI5() %{
3394 predicate(Assembler::is_simm5(n->get_int()));
3395 match(ConI);
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Integer Immediate: 0-bit
3402 operand immI0() %{
3403 predicate(n->get_int() == 0);
3404 match(ConI);
3405 op_cost(0);
3406
3407 format %{ %}
3408 interface(CONST_INTER);
3409 %}
3410
3411 // Integer Immediate: the value 10
3412 operand immI10() %{
3413 predicate(n->get_int() == 10);
3414 match(ConI);
3415 op_cost(0);
3416
3417 format %{ %}
3418 interface(CONST_INTER);
3419 %}
3420
5830 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5831 ins_encode %{
5832 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5833 %}
5834 ins_pipe(iload_mem);
5835 %}
5836
5837 // Load Integer with mask 0xFFFF into a Long Register
5838 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5839 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5840 ins_cost(MEMORY_REF_COST);
5841
5842 size(4);
5843 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5844 ins_encode %{
5845 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5846 %}
5847 ins_pipe(iload_mem);
5848 %}
5849
5850 // Load Integer with a 13-bit mask into a Long Register
5851 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5852 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5853 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5854
5855 size(2*4);
5856 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5857 "AND $dst,$mask,$dst" %}
5858 ins_encode %{
5859 Register Rdst = $dst$$Register;
5860 __ lduw($mem$$Address, Rdst);
5861 __ and3(Rdst, $mask$$constant, Rdst);
5862 %}
5863 ins_pipe(iload_mem);
5864 %}
5865
5866 // Load Integer with a 32-bit mask into a Long Register
5867 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5868 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5869 effect(TEMP dst, TEMP tmp);
5870 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5871
5872 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5873 "SET $mask,$tmp\n\t"
5874 "AND $dst,$tmp,$dst" %}
5875 ins_encode %{
5876 Register Rdst = $dst$$Register;
5877 Register Rtmp = $tmp$$Register;
5878 __ lduw($mem$$Address, Rdst);
5879 __ set($mask$$constant, Rtmp);
5880 __ and3(Rdst, Rtmp, Rdst);
5881 %}
5882 ins_pipe(iload_mem);
5883 %}
5884
5885 // Load Unsigned Integer into a Long Register
5886 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5887 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5888 ins_cost(MEMORY_REF_COST);
5889
5890 size(4);
5891 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5892 ins_encode %{
|
3381 %}
3382
3383 // Integer Immediate: 11-bit
3384 operand immI11() %{
3385 predicate(Assembler::is_simm11(n->get_int()));
3386 match(ConI);
3387 op_cost(0);
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Integer Immediate: 5-bit
3393 operand immI5() %{
3394 predicate(Assembler::is_simm5(n->get_int()));
3395 match(ConI);
3396 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3400
3401 // Int Immediate positive
3402 operand immU32()
3403 %{
3404 predicate(n->get_int() >= 0);
3405 match(ConI);
3406
3407 op_cost(0);
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3411
3412 // Integer Immediate: 0-bit
3413 operand immI0() %{
3414 predicate(n->get_int() == 0);
3415 match(ConI);
3416 op_cost(0);
3417
3418 format %{ %}
3419 interface(CONST_INTER);
3420 %}
3421
3422 // Integer Immediate: the value 10
3423 operand immI10() %{
3424 predicate(n->get_int() == 10);
3425 match(ConI);
3426 op_cost(0);
3427
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3431
5841 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5842 ins_encode %{
5843 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5844 %}
5845 ins_pipe(iload_mem);
5846 %}
5847
5848 // Load Integer with mask 0xFFFF into a Long Register
5849 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5851 ins_cost(MEMORY_REF_COST);
5852
5853 size(4);
5854 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5855 ins_encode %{
5856 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5857 %}
5858 ins_pipe(iload_mem);
5859 %}
5860
5861 // Load Integer with a 12-bit mask into a Long Register
5862 instruct loadI2L_immU13(iRegL dst, memory mem, immU13 mask) %{
5863 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5864 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5865
5866 size(2*4);
5867 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5868 "AND $dst,$mask,$dst" %}
5869 ins_encode %{
5870 Register Rdst = $dst$$Register;
5871 __ lduw($mem$$Address, Rdst);
5872 __ and3(Rdst, $mask$$constant, Rdst);
5873 %}
5874 ins_pipe(iload_mem);
5875 %}
5876
5877 // Load Integer with a 31-bit mask into a Long Register
5878 instruct loadI2L_immU32(iRegL dst, memory mem, immU32 mask, iRegL tmp) %{
5879 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5880 effect(TEMP dst, TEMP tmp);
5881 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5882
5883 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5884 "SET $mask,$tmp\n\t"
5885 "AND $dst,$tmp,$dst" %}
5886 ins_encode %{
5887 Register Rdst = $dst$$Register;
5888 Register Rtmp = $tmp$$Register;
5889 __ lduw($mem$$Address, Rdst);
5890 __ set($mask$$constant, Rtmp);
5891 __ and3(Rdst, Rtmp, Rdst);
5892 %}
5893 ins_pipe(iload_mem);
5894 %}
5895
5896 // Load Unsigned Integer into a Long Register
5897 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5898 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5899 ins_cost(MEMORY_REF_COST);
5900
5901 size(4);
5902 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5903 ins_encode %{
|