1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
491 // Empty encoding
492 }
493
494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
495 return 0;
496 }
497
498 #ifndef PRODUCT
499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
500 st->print("# MachConstantBaseNode (empty encoding)");
501 }
502 #endif
503
504
505 //=============================================================================
506 #ifndef PRODUCT
507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
508 Compile* C = ra_->C;
509
510 int framesize = C->frame_slots() << LogBytesPerInt;
511 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
512 // Remove wordSize for return addr which is already pushed.
513 framesize -= wordSize;
514
515 if (C->need_stack_bang(framesize)) {
516 framesize -= wordSize;
517 st->print("# stack bang");
518 st->print("\n\t");
519 st->print("PUSH EBP\t# Save EBP");
520 if (framesize) {
521 st->print("\n\t");
522 st->print("SUB ESP, #%d\t# Create frame",framesize);
523 }
524 } else {
525 st->print("SUB ESP, #%d\t# Create frame",framesize);
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
529 }
530
531 if (VerifyStackAtCalls) {
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
535 }
536
537 if( C->in_24_bit_fp_mode() ) {
538 st->print("\n\t");
539 st->print("FLDCW \t# load 24 bit fpu control word");
540 }
541 if (UseSSE >= 2 && VerifyFPU) {
542 st->print("\n\t");
543 st->print("# verify FPU stack (must be clean on entry)");
544 }
545
546 #ifdef ASSERT
547 if (VerifyStackAtCalls) {
548 st->print("\n\t");
549 st->print("# stack alignment check");
550 }
551 #endif
552 st->cr();
553 }
554 #endif
555
556
557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
558 Compile* C = ra_->C;
559 MacroAssembler _masm(&cbuf);
560
561 int framesize = C->frame_slots() << LogBytesPerInt;
562
563 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
564
565 C->set_frame_complete(cbuf.insts_size());
566
567 if (C->has_mach_constant_base_node()) {
568 // NOTE: We set the table base offset here because users might be
569 // emitted before MachConstantBaseNode.
570 Compile::ConstantTable& constant_table = C->constant_table();
571 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
572 }
573 }
574
575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
576 return MachNode::size(ra_); // too many variables; just compute it the hard way
577 }
578
579 int MachPrologNode::reloc() const {
580 return 0; // a large enough number
581 }
582
583 //=============================================================================
584 #ifndef PRODUCT
585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
586 Compile *C = ra_->C;
587 int framesize = C->frame_slots() << LogBytesPerInt;
588 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
589 // Remove two words for return addr and rbp,
590 framesize -= 2*wordSize;
591
592 if (C->max_vector_size() > 16) {
593 st->print("VZEROUPPER");
594 st->cr(); st->print("\t");
595 }
596 if (C->in_24_bit_fp_mode()) {
597 st->print("FLDCW standard control word");
598 st->cr(); st->print("\t");
599 }
600 if (framesize) {
601 st->print("ADD ESP,%d\t# Destroy frame",framesize);
602 st->cr(); st->print("\t");
603 }
604 st->print_cr("POPL EBP"); st->print("\t");
605 if (do_polling() && C->is_method_compilation()) {
606 st->print("TEST PollPage,EAX\t! Poll Safepoint");
607 st->cr(); st->print("\t");
608 }
609 }
610 #endif
611
612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
613 Compile *C = ra_->C;
614
615 if (C->max_vector_size() > 16) {
616 // Clear upper bits of YMM registers when current compiled code uses
617 // wide vectors to avoid AVX <-> SSE transition penalty during call.
618 MacroAssembler masm(&cbuf);
619 masm.vzeroupper();
620 }
621 // If method set FPU control word, restore to standard control word
622 if (C->in_24_bit_fp_mode()) {
623 MacroAssembler masm(&cbuf);
624 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
625 }
626
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
631
632 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
633
634 if (framesize >= 128) {
635 emit_opcode(cbuf, 0x81); // add SP, #framesize
636 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
637 emit_d32(cbuf, framesize);
638 } else if (framesize) {
639 emit_opcode(cbuf, 0x83); // add SP, #framesize
640 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
641 emit_d8(cbuf, framesize);
642 }
643
644 emit_opcode(cbuf, 0x58 | EBP_enc);
645
646 if (do_polling() && C->is_method_compilation()) {
647 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
648 emit_opcode(cbuf,0x85);
649 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
650 emit_d32(cbuf, (intptr_t)os::get_polling_page());
651 }
652 }
653
654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
655 Compile *C = ra_->C;
656 // If method set FPU control word, restore to standard control word
657 int size = C->in_24_bit_fp_mode() ? 6 : 0;
658 if (C->max_vector_size() > 16) size += 3; // vzeroupper
659 if (do_polling() && C->is_method_compilation()) size += 6;
660
661 int framesize = C->frame_slots() << LogBytesPerInt;
662 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
663 // Remove two words for return addr and rbp,
664 framesize -= 2*wordSize;
665
666 size++; // popl rbp,
667
668 if (framesize >= 128) {
669 size += 6;
670 } else {
671 size += framesize ? 3 : 0;
672 }
673 return size;
674 }
675
676 int MachEpilogNode::reloc() const {
677 return 0; // a large enough number
678 }
679
680 const Pipeline * MachEpilogNode::pipeline() const {
681 return MachNode::pipeline_class();
682 }
683
684 int MachEpilogNode::safepoint_offset() const { return 0; }
685
686 //=============================================================================
687
688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
689 static enum RC rc_class( OptoReg::Name reg ) {
690
691 if( !OptoReg::is_valid(reg) ) return rc_bad;
692 if (OptoReg::is_stack(reg)) return rc_stack;
693
694 VMReg r = OptoReg::as_VMReg(reg);
695 if (r->is_Register()) return rc_int;
696 if (r->is_FloatRegister()) {
697 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
698 return rc_float;
699 }
700 assert(r->is_XMMRegister(), "must be");
701 return rc_xmm;
702 }
703
704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
705 int opcode, const char *op_str, int size, outputStream* st ) {
706 if( cbuf ) {
707 emit_opcode (*cbuf, opcode );
708 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
709 #ifndef PRODUCT
710 } else if( !do_size ) {
711 if( size != 0 ) st->print("\n\t");
712 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
713 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
714 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
715 } else { // FLD, FST, PUSH, POP
716 st->print("%s [ESP + #%d]",op_str,offset);
717 }
718 #endif
719 }
720 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
721 return size+3+offset_size;
722 }
723
724 // Helper for XMM registers. Extra opcode bits, limited syntax.
725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
726 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
727 if (cbuf) {
728 MacroAssembler _masm(cbuf);
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) {
731 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
732 } else {
733 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
734 }
735 } else {
736 if (is_load) {
737 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
738 } else {
739 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
740 }
741 }
742 #ifndef PRODUCT
743 } else if (!do_size) {
744 if (size != 0) st->print("\n\t");
745 if (reg_lo+1 == reg_hi) { // double move?
746 if (is_load) st->print("%s %s,[ESP + #%d]",
747 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
748 Matcher::regName[reg_lo], offset);
749 else st->print("MOVSD [ESP + #%d],%s",
750 offset, Matcher::regName[reg_lo]);
751 } else {
752 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSS [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 }
757 #endif
758 }
759 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
760 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
761 return size+5+offset_size;
762 }
763
764
765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
766 int src_hi, int dst_hi, int size, outputStream* st ) {
767 if (cbuf) {
768 MacroAssembler _masm(cbuf);
769 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
770 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
771 as_XMMRegister(Matcher::_regEncode[src_lo]));
772 } else {
773 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
774 as_XMMRegister(Matcher::_regEncode[src_lo]));
775 }
776 #ifndef PRODUCT
777 } else if (!do_size) {
778 if (size != 0) st->print("\n\t");
779 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
780 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
781 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
782 } else {
783 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
784 }
785 } else {
786 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
787 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
788 } else {
789 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
790 }
791 }
792 #endif
793 }
794 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
795 // Only MOVAPS SSE prefix uses 1 byte.
796 int sz = 4;
797 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
798 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
799 return size + sz;
800 }
801
802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
808 as_Register(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817
818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
819 int src_hi, int dst_hi, int size, outputStream* st ) {
820 // 32-bit
821 if (cbuf) {
822 MacroAssembler _masm(cbuf);
823 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
824 as_XMMRegister(Matcher::_regEncode[src_lo]));
825 #ifndef PRODUCT
826 } else if (!do_size) {
827 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
828 #endif
829 }
830 return 4;
831 }
832
833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
834 if( cbuf ) {
835 emit_opcode(*cbuf, 0x8B );
836 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
837 #ifndef PRODUCT
838 } else if( !do_size ) {
839 if( size != 0 ) st->print("\n\t");
840 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
841 #endif
842 }
843 return size+2;
844 }
845
846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
847 int offset, int size, outputStream* st ) {
848 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
849 if( cbuf ) {
850 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
851 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
852 #ifndef PRODUCT
853 } else if( !do_size ) {
854 if( size != 0 ) st->print("\n\t");
855 st->print("FLD %s",Matcher::regName[src_lo]);
856 #endif
857 }
858 size += 2;
859 }
860
861 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
862 const char *op_str;
863 int op;
864 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
865 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
866 op = 0xDD;
867 } else { // 32-bit store
868 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
869 op = 0xD9;
870 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
871 }
872
873 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
874 }
875
876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
878 int src_hi, int dst_hi, uint ireg, outputStream* st);
879
880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
881 int stack_offset, int reg, uint ireg, outputStream* st);
882
883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
884 int dst_offset, uint ireg, outputStream* st) {
885 int calc_size = 0;
886 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
887 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
888 switch (ireg) {
889 case Op_VecS:
890 calc_size = 3+src_offset_size + 3+dst_offset_size;
891 break;
892 case Op_VecD:
893 calc_size = 3+src_offset_size + 3+dst_offset_size;
894 src_offset += 4;
895 dst_offset += 4;
896 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
897 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
898 calc_size += 3+src_offset_size + 3+dst_offset_size;
899 break;
900 case Op_VecX:
901 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
902 break;
903 case Op_VecY:
904 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
905 break;
906 default:
907 ShouldNotReachHere();
908 }
909 if (cbuf) {
910 MacroAssembler _masm(cbuf);
911 int offset = __ offset();
912 switch (ireg) {
913 case Op_VecS:
914 __ pushl(Address(rsp, src_offset));
915 __ popl (Address(rsp, dst_offset));
916 break;
917 case Op_VecD:
918 __ pushl(Address(rsp, src_offset));
919 __ popl (Address(rsp, dst_offset));
920 __ pushl(Address(rsp, src_offset+4));
921 __ popl (Address(rsp, dst_offset+4));
922 break;
923 case Op_VecX:
924 __ movdqu(Address(rsp, -16), xmm0);
925 __ movdqu(xmm0, Address(rsp, src_offset));
926 __ movdqu(Address(rsp, dst_offset), xmm0);
927 __ movdqu(xmm0, Address(rsp, -16));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 int size = __ offset() - offset;
939 assert(size == calc_size, "incorrect size calculattion");
940 return size;
941 #ifndef PRODUCT
942 } else if (!do_size) {
943 switch (ireg) {
944 case Op_VecS:
945 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
946 "popl [rsp + #%d]",
947 src_offset, dst_offset);
948 break;
949 case Op_VecD:
950 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
951 "popq [rsp + #%d]\n\t"
952 "pushl [rsp + #%d]\n\t"
953 "popq [rsp + #%d]",
954 src_offset, dst_offset, src_offset+4, dst_offset+4);
955 break;
956 case Op_VecX:
957 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
958 "movdqu xmm0, [rsp + #%d]\n\t"
959 "movdqu [rsp + #%d], xmm0\n\t"
960 "movdqu xmm0, [rsp - #16]",
961 src_offset, dst_offset);
962 break;
963 case Op_VecY:
964 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
965 "vmovdqu xmm0, [rsp + #%d]\n\t"
966 "vmovdqu [rsp + #%d], xmm0\n\t"
967 "vmovdqu xmm0, [rsp - #32]",
968 src_offset, dst_offset);
969 break;
970 default:
971 ShouldNotReachHere();
972 }
973 #endif
974 }
975 return calc_size;
976 }
977
978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this );
983 OptoReg::Name dst_first = ra_->get_reg_first(this );
984
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
989
990 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
991
992 // Generate spill code!
993 int size = 0;
994
995 if( src_first == dst_first && src_second == dst_second )
996 return size; // Self copy, no move
997
998 if (bottom_type()->isa_vect() != NULL) {
999 uint ireg = ideal_reg();
1000 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004 // mem -> mem
1005 int src_offset = ra_->reg2offset(src_first);
1006 int dst_offset = ra_->reg2offset(dst_first);
1007 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011 int stack_offset = ra_->reg2offset(dst_first);
1012 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014 int stack_offset = ra_->reg2offset(src_first);
1015 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1016 } else {
1017 ShouldNotReachHere();
1018 }
1019 }
1020
1021 // --------------------------------------
1022 // Check for mem-mem move. push/pop to move.
1023 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024 if( src_second == dst_first ) { // overlapping stack copy ranges
1025 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1027 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1028 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1029 }
1030 // move low bits
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1033 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1035 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1036 }
1037 return size;
1038 }
1039
1040 // --------------------------------------
1041 // Check for integer reg-reg copy
1042 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1044
1045 // Check for integer store
1046 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1048
1049 // Check for integer load
1050 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1052
1053 // Check for integer reg-xmm reg copy
1054 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056 "no 64 bit integer-float reg moves" );
1057 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058 }
1059 // --------------------------------------
1060 // Check for float reg-reg copy
1061 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064 if( cbuf ) {
1065
1066 // Note the mucking with the register encode to compensate for the 0/1
1067 // indexing issue mentioned in a comment in the reg_def sections
1068 // for FPR registers many lines above here.
1069
1070 if( src_first != FPR1L_num ) {
1071 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1072 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075 } else {
1076 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1077 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078 }
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083 else st->print( "FST %s", Matcher::regName[dst_first]);
1084 #endif
1085 }
1086 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087 }
1088
1089 // Check for float store
1090 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092 }
1093
1094 // Check for float load
1095 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096 int offset = ra_->reg2offset(src_first);
1097 const char *op_str;
1098 int op;
1099 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100 op_str = "FLD_D";
1101 op = 0xDD;
1102 } else { // 32-bit load
1103 op_str = "FLD_S";
1104 op = 0xD9;
1105 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106 }
1107 if( cbuf ) {
1108 emit_opcode (*cbuf, op );
1109 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1111 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113 } else if( !do_size ) {
1114 if( size != 0 ) st->print("\n\t");
1115 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117 }
1118 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119 return size + 3+offset_size+2;
1120 }
1121
1122 // Check for xmm reg-reg copy
1123 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125 (src_first+1 == src_second && dst_first+1 == dst_second),
1126 "no non-adjacent float-moves" );
1127 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128 }
1129
1130 // Check for xmm reg-integer reg copy
1131 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133 "no 64 bit float-integer reg moves" );
1134 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1136
1137 // Check for xmm store
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140 }
1141
1142 // Check for float xmm load
1143 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145 }
1146
1147 // Copy from float reg to xmm reg
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149 // copy to the top of stack from floating point reg
1150 // and use LEA to preserve flags
1151 if( cbuf ) {
1152 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1153 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155 emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157 } else if( !do_size ) {
1158 if( size != 0 ) st->print("\n\t");
1159 st->print("LEA ESP,[ESP-8]");
1160 #endif
1161 }
1162 size += 4;
1163
1164 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1165
1166 // Copy from the temp memory to the xmm reg.
1167 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1168
1169 if( cbuf ) {
1170 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1171 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173 emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175 } else if( !do_size ) {
1176 if( size != 0 ) st->print("\n\t");
1177 st->print("LEA ESP,[ESP+8]");
1178 #endif
1179 }
1180 size += 4;
1181 return size;
1182 }
1183
1184 assert( size > 0, "missed a case" );
1185
1186 // --------------------------------------------------------------------
1187 // Check for second bits still needing moving.
1188 if( src_second == dst_second )
1189 return size; // Self copy; no move
1190 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1191
1192 // Check for second word int-int move
1193 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1195
1196 // Check for second word integer store
1197 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1199
1200 // Check for second word integer load
1201 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1203
1204
1205 Unimplemented();
1206 }
1207
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210 implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1213
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215 implementation( &cbuf, ra_, false, NULL );
1216 }
1217
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219 return implementation( NULL, ra_, true, NULL );
1220 }
1221
1222
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227 int reg = ra_->get_reg_first(this);
1228 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1231
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234 int reg = ra_->get_encode(this);
1235 if( offset >= 128 ) {
1236 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1237 emit_rm(cbuf, 0x2, reg, 0x04);
1238 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239 emit_d32(cbuf, offset);
1240 }
1241 else {
1242 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1243 emit_rm(cbuf, 0x1, reg, 0x04);
1244 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245 emit_d8(cbuf, offset);
1246 }
1247 }
1248
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251 if( offset >= 128 ) {
1252 return 7;
1253 }
1254 else {
1255 return 4;
1256 }
1257 }
1258
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1263 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1264 st->print_cr("\tNOP");
1265 st->print_cr("\tNOP");
1266 if( !OptoBreakpoint )
1267 st->print_cr("\tNOP");
1268 }
1269 #endif
1270
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272 MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274 uint insts_size = cbuf.insts_size();
1275 #endif
1276 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277 masm.jump_cc(Assembler::notEqual,
1278 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279 /* WARNING these NOPs are critical so that verified entry point is properly
1280 aligned for patching by NativeJump::patch_verified_entry() */
1281 int nops_cnt = 2;
1282 if( !OptoBreakpoint ) // Leave space for int3
1283 nops_cnt += 1;
1284 masm.nop(nops_cnt);
1285
1286 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1288
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290 return OptoBreakpoint ? 11 : 12;
1291 }
1292
1293
1294 //=============================================================================
1295 uint size_exception_handler() {
1296 // NativeCall instruction size is the same as NativeJump.
1297 // exception handler starts out as jump and can be patched to
1298 // a call be deoptimization. (4932387)
1299 // Note that this value is also credited (in output.cpp) to
1300 // the size of the code section.
1301 return NativeJump::instruction_size;
1302 }
1303
1304 // Emit exception handler code. Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1307
1308 // Note that the code buffer's insts_mark is always relative to insts.
1309 // That's why we must use the macroassembler to generate a handler.
1310 MacroAssembler _masm(&cbuf);
1311 address base =
1312 __ start_a_stub(size_exception_handler());
1313 if (base == NULL) return 0; // CodeBuffer::expand failed
1314 int offset = __ offset();
1315 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317 __ end_a_stub();
1318 return offset;
1319 }
1320
1321 uint size_deopt_handler() {
1322 // NativeCall instruction size is the same as NativeJump.
1323 // exception handler starts out as jump and can be patched to
1324 // a call be deoptimization. (4932387)
1325 // Note that this value is also credited (in output.cpp) to
1326 // the size of the code section.
1327 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1329
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1332
1333 // Note that the code buffer's insts_mark is always relative to insts.
1334 // That's why we must use the macroassembler to generate a handler.
1335 MacroAssembler _masm(&cbuf);
1336 address base =
1337 __ start_a_stub(size_exception_handler());
1338 if (base == NULL) return 0; // CodeBuffer::expand failed
1339 int offset = __ offset();
1340 InternalAddress here(__ pc());
1341 __ pushptr(here.addr());
1342
1343 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345 __ end_a_stub();
1346 return offset;
1347 }
1348
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1352
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1357
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 // this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363 // The passed offset is relative to address of the branch.
1364 // On 86 a branch displacement is calculated relative to address
1365 // of a next instruction.
1366 offset -= br_size;
1367
1368 // the short version of jmpConUCF2 contains multiple branches,
1369 // making the reach slightly less
1370 if (rule == jmpConUCF2_rule)
1371 return (-126 <= offset && offset <= 125);
1372 return (-128 <= offset && offset <= 127);
1373 }
1374
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377 return false;
1378 }
1379
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1382
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1385
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1388
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers? True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1396
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1400
1401 bool Matcher::narrow_oop_use_complex_address() {
1402 ShouldNotCallThis();
1403 return true;
1404 }
1405
1406 bool Matcher::narrow_klass_use_complex_address() {
1407 ShouldNotCallThis();
1408 return true;
1409 }
1410
1411
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers. Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1417
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed. Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece. Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1423
1424
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426 // Get the memory operand from the node
1427 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1428 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1429 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430 uint opcnt = 1; // First operand
1431 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432 while( idx >= skipped+num_edges ) {
1433 skipped += num_edges;
1434 opcnt++; // Bump operand count
1435 assert( opcnt < numopnds, "Accessing non-existent operand" );
1436 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437 }
1438
1439 MachOper *memory = node->_opnds[opcnt];
1440 MachOper *new_memory = NULL;
1441 switch (memory->opcode()) {
1442 case DIRECT:
1443 case INDOFFSET32X:
1444 // No transformation necessary.
1445 return;
1446 case INDIRECT:
1447 new_memory = new (C) indirect_win95_safeOper( );
1448 break;
1449 case INDOFFSET8:
1450 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451 break;
1452 case INDOFFSET32:
1453 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454 break;
1455 case INDINDEXOFFSET:
1456 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457 break;
1458 case INDINDEXSCALE:
1459 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460 break;
1461 case INDINDEXSCALEOFFSET:
1462 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463 break;
1464 case LOAD_LONG_INDIRECT:
1465 case LOAD_LONG_INDOFFSET32:
1466 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467 return;
1468 default:
1469 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470 return;
1471 }
1472 node->_opnds[opcnt] = new_memory;
1473 }
1474
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1478
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1482
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1485
1486 // Return whether or not this register is ever used as an argument. This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491 if( reg == ECX_num || reg == EDX_num ) return true;
1492 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494 return false;
1495 }
1496
1497 bool Matcher::is_spillable_arg( int reg ) {
1498 return can_be_java_arg(reg);
1499 }
1500
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502 // Use hardware integer DIV instruction when
1503 // it is faster than a code which use multiply.
1504 // Only when constant divisor fits into 32 bit
1505 // (min_jint is excluded to get only correct
1506 // positive 32 bit values from negative).
1507 return VM_Version::has_fast_idiv() &&
1508 (divisor == (int)divisor && divisor != min_jint);
1509 }
1510
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513 return EAX_REG_mask();
1514 }
1515
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518 return EDX_REG_mask();
1519 }
1520
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1526
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1532
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1536
1537 const RegMask Matcher::mathExactI_result_proj_mask() {
1538 return EAX_REG_mask();
1539 }
1540
1541 const RegMask Matcher::mathExactL_result_proj_mask() {
1542 ShouldNotReachHere();
1543 return RegMask();
1544 }
1545
1546 const RegMask Matcher::mathExactI_flags_proj_mask() {
1547 return INT_FLAGS_mask();
1548 }
1549
1550 // Returns true if the high 32 bits of the value is known to be zero.
1551 bool is_operand_hi32_zero(Node* n) {
1552 int opc = n->Opcode();
1553 if (opc == Op_AndL) {
1554 Node* o2 = n->in(2);
1555 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1556 return true;
1557 }
1558 }
1559 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1560 return true;
1561 }
1562 return false;
1563 }
1564
1565 %}
1566
1567 //----------ENCODING BLOCK-----------------------------------------------------
1568 // This block specifies the encoding classes used by the compiler to output
1569 // byte streams. Encoding classes generate functions which are called by
1570 // Machine Instruction Nodes in order to generate the bit encoding of the
1571 // instruction. Operands specify their base encoding interface with the
1572 // interface keyword. There are currently supported four interfaces,
1573 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1574 // operand to generate a function which returns its register number when
1575 // queried. CONST_INTER causes an operand to generate a function which
1576 // returns the value of the constant when queried. MEMORY_INTER causes an
1577 // operand to generate four functions which return the Base Register, the
1578 // Index Register, the Scale Value, and the Offset Value of the operand when
1579 // queried. COND_INTER causes an operand to generate six functions which
1580 // return the encoding code (ie - encoding bits for the instruction)
1581 // associated with each basic boolean condition for a conditional instruction.
1582 // Instructions specify two basic values for encoding. They use the
1583 // ins_encode keyword to specify their encoding class (which must be one of
1584 // the class names specified in the encoding block), and they use the
1585 // opcode keyword to specify, in order, their primary, secondary, and
1586 // tertiary opcode. Only the opcode sections which a particular instruction
1587 // needs for encoding need to be specified.
1588 encode %{
1589 // Build emit functions for each basic byte or larger field in the intel
1590 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1591 // code in the enc_class source block. Emit functions will live in the
1592 // main source block for now. In future, we can generalize this by
1593 // adding a syntax that specifies the sizes of fields in an order,
1594 // so that the adlc can build the emit functions automagically
1595
1596 // Emit primary opcode
1597 enc_class OpcP %{
1598 emit_opcode(cbuf, $primary);
1599 %}
1600
1601 // Emit secondary opcode
1602 enc_class OpcS %{
1603 emit_opcode(cbuf, $secondary);
1604 %}
1605
1606 // Emit opcode directly
1607 enc_class Opcode(immI d8) %{
1608 emit_opcode(cbuf, $d8$$constant);
1609 %}
1610
1611 enc_class SizePrefix %{
1612 emit_opcode(cbuf,0x66);
1613 %}
1614
1615 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1617 %}
1618
1619 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1620 emit_opcode(cbuf,$opcode$$constant);
1621 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1622 %}
1623
1624 enc_class mov_r32_imm0( rRegI dst ) %{
1625 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1626 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1627 %}
1628
1629 enc_class cdq_enc %{
1630 // Full implementation of Java idiv and irem; checks for
1631 // special case as described in JVM spec., p.243 & p.271.
1632 //
1633 // normal case special case
1634 //
1635 // input : rax,: dividend min_int
1636 // reg: divisor -1
1637 //
1638 // output: rax,: quotient (= rax, idiv reg) min_int
1639 // rdx: remainder (= rax, irem reg) 0
1640 //
1641 // Code sequnce:
1642 //
1643 // 81 F8 00 00 00 80 cmp rax,80000000h
1644 // 0F 85 0B 00 00 00 jne normal_case
1645 // 33 D2 xor rdx,edx
1646 // 83 F9 FF cmp rcx,0FFh
1647 // 0F 84 03 00 00 00 je done
1648 // normal_case:
1649 // 99 cdq
1650 // F7 F9 idiv rax,ecx
1651 // done:
1652 //
1653 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1654 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1655 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1657 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1659 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1660 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1661 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1662 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1664 // normal_case:
1665 emit_opcode(cbuf,0x99); // cdq
1666 // idiv (note: must be emitted by the user of this rule)
1667 // normal:
1668 %}
1669
1670 // Dense encoding for older common ops
1671 enc_class Opc_plus(immI opcode, rRegI reg) %{
1672 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1673 %}
1674
1675
1676 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1677 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1678 // Check for 8-bit immediate, and set sign extend bit in opcode
1679 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1680 emit_opcode(cbuf, $primary | 0x02);
1681 }
1682 else { // If 32-bit immediate
1683 emit_opcode(cbuf, $primary);
1684 }
1685 %}
1686
1687 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1688 // Emit primary opcode and set sign-extend bit
1689 // Check for 8-bit immediate, and set sign extend bit in opcode
1690 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1691 emit_opcode(cbuf, $primary | 0x02); }
1692 else { // If 32-bit immediate
1693 emit_opcode(cbuf, $primary);
1694 }
1695 // Emit r/m byte with secondary opcode, after primary opcode.
1696 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1697 %}
1698
1699 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1700 // Check for 8-bit immediate, and set sign extend bit in opcode
1701 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1702 $$$emit8$imm$$constant;
1703 }
1704 else { // If 32-bit immediate
1705 // Output immediate
1706 $$$emit32$imm$$constant;
1707 }
1708 %}
1709
1710 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1711 // Emit primary opcode and set sign-extend bit
1712 // Check for 8-bit immediate, and set sign extend bit in opcode
1713 int con = (int)$imm$$constant; // Throw away top bits
1714 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1715 // Emit r/m byte with secondary opcode, after primary opcode.
1716 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1717 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1718 else emit_d32(cbuf,con);
1719 %}
1720
1721 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1722 // Emit primary opcode and set sign-extend bit
1723 // Check for 8-bit immediate, and set sign extend bit in opcode
1724 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1725 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1726 // Emit r/m byte with tertiary opcode, after primary opcode.
1727 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1728 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1729 else emit_d32(cbuf,con);
1730 %}
1731
1732 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1733 emit_cc(cbuf, $secondary, $dst$$reg );
1734 %}
1735
1736 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1737 int destlo = $dst$$reg;
1738 int desthi = HIGH_FROM_LOW(destlo);
1739 // bswap lo
1740 emit_opcode(cbuf, 0x0F);
1741 emit_cc(cbuf, 0xC8, destlo);
1742 // bswap hi
1743 emit_opcode(cbuf, 0x0F);
1744 emit_cc(cbuf, 0xC8, desthi);
1745 // xchg lo and hi
1746 emit_opcode(cbuf, 0x87);
1747 emit_rm(cbuf, 0x3, destlo, desthi);
1748 %}
1749
1750 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1751 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1752 %}
1753
1754 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1755 $$$emit8$primary;
1756 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1757 %}
1758
1759 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1760 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1761 emit_d8(cbuf, op >> 8 );
1762 emit_d8(cbuf, op & 255);
1763 %}
1764
1765 // emulate a CMOV with a conditional branch around a MOV
1766 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1767 // Invert sense of branch from sense of CMOV
1768 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1769 emit_d8( cbuf, $brOffs$$constant );
1770 %}
1771
1772 enc_class enc_PartialSubtypeCheck( ) %{
1773 Register Redi = as_Register(EDI_enc); // result register
1774 Register Reax = as_Register(EAX_enc); // super class
1775 Register Recx = as_Register(ECX_enc); // killed
1776 Register Resi = as_Register(ESI_enc); // sub class
1777 Label miss;
1778
1779 MacroAssembler _masm(&cbuf);
1780 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1781 NULL, &miss,
1782 /*set_cond_codes:*/ true);
1783 if ($primary) {
1784 __ xorptr(Redi, Redi);
1785 }
1786 __ bind(miss);
1787 %}
1788
1789 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1790 MacroAssembler masm(&cbuf);
1791 int start = masm.offset();
1792 if (UseSSE >= 2) {
1793 if (VerifyFPU) {
1794 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1795 }
1796 } else {
1797 // External c_calling_convention expects the FPU stack to be 'clean'.
1798 // Compiled code leaves it dirty. Do cleanup now.
1799 masm.empty_FPU_stack();
1800 }
1801 if (sizeof_FFree_Float_Stack_All == -1) {
1802 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1803 } else {
1804 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1805 }
1806 %}
1807
1808 enc_class Verify_FPU_For_Leaf %{
1809 if( VerifyFPU ) {
1810 MacroAssembler masm(&cbuf);
1811 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1812 }
1813 %}
1814
1815 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1816 // This is the instruction starting address for relocation info.
1817 cbuf.set_insts_mark();
1818 $$$emit8$primary;
1819 // CALL directly to the runtime
1820 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1821 runtime_call_Relocation::spec(), RELOC_IMM32 );
1822
1823 if (UseSSE >= 2) {
1824 MacroAssembler _masm(&cbuf);
1825 BasicType rt = tf()->return_type();
1826
1827 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1828 // A C runtime call where the return value is unused. In SSE2+
1829 // mode the result needs to be removed from the FPU stack. It's
1830 // likely that this function call could be removed by the
1831 // optimizer if the C function is a pure function.
1832 __ ffree(0);
1833 } else if (rt == T_FLOAT) {
1834 __ lea(rsp, Address(rsp, -4));
1835 __ fstp_s(Address(rsp, 0));
1836 __ movflt(xmm0, Address(rsp, 0));
1837 __ lea(rsp, Address(rsp, 4));
1838 } else if (rt == T_DOUBLE) {
1839 __ lea(rsp, Address(rsp, -8));
1840 __ fstp_d(Address(rsp, 0));
1841 __ movdbl(xmm0, Address(rsp, 0));
1842 __ lea(rsp, Address(rsp, 8));
1843 }
1844 }
1845 %}
1846
1847
1848 enc_class pre_call_resets %{
1849 // If method sets FPU control word restore it here
1850 debug_only(int off0 = cbuf.insts_size());
1851 if (ra_->C->in_24_bit_fp_mode()) {
1852 MacroAssembler _masm(&cbuf);
1853 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1854 }
1855 if (ra_->C->max_vector_size() > 16) {
1856 // Clear upper bits of YMM registers when current compiled code uses
1857 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1858 MacroAssembler _masm(&cbuf);
1859 __ vzeroupper();
1860 }
1861 debug_only(int off1 = cbuf.insts_size());
1862 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1863 %}
1864
1865 enc_class post_call_FPU %{
1866 // If method sets FPU control word do it here also
1867 if (Compile::current()->in_24_bit_fp_mode()) {
1868 MacroAssembler masm(&cbuf);
1869 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1870 }
1871 %}
1872
1873 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1874 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1875 // who we intended to call.
1876 cbuf.set_insts_mark();
1877 $$$emit8$primary;
1878 if (!_method) {
1879 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1880 runtime_call_Relocation::spec(), RELOC_IMM32 );
1881 } else if (_optimized_virtual) {
1882 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1883 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1884 } else {
1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1886 static_call_Relocation::spec(), RELOC_IMM32 );
1887 }
1888 if (_method) { // Emit stub for static call.
1889 CompiledStaticCall::emit_to_interp_stub(cbuf);
1890 }
1891 %}
1892
1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1894 MacroAssembler _masm(&cbuf);
1895 __ ic_call((address)$meth$$method);
1896 %}
1897
1898 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1899 int disp = in_bytes(Method::from_compiled_offset());
1900 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1901
1902 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1903 cbuf.set_insts_mark();
1904 $$$emit8$primary;
1905 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1906 emit_d8(cbuf, disp); // Displacement
1907
1908 %}
1909
1910 // Following encoding is no longer used, but may be restored if calling
1911 // convention changes significantly.
1912 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1913 //
1914 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1915 // // int ic_reg = Matcher::inline_cache_reg();
1916 // // int ic_encode = Matcher::_regEncode[ic_reg];
1917 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1918 // // int imo_encode = Matcher::_regEncode[imo_reg];
1919 //
1920 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1921 // // // so we load it immediately before the call
1922 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1923 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1924 //
1925 // // xor rbp,ebp
1926 // emit_opcode(cbuf, 0x33);
1927 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1928 //
1929 // // CALL to interpreter.
1930 // cbuf.set_insts_mark();
1931 // $$$emit8$primary;
1932 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1933 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1934 // %}
1935
1936 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1937 $$$emit8$primary;
1938 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1939 $$$emit8$shift$$constant;
1940 %}
1941
1942 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1943 // Load immediate does not have a zero or sign extended version
1944 // for 8-bit immediates
1945 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1946 $$$emit32$src$$constant;
1947 %}
1948
1949 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1950 // Load immediate does not have a zero or sign extended version
1951 // for 8-bit immediates
1952 emit_opcode(cbuf, $primary + $dst$$reg);
1953 $$$emit32$src$$constant;
1954 %}
1955
1956 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1957 // Load immediate does not have a zero or sign extended version
1958 // for 8-bit immediates
1959 int dst_enc = $dst$$reg;
1960 int src_con = $src$$constant & 0x0FFFFFFFFL;
1961 if (src_con == 0) {
1962 // xor dst, dst
1963 emit_opcode(cbuf, 0x33);
1964 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1965 } else {
1966 emit_opcode(cbuf, $primary + dst_enc);
1967 emit_d32(cbuf, src_con);
1968 }
1969 %}
1970
1971 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1972 // Load immediate does not have a zero or sign extended version
1973 // for 8-bit immediates
1974 int dst_enc = $dst$$reg + 2;
1975 int src_con = ((julong)($src$$constant)) >> 32;
1976 if (src_con == 0) {
1977 // xor dst, dst
1978 emit_opcode(cbuf, 0x33);
1979 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1980 } else {
1981 emit_opcode(cbuf, $primary + dst_enc);
1982 emit_d32(cbuf, src_con);
1983 }
1984 %}
1985
1986
1987 // Encode a reg-reg copy. If it is useless, then empty encoding.
1988 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1989 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1990 %}
1991
1992 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1993 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1994 %}
1995
1996 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1998 %}
1999
2000 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2001 $$$emit8$primary;
2002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2003 %}
2004
2005 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 $$$emit8$secondary;
2007 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2008 %}
2009
2010 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2011 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2012 %}
2013
2014 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016 %}
2017
2018 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2019 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2020 %}
2021
2022 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2023 // Output immediate
2024 $$$emit32$src$$constant;
2025 %}
2026
2027 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2028 // Output Float immediate bits
2029 jfloat jf = $src$$constant;
2030 int jf_as_bits = jint_cast( jf );
2031 emit_d32(cbuf, jf_as_bits);
2032 %}
2033
2034 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2035 // Output Float immediate bits
2036 jfloat jf = $src$$constant;
2037 int jf_as_bits = jint_cast( jf );
2038 emit_d32(cbuf, jf_as_bits);
2039 %}
2040
2041 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2042 // Output immediate
2043 $$$emit16$src$$constant;
2044 %}
2045
2046 enc_class Con_d32(immI src) %{
2047 emit_d32(cbuf,$src$$constant);
2048 %}
2049
2050 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2051 // Output immediate memory reference
2052 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2053 emit_d32(cbuf, 0x00);
2054 %}
2055
2056 enc_class lock_prefix( ) %{
2057 if( os::is_MP() )
2058 emit_opcode(cbuf,0xF0); // [Lock]
2059 %}
2060
2061 // Cmp-xchg long value.
2062 // Note: we need to swap rbx, and rcx before and after the
2063 // cmpxchg8 instruction because the instruction uses
2064 // rcx as the high order word of the new value to store but
2065 // our register encoding uses rbx,.
2066 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2067
2068 // XCHG rbx,ecx
2069 emit_opcode(cbuf,0x87);
2070 emit_opcode(cbuf,0xD9);
2071 // [Lock]
2072 if( os::is_MP() )
2073 emit_opcode(cbuf,0xF0);
2074 // CMPXCHG8 [Eptr]
2075 emit_opcode(cbuf,0x0F);
2076 emit_opcode(cbuf,0xC7);
2077 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2078 // XCHG rbx,ecx
2079 emit_opcode(cbuf,0x87);
2080 emit_opcode(cbuf,0xD9);
2081 %}
2082
2083 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2084 // [Lock]
2085 if( os::is_MP() )
2086 emit_opcode(cbuf,0xF0);
2087
2088 // CMPXCHG [Eptr]
2089 emit_opcode(cbuf,0x0F);
2090 emit_opcode(cbuf,0xB1);
2091 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2092 %}
2093
2094 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2095 int res_encoding = $res$$reg;
2096
2097 // MOV res,0
2098 emit_opcode( cbuf, 0xB8 + res_encoding);
2099 emit_d32( cbuf, 0 );
2100 // JNE,s fail
2101 emit_opcode(cbuf,0x75);
2102 emit_d8(cbuf, 5 );
2103 // MOV res,1
2104 emit_opcode( cbuf, 0xB8 + res_encoding);
2105 emit_d32( cbuf, 1 );
2106 // fail:
2107 %}
2108
2109 enc_class set_instruction_start( ) %{
2110 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2111 %}
2112
2113 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2114 int reg_encoding = $ereg$$reg;
2115 int base = $mem$$base;
2116 int index = $mem$$index;
2117 int scale = $mem$$scale;
2118 int displace = $mem$$disp;
2119 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2120 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2121 %}
2122
2123 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2124 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2125 int base = $mem$$base;
2126 int index = $mem$$index;
2127 int scale = $mem$$scale;
2128 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2129 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2131 %}
2132
2133 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2134 int r1, r2;
2135 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2136 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2137 emit_opcode(cbuf,0x0F);
2138 emit_opcode(cbuf,$tertiary);
2139 emit_rm(cbuf, 0x3, r1, r2);
2140 emit_d8(cbuf,$cnt$$constant);
2141 emit_d8(cbuf,$primary);
2142 emit_rm(cbuf, 0x3, $secondary, r1);
2143 emit_d8(cbuf,$cnt$$constant);
2144 %}
2145
2146 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2147 emit_opcode( cbuf, 0x8B ); // Move
2148 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2149 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2150 emit_d8(cbuf,$primary);
2151 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2152 emit_d8(cbuf,$cnt$$constant-32);
2153 }
2154 emit_d8(cbuf,$primary);
2155 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2156 emit_d8(cbuf,31);
2157 %}
2158
2159 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2160 int r1, r2;
2161 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2162 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2163
2164 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2165 emit_rm(cbuf, 0x3, r1, r2);
2166 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2167 emit_opcode(cbuf,$primary);
2168 emit_rm(cbuf, 0x3, $secondary, r1);
2169 emit_d8(cbuf,$cnt$$constant-32);
2170 }
2171 emit_opcode(cbuf,0x33); // XOR r2,r2
2172 emit_rm(cbuf, 0x3, r2, r2);
2173 %}
2174
2175 // Clone of RegMem but accepts an extra parameter to access each
2176 // half of a double in memory; it never needs relocation info.
2177 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2178 emit_opcode(cbuf,$opcode$$constant);
2179 int reg_encoding = $rm_reg$$reg;
2180 int base = $mem$$base;
2181 int index = $mem$$index;
2182 int scale = $mem$$scale;
2183 int displace = $mem$$disp + $disp_for_half$$constant;
2184 relocInfo::relocType disp_reloc = relocInfo::none;
2185 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2186 %}
2187
2188 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2189 //
2190 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2191 // and it never needs relocation information.
2192 // Frequently used to move data between FPU's Stack Top and memory.
2193 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2194 int rm_byte_opcode = $rm_opcode$$constant;
2195 int base = $mem$$base;
2196 int index = $mem$$index;
2197 int scale = $mem$$scale;
2198 int displace = $mem$$disp;
2199 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2201 %}
2202
2203 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2204 int rm_byte_opcode = $rm_opcode$$constant;
2205 int base = $mem$$base;
2206 int index = $mem$$index;
2207 int scale = $mem$$scale;
2208 int displace = $mem$$disp;
2209 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2210 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2211 %}
2212
2213 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2214 int reg_encoding = $dst$$reg;
2215 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2216 int index = 0x04; // 0x04 indicates no index
2217 int scale = 0x00; // 0x00 indicates no scale
2218 int displace = $src1$$constant; // 0x00 indicates no displacement
2219 relocInfo::relocType disp_reloc = relocInfo::none;
2220 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2221 %}
2222
2223 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2224 // Compare dst,src
2225 emit_opcode(cbuf,0x3B);
2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2227 // jmp dst < src around move
2228 emit_opcode(cbuf,0x7C);
2229 emit_d8(cbuf,2);
2230 // move dst,src
2231 emit_opcode(cbuf,0x8B);
2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2233 %}
2234
2235 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2236 // Compare dst,src
2237 emit_opcode(cbuf,0x3B);
2238 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2239 // jmp dst > src around move
2240 emit_opcode(cbuf,0x7F);
2241 emit_d8(cbuf,2);
2242 // move dst,src
2243 emit_opcode(cbuf,0x8B);
2244 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2245 %}
2246
2247 enc_class enc_FPR_store(memory mem, regDPR src) %{
2248 // If src is FPR1, we can just FST to store it.
2249 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2250 int reg_encoding = 0x2; // Just store
2251 int base = $mem$$base;
2252 int index = $mem$$index;
2253 int scale = $mem$$scale;
2254 int displace = $mem$$disp;
2255 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2256 if( $src$$reg != FPR1L_enc ) {
2257 reg_encoding = 0x3; // Store & pop
2258 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2259 emit_d8( cbuf, 0xC0-1+$src$$reg );
2260 }
2261 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2262 emit_opcode(cbuf,$primary);
2263 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2264 %}
2265
2266 enc_class neg_reg(rRegI dst) %{
2267 // NEG $dst
2268 emit_opcode(cbuf,0xF7);
2269 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2270 %}
2271
2272 enc_class setLT_reg(eCXRegI dst) %{
2273 // SETLT $dst
2274 emit_opcode(cbuf,0x0F);
2275 emit_opcode(cbuf,0x9C);
2276 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2277 %}
2278
2279 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2280 int tmpReg = $tmp$$reg;
2281
2282 // SUB $p,$q
2283 emit_opcode(cbuf,0x2B);
2284 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2285 // SBB $tmp,$tmp
2286 emit_opcode(cbuf,0x1B);
2287 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2288 // AND $tmp,$y
2289 emit_opcode(cbuf,0x23);
2290 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2291 // ADD $p,$tmp
2292 emit_opcode(cbuf,0x03);
2293 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2294 %}
2295
2296 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2297 // TEST shift,32
2298 emit_opcode(cbuf,0xF7);
2299 emit_rm(cbuf, 0x3, 0, ECX_enc);
2300 emit_d32(cbuf,0x20);
2301 // JEQ,s small
2302 emit_opcode(cbuf, 0x74);
2303 emit_d8(cbuf, 0x04);
2304 // MOV $dst.hi,$dst.lo
2305 emit_opcode( cbuf, 0x8B );
2306 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2307 // CLR $dst.lo
2308 emit_opcode(cbuf, 0x33);
2309 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2310 // small:
2311 // SHLD $dst.hi,$dst.lo,$shift
2312 emit_opcode(cbuf,0x0F);
2313 emit_opcode(cbuf,0xA5);
2314 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2315 // SHL $dst.lo,$shift"
2316 emit_opcode(cbuf,0xD3);
2317 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2318 %}
2319
2320 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2321 // TEST shift,32
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0, ECX_enc);
2324 emit_d32(cbuf,0x20);
2325 // JEQ,s small
2326 emit_opcode(cbuf, 0x74);
2327 emit_d8(cbuf, 0x04);
2328 // MOV $dst.lo,$dst.hi
2329 emit_opcode( cbuf, 0x8B );
2330 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2331 // CLR $dst.hi
2332 emit_opcode(cbuf, 0x33);
2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2334 // small:
2335 // SHRD $dst.lo,$dst.hi,$shift
2336 emit_opcode(cbuf,0x0F);
2337 emit_opcode(cbuf,0xAD);
2338 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2339 // SHR $dst.hi,$shift"
2340 emit_opcode(cbuf,0xD3);
2341 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2342 %}
2343
2344 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2345 // TEST shift,32
2346 emit_opcode(cbuf,0xF7);
2347 emit_rm(cbuf, 0x3, 0, ECX_enc);
2348 emit_d32(cbuf,0x20);
2349 // JEQ,s small
2350 emit_opcode(cbuf, 0x74);
2351 emit_d8(cbuf, 0x05);
2352 // MOV $dst.lo,$dst.hi
2353 emit_opcode( cbuf, 0x8B );
2354 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2355 // SAR $dst.hi,31
2356 emit_opcode(cbuf, 0xC1);
2357 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2358 emit_d8(cbuf, 0x1F );
2359 // small:
2360 // SHRD $dst.lo,$dst.hi,$shift
2361 emit_opcode(cbuf,0x0F);
2362 emit_opcode(cbuf,0xAD);
2363 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2364 // SAR $dst.hi,$shift"
2365 emit_opcode(cbuf,0xD3);
2366 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2367 %}
2368
2369
2370 // ----------------- Encodings for floating point unit -----------------
2371 // May leave result in FPU-TOS or FPU reg depending on opcodes
2372 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2373 $$$emit8$primary;
2374 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2375 %}
2376
2377 // Pop argument in FPR0 with FSTP ST(0)
2378 enc_class PopFPU() %{
2379 emit_opcode( cbuf, 0xDD );
2380 emit_d8( cbuf, 0xD8 );
2381 %}
2382
2383 // !!!!! equivalent to Pop_Reg_F
2384 enc_class Pop_Reg_DPR( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2386 emit_d8( cbuf, 0xD8+$dst$$reg );
2387 %}
2388
2389 enc_class Push_Reg_DPR( regDPR dst ) %{
2390 emit_opcode( cbuf, 0xD9 );
2391 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2392 %}
2393
2394 enc_class strictfp_bias1( regDPR dst ) %{
2395 emit_opcode( cbuf, 0xDB ); // FLD m80real
2396 emit_opcode( cbuf, 0x2D );
2397 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2398 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2399 emit_opcode( cbuf, 0xC8+$dst$$reg );
2400 %}
2401
2402 enc_class strictfp_bias2( regDPR dst ) %{
2403 emit_opcode( cbuf, 0xDB ); // FLD m80real
2404 emit_opcode( cbuf, 0x2D );
2405 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2406 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2407 emit_opcode( cbuf, 0xC8+$dst$$reg );
2408 %}
2409
2410 // Special case for moving an integer register to a stack slot.
2411 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2412 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2413 %}
2414
2415 // Special case for moving a register to a stack slot.
2416 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2417 // Opcode already emitted
2418 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2419 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2420 emit_d32(cbuf, $dst$$disp); // Displacement
2421 %}
2422
2423 // Push the integer in stackSlot 'src' onto FP-stack
2424 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2425 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2426 %}
2427
2428 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2429 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2430 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2431 %}
2432
2433 // Same as Pop_Mem_F except for opcode
2434 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2435 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2436 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2437 %}
2438
2439 enc_class Pop_Reg_FPR( regFPR dst ) %{
2440 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2441 emit_d8( cbuf, 0xD8+$dst$$reg );
2442 %}
2443
2444 enc_class Push_Reg_FPR( regFPR dst ) %{
2445 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2446 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2447 %}
2448
2449 // Push FPU's float to a stack-slot, and pop FPU-stack
2450 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2451 int pop = 0x02;
2452 if ($src$$reg != FPR1L_enc) {
2453 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2454 emit_d8( cbuf, 0xC0-1+$src$$reg );
2455 pop = 0x03;
2456 }
2457 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2458 %}
2459
2460 // Push FPU's double to a stack-slot, and pop FPU-stack
2461 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2462 int pop = 0x02;
2463 if ($src$$reg != FPR1L_enc) {
2464 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2465 emit_d8( cbuf, 0xC0-1+$src$$reg );
2466 pop = 0x03;
2467 }
2468 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2469 %}
2470
2471 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2472 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2473 int pop = 0xD0 - 1; // -1 since we skip FLD
2474 if ($src$$reg != FPR1L_enc) {
2475 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2476 emit_d8( cbuf, 0xC0-1+$src$$reg );
2477 pop = 0xD8;
2478 }
2479 emit_opcode( cbuf, 0xDD );
2480 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2481 %}
2482
2483
2484 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2485 // load dst in FPR0
2486 emit_opcode( cbuf, 0xD9 );
2487 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2488 if ($src$$reg != FPR1L_enc) {
2489 // fincstp
2490 emit_opcode (cbuf, 0xD9);
2491 emit_opcode (cbuf, 0xF7);
2492 // swap src with FPR1:
2493 // FXCH FPR1 with src
2494 emit_opcode(cbuf, 0xD9);
2495 emit_d8(cbuf, 0xC8-1+$src$$reg );
2496 // fdecstp
2497 emit_opcode (cbuf, 0xD9);
2498 emit_opcode (cbuf, 0xF6);
2499 }
2500 %}
2501
2502 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2503 MacroAssembler _masm(&cbuf);
2504 __ subptr(rsp, 8);
2505 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2506 __ fld_d(Address(rsp, 0));
2507 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2508 __ fld_d(Address(rsp, 0));
2509 %}
2510
2511 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2512 MacroAssembler _masm(&cbuf);
2513 __ subptr(rsp, 4);
2514 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2515 __ fld_s(Address(rsp, 0));
2516 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2517 __ fld_s(Address(rsp, 0));
2518 %}
2519
2520 enc_class Push_ResultD(regD dst) %{
2521 MacroAssembler _masm(&cbuf);
2522 __ fstp_d(Address(rsp, 0));
2523 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2524 __ addptr(rsp, 8);
2525 %}
2526
2527 enc_class Push_ResultF(regF dst, immI d8) %{
2528 MacroAssembler _masm(&cbuf);
2529 __ fstp_s(Address(rsp, 0));
2530 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2531 __ addptr(rsp, $d8$$constant);
2532 %}
2533
2534 enc_class Push_SrcD(regD src) %{
2535 MacroAssembler _masm(&cbuf);
2536 __ subptr(rsp, 8);
2537 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2538 __ fld_d(Address(rsp, 0));
2539 %}
2540
2541 enc_class push_stack_temp_qword() %{
2542 MacroAssembler _masm(&cbuf);
2543 __ subptr(rsp, 8);
2544 %}
2545
2546 enc_class pop_stack_temp_qword() %{
2547 MacroAssembler _masm(&cbuf);
2548 __ addptr(rsp, 8);
2549 %}
2550
2551 enc_class push_xmm_to_fpr1(regD src) %{
2552 MacroAssembler _masm(&cbuf);
2553 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2554 __ fld_d(Address(rsp, 0));
2555 %}
2556
2557 enc_class Push_Result_Mod_DPR( regDPR src) %{
2558 if ($src$$reg != FPR1L_enc) {
2559 // fincstp
2560 emit_opcode (cbuf, 0xD9);
2561 emit_opcode (cbuf, 0xF7);
2562 // FXCH FPR1 with src
2563 emit_opcode(cbuf, 0xD9);
2564 emit_d8(cbuf, 0xC8-1+$src$$reg );
2565 // fdecstp
2566 emit_opcode (cbuf, 0xD9);
2567 emit_opcode (cbuf, 0xF6);
2568 }
2569 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2570 // // FSTP FPR$dst$$reg
2571 // emit_opcode( cbuf, 0xDD );
2572 // emit_d8( cbuf, 0xD8+$dst$$reg );
2573 %}
2574
2575 enc_class fnstsw_sahf_skip_parity() %{
2576 // fnstsw ax
2577 emit_opcode( cbuf, 0xDF );
2578 emit_opcode( cbuf, 0xE0 );
2579 // sahf
2580 emit_opcode( cbuf, 0x9E );
2581 // jnp ::skip
2582 emit_opcode( cbuf, 0x7B );
2583 emit_opcode( cbuf, 0x05 );
2584 %}
2585
2586 enc_class emitModDPR() %{
2587 // fprem must be iterative
2588 // :: loop
2589 // fprem
2590 emit_opcode( cbuf, 0xD9 );
2591 emit_opcode( cbuf, 0xF8 );
2592 // wait
2593 emit_opcode( cbuf, 0x9b );
2594 // fnstsw ax
2595 emit_opcode( cbuf, 0xDF );
2596 emit_opcode( cbuf, 0xE0 );
2597 // sahf
2598 emit_opcode( cbuf, 0x9E );
2599 // jp ::loop
2600 emit_opcode( cbuf, 0x0F );
2601 emit_opcode( cbuf, 0x8A );
2602 emit_opcode( cbuf, 0xF4 );
2603 emit_opcode( cbuf, 0xFF );
2604 emit_opcode( cbuf, 0xFF );
2605 emit_opcode( cbuf, 0xFF );
2606 %}
2607
2608 enc_class fpu_flags() %{
2609 // fnstsw_ax
2610 emit_opcode( cbuf, 0xDF);
2611 emit_opcode( cbuf, 0xE0);
2612 // test ax,0x0400
2613 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2614 emit_opcode( cbuf, 0xA9 );
2615 emit_d16 ( cbuf, 0x0400 );
2616 // // // This sequence works, but stalls for 12-16 cycles on PPro
2617 // // test rax,0x0400
2618 // emit_opcode( cbuf, 0xA9 );
2619 // emit_d32 ( cbuf, 0x00000400 );
2620 //
2621 // jz exit (no unordered comparison)
2622 emit_opcode( cbuf, 0x74 );
2623 emit_d8 ( cbuf, 0x02 );
2624 // mov ah,1 - treat as LT case (set carry flag)
2625 emit_opcode( cbuf, 0xB4 );
2626 emit_d8 ( cbuf, 0x01 );
2627 // sahf
2628 emit_opcode( cbuf, 0x9E);
2629 %}
2630
2631 enc_class cmpF_P6_fixup() %{
2632 // Fixup the integer flags in case comparison involved a NaN
2633 //
2634 // JNP exit (no unordered comparison, P-flag is set by NaN)
2635 emit_opcode( cbuf, 0x7B );
2636 emit_d8 ( cbuf, 0x03 );
2637 // MOV AH,1 - treat as LT case (set carry flag)
2638 emit_opcode( cbuf, 0xB4 );
2639 emit_d8 ( cbuf, 0x01 );
2640 // SAHF
2641 emit_opcode( cbuf, 0x9E);
2642 // NOP // target for branch to avoid branch to branch
2643 emit_opcode( cbuf, 0x90);
2644 %}
2645
2646 // fnstsw_ax();
2647 // sahf();
2648 // movl(dst, nan_result);
2649 // jcc(Assembler::parity, exit);
2650 // movl(dst, less_result);
2651 // jcc(Assembler::below, exit);
2652 // movl(dst, equal_result);
2653 // jcc(Assembler::equal, exit);
2654 // movl(dst, greater_result);
2655
2656 // less_result = 1;
2657 // greater_result = -1;
2658 // equal_result = 0;
2659 // nan_result = -1;
2660
2661 enc_class CmpF_Result(rRegI dst) %{
2662 // fnstsw_ax();
2663 emit_opcode( cbuf, 0xDF);
2664 emit_opcode( cbuf, 0xE0);
2665 // sahf
2666 emit_opcode( cbuf, 0x9E);
2667 // movl(dst, nan_result);
2668 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2669 emit_d32( cbuf, -1 );
2670 // jcc(Assembler::parity, exit);
2671 emit_opcode( cbuf, 0x7A );
2672 emit_d8 ( cbuf, 0x13 );
2673 // movl(dst, less_result);
2674 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2675 emit_d32( cbuf, -1 );
2676 // jcc(Assembler::below, exit);
2677 emit_opcode( cbuf, 0x72 );
2678 emit_d8 ( cbuf, 0x0C );
2679 // movl(dst, equal_result);
2680 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2681 emit_d32( cbuf, 0 );
2682 // jcc(Assembler::equal, exit);
2683 emit_opcode( cbuf, 0x74 );
2684 emit_d8 ( cbuf, 0x05 );
2685 // movl(dst, greater_result);
2686 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2687 emit_d32( cbuf, 1 );
2688 %}
2689
2690
2691 // Compare the longs and set flags
2692 // BROKEN! Do Not use as-is
2693 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2694 // CMP $src1.hi,$src2.hi
2695 emit_opcode( cbuf, 0x3B );
2696 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2697 // JNE,s done
2698 emit_opcode(cbuf,0x75);
2699 emit_d8(cbuf, 2 );
2700 // CMP $src1.lo,$src2.lo
2701 emit_opcode( cbuf, 0x3B );
2702 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2703 // done:
2704 %}
2705
2706 enc_class convert_int_long( regL dst, rRegI src ) %{
2707 // mov $dst.lo,$src
2708 int dst_encoding = $dst$$reg;
2709 int src_encoding = $src$$reg;
2710 encode_Copy( cbuf, dst_encoding , src_encoding );
2711 // mov $dst.hi,$src
2712 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2713 // sar $dst.hi,31
2714 emit_opcode( cbuf, 0xC1 );
2715 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2716 emit_d8(cbuf, 0x1F );
2717 %}
2718
2719 enc_class convert_long_double( eRegL src ) %{
2720 // push $src.hi
2721 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2722 // push $src.lo
2723 emit_opcode(cbuf, 0x50+$src$$reg );
2724 // fild 64-bits at [SP]
2725 emit_opcode(cbuf,0xdf);
2726 emit_d8(cbuf, 0x6C);
2727 emit_d8(cbuf, 0x24);
2728 emit_d8(cbuf, 0x00);
2729 // pop stack
2730 emit_opcode(cbuf, 0x83); // add SP, #8
2731 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2732 emit_d8(cbuf, 0x8);
2733 %}
2734
2735 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2736 // IMUL EDX:EAX,$src1
2737 emit_opcode( cbuf, 0xF7 );
2738 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2739 // SAR EDX,$cnt-32
2740 int shift_count = ((int)$cnt$$constant) - 32;
2741 if (shift_count > 0) {
2742 emit_opcode(cbuf, 0xC1);
2743 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2744 emit_d8(cbuf, shift_count);
2745 }
2746 %}
2747
2748 // this version doesn't have add sp, 8
2749 enc_class convert_long_double2( eRegL src ) %{
2750 // push $src.hi
2751 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2752 // push $src.lo
2753 emit_opcode(cbuf, 0x50+$src$$reg );
2754 // fild 64-bits at [SP]
2755 emit_opcode(cbuf,0xdf);
2756 emit_d8(cbuf, 0x6C);
2757 emit_d8(cbuf, 0x24);
2758 emit_d8(cbuf, 0x00);
2759 %}
2760
2761 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2762 // Basic idea: long = (long)int * (long)int
2763 // IMUL EDX:EAX, src
2764 emit_opcode( cbuf, 0xF7 );
2765 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2766 %}
2767
2768 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2769 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2770 // MUL EDX:EAX, src
2771 emit_opcode( cbuf, 0xF7 );
2772 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2773 %}
2774
2775 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2776 // Basic idea: lo(result) = lo(x_lo * y_lo)
2777 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2778 // MOV $tmp,$src.lo
2779 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2780 // IMUL $tmp,EDX
2781 emit_opcode( cbuf, 0x0F );
2782 emit_opcode( cbuf, 0xAF );
2783 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2784 // MOV EDX,$src.hi
2785 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2786 // IMUL EDX,EAX
2787 emit_opcode( cbuf, 0x0F );
2788 emit_opcode( cbuf, 0xAF );
2789 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2790 // ADD $tmp,EDX
2791 emit_opcode( cbuf, 0x03 );
2792 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2793 // MUL EDX:EAX,$src.lo
2794 emit_opcode( cbuf, 0xF7 );
2795 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2796 // ADD EDX,ESI
2797 emit_opcode( cbuf, 0x03 );
2798 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2799 %}
2800
2801 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2802 // Basic idea: lo(result) = lo(src * y_lo)
2803 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2804 // IMUL $tmp,EDX,$src
2805 emit_opcode( cbuf, 0x6B );
2806 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2807 emit_d8( cbuf, (int)$src$$constant );
2808 // MOV EDX,$src
2809 emit_opcode(cbuf, 0xB8 + EDX_enc);
2810 emit_d32( cbuf, (int)$src$$constant );
2811 // MUL EDX:EAX,EDX
2812 emit_opcode( cbuf, 0xF7 );
2813 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2814 // ADD EDX,ESI
2815 emit_opcode( cbuf, 0x03 );
2816 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2817 %}
2818
2819 enc_class long_div( eRegL src1, eRegL src2 ) %{
2820 // PUSH src1.hi
2821 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2822 // PUSH src1.lo
2823 emit_opcode(cbuf, 0x50+$src1$$reg );
2824 // PUSH src2.hi
2825 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2826 // PUSH src2.lo
2827 emit_opcode(cbuf, 0x50+$src2$$reg );
2828 // CALL directly to the runtime
2829 cbuf.set_insts_mark();
2830 emit_opcode(cbuf,0xE8); // Call into runtime
2831 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2832 // Restore stack
2833 emit_opcode(cbuf, 0x83); // add SP, #framesize
2834 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2835 emit_d8(cbuf, 4*4);
2836 %}
2837
2838 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2839 // PUSH src1.hi
2840 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2841 // PUSH src1.lo
2842 emit_opcode(cbuf, 0x50+$src1$$reg );
2843 // PUSH src2.hi
2844 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2845 // PUSH src2.lo
2846 emit_opcode(cbuf, 0x50+$src2$$reg );
2847 // CALL directly to the runtime
2848 cbuf.set_insts_mark();
2849 emit_opcode(cbuf,0xE8); // Call into runtime
2850 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2851 // Restore stack
2852 emit_opcode(cbuf, 0x83); // add SP, #framesize
2853 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2854 emit_d8(cbuf, 4*4);
2855 %}
2856
2857 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2858 // MOV $tmp,$src.lo
2859 emit_opcode(cbuf, 0x8B);
2860 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2861 // OR $tmp,$src.hi
2862 emit_opcode(cbuf, 0x0B);
2863 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2864 %}
2865
2866 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2867 // CMP $src1.lo,$src2.lo
2868 emit_opcode( cbuf, 0x3B );
2869 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2870 // JNE,s skip
2871 emit_cc(cbuf, 0x70, 0x5);
2872 emit_d8(cbuf,2);
2873 // CMP $src1.hi,$src2.hi
2874 emit_opcode( cbuf, 0x3B );
2875 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2876 %}
2877
2878 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2879 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2880 emit_opcode( cbuf, 0x3B );
2881 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2882 // MOV $tmp,$src1.hi
2883 emit_opcode( cbuf, 0x8B );
2884 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2885 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2886 emit_opcode( cbuf, 0x1B );
2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2888 %}
2889
2890 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2891 // XOR $tmp,$tmp
2892 emit_opcode(cbuf,0x33); // XOR
2893 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2894 // CMP $tmp,$src.lo
2895 emit_opcode( cbuf, 0x3B );
2896 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2897 // SBB $tmp,$src.hi
2898 emit_opcode( cbuf, 0x1B );
2899 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2900 %}
2901
2902 // Sniff, sniff... smells like Gnu Superoptimizer
2903 enc_class neg_long( eRegL dst ) %{
2904 emit_opcode(cbuf,0xF7); // NEG hi
2905 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2906 emit_opcode(cbuf,0xF7); // NEG lo
2907 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2908 emit_opcode(cbuf,0x83); // SBB hi,0
2909 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2910 emit_d8 (cbuf,0 );
2911 %}
2912
2913
2914 // Because the transitions from emitted code to the runtime
2915 // monitorenter/exit helper stubs are so slow it's critical that
2916 // we inline both the stack-locking fast-path and the inflated fast path.
2917 //
2918 // See also: cmpFastLock and cmpFastUnlock.
2919 //
2920 // What follows is a specialized inline transliteration of the code
2921 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2922 // another option would be to emit TrySlowEnter and TrySlowExit methods
2923 // at startup-time. These methods would accept arguments as
2924 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2925 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2926 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2927 // In practice, however, the # of lock sites is bounded and is usually small.
2928 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2929 // if the processor uses simple bimodal branch predictors keyed by EIP
2930 // Since the helper routines would be called from multiple synchronization
2931 // sites.
2932 //
2933 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2934 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2935 // to those specialized methods. That'd give us a mostly platform-independent
2936 // implementation that the JITs could optimize and inline at their pleasure.
2937 // Done correctly, the only time we'd need to cross to native could would be
2938 // to park() or unpark() threads. We'd also need a few more unsafe operators
2939 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2940 // (b) explicit barriers or fence operations.
2941 //
2942 // TODO:
2943 //
2944 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2945 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2946 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2947 // the lock operators would typically be faster than reifying Self.
2948 //
2949 // * Ideally I'd define the primitives as:
2950 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2951 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2952 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2953 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2954 // Furthermore the register assignments are overconstrained, possibly resulting in
2955 // sub-optimal code near the synchronization site.
2956 //
2957 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2958 // Alternately, use a better sp-proximity test.
2959 //
2960 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2961 // Either one is sufficient to uniquely identify a thread.
2962 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2963 //
2964 // * Intrinsify notify() and notifyAll() for the common cases where the
2965 // object is locked by the calling thread but the waitlist is empty.
2966 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2967 //
2968 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2969 // But beware of excessive branch density on AMD Opterons.
2970 //
2971 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2972 // or failure of the fast-path. If the fast-path fails then we pass
2973 // control to the slow-path, typically in C. In Fast_Lock and
2974 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2975 // will emit a conditional branch immediately after the node.
2976 // So we have branches to branches and lots of ICC.ZF games.
2977 // Instead, it might be better to have C2 pass a "FailureLabel"
2978 // into Fast_Lock and Fast_Unlock. In the case of success, control
2979 // will drop through the node. ICC.ZF is undefined at exit.
2980 // In the case of failure, the node will branch directly to the
2981 // FailureLabel
2982
2983
2984 // obj: object to lock
2985 // box: on-stack box address (displaced header location) - KILLED
2986 // rax,: tmp -- KILLED
2987 // scr: tmp -- KILLED
2988 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2989
2990 Register objReg = as_Register($obj$$reg);
2991 Register boxReg = as_Register($box$$reg);
2992 Register tmpReg = as_Register($tmp$$reg);
2993 Register scrReg = as_Register($scr$$reg);
2994
2995 // Ensure the register assignents are disjoint
2996 guarantee (objReg != boxReg, "") ;
2997 guarantee (objReg != tmpReg, "") ;
2998 guarantee (objReg != scrReg, "") ;
2999 guarantee (boxReg != tmpReg, "") ;
3000 guarantee (boxReg != scrReg, "") ;
3001 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3002
3003 MacroAssembler masm(&cbuf);
3004
3005 if (_counters != NULL) {
3006 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3007 }
3008 if (EmitSync & 1) {
3009 // set box->dhw = unused_mark (3)
3010 // Force all sync thru slow-path: slow_enter() and slow_exit()
3011 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3012 masm.cmpptr (rsp, (int32_t)0) ;
3013 } else
3014 if (EmitSync & 2) {
3015 Label DONE_LABEL ;
3016 if (UseBiasedLocking) {
3017 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3018 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3019 }
3020
3021 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3022 masm.orptr (tmpReg, 0x1);
3023 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3024 if (os::is_MP()) { masm.lock(); }
3025 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3026 masm.jcc(Assembler::equal, DONE_LABEL);
3027 // Recursive locking
3028 masm.subptr(tmpReg, rsp);
3029 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3030 masm.movptr(Address(boxReg, 0), tmpReg);
3031 masm.bind(DONE_LABEL) ;
3032 } else {
3033 // Possible cases that we'll encounter in fast_lock
3034 // ------------------------------------------------
3035 // * Inflated
3036 // -- unlocked
3037 // -- Locked
3038 // = by self
3039 // = by other
3040 // * biased
3041 // -- by Self
3042 // -- by other
3043 // * neutral
3044 // * stack-locked
3045 // -- by self
3046 // = sp-proximity test hits
3047 // = sp-proximity test generates false-negative
3048 // -- by other
3049 //
3050
3051 Label IsInflated, DONE_LABEL, PopDone ;
3052
3053 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3054 // order to reduce the number of conditional branches in the most common cases.
3055 // Beware -- there's a subtle invariant that fetch of the markword
3056 // at [FETCH], below, will never observe a biased encoding (*101b).
3057 // If this invariant is not held we risk exclusion (safety) failure.
3058 if (UseBiasedLocking && !UseOptoBiasInlining) {
3059 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3060 }
3061
3062 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3063 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3064 masm.jccb (Assembler::notZero, IsInflated) ;
3065
3066 // Attempt stack-locking ...
3067 masm.orptr (tmpReg, 0x1);
3068 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3069 if (os::is_MP()) { masm.lock(); }
3070 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3071 if (_counters != NULL) {
3072 masm.cond_inc32(Assembler::equal,
3073 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3074 }
3075 masm.jccb (Assembler::equal, DONE_LABEL);
3076
3077 // Recursive locking
3078 masm.subptr(tmpReg, rsp);
3079 masm.andptr(tmpReg, 0xFFFFF003 );
3080 masm.movptr(Address(boxReg, 0), tmpReg);
3081 if (_counters != NULL) {
3082 masm.cond_inc32(Assembler::equal,
3083 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3084 }
3085 masm.jmp (DONE_LABEL) ;
3086
3087 masm.bind (IsInflated) ;
3088
3089 // The object is inflated.
3090 //
3091 // TODO-FIXME: eliminate the ugly use of manifest constants:
3092 // Use markOopDesc::monitor_value instead of "2".
3093 // use markOop::unused_mark() instead of "3".
3094 // The tmpReg value is an objectMonitor reference ORed with
3095 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3096 // objectmonitor pointer by masking off the "2" bit or we can just
3097 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3098 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3099 //
3100 // I use the latter as it avoids AGI stalls.
3101 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3102 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3103 //
3104 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3105
3106 // boxReg refers to the on-stack BasicLock in the current frame.
3107 // We'd like to write:
3108 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3109 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3110 // additional latency as we have another ST in the store buffer that must drain.
3111
3112 if (EmitSync & 8192) {
3113 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3114 masm.get_thread (scrReg) ;
3115 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3116 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3117 if (os::is_MP()) { masm.lock(); }
3118 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3119 } else
3120 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3121 masm.movptr(scrReg, boxReg) ;
3122 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3123
3124 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3125 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3126 // prefetchw [eax + Offset(_owner)-2]
3127 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3128 }
3129
3130 if ((EmitSync & 64) == 0) {
3131 // Optimistic form: consider XORL tmpReg,tmpReg
3132 masm.movptr(tmpReg, NULL_WORD) ;
3133 } else {
3134 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3135 // Test-And-CAS instead of CAS
3136 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3137 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3138 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3139 }
3140
3141 // Appears unlocked - try to swing _owner from null to non-null.
3142 // Ideally, I'd manifest "Self" with get_thread and then attempt
3143 // to CAS the register containing Self into m->Owner.
3144 // But we don't have enough registers, so instead we can either try to CAS
3145 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3146 // we later store "Self" into m->Owner. Transiently storing a stack address
3147 // (rsp or the address of the box) into m->owner is harmless.
3148 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3149 if (os::is_MP()) { masm.lock(); }
3150 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3151 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3152 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3153 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3154 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3155 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3156
3157 // If the CAS fails we can either retry or pass control to the slow-path.
3158 // We use the latter tactic.
3159 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3160 // If the CAS was successful ...
3161 // Self has acquired the lock
3162 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3163 // Intentional fall-through into DONE_LABEL ...
3164 } else {
3165 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3166 masm.movptr(boxReg, tmpReg) ;
3167
3168 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3169 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3170 // prefetchw [eax + Offset(_owner)-2]
3171 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3172 }
3173
3174 if ((EmitSync & 64) == 0) {
3175 // Optimistic form
3176 masm.xorptr (tmpReg, tmpReg) ;
3177 } else {
3178 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3179 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3180 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3181 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3182 }
3183
3184 // Appears unlocked - try to swing _owner from null to non-null.
3185 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3186 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3187 masm.get_thread (scrReg) ;
3188 if (os::is_MP()) { masm.lock(); }
3189 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3190
3191 // If the CAS fails we can either retry or pass control to the slow-path.
3192 // We use the latter tactic.
3193 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3194 // If the CAS was successful ...
3195 // Self has acquired the lock
3196 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3197 // Intentional fall-through into DONE_LABEL ...
3198 }
3199
3200 // DONE_LABEL is a hot target - we'd really like to place it at the
3201 // start of cache line by padding with NOPs.
3202 // See the AMD and Intel software optimization manuals for the
3203 // most efficient "long" NOP encodings.
3204 // Unfortunately none of our alignment mechanisms suffice.
3205 masm.bind(DONE_LABEL);
3206
3207 // Avoid branch-to-branch on AMD processors
3208 // This appears to be superstition.
3209 if (EmitSync & 32) masm.nop() ;
3210
3211
3212 // At DONE_LABEL the icc ZFlag is set as follows ...
3213 // Fast_Unlock uses the same protocol.
3214 // ZFlag == 1 -> Success
3215 // ZFlag == 0 -> Failure - force control through the slow-path
3216 }
3217 %}
3218
3219 // obj: object to unlock
3220 // box: box address (displaced header location), killed. Must be EAX.
3221 // rbx,: killed tmp; cannot be obj nor box.
3222 //
3223 // Some commentary on balanced locking:
3224 //
3225 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3226 // Methods that don't have provably balanced locking are forced to run in the
3227 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3228 // The interpreter provides two properties:
3229 // I1: At return-time the interpreter automatically and quietly unlocks any
3230 // objects acquired the current activation (frame). Recall that the
3231 // interpreter maintains an on-stack list of locks currently held by
3232 // a frame.
3233 // I2: If a method attempts to unlock an object that is not held by the
3234 // the frame the interpreter throws IMSX.
3235 //
3236 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3237 // B() doesn't have provably balanced locking so it runs in the interpreter.
3238 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3239 // is still locked by A().
3240 //
3241 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3242 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3243 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3244 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3245
3246 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3247
3248 Register objReg = as_Register($obj$$reg);
3249 Register boxReg = as_Register($box$$reg);
3250 Register tmpReg = as_Register($tmp$$reg);
3251
3252 guarantee (objReg != boxReg, "") ;
3253 guarantee (objReg != tmpReg, "") ;
3254 guarantee (boxReg != tmpReg, "") ;
3255 guarantee (boxReg == as_Register(EAX_enc), "") ;
3256 MacroAssembler masm(&cbuf);
3257
3258 if (EmitSync & 4) {
3259 // Disable - inhibit all inlining. Force control through the slow-path
3260 masm.cmpptr (rsp, 0) ;
3261 } else
3262 if (EmitSync & 8) {
3263 Label DONE_LABEL ;
3264 if (UseBiasedLocking) {
3265 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3266 }
3267 // classic stack-locking code ...
3268 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3269 masm.testptr(tmpReg, tmpReg) ;
3270 masm.jcc (Assembler::zero, DONE_LABEL) ;
3271 if (os::is_MP()) { masm.lock(); }
3272 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3273 masm.bind(DONE_LABEL);
3274 } else {
3275 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3276
3277 // Critically, the biased locking test must have precedence over
3278 // and appear before the (box->dhw == 0) recursive stack-lock test.
3279 if (UseBiasedLocking && !UseOptoBiasInlining) {
3280 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3281 }
3282
3283 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3284 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3285 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3286
3287 masm.testptr(tmpReg, 0x02) ; // Inflated?
3288 masm.jccb (Assembler::zero, Stacked) ;
3289
3290 masm.bind (Inflated) ;
3291 // It's inflated.
3292 // Despite our balanced locking property we still check that m->_owner == Self
3293 // as java routines or native JNI code called by this thread might
3294 // have released the lock.
3295 // Refer to the comments in synchronizer.cpp for how we might encode extra
3296 // state in _succ so we can avoid fetching EntryList|cxq.
3297 //
3298 // I'd like to add more cases in fast_lock() and fast_unlock() --
3299 // such as recursive enter and exit -- but we have to be wary of
3300 // I$ bloat, T$ effects and BP$ effects.
3301 //
3302 // If there's no contention try a 1-0 exit. That is, exit without
3303 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3304 // we detect and recover from the race that the 1-0 exit admits.
3305 //
3306 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3307 // before it STs null into _owner, releasing the lock. Updates
3308 // to data protected by the critical section must be visible before
3309 // we drop the lock (and thus before any other thread could acquire
3310 // the lock and observe the fields protected by the lock).
3311 // IA32's memory-model is SPO, so STs are ordered with respect to
3312 // each other and there's no need for an explicit barrier (fence).
3313 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3314
3315 masm.get_thread (boxReg) ;
3316 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3317 // prefetchw [ebx + Offset(_owner)-2]
3318 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3319 }
3320
3321 // Note that we could employ various encoding schemes to reduce
3322 // the number of loads below (currently 4) to just 2 or 3.
3323 // Refer to the comments in synchronizer.cpp.
3324 // In practice the chain of fetches doesn't seem to impact performance, however.
3325 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3326 // Attempt to reduce branch density - AMD's branch predictor.
3327 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3328 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3329 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3330 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3331 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3332 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3333 masm.jmpb (DONE_LABEL) ;
3334 } else {
3335 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3336 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3337 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3338 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3339 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3340 masm.jccb (Assembler::notZero, CheckSucc) ;
3341 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3342 masm.jmpb (DONE_LABEL) ;
3343 }
3344
3345 // The Following code fragment (EmitSync & 65536) improves the performance of
3346 // contended applications and contended synchronization microbenchmarks.
3347 // Unfortunately the emission of the code - even though not executed - causes regressions
3348 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3349 // with an equal number of never-executed NOPs results in the same regression.
3350 // We leave it off by default.
3351
3352 if ((EmitSync & 65536) != 0) {
3353 Label LSuccess, LGoSlowPath ;
3354
3355 masm.bind (CheckSucc) ;
3356
3357 // Optional pre-test ... it's safe to elide this
3358 if ((EmitSync & 16) == 0) {
3359 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3360 masm.jccb (Assembler::zero, LGoSlowPath) ;
3361 }
3362
3363 // We have a classic Dekker-style idiom:
3364 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3365 // There are a number of ways to implement the barrier:
3366 // (1) lock:andl &m->_owner, 0
3367 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3368 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3369 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3370 // (2) If supported, an explicit MFENCE is appealing.
3371 // In older IA32 processors MFENCE is slower than lock:add or xchg
3372 // particularly if the write-buffer is full as might be the case if
3373 // if stores closely precede the fence or fence-equivalent instruction.
3374 // In more modern implementations MFENCE appears faster, however.
3375 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3376 // The $lines underlying the top-of-stack should be in M-state.
3377 // The locked add instruction is serializing, of course.
3378 // (4) Use xchg, which is serializing
3379 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3380 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3381 // The integer condition codes will tell us if succ was 0.
3382 // Since _succ and _owner should reside in the same $line and
3383 // we just stored into _owner, it's likely that the $line
3384 // remains in M-state for the lock:orl.
3385 //
3386 // We currently use (3), although it's likely that switching to (2)
3387 // is correct for the future.
3388
3389 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3390 if (os::is_MP()) {
3391 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3392 masm.mfence();
3393 } else {
3394 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3395 }
3396 }
3397 // Ratify _succ remains non-null
3398 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3399 masm.jccb (Assembler::notZero, LSuccess) ;
3400
3401 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3402 if (os::is_MP()) { masm.lock(); }
3403 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3404 masm.jccb (Assembler::notEqual, LSuccess) ;
3405 // Since we're low on registers we installed rsp as a placeholding in _owner.
3406 // Now install Self over rsp. This is safe as we're transitioning from
3407 // non-null to non=null
3408 masm.get_thread (boxReg) ;
3409 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3410 // Intentional fall-through into LGoSlowPath ...
3411
3412 masm.bind (LGoSlowPath) ;
3413 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3414 masm.jmpb (DONE_LABEL) ;
3415
3416 masm.bind (LSuccess) ;
3417 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3418 masm.jmpb (DONE_LABEL) ;
3419 }
3420
3421 masm.bind (Stacked) ;
3422 // It's not inflated and it's not recursively stack-locked and it's not biased.
3423 // It must be stack-locked.
3424 // Try to reset the header to displaced header.
3425 // The "box" value on the stack is stable, so we can reload
3426 // and be assured we observe the same value as above.
3427 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3428 if (os::is_MP()) { masm.lock(); }
3429 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3430 // Intention fall-thru into DONE_LABEL
3431
3432
3433 // DONE_LABEL is a hot target - we'd really like to place it at the
3434 // start of cache line by padding with NOPs.
3435 // See the AMD and Intel software optimization manuals for the
3436 // most efficient "long" NOP encodings.
3437 // Unfortunately none of our alignment mechanisms suffice.
3438 if ((EmitSync & 65536) == 0) {
3439 masm.bind (CheckSucc) ;
3440 }
3441 masm.bind(DONE_LABEL);
3442
3443 // Avoid branch to branch on AMD processors
3444 if (EmitSync & 32768) { masm.nop() ; }
3445 }
3446 %}
3447
3448
3449 enc_class enc_pop_rdx() %{
3450 emit_opcode(cbuf,0x5A);
3451 %}
3452
3453 enc_class enc_rethrow() %{
3454 cbuf.set_insts_mark();
3455 emit_opcode(cbuf, 0xE9); // jmp entry
3456 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3457 runtime_call_Relocation::spec(), RELOC_IMM32 );
3458 %}
3459
3460
3461 // Convert a double to an int. Java semantics require we do complex
3462 // manglelations in the corner cases. So we set the rounding mode to
3463 // 'zero', store the darned double down as an int, and reset the
3464 // rounding mode to 'nearest'. The hardware throws an exception which
3465 // patches up the correct value directly to the stack.
3466 enc_class DPR2I_encoding( regDPR src ) %{
3467 // Flip to round-to-zero mode. We attempted to allow invalid-op
3468 // exceptions here, so that a NAN or other corner-case value will
3469 // thrown an exception (but normal values get converted at full speed).
3470 // However, I2C adapters and other float-stack manglers leave pending
3471 // invalid-op exceptions hanging. We would have to clear them before
3472 // enabling them and that is more expensive than just testing for the
3473 // invalid value Intel stores down in the corner cases.
3474 emit_opcode(cbuf,0xD9); // FLDCW trunc
3475 emit_opcode(cbuf,0x2D);
3476 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3477 // Allocate a word
3478 emit_opcode(cbuf,0x83); // SUB ESP,4
3479 emit_opcode(cbuf,0xEC);
3480 emit_d8(cbuf,0x04);
3481 // Encoding assumes a double has been pushed into FPR0.
3482 // Store down the double as an int, popping the FPU stack
3483 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3484 emit_opcode(cbuf,0x1C);
3485 emit_d8(cbuf,0x24);
3486 // Restore the rounding mode; mask the exception
3487 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3488 emit_opcode(cbuf,0x2D);
3489 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3490 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3491 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3492
3493 // Load the converted int; adjust CPU stack
3494 emit_opcode(cbuf,0x58); // POP EAX
3495 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3496 emit_d32 (cbuf,0x80000000); // 0x80000000
3497 emit_opcode(cbuf,0x75); // JNE around_slow_call
3498 emit_d8 (cbuf,0x07); // Size of slow_call
3499 // Push src onto stack slow-path
3500 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3501 emit_d8 (cbuf,0xC0-1+$src$$reg );
3502 // CALL directly to the runtime
3503 cbuf.set_insts_mark();
3504 emit_opcode(cbuf,0xE8); // Call into runtime
3505 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3506 // Carry on here...
3507 %}
3508
3509 enc_class DPR2L_encoding( regDPR src ) %{
3510 emit_opcode(cbuf,0xD9); // FLDCW trunc
3511 emit_opcode(cbuf,0x2D);
3512 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3513 // Allocate a word
3514 emit_opcode(cbuf,0x83); // SUB ESP,8
3515 emit_opcode(cbuf,0xEC);
3516 emit_d8(cbuf,0x08);
3517 // Encoding assumes a double has been pushed into FPR0.
3518 // Store down the double as a long, popping the FPU stack
3519 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3520 emit_opcode(cbuf,0x3C);
3521 emit_d8(cbuf,0x24);
3522 // Restore the rounding mode; mask the exception
3523 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3524 emit_opcode(cbuf,0x2D);
3525 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3526 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3527 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3528
3529 // Load the converted int; adjust CPU stack
3530 emit_opcode(cbuf,0x58); // POP EAX
3531 emit_opcode(cbuf,0x5A); // POP EDX
3532 emit_opcode(cbuf,0x81); // CMP EDX,imm
3533 emit_d8 (cbuf,0xFA); // rdx
3534 emit_d32 (cbuf,0x80000000); // 0x80000000
3535 emit_opcode(cbuf,0x75); // JNE around_slow_call
3536 emit_d8 (cbuf,0x07+4); // Size of slow_call
3537 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3538 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3539 emit_opcode(cbuf,0x75); // JNE around_slow_call
3540 emit_d8 (cbuf,0x07); // Size of slow_call
3541 // Push src onto stack slow-path
3542 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3543 emit_d8 (cbuf,0xC0-1+$src$$reg );
3544 // CALL directly to the runtime
3545 cbuf.set_insts_mark();
3546 emit_opcode(cbuf,0xE8); // Call into runtime
3547 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3548 // Carry on here...
3549 %}
3550
3551 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3552 // Operand was loaded from memory into fp ST (stack top)
3553 // FMUL ST,$src /* D8 C8+i */
3554 emit_opcode(cbuf, 0xD8);
3555 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3556 %}
3557
3558 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3559 // FADDP ST,src2 /* D8 C0+i */
3560 emit_opcode(cbuf, 0xD8);
3561 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3562 //could use FADDP src2,fpST /* DE C0+i */
3563 %}
3564
3565 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3566 // FADDP src2,ST /* DE C0+i */
3567 emit_opcode(cbuf, 0xDE);
3568 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3569 %}
3570
3571 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3572 // Operand has been loaded into fp ST (stack top)
3573 // FSUB ST,$src1
3574 emit_opcode(cbuf, 0xD8);
3575 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3576
3577 // FDIV
3578 emit_opcode(cbuf, 0xD8);
3579 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3580 %}
3581
3582 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3583 // Operand was loaded from memory into fp ST (stack top)
3584 // FADD ST,$src /* D8 C0+i */
3585 emit_opcode(cbuf, 0xD8);
3586 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3587
3588 // FMUL ST,src2 /* D8 C*+i */
3589 emit_opcode(cbuf, 0xD8);
3590 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3591 %}
3592
3593
3594 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3595 // Operand was loaded from memory into fp ST (stack top)
3596 // FADD ST,$src /* D8 C0+i */
3597 emit_opcode(cbuf, 0xD8);
3598 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3599
3600 // FMULP src2,ST /* DE C8+i */
3601 emit_opcode(cbuf, 0xDE);
3602 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3603 %}
3604
3605 // Atomically load the volatile long
3606 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3607 emit_opcode(cbuf,0xDF);
3608 int rm_byte_opcode = 0x05;
3609 int base = $mem$$base;
3610 int index = $mem$$index;
3611 int scale = $mem$$scale;
3612 int displace = $mem$$disp;
3613 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3614 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3615 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3616 %}
3617
3618 // Volatile Store Long. Must be atomic, so move it into
3619 // the FP TOS and then do a 64-bit FIST. Has to probe the
3620 // target address before the store (for null-ptr checks)
3621 // so the memory operand is used twice in the encoding.
3622 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3623 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3624 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3625 emit_opcode(cbuf,0xDF);
3626 int rm_byte_opcode = 0x07;
3627 int base = $mem$$base;
3628 int index = $mem$$index;
3629 int scale = $mem$$scale;
3630 int displace = $mem$$disp;
3631 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3632 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3633 %}
3634
3635 // Safepoint Poll. This polls the safepoint page, and causes an
3636 // exception if it is not readable. Unfortunately, it kills the condition code
3637 // in the process
3638 // We current use TESTL [spp],EDI
3639 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3640
3641 enc_class Safepoint_Poll() %{
3642 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3643 emit_opcode(cbuf,0x85);
3644 emit_rm (cbuf, 0x0, 0x7, 0x5);
3645 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3646 %}
3647 %}
3648
3649
3650 //----------FRAME--------------------------------------------------------------
3651 // Definition of frame structure and management information.
3652 //
3653 // S T A C K L A Y O U T Allocators stack-slot number
3654 // | (to get allocators register number
3655 // G Owned by | | v add OptoReg::stack0())
3656 // r CALLER | |
3657 // o | +--------+ pad to even-align allocators stack-slot
3658 // w V | pad0 | numbers; owned by CALLER
3659 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3660 // h ^ | in | 5
3661 // | | args | 4 Holes in incoming args owned by SELF
3662 // | | | | 3
3663 // | | +--------+
3664 // V | | old out| Empty on Intel, window on Sparc
3665 // | old |preserve| Must be even aligned.
3666 // | SP-+--------+----> Matcher::_old_SP, even aligned
3667 // | | in | 3 area for Intel ret address
3668 // Owned by |preserve| Empty on Sparc.
3669 // SELF +--------+
3670 // | | pad2 | 2 pad to align old SP
3671 // | +--------+ 1
3672 // | | locks | 0
3673 // | +--------+----> OptoReg::stack0(), even aligned
3674 // | | pad1 | 11 pad to align new SP
3675 // | +--------+
3676 // | | | 10
3677 // | | spills | 9 spills
3678 // V | | 8 (pad0 slot for callee)
3679 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3680 // ^ | out | 7
3681 // | | args | 6 Holes in outgoing args owned by CALLEE
3682 // Owned by +--------+
3683 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3684 // | new |preserve| Must be even-aligned.
3685 // | SP-+--------+----> Matcher::_new_SP, even aligned
3686 // | | |
3687 //
3688 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3689 // known from SELF's arguments and the Java calling convention.
3690 // Region 6-7 is determined per call site.
3691 // Note 2: If the calling convention leaves holes in the incoming argument
3692 // area, those holes are owned by SELF. Holes in the outgoing area
3693 // are owned by the CALLEE. Holes should not be nessecary in the
3694 // incoming area, as the Java calling convention is completely under
3695 // the control of the AD file. Doubles can be sorted and packed to
3696 // avoid holes. Holes in the outgoing arguments may be nessecary for
3697 // varargs C calling conventions.
3698 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3699 // even aligned with pad0 as needed.
3700 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3701 // region 6-11 is even aligned; it may be padded out more so that
3702 // the region from SP to FP meets the minimum stack alignment.
3703
3704 frame %{
3705 // What direction does stack grow in (assumed to be same for C & Java)
3706 stack_direction(TOWARDS_LOW);
3707
3708 // These three registers define part of the calling convention
3709 // between compiled code and the interpreter.
3710 inline_cache_reg(EAX); // Inline Cache Register
3711 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3712
3713 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3714 cisc_spilling_operand_name(indOffset32);
3715
3716 // Number of stack slots consumed by locking an object
3717 sync_stack_slots(1);
3718
3719 // Compiled code's Frame Pointer
3720 frame_pointer(ESP);
3721 // Interpreter stores its frame pointer in a register which is
3722 // stored to the stack by I2CAdaptors.
3723 // I2CAdaptors convert from interpreted java to compiled java.
3724 interpreter_frame_pointer(EBP);
3725
3726 // Stack alignment requirement
3727 // Alignment size in bytes (128-bit -> 16 bytes)
3728 stack_alignment(StackAlignmentInBytes);
3729
3730 // Number of stack slots between incoming argument block and the start of
3731 // a new frame. The PROLOG must add this many slots to the stack. The
3732 // EPILOG must remove this many slots. Intel needs one slot for
3733 // return address and one for rbp, (must save rbp)
3734 in_preserve_stack_slots(2+VerifyStackAtCalls);
3735
3736 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3737 // for calls to C. Supports the var-args backing area for register parms.
3738 varargs_C_out_slots_killed(0);
3739
3740 // The after-PROLOG location of the return address. Location of
3741 // return address specifies a type (REG or STACK) and a number
3742 // representing the register number (i.e. - use a register name) or
3743 // stack slot.
3744 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3745 // Otherwise, it is above the locks and verification slot and alignment word
3746 return_addr(STACK - 1 +
3747 round_to((Compile::current()->in_preserve_stack_slots() +
3748 Compile::current()->fixed_slots()),
3749 stack_alignment_in_slots()));
3750
3751 // Body of function which returns an integer array locating
3752 // arguments either in registers or in stack slots. Passed an array
3753 // of ideal registers called "sig" and a "length" count. Stack-slot
3754 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3755 // arguments for a CALLEE. Incoming stack arguments are
3756 // automatically biased by the preserve_stack_slots field above.
3757 calling_convention %{
3758 // No difference between ingoing/outgoing just pass false
3759 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3760 %}
3761
3762
3763 // Body of function which returns an integer array locating
3764 // arguments either in registers or in stack slots. Passed an array
3765 // of ideal registers called "sig" and a "length" count. Stack-slot
3766 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3767 // arguments for a CALLEE. Incoming stack arguments are
3768 // automatically biased by the preserve_stack_slots field above.
3769 c_calling_convention %{
3770 // This is obviously always outgoing
3771 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3772 %}
3773
3774 // Location of C & interpreter return values
3775 c_return_value %{
3776 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3777 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3778 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3779
3780 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3781 // that C functions return float and double results in XMM0.
3782 if( ideal_reg == Op_RegD && UseSSE>=2 )
3783 return OptoRegPair(XMM0b_num,XMM0_num);
3784 if( ideal_reg == Op_RegF && UseSSE>=2 )
3785 return OptoRegPair(OptoReg::Bad,XMM0_num);
3786
3787 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3788 %}
3789
3790 // Location of return values
3791 return_value %{
3792 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3793 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3794 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3795 if( ideal_reg == Op_RegD && UseSSE>=2 )
3796 return OptoRegPair(XMM0b_num,XMM0_num);
3797 if( ideal_reg == Op_RegF && UseSSE>=1 )
3798 return OptoRegPair(OptoReg::Bad,XMM0_num);
3799 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3800 %}
3801
3802 %}
3803
3804 //----------ATTRIBUTES---------------------------------------------------------
3805 //----------Operand Attributes-------------------------------------------------
3806 op_attrib op_cost(0); // Required cost attribute
3807
3808 //----------Instruction Attributes---------------------------------------------
3809 ins_attrib ins_cost(100); // Required cost attribute
3810 ins_attrib ins_size(8); // Required size attribute (in bits)
3811 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3812 // non-matching short branch variant of some
3813 // long branch?
3814 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3815 // specifies the alignment that some part of the instruction (not
3816 // necessarily the start) requires. If > 1, a compute_padding()
3817 // function must be provided for the instruction
3818
3819 //----------OPERANDS-----------------------------------------------------------
3820 // Operand definitions must precede instruction definitions for correct parsing
3821 // in the ADLC because operands constitute user defined types which are used in
3822 // instruction definitions.
3823
3824 //----------Simple Operands----------------------------------------------------
3825 // Immediate Operands
3826 // Integer Immediate
3827 operand immI() %{
3828 match(ConI);
3829
3830 op_cost(10);
3831 format %{ %}
3832 interface(CONST_INTER);
3833 %}
3834
3835 // Constant for test vs zero
3836 operand immI0() %{
3837 predicate(n->get_int() == 0);
3838 match(ConI);
3839
3840 op_cost(0);
3841 format %{ %}
3842 interface(CONST_INTER);
3843 %}
3844
3845 // Constant for increment
3846 operand immI1() %{
3847 predicate(n->get_int() == 1);
3848 match(ConI);
3849
3850 op_cost(0);
3851 format %{ %}
3852 interface(CONST_INTER);
3853 %}
3854
3855 // Constant for decrement
3856 operand immI_M1() %{
3857 predicate(n->get_int() == -1);
3858 match(ConI);
3859
3860 op_cost(0);
3861 format %{ %}
3862 interface(CONST_INTER);
3863 %}
3864
3865 // Valid scale values for addressing modes
3866 operand immI2() %{
3867 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3868 match(ConI);
3869
3870 format %{ %}
3871 interface(CONST_INTER);
3872 %}
3873
3874 operand immI8() %{
3875 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3876 match(ConI);
3877
3878 op_cost(5);
3879 format %{ %}
3880 interface(CONST_INTER);
3881 %}
3882
3883 operand immI16() %{
3884 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3885 match(ConI);
3886
3887 op_cost(10);
3888 format %{ %}
3889 interface(CONST_INTER);
3890 %}
3891
3892 // Int Immediate positive
3893 operand immU32()
3894 %{
3895 predicate(n->get_int() >= 0);
3896 match(ConI);
3897
3898 op_cost(0);
3899 format %{ %}
3900 interface(CONST_INTER);
3901 %}
3902
3903 // Constant for long shifts
3904 operand immI_32() %{
3905 predicate( n->get_int() == 32 );
3906 match(ConI);
3907
3908 op_cost(0);
3909 format %{ %}
3910 interface(CONST_INTER);
3911 %}
3912
3913 operand immI_1_31() %{
3914 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3915 match(ConI);
3916
3917 op_cost(0);
3918 format %{ %}
3919 interface(CONST_INTER);
3920 %}
3921
3922 operand immI_32_63() %{
3923 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3924 match(ConI);
3925 op_cost(0);
3926
3927 format %{ %}
3928 interface(CONST_INTER);
3929 %}
3930
3931 operand immI_1() %{
3932 predicate( n->get_int() == 1 );
3933 match(ConI);
3934
3935 op_cost(0);
3936 format %{ %}
3937 interface(CONST_INTER);
3938 %}
3939
3940 operand immI_2() %{
3941 predicate( n->get_int() == 2 );
3942 match(ConI);
3943
3944 op_cost(0);
3945 format %{ %}
3946 interface(CONST_INTER);
3947 %}
3948
3949 operand immI_3() %{
3950 predicate( n->get_int() == 3 );
3951 match(ConI);
3952
3953 op_cost(0);
3954 format %{ %}
3955 interface(CONST_INTER);
3956 %}
3957
3958 // Pointer Immediate
3959 operand immP() %{
3960 match(ConP);
3961
3962 op_cost(10);
3963 format %{ %}
3964 interface(CONST_INTER);
3965 %}
3966
3967 // NULL Pointer Immediate
3968 operand immP0() %{
3969 predicate( n->get_ptr() == 0 );
3970 match(ConP);
3971 op_cost(0);
3972
3973 format %{ %}
3974 interface(CONST_INTER);
3975 %}
3976
3977 // Long Immediate
3978 operand immL() %{
3979 match(ConL);
3980
3981 op_cost(20);
3982 format %{ %}
3983 interface(CONST_INTER);
3984 %}
3985
3986 // Long Immediate zero
3987 operand immL0() %{
3988 predicate( n->get_long() == 0L );
3989 match(ConL);
3990 op_cost(0);
3991
3992 format %{ %}
3993 interface(CONST_INTER);
3994 %}
3995
3996 // Long Immediate zero
3997 operand immL_M1() %{
3998 predicate( n->get_long() == -1L );
3999 match(ConL);
4000 op_cost(0);
4001
4002 format %{ %}
4003 interface(CONST_INTER);
4004 %}
4005
4006 // Long immediate from 0 to 127.
4007 // Used for a shorter form of long mul by 10.
4008 operand immL_127() %{
4009 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4010 match(ConL);
4011 op_cost(0);
4012
4013 format %{ %}
4014 interface(CONST_INTER);
4015 %}
4016
4017 // Long Immediate: low 32-bit mask
4018 operand immL_32bits() %{
4019 predicate(n->get_long() == 0xFFFFFFFFL);
4020 match(ConL);
4021 op_cost(0);
4022
4023 format %{ %}
4024 interface(CONST_INTER);
4025 %}
4026
4027 // Long Immediate: low 32-bit mask
4028 operand immL32() %{
4029 predicate(n->get_long() == (int)(n->get_long()));
4030 match(ConL);
4031 op_cost(20);
4032
4033 format %{ %}
4034 interface(CONST_INTER);
4035 %}
4036
4037 //Double Immediate zero
4038 operand immDPR0() %{
4039 // Do additional (and counter-intuitive) test against NaN to work around VC++
4040 // bug that generates code such that NaNs compare equal to 0.0
4041 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4042 match(ConD);
4043
4044 op_cost(5);
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4048
4049 // Double Immediate one
4050 operand immDPR1() %{
4051 predicate( UseSSE<=1 && n->getd() == 1.0 );
4052 match(ConD);
4053
4054 op_cost(5);
4055 format %{ %}
4056 interface(CONST_INTER);
4057 %}
4058
4059 // Double Immediate
4060 operand immDPR() %{
4061 predicate(UseSSE<=1);
4062 match(ConD);
4063
4064 op_cost(5);
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4068
4069 operand immD() %{
4070 predicate(UseSSE>=2);
4071 match(ConD);
4072
4073 op_cost(5);
4074 format %{ %}
4075 interface(CONST_INTER);
4076 %}
4077
4078 // Double Immediate zero
4079 operand immD0() %{
4080 // Do additional (and counter-intuitive) test against NaN to work around VC++
4081 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4082 // compare equal to -0.0.
4083 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4084 match(ConD);
4085
4086 format %{ %}
4087 interface(CONST_INTER);
4088 %}
4089
4090 // Float Immediate zero
4091 operand immFPR0() %{
4092 predicate(UseSSE == 0 && n->getf() == 0.0F);
4093 match(ConF);
4094
4095 op_cost(5);
4096 format %{ %}
4097 interface(CONST_INTER);
4098 %}
4099
4100 // Float Immediate one
4101 operand immFPR1() %{
4102 predicate(UseSSE == 0 && n->getf() == 1.0F);
4103 match(ConF);
4104
4105 op_cost(5);
4106 format %{ %}
4107 interface(CONST_INTER);
4108 %}
4109
4110 // Float Immediate
4111 operand immFPR() %{
4112 predicate( UseSSE == 0 );
4113 match(ConF);
4114
4115 op_cost(5);
4116 format %{ %}
4117 interface(CONST_INTER);
4118 %}
4119
4120 // Float Immediate
4121 operand immF() %{
4122 predicate(UseSSE >= 1);
4123 match(ConF);
4124
4125 op_cost(5);
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4129
4130 // Float Immediate zero. Zero and not -0.0
4131 operand immF0() %{
4132 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4133 match(ConF);
4134
4135 op_cost(5);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Immediates for special shifts (sign extend)
4141
4142 // Constants for increment
4143 operand immI_16() %{
4144 predicate( n->get_int() == 16 );
4145 match(ConI);
4146
4147 format %{ %}
4148 interface(CONST_INTER);
4149 %}
4150
4151 operand immI_24() %{
4152 predicate( n->get_int() == 24 );
4153 match(ConI);
4154
4155 format %{ %}
4156 interface(CONST_INTER);
4157 %}
4158
4159 // Constant for byte-wide masking
4160 operand immI_255() %{
4161 predicate( n->get_int() == 255 );
4162 match(ConI);
4163
4164 format %{ %}
4165 interface(CONST_INTER);
4166 %}
4167
4168 // Constant for short-wide masking
4169 operand immI_65535() %{
4170 predicate(n->get_int() == 65535);
4171 match(ConI);
4172
4173 format %{ %}
4174 interface(CONST_INTER);
4175 %}
4176
4177 // Register Operands
4178 // Integer Register
4179 operand rRegI() %{
4180 constraint(ALLOC_IN_RC(int_reg));
4181 match(RegI);
4182 match(xRegI);
4183 match(eAXRegI);
4184 match(eBXRegI);
4185 match(eCXRegI);
4186 match(eDXRegI);
4187 match(eDIRegI);
4188 match(eSIRegI);
4189
4190 format %{ %}
4191 interface(REG_INTER);
4192 %}
4193
4194 // Subset of Integer Register
4195 operand xRegI(rRegI reg) %{
4196 constraint(ALLOC_IN_RC(int_x_reg));
4197 match(reg);
4198 match(eAXRegI);
4199 match(eBXRegI);
4200 match(eCXRegI);
4201 match(eDXRegI);
4202
4203 format %{ %}
4204 interface(REG_INTER);
4205 %}
4206
4207 // Special Registers
4208 operand eAXRegI(xRegI reg) %{
4209 constraint(ALLOC_IN_RC(eax_reg));
4210 match(reg);
4211 match(rRegI);
4212
4213 format %{ "EAX" %}
4214 interface(REG_INTER);
4215 %}
4216
4217 // Special Registers
4218 operand eBXRegI(xRegI reg) %{
4219 constraint(ALLOC_IN_RC(ebx_reg));
4220 match(reg);
4221 match(rRegI);
4222
4223 format %{ "EBX" %}
4224 interface(REG_INTER);
4225 %}
4226
4227 operand eCXRegI(xRegI reg) %{
4228 constraint(ALLOC_IN_RC(ecx_reg));
4229 match(reg);
4230 match(rRegI);
4231
4232 format %{ "ECX" %}
4233 interface(REG_INTER);
4234 %}
4235
4236 operand eDXRegI(xRegI reg) %{
4237 constraint(ALLOC_IN_RC(edx_reg));
4238 match(reg);
4239 match(rRegI);
4240
4241 format %{ "EDX" %}
4242 interface(REG_INTER);
4243 %}
4244
4245 operand eDIRegI(xRegI reg) %{
4246 constraint(ALLOC_IN_RC(edi_reg));
4247 match(reg);
4248 match(rRegI);
4249
4250 format %{ "EDI" %}
4251 interface(REG_INTER);
4252 %}
4253
4254 operand naxRegI() %{
4255 constraint(ALLOC_IN_RC(nax_reg));
4256 match(RegI);
4257 match(eCXRegI);
4258 match(eDXRegI);
4259 match(eSIRegI);
4260 match(eDIRegI);
4261
4262 format %{ %}
4263 interface(REG_INTER);
4264 %}
4265
4266 operand nadxRegI() %{
4267 constraint(ALLOC_IN_RC(nadx_reg));
4268 match(RegI);
4269 match(eBXRegI);
4270 match(eCXRegI);
4271 match(eSIRegI);
4272 match(eDIRegI);
4273
4274 format %{ %}
4275 interface(REG_INTER);
4276 %}
4277
4278 operand ncxRegI() %{
4279 constraint(ALLOC_IN_RC(ncx_reg));
4280 match(RegI);
4281 match(eAXRegI);
4282 match(eDXRegI);
4283 match(eSIRegI);
4284 match(eDIRegI);
4285
4286 format %{ %}
4287 interface(REG_INTER);
4288 %}
4289
4290 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4291 // //
4292 operand eSIRegI(xRegI reg) %{
4293 constraint(ALLOC_IN_RC(esi_reg));
4294 match(reg);
4295 match(rRegI);
4296
4297 format %{ "ESI" %}
4298 interface(REG_INTER);
4299 %}
4300
4301 // Pointer Register
4302 operand anyRegP() %{
4303 constraint(ALLOC_IN_RC(any_reg));
4304 match(RegP);
4305 match(eAXRegP);
4306 match(eBXRegP);
4307 match(eCXRegP);
4308 match(eDIRegP);
4309 match(eRegP);
4310
4311 format %{ %}
4312 interface(REG_INTER);
4313 %}
4314
4315 operand eRegP() %{
4316 constraint(ALLOC_IN_RC(int_reg));
4317 match(RegP);
4318 match(eAXRegP);
4319 match(eBXRegP);
4320 match(eCXRegP);
4321 match(eDIRegP);
4322
4323 format %{ %}
4324 interface(REG_INTER);
4325 %}
4326
4327 // On windows95, EBP is not safe to use for implicit null tests.
4328 operand eRegP_no_EBP() %{
4329 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4330 match(RegP);
4331 match(eAXRegP);
4332 match(eBXRegP);
4333 match(eCXRegP);
4334 match(eDIRegP);
4335
4336 op_cost(100);
4337 format %{ %}
4338 interface(REG_INTER);
4339 %}
4340
4341 operand naxRegP() %{
4342 constraint(ALLOC_IN_RC(nax_reg));
4343 match(RegP);
4344 match(eBXRegP);
4345 match(eDXRegP);
4346 match(eCXRegP);
4347 match(eSIRegP);
4348 match(eDIRegP);
4349
4350 format %{ %}
4351 interface(REG_INTER);
4352 %}
4353
4354 operand nabxRegP() %{
4355 constraint(ALLOC_IN_RC(nabx_reg));
4356 match(RegP);
4357 match(eCXRegP);
4358 match(eDXRegP);
4359 match(eSIRegP);
4360 match(eDIRegP);
4361
4362 format %{ %}
4363 interface(REG_INTER);
4364 %}
4365
4366 operand pRegP() %{
4367 constraint(ALLOC_IN_RC(p_reg));
4368 match(RegP);
4369 match(eBXRegP);
4370 match(eDXRegP);
4371 match(eSIRegP);
4372 match(eDIRegP);
4373
4374 format %{ %}
4375 interface(REG_INTER);
4376 %}
4377
4378 // Special Registers
4379 // Return a pointer value
4380 operand eAXRegP(eRegP reg) %{
4381 constraint(ALLOC_IN_RC(eax_reg));
4382 match(reg);
4383 format %{ "EAX" %}
4384 interface(REG_INTER);
4385 %}
4386
4387 // Used in AtomicAdd
4388 operand eBXRegP(eRegP reg) %{
4389 constraint(ALLOC_IN_RC(ebx_reg));
4390 match(reg);
4391 format %{ "EBX" %}
4392 interface(REG_INTER);
4393 %}
4394
4395 // Tail-call (interprocedural jump) to interpreter
4396 operand eCXRegP(eRegP reg) %{
4397 constraint(ALLOC_IN_RC(ecx_reg));
4398 match(reg);
4399 format %{ "ECX" %}
4400 interface(REG_INTER);
4401 %}
4402
4403 operand eSIRegP(eRegP reg) %{
4404 constraint(ALLOC_IN_RC(esi_reg));
4405 match(reg);
4406 format %{ "ESI" %}
4407 interface(REG_INTER);
4408 %}
4409
4410 // Used in rep stosw
4411 operand eDIRegP(eRegP reg) %{
4412 constraint(ALLOC_IN_RC(edi_reg));
4413 match(reg);
4414 format %{ "EDI" %}
4415 interface(REG_INTER);
4416 %}
4417
4418 operand eBPRegP() %{
4419 constraint(ALLOC_IN_RC(ebp_reg));
4420 match(RegP);
4421 format %{ "EBP" %}
4422 interface(REG_INTER);
4423 %}
4424
4425 operand eRegL() %{
4426 constraint(ALLOC_IN_RC(long_reg));
4427 match(RegL);
4428 match(eADXRegL);
4429
4430 format %{ %}
4431 interface(REG_INTER);
4432 %}
4433
4434 operand eADXRegL( eRegL reg ) %{
4435 constraint(ALLOC_IN_RC(eadx_reg));
4436 match(reg);
4437
4438 format %{ "EDX:EAX" %}
4439 interface(REG_INTER);
4440 %}
4441
4442 operand eBCXRegL( eRegL reg ) %{
4443 constraint(ALLOC_IN_RC(ebcx_reg));
4444 match(reg);
4445
4446 format %{ "EBX:ECX" %}
4447 interface(REG_INTER);
4448 %}
4449
4450 // Special case for integer high multiply
4451 operand eADXRegL_low_only() %{
4452 constraint(ALLOC_IN_RC(eadx_reg));
4453 match(RegL);
4454
4455 format %{ "EAX" %}
4456 interface(REG_INTER);
4457 %}
4458
4459 // Flags register, used as output of compare instructions
4460 operand eFlagsReg() %{
4461 constraint(ALLOC_IN_RC(int_flags));
4462 match(RegFlags);
4463
4464 format %{ "EFLAGS" %}
4465 interface(REG_INTER);
4466 %}
4467
4468 // Flags register, used as output of FLOATING POINT compare instructions
4469 operand eFlagsRegU() %{
4470 constraint(ALLOC_IN_RC(int_flags));
4471 match(RegFlags);
4472
4473 format %{ "EFLAGS_U" %}
4474 interface(REG_INTER);
4475 %}
4476
4477 operand eFlagsRegUCF() %{
4478 constraint(ALLOC_IN_RC(int_flags));
4479 match(RegFlags);
4480 predicate(false);
4481
4482 format %{ "EFLAGS_U_CF" %}
4483 interface(REG_INTER);
4484 %}
4485
4486 // Condition Code Register used by long compare
4487 operand flagsReg_long_LTGE() %{
4488 constraint(ALLOC_IN_RC(int_flags));
4489 match(RegFlags);
4490 format %{ "FLAGS_LTGE" %}
4491 interface(REG_INTER);
4492 %}
4493 operand flagsReg_long_EQNE() %{
4494 constraint(ALLOC_IN_RC(int_flags));
4495 match(RegFlags);
4496 format %{ "FLAGS_EQNE" %}
4497 interface(REG_INTER);
4498 %}
4499 operand flagsReg_long_LEGT() %{
4500 constraint(ALLOC_IN_RC(int_flags));
4501 match(RegFlags);
4502 format %{ "FLAGS_LEGT" %}
4503 interface(REG_INTER);
4504 %}
4505
4506 // Float register operands
4507 operand regDPR() %{
4508 predicate( UseSSE < 2 );
4509 constraint(ALLOC_IN_RC(fp_dbl_reg));
4510 match(RegD);
4511 match(regDPR1);
4512 match(regDPR2);
4513 format %{ %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand regDPR1(regDPR reg) %{
4518 predicate( UseSSE < 2 );
4519 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4520 match(reg);
4521 format %{ "FPR1" %}
4522 interface(REG_INTER);
4523 %}
4524
4525 operand regDPR2(regDPR reg) %{
4526 predicate( UseSSE < 2 );
4527 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4528 match(reg);
4529 format %{ "FPR2" %}
4530 interface(REG_INTER);
4531 %}
4532
4533 operand regnotDPR1(regDPR reg) %{
4534 predicate( UseSSE < 2 );
4535 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4536 match(reg);
4537 format %{ %}
4538 interface(REG_INTER);
4539 %}
4540
4541 // Float register operands
4542 operand regFPR() %{
4543 predicate( UseSSE < 2 );
4544 constraint(ALLOC_IN_RC(fp_flt_reg));
4545 match(RegF);
4546 match(regFPR1);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4550
4551 // Float register operands
4552 operand regFPR1(regFPR reg) %{
4553 predicate( UseSSE < 2 );
4554 constraint(ALLOC_IN_RC(fp_flt_reg0));
4555 match(reg);
4556 format %{ "FPR1" %}
4557 interface(REG_INTER);
4558 %}
4559
4560 // XMM Float register operands
4561 operand regF() %{
4562 predicate( UseSSE>=1 );
4563 constraint(ALLOC_IN_RC(float_reg));
4564 match(RegF);
4565 format %{ %}
4566 interface(REG_INTER);
4567 %}
4568
4569 // XMM Double register operands
4570 operand regD() %{
4571 predicate( UseSSE>=2 );
4572 constraint(ALLOC_IN_RC(double_reg));
4573 match(RegD);
4574 format %{ %}
4575 interface(REG_INTER);
4576 %}
4577
4578
4579 //----------Memory Operands----------------------------------------------------
4580 // Direct Memory Operand
4581 operand direct(immP addr) %{
4582 match(addr);
4583
4584 format %{ "[$addr]" %}
4585 interface(MEMORY_INTER) %{
4586 base(0xFFFFFFFF);
4587 index(0x4);
4588 scale(0x0);
4589 disp($addr);
4590 %}
4591 %}
4592
4593 // Indirect Memory Operand
4594 operand indirect(eRegP reg) %{
4595 constraint(ALLOC_IN_RC(int_reg));
4596 match(reg);
4597
4598 format %{ "[$reg]" %}
4599 interface(MEMORY_INTER) %{
4600 base($reg);
4601 index(0x4);
4602 scale(0x0);
4603 disp(0x0);
4604 %}
4605 %}
4606
4607 // Indirect Memory Plus Short Offset Operand
4608 operand indOffset8(eRegP reg, immI8 off) %{
4609 match(AddP reg off);
4610
4611 format %{ "[$reg + $off]" %}
4612 interface(MEMORY_INTER) %{
4613 base($reg);
4614 index(0x4);
4615 scale(0x0);
4616 disp($off);
4617 %}
4618 %}
4619
4620 // Indirect Memory Plus Long Offset Operand
4621 operand indOffset32(eRegP reg, immI off) %{
4622 match(AddP reg off);
4623
4624 format %{ "[$reg + $off]" %}
4625 interface(MEMORY_INTER) %{
4626 base($reg);
4627 index(0x4);
4628 scale(0x0);
4629 disp($off);
4630 %}
4631 %}
4632
4633 // Indirect Memory Plus Long Offset Operand
4634 operand indOffset32X(rRegI reg, immP off) %{
4635 match(AddP off reg);
4636
4637 format %{ "[$reg + $off]" %}
4638 interface(MEMORY_INTER) %{
4639 base($reg);
4640 index(0x4);
4641 scale(0x0);
4642 disp($off);
4643 %}
4644 %}
4645
4646 // Indirect Memory Plus Index Register Plus Offset Operand
4647 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4648 match(AddP (AddP reg ireg) off);
4649
4650 op_cost(10);
4651 format %{"[$reg + $off + $ireg]" %}
4652 interface(MEMORY_INTER) %{
4653 base($reg);
4654 index($ireg);
4655 scale(0x0);
4656 disp($off);
4657 %}
4658 %}
4659
4660 // Indirect Memory Plus Index Register Plus Offset Operand
4661 operand indIndex(eRegP reg, rRegI ireg) %{
4662 match(AddP reg ireg);
4663
4664 op_cost(10);
4665 format %{"[$reg + $ireg]" %}
4666 interface(MEMORY_INTER) %{
4667 base($reg);
4668 index($ireg);
4669 scale(0x0);
4670 disp(0x0);
4671 %}
4672 %}
4673
4674 // // -------------------------------------------------------------------------
4675 // // 486 architecture doesn't support "scale * index + offset" with out a base
4676 // // -------------------------------------------------------------------------
4677 // // Scaled Memory Operands
4678 // // Indirect Memory Times Scale Plus Offset Operand
4679 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4680 // match(AddP off (LShiftI ireg scale));
4681 //
4682 // op_cost(10);
4683 // format %{"[$off + $ireg << $scale]" %}
4684 // interface(MEMORY_INTER) %{
4685 // base(0x4);
4686 // index($ireg);
4687 // scale($scale);
4688 // disp($off);
4689 // %}
4690 // %}
4691
4692 // Indirect Memory Times Scale Plus Index Register
4693 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4694 match(AddP reg (LShiftI ireg scale));
4695
4696 op_cost(10);
4697 format %{"[$reg + $ireg << $scale]" %}
4698 interface(MEMORY_INTER) %{
4699 base($reg);
4700 index($ireg);
4701 scale($scale);
4702 disp(0x0);
4703 %}
4704 %}
4705
4706 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4707 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4708 match(AddP (AddP reg (LShiftI ireg scale)) off);
4709
4710 op_cost(10);
4711 format %{"[$reg + $off + $ireg << $scale]" %}
4712 interface(MEMORY_INTER) %{
4713 base($reg);
4714 index($ireg);
4715 scale($scale);
4716 disp($off);
4717 %}
4718 %}
4719
4720 //----------Load Long Memory Operands------------------------------------------
4721 // The load-long idiom will use it's address expression again after loading
4722 // the first word of the long. If the load-long destination overlaps with
4723 // registers used in the addressing expression, the 2nd half will be loaded
4724 // from a clobbered address. Fix this by requiring that load-long use
4725 // address registers that do not overlap with the load-long target.
4726
4727 // load-long support
4728 operand load_long_RegP() %{
4729 constraint(ALLOC_IN_RC(esi_reg));
4730 match(RegP);
4731 match(eSIRegP);
4732 op_cost(100);
4733 format %{ %}
4734 interface(REG_INTER);
4735 %}
4736
4737 // Indirect Memory Operand Long
4738 operand load_long_indirect(load_long_RegP reg) %{
4739 constraint(ALLOC_IN_RC(esi_reg));
4740 match(reg);
4741
4742 format %{ "[$reg]" %}
4743 interface(MEMORY_INTER) %{
4744 base($reg);
4745 index(0x4);
4746 scale(0x0);
4747 disp(0x0);
4748 %}
4749 %}
4750
4751 // Indirect Memory Plus Long Offset Operand
4752 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4753 match(AddP reg off);
4754
4755 format %{ "[$reg + $off]" %}
4756 interface(MEMORY_INTER) %{
4757 base($reg);
4758 index(0x4);
4759 scale(0x0);
4760 disp($off);
4761 %}
4762 %}
4763
4764 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4765
4766
4767 //----------Special Memory Operands--------------------------------------------
4768 // Stack Slot Operand - This operand is used for loading and storing temporary
4769 // values on the stack where a match requires a value to
4770 // flow through memory.
4771 operand stackSlotP(sRegP reg) %{
4772 constraint(ALLOC_IN_RC(stack_slots));
4773 // No match rule because this operand is only generated in matching
4774 format %{ "[$reg]" %}
4775 interface(MEMORY_INTER) %{
4776 base(0x4); // ESP
4777 index(0x4); // No Index
4778 scale(0x0); // No Scale
4779 disp($reg); // Stack Offset
4780 %}
4781 %}
4782
4783 operand stackSlotI(sRegI reg) %{
4784 constraint(ALLOC_IN_RC(stack_slots));
4785 // No match rule because this operand is only generated in matching
4786 format %{ "[$reg]" %}
4787 interface(MEMORY_INTER) %{
4788 base(0x4); // ESP
4789 index(0x4); // No Index
4790 scale(0x0); // No Scale
4791 disp($reg); // Stack Offset
4792 %}
4793 %}
4794
4795 operand stackSlotF(sRegF reg) %{
4796 constraint(ALLOC_IN_RC(stack_slots));
4797 // No match rule because this operand is only generated in matching
4798 format %{ "[$reg]" %}
4799 interface(MEMORY_INTER) %{
4800 base(0x4); // ESP
4801 index(0x4); // No Index
4802 scale(0x0); // No Scale
4803 disp($reg); // Stack Offset
4804 %}
4805 %}
4806
4807 operand stackSlotD(sRegD reg) %{
4808 constraint(ALLOC_IN_RC(stack_slots));
4809 // No match rule because this operand is only generated in matching
4810 format %{ "[$reg]" %}
4811 interface(MEMORY_INTER) %{
4812 base(0x4); // ESP
4813 index(0x4); // No Index
4814 scale(0x0); // No Scale
4815 disp($reg); // Stack Offset
4816 %}
4817 %}
4818
4819 operand stackSlotL(sRegL reg) %{
4820 constraint(ALLOC_IN_RC(stack_slots));
4821 // No match rule because this operand is only generated in matching
4822 format %{ "[$reg]" %}
4823 interface(MEMORY_INTER) %{
4824 base(0x4); // ESP
4825 index(0x4); // No Index
4826 scale(0x0); // No Scale
4827 disp($reg); // Stack Offset
4828 %}
4829 %}
4830
4831 //----------Memory Operands - Win95 Implicit Null Variants----------------
4832 // Indirect Memory Operand
4833 operand indirect_win95_safe(eRegP_no_EBP reg)
4834 %{
4835 constraint(ALLOC_IN_RC(int_reg));
4836 match(reg);
4837
4838 op_cost(100);
4839 format %{ "[$reg]" %}
4840 interface(MEMORY_INTER) %{
4841 base($reg);
4842 index(0x4);
4843 scale(0x0);
4844 disp(0x0);
4845 %}
4846 %}
4847
4848 // Indirect Memory Plus Short Offset Operand
4849 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4850 %{
4851 match(AddP reg off);
4852
4853 op_cost(100);
4854 format %{ "[$reg + $off]" %}
4855 interface(MEMORY_INTER) %{
4856 base($reg);
4857 index(0x4);
4858 scale(0x0);
4859 disp($off);
4860 %}
4861 %}
4862
4863 // Indirect Memory Plus Long Offset Operand
4864 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4865 %{
4866 match(AddP reg off);
4867
4868 op_cost(100);
4869 format %{ "[$reg + $off]" %}
4870 interface(MEMORY_INTER) %{
4871 base($reg);
4872 index(0x4);
4873 scale(0x0);
4874 disp($off);
4875 %}
4876 %}
4877
4878 // Indirect Memory Plus Index Register Plus Offset Operand
4879 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4880 %{
4881 match(AddP (AddP reg ireg) off);
4882
4883 op_cost(100);
4884 format %{"[$reg + $off + $ireg]" %}
4885 interface(MEMORY_INTER) %{
4886 base($reg);
4887 index($ireg);
4888 scale(0x0);
4889 disp($off);
4890 %}
4891 %}
4892
4893 // Indirect Memory Times Scale Plus Index Register
4894 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4895 %{
4896 match(AddP reg (LShiftI ireg scale));
4897
4898 op_cost(100);
4899 format %{"[$reg + $ireg << $scale]" %}
4900 interface(MEMORY_INTER) %{
4901 base($reg);
4902 index($ireg);
4903 scale($scale);
4904 disp(0x0);
4905 %}
4906 %}
4907
4908 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4909 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4910 %{
4911 match(AddP (AddP reg (LShiftI ireg scale)) off);
4912
4913 op_cost(100);
4914 format %{"[$reg + $off + $ireg << $scale]" %}
4915 interface(MEMORY_INTER) %{
4916 base($reg);
4917 index($ireg);
4918 scale($scale);
4919 disp($off);
4920 %}
4921 %}
4922
4923 //----------Conditional Branch Operands----------------------------------------
4924 // Comparison Op - This is the operation of the comparison, and is limited to
4925 // the following set of codes:
4926 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4927 //
4928 // Other attributes of the comparison, such as unsignedness, are specified
4929 // by the comparison instruction that sets a condition code flags register.
4930 // That result is represented by a flags operand whose subtype is appropriate
4931 // to the unsignedness (etc.) of the comparison.
4932 //
4933 // Later, the instruction which matches both the Comparison Op (a Bool) and
4934 // the flags (produced by the Cmp) specifies the coding of the comparison op
4935 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4936
4937 // Comparision Code
4938 operand cmpOp() %{
4939 match(Bool);
4940
4941 format %{ "" %}
4942 interface(COND_INTER) %{
4943 equal(0x4, "e");
4944 not_equal(0x5, "ne");
4945 less(0xC, "l");
4946 greater_equal(0xD, "ge");
4947 less_equal(0xE, "le");
4948 greater(0xF, "g");
4949 overflow(0x0, "o");
4950 no_overflow(0x1, "no");
4951 %}
4952 %}
4953
4954 // Comparison Code, unsigned compare. Used by FP also, with
4955 // C2 (unordered) turned into GT or LT already. The other bits
4956 // C0 and C3 are turned into Carry & Zero flags.
4957 operand cmpOpU() %{
4958 match(Bool);
4959
4960 format %{ "" %}
4961 interface(COND_INTER) %{
4962 equal(0x4, "e");
4963 not_equal(0x5, "ne");
4964 less(0x2, "b");
4965 greater_equal(0x3, "nb");
4966 less_equal(0x6, "be");
4967 greater(0x7, "nbe");
4968 overflow(0x0, "o");
4969 no_overflow(0x1, "no");
4970 %}
4971 %}
4972
4973 // Floating comparisons that don't require any fixup for the unordered case
4974 operand cmpOpUCF() %{
4975 match(Bool);
4976 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4977 n->as_Bool()->_test._test == BoolTest::ge ||
4978 n->as_Bool()->_test._test == BoolTest::le ||
4979 n->as_Bool()->_test._test == BoolTest::gt);
4980 format %{ "" %}
4981 interface(COND_INTER) %{
4982 equal(0x4, "e");
4983 not_equal(0x5, "ne");
4984 less(0x2, "b");
4985 greater_equal(0x3, "nb");
4986 less_equal(0x6, "be");
4987 greater(0x7, "nbe");
4988 overflow(0x0, "o");
4989 no_overflow(0x1, "no");
4990 %}
4991 %}
4992
4993
4994 // Floating comparisons that can be fixed up with extra conditional jumps
4995 operand cmpOpUCF2() %{
4996 match(Bool);
4997 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4998 n->as_Bool()->_test._test == BoolTest::eq);
4999 format %{ "" %}
5000 interface(COND_INTER) %{
5001 equal(0x4, "e");
5002 not_equal(0x5, "ne");
5003 less(0x2, "b");
5004 greater_equal(0x3, "nb");
5005 less_equal(0x6, "be");
5006 greater(0x7, "nbe");
5007 overflow(0x0, "o");
5008 no_overflow(0x1, "no");
5009 %}
5010 %}
5011
5012 // Comparison Code for FP conditional move
5013 operand cmpOp_fcmov() %{
5014 match(Bool);
5015
5016 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5017 n->as_Bool()->_test._test != BoolTest::no_overflow);
5018 format %{ "" %}
5019 interface(COND_INTER) %{
5020 equal (0x0C8);
5021 not_equal (0x1C8);
5022 less (0x0C0);
5023 greater_equal(0x1C0);
5024 less_equal (0x0D0);
5025 greater (0x1D0);
5026 overflow(0x0, "o"); // not really supported by the instruction
5027 no_overflow(0x1, "no"); // not really supported by the instruction
5028 %}
5029 %}
5030
5031 // Comparision Code used in long compares
5032 operand cmpOp_commute() %{
5033 match(Bool);
5034
5035 format %{ "" %}
5036 interface(COND_INTER) %{
5037 equal(0x4, "e");
5038 not_equal(0x5, "ne");
5039 less(0xF, "g");
5040 greater_equal(0xE, "le");
5041 less_equal(0xD, "ge");
5042 greater(0xC, "l");
5043 overflow(0x0, "o");
5044 no_overflow(0x1, "no");
5045 %}
5046 %}
5047
5048 //----------OPERAND CLASSES----------------------------------------------------
5049 // Operand Classes are groups of operands that are used as to simplify
5050 // instruction definitions by not requiring the AD writer to specify separate
5051 // instructions for every form of operand when the instruction accepts
5052 // multiple operand types with the same basic encoding and format. The classic
5053 // case of this is memory operands.
5054
5055 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5056 indIndex, indIndexScale, indIndexScaleOffset);
5057
5058 // Long memory operations are encoded in 2 instructions and a +4 offset.
5059 // This means some kind of offset is always required and you cannot use
5060 // an oop as the offset (done when working on static globals).
5061 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5062 indIndex, indIndexScale, indIndexScaleOffset);
5063
5064
5065 //----------PIPELINE-----------------------------------------------------------
5066 // Rules which define the behavior of the target architectures pipeline.
5067 pipeline %{
5068
5069 //----------ATTRIBUTES---------------------------------------------------------
5070 attributes %{
5071 variable_size_instructions; // Fixed size instructions
5072 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5073 instruction_unit_size = 1; // An instruction is 1 bytes long
5074 instruction_fetch_unit_size = 16; // The processor fetches one line
5075 instruction_fetch_units = 1; // of 16 bytes
5076
5077 // List of nop instructions
5078 nops( MachNop );
5079 %}
5080
5081 //----------RESOURCES----------------------------------------------------------
5082 // Resources are the functional units available to the machine
5083
5084 // Generic P2/P3 pipeline
5085 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5086 // 3 instructions decoded per cycle.
5087 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5088 // 2 ALU op, only ALU0 handles mul/div instructions.
5089 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5090 MS0, MS1, MEM = MS0 | MS1,
5091 BR, FPU,
5092 ALU0, ALU1, ALU = ALU0 | ALU1 );
5093
5094 //----------PIPELINE DESCRIPTION-----------------------------------------------
5095 // Pipeline Description specifies the stages in the machine's pipeline
5096
5097 // Generic P2/P3 pipeline
5098 pipe_desc(S0, S1, S2, S3, S4, S5);
5099
5100 //----------PIPELINE CLASSES---------------------------------------------------
5101 // Pipeline Classes describe the stages in which input and output are
5102 // referenced by the hardware pipeline.
5103
5104 // Naming convention: ialu or fpu
5105 // Then: _reg
5106 // Then: _reg if there is a 2nd register
5107 // Then: _long if it's a pair of instructions implementing a long
5108 // Then: _fat if it requires the big decoder
5109 // Or: _mem if it requires the big decoder and a memory unit.
5110
5111 // Integer ALU reg operation
5112 pipe_class ialu_reg(rRegI dst) %{
5113 single_instruction;
5114 dst : S4(write);
5115 dst : S3(read);
5116 DECODE : S0; // any decoder
5117 ALU : S3; // any alu
5118 %}
5119
5120 // Long ALU reg operation
5121 pipe_class ialu_reg_long(eRegL dst) %{
5122 instruction_count(2);
5123 dst : S4(write);
5124 dst : S3(read);
5125 DECODE : S0(2); // any 2 decoders
5126 ALU : S3(2); // both alus
5127 %}
5128
5129 // Integer ALU reg operation using big decoder
5130 pipe_class ialu_reg_fat(rRegI dst) %{
5131 single_instruction;
5132 dst : S4(write);
5133 dst : S3(read);
5134 D0 : S0; // big decoder only
5135 ALU : S3; // any alu
5136 %}
5137
5138 // Long ALU reg operation using big decoder
5139 pipe_class ialu_reg_long_fat(eRegL dst) %{
5140 instruction_count(2);
5141 dst : S4(write);
5142 dst : S3(read);
5143 D0 : S0(2); // big decoder only; twice
5144 ALU : S3(2); // any 2 alus
5145 %}
5146
5147 // Integer ALU reg-reg operation
5148 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5149 single_instruction;
5150 dst : S4(write);
5151 src : S3(read);
5152 DECODE : S0; // any decoder
5153 ALU : S3; // any alu
5154 %}
5155
5156 // Long ALU reg-reg operation
5157 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5158 instruction_count(2);
5159 dst : S4(write);
5160 src : S3(read);
5161 DECODE : S0(2); // any 2 decoders
5162 ALU : S3(2); // both alus
5163 %}
5164
5165 // Integer ALU reg-reg operation
5166 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5167 single_instruction;
5168 dst : S4(write);
5169 src : S3(read);
5170 D0 : S0; // big decoder only
5171 ALU : S3; // any alu
5172 %}
5173
5174 // Long ALU reg-reg operation
5175 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5176 instruction_count(2);
5177 dst : S4(write);
5178 src : S3(read);
5179 D0 : S0(2); // big decoder only; twice
5180 ALU : S3(2); // both alus
5181 %}
5182
5183 // Integer ALU reg-mem operation
5184 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5185 single_instruction;
5186 dst : S5(write);
5187 mem : S3(read);
5188 D0 : S0; // big decoder only
5189 ALU : S4; // any alu
5190 MEM : S3; // any mem
5191 %}
5192
5193 // Long ALU reg-mem operation
5194 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5195 instruction_count(2);
5196 dst : S5(write);
5197 mem : S3(read);
5198 D0 : S0(2); // big decoder only; twice
5199 ALU : S4(2); // any 2 alus
5200 MEM : S3(2); // both mems
5201 %}
5202
5203 // Integer mem operation (prefetch)
5204 pipe_class ialu_mem(memory mem)
5205 %{
5206 single_instruction;
5207 mem : S3(read);
5208 D0 : S0; // big decoder only
5209 MEM : S3; // any mem
5210 %}
5211
5212 // Integer Store to Memory
5213 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5214 single_instruction;
5215 mem : S3(read);
5216 src : S5(read);
5217 D0 : S0; // big decoder only
5218 ALU : S4; // any alu
5219 MEM : S3;
5220 %}
5221
5222 // Long Store to Memory
5223 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5224 instruction_count(2);
5225 mem : S3(read);
5226 src : S5(read);
5227 D0 : S0(2); // big decoder only; twice
5228 ALU : S4(2); // any 2 alus
5229 MEM : S3(2); // Both mems
5230 %}
5231
5232 // Integer Store to Memory
5233 pipe_class ialu_mem_imm(memory mem) %{
5234 single_instruction;
5235 mem : S3(read);
5236 D0 : S0; // big decoder only
5237 ALU : S4; // any alu
5238 MEM : S3;
5239 %}
5240
5241 // Integer ALU0 reg-reg operation
5242 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5243 single_instruction;
5244 dst : S4(write);
5245 src : S3(read);
5246 D0 : S0; // Big decoder only
5247 ALU0 : S3; // only alu0
5248 %}
5249
5250 // Integer ALU0 reg-mem operation
5251 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5252 single_instruction;
5253 dst : S5(write);
5254 mem : S3(read);
5255 D0 : S0; // big decoder only
5256 ALU0 : S4; // ALU0 only
5257 MEM : S3; // any mem
5258 %}
5259
5260 // Integer ALU reg-reg operation
5261 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5262 single_instruction;
5263 cr : S4(write);
5264 src1 : S3(read);
5265 src2 : S3(read);
5266 DECODE : S0; // any decoder
5267 ALU : S3; // any alu
5268 %}
5269
5270 // Integer ALU reg-imm operation
5271 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5272 single_instruction;
5273 cr : S4(write);
5274 src1 : S3(read);
5275 DECODE : S0; // any decoder
5276 ALU : S3; // any alu
5277 %}
5278
5279 // Integer ALU reg-mem operation
5280 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5281 single_instruction;
5282 cr : S4(write);
5283 src1 : S3(read);
5284 src2 : S3(read);
5285 D0 : S0; // big decoder only
5286 ALU : S4; // any alu
5287 MEM : S3;
5288 %}
5289
5290 // Conditional move reg-reg
5291 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5292 instruction_count(4);
5293 y : S4(read);
5294 q : S3(read);
5295 p : S3(read);
5296 DECODE : S0(4); // any decoder
5297 %}
5298
5299 // Conditional move reg-reg
5300 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5301 single_instruction;
5302 dst : S4(write);
5303 src : S3(read);
5304 cr : S3(read);
5305 DECODE : S0; // any decoder
5306 %}
5307
5308 // Conditional move reg-mem
5309 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5310 single_instruction;
5311 dst : S4(write);
5312 src : S3(read);
5313 cr : S3(read);
5314 DECODE : S0; // any decoder
5315 MEM : S3;
5316 %}
5317
5318 // Conditional move reg-reg long
5319 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5320 single_instruction;
5321 dst : S4(write);
5322 src : S3(read);
5323 cr : S3(read);
5324 DECODE : S0(2); // any 2 decoders
5325 %}
5326
5327 // Conditional move double reg-reg
5328 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5329 single_instruction;
5330 dst : S4(write);
5331 src : S3(read);
5332 cr : S3(read);
5333 DECODE : S0; // any decoder
5334 %}
5335
5336 // Float reg-reg operation
5337 pipe_class fpu_reg(regDPR dst) %{
5338 instruction_count(2);
5339 dst : S3(read);
5340 DECODE : S0(2); // any 2 decoders
5341 FPU : S3;
5342 %}
5343
5344 // Float reg-reg operation
5345 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5346 instruction_count(2);
5347 dst : S4(write);
5348 src : S3(read);
5349 DECODE : S0(2); // any 2 decoders
5350 FPU : S3;
5351 %}
5352
5353 // Float reg-reg operation
5354 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5355 instruction_count(3);
5356 dst : S4(write);
5357 src1 : S3(read);
5358 src2 : S3(read);
5359 DECODE : S0(3); // any 3 decoders
5360 FPU : S3(2);
5361 %}
5362
5363 // Float reg-reg operation
5364 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5365 instruction_count(4);
5366 dst : S4(write);
5367 src1 : S3(read);
5368 src2 : S3(read);
5369 src3 : S3(read);
5370 DECODE : S0(4); // any 3 decoders
5371 FPU : S3(2);
5372 %}
5373
5374 // Float reg-reg operation
5375 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5376 instruction_count(4);
5377 dst : S4(write);
5378 src1 : S3(read);
5379 src2 : S3(read);
5380 src3 : S3(read);
5381 DECODE : S1(3); // any 3 decoders
5382 D0 : S0; // Big decoder only
5383 FPU : S3(2);
5384 MEM : S3;
5385 %}
5386
5387 // Float reg-mem operation
5388 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5389 instruction_count(2);
5390 dst : S5(write);
5391 mem : S3(read);
5392 D0 : S0; // big decoder only
5393 DECODE : S1; // any decoder for FPU POP
5394 FPU : S4;
5395 MEM : S3; // any mem
5396 %}
5397
5398 // Float reg-mem operation
5399 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5400 instruction_count(3);
5401 dst : S5(write);
5402 src1 : S3(read);
5403 mem : S3(read);
5404 D0 : S0; // big decoder only
5405 DECODE : S1(2); // any decoder for FPU POP
5406 FPU : S4;
5407 MEM : S3; // any mem
5408 %}
5409
5410 // Float mem-reg operation
5411 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5412 instruction_count(2);
5413 src : S5(read);
5414 mem : S3(read);
5415 DECODE : S0; // any decoder for FPU PUSH
5416 D0 : S1; // big decoder only
5417 FPU : S4;
5418 MEM : S3; // any mem
5419 %}
5420
5421 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5422 instruction_count(3);
5423 src1 : S3(read);
5424 src2 : S3(read);
5425 mem : S3(read);
5426 DECODE : S0(2); // any decoder for FPU PUSH
5427 D0 : S1; // big decoder only
5428 FPU : S4;
5429 MEM : S3; // any mem
5430 %}
5431
5432 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5433 instruction_count(3);
5434 src1 : S3(read);
5435 src2 : S3(read);
5436 mem : S4(read);
5437 DECODE : S0; // any decoder for FPU PUSH
5438 D0 : S0(2); // big decoder only
5439 FPU : S4;
5440 MEM : S3(2); // any mem
5441 %}
5442
5443 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5444 instruction_count(2);
5445 src1 : S3(read);
5446 dst : S4(read);
5447 D0 : S0(2); // big decoder only
5448 MEM : S3(2); // any mem
5449 %}
5450
5451 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5452 instruction_count(3);
5453 src1 : S3(read);
5454 src2 : S3(read);
5455 dst : S4(read);
5456 D0 : S0(3); // big decoder only
5457 FPU : S4;
5458 MEM : S3(3); // any mem
5459 %}
5460
5461 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5462 instruction_count(3);
5463 src1 : S4(read);
5464 mem : S4(read);
5465 DECODE : S0; // any decoder for FPU PUSH
5466 D0 : S0(2); // big decoder only
5467 FPU : S4;
5468 MEM : S3(2); // any mem
5469 %}
5470
5471 // Float load constant
5472 pipe_class fpu_reg_con(regDPR dst) %{
5473 instruction_count(2);
5474 dst : S5(write);
5475 D0 : S0; // big decoder only for the load
5476 DECODE : S1; // any decoder for FPU POP
5477 FPU : S4;
5478 MEM : S3; // any mem
5479 %}
5480
5481 // Float load constant
5482 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5483 instruction_count(3);
5484 dst : S5(write);
5485 src : S3(read);
5486 D0 : S0; // big decoder only for the load
5487 DECODE : S1(2); // any decoder for FPU POP
5488 FPU : S4;
5489 MEM : S3; // any mem
5490 %}
5491
5492 // UnConditional branch
5493 pipe_class pipe_jmp( label labl ) %{
5494 single_instruction;
5495 BR : S3;
5496 %}
5497
5498 // Conditional branch
5499 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5500 single_instruction;
5501 cr : S1(read);
5502 BR : S3;
5503 %}
5504
5505 // Allocation idiom
5506 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5507 instruction_count(1); force_serialization;
5508 fixed_latency(6);
5509 heap_ptr : S3(read);
5510 DECODE : S0(3);
5511 D0 : S2;
5512 MEM : S3;
5513 ALU : S3(2);
5514 dst : S5(write);
5515 BR : S5;
5516 %}
5517
5518 // Generic big/slow expanded idiom
5519 pipe_class pipe_slow( ) %{
5520 instruction_count(10); multiple_bundles; force_serialization;
5521 fixed_latency(100);
5522 D0 : S0(2);
5523 MEM : S3(2);
5524 %}
5525
5526 // The real do-nothing guy
5527 pipe_class empty( ) %{
5528 instruction_count(0);
5529 %}
5530
5531 // Define the class for the Nop node
5532 define %{
5533 MachNop = empty;
5534 %}
5535
5536 %}
5537
5538 //----------INSTRUCTIONS-------------------------------------------------------
5539 //
5540 // match -- States which machine-independent subtree may be replaced
5541 // by this instruction.
5542 // ins_cost -- The estimated cost of this instruction is used by instruction
5543 // selection to identify a minimum cost tree of machine
5544 // instructions that matches a tree of machine-independent
5545 // instructions.
5546 // format -- A string providing the disassembly for this instruction.
5547 // The value of an instruction's operand may be inserted
5548 // by referring to it with a '$' prefix.
5549 // opcode -- Three instruction opcodes may be provided. These are referred
5550 // to within an encode class as $primary, $secondary, and $tertiary
5551 // respectively. The primary opcode is commonly used to
5552 // indicate the type of machine instruction, while secondary
5553 // and tertiary are often used for prefix options or addressing
5554 // modes.
5555 // ins_encode -- A list of encode classes with parameters. The encode class
5556 // name must have been defined in an 'enc_class' specification
5557 // in the encode section of the architecture description.
5558
5559 //----------BSWAP-Instruction--------------------------------------------------
5560 instruct bytes_reverse_int(rRegI dst) %{
5561 match(Set dst (ReverseBytesI dst));
5562
5563 format %{ "BSWAP $dst" %}
5564 opcode(0x0F, 0xC8);
5565 ins_encode( OpcP, OpcSReg(dst) );
5566 ins_pipe( ialu_reg );
5567 %}
5568
5569 instruct bytes_reverse_long(eRegL dst) %{
5570 match(Set dst (ReverseBytesL dst));
5571
5572 format %{ "BSWAP $dst.lo\n\t"
5573 "BSWAP $dst.hi\n\t"
5574 "XCHG $dst.lo $dst.hi" %}
5575
5576 ins_cost(125);
5577 ins_encode( bswap_long_bytes(dst) );
5578 ins_pipe( ialu_reg_reg);
5579 %}
5580
5581 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5582 match(Set dst (ReverseBytesUS dst));
5583 effect(KILL cr);
5584
5585 format %{ "BSWAP $dst\n\t"
5586 "SHR $dst,16\n\t" %}
5587 ins_encode %{
5588 __ bswapl($dst$$Register);
5589 __ shrl($dst$$Register, 16);
5590 %}
5591 ins_pipe( ialu_reg );
5592 %}
5593
5594 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5595 match(Set dst (ReverseBytesS dst));
5596 effect(KILL cr);
5597
5598 format %{ "BSWAP $dst\n\t"
5599 "SAR $dst,16\n\t" %}
5600 ins_encode %{
5601 __ bswapl($dst$$Register);
5602 __ sarl($dst$$Register, 16);
5603 %}
5604 ins_pipe( ialu_reg );
5605 %}
5606
5607
5608 //---------- Zeros Count Instructions ------------------------------------------
5609
5610 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5611 predicate(UseCountLeadingZerosInstruction);
5612 match(Set dst (CountLeadingZerosI src));
5613 effect(KILL cr);
5614
5615 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5616 ins_encode %{
5617 __ lzcntl($dst$$Register, $src$$Register);
5618 %}
5619 ins_pipe(ialu_reg);
5620 %}
5621
5622 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5623 predicate(!UseCountLeadingZerosInstruction);
5624 match(Set dst (CountLeadingZerosI src));
5625 effect(KILL cr);
5626
5627 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5628 "JNZ skip\n\t"
5629 "MOV $dst, -1\n"
5630 "skip:\n\t"
5631 "NEG $dst\n\t"
5632 "ADD $dst, 31" %}
5633 ins_encode %{
5634 Register Rdst = $dst$$Register;
5635 Register Rsrc = $src$$Register;
5636 Label skip;
5637 __ bsrl(Rdst, Rsrc);
5638 __ jccb(Assembler::notZero, skip);
5639 __ movl(Rdst, -1);
5640 __ bind(skip);
5641 __ negl(Rdst);
5642 __ addl(Rdst, BitsPerInt - 1);
5643 %}
5644 ins_pipe(ialu_reg);
5645 %}
5646
5647 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5648 predicate(UseCountLeadingZerosInstruction);
5649 match(Set dst (CountLeadingZerosL src));
5650 effect(TEMP dst, KILL cr);
5651
5652 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5653 "JNC done\n\t"
5654 "LZCNT $dst, $src.lo\n\t"
5655 "ADD $dst, 32\n"
5656 "done:" %}
5657 ins_encode %{
5658 Register Rdst = $dst$$Register;
5659 Register Rsrc = $src$$Register;
5660 Label done;
5661 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5662 __ jccb(Assembler::carryClear, done);
5663 __ lzcntl(Rdst, Rsrc);
5664 __ addl(Rdst, BitsPerInt);
5665 __ bind(done);
5666 %}
5667 ins_pipe(ialu_reg);
5668 %}
5669
5670 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5671 predicate(!UseCountLeadingZerosInstruction);
5672 match(Set dst (CountLeadingZerosL src));
5673 effect(TEMP dst, KILL cr);
5674
5675 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5676 "JZ msw_is_zero\n\t"
5677 "ADD $dst, 32\n\t"
5678 "JMP not_zero\n"
5679 "msw_is_zero:\n\t"
5680 "BSR $dst, $src.lo\n\t"
5681 "JNZ not_zero\n\t"
5682 "MOV $dst, -1\n"
5683 "not_zero:\n\t"
5684 "NEG $dst\n\t"
5685 "ADD $dst, 63\n" %}
5686 ins_encode %{
5687 Register Rdst = $dst$$Register;
5688 Register Rsrc = $src$$Register;
5689 Label msw_is_zero;
5690 Label not_zero;
5691 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5692 __ jccb(Assembler::zero, msw_is_zero);
5693 __ addl(Rdst, BitsPerInt);
5694 __ jmpb(not_zero);
5695 __ bind(msw_is_zero);
5696 __ bsrl(Rdst, Rsrc);
5697 __ jccb(Assembler::notZero, not_zero);
5698 __ movl(Rdst, -1);
5699 __ bind(not_zero);
5700 __ negl(Rdst);
5701 __ addl(Rdst, BitsPerLong - 1);
5702 %}
5703 ins_pipe(ialu_reg);
5704 %}
5705
5706 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5707 match(Set dst (CountTrailingZerosI src));
5708 effect(KILL cr);
5709
5710 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5711 "JNZ done\n\t"
5712 "MOV $dst, 32\n"
5713 "done:" %}
5714 ins_encode %{
5715 Register Rdst = $dst$$Register;
5716 Label done;
5717 __ bsfl(Rdst, $src$$Register);
5718 __ jccb(Assembler::notZero, done);
5719 __ movl(Rdst, BitsPerInt);
5720 __ bind(done);
5721 %}
5722 ins_pipe(ialu_reg);
5723 %}
5724
5725 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5726 match(Set dst (CountTrailingZerosL src));
5727 effect(TEMP dst, KILL cr);
5728
5729 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5730 "JNZ done\n\t"
5731 "BSF $dst, $src.hi\n\t"
5732 "JNZ msw_not_zero\n\t"
5733 "MOV $dst, 32\n"
5734 "msw_not_zero:\n\t"
5735 "ADD $dst, 32\n"
5736 "done:" %}
5737 ins_encode %{
5738 Register Rdst = $dst$$Register;
5739 Register Rsrc = $src$$Register;
5740 Label msw_not_zero;
5741 Label done;
5742 __ bsfl(Rdst, Rsrc);
5743 __ jccb(Assembler::notZero, done);
5744 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5745 __ jccb(Assembler::notZero, msw_not_zero);
5746 __ movl(Rdst, BitsPerInt);
5747 __ bind(msw_not_zero);
5748 __ addl(Rdst, BitsPerInt);
5749 __ bind(done);
5750 %}
5751 ins_pipe(ialu_reg);
5752 %}
5753
5754
5755 //---------- Population Count Instructions -------------------------------------
5756
5757 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5758 predicate(UsePopCountInstruction);
5759 match(Set dst (PopCountI src));
5760 effect(KILL cr);
5761
5762 format %{ "POPCNT $dst, $src" %}
5763 ins_encode %{
5764 __ popcntl($dst$$Register, $src$$Register);
5765 %}
5766 ins_pipe(ialu_reg);
5767 %}
5768
5769 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5770 predicate(UsePopCountInstruction);
5771 match(Set dst (PopCountI (LoadI mem)));
5772 effect(KILL cr);
5773
5774 format %{ "POPCNT $dst, $mem" %}
5775 ins_encode %{
5776 __ popcntl($dst$$Register, $mem$$Address);
5777 %}
5778 ins_pipe(ialu_reg);
5779 %}
5780
5781 // Note: Long.bitCount(long) returns an int.
5782 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5783 predicate(UsePopCountInstruction);
5784 match(Set dst (PopCountL src));
5785 effect(KILL cr, TEMP tmp, TEMP dst);
5786
5787 format %{ "POPCNT $dst, $src.lo\n\t"
5788 "POPCNT $tmp, $src.hi\n\t"
5789 "ADD $dst, $tmp" %}
5790 ins_encode %{
5791 __ popcntl($dst$$Register, $src$$Register);
5792 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5793 __ addl($dst$$Register, $tmp$$Register);
5794 %}
5795 ins_pipe(ialu_reg);
5796 %}
5797
5798 // Note: Long.bitCount(long) returns an int.
5799 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5800 predicate(UsePopCountInstruction);
5801 match(Set dst (PopCountL (LoadL mem)));
5802 effect(KILL cr, TEMP tmp, TEMP dst);
5803
5804 format %{ "POPCNT $dst, $mem\n\t"
5805 "POPCNT $tmp, $mem+4\n\t"
5806 "ADD $dst, $tmp" %}
5807 ins_encode %{
5808 //__ popcntl($dst$$Register, $mem$$Address$$first);
5809 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5810 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5811 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5812 __ addl($dst$$Register, $tmp$$Register);
5813 %}
5814 ins_pipe(ialu_reg);
5815 %}
5816
5817
5818 //----------Load/Store/Move Instructions---------------------------------------
5819 //----------Load Instructions--------------------------------------------------
5820 // Load Byte (8bit signed)
5821 instruct loadB(xRegI dst, memory mem) %{
5822 match(Set dst (LoadB mem));
5823
5824 ins_cost(125);
5825 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5826
5827 ins_encode %{
5828 __ movsbl($dst$$Register, $mem$$Address);
5829 %}
5830
5831 ins_pipe(ialu_reg_mem);
5832 %}
5833
5834 // Load Byte (8bit signed) into Long Register
5835 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5836 match(Set dst (ConvI2L (LoadB mem)));
5837 effect(KILL cr);
5838
5839 ins_cost(375);
5840 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5841 "MOV $dst.hi,$dst.lo\n\t"
5842 "SAR $dst.hi,7" %}
5843
5844 ins_encode %{
5845 __ movsbl($dst$$Register, $mem$$Address);
5846 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5847 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5848 %}
5849
5850 ins_pipe(ialu_reg_mem);
5851 %}
5852
5853 // Load Unsigned Byte (8bit UNsigned)
5854 instruct loadUB(xRegI dst, memory mem) %{
5855 match(Set dst (LoadUB mem));
5856
5857 ins_cost(125);
5858 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5859
5860 ins_encode %{
5861 __ movzbl($dst$$Register, $mem$$Address);
5862 %}
5863
5864 ins_pipe(ialu_reg_mem);
5865 %}
5866
5867 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5868 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5869 match(Set dst (ConvI2L (LoadUB mem)));
5870 effect(KILL cr);
5871
5872 ins_cost(250);
5873 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5874 "XOR $dst.hi,$dst.hi" %}
5875
5876 ins_encode %{
5877 Register Rdst = $dst$$Register;
5878 __ movzbl(Rdst, $mem$$Address);
5879 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5880 %}
5881
5882 ins_pipe(ialu_reg_mem);
5883 %}
5884
5885 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5886 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5887 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5888 effect(KILL cr);
5889
5890 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5891 "XOR $dst.hi,$dst.hi\n\t"
5892 "AND $dst.lo,$mask" %}
5893 ins_encode %{
5894 Register Rdst = $dst$$Register;
5895 __ movzbl(Rdst, $mem$$Address);
5896 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5897 __ andl(Rdst, $mask$$constant);
5898 %}
5899 ins_pipe(ialu_reg_mem);
5900 %}
5901
5902 // Load Short (16bit signed)
5903 instruct loadS(rRegI dst, memory mem) %{
5904 match(Set dst (LoadS mem));
5905
5906 ins_cost(125);
5907 format %{ "MOVSX $dst,$mem\t# short" %}
5908
5909 ins_encode %{
5910 __ movswl($dst$$Register, $mem$$Address);
5911 %}
5912
5913 ins_pipe(ialu_reg_mem);
5914 %}
5915
5916 // Load Short (16 bit signed) to Byte (8 bit signed)
5917 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5918 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5919
5920 ins_cost(125);
5921 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5922 ins_encode %{
5923 __ movsbl($dst$$Register, $mem$$Address);
5924 %}
5925 ins_pipe(ialu_reg_mem);
5926 %}
5927
5928 // Load Short (16bit signed) into Long Register
5929 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5930 match(Set dst (ConvI2L (LoadS mem)));
5931 effect(KILL cr);
5932
5933 ins_cost(375);
5934 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5935 "MOV $dst.hi,$dst.lo\n\t"
5936 "SAR $dst.hi,15" %}
5937
5938 ins_encode %{
5939 __ movswl($dst$$Register, $mem$$Address);
5940 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5941 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5942 %}
5943
5944 ins_pipe(ialu_reg_mem);
5945 %}
5946
5947 // Load Unsigned Short/Char (16bit unsigned)
5948 instruct loadUS(rRegI dst, memory mem) %{
5949 match(Set dst (LoadUS mem));
5950
5951 ins_cost(125);
5952 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5953
5954 ins_encode %{
5955 __ movzwl($dst$$Register, $mem$$Address);
5956 %}
5957
5958 ins_pipe(ialu_reg_mem);
5959 %}
5960
5961 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5962 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5963 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5964
5965 ins_cost(125);
5966 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5967 ins_encode %{
5968 __ movsbl($dst$$Register, $mem$$Address);
5969 %}
5970 ins_pipe(ialu_reg_mem);
5971 %}
5972
5973 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5974 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5975 match(Set dst (ConvI2L (LoadUS mem)));
5976 effect(KILL cr);
5977
5978 ins_cost(250);
5979 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5980 "XOR $dst.hi,$dst.hi" %}
5981
5982 ins_encode %{
5983 __ movzwl($dst$$Register, $mem$$Address);
5984 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5985 %}
5986
5987 ins_pipe(ialu_reg_mem);
5988 %}
5989
5990 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5991 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5992 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5993 effect(KILL cr);
5994
5995 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5996 "XOR $dst.hi,$dst.hi" %}
5997 ins_encode %{
5998 Register Rdst = $dst$$Register;
5999 __ movzbl(Rdst, $mem$$Address);
6000 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6001 %}
6002 ins_pipe(ialu_reg_mem);
6003 %}
6004
6005 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6006 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6007 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6008 effect(KILL cr);
6009
6010 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6011 "XOR $dst.hi,$dst.hi\n\t"
6012 "AND $dst.lo,$mask" %}
6013 ins_encode %{
6014 Register Rdst = $dst$$Register;
6015 __ movzwl(Rdst, $mem$$Address);
6016 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6017 __ andl(Rdst, $mask$$constant);
6018 %}
6019 ins_pipe(ialu_reg_mem);
6020 %}
6021
6022 // Load Integer
6023 instruct loadI(rRegI dst, memory mem) %{
6024 match(Set dst (LoadI mem));
6025
6026 ins_cost(125);
6027 format %{ "MOV $dst,$mem\t# int" %}
6028
6029 ins_encode %{
6030 __ movl($dst$$Register, $mem$$Address);
6031 %}
6032
6033 ins_pipe(ialu_reg_mem);
6034 %}
6035
6036 // Load Integer (32 bit signed) to Byte (8 bit signed)
6037 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6038 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6039
6040 ins_cost(125);
6041 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6042 ins_encode %{
6043 __ movsbl($dst$$Register, $mem$$Address);
6044 %}
6045 ins_pipe(ialu_reg_mem);
6046 %}
6047
6048 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6049 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6050 match(Set dst (AndI (LoadI mem) mask));
6051
6052 ins_cost(125);
6053 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6054 ins_encode %{
6055 __ movzbl($dst$$Register, $mem$$Address);
6056 %}
6057 ins_pipe(ialu_reg_mem);
6058 %}
6059
6060 // Load Integer (32 bit signed) to Short (16 bit signed)
6061 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6062 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6063
6064 ins_cost(125);
6065 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6066 ins_encode %{
6067 __ movswl($dst$$Register, $mem$$Address);
6068 %}
6069 ins_pipe(ialu_reg_mem);
6070 %}
6071
6072 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6073 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6074 match(Set dst (AndI (LoadI mem) mask));
6075
6076 ins_cost(125);
6077 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6078 ins_encode %{
6079 __ movzwl($dst$$Register, $mem$$Address);
6080 %}
6081 ins_pipe(ialu_reg_mem);
6082 %}
6083
6084 // Load Integer into Long Register
6085 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6086 match(Set dst (ConvI2L (LoadI mem)));
6087 effect(KILL cr);
6088
6089 ins_cost(375);
6090 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6091 "MOV $dst.hi,$dst.lo\n\t"
6092 "SAR $dst.hi,31" %}
6093
6094 ins_encode %{
6095 __ movl($dst$$Register, $mem$$Address);
6096 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6097 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6098 %}
6099
6100 ins_pipe(ialu_reg_mem);
6101 %}
6102
6103 // Load Integer with mask 0xFF into Long Register
6104 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6105 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6106 effect(KILL cr);
6107
6108 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6109 "XOR $dst.hi,$dst.hi" %}
6110 ins_encode %{
6111 Register Rdst = $dst$$Register;
6112 __ movzbl(Rdst, $mem$$Address);
6113 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6114 %}
6115 ins_pipe(ialu_reg_mem);
6116 %}
6117
6118 // Load Integer with mask 0xFFFF into Long Register
6119 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6120 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6121 effect(KILL cr);
6122
6123 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6124 "XOR $dst.hi,$dst.hi" %}
6125 ins_encode %{
6126 Register Rdst = $dst$$Register;
6127 __ movzwl(Rdst, $mem$$Address);
6128 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6129 %}
6130 ins_pipe(ialu_reg_mem);
6131 %}
6132
6133 // Load Integer with 31-bit mask into Long Register
6134 instruct loadI2L_immU32(eRegL dst, memory mem, immU32 mask, eFlagsReg cr) %{
6135 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6136 effect(KILL cr);
6137
6138 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6139 "XOR $dst.hi,$dst.hi\n\t"
6140 "AND $dst.lo,$mask" %}
6141 ins_encode %{
6142 Register Rdst = $dst$$Register;
6143 __ movl(Rdst, $mem$$Address);
6144 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6145 __ andl(Rdst, $mask$$constant);
6146 %}
6147 ins_pipe(ialu_reg_mem);
6148 %}
6149
6150 // Load Unsigned Integer into Long Register
6151 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6152 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6153 effect(KILL cr);
6154
6155 ins_cost(250);
6156 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6157 "XOR $dst.hi,$dst.hi" %}
6158
6159 ins_encode %{
6160 __ movl($dst$$Register, $mem$$Address);
6161 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6162 %}
6163
6164 ins_pipe(ialu_reg_mem);
6165 %}
6166
6167 // Load Long. Cannot clobber address while loading, so restrict address
6168 // register to ESI
6169 instruct loadL(eRegL dst, load_long_memory mem) %{
6170 predicate(!((LoadLNode*)n)->require_atomic_access());
6171 match(Set dst (LoadL mem));
6172
6173 ins_cost(250);
6174 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6175 "MOV $dst.hi,$mem+4" %}
6176
6177 ins_encode %{
6178 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6179 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6180 __ movl($dst$$Register, Amemlo);
6181 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6182 %}
6183
6184 ins_pipe(ialu_reg_long_mem);
6185 %}
6186
6187 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6188 // then store it down to the stack and reload on the int
6189 // side.
6190 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6191 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6192 match(Set dst (LoadL mem));
6193
6194 ins_cost(200);
6195 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6196 "FISTp $dst" %}
6197 ins_encode(enc_loadL_volatile(mem,dst));
6198 ins_pipe( fpu_reg_mem );
6199 %}
6200
6201 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6202 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6203 match(Set dst (LoadL mem));
6204 effect(TEMP tmp);
6205 ins_cost(180);
6206 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6207 "MOVSD $dst,$tmp" %}
6208 ins_encode %{
6209 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6210 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6211 %}
6212 ins_pipe( pipe_slow );
6213 %}
6214
6215 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6216 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6217 match(Set dst (LoadL mem));
6218 effect(TEMP tmp);
6219 ins_cost(160);
6220 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6221 "MOVD $dst.lo,$tmp\n\t"
6222 "PSRLQ $tmp,32\n\t"
6223 "MOVD $dst.hi,$tmp" %}
6224 ins_encode %{
6225 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6226 __ movdl($dst$$Register, $tmp$$XMMRegister);
6227 __ psrlq($tmp$$XMMRegister, 32);
6228 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6229 %}
6230 ins_pipe( pipe_slow );
6231 %}
6232
6233 // Load Range
6234 instruct loadRange(rRegI dst, memory mem) %{
6235 match(Set dst (LoadRange mem));
6236
6237 ins_cost(125);
6238 format %{ "MOV $dst,$mem" %}
6239 opcode(0x8B);
6240 ins_encode( OpcP, RegMem(dst,mem));
6241 ins_pipe( ialu_reg_mem );
6242 %}
6243
6244
6245 // Load Pointer
6246 instruct loadP(eRegP dst, memory mem) %{
6247 match(Set dst (LoadP mem));
6248
6249 ins_cost(125);
6250 format %{ "MOV $dst,$mem" %}
6251 opcode(0x8B);
6252 ins_encode( OpcP, RegMem(dst,mem));
6253 ins_pipe( ialu_reg_mem );
6254 %}
6255
6256 // Load Klass Pointer
6257 instruct loadKlass(eRegP dst, memory mem) %{
6258 match(Set dst (LoadKlass mem));
6259
6260 ins_cost(125);
6261 format %{ "MOV $dst,$mem" %}
6262 opcode(0x8B);
6263 ins_encode( OpcP, RegMem(dst,mem));
6264 ins_pipe( ialu_reg_mem );
6265 %}
6266
6267 // Load Double
6268 instruct loadDPR(regDPR dst, memory mem) %{
6269 predicate(UseSSE<=1);
6270 match(Set dst (LoadD mem));
6271
6272 ins_cost(150);
6273 format %{ "FLD_D ST,$mem\n\t"
6274 "FSTP $dst" %}
6275 opcode(0xDD); /* DD /0 */
6276 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6277 Pop_Reg_DPR(dst) );
6278 ins_pipe( fpu_reg_mem );
6279 %}
6280
6281 // Load Double to XMM
6282 instruct loadD(regD dst, memory mem) %{
6283 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6284 match(Set dst (LoadD mem));
6285 ins_cost(145);
6286 format %{ "MOVSD $dst,$mem" %}
6287 ins_encode %{
6288 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6289 %}
6290 ins_pipe( pipe_slow );
6291 %}
6292
6293 instruct loadD_partial(regD dst, memory mem) %{
6294 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6295 match(Set dst (LoadD mem));
6296 ins_cost(145);
6297 format %{ "MOVLPD $dst,$mem" %}
6298 ins_encode %{
6299 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6300 %}
6301 ins_pipe( pipe_slow );
6302 %}
6303
6304 // Load to XMM register (single-precision floating point)
6305 // MOVSS instruction
6306 instruct loadF(regF dst, memory mem) %{
6307 predicate(UseSSE>=1);
6308 match(Set dst (LoadF mem));
6309 ins_cost(145);
6310 format %{ "MOVSS $dst,$mem" %}
6311 ins_encode %{
6312 __ movflt ($dst$$XMMRegister, $mem$$Address);
6313 %}
6314 ins_pipe( pipe_slow );
6315 %}
6316
6317 // Load Float
6318 instruct loadFPR(regFPR dst, memory mem) %{
6319 predicate(UseSSE==0);
6320 match(Set dst (LoadF mem));
6321
6322 ins_cost(150);
6323 format %{ "FLD_S ST,$mem\n\t"
6324 "FSTP $dst" %}
6325 opcode(0xD9); /* D9 /0 */
6326 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6327 Pop_Reg_FPR(dst) );
6328 ins_pipe( fpu_reg_mem );
6329 %}
6330
6331 // Load Effective Address
6332 instruct leaP8(eRegP dst, indOffset8 mem) %{
6333 match(Set dst mem);
6334
6335 ins_cost(110);
6336 format %{ "LEA $dst,$mem" %}
6337 opcode(0x8D);
6338 ins_encode( OpcP, RegMem(dst,mem));
6339 ins_pipe( ialu_reg_reg_fat );
6340 %}
6341
6342 instruct leaP32(eRegP dst, indOffset32 mem) %{
6343 match(Set dst mem);
6344
6345 ins_cost(110);
6346 format %{ "LEA $dst,$mem" %}
6347 opcode(0x8D);
6348 ins_encode( OpcP, RegMem(dst,mem));
6349 ins_pipe( ialu_reg_reg_fat );
6350 %}
6351
6352 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6353 match(Set dst mem);
6354
6355 ins_cost(110);
6356 format %{ "LEA $dst,$mem" %}
6357 opcode(0x8D);
6358 ins_encode( OpcP, RegMem(dst,mem));
6359 ins_pipe( ialu_reg_reg_fat );
6360 %}
6361
6362 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6363 match(Set dst mem);
6364
6365 ins_cost(110);
6366 format %{ "LEA $dst,$mem" %}
6367 opcode(0x8D);
6368 ins_encode( OpcP, RegMem(dst,mem));
6369 ins_pipe( ialu_reg_reg_fat );
6370 %}
6371
6372 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6373 match(Set dst mem);
6374
6375 ins_cost(110);
6376 format %{ "LEA $dst,$mem" %}
6377 opcode(0x8D);
6378 ins_encode( OpcP, RegMem(dst,mem));
6379 ins_pipe( ialu_reg_reg_fat );
6380 %}
6381
6382 // Load Constant
6383 instruct loadConI(rRegI dst, immI src) %{
6384 match(Set dst src);
6385
6386 format %{ "MOV $dst,$src" %}
6387 ins_encode( LdImmI(dst, src) );
6388 ins_pipe( ialu_reg_fat );
6389 %}
6390
6391 // Load Constant zero
6392 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6393 match(Set dst src);
6394 effect(KILL cr);
6395
6396 ins_cost(50);
6397 format %{ "XOR $dst,$dst" %}
6398 opcode(0x33); /* + rd */
6399 ins_encode( OpcP, RegReg( dst, dst ) );
6400 ins_pipe( ialu_reg );
6401 %}
6402
6403 instruct loadConP(eRegP dst, immP src) %{
6404 match(Set dst src);
6405
6406 format %{ "MOV $dst,$src" %}
6407 opcode(0xB8); /* + rd */
6408 ins_encode( LdImmP(dst, src) );
6409 ins_pipe( ialu_reg_fat );
6410 %}
6411
6412 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6413 match(Set dst src);
6414 effect(KILL cr);
6415 ins_cost(200);
6416 format %{ "MOV $dst.lo,$src.lo\n\t"
6417 "MOV $dst.hi,$src.hi" %}
6418 opcode(0xB8);
6419 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6420 ins_pipe( ialu_reg_long_fat );
6421 %}
6422
6423 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6424 match(Set dst src);
6425 effect(KILL cr);
6426 ins_cost(150);
6427 format %{ "XOR $dst.lo,$dst.lo\n\t"
6428 "XOR $dst.hi,$dst.hi" %}
6429 opcode(0x33,0x33);
6430 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6431 ins_pipe( ialu_reg_long );
6432 %}
6433
6434 // The instruction usage is guarded by predicate in operand immFPR().
6435 instruct loadConFPR(regFPR dst, immFPR con) %{
6436 match(Set dst con);
6437 ins_cost(125);
6438 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6439 "FSTP $dst" %}
6440 ins_encode %{
6441 __ fld_s($constantaddress($con));
6442 __ fstp_d($dst$$reg);
6443 %}
6444 ins_pipe(fpu_reg_con);
6445 %}
6446
6447 // The instruction usage is guarded by predicate in operand immFPR0().
6448 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6449 match(Set dst con);
6450 ins_cost(125);
6451 format %{ "FLDZ ST\n\t"
6452 "FSTP $dst" %}
6453 ins_encode %{
6454 __ fldz();
6455 __ fstp_d($dst$$reg);
6456 %}
6457 ins_pipe(fpu_reg_con);
6458 %}
6459
6460 // The instruction usage is guarded by predicate in operand immFPR1().
6461 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6462 match(Set dst con);
6463 ins_cost(125);
6464 format %{ "FLD1 ST\n\t"
6465 "FSTP $dst" %}
6466 ins_encode %{
6467 __ fld1();
6468 __ fstp_d($dst$$reg);
6469 %}
6470 ins_pipe(fpu_reg_con);
6471 %}
6472
6473 // The instruction usage is guarded by predicate in operand immF().
6474 instruct loadConF(regF dst, immF con) %{
6475 match(Set dst con);
6476 ins_cost(125);
6477 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6478 ins_encode %{
6479 __ movflt($dst$$XMMRegister, $constantaddress($con));
6480 %}
6481 ins_pipe(pipe_slow);
6482 %}
6483
6484 // The instruction usage is guarded by predicate in operand immF0().
6485 instruct loadConF0(regF dst, immF0 src) %{
6486 match(Set dst src);
6487 ins_cost(100);
6488 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6489 ins_encode %{
6490 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6491 %}
6492 ins_pipe(pipe_slow);
6493 %}
6494
6495 // The instruction usage is guarded by predicate in operand immDPR().
6496 instruct loadConDPR(regDPR dst, immDPR con) %{
6497 match(Set dst con);
6498 ins_cost(125);
6499
6500 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6501 "FSTP $dst" %}
6502 ins_encode %{
6503 __ fld_d($constantaddress($con));
6504 __ fstp_d($dst$$reg);
6505 %}
6506 ins_pipe(fpu_reg_con);
6507 %}
6508
6509 // The instruction usage is guarded by predicate in operand immDPR0().
6510 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6511 match(Set dst con);
6512 ins_cost(125);
6513
6514 format %{ "FLDZ ST\n\t"
6515 "FSTP $dst" %}
6516 ins_encode %{
6517 __ fldz();
6518 __ fstp_d($dst$$reg);
6519 %}
6520 ins_pipe(fpu_reg_con);
6521 %}
6522
6523 // The instruction usage is guarded by predicate in operand immDPR1().
6524 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6525 match(Set dst con);
6526 ins_cost(125);
6527
6528 format %{ "FLD1 ST\n\t"
6529 "FSTP $dst" %}
6530 ins_encode %{
6531 __ fld1();
6532 __ fstp_d($dst$$reg);
6533 %}
6534 ins_pipe(fpu_reg_con);
6535 %}
6536
6537 // The instruction usage is guarded by predicate in operand immD().
6538 instruct loadConD(regD dst, immD con) %{
6539 match(Set dst con);
6540 ins_cost(125);
6541 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6542 ins_encode %{
6543 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6544 %}
6545 ins_pipe(pipe_slow);
6546 %}
6547
6548 // The instruction usage is guarded by predicate in operand immD0().
6549 instruct loadConD0(regD dst, immD0 src) %{
6550 match(Set dst src);
6551 ins_cost(100);
6552 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6553 ins_encode %{
6554 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6555 %}
6556 ins_pipe( pipe_slow );
6557 %}
6558
6559 // Load Stack Slot
6560 instruct loadSSI(rRegI dst, stackSlotI src) %{
6561 match(Set dst src);
6562 ins_cost(125);
6563
6564 format %{ "MOV $dst,$src" %}
6565 opcode(0x8B);
6566 ins_encode( OpcP, RegMem(dst,src));
6567 ins_pipe( ialu_reg_mem );
6568 %}
6569
6570 instruct loadSSL(eRegL dst, stackSlotL src) %{
6571 match(Set dst src);
6572
6573 ins_cost(200);
6574 format %{ "MOV $dst,$src.lo\n\t"
6575 "MOV $dst+4,$src.hi" %}
6576 opcode(0x8B, 0x8B);
6577 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6578 ins_pipe( ialu_mem_long_reg );
6579 %}
6580
6581 // Load Stack Slot
6582 instruct loadSSP(eRegP dst, stackSlotP src) %{
6583 match(Set dst src);
6584 ins_cost(125);
6585
6586 format %{ "MOV $dst,$src" %}
6587 opcode(0x8B);
6588 ins_encode( OpcP, RegMem(dst,src));
6589 ins_pipe( ialu_reg_mem );
6590 %}
6591
6592 // Load Stack Slot
6593 instruct loadSSF(regFPR dst, stackSlotF src) %{
6594 match(Set dst src);
6595 ins_cost(125);
6596
6597 format %{ "FLD_S $src\n\t"
6598 "FSTP $dst" %}
6599 opcode(0xD9); /* D9 /0, FLD m32real */
6600 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6601 Pop_Reg_FPR(dst) );
6602 ins_pipe( fpu_reg_mem );
6603 %}
6604
6605 // Load Stack Slot
6606 instruct loadSSD(regDPR dst, stackSlotD src) %{
6607 match(Set dst src);
6608 ins_cost(125);
6609
6610 format %{ "FLD_D $src\n\t"
6611 "FSTP $dst" %}
6612 opcode(0xDD); /* DD /0, FLD m64real */
6613 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6614 Pop_Reg_DPR(dst) );
6615 ins_pipe( fpu_reg_mem );
6616 %}
6617
6618 // Prefetch instructions.
6619 // Must be safe to execute with invalid address (cannot fault).
6620
6621 instruct prefetchr0( memory mem ) %{
6622 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6623 match(PrefetchRead mem);
6624 ins_cost(0);
6625 size(0);
6626 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6627 ins_encode();
6628 ins_pipe(empty);
6629 %}
6630
6631 instruct prefetchr( memory mem ) %{
6632 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6633 match(PrefetchRead mem);
6634 ins_cost(100);
6635
6636 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6637 ins_encode %{
6638 __ prefetchr($mem$$Address);
6639 %}
6640 ins_pipe(ialu_mem);
6641 %}
6642
6643 instruct prefetchrNTA( memory mem ) %{
6644 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6645 match(PrefetchRead mem);
6646 ins_cost(100);
6647
6648 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6649 ins_encode %{
6650 __ prefetchnta($mem$$Address);
6651 %}
6652 ins_pipe(ialu_mem);
6653 %}
6654
6655 instruct prefetchrT0( memory mem ) %{
6656 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6657 match(PrefetchRead mem);
6658 ins_cost(100);
6659
6660 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6661 ins_encode %{
6662 __ prefetcht0($mem$$Address);
6663 %}
6664 ins_pipe(ialu_mem);
6665 %}
6666
6667 instruct prefetchrT2( memory mem ) %{
6668 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6669 match(PrefetchRead mem);
6670 ins_cost(100);
6671
6672 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6673 ins_encode %{
6674 __ prefetcht2($mem$$Address);
6675 %}
6676 ins_pipe(ialu_mem);
6677 %}
6678
6679 instruct prefetchw0( memory mem ) %{
6680 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6681 match(PrefetchWrite mem);
6682 ins_cost(0);
6683 size(0);
6684 format %{ "Prefetch (non-SSE is empty encoding)" %}
6685 ins_encode();
6686 ins_pipe(empty);
6687 %}
6688
6689 instruct prefetchw( memory mem ) %{
6690 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6691 match( PrefetchWrite mem );
6692 ins_cost(100);
6693
6694 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6695 ins_encode %{
6696 __ prefetchw($mem$$Address);
6697 %}
6698 ins_pipe(ialu_mem);
6699 %}
6700
6701 instruct prefetchwNTA( memory mem ) %{
6702 predicate(UseSSE>=1);
6703 match(PrefetchWrite mem);
6704 ins_cost(100);
6705
6706 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6707 ins_encode %{
6708 __ prefetchnta($mem$$Address);
6709 %}
6710 ins_pipe(ialu_mem);
6711 %}
6712
6713 // Prefetch instructions for allocation.
6714
6715 instruct prefetchAlloc0( memory mem ) %{
6716 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6717 match(PrefetchAllocation mem);
6718 ins_cost(0);
6719 size(0);
6720 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6721 ins_encode();
6722 ins_pipe(empty);
6723 %}
6724
6725 instruct prefetchAlloc( memory mem ) %{
6726 predicate(AllocatePrefetchInstr==3);
6727 match( PrefetchAllocation mem );
6728 ins_cost(100);
6729
6730 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6731 ins_encode %{
6732 __ prefetchw($mem$$Address);
6733 %}
6734 ins_pipe(ialu_mem);
6735 %}
6736
6737 instruct prefetchAllocNTA( memory mem ) %{
6738 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6739 match(PrefetchAllocation mem);
6740 ins_cost(100);
6741
6742 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6743 ins_encode %{
6744 __ prefetchnta($mem$$Address);
6745 %}
6746 ins_pipe(ialu_mem);
6747 %}
6748
6749 instruct prefetchAllocT0( memory mem ) %{
6750 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6751 match(PrefetchAllocation mem);
6752 ins_cost(100);
6753
6754 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6755 ins_encode %{
6756 __ prefetcht0($mem$$Address);
6757 %}
6758 ins_pipe(ialu_mem);
6759 %}
6760
6761 instruct prefetchAllocT2( memory mem ) %{
6762 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6763 match(PrefetchAllocation mem);
6764 ins_cost(100);
6765
6766 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6767 ins_encode %{
6768 __ prefetcht2($mem$$Address);
6769 %}
6770 ins_pipe(ialu_mem);
6771 %}
6772
6773 //----------Store Instructions-------------------------------------------------
6774
6775 // Store Byte
6776 instruct storeB(memory mem, xRegI src) %{
6777 match(Set mem (StoreB mem src));
6778
6779 ins_cost(125);
6780 format %{ "MOV8 $mem,$src" %}
6781 opcode(0x88);
6782 ins_encode( OpcP, RegMem( src, mem ) );
6783 ins_pipe( ialu_mem_reg );
6784 %}
6785
6786 // Store Char/Short
6787 instruct storeC(memory mem, rRegI src) %{
6788 match(Set mem (StoreC mem src));
6789
6790 ins_cost(125);
6791 format %{ "MOV16 $mem,$src" %}
6792 opcode(0x89, 0x66);
6793 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6794 ins_pipe( ialu_mem_reg );
6795 %}
6796
6797 // Store Integer
6798 instruct storeI(memory mem, rRegI src) %{
6799 match(Set mem (StoreI mem src));
6800
6801 ins_cost(125);
6802 format %{ "MOV $mem,$src" %}
6803 opcode(0x89);
6804 ins_encode( OpcP, RegMem( src, mem ) );
6805 ins_pipe( ialu_mem_reg );
6806 %}
6807
6808 // Store Long
6809 instruct storeL(long_memory mem, eRegL src) %{
6810 predicate(!((StoreLNode*)n)->require_atomic_access());
6811 match(Set mem (StoreL mem src));
6812
6813 ins_cost(200);
6814 format %{ "MOV $mem,$src.lo\n\t"
6815 "MOV $mem+4,$src.hi" %}
6816 opcode(0x89, 0x89);
6817 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6818 ins_pipe( ialu_mem_long_reg );
6819 %}
6820
6821 // Store Long to Integer
6822 instruct storeL2I(memory mem, eRegL src) %{
6823 match(Set mem (StoreI mem (ConvL2I src)));
6824
6825 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6826 ins_encode %{
6827 __ movl($mem$$Address, $src$$Register);
6828 %}
6829 ins_pipe(ialu_mem_reg);
6830 %}
6831
6832 // Volatile Store Long. Must be atomic, so move it into
6833 // the FP TOS and then do a 64-bit FIST. Has to probe the
6834 // target address before the store (for null-ptr checks)
6835 // so the memory operand is used twice in the encoding.
6836 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6837 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6838 match(Set mem (StoreL mem src));
6839 effect( KILL cr );
6840 ins_cost(400);
6841 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6842 "FILD $src\n\t"
6843 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6844 opcode(0x3B);
6845 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6846 ins_pipe( fpu_reg_mem );
6847 %}
6848
6849 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6850 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6851 match(Set mem (StoreL mem src));
6852 effect( TEMP tmp, KILL cr );
6853 ins_cost(380);
6854 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6855 "MOVSD $tmp,$src\n\t"
6856 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6857 ins_encode %{
6858 __ cmpl(rax, $mem$$Address);
6859 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6860 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6861 %}
6862 ins_pipe( pipe_slow );
6863 %}
6864
6865 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6866 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6867 match(Set mem (StoreL mem src));
6868 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6869 ins_cost(360);
6870 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6871 "MOVD $tmp,$src.lo\n\t"
6872 "MOVD $tmp2,$src.hi\n\t"
6873 "PUNPCKLDQ $tmp,$tmp2\n\t"
6874 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6875 ins_encode %{
6876 __ cmpl(rax, $mem$$Address);
6877 __ movdl($tmp$$XMMRegister, $src$$Register);
6878 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6879 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6880 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6881 %}
6882 ins_pipe( pipe_slow );
6883 %}
6884
6885 // Store Pointer; for storing unknown oops and raw pointers
6886 instruct storeP(memory mem, anyRegP src) %{
6887 match(Set mem (StoreP mem src));
6888
6889 ins_cost(125);
6890 format %{ "MOV $mem,$src" %}
6891 opcode(0x89);
6892 ins_encode( OpcP, RegMem( src, mem ) );
6893 ins_pipe( ialu_mem_reg );
6894 %}
6895
6896 // Store Integer Immediate
6897 instruct storeImmI(memory mem, immI src) %{
6898 match(Set mem (StoreI mem src));
6899
6900 ins_cost(150);
6901 format %{ "MOV $mem,$src" %}
6902 opcode(0xC7); /* C7 /0 */
6903 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6904 ins_pipe( ialu_mem_imm );
6905 %}
6906
6907 // Store Short/Char Immediate
6908 instruct storeImmI16(memory mem, immI16 src) %{
6909 predicate(UseStoreImmI16);
6910 match(Set mem (StoreC mem src));
6911
6912 ins_cost(150);
6913 format %{ "MOV16 $mem,$src" %}
6914 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6915 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6916 ins_pipe( ialu_mem_imm );
6917 %}
6918
6919 // Store Pointer Immediate; null pointers or constant oops that do not
6920 // need card-mark barriers.
6921 instruct storeImmP(memory mem, immP src) %{
6922 match(Set mem (StoreP mem src));
6923
6924 ins_cost(150);
6925 format %{ "MOV $mem,$src" %}
6926 opcode(0xC7); /* C7 /0 */
6927 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6928 ins_pipe( ialu_mem_imm );
6929 %}
6930
6931 // Store Byte Immediate
6932 instruct storeImmB(memory mem, immI8 src) %{
6933 match(Set mem (StoreB mem src));
6934
6935 ins_cost(150);
6936 format %{ "MOV8 $mem,$src" %}
6937 opcode(0xC6); /* C6 /0 */
6938 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6939 ins_pipe( ialu_mem_imm );
6940 %}
6941
6942 // Store CMS card-mark Immediate
6943 instruct storeImmCM(memory mem, immI8 src) %{
6944 match(Set mem (StoreCM mem src));
6945
6946 ins_cost(150);
6947 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6948 opcode(0xC6); /* C6 /0 */
6949 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6950 ins_pipe( ialu_mem_imm );
6951 %}
6952
6953 // Store Double
6954 instruct storeDPR( memory mem, regDPR1 src) %{
6955 predicate(UseSSE<=1);
6956 match(Set mem (StoreD mem src));
6957
6958 ins_cost(100);
6959 format %{ "FST_D $mem,$src" %}
6960 opcode(0xDD); /* DD /2 */
6961 ins_encode( enc_FPR_store(mem,src) );
6962 ins_pipe( fpu_mem_reg );
6963 %}
6964
6965 // Store double does rounding on x86
6966 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6967 predicate(UseSSE<=1);
6968 match(Set mem (StoreD mem (RoundDouble src)));
6969
6970 ins_cost(100);
6971 format %{ "FST_D $mem,$src\t# round" %}
6972 opcode(0xDD); /* DD /2 */
6973 ins_encode( enc_FPR_store(mem,src) );
6974 ins_pipe( fpu_mem_reg );
6975 %}
6976
6977 // Store XMM register to memory (double-precision floating points)
6978 // MOVSD instruction
6979 instruct storeD(memory mem, regD src) %{
6980 predicate(UseSSE>=2);
6981 match(Set mem (StoreD mem src));
6982 ins_cost(95);
6983 format %{ "MOVSD $mem,$src" %}
6984 ins_encode %{
6985 __ movdbl($mem$$Address, $src$$XMMRegister);
6986 %}
6987 ins_pipe( pipe_slow );
6988 %}
6989
6990 // Store XMM register to memory (single-precision floating point)
6991 // MOVSS instruction
6992 instruct storeF(memory mem, regF src) %{
6993 predicate(UseSSE>=1);
6994 match(Set mem (StoreF mem src));
6995 ins_cost(95);
6996 format %{ "MOVSS $mem,$src" %}
6997 ins_encode %{
6998 __ movflt($mem$$Address, $src$$XMMRegister);
6999 %}
7000 ins_pipe( pipe_slow );
7001 %}
7002
7003 // Store Float
7004 instruct storeFPR( memory mem, regFPR1 src) %{
7005 predicate(UseSSE==0);
7006 match(Set mem (StoreF mem src));
7007
7008 ins_cost(100);
7009 format %{ "FST_S $mem,$src" %}
7010 opcode(0xD9); /* D9 /2 */
7011 ins_encode( enc_FPR_store(mem,src) );
7012 ins_pipe( fpu_mem_reg );
7013 %}
7014
7015 // Store Float does rounding on x86
7016 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7017 predicate(UseSSE==0);
7018 match(Set mem (StoreF mem (RoundFloat src)));
7019
7020 ins_cost(100);
7021 format %{ "FST_S $mem,$src\t# round" %}
7022 opcode(0xD9); /* D9 /2 */
7023 ins_encode( enc_FPR_store(mem,src) );
7024 ins_pipe( fpu_mem_reg );
7025 %}
7026
7027 // Store Float does rounding on x86
7028 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7029 predicate(UseSSE<=1);
7030 match(Set mem (StoreF mem (ConvD2F src)));
7031
7032 ins_cost(100);
7033 format %{ "FST_S $mem,$src\t# D-round" %}
7034 opcode(0xD9); /* D9 /2 */
7035 ins_encode( enc_FPR_store(mem,src) );
7036 ins_pipe( fpu_mem_reg );
7037 %}
7038
7039 // Store immediate Float value (it is faster than store from FPU register)
7040 // The instruction usage is guarded by predicate in operand immFPR().
7041 instruct storeFPR_imm( memory mem, immFPR src) %{
7042 match(Set mem (StoreF mem src));
7043
7044 ins_cost(50);
7045 format %{ "MOV $mem,$src\t# store float" %}
7046 opcode(0xC7); /* C7 /0 */
7047 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7048 ins_pipe( ialu_mem_imm );
7049 %}
7050
7051 // Store immediate Float value (it is faster than store from XMM register)
7052 // The instruction usage is guarded by predicate in operand immF().
7053 instruct storeF_imm( memory mem, immF src) %{
7054 match(Set mem (StoreF mem src));
7055
7056 ins_cost(50);
7057 format %{ "MOV $mem,$src\t# store float" %}
7058 opcode(0xC7); /* C7 /0 */
7059 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7060 ins_pipe( ialu_mem_imm );
7061 %}
7062
7063 // Store Integer to stack slot
7064 instruct storeSSI(stackSlotI dst, rRegI src) %{
7065 match(Set dst src);
7066
7067 ins_cost(100);
7068 format %{ "MOV $dst,$src" %}
7069 opcode(0x89);
7070 ins_encode( OpcPRegSS( dst, src ) );
7071 ins_pipe( ialu_mem_reg );
7072 %}
7073
7074 // Store Integer to stack slot
7075 instruct storeSSP(stackSlotP dst, eRegP src) %{
7076 match(Set dst src);
7077
7078 ins_cost(100);
7079 format %{ "MOV $dst,$src" %}
7080 opcode(0x89);
7081 ins_encode( OpcPRegSS( dst, src ) );
7082 ins_pipe( ialu_mem_reg );
7083 %}
7084
7085 // Store Long to stack slot
7086 instruct storeSSL(stackSlotL dst, eRegL src) %{
7087 match(Set dst src);
7088
7089 ins_cost(200);
7090 format %{ "MOV $dst,$src.lo\n\t"
7091 "MOV $dst+4,$src.hi" %}
7092 opcode(0x89, 0x89);
7093 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7094 ins_pipe( ialu_mem_long_reg );
7095 %}
7096
7097 //----------MemBar Instructions-----------------------------------------------
7098 // Memory barrier flavors
7099
7100 instruct membar_acquire() %{
7101 match(MemBarAcquire);
7102 ins_cost(400);
7103
7104 size(0);
7105 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7106 ins_encode();
7107 ins_pipe(empty);
7108 %}
7109
7110 instruct membar_acquire_lock() %{
7111 match(MemBarAcquireLock);
7112 ins_cost(0);
7113
7114 size(0);
7115 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7116 ins_encode( );
7117 ins_pipe(empty);
7118 %}
7119
7120 instruct membar_release() %{
7121 match(MemBarRelease);
7122 ins_cost(400);
7123
7124 size(0);
7125 format %{ "MEMBAR-release ! (empty encoding)" %}
7126 ins_encode( );
7127 ins_pipe(empty);
7128 %}
7129
7130 instruct membar_release_lock() %{
7131 match(MemBarReleaseLock);
7132 ins_cost(0);
7133
7134 size(0);
7135 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7136 ins_encode( );
7137 ins_pipe(empty);
7138 %}
7139
7140 instruct membar_volatile(eFlagsReg cr) %{
7141 match(MemBarVolatile);
7142 effect(KILL cr);
7143 ins_cost(400);
7144
7145 format %{
7146 $$template
7147 if (os::is_MP()) {
7148 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7149 } else {
7150 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7151 }
7152 %}
7153 ins_encode %{
7154 __ membar(Assembler::StoreLoad);
7155 %}
7156 ins_pipe(pipe_slow);
7157 %}
7158
7159 instruct unnecessary_membar_volatile() %{
7160 match(MemBarVolatile);
7161 predicate(Matcher::post_store_load_barrier(n));
7162 ins_cost(0);
7163
7164 size(0);
7165 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7166 ins_encode( );
7167 ins_pipe(empty);
7168 %}
7169
7170 instruct membar_storestore() %{
7171 match(MemBarStoreStore);
7172 ins_cost(0);
7173
7174 size(0);
7175 format %{ "MEMBAR-storestore (empty encoding)" %}
7176 ins_encode( );
7177 ins_pipe(empty);
7178 %}
7179
7180 //----------Move Instructions--------------------------------------------------
7181 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7182 match(Set dst (CastX2P src));
7183 format %{ "# X2P $dst, $src" %}
7184 ins_encode( /*empty encoding*/ );
7185 ins_cost(0);
7186 ins_pipe(empty);
7187 %}
7188
7189 instruct castP2X(rRegI dst, eRegP src ) %{
7190 match(Set dst (CastP2X src));
7191 ins_cost(50);
7192 format %{ "MOV $dst, $src\t# CastP2X" %}
7193 ins_encode( enc_Copy( dst, src) );
7194 ins_pipe( ialu_reg_reg );
7195 %}
7196
7197 //----------Conditional Move---------------------------------------------------
7198 // Conditional move
7199 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7200 predicate(!VM_Version::supports_cmov() );
7201 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7202 ins_cost(200);
7203 format %{ "J$cop,us skip\t# signed cmove\n\t"
7204 "MOV $dst,$src\n"
7205 "skip:" %}
7206 ins_encode %{
7207 Label Lskip;
7208 // Invert sense of branch from sense of CMOV
7209 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7210 __ movl($dst$$Register, $src$$Register);
7211 __ bind(Lskip);
7212 %}
7213 ins_pipe( pipe_cmov_reg );
7214 %}
7215
7216 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7217 predicate(!VM_Version::supports_cmov() );
7218 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7219 ins_cost(200);
7220 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7221 "MOV $dst,$src\n"
7222 "skip:" %}
7223 ins_encode %{
7224 Label Lskip;
7225 // Invert sense of branch from sense of CMOV
7226 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7227 __ movl($dst$$Register, $src$$Register);
7228 __ bind(Lskip);
7229 %}
7230 ins_pipe( pipe_cmov_reg );
7231 %}
7232
7233 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7234 predicate(VM_Version::supports_cmov() );
7235 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7236 ins_cost(200);
7237 format %{ "CMOV$cop $dst,$src" %}
7238 opcode(0x0F,0x40);
7239 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7240 ins_pipe( pipe_cmov_reg );
7241 %}
7242
7243 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7244 predicate(VM_Version::supports_cmov() );
7245 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7246 ins_cost(200);
7247 format %{ "CMOV$cop $dst,$src" %}
7248 opcode(0x0F,0x40);
7249 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7250 ins_pipe( pipe_cmov_reg );
7251 %}
7252
7253 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7254 predicate(VM_Version::supports_cmov() );
7255 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7256 ins_cost(200);
7257 expand %{
7258 cmovI_regU(cop, cr, dst, src);
7259 %}
7260 %}
7261
7262 // Conditional move
7263 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7264 predicate(VM_Version::supports_cmov() );
7265 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7266 ins_cost(250);
7267 format %{ "CMOV$cop $dst,$src" %}
7268 opcode(0x0F,0x40);
7269 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7270 ins_pipe( pipe_cmov_mem );
7271 %}
7272
7273 // Conditional move
7274 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7275 predicate(VM_Version::supports_cmov() );
7276 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7277 ins_cost(250);
7278 format %{ "CMOV$cop $dst,$src" %}
7279 opcode(0x0F,0x40);
7280 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7281 ins_pipe( pipe_cmov_mem );
7282 %}
7283
7284 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7285 predicate(VM_Version::supports_cmov() );
7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7287 ins_cost(250);
7288 expand %{
7289 cmovI_memU(cop, cr, dst, src);
7290 %}
7291 %}
7292
7293 // Conditional move
7294 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7295 predicate(VM_Version::supports_cmov() );
7296 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7297 ins_cost(200);
7298 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7299 opcode(0x0F,0x40);
7300 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7301 ins_pipe( pipe_cmov_reg );
7302 %}
7303
7304 // Conditional move (non-P6 version)
7305 // Note: a CMoveP is generated for stubs and native wrappers
7306 // regardless of whether we are on a P6, so we
7307 // emulate a cmov here
7308 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7309 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7310 ins_cost(300);
7311 format %{ "Jn$cop skip\n\t"
7312 "MOV $dst,$src\t# pointer\n"
7313 "skip:" %}
7314 opcode(0x8b);
7315 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7316 ins_pipe( pipe_cmov_reg );
7317 %}
7318
7319 // Conditional move
7320 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7321 predicate(VM_Version::supports_cmov() );
7322 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7323 ins_cost(200);
7324 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7325 opcode(0x0F,0x40);
7326 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7327 ins_pipe( pipe_cmov_reg );
7328 %}
7329
7330 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7331 predicate(VM_Version::supports_cmov() );
7332 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7333 ins_cost(200);
7334 expand %{
7335 cmovP_regU(cop, cr, dst, src);
7336 %}
7337 %}
7338
7339 // DISABLED: Requires the ADLC to emit a bottom_type call that
7340 // correctly meets the two pointer arguments; one is an incoming
7341 // register but the other is a memory operand. ALSO appears to
7342 // be buggy with implicit null checks.
7343 //
7344 //// Conditional move
7345 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7346 // predicate(VM_Version::supports_cmov() );
7347 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7348 // ins_cost(250);
7349 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7350 // opcode(0x0F,0x40);
7351 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7352 // ins_pipe( pipe_cmov_mem );
7353 //%}
7354 //
7355 //// Conditional move
7356 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7357 // predicate(VM_Version::supports_cmov() );
7358 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7359 // ins_cost(250);
7360 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7361 // opcode(0x0F,0x40);
7362 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7363 // ins_pipe( pipe_cmov_mem );
7364 //%}
7365
7366 // Conditional move
7367 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7368 predicate(UseSSE<=1);
7369 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7370 ins_cost(200);
7371 format %{ "FCMOV$cop $dst,$src\t# double" %}
7372 opcode(0xDA);
7373 ins_encode( enc_cmov_dpr(cop,src) );
7374 ins_pipe( pipe_cmovDPR_reg );
7375 %}
7376
7377 // Conditional move
7378 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7379 predicate(UseSSE==0);
7380 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7381 ins_cost(200);
7382 format %{ "FCMOV$cop $dst,$src\t# float" %}
7383 opcode(0xDA);
7384 ins_encode( enc_cmov_dpr(cop,src) );
7385 ins_pipe( pipe_cmovDPR_reg );
7386 %}
7387
7388 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7389 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7390 predicate(UseSSE<=1);
7391 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7392 ins_cost(200);
7393 format %{ "Jn$cop skip\n\t"
7394 "MOV $dst,$src\t# double\n"
7395 "skip:" %}
7396 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7397 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7398 ins_pipe( pipe_cmovDPR_reg );
7399 %}
7400
7401 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7402 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7403 predicate(UseSSE==0);
7404 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7405 ins_cost(200);
7406 format %{ "Jn$cop skip\n\t"
7407 "MOV $dst,$src\t# float\n"
7408 "skip:" %}
7409 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7410 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7411 ins_pipe( pipe_cmovDPR_reg );
7412 %}
7413
7414 // No CMOVE with SSE/SSE2
7415 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7416 predicate (UseSSE>=1);
7417 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7418 ins_cost(200);
7419 format %{ "Jn$cop skip\n\t"
7420 "MOVSS $dst,$src\t# float\n"
7421 "skip:" %}
7422 ins_encode %{
7423 Label skip;
7424 // Invert sense of branch from sense of CMOV
7425 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7426 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7427 __ bind(skip);
7428 %}
7429 ins_pipe( pipe_slow );
7430 %}
7431
7432 // No CMOVE with SSE/SSE2
7433 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7434 predicate (UseSSE>=2);
7435 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7436 ins_cost(200);
7437 format %{ "Jn$cop skip\n\t"
7438 "MOVSD $dst,$src\t# float\n"
7439 "skip:" %}
7440 ins_encode %{
7441 Label skip;
7442 // Invert sense of branch from sense of CMOV
7443 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7444 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7445 __ bind(skip);
7446 %}
7447 ins_pipe( pipe_slow );
7448 %}
7449
7450 // unsigned version
7451 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7452 predicate (UseSSE>=1);
7453 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7454 ins_cost(200);
7455 format %{ "Jn$cop skip\n\t"
7456 "MOVSS $dst,$src\t# float\n"
7457 "skip:" %}
7458 ins_encode %{
7459 Label skip;
7460 // Invert sense of branch from sense of CMOV
7461 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7462 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7463 __ bind(skip);
7464 %}
7465 ins_pipe( pipe_slow );
7466 %}
7467
7468 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7469 predicate (UseSSE>=1);
7470 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7471 ins_cost(200);
7472 expand %{
7473 fcmovF_regU(cop, cr, dst, src);
7474 %}
7475 %}
7476
7477 // unsigned version
7478 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7479 predicate (UseSSE>=2);
7480 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7481 ins_cost(200);
7482 format %{ "Jn$cop skip\n\t"
7483 "MOVSD $dst,$src\t# float\n"
7484 "skip:" %}
7485 ins_encode %{
7486 Label skip;
7487 // Invert sense of branch from sense of CMOV
7488 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7489 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7490 __ bind(skip);
7491 %}
7492 ins_pipe( pipe_slow );
7493 %}
7494
7495 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7496 predicate (UseSSE>=2);
7497 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7498 ins_cost(200);
7499 expand %{
7500 fcmovD_regU(cop, cr, dst, src);
7501 %}
7502 %}
7503
7504 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7505 predicate(VM_Version::supports_cmov() );
7506 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7507 ins_cost(200);
7508 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7509 "CMOV$cop $dst.hi,$src.hi" %}
7510 opcode(0x0F,0x40);
7511 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7512 ins_pipe( pipe_cmov_reg_long );
7513 %}
7514
7515 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7516 predicate(VM_Version::supports_cmov() );
7517 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7518 ins_cost(200);
7519 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7520 "CMOV$cop $dst.hi,$src.hi" %}
7521 opcode(0x0F,0x40);
7522 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7523 ins_pipe( pipe_cmov_reg_long );
7524 %}
7525
7526 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7527 predicate(VM_Version::supports_cmov() );
7528 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7529 ins_cost(200);
7530 expand %{
7531 cmovL_regU(cop, cr, dst, src);
7532 %}
7533 %}
7534
7535 //----------Arithmetic Instructions--------------------------------------------
7536 //----------Addition Instructions----------------------------------------------
7537
7538 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7539 %{
7540 match(AddExactI dst src);
7541 effect(DEF cr);
7542
7543 format %{ "ADD $dst, $src\t# addExact int" %}
7544 ins_encode %{
7545 __ addl($dst$$Register, $src$$Register);
7546 %}
7547 ins_pipe(ialu_reg_reg);
7548 %}
7549
7550 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7551 %{
7552 match(AddExactI dst src);
7553 effect(DEF cr);
7554
7555 format %{ "ADD $dst, $src\t# addExact int" %}
7556 ins_encode %{
7557 __ addl($dst$$Register, $src$$constant);
7558 %}
7559 ins_pipe(ialu_reg_reg);
7560 %}
7561
7562 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7563 %{
7564 match(AddExactI dst (LoadI src));
7565 effect(DEF cr);
7566
7567 ins_cost(125);
7568 format %{ "ADD $dst,$src\t# addExact int" %}
7569 ins_encode %{
7570 __ addl($dst$$Register, $src$$Address);
7571 %}
7572 ins_pipe( ialu_reg_mem );
7573 %}
7574
7575
7576 // Integer Addition Instructions
7577 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7578 match(Set dst (AddI dst src));
7579 effect(KILL cr);
7580
7581 size(2);
7582 format %{ "ADD $dst,$src" %}
7583 opcode(0x03);
7584 ins_encode( OpcP, RegReg( dst, src) );
7585 ins_pipe( ialu_reg_reg );
7586 %}
7587
7588 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7589 match(Set dst (AddI dst src));
7590 effect(KILL cr);
7591
7592 format %{ "ADD $dst,$src" %}
7593 opcode(0x81, 0x00); /* /0 id */
7594 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7595 ins_pipe( ialu_reg );
7596 %}
7597
7598 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7599 predicate(UseIncDec);
7600 match(Set dst (AddI dst src));
7601 effect(KILL cr);
7602
7603 size(1);
7604 format %{ "INC $dst" %}
7605 opcode(0x40); /* */
7606 ins_encode( Opc_plus( primary, dst ) );
7607 ins_pipe( ialu_reg );
7608 %}
7609
7610 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7611 match(Set dst (AddI src0 src1));
7612 ins_cost(110);
7613
7614 format %{ "LEA $dst,[$src0 + $src1]" %}
7615 opcode(0x8D); /* 0x8D /r */
7616 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7617 ins_pipe( ialu_reg_reg );
7618 %}
7619
7620 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7621 match(Set dst (AddP src0 src1));
7622 ins_cost(110);
7623
7624 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7625 opcode(0x8D); /* 0x8D /r */
7626 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7627 ins_pipe( ialu_reg_reg );
7628 %}
7629
7630 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7631 predicate(UseIncDec);
7632 match(Set dst (AddI dst src));
7633 effect(KILL cr);
7634
7635 size(1);
7636 format %{ "DEC $dst" %}
7637 opcode(0x48); /* */
7638 ins_encode( Opc_plus( primary, dst ) );
7639 ins_pipe( ialu_reg );
7640 %}
7641
7642 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7643 match(Set dst (AddP dst src));
7644 effect(KILL cr);
7645
7646 size(2);
7647 format %{ "ADD $dst,$src" %}
7648 opcode(0x03);
7649 ins_encode( OpcP, RegReg( dst, src) );
7650 ins_pipe( ialu_reg_reg );
7651 %}
7652
7653 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7654 match(Set dst (AddP dst src));
7655 effect(KILL cr);
7656
7657 format %{ "ADD $dst,$src" %}
7658 opcode(0x81,0x00); /* Opcode 81 /0 id */
7659 // ins_encode( RegImm( dst, src) );
7660 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7661 ins_pipe( ialu_reg );
7662 %}
7663
7664 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7665 match(Set dst (AddI dst (LoadI src)));
7666 effect(KILL cr);
7667
7668 ins_cost(125);
7669 format %{ "ADD $dst,$src" %}
7670 opcode(0x03);
7671 ins_encode( OpcP, RegMem( dst, src) );
7672 ins_pipe( ialu_reg_mem );
7673 %}
7674
7675 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7676 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7677 effect(KILL cr);
7678
7679 ins_cost(150);
7680 format %{ "ADD $dst,$src" %}
7681 opcode(0x01); /* Opcode 01 /r */
7682 ins_encode( OpcP, RegMem( src, dst ) );
7683 ins_pipe( ialu_mem_reg );
7684 %}
7685
7686 // Add Memory with Immediate
7687 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7688 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7689 effect(KILL cr);
7690
7691 ins_cost(125);
7692 format %{ "ADD $dst,$src" %}
7693 opcode(0x81); /* Opcode 81 /0 id */
7694 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7695 ins_pipe( ialu_mem_imm );
7696 %}
7697
7698 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7699 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7700 effect(KILL cr);
7701
7702 ins_cost(125);
7703 format %{ "INC $dst" %}
7704 opcode(0xFF); /* Opcode FF /0 */
7705 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7706 ins_pipe( ialu_mem_imm );
7707 %}
7708
7709 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7710 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7711 effect(KILL cr);
7712
7713 ins_cost(125);
7714 format %{ "DEC $dst" %}
7715 opcode(0xFF); /* Opcode FF /1 */
7716 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7717 ins_pipe( ialu_mem_imm );
7718 %}
7719
7720
7721 instruct checkCastPP( eRegP dst ) %{
7722 match(Set dst (CheckCastPP dst));
7723
7724 size(0);
7725 format %{ "#checkcastPP of $dst" %}
7726 ins_encode( /*empty encoding*/ );
7727 ins_pipe( empty );
7728 %}
7729
7730 instruct castPP( eRegP dst ) %{
7731 match(Set dst (CastPP dst));
7732 format %{ "#castPP of $dst" %}
7733 ins_encode( /*empty encoding*/ );
7734 ins_pipe( empty );
7735 %}
7736
7737 instruct castII( rRegI dst ) %{
7738 match(Set dst (CastII dst));
7739 format %{ "#castII of $dst" %}
7740 ins_encode( /*empty encoding*/ );
7741 ins_cost(0);
7742 ins_pipe( empty );
7743 %}
7744
7745
7746 // Load-locked - same as a regular pointer load when used with compare-swap
7747 instruct loadPLocked(eRegP dst, memory mem) %{
7748 match(Set dst (LoadPLocked mem));
7749
7750 ins_cost(125);
7751 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7752 opcode(0x8B);
7753 ins_encode( OpcP, RegMem(dst,mem));
7754 ins_pipe( ialu_reg_mem );
7755 %}
7756
7757 // Conditional-store of the updated heap-top.
7758 // Used during allocation of the shared heap.
7759 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7760 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7761 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7762 // EAX is killed if there is contention, but then it's also unused.
7763 // In the common case of no contention, EAX holds the new oop address.
7764 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7765 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7766 ins_pipe( pipe_cmpxchg );
7767 %}
7768
7769 // Conditional-store of an int value.
7770 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7771 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7772 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7773 effect(KILL oldval);
7774 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7775 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7776 ins_pipe( pipe_cmpxchg );
7777 %}
7778
7779 // Conditional-store of a long value.
7780 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7781 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7782 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7783 effect(KILL oldval);
7784 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7785 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7786 "XCHG EBX,ECX"
7787 %}
7788 ins_encode %{
7789 // Note: we need to swap rbx, and rcx before and after the
7790 // cmpxchg8 instruction because the instruction uses
7791 // rcx as the high order word of the new value to store but
7792 // our register encoding uses rbx.
7793 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7794 if( os::is_MP() )
7795 __ lock();
7796 __ cmpxchg8($mem$$Address);
7797 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7798 %}
7799 ins_pipe( pipe_cmpxchg );
7800 %}
7801
7802 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7803
7804 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7805 predicate(VM_Version::supports_cx8());
7806 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7807 effect(KILL cr, KILL oldval);
7808 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7809 "MOV $res,0\n\t"
7810 "JNE,s fail\n\t"
7811 "MOV $res,1\n"
7812 "fail:" %}
7813 ins_encode( enc_cmpxchg8(mem_ptr),
7814 enc_flags_ne_to_boolean(res) );
7815 ins_pipe( pipe_cmpxchg );
7816 %}
7817
7818 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7819 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7820 effect(KILL cr, KILL oldval);
7821 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7822 "MOV $res,0\n\t"
7823 "JNE,s fail\n\t"
7824 "MOV $res,1\n"
7825 "fail:" %}
7826 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7827 ins_pipe( pipe_cmpxchg );
7828 %}
7829
7830 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7831 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7832 effect(KILL cr, KILL oldval);
7833 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7834 "MOV $res,0\n\t"
7835 "JNE,s fail\n\t"
7836 "MOV $res,1\n"
7837 "fail:" %}
7838 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7839 ins_pipe( pipe_cmpxchg );
7840 %}
7841
7842 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7843 predicate(n->as_LoadStore()->result_not_used());
7844 match(Set dummy (GetAndAddI mem add));
7845 effect(KILL cr);
7846 format %{ "ADDL [$mem],$add" %}
7847 ins_encode %{
7848 if (os::is_MP()) { __ lock(); }
7849 __ addl($mem$$Address, $add$$constant);
7850 %}
7851 ins_pipe( pipe_cmpxchg );
7852 %}
7853
7854 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7855 match(Set newval (GetAndAddI mem newval));
7856 effect(KILL cr);
7857 format %{ "XADDL [$mem],$newval" %}
7858 ins_encode %{
7859 if (os::is_MP()) { __ lock(); }
7860 __ xaddl($mem$$Address, $newval$$Register);
7861 %}
7862 ins_pipe( pipe_cmpxchg );
7863 %}
7864
7865 instruct xchgI( memory mem, rRegI newval) %{
7866 match(Set newval (GetAndSetI mem newval));
7867 format %{ "XCHGL $newval,[$mem]" %}
7868 ins_encode %{
7869 __ xchgl($newval$$Register, $mem$$Address);
7870 %}
7871 ins_pipe( pipe_cmpxchg );
7872 %}
7873
7874 instruct xchgP( memory mem, pRegP newval) %{
7875 match(Set newval (GetAndSetP mem newval));
7876 format %{ "XCHGL $newval,[$mem]" %}
7877 ins_encode %{
7878 __ xchgl($newval$$Register, $mem$$Address);
7879 %}
7880 ins_pipe( pipe_cmpxchg );
7881 %}
7882
7883 //----------Subtraction Instructions-------------------------------------------
7884
7885 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7886 %{
7887 match(SubExactI dst src);
7888 effect(DEF cr);
7889
7890 format %{ "SUB $dst, $src\t# subExact int" %}
7891 ins_encode %{
7892 __ subl($dst$$Register, $src$$Register);
7893 %}
7894 ins_pipe(ialu_reg_reg);
7895 %}
7896
7897 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7898 %{
7899 match(SubExactI dst src);
7900 effect(DEF cr);
7901
7902 format %{ "SUB $dst, $src\t# subExact int" %}
7903 ins_encode %{
7904 __ subl($dst$$Register, $src$$constant);
7905 %}
7906 ins_pipe(ialu_reg_reg);
7907 %}
7908
7909 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7910 %{
7911 match(SubExactI dst (LoadI src));
7912 effect(DEF cr);
7913
7914 ins_cost(125);
7915 format %{ "SUB $dst,$src\t# subExact int" %}
7916 ins_encode %{
7917 __ subl($dst$$Register, $src$$Address);
7918 %}
7919 ins_pipe( ialu_reg_mem );
7920 %}
7921
7922 // Integer Subtraction Instructions
7923 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7924 match(Set dst (SubI dst src));
7925 effect(KILL cr);
7926
7927 size(2);
7928 format %{ "SUB $dst,$src" %}
7929 opcode(0x2B);
7930 ins_encode( OpcP, RegReg( dst, src) );
7931 ins_pipe( ialu_reg_reg );
7932 %}
7933
7934 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7935 match(Set dst (SubI dst src));
7936 effect(KILL cr);
7937
7938 format %{ "SUB $dst,$src" %}
7939 opcode(0x81,0x05); /* Opcode 81 /5 */
7940 // ins_encode( RegImm( dst, src) );
7941 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7942 ins_pipe( ialu_reg );
7943 %}
7944
7945 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7946 match(Set dst (SubI dst (LoadI src)));
7947 effect(KILL cr);
7948
7949 ins_cost(125);
7950 format %{ "SUB $dst,$src" %}
7951 opcode(0x2B);
7952 ins_encode( OpcP, RegMem( dst, src) );
7953 ins_pipe( ialu_reg_mem );
7954 %}
7955
7956 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7957 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7958 effect(KILL cr);
7959
7960 ins_cost(150);
7961 format %{ "SUB $dst,$src" %}
7962 opcode(0x29); /* Opcode 29 /r */
7963 ins_encode( OpcP, RegMem( src, dst ) );
7964 ins_pipe( ialu_mem_reg );
7965 %}
7966
7967 // Subtract from a pointer
7968 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7969 match(Set dst (AddP dst (SubI zero src)));
7970 effect(KILL cr);
7971
7972 size(2);
7973 format %{ "SUB $dst,$src" %}
7974 opcode(0x2B);
7975 ins_encode( OpcP, RegReg( dst, src) );
7976 ins_pipe( ialu_reg_reg );
7977 %}
7978
7979 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7980 match(Set dst (SubI zero dst));
7981 effect(KILL cr);
7982
7983 size(2);
7984 format %{ "NEG $dst" %}
7985 opcode(0xF7,0x03); // Opcode F7 /3
7986 ins_encode( OpcP, RegOpc( dst ) );
7987 ins_pipe( ialu_reg );
7988 %}
7989
7990 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
7991 match(NegExactI dst);
7992 effect(DEF cr);
7993
7994 format %{ "NEG $dst\t# negExact int"%}
7995 ins_encode %{
7996 __ negl($dst$$Register);
7997 %}
7998 ins_pipe(ialu_reg);
7999 %}
8000
8001 //----------Multiplication/Division Instructions-------------------------------
8002 // Integer Multiplication Instructions
8003 // Multiply Register
8004 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8005 match(Set dst (MulI dst src));
8006 effect(KILL cr);
8007
8008 size(3);
8009 ins_cost(300);
8010 format %{ "IMUL $dst,$src" %}
8011 opcode(0xAF, 0x0F);
8012 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8013 ins_pipe( ialu_reg_reg_alu0 );
8014 %}
8015
8016 // Multiply 32-bit Immediate
8017 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8018 match(Set dst (MulI src imm));
8019 effect(KILL cr);
8020
8021 ins_cost(300);
8022 format %{ "IMUL $dst,$src,$imm" %}
8023 opcode(0x69); /* 69 /r id */
8024 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8025 ins_pipe( ialu_reg_reg_alu0 );
8026 %}
8027
8028 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8029 match(Set dst src);
8030 effect(KILL cr);
8031
8032 // Note that this is artificially increased to make it more expensive than loadConL
8033 ins_cost(250);
8034 format %{ "MOV EAX,$src\t// low word only" %}
8035 opcode(0xB8);
8036 ins_encode( LdImmL_Lo(dst, src) );
8037 ins_pipe( ialu_reg_fat );
8038 %}
8039
8040 // Multiply by 32-bit Immediate, taking the shifted high order results
8041 // (special case for shift by 32)
8042 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8043 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8044 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8045 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8046 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8047 effect(USE src1, KILL cr);
8048
8049 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8050 ins_cost(0*100 + 1*400 - 150);
8051 format %{ "IMUL EDX:EAX,$src1" %}
8052 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8053 ins_pipe( pipe_slow );
8054 %}
8055
8056 // Multiply by 32-bit Immediate, taking the shifted high order results
8057 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8058 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8059 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8060 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8061 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8062 effect(USE src1, KILL cr);
8063
8064 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8065 ins_cost(1*100 + 1*400 - 150);
8066 format %{ "IMUL EDX:EAX,$src1\n\t"
8067 "SAR EDX,$cnt-32" %}
8068 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8069 ins_pipe( pipe_slow );
8070 %}
8071
8072 // Multiply Memory 32-bit Immediate
8073 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8074 match(Set dst (MulI (LoadI src) imm));
8075 effect(KILL cr);
8076
8077 ins_cost(300);
8078 format %{ "IMUL $dst,$src,$imm" %}
8079 opcode(0x69); /* 69 /r id */
8080 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8081 ins_pipe( ialu_reg_mem_alu0 );
8082 %}
8083
8084 // Multiply Memory
8085 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8086 match(Set dst (MulI dst (LoadI src)));
8087 effect(KILL cr);
8088
8089 ins_cost(350);
8090 format %{ "IMUL $dst,$src" %}
8091 opcode(0xAF, 0x0F);
8092 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8093 ins_pipe( ialu_reg_mem_alu0 );
8094 %}
8095
8096 // Multiply Register Int to Long
8097 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8098 // Basic Idea: long = (long)int * (long)int
8099 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8100 effect(DEF dst, USE src, USE src1, KILL flags);
8101
8102 ins_cost(300);
8103 format %{ "IMUL $dst,$src1" %}
8104
8105 ins_encode( long_int_multiply( dst, src1 ) );
8106 ins_pipe( ialu_reg_reg_alu0 );
8107 %}
8108
8109 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8110 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8111 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8112 effect(KILL flags);
8113
8114 ins_cost(300);
8115 format %{ "MUL $dst,$src1" %}
8116
8117 ins_encode( long_uint_multiply(dst, src1) );
8118 ins_pipe( ialu_reg_reg_alu0 );
8119 %}
8120
8121 // Multiply Register Long
8122 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8123 match(Set dst (MulL dst src));
8124 effect(KILL cr, TEMP tmp);
8125 ins_cost(4*100+3*400);
8126 // Basic idea: lo(result) = lo(x_lo * y_lo)
8127 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8128 format %{ "MOV $tmp,$src.lo\n\t"
8129 "IMUL $tmp,EDX\n\t"
8130 "MOV EDX,$src.hi\n\t"
8131 "IMUL EDX,EAX\n\t"
8132 "ADD $tmp,EDX\n\t"
8133 "MUL EDX:EAX,$src.lo\n\t"
8134 "ADD EDX,$tmp" %}
8135 ins_encode( long_multiply( dst, src, tmp ) );
8136 ins_pipe( pipe_slow );
8137 %}
8138
8139 // Multiply Register Long where the left operand's high 32 bits are zero
8140 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8141 predicate(is_operand_hi32_zero(n->in(1)));
8142 match(Set dst (MulL dst src));
8143 effect(KILL cr, TEMP tmp);
8144 ins_cost(2*100+2*400);
8145 // Basic idea: lo(result) = lo(x_lo * y_lo)
8146 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8147 format %{ "MOV $tmp,$src.hi\n\t"
8148 "IMUL $tmp,EAX\n\t"
8149 "MUL EDX:EAX,$src.lo\n\t"
8150 "ADD EDX,$tmp" %}
8151 ins_encode %{
8152 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8153 __ imull($tmp$$Register, rax);
8154 __ mull($src$$Register);
8155 __ addl(rdx, $tmp$$Register);
8156 %}
8157 ins_pipe( pipe_slow );
8158 %}
8159
8160 // Multiply Register Long where the right operand's high 32 bits are zero
8161 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8162 predicate(is_operand_hi32_zero(n->in(2)));
8163 match(Set dst (MulL dst src));
8164 effect(KILL cr, TEMP tmp);
8165 ins_cost(2*100+2*400);
8166 // Basic idea: lo(result) = lo(x_lo * y_lo)
8167 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8168 format %{ "MOV $tmp,$src.lo\n\t"
8169 "IMUL $tmp,EDX\n\t"
8170 "MUL EDX:EAX,$src.lo\n\t"
8171 "ADD EDX,$tmp" %}
8172 ins_encode %{
8173 __ movl($tmp$$Register, $src$$Register);
8174 __ imull($tmp$$Register, rdx);
8175 __ mull($src$$Register);
8176 __ addl(rdx, $tmp$$Register);
8177 %}
8178 ins_pipe( pipe_slow );
8179 %}
8180
8181 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8182 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8183 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8184 match(Set dst (MulL dst src));
8185 effect(KILL cr);
8186 ins_cost(1*400);
8187 // Basic idea: lo(result) = lo(x_lo * y_lo)
8188 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8189 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8190 ins_encode %{
8191 __ mull($src$$Register);
8192 %}
8193 ins_pipe( pipe_slow );
8194 %}
8195
8196 // Multiply Register Long by small constant
8197 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8198 match(Set dst (MulL dst src));
8199 effect(KILL cr, TEMP tmp);
8200 ins_cost(2*100+2*400);
8201 size(12);
8202 // Basic idea: lo(result) = lo(src * EAX)
8203 // hi(result) = hi(src * EAX) + lo(src * EDX)
8204 format %{ "IMUL $tmp,EDX,$src\n\t"
8205 "MOV EDX,$src\n\t"
8206 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8207 "ADD EDX,$tmp" %}
8208 ins_encode( long_multiply_con( dst, src, tmp ) );
8209 ins_pipe( pipe_slow );
8210 %}
8211
8212 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8213 %{
8214 match(MulExactI dst src);
8215 effect(DEF cr);
8216
8217 ins_cost(300);
8218 format %{ "IMUL $dst, $src\t# mulExact int" %}
8219 ins_encode %{
8220 __ imull($dst$$Register, $src$$Register);
8221 %}
8222 ins_pipe(ialu_reg_reg_alu0);
8223 %}
8224
8225 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8226 %{
8227 match(MulExactI src imm);
8228 effect(DEF cr);
8229
8230 ins_cost(300);
8231 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8232 ins_encode %{
8233 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8234 %}
8235 ins_pipe(ialu_reg_reg_alu0);
8236 %}
8237
8238 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8239 %{
8240 match(MulExactI dst (LoadI src));
8241 effect(DEF cr);
8242
8243 ins_cost(350);
8244 format %{ "IMUL $dst, $src\t# mulExact int" %}
8245 ins_encode %{
8246 __ imull($dst$$Register, $src$$Address);
8247 %}
8248 ins_pipe(ialu_reg_mem_alu0);
8249 %}
8250
8251
8252 // Integer DIV with Register
8253 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8254 match(Set rax (DivI rax div));
8255 effect(KILL rdx, KILL cr);
8256 size(26);
8257 ins_cost(30*100+10*100);
8258 format %{ "CMP EAX,0x80000000\n\t"
8259 "JNE,s normal\n\t"
8260 "XOR EDX,EDX\n\t"
8261 "CMP ECX,-1\n\t"
8262 "JE,s done\n"
8263 "normal: CDQ\n\t"
8264 "IDIV $div\n\t"
8265 "done:" %}
8266 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8267 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8268 ins_pipe( ialu_reg_reg_alu0 );
8269 %}
8270
8271 // Divide Register Long
8272 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8273 match(Set dst (DivL src1 src2));
8274 effect( KILL cr, KILL cx, KILL bx );
8275 ins_cost(10000);
8276 format %{ "PUSH $src1.hi\n\t"
8277 "PUSH $src1.lo\n\t"
8278 "PUSH $src2.hi\n\t"
8279 "PUSH $src2.lo\n\t"
8280 "CALL SharedRuntime::ldiv\n\t"
8281 "ADD ESP,16" %}
8282 ins_encode( long_div(src1,src2) );
8283 ins_pipe( pipe_slow );
8284 %}
8285
8286 // Integer DIVMOD with Register, both quotient and mod results
8287 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8288 match(DivModI rax div);
8289 effect(KILL cr);
8290 size(26);
8291 ins_cost(30*100+10*100);
8292 format %{ "CMP EAX,0x80000000\n\t"
8293 "JNE,s normal\n\t"
8294 "XOR EDX,EDX\n\t"
8295 "CMP ECX,-1\n\t"
8296 "JE,s done\n"
8297 "normal: CDQ\n\t"
8298 "IDIV $div\n\t"
8299 "done:" %}
8300 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8301 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8302 ins_pipe( pipe_slow );
8303 %}
8304
8305 // Integer MOD with Register
8306 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8307 match(Set rdx (ModI rax div));
8308 effect(KILL rax, KILL cr);
8309
8310 size(26);
8311 ins_cost(300);
8312 format %{ "CDQ\n\t"
8313 "IDIV $div" %}
8314 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8315 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8316 ins_pipe( ialu_reg_reg_alu0 );
8317 %}
8318
8319 // Remainder Register Long
8320 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8321 match(Set dst (ModL src1 src2));
8322 effect( KILL cr, KILL cx, KILL bx );
8323 ins_cost(10000);
8324 format %{ "PUSH $src1.hi\n\t"
8325 "PUSH $src1.lo\n\t"
8326 "PUSH $src2.hi\n\t"
8327 "PUSH $src2.lo\n\t"
8328 "CALL SharedRuntime::lrem\n\t"
8329 "ADD ESP,16" %}
8330 ins_encode( long_mod(src1,src2) );
8331 ins_pipe( pipe_slow );
8332 %}
8333
8334 // Divide Register Long (no special case since divisor != -1)
8335 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8336 match(Set dst (DivL dst imm));
8337 effect( TEMP tmp, TEMP tmp2, KILL cr );
8338 ins_cost(1000);
8339 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8340 "XOR $tmp2,$tmp2\n\t"
8341 "CMP $tmp,EDX\n\t"
8342 "JA,s fast\n\t"
8343 "MOV $tmp2,EAX\n\t"
8344 "MOV EAX,EDX\n\t"
8345 "MOV EDX,0\n\t"
8346 "JLE,s pos\n\t"
8347 "LNEG EAX : $tmp2\n\t"
8348 "DIV $tmp # unsigned division\n\t"
8349 "XCHG EAX,$tmp2\n\t"
8350 "DIV $tmp\n\t"
8351 "LNEG $tmp2 : EAX\n\t"
8352 "JMP,s done\n"
8353 "pos:\n\t"
8354 "DIV $tmp\n\t"
8355 "XCHG EAX,$tmp2\n"
8356 "fast:\n\t"
8357 "DIV $tmp\n"
8358 "done:\n\t"
8359 "MOV EDX,$tmp2\n\t"
8360 "NEG EDX:EAX # if $imm < 0" %}
8361 ins_encode %{
8362 int con = (int)$imm$$constant;
8363 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8364 int pcon = (con > 0) ? con : -con;
8365 Label Lfast, Lpos, Ldone;
8366
8367 __ movl($tmp$$Register, pcon);
8368 __ xorl($tmp2$$Register,$tmp2$$Register);
8369 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8370 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8371
8372 __ movl($tmp2$$Register, $dst$$Register); // save
8373 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8374 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8375 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8376
8377 // Negative dividend.
8378 // convert value to positive to use unsigned division
8379 __ lneg($dst$$Register, $tmp2$$Register);
8380 __ divl($tmp$$Register);
8381 __ xchgl($dst$$Register, $tmp2$$Register);
8382 __ divl($tmp$$Register);
8383 // revert result back to negative
8384 __ lneg($tmp2$$Register, $dst$$Register);
8385 __ jmpb(Ldone);
8386
8387 __ bind(Lpos);
8388 __ divl($tmp$$Register); // Use unsigned division
8389 __ xchgl($dst$$Register, $tmp2$$Register);
8390 // Fallthrow for final divide, tmp2 has 32 bit hi result
8391
8392 __ bind(Lfast);
8393 // fast path: src is positive
8394 __ divl($tmp$$Register); // Use unsigned division
8395
8396 __ bind(Ldone);
8397 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8398 if (con < 0) {
8399 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8400 }
8401 %}
8402 ins_pipe( pipe_slow );
8403 %}
8404
8405 // Remainder Register Long (remainder fit into 32 bits)
8406 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8407 match(Set dst (ModL dst imm));
8408 effect( TEMP tmp, TEMP tmp2, KILL cr );
8409 ins_cost(1000);
8410 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8411 "CMP $tmp,EDX\n\t"
8412 "JA,s fast\n\t"
8413 "MOV $tmp2,EAX\n\t"
8414 "MOV EAX,EDX\n\t"
8415 "MOV EDX,0\n\t"
8416 "JLE,s pos\n\t"
8417 "LNEG EAX : $tmp2\n\t"
8418 "DIV $tmp # unsigned division\n\t"
8419 "MOV EAX,$tmp2\n\t"
8420 "DIV $tmp\n\t"
8421 "NEG EDX\n\t"
8422 "JMP,s done\n"
8423 "pos:\n\t"
8424 "DIV $tmp\n\t"
8425 "MOV EAX,$tmp2\n"
8426 "fast:\n\t"
8427 "DIV $tmp\n"
8428 "done:\n\t"
8429 "MOV EAX,EDX\n\t"
8430 "SAR EDX,31\n\t" %}
8431 ins_encode %{
8432 int con = (int)$imm$$constant;
8433 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8434 int pcon = (con > 0) ? con : -con;
8435 Label Lfast, Lpos, Ldone;
8436
8437 __ movl($tmp$$Register, pcon);
8438 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8439 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8440
8441 __ movl($tmp2$$Register, $dst$$Register); // save
8442 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8443 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8444 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8445
8446 // Negative dividend.
8447 // convert value to positive to use unsigned division
8448 __ lneg($dst$$Register, $tmp2$$Register);
8449 __ divl($tmp$$Register);
8450 __ movl($dst$$Register, $tmp2$$Register);
8451 __ divl($tmp$$Register);
8452 // revert remainder back to negative
8453 __ negl(HIGH_FROM_LOW($dst$$Register));
8454 __ jmpb(Ldone);
8455
8456 __ bind(Lpos);
8457 __ divl($tmp$$Register);
8458 __ movl($dst$$Register, $tmp2$$Register);
8459
8460 __ bind(Lfast);
8461 // fast path: src is positive
8462 __ divl($tmp$$Register);
8463
8464 __ bind(Ldone);
8465 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8466 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8467
8468 %}
8469 ins_pipe( pipe_slow );
8470 %}
8471
8472 // Integer Shift Instructions
8473 // Shift Left by one
8474 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8475 match(Set dst (LShiftI dst shift));
8476 effect(KILL cr);
8477
8478 size(2);
8479 format %{ "SHL $dst,$shift" %}
8480 opcode(0xD1, 0x4); /* D1 /4 */
8481 ins_encode( OpcP, RegOpc( dst ) );
8482 ins_pipe( ialu_reg );
8483 %}
8484
8485 // Shift Left by 8-bit immediate
8486 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8487 match(Set dst (LShiftI dst shift));
8488 effect(KILL cr);
8489
8490 size(3);
8491 format %{ "SHL $dst,$shift" %}
8492 opcode(0xC1, 0x4); /* C1 /4 ib */
8493 ins_encode( RegOpcImm( dst, shift) );
8494 ins_pipe( ialu_reg );
8495 %}
8496
8497 // Shift Left by variable
8498 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8499 match(Set dst (LShiftI dst shift));
8500 effect(KILL cr);
8501
8502 size(2);
8503 format %{ "SHL $dst,$shift" %}
8504 opcode(0xD3, 0x4); /* D3 /4 */
8505 ins_encode( OpcP, RegOpc( dst ) );
8506 ins_pipe( ialu_reg_reg );
8507 %}
8508
8509 // Arithmetic shift right by one
8510 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8511 match(Set dst (RShiftI dst shift));
8512 effect(KILL cr);
8513
8514 size(2);
8515 format %{ "SAR $dst,$shift" %}
8516 opcode(0xD1, 0x7); /* D1 /7 */
8517 ins_encode( OpcP, RegOpc( dst ) );
8518 ins_pipe( ialu_reg );
8519 %}
8520
8521 // Arithmetic shift right by one
8522 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8523 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8524 effect(KILL cr);
8525 format %{ "SAR $dst,$shift" %}
8526 opcode(0xD1, 0x7); /* D1 /7 */
8527 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8528 ins_pipe( ialu_mem_imm );
8529 %}
8530
8531 // Arithmetic Shift Right by 8-bit immediate
8532 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8533 match(Set dst (RShiftI dst shift));
8534 effect(KILL cr);
8535
8536 size(3);
8537 format %{ "SAR $dst,$shift" %}
8538 opcode(0xC1, 0x7); /* C1 /7 ib */
8539 ins_encode( RegOpcImm( dst, shift ) );
8540 ins_pipe( ialu_mem_imm );
8541 %}
8542
8543 // Arithmetic Shift Right by 8-bit immediate
8544 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8545 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8546 effect(KILL cr);
8547
8548 format %{ "SAR $dst,$shift" %}
8549 opcode(0xC1, 0x7); /* C1 /7 ib */
8550 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8551 ins_pipe( ialu_mem_imm );
8552 %}
8553
8554 // Arithmetic Shift Right by variable
8555 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8556 match(Set dst (RShiftI dst shift));
8557 effect(KILL cr);
8558
8559 size(2);
8560 format %{ "SAR $dst,$shift" %}
8561 opcode(0xD3, 0x7); /* D3 /7 */
8562 ins_encode( OpcP, RegOpc( dst ) );
8563 ins_pipe( ialu_reg_reg );
8564 %}
8565
8566 // Logical shift right by one
8567 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8568 match(Set dst (URShiftI dst shift));
8569 effect(KILL cr);
8570
8571 size(2);
8572 format %{ "SHR $dst,$shift" %}
8573 opcode(0xD1, 0x5); /* D1 /5 */
8574 ins_encode( OpcP, RegOpc( dst ) );
8575 ins_pipe( ialu_reg );
8576 %}
8577
8578 // Logical Shift Right by 8-bit immediate
8579 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8580 match(Set dst (URShiftI dst shift));
8581 effect(KILL cr);
8582
8583 size(3);
8584 format %{ "SHR $dst,$shift" %}
8585 opcode(0xC1, 0x5); /* C1 /5 ib */
8586 ins_encode( RegOpcImm( dst, shift) );
8587 ins_pipe( ialu_reg );
8588 %}
8589
8590
8591 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8592 // This idiom is used by the compiler for the i2b bytecode.
8593 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8594 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8595
8596 size(3);
8597 format %{ "MOVSX $dst,$src :8" %}
8598 ins_encode %{
8599 __ movsbl($dst$$Register, $src$$Register);
8600 %}
8601 ins_pipe(ialu_reg_reg);
8602 %}
8603
8604 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8605 // This idiom is used by the compiler the i2s bytecode.
8606 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8607 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8608
8609 size(3);
8610 format %{ "MOVSX $dst,$src :16" %}
8611 ins_encode %{
8612 __ movswl($dst$$Register, $src$$Register);
8613 %}
8614 ins_pipe(ialu_reg_reg);
8615 %}
8616
8617
8618 // Logical Shift Right by variable
8619 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8620 match(Set dst (URShiftI dst shift));
8621 effect(KILL cr);
8622
8623 size(2);
8624 format %{ "SHR $dst,$shift" %}
8625 opcode(0xD3, 0x5); /* D3 /5 */
8626 ins_encode( OpcP, RegOpc( dst ) );
8627 ins_pipe( ialu_reg_reg );
8628 %}
8629
8630
8631 //----------Logical Instructions-----------------------------------------------
8632 //----------Integer Logical Instructions---------------------------------------
8633 // And Instructions
8634 // And Register with Register
8635 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8636 match(Set dst (AndI dst src));
8637 effect(KILL cr);
8638
8639 size(2);
8640 format %{ "AND $dst,$src" %}
8641 opcode(0x23);
8642 ins_encode( OpcP, RegReg( dst, src) );
8643 ins_pipe( ialu_reg_reg );
8644 %}
8645
8646 // And Register with Immediate
8647 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8648 match(Set dst (AndI dst src));
8649 effect(KILL cr);
8650
8651 format %{ "AND $dst,$src" %}
8652 opcode(0x81,0x04); /* Opcode 81 /4 */
8653 // ins_encode( RegImm( dst, src) );
8654 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8655 ins_pipe( ialu_reg );
8656 %}
8657
8658 // And Register with Memory
8659 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8660 match(Set dst (AndI dst (LoadI src)));
8661 effect(KILL cr);
8662
8663 ins_cost(125);
8664 format %{ "AND $dst,$src" %}
8665 opcode(0x23);
8666 ins_encode( OpcP, RegMem( dst, src) );
8667 ins_pipe( ialu_reg_mem );
8668 %}
8669
8670 // And Memory with Register
8671 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8672 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8673 effect(KILL cr);
8674
8675 ins_cost(150);
8676 format %{ "AND $dst,$src" %}
8677 opcode(0x21); /* Opcode 21 /r */
8678 ins_encode( OpcP, RegMem( src, dst ) );
8679 ins_pipe( ialu_mem_reg );
8680 %}
8681
8682 // And Memory with Immediate
8683 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8684 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8685 effect(KILL cr);
8686
8687 ins_cost(125);
8688 format %{ "AND $dst,$src" %}
8689 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8690 // ins_encode( MemImm( dst, src) );
8691 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8692 ins_pipe( ialu_mem_imm );
8693 %}
8694
8695 // Or Instructions
8696 // Or Register with Register
8697 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8698 match(Set dst (OrI dst src));
8699 effect(KILL cr);
8700
8701 size(2);
8702 format %{ "OR $dst,$src" %}
8703 opcode(0x0B);
8704 ins_encode( OpcP, RegReg( dst, src) );
8705 ins_pipe( ialu_reg_reg );
8706 %}
8707
8708 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8709 match(Set dst (OrI dst (CastP2X src)));
8710 effect(KILL cr);
8711
8712 size(2);
8713 format %{ "OR $dst,$src" %}
8714 opcode(0x0B);
8715 ins_encode( OpcP, RegReg( dst, src) );
8716 ins_pipe( ialu_reg_reg );
8717 %}
8718
8719
8720 // Or Register with Immediate
8721 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8722 match(Set dst (OrI dst src));
8723 effect(KILL cr);
8724
8725 format %{ "OR $dst,$src" %}
8726 opcode(0x81,0x01); /* Opcode 81 /1 id */
8727 // ins_encode( RegImm( dst, src) );
8728 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8729 ins_pipe( ialu_reg );
8730 %}
8731
8732 // Or Register with Memory
8733 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8734 match(Set dst (OrI dst (LoadI src)));
8735 effect(KILL cr);
8736
8737 ins_cost(125);
8738 format %{ "OR $dst,$src" %}
8739 opcode(0x0B);
8740 ins_encode( OpcP, RegMem( dst, src) );
8741 ins_pipe( ialu_reg_mem );
8742 %}
8743
8744 // Or Memory with Register
8745 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8746 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8747 effect(KILL cr);
8748
8749 ins_cost(150);
8750 format %{ "OR $dst,$src" %}
8751 opcode(0x09); /* Opcode 09 /r */
8752 ins_encode( OpcP, RegMem( src, dst ) );
8753 ins_pipe( ialu_mem_reg );
8754 %}
8755
8756 // Or Memory with Immediate
8757 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8758 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8759 effect(KILL cr);
8760
8761 ins_cost(125);
8762 format %{ "OR $dst,$src" %}
8763 opcode(0x81,0x1); /* Opcode 81 /1 id */
8764 // ins_encode( MemImm( dst, src) );
8765 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8766 ins_pipe( ialu_mem_imm );
8767 %}
8768
8769 // ROL/ROR
8770 // ROL expand
8771 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8772 effect(USE_DEF dst, USE shift, KILL cr);
8773
8774 format %{ "ROL $dst, $shift" %}
8775 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8776 ins_encode( OpcP, RegOpc( dst ));
8777 ins_pipe( ialu_reg );
8778 %}
8779
8780 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8781 effect(USE_DEF dst, USE shift, KILL cr);
8782
8783 format %{ "ROL $dst, $shift" %}
8784 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8785 ins_encode( RegOpcImm(dst, shift) );
8786 ins_pipe(ialu_reg);
8787 %}
8788
8789 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8790 effect(USE_DEF dst, USE shift, KILL cr);
8791
8792 format %{ "ROL $dst, $shift" %}
8793 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8794 ins_encode(OpcP, RegOpc(dst));
8795 ins_pipe( ialu_reg_reg );
8796 %}
8797 // end of ROL expand
8798
8799 // ROL 32bit by one once
8800 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8801 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8802
8803 expand %{
8804 rolI_eReg_imm1(dst, lshift, cr);
8805 %}
8806 %}
8807
8808 // ROL 32bit var by imm8 once
8809 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8810 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8811 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8812
8813 expand %{
8814 rolI_eReg_imm8(dst, lshift, cr);
8815 %}
8816 %}
8817
8818 // ROL 32bit var by var once
8819 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8820 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8821
8822 expand %{
8823 rolI_eReg_CL(dst, shift, cr);
8824 %}
8825 %}
8826
8827 // ROL 32bit var by var once
8828 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8829 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8830
8831 expand %{
8832 rolI_eReg_CL(dst, shift, cr);
8833 %}
8834 %}
8835
8836 // ROR expand
8837 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8838 effect(USE_DEF dst, USE shift, KILL cr);
8839
8840 format %{ "ROR $dst, $shift" %}
8841 opcode(0xD1,0x1); /* Opcode D1 /1 */
8842 ins_encode( OpcP, RegOpc( dst ) );
8843 ins_pipe( ialu_reg );
8844 %}
8845
8846 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8847 effect (USE_DEF dst, USE shift, KILL cr);
8848
8849 format %{ "ROR $dst, $shift" %}
8850 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8851 ins_encode( RegOpcImm(dst, shift) );
8852 ins_pipe( ialu_reg );
8853 %}
8854
8855 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8856 effect(USE_DEF dst, USE shift, KILL cr);
8857
8858 format %{ "ROR $dst, $shift" %}
8859 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8860 ins_encode(OpcP, RegOpc(dst));
8861 ins_pipe( ialu_reg_reg );
8862 %}
8863 // end of ROR expand
8864
8865 // ROR right once
8866 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8867 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8868
8869 expand %{
8870 rorI_eReg_imm1(dst, rshift, cr);
8871 %}
8872 %}
8873
8874 // ROR 32bit by immI8 once
8875 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8876 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8877 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8878
8879 expand %{
8880 rorI_eReg_imm8(dst, rshift, cr);
8881 %}
8882 %}
8883
8884 // ROR 32bit var by var once
8885 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8886 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8887
8888 expand %{
8889 rorI_eReg_CL(dst, shift, cr);
8890 %}
8891 %}
8892
8893 // ROR 32bit var by var once
8894 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8895 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8896
8897 expand %{
8898 rorI_eReg_CL(dst, shift, cr);
8899 %}
8900 %}
8901
8902 // Xor Instructions
8903 // Xor Register with Register
8904 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8905 match(Set dst (XorI dst src));
8906 effect(KILL cr);
8907
8908 size(2);
8909 format %{ "XOR $dst,$src" %}
8910 opcode(0x33);
8911 ins_encode( OpcP, RegReg( dst, src) );
8912 ins_pipe( ialu_reg_reg );
8913 %}
8914
8915 // Xor Register with Immediate -1
8916 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8917 match(Set dst (XorI dst imm));
8918
8919 size(2);
8920 format %{ "NOT $dst" %}
8921 ins_encode %{
8922 __ notl($dst$$Register);
8923 %}
8924 ins_pipe( ialu_reg );
8925 %}
8926
8927 // Xor Register with Immediate
8928 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8929 match(Set dst (XorI dst src));
8930 effect(KILL cr);
8931
8932 format %{ "XOR $dst,$src" %}
8933 opcode(0x81,0x06); /* Opcode 81 /6 id */
8934 // ins_encode( RegImm( dst, src) );
8935 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8936 ins_pipe( ialu_reg );
8937 %}
8938
8939 // Xor Register with Memory
8940 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8941 match(Set dst (XorI dst (LoadI src)));
8942 effect(KILL cr);
8943
8944 ins_cost(125);
8945 format %{ "XOR $dst,$src" %}
8946 opcode(0x33);
8947 ins_encode( OpcP, RegMem(dst, src) );
8948 ins_pipe( ialu_reg_mem );
8949 %}
8950
8951 // Xor Memory with Register
8952 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8953 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8954 effect(KILL cr);
8955
8956 ins_cost(150);
8957 format %{ "XOR $dst,$src" %}
8958 opcode(0x31); /* Opcode 31 /r */
8959 ins_encode( OpcP, RegMem( src, dst ) );
8960 ins_pipe( ialu_mem_reg );
8961 %}
8962
8963 // Xor Memory with Immediate
8964 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8965 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8966 effect(KILL cr);
8967
8968 ins_cost(125);
8969 format %{ "XOR $dst,$src" %}
8970 opcode(0x81,0x6); /* Opcode 81 /6 id */
8971 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8972 ins_pipe( ialu_mem_imm );
8973 %}
8974
8975 //----------Convert Int to Boolean---------------------------------------------
8976
8977 instruct movI_nocopy(rRegI dst, rRegI src) %{
8978 effect( DEF dst, USE src );
8979 format %{ "MOV $dst,$src" %}
8980 ins_encode( enc_Copy( dst, src) );
8981 ins_pipe( ialu_reg_reg );
8982 %}
8983
8984 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8985 effect( USE_DEF dst, USE src, KILL cr );
8986
8987 size(4);
8988 format %{ "NEG $dst\n\t"
8989 "ADC $dst,$src" %}
8990 ins_encode( neg_reg(dst),
8991 OpcRegReg(0x13,dst,src) );
8992 ins_pipe( ialu_reg_reg_long );
8993 %}
8994
8995 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8996 match(Set dst (Conv2B src));
8997
8998 expand %{
8999 movI_nocopy(dst,src);
9000 ci2b(dst,src,cr);
9001 %}
9002 %}
9003
9004 instruct movP_nocopy(rRegI dst, eRegP src) %{
9005 effect( DEF dst, USE src );
9006 format %{ "MOV $dst,$src" %}
9007 ins_encode( enc_Copy( dst, src) );
9008 ins_pipe( ialu_reg_reg );
9009 %}
9010
9011 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
9012 effect( USE_DEF dst, USE src, KILL cr );
9013 format %{ "NEG $dst\n\t"
9014 "ADC $dst,$src" %}
9015 ins_encode( neg_reg(dst),
9016 OpcRegReg(0x13,dst,src) );
9017 ins_pipe( ialu_reg_reg_long );
9018 %}
9019
9020 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
9021 match(Set dst (Conv2B src));
9022
9023 expand %{
9024 movP_nocopy(dst,src);
9025 cp2b(dst,src,cr);
9026 %}
9027 %}
9028
9029 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
9030 match(Set dst (CmpLTMask p q));
9031 effect(KILL cr);
9032 ins_cost(400);
9033
9034 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9035 format %{ "XOR $dst,$dst\n\t"
9036 "CMP $p,$q\n\t"
9037 "SETlt $dst\n\t"
9038 "NEG $dst" %}
9039 ins_encode %{
9040 Register Rp = $p$$Register;
9041 Register Rq = $q$$Register;
9042 Register Rd = $dst$$Register;
9043 Label done;
9044 __ xorl(Rd, Rd);
9045 __ cmpl(Rp, Rq);
9046 __ setb(Assembler::less, Rd);
9047 __ negl(Rd);
9048 %}
9049
9050 ins_pipe(pipe_slow);
9051 %}
9052
9053 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
9054 match(Set dst (CmpLTMask dst zero));
9055 effect(DEF dst, KILL cr);
9056 ins_cost(100);
9057
9058 format %{ "SAR $dst,31\t# cmpLTMask0" %}
9059 ins_encode %{
9060 __ sarl($dst$$Register, 31);
9061 %}
9062 ins_pipe(ialu_reg);
9063 %}
9064
9065 /* better to save a register than avoid a branch */
9066 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9067 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9068 effect(KILL cr);
9069 ins_cost(400);
9070 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
9071 "JGE done\n\t"
9072 "ADD $p,$y\n"
9073 "done: " %}
9074 ins_encode %{
9075 Register Rp = $p$$Register;
9076 Register Rq = $q$$Register;
9077 Register Ry = $y$$Register;
9078 Label done;
9079 __ subl(Rp, Rq);
9080 __ jccb(Assembler::greaterEqual, done);
9081 __ addl(Rp, Ry);
9082 __ bind(done);
9083 %}
9084
9085 ins_pipe(pipe_cmplt);
9086 %}
9087
9088 /* better to save a register than avoid a branch */
9089 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9090 match(Set y (AndI (CmpLTMask p q) y));
9091 effect(KILL cr);
9092
9093 ins_cost(300);
9094
9095 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
9096 "JLT done\n\t"
9097 "XORL $y, $y\n"
9098 "done: " %}
9099 ins_encode %{
9100 Register Rp = $p$$Register;
9101 Register Rq = $q$$Register;
9102 Register Ry = $y$$Register;
9103 Label done;
9104 __ cmpl(Rp, Rq);
9105 __ jccb(Assembler::less, done);
9106 __ xorl(Ry, Ry);
9107 __ bind(done);
9108 %}
9109
9110 ins_pipe(pipe_cmplt);
9111 %}
9112
9113 /* If I enable this, I encourage spilling in the inner loop of compress.
9114 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9115 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9116 */
9117
9118 //----------Long Instructions------------------------------------------------
9119 // Add Long Register with Register
9120 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9121 match(Set dst (AddL dst src));
9122 effect(KILL cr);
9123 ins_cost(200);
9124 format %{ "ADD $dst.lo,$src.lo\n\t"
9125 "ADC $dst.hi,$src.hi" %}
9126 opcode(0x03, 0x13);
9127 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9128 ins_pipe( ialu_reg_reg_long );
9129 %}
9130
9131 // Add Long Register with Immediate
9132 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9133 match(Set dst (AddL dst src));
9134 effect(KILL cr);
9135 format %{ "ADD $dst.lo,$src.lo\n\t"
9136 "ADC $dst.hi,$src.hi" %}
9137 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9138 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9139 ins_pipe( ialu_reg_long );
9140 %}
9141
9142 // Add Long Register with Memory
9143 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9144 match(Set dst (AddL dst (LoadL mem)));
9145 effect(KILL cr);
9146 ins_cost(125);
9147 format %{ "ADD $dst.lo,$mem\n\t"
9148 "ADC $dst.hi,$mem+4" %}
9149 opcode(0x03, 0x13);
9150 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9151 ins_pipe( ialu_reg_long_mem );
9152 %}
9153
9154 // Subtract Long Register with Register.
9155 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9156 match(Set dst (SubL dst src));
9157 effect(KILL cr);
9158 ins_cost(200);
9159 format %{ "SUB $dst.lo,$src.lo\n\t"
9160 "SBB $dst.hi,$src.hi" %}
9161 opcode(0x2B, 0x1B);
9162 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9163 ins_pipe( ialu_reg_reg_long );
9164 %}
9165
9166 // Subtract Long Register with Immediate
9167 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9168 match(Set dst (SubL dst src));
9169 effect(KILL cr);
9170 format %{ "SUB $dst.lo,$src.lo\n\t"
9171 "SBB $dst.hi,$src.hi" %}
9172 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9173 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9174 ins_pipe( ialu_reg_long );
9175 %}
9176
9177 // Subtract Long Register with Memory
9178 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9179 match(Set dst (SubL dst (LoadL mem)));
9180 effect(KILL cr);
9181 ins_cost(125);
9182 format %{ "SUB $dst.lo,$mem\n\t"
9183 "SBB $dst.hi,$mem+4" %}
9184 opcode(0x2B, 0x1B);
9185 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9186 ins_pipe( ialu_reg_long_mem );
9187 %}
9188
9189 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9190 match(Set dst (SubL zero dst));
9191 effect(KILL cr);
9192 ins_cost(300);
9193 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9194 ins_encode( neg_long(dst) );
9195 ins_pipe( ialu_reg_reg_long );
9196 %}
9197
9198 // And Long Register with Register
9199 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9200 match(Set dst (AndL dst src));
9201 effect(KILL cr);
9202 format %{ "AND $dst.lo,$src.lo\n\t"
9203 "AND $dst.hi,$src.hi" %}
9204 opcode(0x23,0x23);
9205 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9206 ins_pipe( ialu_reg_reg_long );
9207 %}
9208
9209 // And Long Register with Immediate
9210 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9211 match(Set dst (AndL dst src));
9212 effect(KILL cr);
9213 format %{ "AND $dst.lo,$src.lo\n\t"
9214 "AND $dst.hi,$src.hi" %}
9215 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9216 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9217 ins_pipe( ialu_reg_long );
9218 %}
9219
9220 // And Long Register with Memory
9221 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9222 match(Set dst (AndL dst (LoadL mem)));
9223 effect(KILL cr);
9224 ins_cost(125);
9225 format %{ "AND $dst.lo,$mem\n\t"
9226 "AND $dst.hi,$mem+4" %}
9227 opcode(0x23, 0x23);
9228 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9229 ins_pipe( ialu_reg_long_mem );
9230 %}
9231
9232 // Or Long Register with Register
9233 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9234 match(Set dst (OrL dst src));
9235 effect(KILL cr);
9236 format %{ "OR $dst.lo,$src.lo\n\t"
9237 "OR $dst.hi,$src.hi" %}
9238 opcode(0x0B,0x0B);
9239 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9240 ins_pipe( ialu_reg_reg_long );
9241 %}
9242
9243 // Or Long Register with Immediate
9244 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9245 match(Set dst (OrL dst src));
9246 effect(KILL cr);
9247 format %{ "OR $dst.lo,$src.lo\n\t"
9248 "OR $dst.hi,$src.hi" %}
9249 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9250 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9251 ins_pipe( ialu_reg_long );
9252 %}
9253
9254 // Or Long Register with Memory
9255 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9256 match(Set dst (OrL dst (LoadL mem)));
9257 effect(KILL cr);
9258 ins_cost(125);
9259 format %{ "OR $dst.lo,$mem\n\t"
9260 "OR $dst.hi,$mem+4" %}
9261 opcode(0x0B,0x0B);
9262 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9263 ins_pipe( ialu_reg_long_mem );
9264 %}
9265
9266 // Xor Long Register with Register
9267 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9268 match(Set dst (XorL dst src));
9269 effect(KILL cr);
9270 format %{ "XOR $dst.lo,$src.lo\n\t"
9271 "XOR $dst.hi,$src.hi" %}
9272 opcode(0x33,0x33);
9273 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9274 ins_pipe( ialu_reg_reg_long );
9275 %}
9276
9277 // Xor Long Register with Immediate -1
9278 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9279 match(Set dst (XorL dst imm));
9280 format %{ "NOT $dst.lo\n\t"
9281 "NOT $dst.hi" %}
9282 ins_encode %{
9283 __ notl($dst$$Register);
9284 __ notl(HIGH_FROM_LOW($dst$$Register));
9285 %}
9286 ins_pipe( ialu_reg_long );
9287 %}
9288
9289 // Xor Long Register with Immediate
9290 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9291 match(Set dst (XorL dst src));
9292 effect(KILL cr);
9293 format %{ "XOR $dst.lo,$src.lo\n\t"
9294 "XOR $dst.hi,$src.hi" %}
9295 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9296 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9297 ins_pipe( ialu_reg_long );
9298 %}
9299
9300 // Xor Long Register with Memory
9301 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9302 match(Set dst (XorL dst (LoadL mem)));
9303 effect(KILL cr);
9304 ins_cost(125);
9305 format %{ "XOR $dst.lo,$mem\n\t"
9306 "XOR $dst.hi,$mem+4" %}
9307 opcode(0x33,0x33);
9308 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9309 ins_pipe( ialu_reg_long_mem );
9310 %}
9311
9312 // Shift Left Long by 1
9313 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9314 predicate(UseNewLongLShift);
9315 match(Set dst (LShiftL dst cnt));
9316 effect(KILL cr);
9317 ins_cost(100);
9318 format %{ "ADD $dst.lo,$dst.lo\n\t"
9319 "ADC $dst.hi,$dst.hi" %}
9320 ins_encode %{
9321 __ addl($dst$$Register,$dst$$Register);
9322 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9323 %}
9324 ins_pipe( ialu_reg_long );
9325 %}
9326
9327 // Shift Left Long by 2
9328 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9329 predicate(UseNewLongLShift);
9330 match(Set dst (LShiftL dst cnt));
9331 effect(KILL cr);
9332 ins_cost(100);
9333 format %{ "ADD $dst.lo,$dst.lo\n\t"
9334 "ADC $dst.hi,$dst.hi\n\t"
9335 "ADD $dst.lo,$dst.lo\n\t"
9336 "ADC $dst.hi,$dst.hi" %}
9337 ins_encode %{
9338 __ addl($dst$$Register,$dst$$Register);
9339 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9340 __ addl($dst$$Register,$dst$$Register);
9341 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9342 %}
9343 ins_pipe( ialu_reg_long );
9344 %}
9345
9346 // Shift Left Long by 3
9347 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9348 predicate(UseNewLongLShift);
9349 match(Set dst (LShiftL dst cnt));
9350 effect(KILL cr);
9351 ins_cost(100);
9352 format %{ "ADD $dst.lo,$dst.lo\n\t"
9353 "ADC $dst.hi,$dst.hi\n\t"
9354 "ADD $dst.lo,$dst.lo\n\t"
9355 "ADC $dst.hi,$dst.hi\n\t"
9356 "ADD $dst.lo,$dst.lo\n\t"
9357 "ADC $dst.hi,$dst.hi" %}
9358 ins_encode %{
9359 __ addl($dst$$Register,$dst$$Register);
9360 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9361 __ addl($dst$$Register,$dst$$Register);
9362 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9363 __ addl($dst$$Register,$dst$$Register);
9364 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9365 %}
9366 ins_pipe( ialu_reg_long );
9367 %}
9368
9369 // Shift Left Long by 1-31
9370 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9371 match(Set dst (LShiftL dst cnt));
9372 effect(KILL cr);
9373 ins_cost(200);
9374 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9375 "SHL $dst.lo,$cnt" %}
9376 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9377 ins_encode( move_long_small_shift(dst,cnt) );
9378 ins_pipe( ialu_reg_long );
9379 %}
9380
9381 // Shift Left Long by 32-63
9382 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9383 match(Set dst (LShiftL dst cnt));
9384 effect(KILL cr);
9385 ins_cost(300);
9386 format %{ "MOV $dst.hi,$dst.lo\n"
9387 "\tSHL $dst.hi,$cnt-32\n"
9388 "\tXOR $dst.lo,$dst.lo" %}
9389 opcode(0xC1, 0x4); /* C1 /4 ib */
9390 ins_encode( move_long_big_shift_clr(dst,cnt) );
9391 ins_pipe( ialu_reg_long );
9392 %}
9393
9394 // Shift Left Long by variable
9395 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9396 match(Set dst (LShiftL dst shift));
9397 effect(KILL cr);
9398 ins_cost(500+200);
9399 size(17);
9400 format %{ "TEST $shift,32\n\t"
9401 "JEQ,s small\n\t"
9402 "MOV $dst.hi,$dst.lo\n\t"
9403 "XOR $dst.lo,$dst.lo\n"
9404 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9405 "SHL $dst.lo,$shift" %}
9406 ins_encode( shift_left_long( dst, shift ) );
9407 ins_pipe( pipe_slow );
9408 %}
9409
9410 // Shift Right Long by 1-31
9411 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9412 match(Set dst (URShiftL dst cnt));
9413 effect(KILL cr);
9414 ins_cost(200);
9415 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9416 "SHR $dst.hi,$cnt" %}
9417 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9418 ins_encode( move_long_small_shift(dst,cnt) );
9419 ins_pipe( ialu_reg_long );
9420 %}
9421
9422 // Shift Right Long by 32-63
9423 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9424 match(Set dst (URShiftL dst cnt));
9425 effect(KILL cr);
9426 ins_cost(300);
9427 format %{ "MOV $dst.lo,$dst.hi\n"
9428 "\tSHR $dst.lo,$cnt-32\n"
9429 "\tXOR $dst.hi,$dst.hi" %}
9430 opcode(0xC1, 0x5); /* C1 /5 ib */
9431 ins_encode( move_long_big_shift_clr(dst,cnt) );
9432 ins_pipe( ialu_reg_long );
9433 %}
9434
9435 // Shift Right Long by variable
9436 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9437 match(Set dst (URShiftL dst shift));
9438 effect(KILL cr);
9439 ins_cost(600);
9440 size(17);
9441 format %{ "TEST $shift,32\n\t"
9442 "JEQ,s small\n\t"
9443 "MOV $dst.lo,$dst.hi\n\t"
9444 "XOR $dst.hi,$dst.hi\n"
9445 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9446 "SHR $dst.hi,$shift" %}
9447 ins_encode( shift_right_long( dst, shift ) );
9448 ins_pipe( pipe_slow );
9449 %}
9450
9451 // Shift Right Long by 1-31
9452 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9453 match(Set dst (RShiftL dst cnt));
9454 effect(KILL cr);
9455 ins_cost(200);
9456 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9457 "SAR $dst.hi,$cnt" %}
9458 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9459 ins_encode( move_long_small_shift(dst,cnt) );
9460 ins_pipe( ialu_reg_long );
9461 %}
9462
9463 // Shift Right Long by 32-63
9464 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9465 match(Set dst (RShiftL dst cnt));
9466 effect(KILL cr);
9467 ins_cost(300);
9468 format %{ "MOV $dst.lo,$dst.hi\n"
9469 "\tSAR $dst.lo,$cnt-32\n"
9470 "\tSAR $dst.hi,31" %}
9471 opcode(0xC1, 0x7); /* C1 /7 ib */
9472 ins_encode( move_long_big_shift_sign(dst,cnt) );
9473 ins_pipe( ialu_reg_long );
9474 %}
9475
9476 // Shift Right arithmetic Long by variable
9477 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9478 match(Set dst (RShiftL dst shift));
9479 effect(KILL cr);
9480 ins_cost(600);
9481 size(18);
9482 format %{ "TEST $shift,32\n\t"
9483 "JEQ,s small\n\t"
9484 "MOV $dst.lo,$dst.hi\n\t"
9485 "SAR $dst.hi,31\n"
9486 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9487 "SAR $dst.hi,$shift" %}
9488 ins_encode( shift_right_arith_long( dst, shift ) );
9489 ins_pipe( pipe_slow );
9490 %}
9491
9492
9493 //----------Double Instructions------------------------------------------------
9494 // Double Math
9495
9496 // Compare & branch
9497
9498 // P6 version of float compare, sets condition codes in EFLAGS
9499 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9500 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9501 match(Set cr (CmpD src1 src2));
9502 effect(KILL rax);
9503 ins_cost(150);
9504 format %{ "FLD $src1\n\t"
9505 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9506 "JNP exit\n\t"
9507 "MOV ah,1 // saw a NaN, set CF\n\t"
9508 "SAHF\n"
9509 "exit:\tNOP // avoid branch to branch" %}
9510 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9511 ins_encode( Push_Reg_DPR(src1),
9512 OpcP, RegOpc(src2),
9513 cmpF_P6_fixup );
9514 ins_pipe( pipe_slow );
9515 %}
9516
9517 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9518 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9519 match(Set cr (CmpD src1 src2));
9520 ins_cost(150);
9521 format %{ "FLD $src1\n\t"
9522 "FUCOMIP ST,$src2 // P6 instruction" %}
9523 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9524 ins_encode( Push_Reg_DPR(src1),
9525 OpcP, RegOpc(src2));
9526 ins_pipe( pipe_slow );
9527 %}
9528
9529 // Compare & branch
9530 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9531 predicate(UseSSE<=1);
9532 match(Set cr (CmpD src1 src2));
9533 effect(KILL rax);
9534 ins_cost(200);
9535 format %{ "FLD $src1\n\t"
9536 "FCOMp $src2\n\t"
9537 "FNSTSW AX\n\t"
9538 "TEST AX,0x400\n\t"
9539 "JZ,s flags\n\t"
9540 "MOV AH,1\t# unordered treat as LT\n"
9541 "flags:\tSAHF" %}
9542 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9543 ins_encode( Push_Reg_DPR(src1),
9544 OpcP, RegOpc(src2),
9545 fpu_flags);
9546 ins_pipe( pipe_slow );
9547 %}
9548
9549 // Compare vs zero into -1,0,1
9550 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9551 predicate(UseSSE<=1);
9552 match(Set dst (CmpD3 src1 zero));
9553 effect(KILL cr, KILL rax);
9554 ins_cost(280);
9555 format %{ "FTSTD $dst,$src1" %}
9556 opcode(0xE4, 0xD9);
9557 ins_encode( Push_Reg_DPR(src1),
9558 OpcS, OpcP, PopFPU,
9559 CmpF_Result(dst));
9560 ins_pipe( pipe_slow );
9561 %}
9562
9563 // Compare into -1,0,1
9564 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9565 predicate(UseSSE<=1);
9566 match(Set dst (CmpD3 src1 src2));
9567 effect(KILL cr, KILL rax);
9568 ins_cost(300);
9569 format %{ "FCMPD $dst,$src1,$src2" %}
9570 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9571 ins_encode( Push_Reg_DPR(src1),
9572 OpcP, RegOpc(src2),
9573 CmpF_Result(dst));
9574 ins_pipe( pipe_slow );
9575 %}
9576
9577 // float compare and set condition codes in EFLAGS by XMM regs
9578 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9579 predicate(UseSSE>=2);
9580 match(Set cr (CmpD src1 src2));
9581 ins_cost(145);
9582 format %{ "UCOMISD $src1,$src2\n\t"
9583 "JNP,s exit\n\t"
9584 "PUSHF\t# saw NaN, set CF\n\t"
9585 "AND [rsp], #0xffffff2b\n\t"
9586 "POPF\n"
9587 "exit:" %}
9588 ins_encode %{
9589 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9590 emit_cmpfp_fixup(_masm);
9591 %}
9592 ins_pipe( pipe_slow );
9593 %}
9594
9595 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9596 predicate(UseSSE>=2);
9597 match(Set cr (CmpD src1 src2));
9598 ins_cost(100);
9599 format %{ "UCOMISD $src1,$src2" %}
9600 ins_encode %{
9601 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9602 %}
9603 ins_pipe( pipe_slow );
9604 %}
9605
9606 // float compare and set condition codes in EFLAGS by XMM regs
9607 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9608 predicate(UseSSE>=2);
9609 match(Set cr (CmpD src1 (LoadD src2)));
9610 ins_cost(145);
9611 format %{ "UCOMISD $src1,$src2\n\t"
9612 "JNP,s exit\n\t"
9613 "PUSHF\t# saw NaN, set CF\n\t"
9614 "AND [rsp], #0xffffff2b\n\t"
9615 "POPF\n"
9616 "exit:" %}
9617 ins_encode %{
9618 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9619 emit_cmpfp_fixup(_masm);
9620 %}
9621 ins_pipe( pipe_slow );
9622 %}
9623
9624 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9625 predicate(UseSSE>=2);
9626 match(Set cr (CmpD src1 (LoadD src2)));
9627 ins_cost(100);
9628 format %{ "UCOMISD $src1,$src2" %}
9629 ins_encode %{
9630 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9631 %}
9632 ins_pipe( pipe_slow );
9633 %}
9634
9635 // Compare into -1,0,1 in XMM
9636 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9637 predicate(UseSSE>=2);
9638 match(Set dst (CmpD3 src1 src2));
9639 effect(KILL cr);
9640 ins_cost(255);
9641 format %{ "UCOMISD $src1, $src2\n\t"
9642 "MOV $dst, #-1\n\t"
9643 "JP,s done\n\t"
9644 "JB,s done\n\t"
9645 "SETNE $dst\n\t"
9646 "MOVZB $dst, $dst\n"
9647 "done:" %}
9648 ins_encode %{
9649 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9650 emit_cmpfp3(_masm, $dst$$Register);
9651 %}
9652 ins_pipe( pipe_slow );
9653 %}
9654
9655 // Compare into -1,0,1 in XMM and memory
9656 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9657 predicate(UseSSE>=2);
9658 match(Set dst (CmpD3 src1 (LoadD src2)));
9659 effect(KILL cr);
9660 ins_cost(275);
9661 format %{ "UCOMISD $src1, $src2\n\t"
9662 "MOV $dst, #-1\n\t"
9663 "JP,s done\n\t"
9664 "JB,s done\n\t"
9665 "SETNE $dst\n\t"
9666 "MOVZB $dst, $dst\n"
9667 "done:" %}
9668 ins_encode %{
9669 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9670 emit_cmpfp3(_masm, $dst$$Register);
9671 %}
9672 ins_pipe( pipe_slow );
9673 %}
9674
9675
9676 instruct subDPR_reg(regDPR dst, regDPR src) %{
9677 predicate (UseSSE <=1);
9678 match(Set dst (SubD dst src));
9679
9680 format %{ "FLD $src\n\t"
9681 "DSUBp $dst,ST" %}
9682 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9683 ins_cost(150);
9684 ins_encode( Push_Reg_DPR(src),
9685 OpcP, RegOpc(dst) );
9686 ins_pipe( fpu_reg_reg );
9687 %}
9688
9689 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9690 predicate (UseSSE <=1);
9691 match(Set dst (RoundDouble (SubD src1 src2)));
9692 ins_cost(250);
9693
9694 format %{ "FLD $src2\n\t"
9695 "DSUB ST,$src1\n\t"
9696 "FSTP_D $dst\t# D-round" %}
9697 opcode(0xD8, 0x5);
9698 ins_encode( Push_Reg_DPR(src2),
9699 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9700 ins_pipe( fpu_mem_reg_reg );
9701 %}
9702
9703
9704 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9705 predicate (UseSSE <=1);
9706 match(Set dst (SubD dst (LoadD src)));
9707 ins_cost(150);
9708
9709 format %{ "FLD $src\n\t"
9710 "DSUBp $dst,ST" %}
9711 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9712 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9713 OpcP, RegOpc(dst) );
9714 ins_pipe( fpu_reg_mem );
9715 %}
9716
9717 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9718 predicate (UseSSE<=1);
9719 match(Set dst (AbsD src));
9720 ins_cost(100);
9721 format %{ "FABS" %}
9722 opcode(0xE1, 0xD9);
9723 ins_encode( OpcS, OpcP );
9724 ins_pipe( fpu_reg_reg );
9725 %}
9726
9727 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9728 predicate(UseSSE<=1);
9729 match(Set dst (NegD src));
9730 ins_cost(100);
9731 format %{ "FCHS" %}
9732 opcode(0xE0, 0xD9);
9733 ins_encode( OpcS, OpcP );
9734 ins_pipe( fpu_reg_reg );
9735 %}
9736
9737 instruct addDPR_reg(regDPR dst, regDPR src) %{
9738 predicate(UseSSE<=1);
9739 match(Set dst (AddD dst src));
9740 format %{ "FLD $src\n\t"
9741 "DADD $dst,ST" %}
9742 size(4);
9743 ins_cost(150);
9744 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9745 ins_encode( Push_Reg_DPR(src),
9746 OpcP, RegOpc(dst) );
9747 ins_pipe( fpu_reg_reg );
9748 %}
9749
9750
9751 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9752 predicate(UseSSE<=1);
9753 match(Set dst (RoundDouble (AddD src1 src2)));
9754 ins_cost(250);
9755
9756 format %{ "FLD $src2\n\t"
9757 "DADD ST,$src1\n\t"
9758 "FSTP_D $dst\t# D-round" %}
9759 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9760 ins_encode( Push_Reg_DPR(src2),
9761 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9762 ins_pipe( fpu_mem_reg_reg );
9763 %}
9764
9765
9766 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9767 predicate(UseSSE<=1);
9768 match(Set dst (AddD dst (LoadD src)));
9769 ins_cost(150);
9770
9771 format %{ "FLD $src\n\t"
9772 "DADDp $dst,ST" %}
9773 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9774 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9775 OpcP, RegOpc(dst) );
9776 ins_pipe( fpu_reg_mem );
9777 %}
9778
9779 // add-to-memory
9780 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9781 predicate(UseSSE<=1);
9782 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9783 ins_cost(150);
9784
9785 format %{ "FLD_D $dst\n\t"
9786 "DADD ST,$src\n\t"
9787 "FST_D $dst" %}
9788 opcode(0xDD, 0x0);
9789 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9790 Opcode(0xD8), RegOpc(src),
9791 set_instruction_start,
9792 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9793 ins_pipe( fpu_reg_mem );
9794 %}
9795
9796 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9797 predicate(UseSSE<=1);
9798 match(Set dst (AddD dst con));
9799 ins_cost(125);
9800 format %{ "FLD1\n\t"
9801 "DADDp $dst,ST" %}
9802 ins_encode %{
9803 __ fld1();
9804 __ faddp($dst$$reg);
9805 %}
9806 ins_pipe(fpu_reg);
9807 %}
9808
9809 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9810 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9811 match(Set dst (AddD dst con));
9812 ins_cost(200);
9813 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9814 "DADDp $dst,ST" %}
9815 ins_encode %{
9816 __ fld_d($constantaddress($con));
9817 __ faddp($dst$$reg);
9818 %}
9819 ins_pipe(fpu_reg_mem);
9820 %}
9821
9822 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9823 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9824 match(Set dst (RoundDouble (AddD src con)));
9825 ins_cost(200);
9826 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9827 "DADD ST,$src\n\t"
9828 "FSTP_D $dst\t# D-round" %}
9829 ins_encode %{
9830 __ fld_d($constantaddress($con));
9831 __ fadd($src$$reg);
9832 __ fstp_d(Address(rsp, $dst$$disp));
9833 %}
9834 ins_pipe(fpu_mem_reg_con);
9835 %}
9836
9837 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9838 predicate(UseSSE<=1);
9839 match(Set dst (MulD dst src));
9840 format %{ "FLD $src\n\t"
9841 "DMULp $dst,ST" %}
9842 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9843 ins_cost(150);
9844 ins_encode( Push_Reg_DPR(src),
9845 OpcP, RegOpc(dst) );
9846 ins_pipe( fpu_reg_reg );
9847 %}
9848
9849 // Strict FP instruction biases argument before multiply then
9850 // biases result to avoid double rounding of subnormals.
9851 //
9852 // scale arg1 by multiplying arg1 by 2^(-15360)
9853 // load arg2
9854 // multiply scaled arg1 by arg2
9855 // rescale product by 2^(15360)
9856 //
9857 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9858 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9859 match(Set dst (MulD dst src));
9860 ins_cost(1); // Select this instruction for all strict FP double multiplies
9861
9862 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9863 "DMULp $dst,ST\n\t"
9864 "FLD $src\n\t"
9865 "DMULp $dst,ST\n\t"
9866 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9867 "DMULp $dst,ST\n\t" %}
9868 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9869 ins_encode( strictfp_bias1(dst),
9870 Push_Reg_DPR(src),
9871 OpcP, RegOpc(dst),
9872 strictfp_bias2(dst) );
9873 ins_pipe( fpu_reg_reg );
9874 %}
9875
9876 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9877 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9878 match(Set dst (MulD dst con));
9879 ins_cost(200);
9880 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9881 "DMULp $dst,ST" %}
9882 ins_encode %{
9883 __ fld_d($constantaddress($con));
9884 __ fmulp($dst$$reg);
9885 %}
9886 ins_pipe(fpu_reg_mem);
9887 %}
9888
9889
9890 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9891 predicate( UseSSE<=1 );
9892 match(Set dst (MulD dst (LoadD src)));
9893 ins_cost(200);
9894 format %{ "FLD_D $src\n\t"
9895 "DMULp $dst,ST" %}
9896 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9897 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9898 OpcP, RegOpc(dst) );
9899 ins_pipe( fpu_reg_mem );
9900 %}
9901
9902 //
9903 // Cisc-alternate to reg-reg multiply
9904 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9905 predicate( UseSSE<=1 );
9906 match(Set dst (MulD src (LoadD mem)));
9907 ins_cost(250);
9908 format %{ "FLD_D $mem\n\t"
9909 "DMUL ST,$src\n\t"
9910 "FSTP_D $dst" %}
9911 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9912 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9913 OpcReg_FPR(src),
9914 Pop_Reg_DPR(dst) );
9915 ins_pipe( fpu_reg_reg_mem );
9916 %}
9917
9918
9919 // MACRO3 -- addDPR a mulDPR
9920 // This instruction is a '2-address' instruction in that the result goes
9921 // back to src2. This eliminates a move from the macro; possibly the
9922 // register allocator will have to add it back (and maybe not).
9923 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9924 predicate( UseSSE<=1 );
9925 match(Set src2 (AddD (MulD src0 src1) src2));
9926 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9927 "DMUL ST,$src1\n\t"
9928 "DADDp $src2,ST" %}
9929 ins_cost(250);
9930 opcode(0xDD); /* LoadD DD /0 */
9931 ins_encode( Push_Reg_FPR(src0),
9932 FMul_ST_reg(src1),
9933 FAddP_reg_ST(src2) );
9934 ins_pipe( fpu_reg_reg_reg );
9935 %}
9936
9937
9938 // MACRO3 -- subDPR a mulDPR
9939 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9940 predicate( UseSSE<=1 );
9941 match(Set src2 (SubD (MulD src0 src1) src2));
9942 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9943 "DMUL ST,$src1\n\t"
9944 "DSUBRp $src2,ST" %}
9945 ins_cost(250);
9946 ins_encode( Push_Reg_FPR(src0),
9947 FMul_ST_reg(src1),
9948 Opcode(0xDE), Opc_plus(0xE0,src2));
9949 ins_pipe( fpu_reg_reg_reg );
9950 %}
9951
9952
9953 instruct divDPR_reg(regDPR dst, regDPR src) %{
9954 predicate( UseSSE<=1 );
9955 match(Set dst (DivD dst src));
9956
9957 format %{ "FLD $src\n\t"
9958 "FDIVp $dst,ST" %}
9959 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9960 ins_cost(150);
9961 ins_encode( Push_Reg_DPR(src),
9962 OpcP, RegOpc(dst) );
9963 ins_pipe( fpu_reg_reg );
9964 %}
9965
9966 // Strict FP instruction biases argument before division then
9967 // biases result, to avoid double rounding of subnormals.
9968 //
9969 // scale dividend by multiplying dividend by 2^(-15360)
9970 // load divisor
9971 // divide scaled dividend by divisor
9972 // rescale quotient by 2^(15360)
9973 //
9974 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9975 predicate (UseSSE<=1);
9976 match(Set dst (DivD dst src));
9977 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9978 ins_cost(01);
9979
9980 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9981 "DMULp $dst,ST\n\t"
9982 "FLD $src\n\t"
9983 "FDIVp $dst,ST\n\t"
9984 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9985 "DMULp $dst,ST\n\t" %}
9986 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9987 ins_encode( strictfp_bias1(dst),
9988 Push_Reg_DPR(src),
9989 OpcP, RegOpc(dst),
9990 strictfp_bias2(dst) );
9991 ins_pipe( fpu_reg_reg );
9992 %}
9993
9994 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9995 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9996 match(Set dst (RoundDouble (DivD src1 src2)));
9997
9998 format %{ "FLD $src1\n\t"
9999 "FDIV ST,$src2\n\t"
10000 "FSTP_D $dst\t# D-round" %}
10001 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10002 ins_encode( Push_Reg_DPR(src1),
10003 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
10004 ins_pipe( fpu_mem_reg_reg );
10005 %}
10006
10007
10008 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
10009 predicate(UseSSE<=1);
10010 match(Set dst (ModD dst src));
10011 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10012
10013 format %{ "DMOD $dst,$src" %}
10014 ins_cost(250);
10015 ins_encode(Push_Reg_Mod_DPR(dst, src),
10016 emitModDPR(),
10017 Push_Result_Mod_DPR(src),
10018 Pop_Reg_DPR(dst));
10019 ins_pipe( pipe_slow );
10020 %}
10021
10022 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
10023 predicate(UseSSE>=2);
10024 match(Set dst (ModD src0 src1));
10025 effect(KILL rax, KILL cr);
10026
10027 format %{ "SUB ESP,8\t # DMOD\n"
10028 "\tMOVSD [ESP+0],$src1\n"
10029 "\tFLD_D [ESP+0]\n"
10030 "\tMOVSD [ESP+0],$src0\n"
10031 "\tFLD_D [ESP+0]\n"
10032 "loop:\tFPREM\n"
10033 "\tFWAIT\n"
10034 "\tFNSTSW AX\n"
10035 "\tSAHF\n"
10036 "\tJP loop\n"
10037 "\tFSTP_D [ESP+0]\n"
10038 "\tMOVSD $dst,[ESP+0]\n"
10039 "\tADD ESP,8\n"
10040 "\tFSTP ST0\t # Restore FPU Stack"
10041 %}
10042 ins_cost(250);
10043 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10044 ins_pipe( pipe_slow );
10045 %}
10046
10047 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10048 predicate (UseSSE<=1);
10049 match(Set dst (SinD src));
10050 ins_cost(1800);
10051 format %{ "DSIN $dst" %}
10052 opcode(0xD9, 0xFE);
10053 ins_encode( OpcP, OpcS );
10054 ins_pipe( pipe_slow );
10055 %}
10056
10057 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10058 predicate (UseSSE>=2);
10059 match(Set dst (SinD dst));
10060 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10061 ins_cost(1800);
10062 format %{ "DSIN $dst" %}
10063 opcode(0xD9, 0xFE);
10064 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10065 ins_pipe( pipe_slow );
10066 %}
10067
10068 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10069 predicate (UseSSE<=1);
10070 match(Set dst (CosD src));
10071 ins_cost(1800);
10072 format %{ "DCOS $dst" %}
10073 opcode(0xD9, 0xFF);
10074 ins_encode( OpcP, OpcS );
10075 ins_pipe( pipe_slow );
10076 %}
10077
10078 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10079 predicate (UseSSE>=2);
10080 match(Set dst (CosD dst));
10081 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10082 ins_cost(1800);
10083 format %{ "DCOS $dst" %}
10084 opcode(0xD9, 0xFF);
10085 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10086 ins_pipe( pipe_slow );
10087 %}
10088
10089 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10090 predicate (UseSSE<=1);
10091 match(Set dst(TanD src));
10092 format %{ "DTAN $dst" %}
10093 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10094 Opcode(0xDD), Opcode(0xD8)); // fstp st
10095 ins_pipe( pipe_slow );
10096 %}
10097
10098 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10099 predicate (UseSSE>=2);
10100 match(Set dst(TanD dst));
10101 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10102 format %{ "DTAN $dst" %}
10103 ins_encode( Push_SrcD(dst),
10104 Opcode(0xD9), Opcode(0xF2), // fptan
10105 Opcode(0xDD), Opcode(0xD8), // fstp st
10106 Push_ResultD(dst) );
10107 ins_pipe( pipe_slow );
10108 %}
10109
10110 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10111 predicate (UseSSE<=1);
10112 match(Set dst(AtanD dst src));
10113 format %{ "DATA $dst,$src" %}
10114 opcode(0xD9, 0xF3);
10115 ins_encode( Push_Reg_DPR(src),
10116 OpcP, OpcS, RegOpc(dst) );
10117 ins_pipe( pipe_slow );
10118 %}
10119
10120 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10121 predicate (UseSSE>=2);
10122 match(Set dst(AtanD dst src));
10123 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10124 format %{ "DATA $dst,$src" %}
10125 opcode(0xD9, 0xF3);
10126 ins_encode( Push_SrcD(src),
10127 OpcP, OpcS, Push_ResultD(dst) );
10128 ins_pipe( pipe_slow );
10129 %}
10130
10131 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10132 predicate (UseSSE<=1);
10133 match(Set dst (SqrtD src));
10134 format %{ "DSQRT $dst,$src" %}
10135 opcode(0xFA, 0xD9);
10136 ins_encode( Push_Reg_DPR(src),
10137 OpcS, OpcP, Pop_Reg_DPR(dst) );
10138 ins_pipe( pipe_slow );
10139 %}
10140
10141 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10142 predicate (UseSSE<=1);
10143 match(Set Y (PowD X Y)); // Raise X to the Yth power
10144 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10145 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10146 ins_encode %{
10147 __ subptr(rsp, 8);
10148 __ fld_s($X$$reg - 1);
10149 __ fast_pow();
10150 __ addptr(rsp, 8);
10151 %}
10152 ins_pipe( pipe_slow );
10153 %}
10154
10155 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10156 predicate (UseSSE>=2);
10157 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10158 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10159 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10160 ins_encode %{
10161 __ subptr(rsp, 8);
10162 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10163 __ fld_d(Address(rsp, 0));
10164 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10165 __ fld_d(Address(rsp, 0));
10166 __ fast_pow();
10167 __ fstp_d(Address(rsp, 0));
10168 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10169 __ addptr(rsp, 8);
10170 %}
10171 ins_pipe( pipe_slow );
10172 %}
10173
10174
10175 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10176 predicate (UseSSE<=1);
10177 match(Set dpr1 (ExpD dpr1));
10178 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10179 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10180 ins_encode %{
10181 __ fast_exp();
10182 %}
10183 ins_pipe( pipe_slow );
10184 %}
10185
10186 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10187 predicate (UseSSE>=2);
10188 match(Set dst (ExpD src));
10189 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10190 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10191 ins_encode %{
10192 __ subptr(rsp, 8);
10193 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10194 __ fld_d(Address(rsp, 0));
10195 __ fast_exp();
10196 __ fstp_d(Address(rsp, 0));
10197 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10198 __ addptr(rsp, 8);
10199 %}
10200 ins_pipe( pipe_slow );
10201 %}
10202
10203 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10204 predicate (UseSSE<=1);
10205 // The source Double operand on FPU stack
10206 match(Set dst (Log10D src));
10207 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10208 // fxch ; swap ST(0) with ST(1)
10209 // fyl2x ; compute log_10(2) * log_2(x)
10210 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10211 "FXCH \n\t"
10212 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10213 %}
10214 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10215 Opcode(0xD9), Opcode(0xC9), // fxch
10216 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10217
10218 ins_pipe( pipe_slow );
10219 %}
10220
10221 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10222 predicate (UseSSE>=2);
10223 effect(KILL cr);
10224 match(Set dst (Log10D src));
10225 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10226 // fyl2x ; compute log_10(2) * log_2(x)
10227 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10228 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10229 %}
10230 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10231 Push_SrcD(src),
10232 Opcode(0xD9), Opcode(0xF1), // fyl2x
10233 Push_ResultD(dst));
10234
10235 ins_pipe( pipe_slow );
10236 %}
10237
10238 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10239 predicate (UseSSE<=1);
10240 // The source Double operand on FPU stack
10241 match(Set dst (LogD src));
10242 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10243 // fxch ; swap ST(0) with ST(1)
10244 // fyl2x ; compute log_e(2) * log_2(x)
10245 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10246 "FXCH \n\t"
10247 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10248 %}
10249 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10250 Opcode(0xD9), Opcode(0xC9), // fxch
10251 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10252
10253 ins_pipe( pipe_slow );
10254 %}
10255
10256 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10257 predicate (UseSSE>=2);
10258 effect(KILL cr);
10259 // The source and result Double operands in XMM registers
10260 match(Set dst (LogD src));
10261 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10262 // fyl2x ; compute log_e(2) * log_2(x)
10263 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10264 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10265 %}
10266 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10267 Push_SrcD(src),
10268 Opcode(0xD9), Opcode(0xF1), // fyl2x
10269 Push_ResultD(dst));
10270 ins_pipe( pipe_slow );
10271 %}
10272
10273 //-------------Float Instructions-------------------------------
10274 // Float Math
10275
10276 // Code for float compare:
10277 // fcompp();
10278 // fwait(); fnstsw_ax();
10279 // sahf();
10280 // movl(dst, unordered_result);
10281 // jcc(Assembler::parity, exit);
10282 // movl(dst, less_result);
10283 // jcc(Assembler::below, exit);
10284 // movl(dst, equal_result);
10285 // jcc(Assembler::equal, exit);
10286 // movl(dst, greater_result);
10287 // exit:
10288
10289 // P6 version of float compare, sets condition codes in EFLAGS
10290 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10291 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10292 match(Set cr (CmpF src1 src2));
10293 effect(KILL rax);
10294 ins_cost(150);
10295 format %{ "FLD $src1\n\t"
10296 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10297 "JNP exit\n\t"
10298 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10299 "SAHF\n"
10300 "exit:\tNOP // avoid branch to branch" %}
10301 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10302 ins_encode( Push_Reg_DPR(src1),
10303 OpcP, RegOpc(src2),
10304 cmpF_P6_fixup );
10305 ins_pipe( pipe_slow );
10306 %}
10307
10308 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10309 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10310 match(Set cr (CmpF src1 src2));
10311 ins_cost(100);
10312 format %{ "FLD $src1\n\t"
10313 "FUCOMIP ST,$src2 // P6 instruction" %}
10314 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10315 ins_encode( Push_Reg_DPR(src1),
10316 OpcP, RegOpc(src2));
10317 ins_pipe( pipe_slow );
10318 %}
10319
10320
10321 // Compare & branch
10322 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10323 predicate(UseSSE == 0);
10324 match(Set cr (CmpF src1 src2));
10325 effect(KILL rax);
10326 ins_cost(200);
10327 format %{ "FLD $src1\n\t"
10328 "FCOMp $src2\n\t"
10329 "FNSTSW AX\n\t"
10330 "TEST AX,0x400\n\t"
10331 "JZ,s flags\n\t"
10332 "MOV AH,1\t# unordered treat as LT\n"
10333 "flags:\tSAHF" %}
10334 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10335 ins_encode( Push_Reg_DPR(src1),
10336 OpcP, RegOpc(src2),
10337 fpu_flags);
10338 ins_pipe( pipe_slow );
10339 %}
10340
10341 // Compare vs zero into -1,0,1
10342 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10343 predicate(UseSSE == 0);
10344 match(Set dst (CmpF3 src1 zero));
10345 effect(KILL cr, KILL rax);
10346 ins_cost(280);
10347 format %{ "FTSTF $dst,$src1" %}
10348 opcode(0xE4, 0xD9);
10349 ins_encode( Push_Reg_DPR(src1),
10350 OpcS, OpcP, PopFPU,
10351 CmpF_Result(dst));
10352 ins_pipe( pipe_slow );
10353 %}
10354
10355 // Compare into -1,0,1
10356 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10357 predicate(UseSSE == 0);
10358 match(Set dst (CmpF3 src1 src2));
10359 effect(KILL cr, KILL rax);
10360 ins_cost(300);
10361 format %{ "FCMPF $dst,$src1,$src2" %}
10362 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10363 ins_encode( Push_Reg_DPR(src1),
10364 OpcP, RegOpc(src2),
10365 CmpF_Result(dst));
10366 ins_pipe( pipe_slow );
10367 %}
10368
10369 // float compare and set condition codes in EFLAGS by XMM regs
10370 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10371 predicate(UseSSE>=1);
10372 match(Set cr (CmpF src1 src2));
10373 ins_cost(145);
10374 format %{ "UCOMISS $src1,$src2\n\t"
10375 "JNP,s exit\n\t"
10376 "PUSHF\t# saw NaN, set CF\n\t"
10377 "AND [rsp], #0xffffff2b\n\t"
10378 "POPF\n"
10379 "exit:" %}
10380 ins_encode %{
10381 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10382 emit_cmpfp_fixup(_masm);
10383 %}
10384 ins_pipe( pipe_slow );
10385 %}
10386
10387 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10388 predicate(UseSSE>=1);
10389 match(Set cr (CmpF src1 src2));
10390 ins_cost(100);
10391 format %{ "UCOMISS $src1,$src2" %}
10392 ins_encode %{
10393 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10394 %}
10395 ins_pipe( pipe_slow );
10396 %}
10397
10398 // float compare and set condition codes in EFLAGS by XMM regs
10399 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10400 predicate(UseSSE>=1);
10401 match(Set cr (CmpF src1 (LoadF src2)));
10402 ins_cost(165);
10403 format %{ "UCOMISS $src1,$src2\n\t"
10404 "JNP,s exit\n\t"
10405 "PUSHF\t# saw NaN, set CF\n\t"
10406 "AND [rsp], #0xffffff2b\n\t"
10407 "POPF\n"
10408 "exit:" %}
10409 ins_encode %{
10410 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10411 emit_cmpfp_fixup(_masm);
10412 %}
10413 ins_pipe( pipe_slow );
10414 %}
10415
10416 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10417 predicate(UseSSE>=1);
10418 match(Set cr (CmpF src1 (LoadF src2)));
10419 ins_cost(100);
10420 format %{ "UCOMISS $src1,$src2" %}
10421 ins_encode %{
10422 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10423 %}
10424 ins_pipe( pipe_slow );
10425 %}
10426
10427 // Compare into -1,0,1 in XMM
10428 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10429 predicate(UseSSE>=1);
10430 match(Set dst (CmpF3 src1 src2));
10431 effect(KILL cr);
10432 ins_cost(255);
10433 format %{ "UCOMISS $src1, $src2\n\t"
10434 "MOV $dst, #-1\n\t"
10435 "JP,s done\n\t"
10436 "JB,s done\n\t"
10437 "SETNE $dst\n\t"
10438 "MOVZB $dst, $dst\n"
10439 "done:" %}
10440 ins_encode %{
10441 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10442 emit_cmpfp3(_masm, $dst$$Register);
10443 %}
10444 ins_pipe( pipe_slow );
10445 %}
10446
10447 // Compare into -1,0,1 in XMM and memory
10448 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10449 predicate(UseSSE>=1);
10450 match(Set dst (CmpF3 src1 (LoadF src2)));
10451 effect(KILL cr);
10452 ins_cost(275);
10453 format %{ "UCOMISS $src1, $src2\n\t"
10454 "MOV $dst, #-1\n\t"
10455 "JP,s done\n\t"
10456 "JB,s done\n\t"
10457 "SETNE $dst\n\t"
10458 "MOVZB $dst, $dst\n"
10459 "done:" %}
10460 ins_encode %{
10461 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10462 emit_cmpfp3(_masm, $dst$$Register);
10463 %}
10464 ins_pipe( pipe_slow );
10465 %}
10466
10467 // Spill to obtain 24-bit precision
10468 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10469 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10470 match(Set dst (SubF src1 src2));
10471
10472 format %{ "FSUB $dst,$src1 - $src2" %}
10473 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10474 ins_encode( Push_Reg_FPR(src1),
10475 OpcReg_FPR(src2),
10476 Pop_Mem_FPR(dst) );
10477 ins_pipe( fpu_mem_reg_reg );
10478 %}
10479 //
10480 // This instruction does not round to 24-bits
10481 instruct subFPR_reg(regFPR dst, regFPR src) %{
10482 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10483 match(Set dst (SubF dst src));
10484
10485 format %{ "FSUB $dst,$src" %}
10486 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10487 ins_encode( Push_Reg_FPR(src),
10488 OpcP, RegOpc(dst) );
10489 ins_pipe( fpu_reg_reg );
10490 %}
10491
10492 // Spill to obtain 24-bit precision
10493 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10494 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10495 match(Set dst (AddF src1 src2));
10496
10497 format %{ "FADD $dst,$src1,$src2" %}
10498 opcode(0xD8, 0x0); /* D8 C0+i */
10499 ins_encode( Push_Reg_FPR(src2),
10500 OpcReg_FPR(src1),
10501 Pop_Mem_FPR(dst) );
10502 ins_pipe( fpu_mem_reg_reg );
10503 %}
10504 //
10505 // This instruction does not round to 24-bits
10506 instruct addFPR_reg(regFPR dst, regFPR src) %{
10507 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10508 match(Set dst (AddF dst src));
10509
10510 format %{ "FLD $src\n\t"
10511 "FADDp $dst,ST" %}
10512 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10513 ins_encode( Push_Reg_FPR(src),
10514 OpcP, RegOpc(dst) );
10515 ins_pipe( fpu_reg_reg );
10516 %}
10517
10518 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10519 predicate(UseSSE==0);
10520 match(Set dst (AbsF src));
10521 ins_cost(100);
10522 format %{ "FABS" %}
10523 opcode(0xE1, 0xD9);
10524 ins_encode( OpcS, OpcP );
10525 ins_pipe( fpu_reg_reg );
10526 %}
10527
10528 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10529 predicate(UseSSE==0);
10530 match(Set dst (NegF src));
10531 ins_cost(100);
10532 format %{ "FCHS" %}
10533 opcode(0xE0, 0xD9);
10534 ins_encode( OpcS, OpcP );
10535 ins_pipe( fpu_reg_reg );
10536 %}
10537
10538 // Cisc-alternate to addFPR_reg
10539 // Spill to obtain 24-bit precision
10540 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10541 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10542 match(Set dst (AddF src1 (LoadF src2)));
10543
10544 format %{ "FLD $src2\n\t"
10545 "FADD ST,$src1\n\t"
10546 "FSTP_S $dst" %}
10547 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10548 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10549 OpcReg_FPR(src1),
10550 Pop_Mem_FPR(dst) );
10551 ins_pipe( fpu_mem_reg_mem );
10552 %}
10553 //
10554 // Cisc-alternate to addFPR_reg
10555 // This instruction does not round to 24-bits
10556 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10557 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10558 match(Set dst (AddF dst (LoadF src)));
10559
10560 format %{ "FADD $dst,$src" %}
10561 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10562 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10563 OpcP, RegOpc(dst) );
10564 ins_pipe( fpu_reg_mem );
10565 %}
10566
10567 // // Following two instructions for _222_mpegaudio
10568 // Spill to obtain 24-bit precision
10569 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10570 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10571 match(Set dst (AddF src1 src2));
10572
10573 format %{ "FADD $dst,$src1,$src2" %}
10574 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10575 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10576 OpcReg_FPR(src2),
10577 Pop_Mem_FPR(dst) );
10578 ins_pipe( fpu_mem_reg_mem );
10579 %}
10580
10581 // Cisc-spill variant
10582 // Spill to obtain 24-bit precision
10583 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10584 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10585 match(Set dst (AddF src1 (LoadF src2)));
10586
10587 format %{ "FADD $dst,$src1,$src2 cisc" %}
10588 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10589 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10590 set_instruction_start,
10591 OpcP, RMopc_Mem(secondary,src1),
10592 Pop_Mem_FPR(dst) );
10593 ins_pipe( fpu_mem_mem_mem );
10594 %}
10595
10596 // Spill to obtain 24-bit precision
10597 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10598 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10599 match(Set dst (AddF src1 src2));
10600
10601 format %{ "FADD $dst,$src1,$src2" %}
10602 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10603 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10604 set_instruction_start,
10605 OpcP, RMopc_Mem(secondary,src1),
10606 Pop_Mem_FPR(dst) );
10607 ins_pipe( fpu_mem_mem_mem );
10608 %}
10609
10610
10611 // Spill to obtain 24-bit precision
10612 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10613 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10614 match(Set dst (AddF src con));
10615 format %{ "FLD $src\n\t"
10616 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10617 "FSTP_S $dst" %}
10618 ins_encode %{
10619 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10620 __ fadd_s($constantaddress($con));
10621 __ fstp_s(Address(rsp, $dst$$disp));
10622 %}
10623 ins_pipe(fpu_mem_reg_con);
10624 %}
10625 //
10626 // This instruction does not round to 24-bits
10627 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10628 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10629 match(Set dst (AddF src con));
10630 format %{ "FLD $src\n\t"
10631 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10632 "FSTP $dst" %}
10633 ins_encode %{
10634 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10635 __ fadd_s($constantaddress($con));
10636 __ fstp_d($dst$$reg);
10637 %}
10638 ins_pipe(fpu_reg_reg_con);
10639 %}
10640
10641 // Spill to obtain 24-bit precision
10642 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10643 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10644 match(Set dst (MulF src1 src2));
10645
10646 format %{ "FLD $src1\n\t"
10647 "FMUL $src2\n\t"
10648 "FSTP_S $dst" %}
10649 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10650 ins_encode( Push_Reg_FPR(src1),
10651 OpcReg_FPR(src2),
10652 Pop_Mem_FPR(dst) );
10653 ins_pipe( fpu_mem_reg_reg );
10654 %}
10655 //
10656 // This instruction does not round to 24-bits
10657 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10658 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10659 match(Set dst (MulF src1 src2));
10660
10661 format %{ "FLD $src1\n\t"
10662 "FMUL $src2\n\t"
10663 "FSTP_S $dst" %}
10664 opcode(0xD8, 0x1); /* D8 C8+i */
10665 ins_encode( Push_Reg_FPR(src2),
10666 OpcReg_FPR(src1),
10667 Pop_Reg_FPR(dst) );
10668 ins_pipe( fpu_reg_reg_reg );
10669 %}
10670
10671
10672 // Spill to obtain 24-bit precision
10673 // Cisc-alternate to reg-reg multiply
10674 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10675 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10676 match(Set dst (MulF src1 (LoadF src2)));
10677
10678 format %{ "FLD_S $src2\n\t"
10679 "FMUL $src1\n\t"
10680 "FSTP_S $dst" %}
10681 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10682 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10683 OpcReg_FPR(src1),
10684 Pop_Mem_FPR(dst) );
10685 ins_pipe( fpu_mem_reg_mem );
10686 %}
10687 //
10688 // This instruction does not round to 24-bits
10689 // Cisc-alternate to reg-reg multiply
10690 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10691 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10692 match(Set dst (MulF src1 (LoadF src2)));
10693
10694 format %{ "FMUL $dst,$src1,$src2" %}
10695 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10696 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10697 OpcReg_FPR(src1),
10698 Pop_Reg_FPR(dst) );
10699 ins_pipe( fpu_reg_reg_mem );
10700 %}
10701
10702 // Spill to obtain 24-bit precision
10703 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10704 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10705 match(Set dst (MulF src1 src2));
10706
10707 format %{ "FMUL $dst,$src1,$src2" %}
10708 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10709 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10710 set_instruction_start,
10711 OpcP, RMopc_Mem(secondary,src1),
10712 Pop_Mem_FPR(dst) );
10713 ins_pipe( fpu_mem_mem_mem );
10714 %}
10715
10716 // Spill to obtain 24-bit precision
10717 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10718 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10719 match(Set dst (MulF src con));
10720
10721 format %{ "FLD $src\n\t"
10722 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10723 "FSTP_S $dst" %}
10724 ins_encode %{
10725 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10726 __ fmul_s($constantaddress($con));
10727 __ fstp_s(Address(rsp, $dst$$disp));
10728 %}
10729 ins_pipe(fpu_mem_reg_con);
10730 %}
10731 //
10732 // This instruction does not round to 24-bits
10733 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10734 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10735 match(Set dst (MulF src con));
10736
10737 format %{ "FLD $src\n\t"
10738 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10739 "FSTP $dst" %}
10740 ins_encode %{
10741 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10742 __ fmul_s($constantaddress($con));
10743 __ fstp_d($dst$$reg);
10744 %}
10745 ins_pipe(fpu_reg_reg_con);
10746 %}
10747
10748
10749 //
10750 // MACRO1 -- subsume unshared load into mulFPR
10751 // This instruction does not round to 24-bits
10752 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10753 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10754 match(Set dst (MulF (LoadF mem1) src));
10755
10756 format %{ "FLD $mem1 ===MACRO1===\n\t"
10757 "FMUL ST,$src\n\t"
10758 "FSTP $dst" %}
10759 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10760 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10761 OpcReg_FPR(src),
10762 Pop_Reg_FPR(dst) );
10763 ins_pipe( fpu_reg_reg_mem );
10764 %}
10765 //
10766 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10767 // This instruction does not round to 24-bits
10768 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10769 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10770 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10771 ins_cost(95);
10772
10773 format %{ "FLD $mem1 ===MACRO2===\n\t"
10774 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10775 "FADD ST,$src2\n\t"
10776 "FSTP $dst" %}
10777 opcode(0xD9); /* LoadF D9 /0 */
10778 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10779 FMul_ST_reg(src1),
10780 FAdd_ST_reg(src2),
10781 Pop_Reg_FPR(dst) );
10782 ins_pipe( fpu_reg_mem_reg_reg );
10783 %}
10784
10785 // MACRO3 -- addFPR a mulFPR
10786 // This instruction does not round to 24-bits. It is a '2-address'
10787 // instruction in that the result goes back to src2. This eliminates
10788 // a move from the macro; possibly the register allocator will have
10789 // to add it back (and maybe not).
10790 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10791 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10792 match(Set src2 (AddF (MulF src0 src1) src2));
10793
10794 format %{ "FLD $src0 ===MACRO3===\n\t"
10795 "FMUL ST,$src1\n\t"
10796 "FADDP $src2,ST" %}
10797 opcode(0xD9); /* LoadF D9 /0 */
10798 ins_encode( Push_Reg_FPR(src0),
10799 FMul_ST_reg(src1),
10800 FAddP_reg_ST(src2) );
10801 ins_pipe( fpu_reg_reg_reg );
10802 %}
10803
10804 // MACRO4 -- divFPR subFPR
10805 // This instruction does not round to 24-bits
10806 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10807 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10808 match(Set dst (DivF (SubF src2 src1) src3));
10809
10810 format %{ "FLD $src2 ===MACRO4===\n\t"
10811 "FSUB ST,$src1\n\t"
10812 "FDIV ST,$src3\n\t"
10813 "FSTP $dst" %}
10814 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10815 ins_encode( Push_Reg_FPR(src2),
10816 subFPR_divFPR_encode(src1,src3),
10817 Pop_Reg_FPR(dst) );
10818 ins_pipe( fpu_reg_reg_reg_reg );
10819 %}
10820
10821 // Spill to obtain 24-bit precision
10822 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10823 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10824 match(Set dst (DivF src1 src2));
10825
10826 format %{ "FDIV $dst,$src1,$src2" %}
10827 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10828 ins_encode( Push_Reg_FPR(src1),
10829 OpcReg_FPR(src2),
10830 Pop_Mem_FPR(dst) );
10831 ins_pipe( fpu_mem_reg_reg );
10832 %}
10833 //
10834 // This instruction does not round to 24-bits
10835 instruct divFPR_reg(regFPR dst, regFPR src) %{
10836 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10837 match(Set dst (DivF dst src));
10838
10839 format %{ "FDIV $dst,$src" %}
10840 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10841 ins_encode( Push_Reg_FPR(src),
10842 OpcP, RegOpc(dst) );
10843 ins_pipe( fpu_reg_reg );
10844 %}
10845
10846
10847 // Spill to obtain 24-bit precision
10848 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10849 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10850 match(Set dst (ModF src1 src2));
10851 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10852
10853 format %{ "FMOD $dst,$src1,$src2" %}
10854 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10855 emitModDPR(),
10856 Push_Result_Mod_DPR(src2),
10857 Pop_Mem_FPR(dst));
10858 ins_pipe( pipe_slow );
10859 %}
10860 //
10861 // This instruction does not round to 24-bits
10862 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10863 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10864 match(Set dst (ModF dst src));
10865 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10866
10867 format %{ "FMOD $dst,$src" %}
10868 ins_encode(Push_Reg_Mod_DPR(dst, src),
10869 emitModDPR(),
10870 Push_Result_Mod_DPR(src),
10871 Pop_Reg_FPR(dst));
10872 ins_pipe( pipe_slow );
10873 %}
10874
10875 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10876 predicate(UseSSE>=1);
10877 match(Set dst (ModF src0 src1));
10878 effect(KILL rax, KILL cr);
10879 format %{ "SUB ESP,4\t # FMOD\n"
10880 "\tMOVSS [ESP+0],$src1\n"
10881 "\tFLD_S [ESP+0]\n"
10882 "\tMOVSS [ESP+0],$src0\n"
10883 "\tFLD_S [ESP+0]\n"
10884 "loop:\tFPREM\n"
10885 "\tFWAIT\n"
10886 "\tFNSTSW AX\n"
10887 "\tSAHF\n"
10888 "\tJP loop\n"
10889 "\tFSTP_S [ESP+0]\n"
10890 "\tMOVSS $dst,[ESP+0]\n"
10891 "\tADD ESP,4\n"
10892 "\tFSTP ST0\t # Restore FPU Stack"
10893 %}
10894 ins_cost(250);
10895 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10896 ins_pipe( pipe_slow );
10897 %}
10898
10899
10900 //----------Arithmetic Conversion Instructions---------------------------------
10901 // The conversions operations are all Alpha sorted. Please keep it that way!
10902
10903 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10904 predicate(UseSSE==0);
10905 match(Set dst (RoundFloat src));
10906 ins_cost(125);
10907 format %{ "FST_S $dst,$src\t# F-round" %}
10908 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10909 ins_pipe( fpu_mem_reg );
10910 %}
10911
10912 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10913 predicate(UseSSE<=1);
10914 match(Set dst (RoundDouble src));
10915 ins_cost(125);
10916 format %{ "FST_D $dst,$src\t# D-round" %}
10917 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10918 ins_pipe( fpu_mem_reg );
10919 %}
10920
10921 // Force rounding to 24-bit precision and 6-bit exponent
10922 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10923 predicate(UseSSE==0);
10924 match(Set dst (ConvD2F src));
10925 format %{ "FST_S $dst,$src\t# F-round" %}
10926 expand %{
10927 roundFloat_mem_reg(dst,src);
10928 %}
10929 %}
10930
10931 // Force rounding to 24-bit precision and 6-bit exponent
10932 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10933 predicate(UseSSE==1);
10934 match(Set dst (ConvD2F src));
10935 effect( KILL cr );
10936 format %{ "SUB ESP,4\n\t"
10937 "FST_S [ESP],$src\t# F-round\n\t"
10938 "MOVSS $dst,[ESP]\n\t"
10939 "ADD ESP,4" %}
10940 ins_encode %{
10941 __ subptr(rsp, 4);
10942 if ($src$$reg != FPR1L_enc) {
10943 __ fld_s($src$$reg-1);
10944 __ fstp_s(Address(rsp, 0));
10945 } else {
10946 __ fst_s(Address(rsp, 0));
10947 }
10948 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10949 __ addptr(rsp, 4);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 // Force rounding double precision to single precision
10955 instruct convD2F_reg(regF dst, regD src) %{
10956 predicate(UseSSE>=2);
10957 match(Set dst (ConvD2F src));
10958 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10959 ins_encode %{
10960 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10961 %}
10962 ins_pipe( pipe_slow );
10963 %}
10964
10965 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10966 predicate(UseSSE==0);
10967 match(Set dst (ConvF2D src));
10968 format %{ "FST_S $dst,$src\t# D-round" %}
10969 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10970 ins_pipe( fpu_reg_reg );
10971 %}
10972
10973 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10974 predicate(UseSSE==1);
10975 match(Set dst (ConvF2D src));
10976 format %{ "FST_D $dst,$src\t# D-round" %}
10977 expand %{
10978 roundDouble_mem_reg(dst,src);
10979 %}
10980 %}
10981
10982 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10983 predicate(UseSSE==1);
10984 match(Set dst (ConvF2D src));
10985 effect( KILL cr );
10986 format %{ "SUB ESP,4\n\t"
10987 "MOVSS [ESP] $src\n\t"
10988 "FLD_S [ESP]\n\t"
10989 "ADD ESP,4\n\t"
10990 "FSTP $dst\t# D-round" %}
10991 ins_encode %{
10992 __ subptr(rsp, 4);
10993 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10994 __ fld_s(Address(rsp, 0));
10995 __ addptr(rsp, 4);
10996 __ fstp_d($dst$$reg);
10997 %}
10998 ins_pipe( pipe_slow );
10999 %}
11000
11001 instruct convF2D_reg(regD dst, regF src) %{
11002 predicate(UseSSE>=2);
11003 match(Set dst (ConvF2D src));
11004 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11005 ins_encode %{
11006 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11007 %}
11008 ins_pipe( pipe_slow );
11009 %}
11010
11011 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11012 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11013 predicate(UseSSE<=1);
11014 match(Set dst (ConvD2I src));
11015 effect( KILL tmp, KILL cr );
11016 format %{ "FLD $src\t# Convert double to int \n\t"
11017 "FLDCW trunc mode\n\t"
11018 "SUB ESP,4\n\t"
11019 "FISTp [ESP + #0]\n\t"
11020 "FLDCW std/24-bit mode\n\t"
11021 "POP EAX\n\t"
11022 "CMP EAX,0x80000000\n\t"
11023 "JNE,s fast\n\t"
11024 "FLD_D $src\n\t"
11025 "CALL d2i_wrapper\n"
11026 "fast:" %}
11027 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11028 ins_pipe( pipe_slow );
11029 %}
11030
11031 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11032 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11033 predicate(UseSSE>=2);
11034 match(Set dst (ConvD2I src));
11035 effect( KILL tmp, KILL cr );
11036 format %{ "CVTTSD2SI $dst, $src\n\t"
11037 "CMP $dst,0x80000000\n\t"
11038 "JNE,s fast\n\t"
11039 "SUB ESP, 8\n\t"
11040 "MOVSD [ESP], $src\n\t"
11041 "FLD_D [ESP]\n\t"
11042 "ADD ESP, 8\n\t"
11043 "CALL d2i_wrapper\n"
11044 "fast:" %}
11045 ins_encode %{
11046 Label fast;
11047 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11048 __ cmpl($dst$$Register, 0x80000000);
11049 __ jccb(Assembler::notEqual, fast);
11050 __ subptr(rsp, 8);
11051 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11052 __ fld_d(Address(rsp, 0));
11053 __ addptr(rsp, 8);
11054 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11055 __ bind(fast);
11056 %}
11057 ins_pipe( pipe_slow );
11058 %}
11059
11060 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11061 predicate(UseSSE<=1);
11062 match(Set dst (ConvD2L src));
11063 effect( KILL cr );
11064 format %{ "FLD $src\t# Convert double to long\n\t"
11065 "FLDCW trunc mode\n\t"
11066 "SUB ESP,8\n\t"
11067 "FISTp [ESP + #0]\n\t"
11068 "FLDCW std/24-bit mode\n\t"
11069 "POP EAX\n\t"
11070 "POP EDX\n\t"
11071 "CMP EDX,0x80000000\n\t"
11072 "JNE,s fast\n\t"
11073 "TEST EAX,EAX\n\t"
11074 "JNE,s fast\n\t"
11075 "FLD $src\n\t"
11076 "CALL d2l_wrapper\n"
11077 "fast:" %}
11078 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11079 ins_pipe( pipe_slow );
11080 %}
11081
11082 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11083 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11084 predicate (UseSSE>=2);
11085 match(Set dst (ConvD2L src));
11086 effect( KILL cr );
11087 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11088 "MOVSD [ESP],$src\n\t"
11089 "FLD_D [ESP]\n\t"
11090 "FLDCW trunc mode\n\t"
11091 "FISTp [ESP + #0]\n\t"
11092 "FLDCW std/24-bit mode\n\t"
11093 "POP EAX\n\t"
11094 "POP EDX\n\t"
11095 "CMP EDX,0x80000000\n\t"
11096 "JNE,s fast\n\t"
11097 "TEST EAX,EAX\n\t"
11098 "JNE,s fast\n\t"
11099 "SUB ESP,8\n\t"
11100 "MOVSD [ESP],$src\n\t"
11101 "FLD_D [ESP]\n\t"
11102 "ADD ESP,8\n\t"
11103 "CALL d2l_wrapper\n"
11104 "fast:" %}
11105 ins_encode %{
11106 Label fast;
11107 __ subptr(rsp, 8);
11108 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11109 __ fld_d(Address(rsp, 0));
11110 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11111 __ fistp_d(Address(rsp, 0));
11112 // Restore the rounding mode, mask the exception
11113 if (Compile::current()->in_24_bit_fp_mode()) {
11114 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11115 } else {
11116 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11117 }
11118 // Load the converted long, adjust CPU stack
11119 __ pop(rax);
11120 __ pop(rdx);
11121 __ cmpl(rdx, 0x80000000);
11122 __ jccb(Assembler::notEqual, fast);
11123 __ testl(rax, rax);
11124 __ jccb(Assembler::notEqual, fast);
11125 __ subptr(rsp, 8);
11126 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11127 __ fld_d(Address(rsp, 0));
11128 __ addptr(rsp, 8);
11129 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11130 __ bind(fast);
11131 %}
11132 ins_pipe( pipe_slow );
11133 %}
11134
11135 // Convert a double to an int. Java semantics require we do complex
11136 // manglations in the corner cases. So we set the rounding mode to
11137 // 'zero', store the darned double down as an int, and reset the
11138 // rounding mode to 'nearest'. The hardware stores a flag value down
11139 // if we would overflow or converted a NAN; we check for this and
11140 // and go the slow path if needed.
11141 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11142 predicate(UseSSE==0);
11143 match(Set dst (ConvF2I src));
11144 effect( KILL tmp, KILL cr );
11145 format %{ "FLD $src\t# Convert float to int \n\t"
11146 "FLDCW trunc mode\n\t"
11147 "SUB ESP,4\n\t"
11148 "FISTp [ESP + #0]\n\t"
11149 "FLDCW std/24-bit mode\n\t"
11150 "POP EAX\n\t"
11151 "CMP EAX,0x80000000\n\t"
11152 "JNE,s fast\n\t"
11153 "FLD $src\n\t"
11154 "CALL d2i_wrapper\n"
11155 "fast:" %}
11156 // DPR2I_encoding works for FPR2I
11157 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11158 ins_pipe( pipe_slow );
11159 %}
11160
11161 // Convert a float in xmm to an int reg.
11162 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11163 predicate(UseSSE>=1);
11164 match(Set dst (ConvF2I src));
11165 effect( KILL tmp, KILL cr );
11166 format %{ "CVTTSS2SI $dst, $src\n\t"
11167 "CMP $dst,0x80000000\n\t"
11168 "JNE,s fast\n\t"
11169 "SUB ESP, 4\n\t"
11170 "MOVSS [ESP], $src\n\t"
11171 "FLD [ESP]\n\t"
11172 "ADD ESP, 4\n\t"
11173 "CALL d2i_wrapper\n"
11174 "fast:" %}
11175 ins_encode %{
11176 Label fast;
11177 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11178 __ cmpl($dst$$Register, 0x80000000);
11179 __ jccb(Assembler::notEqual, fast);
11180 __ subptr(rsp, 4);
11181 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11182 __ fld_s(Address(rsp, 0));
11183 __ addptr(rsp, 4);
11184 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11185 __ bind(fast);
11186 %}
11187 ins_pipe( pipe_slow );
11188 %}
11189
11190 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11191 predicate(UseSSE==0);
11192 match(Set dst (ConvF2L src));
11193 effect( KILL cr );
11194 format %{ "FLD $src\t# Convert float to long\n\t"
11195 "FLDCW trunc mode\n\t"
11196 "SUB ESP,8\n\t"
11197 "FISTp [ESP + #0]\n\t"
11198 "FLDCW std/24-bit mode\n\t"
11199 "POP EAX\n\t"
11200 "POP EDX\n\t"
11201 "CMP EDX,0x80000000\n\t"
11202 "JNE,s fast\n\t"
11203 "TEST EAX,EAX\n\t"
11204 "JNE,s fast\n\t"
11205 "FLD $src\n\t"
11206 "CALL d2l_wrapper\n"
11207 "fast:" %}
11208 // DPR2L_encoding works for FPR2L
11209 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11210 ins_pipe( pipe_slow );
11211 %}
11212
11213 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11214 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11215 predicate (UseSSE>=1);
11216 match(Set dst (ConvF2L src));
11217 effect( KILL cr );
11218 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11219 "MOVSS [ESP],$src\n\t"
11220 "FLD_S [ESP]\n\t"
11221 "FLDCW trunc mode\n\t"
11222 "FISTp [ESP + #0]\n\t"
11223 "FLDCW std/24-bit mode\n\t"
11224 "POP EAX\n\t"
11225 "POP EDX\n\t"
11226 "CMP EDX,0x80000000\n\t"
11227 "JNE,s fast\n\t"
11228 "TEST EAX,EAX\n\t"
11229 "JNE,s fast\n\t"
11230 "SUB ESP,4\t# Convert float to long\n\t"
11231 "MOVSS [ESP],$src\n\t"
11232 "FLD_S [ESP]\n\t"
11233 "ADD ESP,4\n\t"
11234 "CALL d2l_wrapper\n"
11235 "fast:" %}
11236 ins_encode %{
11237 Label fast;
11238 __ subptr(rsp, 8);
11239 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11240 __ fld_s(Address(rsp, 0));
11241 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11242 __ fistp_d(Address(rsp, 0));
11243 // Restore the rounding mode, mask the exception
11244 if (Compile::current()->in_24_bit_fp_mode()) {
11245 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11246 } else {
11247 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11248 }
11249 // Load the converted long, adjust CPU stack
11250 __ pop(rax);
11251 __ pop(rdx);
11252 __ cmpl(rdx, 0x80000000);
11253 __ jccb(Assembler::notEqual, fast);
11254 __ testl(rax, rax);
11255 __ jccb(Assembler::notEqual, fast);
11256 __ subptr(rsp, 4);
11257 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11258 __ fld_s(Address(rsp, 0));
11259 __ addptr(rsp, 4);
11260 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11261 __ bind(fast);
11262 %}
11263 ins_pipe( pipe_slow );
11264 %}
11265
11266 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11267 predicate( UseSSE<=1 );
11268 match(Set dst (ConvI2D src));
11269 format %{ "FILD $src\n\t"
11270 "FSTP $dst" %}
11271 opcode(0xDB, 0x0); /* DB /0 */
11272 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11273 ins_pipe( fpu_reg_mem );
11274 %}
11275
11276 instruct convI2D_reg(regD dst, rRegI src) %{
11277 predicate( UseSSE>=2 && !UseXmmI2D );
11278 match(Set dst (ConvI2D src));
11279 format %{ "CVTSI2SD $dst,$src" %}
11280 ins_encode %{
11281 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11282 %}
11283 ins_pipe( pipe_slow );
11284 %}
11285
11286 instruct convI2D_mem(regD dst, memory mem) %{
11287 predicate( UseSSE>=2 );
11288 match(Set dst (ConvI2D (LoadI mem)));
11289 format %{ "CVTSI2SD $dst,$mem" %}
11290 ins_encode %{
11291 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11292 %}
11293 ins_pipe( pipe_slow );
11294 %}
11295
11296 instruct convXI2D_reg(regD dst, rRegI src)
11297 %{
11298 predicate( UseSSE>=2 && UseXmmI2D );
11299 match(Set dst (ConvI2D src));
11300
11301 format %{ "MOVD $dst,$src\n\t"
11302 "CVTDQ2PD $dst,$dst\t# i2d" %}
11303 ins_encode %{
11304 __ movdl($dst$$XMMRegister, $src$$Register);
11305 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11306 %}
11307 ins_pipe(pipe_slow); // XXX
11308 %}
11309
11310 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11311 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11312 match(Set dst (ConvI2D (LoadI mem)));
11313 format %{ "FILD $mem\n\t"
11314 "FSTP $dst" %}
11315 opcode(0xDB); /* DB /0 */
11316 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11317 Pop_Reg_DPR(dst));
11318 ins_pipe( fpu_reg_mem );
11319 %}
11320
11321 // Convert a byte to a float; no rounding step needed.
11322 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11323 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11324 match(Set dst (ConvI2F src));
11325 format %{ "FILD $src\n\t"
11326 "FSTP $dst" %}
11327
11328 opcode(0xDB, 0x0); /* DB /0 */
11329 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11330 ins_pipe( fpu_reg_mem );
11331 %}
11332
11333 // In 24-bit mode, force exponent rounding by storing back out
11334 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11335 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11336 match(Set dst (ConvI2F src));
11337 ins_cost(200);
11338 format %{ "FILD $src\n\t"
11339 "FSTP_S $dst" %}
11340 opcode(0xDB, 0x0); /* DB /0 */
11341 ins_encode( Push_Mem_I(src),
11342 Pop_Mem_FPR(dst));
11343 ins_pipe( fpu_mem_mem );
11344 %}
11345
11346 // In 24-bit mode, force exponent rounding by storing back out
11347 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11348 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11349 match(Set dst (ConvI2F (LoadI mem)));
11350 ins_cost(200);
11351 format %{ "FILD $mem\n\t"
11352 "FSTP_S $dst" %}
11353 opcode(0xDB); /* DB /0 */
11354 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11355 Pop_Mem_FPR(dst));
11356 ins_pipe( fpu_mem_mem );
11357 %}
11358
11359 // This instruction does not round to 24-bits
11360 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11361 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11362 match(Set dst (ConvI2F src));
11363 format %{ "FILD $src\n\t"
11364 "FSTP $dst" %}
11365 opcode(0xDB, 0x0); /* DB /0 */
11366 ins_encode( Push_Mem_I(src),
11367 Pop_Reg_FPR(dst));
11368 ins_pipe( fpu_reg_mem );
11369 %}
11370
11371 // This instruction does not round to 24-bits
11372 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11373 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11374 match(Set dst (ConvI2F (LoadI mem)));
11375 format %{ "FILD $mem\n\t"
11376 "FSTP $dst" %}
11377 opcode(0xDB); /* DB /0 */
11378 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11379 Pop_Reg_FPR(dst));
11380 ins_pipe( fpu_reg_mem );
11381 %}
11382
11383 // Convert an int to a float in xmm; no rounding step needed.
11384 instruct convI2F_reg(regF dst, rRegI src) %{
11385 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11386 match(Set dst (ConvI2F src));
11387 format %{ "CVTSI2SS $dst, $src" %}
11388 ins_encode %{
11389 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11390 %}
11391 ins_pipe( pipe_slow );
11392 %}
11393
11394 instruct convXI2F_reg(regF dst, rRegI src)
11395 %{
11396 predicate( UseSSE>=2 && UseXmmI2F );
11397 match(Set dst (ConvI2F src));
11398
11399 format %{ "MOVD $dst,$src\n\t"
11400 "CVTDQ2PS $dst,$dst\t# i2f" %}
11401 ins_encode %{
11402 __ movdl($dst$$XMMRegister, $src$$Register);
11403 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11404 %}
11405 ins_pipe(pipe_slow); // XXX
11406 %}
11407
11408 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11409 match(Set dst (ConvI2L src));
11410 effect(KILL cr);
11411 ins_cost(375);
11412 format %{ "MOV $dst.lo,$src\n\t"
11413 "MOV $dst.hi,$src\n\t"
11414 "SAR $dst.hi,31" %}
11415 ins_encode(convert_int_long(dst,src));
11416 ins_pipe( ialu_reg_reg_long );
11417 %}
11418
11419 // Zero-extend convert int to long
11420 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11421 match(Set dst (AndL (ConvI2L src) mask) );
11422 effect( KILL flags );
11423 ins_cost(250);
11424 format %{ "MOV $dst.lo,$src\n\t"
11425 "XOR $dst.hi,$dst.hi" %}
11426 opcode(0x33); // XOR
11427 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11428 ins_pipe( ialu_reg_reg_long );
11429 %}
11430
11431 // Zero-extend long
11432 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11433 match(Set dst (AndL src mask) );
11434 effect( KILL flags );
11435 ins_cost(250);
11436 format %{ "MOV $dst.lo,$src.lo\n\t"
11437 "XOR $dst.hi,$dst.hi\n\t" %}
11438 opcode(0x33); // XOR
11439 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11440 ins_pipe( ialu_reg_reg_long );
11441 %}
11442
11443 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11444 predicate (UseSSE<=1);
11445 match(Set dst (ConvL2D src));
11446 effect( KILL cr );
11447 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11448 "PUSH $src.lo\n\t"
11449 "FILD ST,[ESP + #0]\n\t"
11450 "ADD ESP,8\n\t"
11451 "FSTP_D $dst\t# D-round" %}
11452 opcode(0xDF, 0x5); /* DF /5 */
11453 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11454 ins_pipe( pipe_slow );
11455 %}
11456
11457 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11458 predicate (UseSSE>=2);
11459 match(Set dst (ConvL2D src));
11460 effect( KILL cr );
11461 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11462 "PUSH $src.lo\n\t"
11463 "FILD_D [ESP]\n\t"
11464 "FSTP_D [ESP]\n\t"
11465 "MOVSD $dst,[ESP]\n\t"
11466 "ADD ESP,8" %}
11467 opcode(0xDF, 0x5); /* DF /5 */
11468 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11469 ins_pipe( pipe_slow );
11470 %}
11471
11472 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11473 predicate (UseSSE>=1);
11474 match(Set dst (ConvL2F src));
11475 effect( KILL cr );
11476 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11477 "PUSH $src.lo\n\t"
11478 "FILD_D [ESP]\n\t"
11479 "FSTP_S [ESP]\n\t"
11480 "MOVSS $dst,[ESP]\n\t"
11481 "ADD ESP,8" %}
11482 opcode(0xDF, 0x5); /* DF /5 */
11483 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11484 ins_pipe( pipe_slow );
11485 %}
11486
11487 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11488 match(Set dst (ConvL2F src));
11489 effect( KILL cr );
11490 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11491 "PUSH $src.lo\n\t"
11492 "FILD ST,[ESP + #0]\n\t"
11493 "ADD ESP,8\n\t"
11494 "FSTP_S $dst\t# F-round" %}
11495 opcode(0xDF, 0x5); /* DF /5 */
11496 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11497 ins_pipe( pipe_slow );
11498 %}
11499
11500 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11501 match(Set dst (ConvL2I src));
11502 effect( DEF dst, USE src );
11503 format %{ "MOV $dst,$src.lo" %}
11504 ins_encode(enc_CopyL_Lo(dst,src));
11505 ins_pipe( ialu_reg_reg );
11506 %}
11507
11508
11509 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11510 match(Set dst (MoveF2I src));
11511 effect( DEF dst, USE src );
11512 ins_cost(100);
11513 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11514 ins_encode %{
11515 __ movl($dst$$Register, Address(rsp, $src$$disp));
11516 %}
11517 ins_pipe( ialu_reg_mem );
11518 %}
11519
11520 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11521 predicate(UseSSE==0);
11522 match(Set dst (MoveF2I src));
11523 effect( DEF dst, USE src );
11524
11525 ins_cost(125);
11526 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11527 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11528 ins_pipe( fpu_mem_reg );
11529 %}
11530
11531 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11532 predicate(UseSSE>=1);
11533 match(Set dst (MoveF2I src));
11534 effect( DEF dst, USE src );
11535
11536 ins_cost(95);
11537 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11538 ins_encode %{
11539 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11540 %}
11541 ins_pipe( pipe_slow );
11542 %}
11543
11544 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11545 predicate(UseSSE>=2);
11546 match(Set dst (MoveF2I src));
11547 effect( DEF dst, USE src );
11548 ins_cost(85);
11549 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11550 ins_encode %{
11551 __ movdl($dst$$Register, $src$$XMMRegister);
11552 %}
11553 ins_pipe( pipe_slow );
11554 %}
11555
11556 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11557 match(Set dst (MoveI2F src));
11558 effect( DEF dst, USE src );
11559
11560 ins_cost(100);
11561 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11562 ins_encode %{
11563 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11564 %}
11565 ins_pipe( ialu_mem_reg );
11566 %}
11567
11568
11569 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11570 predicate(UseSSE==0);
11571 match(Set dst (MoveI2F src));
11572 effect(DEF dst, USE src);
11573
11574 ins_cost(125);
11575 format %{ "FLD_S $src\n\t"
11576 "FSTP $dst\t# MoveI2F_stack_reg" %}
11577 opcode(0xD9); /* D9 /0, FLD m32real */
11578 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11579 Pop_Reg_FPR(dst) );
11580 ins_pipe( fpu_reg_mem );
11581 %}
11582
11583 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11584 predicate(UseSSE>=1);
11585 match(Set dst (MoveI2F src));
11586 effect( DEF dst, USE src );
11587
11588 ins_cost(95);
11589 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11590 ins_encode %{
11591 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11592 %}
11593 ins_pipe( pipe_slow );
11594 %}
11595
11596 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11597 predicate(UseSSE>=2);
11598 match(Set dst (MoveI2F src));
11599 effect( DEF dst, USE src );
11600
11601 ins_cost(85);
11602 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11603 ins_encode %{
11604 __ movdl($dst$$XMMRegister, $src$$Register);
11605 %}
11606 ins_pipe( pipe_slow );
11607 %}
11608
11609 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11610 match(Set dst (MoveD2L src));
11611 effect(DEF dst, USE src);
11612
11613 ins_cost(250);
11614 format %{ "MOV $dst.lo,$src\n\t"
11615 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11616 opcode(0x8B, 0x8B);
11617 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11618 ins_pipe( ialu_mem_long_reg );
11619 %}
11620
11621 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11622 predicate(UseSSE<=1);
11623 match(Set dst (MoveD2L src));
11624 effect(DEF dst, USE src);
11625
11626 ins_cost(125);
11627 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11628 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11629 ins_pipe( fpu_mem_reg );
11630 %}
11631
11632 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11633 predicate(UseSSE>=2);
11634 match(Set dst (MoveD2L src));
11635 effect(DEF dst, USE src);
11636 ins_cost(95);
11637 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11638 ins_encode %{
11639 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11640 %}
11641 ins_pipe( pipe_slow );
11642 %}
11643
11644 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11645 predicate(UseSSE>=2);
11646 match(Set dst (MoveD2L src));
11647 effect(DEF dst, USE src, TEMP tmp);
11648 ins_cost(85);
11649 format %{ "MOVD $dst.lo,$src\n\t"
11650 "PSHUFLW $tmp,$src,0x4E\n\t"
11651 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11652 ins_encode %{
11653 __ movdl($dst$$Register, $src$$XMMRegister);
11654 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11655 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11656 %}
11657 ins_pipe( pipe_slow );
11658 %}
11659
11660 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11661 match(Set dst (MoveL2D src));
11662 effect(DEF dst, USE src);
11663
11664 ins_cost(200);
11665 format %{ "MOV $dst,$src.lo\n\t"
11666 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11667 opcode(0x89, 0x89);
11668 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11669 ins_pipe( ialu_mem_long_reg );
11670 %}
11671
11672
11673 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11674 predicate(UseSSE<=1);
11675 match(Set dst (MoveL2D src));
11676 effect(DEF dst, USE src);
11677 ins_cost(125);
11678
11679 format %{ "FLD_D $src\n\t"
11680 "FSTP $dst\t# MoveL2D_stack_reg" %}
11681 opcode(0xDD); /* DD /0, FLD m64real */
11682 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11683 Pop_Reg_DPR(dst) );
11684 ins_pipe( fpu_reg_mem );
11685 %}
11686
11687
11688 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11689 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11690 match(Set dst (MoveL2D src));
11691 effect(DEF dst, USE src);
11692
11693 ins_cost(95);
11694 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11695 ins_encode %{
11696 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11697 %}
11698 ins_pipe( pipe_slow );
11699 %}
11700
11701 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11702 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11703 match(Set dst (MoveL2D src));
11704 effect(DEF dst, USE src);
11705
11706 ins_cost(95);
11707 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11708 ins_encode %{
11709 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11710 %}
11711 ins_pipe( pipe_slow );
11712 %}
11713
11714 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11715 predicate(UseSSE>=2);
11716 match(Set dst (MoveL2D src));
11717 effect(TEMP dst, USE src, TEMP tmp);
11718 ins_cost(85);
11719 format %{ "MOVD $dst,$src.lo\n\t"
11720 "MOVD $tmp,$src.hi\n\t"
11721 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11722 ins_encode %{
11723 __ movdl($dst$$XMMRegister, $src$$Register);
11724 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11725 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11726 %}
11727 ins_pipe( pipe_slow );
11728 %}
11729
11730
11731 // =======================================================================
11732 // fast clearing of an array
11733 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11734 predicate(!UseFastStosb);
11735 match(Set dummy (ClearArray cnt base));
11736 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11737 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11738 "SHL ECX,1\t# Convert doublewords to words\n\t"
11739 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11740 ins_encode %{
11741 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11742 %}
11743 ins_pipe( pipe_slow );
11744 %}
11745
11746 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11747 predicate(UseFastStosb);
11748 match(Set dummy (ClearArray cnt base));
11749 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11750 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11751 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11752 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11753 ins_encode %{
11754 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11755 %}
11756 ins_pipe( pipe_slow );
11757 %}
11758
11759 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11760 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11761 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11762 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11763
11764 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11765 ins_encode %{
11766 __ string_compare($str1$$Register, $str2$$Register,
11767 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11768 $tmp1$$XMMRegister);
11769 %}
11770 ins_pipe( pipe_slow );
11771 %}
11772
11773 // fast string equals
11774 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11775 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11776 match(Set result (StrEquals (Binary str1 str2) cnt));
11777 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11778
11779 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11780 ins_encode %{
11781 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11782 $cnt$$Register, $result$$Register, $tmp3$$Register,
11783 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11784 %}
11785 ins_pipe( pipe_slow );
11786 %}
11787
11788 // fast search of substring with known size.
11789 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11790 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11791 predicate(UseSSE42Intrinsics);
11792 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11793 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11794
11795 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11796 ins_encode %{
11797 int icnt2 = (int)$int_cnt2$$constant;
11798 if (icnt2 >= 8) {
11799 // IndexOf for constant substrings with size >= 8 elements
11800 // which don't need to be loaded through stack.
11801 __ string_indexofC8($str1$$Register, $str2$$Register,
11802 $cnt1$$Register, $cnt2$$Register,
11803 icnt2, $result$$Register,
11804 $vec$$XMMRegister, $tmp$$Register);
11805 } else {
11806 // Small strings are loaded through stack if they cross page boundary.
11807 __ string_indexof($str1$$Register, $str2$$Register,
11808 $cnt1$$Register, $cnt2$$Register,
11809 icnt2, $result$$Register,
11810 $vec$$XMMRegister, $tmp$$Register);
11811 }
11812 %}
11813 ins_pipe( pipe_slow );
11814 %}
11815
11816 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11817 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11818 predicate(UseSSE42Intrinsics);
11819 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11820 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11821
11822 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11823 ins_encode %{
11824 __ string_indexof($str1$$Register, $str2$$Register,
11825 $cnt1$$Register, $cnt2$$Register,
11826 (-1), $result$$Register,
11827 $vec$$XMMRegister, $tmp$$Register);
11828 %}
11829 ins_pipe( pipe_slow );
11830 %}
11831
11832 // fast array equals
11833 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11834 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11835 %{
11836 match(Set result (AryEq ary1 ary2));
11837 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11838 //ins_cost(300);
11839
11840 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11841 ins_encode %{
11842 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11843 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11844 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11845 %}
11846 ins_pipe( pipe_slow );
11847 %}
11848
11849 // encode char[] to byte[] in ISO_8859_1
11850 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11851 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11852 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11853 match(Set result (EncodeISOArray src (Binary dst len)));
11854 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11855
11856 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11857 ins_encode %{
11858 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11859 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11860 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11861 %}
11862 ins_pipe( pipe_slow );
11863 %}
11864
11865
11866 //----------Control Flow Instructions------------------------------------------
11867 // Signed compare Instructions
11868 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11869 match(Set cr (CmpI op1 op2));
11870 effect( DEF cr, USE op1, USE op2 );
11871 format %{ "CMP $op1,$op2" %}
11872 opcode(0x3B); /* Opcode 3B /r */
11873 ins_encode( OpcP, RegReg( op1, op2) );
11874 ins_pipe( ialu_cr_reg_reg );
11875 %}
11876
11877 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11878 match(Set cr (CmpI op1 op2));
11879 effect( DEF cr, USE op1 );
11880 format %{ "CMP $op1,$op2" %}
11881 opcode(0x81,0x07); /* Opcode 81 /7 */
11882 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11883 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11884 ins_pipe( ialu_cr_reg_imm );
11885 %}
11886
11887 // Cisc-spilled version of cmpI_eReg
11888 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11889 match(Set cr (CmpI op1 (LoadI op2)));
11890
11891 format %{ "CMP $op1,$op2" %}
11892 ins_cost(500);
11893 opcode(0x3B); /* Opcode 3B /r */
11894 ins_encode( OpcP, RegMem( op1, op2) );
11895 ins_pipe( ialu_cr_reg_mem );
11896 %}
11897
11898 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11899 match(Set cr (CmpI src zero));
11900 effect( DEF cr, USE src );
11901
11902 format %{ "TEST $src,$src" %}
11903 opcode(0x85);
11904 ins_encode( OpcP, RegReg( src, src ) );
11905 ins_pipe( ialu_cr_reg_imm );
11906 %}
11907
11908 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11909 match(Set cr (CmpI (AndI src con) zero));
11910
11911 format %{ "TEST $src,$con" %}
11912 opcode(0xF7,0x00);
11913 ins_encode( OpcP, RegOpc(src), Con32(con) );
11914 ins_pipe( ialu_cr_reg_imm );
11915 %}
11916
11917 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11918 match(Set cr (CmpI (AndI src mem) zero));
11919
11920 format %{ "TEST $src,$mem" %}
11921 opcode(0x85);
11922 ins_encode( OpcP, RegMem( src, mem ) );
11923 ins_pipe( ialu_cr_reg_mem );
11924 %}
11925
11926 // Unsigned compare Instructions; really, same as signed except they
11927 // produce an eFlagsRegU instead of eFlagsReg.
11928 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11929 match(Set cr (CmpU op1 op2));
11930
11931 format %{ "CMPu $op1,$op2" %}
11932 opcode(0x3B); /* Opcode 3B /r */
11933 ins_encode( OpcP, RegReg( op1, op2) );
11934 ins_pipe( ialu_cr_reg_reg );
11935 %}
11936
11937 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11938 match(Set cr (CmpU op1 op2));
11939
11940 format %{ "CMPu $op1,$op2" %}
11941 opcode(0x81,0x07); /* Opcode 81 /7 */
11942 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11943 ins_pipe( ialu_cr_reg_imm );
11944 %}
11945
11946 // // Cisc-spilled version of cmpU_eReg
11947 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11948 match(Set cr (CmpU op1 (LoadI op2)));
11949
11950 format %{ "CMPu $op1,$op2" %}
11951 ins_cost(500);
11952 opcode(0x3B); /* Opcode 3B /r */
11953 ins_encode( OpcP, RegMem( op1, op2) );
11954 ins_pipe( ialu_cr_reg_mem );
11955 %}
11956
11957 // // Cisc-spilled version of cmpU_eReg
11958 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11959 // match(Set cr (CmpU (LoadI op1) op2));
11960 //
11961 // format %{ "CMPu $op1,$op2" %}
11962 // ins_cost(500);
11963 // opcode(0x39); /* Opcode 39 /r */
11964 // ins_encode( OpcP, RegMem( op1, op2) );
11965 //%}
11966
11967 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11968 match(Set cr (CmpU src zero));
11969
11970 format %{ "TESTu $src,$src" %}
11971 opcode(0x85);
11972 ins_encode( OpcP, RegReg( src, src ) );
11973 ins_pipe( ialu_cr_reg_imm );
11974 %}
11975
11976 // Unsigned pointer compare Instructions
11977 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11978 match(Set cr (CmpP op1 op2));
11979
11980 format %{ "CMPu $op1,$op2" %}
11981 opcode(0x3B); /* Opcode 3B /r */
11982 ins_encode( OpcP, RegReg( op1, op2) );
11983 ins_pipe( ialu_cr_reg_reg );
11984 %}
11985
11986 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11987 match(Set cr (CmpP op1 op2));
11988
11989 format %{ "CMPu $op1,$op2" %}
11990 opcode(0x81,0x07); /* Opcode 81 /7 */
11991 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11992 ins_pipe( ialu_cr_reg_imm );
11993 %}
11994
11995 // // Cisc-spilled version of cmpP_eReg
11996 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11997 match(Set cr (CmpP op1 (LoadP op2)));
11998
11999 format %{ "CMPu $op1,$op2" %}
12000 ins_cost(500);
12001 opcode(0x3B); /* Opcode 3B /r */
12002 ins_encode( OpcP, RegMem( op1, op2) );
12003 ins_pipe( ialu_cr_reg_mem );
12004 %}
12005
12006 // // Cisc-spilled version of cmpP_eReg
12007 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12008 // match(Set cr (CmpP (LoadP op1) op2));
12009 //
12010 // format %{ "CMPu $op1,$op2" %}
12011 // ins_cost(500);
12012 // opcode(0x39); /* Opcode 39 /r */
12013 // ins_encode( OpcP, RegMem( op1, op2) );
12014 //%}
12015
12016 // Compare raw pointer (used in out-of-heap check).
12017 // Only works because non-oop pointers must be raw pointers
12018 // and raw pointers have no anti-dependencies.
12019 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12020 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
12021 match(Set cr (CmpP op1 (LoadP op2)));
12022
12023 format %{ "CMPu $op1,$op2" %}
12024 opcode(0x3B); /* Opcode 3B /r */
12025 ins_encode( OpcP, RegMem( op1, op2) );
12026 ins_pipe( ialu_cr_reg_mem );
12027 %}
12028
12029 //
12030 // This will generate a signed flags result. This should be ok
12031 // since any compare to a zero should be eq/neq.
12032 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12033 match(Set cr (CmpP src zero));
12034
12035 format %{ "TEST $src,$src" %}
12036 opcode(0x85);
12037 ins_encode( OpcP, RegReg( src, src ) );
12038 ins_pipe( ialu_cr_reg_imm );
12039 %}
12040
12041 // Cisc-spilled version of testP_reg
12042 // This will generate a signed flags result. This should be ok
12043 // since any compare to a zero should be eq/neq.
12044 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12045 match(Set cr (CmpP (LoadP op) zero));
12046
12047 format %{ "TEST $op,0xFFFFFFFF" %}
12048 ins_cost(500);
12049 opcode(0xF7); /* Opcode F7 /0 */
12050 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12051 ins_pipe( ialu_cr_reg_imm );
12052 %}
12053
12054 // Yanked all unsigned pointer compare operations.
12055 // Pointer compares are done with CmpP which is already unsigned.
12056
12057 //----------Max and Min--------------------------------------------------------
12058 // Min Instructions
12059 ////
12060 // *** Min and Max using the conditional move are slower than the
12061 // *** branch version on a Pentium III.
12062 // // Conditional move for min
12063 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12064 // effect( USE_DEF op2, USE op1, USE cr );
12065 // format %{ "CMOVlt $op2,$op1\t! min" %}
12066 // opcode(0x4C,0x0F);
12067 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12068 // ins_pipe( pipe_cmov_reg );
12069 //%}
12070 //
12071 //// Min Register with Register (P6 version)
12072 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12073 // predicate(VM_Version::supports_cmov() );
12074 // match(Set op2 (MinI op1 op2));
12075 // ins_cost(200);
12076 // expand %{
12077 // eFlagsReg cr;
12078 // compI_eReg(cr,op1,op2);
12079 // cmovI_reg_lt(op2,op1,cr);
12080 // %}
12081 //%}
12082
12083 // Min Register with Register (generic version)
12084 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12085 match(Set dst (MinI dst src));
12086 effect(KILL flags);
12087 ins_cost(300);
12088
12089 format %{ "MIN $dst,$src" %}
12090 opcode(0xCC);
12091 ins_encode( min_enc(dst,src) );
12092 ins_pipe( pipe_slow );
12093 %}
12094
12095 // Max Register with Register
12096 // *** Min and Max using the conditional move are slower than the
12097 // *** branch version on a Pentium III.
12098 // // Conditional move for max
12099 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12100 // effect( USE_DEF op2, USE op1, USE cr );
12101 // format %{ "CMOVgt $op2,$op1\t! max" %}
12102 // opcode(0x4F,0x0F);
12103 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12104 // ins_pipe( pipe_cmov_reg );
12105 //%}
12106 //
12107 // // Max Register with Register (P6 version)
12108 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12109 // predicate(VM_Version::supports_cmov() );
12110 // match(Set op2 (MaxI op1 op2));
12111 // ins_cost(200);
12112 // expand %{
12113 // eFlagsReg cr;
12114 // compI_eReg(cr,op1,op2);
12115 // cmovI_reg_gt(op2,op1,cr);
12116 // %}
12117 //%}
12118
12119 // Max Register with Register (generic version)
12120 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12121 match(Set dst (MaxI dst src));
12122 effect(KILL flags);
12123 ins_cost(300);
12124
12125 format %{ "MAX $dst,$src" %}
12126 opcode(0xCC);
12127 ins_encode( max_enc(dst,src) );
12128 ins_pipe( pipe_slow );
12129 %}
12130
12131 // ============================================================================
12132 // Counted Loop limit node which represents exact final iterator value.
12133 // Note: the resulting value should fit into integer range since
12134 // counted loops have limit check on overflow.
12135 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12136 match(Set limit (LoopLimit (Binary init limit) stride));
12137 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12138 ins_cost(300);
12139
12140 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12141 ins_encode %{
12142 int strd = (int)$stride$$constant;
12143 assert(strd != 1 && strd != -1, "sanity");
12144 int m1 = (strd > 0) ? 1 : -1;
12145 // Convert limit to long (EAX:EDX)
12146 __ cdql();
12147 // Convert init to long (init:tmp)
12148 __ movl($tmp$$Register, $init$$Register);
12149 __ sarl($tmp$$Register, 31);
12150 // $limit - $init
12151 __ subl($limit$$Register, $init$$Register);
12152 __ sbbl($limit_hi$$Register, $tmp$$Register);
12153 // + ($stride - 1)
12154 if (strd > 0) {
12155 __ addl($limit$$Register, (strd - 1));
12156 __ adcl($limit_hi$$Register, 0);
12157 __ movl($tmp$$Register, strd);
12158 } else {
12159 __ addl($limit$$Register, (strd + 1));
12160 __ adcl($limit_hi$$Register, -1);
12161 __ lneg($limit_hi$$Register, $limit$$Register);
12162 __ movl($tmp$$Register, -strd);
12163 }
12164 // signed devision: (EAX:EDX) / pos_stride
12165 __ idivl($tmp$$Register);
12166 if (strd < 0) {
12167 // restore sign
12168 __ negl($tmp$$Register);
12169 }
12170 // (EAX) * stride
12171 __ mull($tmp$$Register);
12172 // + init (ignore upper bits)
12173 __ addl($limit$$Register, $init$$Register);
12174 %}
12175 ins_pipe( pipe_slow );
12176 %}
12177
12178 // ============================================================================
12179 // Branch Instructions
12180 // Jump Table
12181 instruct jumpXtnd(rRegI switch_val) %{
12182 match(Jump switch_val);
12183 ins_cost(350);
12184 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12185 ins_encode %{
12186 // Jump to Address(table_base + switch_reg)
12187 Address index(noreg, $switch_val$$Register, Address::times_1);
12188 __ jump(ArrayAddress($constantaddress, index));
12189 %}
12190 ins_pipe(pipe_jmp);
12191 %}
12192
12193 // Jump Direct - Label defines a relative address from JMP+1
12194 instruct jmpDir(label labl) %{
12195 match(Goto);
12196 effect(USE labl);
12197
12198 ins_cost(300);
12199 format %{ "JMP $labl" %}
12200 size(5);
12201 ins_encode %{
12202 Label* L = $labl$$label;
12203 __ jmp(*L, false); // Always long jump
12204 %}
12205 ins_pipe( pipe_jmp );
12206 %}
12207
12208 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12209 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12210 match(If cop cr);
12211 effect(USE labl);
12212
12213 ins_cost(300);
12214 format %{ "J$cop $labl" %}
12215 size(6);
12216 ins_encode %{
12217 Label* L = $labl$$label;
12218 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12219 %}
12220 ins_pipe( pipe_jcc );
12221 %}
12222
12223 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12224 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12225 match(CountedLoopEnd cop cr);
12226 effect(USE labl);
12227
12228 ins_cost(300);
12229 format %{ "J$cop $labl\t# Loop end" %}
12230 size(6);
12231 ins_encode %{
12232 Label* L = $labl$$label;
12233 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12234 %}
12235 ins_pipe( pipe_jcc );
12236 %}
12237
12238 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12239 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12240 match(CountedLoopEnd cop cmp);
12241 effect(USE labl);
12242
12243 ins_cost(300);
12244 format %{ "J$cop,u $labl\t# Loop end" %}
12245 size(6);
12246 ins_encode %{
12247 Label* L = $labl$$label;
12248 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12249 %}
12250 ins_pipe( pipe_jcc );
12251 %}
12252
12253 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12254 match(CountedLoopEnd cop cmp);
12255 effect(USE labl);
12256
12257 ins_cost(200);
12258 format %{ "J$cop,u $labl\t# Loop end" %}
12259 size(6);
12260 ins_encode %{
12261 Label* L = $labl$$label;
12262 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12263 %}
12264 ins_pipe( pipe_jcc );
12265 %}
12266
12267 // Jump Direct Conditional - using unsigned comparison
12268 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12269 match(If cop cmp);
12270 effect(USE labl);
12271
12272 ins_cost(300);
12273 format %{ "J$cop,u $labl" %}
12274 size(6);
12275 ins_encode %{
12276 Label* L = $labl$$label;
12277 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12278 %}
12279 ins_pipe(pipe_jcc);
12280 %}
12281
12282 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12283 match(If cop cmp);
12284 effect(USE labl);
12285
12286 ins_cost(200);
12287 format %{ "J$cop,u $labl" %}
12288 size(6);
12289 ins_encode %{
12290 Label* L = $labl$$label;
12291 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12292 %}
12293 ins_pipe(pipe_jcc);
12294 %}
12295
12296 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12297 match(If cop cmp);
12298 effect(USE labl);
12299
12300 ins_cost(200);
12301 format %{ $$template
12302 if ($cop$$cmpcode == Assembler::notEqual) {
12303 $$emit$$"JP,u $labl\n\t"
12304 $$emit$$"J$cop,u $labl"
12305 } else {
12306 $$emit$$"JP,u done\n\t"
12307 $$emit$$"J$cop,u $labl\n\t"
12308 $$emit$$"done:"
12309 }
12310 %}
12311 ins_encode %{
12312 Label* l = $labl$$label;
12313 if ($cop$$cmpcode == Assembler::notEqual) {
12314 __ jcc(Assembler::parity, *l, false);
12315 __ jcc(Assembler::notEqual, *l, false);
12316 } else if ($cop$$cmpcode == Assembler::equal) {
12317 Label done;
12318 __ jccb(Assembler::parity, done);
12319 __ jcc(Assembler::equal, *l, false);
12320 __ bind(done);
12321 } else {
12322 ShouldNotReachHere();
12323 }
12324 %}
12325 ins_pipe(pipe_jcc);
12326 %}
12327
12328 // ============================================================================
12329 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12330 // array for an instance of the superklass. Set a hidden internal cache on a
12331 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12332 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12333 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12334 match(Set result (PartialSubtypeCheck sub super));
12335 effect( KILL rcx, KILL cr );
12336
12337 ins_cost(1100); // slightly larger than the next version
12338 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12339 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12340 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12341 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12342 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12343 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12344 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12345 "miss:\t" %}
12346
12347 opcode(0x1); // Force a XOR of EDI
12348 ins_encode( enc_PartialSubtypeCheck() );
12349 ins_pipe( pipe_slow );
12350 %}
12351
12352 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12353 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12354 effect( KILL rcx, KILL result );
12355
12356 ins_cost(1000);
12357 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12358 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12359 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12360 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12361 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12362 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12363 "miss:\t" %}
12364
12365 opcode(0x0); // No need to XOR EDI
12366 ins_encode( enc_PartialSubtypeCheck() );
12367 ins_pipe( pipe_slow );
12368 %}
12369
12370 // ============================================================================
12371 // Branch Instructions -- short offset versions
12372 //
12373 // These instructions are used to replace jumps of a long offset (the default
12374 // match) with jumps of a shorter offset. These instructions are all tagged
12375 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12376 // match rules in general matching. Instead, the ADLC generates a conversion
12377 // method in the MachNode which can be used to do in-place replacement of the
12378 // long variant with the shorter variant. The compiler will determine if a
12379 // branch can be taken by the is_short_branch_offset() predicate in the machine
12380 // specific code section of the file.
12381
12382 // Jump Direct - Label defines a relative address from JMP+1
12383 instruct jmpDir_short(label labl) %{
12384 match(Goto);
12385 effect(USE labl);
12386
12387 ins_cost(300);
12388 format %{ "JMP,s $labl" %}
12389 size(2);
12390 ins_encode %{
12391 Label* L = $labl$$label;
12392 __ jmpb(*L);
12393 %}
12394 ins_pipe( pipe_jmp );
12395 ins_short_branch(1);
12396 %}
12397
12398 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12399 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12400 match(If cop cr);
12401 effect(USE labl);
12402
12403 ins_cost(300);
12404 format %{ "J$cop,s $labl" %}
12405 size(2);
12406 ins_encode %{
12407 Label* L = $labl$$label;
12408 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12409 %}
12410 ins_pipe( pipe_jcc );
12411 ins_short_branch(1);
12412 %}
12413
12414 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12415 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12416 match(CountedLoopEnd cop cr);
12417 effect(USE labl);
12418
12419 ins_cost(300);
12420 format %{ "J$cop,s $labl\t# Loop end" %}
12421 size(2);
12422 ins_encode %{
12423 Label* L = $labl$$label;
12424 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12425 %}
12426 ins_pipe( pipe_jcc );
12427 ins_short_branch(1);
12428 %}
12429
12430 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12431 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12432 match(CountedLoopEnd cop cmp);
12433 effect(USE labl);
12434
12435 ins_cost(300);
12436 format %{ "J$cop,us $labl\t# Loop end" %}
12437 size(2);
12438 ins_encode %{
12439 Label* L = $labl$$label;
12440 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12441 %}
12442 ins_pipe( pipe_jcc );
12443 ins_short_branch(1);
12444 %}
12445
12446 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12447 match(CountedLoopEnd cop cmp);
12448 effect(USE labl);
12449
12450 ins_cost(300);
12451 format %{ "J$cop,us $labl\t# Loop end" %}
12452 size(2);
12453 ins_encode %{
12454 Label* L = $labl$$label;
12455 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12456 %}
12457 ins_pipe( pipe_jcc );
12458 ins_short_branch(1);
12459 %}
12460
12461 // Jump Direct Conditional - using unsigned comparison
12462 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12463 match(If cop cmp);
12464 effect(USE labl);
12465
12466 ins_cost(300);
12467 format %{ "J$cop,us $labl" %}
12468 size(2);
12469 ins_encode %{
12470 Label* L = $labl$$label;
12471 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12472 %}
12473 ins_pipe( pipe_jcc );
12474 ins_short_branch(1);
12475 %}
12476
12477 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12478 match(If cop cmp);
12479 effect(USE labl);
12480
12481 ins_cost(300);
12482 format %{ "J$cop,us $labl" %}
12483 size(2);
12484 ins_encode %{
12485 Label* L = $labl$$label;
12486 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12487 %}
12488 ins_pipe( pipe_jcc );
12489 ins_short_branch(1);
12490 %}
12491
12492 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12493 match(If cop cmp);
12494 effect(USE labl);
12495
12496 ins_cost(300);
12497 format %{ $$template
12498 if ($cop$$cmpcode == Assembler::notEqual) {
12499 $$emit$$"JP,u,s $labl\n\t"
12500 $$emit$$"J$cop,u,s $labl"
12501 } else {
12502 $$emit$$"JP,u,s done\n\t"
12503 $$emit$$"J$cop,u,s $labl\n\t"
12504 $$emit$$"done:"
12505 }
12506 %}
12507 size(4);
12508 ins_encode %{
12509 Label* l = $labl$$label;
12510 if ($cop$$cmpcode == Assembler::notEqual) {
12511 __ jccb(Assembler::parity, *l);
12512 __ jccb(Assembler::notEqual, *l);
12513 } else if ($cop$$cmpcode == Assembler::equal) {
12514 Label done;
12515 __ jccb(Assembler::parity, done);
12516 __ jccb(Assembler::equal, *l);
12517 __ bind(done);
12518 } else {
12519 ShouldNotReachHere();
12520 }
12521 %}
12522 ins_pipe(pipe_jcc);
12523 ins_short_branch(1);
12524 %}
12525
12526 // ============================================================================
12527 // Long Compare
12528 //
12529 // Currently we hold longs in 2 registers. Comparing such values efficiently
12530 // is tricky. The flavor of compare used depends on whether we are testing
12531 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12532 // The GE test is the negated LT test. The LE test can be had by commuting
12533 // the operands (yielding a GE test) and then negating; negate again for the
12534 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12535 // NE test is negated from that.
12536
12537 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12538 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12539 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12540 // are collapsed internally in the ADLC's dfa-gen code. The match for
12541 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12542 // foo match ends up with the wrong leaf. One fix is to not match both
12543 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12544 // both forms beat the trinary form of long-compare and both are very useful
12545 // on Intel which has so few registers.
12546
12547 // Manifest a CmpL result in an integer register. Very painful.
12548 // This is the test to avoid.
12549 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12550 match(Set dst (CmpL3 src1 src2));
12551 effect( KILL flags );
12552 ins_cost(1000);
12553 format %{ "XOR $dst,$dst\n\t"
12554 "CMP $src1.hi,$src2.hi\n\t"
12555 "JLT,s m_one\n\t"
12556 "JGT,s p_one\n\t"
12557 "CMP $src1.lo,$src2.lo\n\t"
12558 "JB,s m_one\n\t"
12559 "JEQ,s done\n"
12560 "p_one:\tINC $dst\n\t"
12561 "JMP,s done\n"
12562 "m_one:\tDEC $dst\n"
12563 "done:" %}
12564 ins_encode %{
12565 Label p_one, m_one, done;
12566 __ xorptr($dst$$Register, $dst$$Register);
12567 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12568 __ jccb(Assembler::less, m_one);
12569 __ jccb(Assembler::greater, p_one);
12570 __ cmpl($src1$$Register, $src2$$Register);
12571 __ jccb(Assembler::below, m_one);
12572 __ jccb(Assembler::equal, done);
12573 __ bind(p_one);
12574 __ incrementl($dst$$Register);
12575 __ jmpb(done);
12576 __ bind(m_one);
12577 __ decrementl($dst$$Register);
12578 __ bind(done);
12579 %}
12580 ins_pipe( pipe_slow );
12581 %}
12582
12583 //======
12584 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12585 // compares. Can be used for LE or GT compares by reversing arguments.
12586 // NOT GOOD FOR EQ/NE tests.
12587 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12588 match( Set flags (CmpL src zero ));
12589 ins_cost(100);
12590 format %{ "TEST $src.hi,$src.hi" %}
12591 opcode(0x85);
12592 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12593 ins_pipe( ialu_cr_reg_reg );
12594 %}
12595
12596 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12597 // compares. Can be used for LE or GT compares by reversing arguments.
12598 // NOT GOOD FOR EQ/NE tests.
12599 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12600 match( Set flags (CmpL src1 src2 ));
12601 effect( TEMP tmp );
12602 ins_cost(300);
12603 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12604 "MOV $tmp,$src1.hi\n\t"
12605 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12606 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12607 ins_pipe( ialu_cr_reg_reg );
12608 %}
12609
12610 // Long compares reg < zero/req OR reg >= zero/req.
12611 // Just a wrapper for a normal branch, plus the predicate test.
12612 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12613 match(If cmp flags);
12614 effect(USE labl);
12615 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12616 expand %{
12617 jmpCon(cmp,flags,labl); // JLT or JGE...
12618 %}
12619 %}
12620
12621 // Compare 2 longs and CMOVE longs.
12622 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12623 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12624 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12625 ins_cost(400);
12626 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12627 "CMOV$cmp $dst.hi,$src.hi" %}
12628 opcode(0x0F,0x40);
12629 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12630 ins_pipe( pipe_cmov_reg_long );
12631 %}
12632
12633 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12634 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12635 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12636 ins_cost(500);
12637 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12638 "CMOV$cmp $dst.hi,$src.hi" %}
12639 opcode(0x0F,0x40);
12640 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12641 ins_pipe( pipe_cmov_reg_long );
12642 %}
12643
12644 // Compare 2 longs and CMOVE ints.
12645 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12646 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12647 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12648 ins_cost(200);
12649 format %{ "CMOV$cmp $dst,$src" %}
12650 opcode(0x0F,0x40);
12651 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12652 ins_pipe( pipe_cmov_reg );
12653 %}
12654
12655 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12656 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12657 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12658 ins_cost(250);
12659 format %{ "CMOV$cmp $dst,$src" %}
12660 opcode(0x0F,0x40);
12661 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12662 ins_pipe( pipe_cmov_mem );
12663 %}
12664
12665 // Compare 2 longs and CMOVE ints.
12666 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12667 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12668 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12669 ins_cost(200);
12670 format %{ "CMOV$cmp $dst,$src" %}
12671 opcode(0x0F,0x40);
12672 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12673 ins_pipe( pipe_cmov_reg );
12674 %}
12675
12676 // Compare 2 longs and CMOVE doubles
12677 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12678 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12679 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12680 ins_cost(200);
12681 expand %{
12682 fcmovDPR_regS(cmp,flags,dst,src);
12683 %}
12684 %}
12685
12686 // Compare 2 longs and CMOVE doubles
12687 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12688 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12689 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12690 ins_cost(200);
12691 expand %{
12692 fcmovD_regS(cmp,flags,dst,src);
12693 %}
12694 %}
12695
12696 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12697 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12698 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12699 ins_cost(200);
12700 expand %{
12701 fcmovFPR_regS(cmp,flags,dst,src);
12702 %}
12703 %}
12704
12705 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12706 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12707 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12708 ins_cost(200);
12709 expand %{
12710 fcmovF_regS(cmp,flags,dst,src);
12711 %}
12712 %}
12713
12714 //======
12715 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12716 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12717 match( Set flags (CmpL src zero ));
12718 effect(TEMP tmp);
12719 ins_cost(200);
12720 format %{ "MOV $tmp,$src.lo\n\t"
12721 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12722 ins_encode( long_cmp_flags0( src, tmp ) );
12723 ins_pipe( ialu_reg_reg_long );
12724 %}
12725
12726 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12727 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12728 match( Set flags (CmpL src1 src2 ));
12729 ins_cost(200+300);
12730 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12731 "JNE,s skip\n\t"
12732 "CMP $src1.hi,$src2.hi\n\t"
12733 "skip:\t" %}
12734 ins_encode( long_cmp_flags1( src1, src2 ) );
12735 ins_pipe( ialu_cr_reg_reg );
12736 %}
12737
12738 // Long compare reg == zero/reg OR reg != zero/reg
12739 // Just a wrapper for a normal branch, plus the predicate test.
12740 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12741 match(If cmp flags);
12742 effect(USE labl);
12743 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12744 expand %{
12745 jmpCon(cmp,flags,labl); // JEQ or JNE...
12746 %}
12747 %}
12748
12749 // Compare 2 longs and CMOVE longs.
12750 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12751 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12752 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12753 ins_cost(400);
12754 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12755 "CMOV$cmp $dst.hi,$src.hi" %}
12756 opcode(0x0F,0x40);
12757 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12758 ins_pipe( pipe_cmov_reg_long );
12759 %}
12760
12761 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12762 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12763 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12764 ins_cost(500);
12765 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12766 "CMOV$cmp $dst.hi,$src.hi" %}
12767 opcode(0x0F,0x40);
12768 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12769 ins_pipe( pipe_cmov_reg_long );
12770 %}
12771
12772 // Compare 2 longs and CMOVE ints.
12773 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12774 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12775 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12776 ins_cost(200);
12777 format %{ "CMOV$cmp $dst,$src" %}
12778 opcode(0x0F,0x40);
12779 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12780 ins_pipe( pipe_cmov_reg );
12781 %}
12782
12783 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12784 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12785 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12786 ins_cost(250);
12787 format %{ "CMOV$cmp $dst,$src" %}
12788 opcode(0x0F,0x40);
12789 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12790 ins_pipe( pipe_cmov_mem );
12791 %}
12792
12793 // Compare 2 longs and CMOVE ints.
12794 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12795 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12796 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12797 ins_cost(200);
12798 format %{ "CMOV$cmp $dst,$src" %}
12799 opcode(0x0F,0x40);
12800 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12801 ins_pipe( pipe_cmov_reg );
12802 %}
12803
12804 // Compare 2 longs and CMOVE doubles
12805 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12806 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12807 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12808 ins_cost(200);
12809 expand %{
12810 fcmovDPR_regS(cmp,flags,dst,src);
12811 %}
12812 %}
12813
12814 // Compare 2 longs and CMOVE doubles
12815 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12816 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12817 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12818 ins_cost(200);
12819 expand %{
12820 fcmovD_regS(cmp,flags,dst,src);
12821 %}
12822 %}
12823
12824 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12825 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12826 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12827 ins_cost(200);
12828 expand %{
12829 fcmovFPR_regS(cmp,flags,dst,src);
12830 %}
12831 %}
12832
12833 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12834 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12835 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12836 ins_cost(200);
12837 expand %{
12838 fcmovF_regS(cmp,flags,dst,src);
12839 %}
12840 %}
12841
12842 //======
12843 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12844 // Same as cmpL_reg_flags_LEGT except must negate src
12845 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12846 match( Set flags (CmpL src zero ));
12847 effect( TEMP tmp );
12848 ins_cost(300);
12849 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12850 "CMP $tmp,$src.lo\n\t"
12851 "SBB $tmp,$src.hi\n\t" %}
12852 ins_encode( long_cmp_flags3(src, tmp) );
12853 ins_pipe( ialu_reg_reg_long );
12854 %}
12855
12856 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12857 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12858 // requires a commuted test to get the same result.
12859 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12860 match( Set flags (CmpL src1 src2 ));
12861 effect( TEMP tmp );
12862 ins_cost(300);
12863 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12864 "MOV $tmp,$src2.hi\n\t"
12865 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12866 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12867 ins_pipe( ialu_cr_reg_reg );
12868 %}
12869
12870 // Long compares reg < zero/req OR reg >= zero/req.
12871 // Just a wrapper for a normal branch, plus the predicate test
12872 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12873 match(If cmp flags);
12874 effect(USE labl);
12875 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12876 ins_cost(300);
12877 expand %{
12878 jmpCon(cmp,flags,labl); // JGT or JLE...
12879 %}
12880 %}
12881
12882 // Compare 2 longs and CMOVE longs.
12883 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12884 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12885 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12886 ins_cost(400);
12887 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12888 "CMOV$cmp $dst.hi,$src.hi" %}
12889 opcode(0x0F,0x40);
12890 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12891 ins_pipe( pipe_cmov_reg_long );
12892 %}
12893
12894 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12895 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12896 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12897 ins_cost(500);
12898 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12899 "CMOV$cmp $dst.hi,$src.hi+4" %}
12900 opcode(0x0F,0x40);
12901 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12902 ins_pipe( pipe_cmov_reg_long );
12903 %}
12904
12905 // Compare 2 longs and CMOVE ints.
12906 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12907 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12908 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12909 ins_cost(200);
12910 format %{ "CMOV$cmp $dst,$src" %}
12911 opcode(0x0F,0x40);
12912 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12913 ins_pipe( pipe_cmov_reg );
12914 %}
12915
12916 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12917 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12918 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12919 ins_cost(250);
12920 format %{ "CMOV$cmp $dst,$src" %}
12921 opcode(0x0F,0x40);
12922 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12923 ins_pipe( pipe_cmov_mem );
12924 %}
12925
12926 // Compare 2 longs and CMOVE ptrs.
12927 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12928 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12929 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12930 ins_cost(200);
12931 format %{ "CMOV$cmp $dst,$src" %}
12932 opcode(0x0F,0x40);
12933 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12934 ins_pipe( pipe_cmov_reg );
12935 %}
12936
12937 // Compare 2 longs and CMOVE doubles
12938 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12939 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12940 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12941 ins_cost(200);
12942 expand %{
12943 fcmovDPR_regS(cmp,flags,dst,src);
12944 %}
12945 %}
12946
12947 // Compare 2 longs and CMOVE doubles
12948 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12949 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12950 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12951 ins_cost(200);
12952 expand %{
12953 fcmovD_regS(cmp,flags,dst,src);
12954 %}
12955 %}
12956
12957 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12958 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12959 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12960 ins_cost(200);
12961 expand %{
12962 fcmovFPR_regS(cmp,flags,dst,src);
12963 %}
12964 %}
12965
12966
12967 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12968 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12969 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12970 ins_cost(200);
12971 expand %{
12972 fcmovF_regS(cmp,flags,dst,src);
12973 %}
12974 %}
12975
12976
12977 // ============================================================================
12978 // Procedure Call/Return Instructions
12979 // Call Java Static Instruction
12980 // Note: If this code changes, the corresponding ret_addr_offset() and
12981 // compute_padding() functions will have to be adjusted.
12982 instruct CallStaticJavaDirect(method meth) %{
12983 match(CallStaticJava);
12984 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12985 effect(USE meth);
12986
12987 ins_cost(300);
12988 format %{ "CALL,static " %}
12989 opcode(0xE8); /* E8 cd */
12990 ins_encode( pre_call_resets,
12991 Java_Static_Call( meth ),
12992 call_epilog,
12993 post_call_FPU );
12994 ins_pipe( pipe_slow );
12995 ins_alignment(4);
12996 %}
12997
12998 // Call Java Static Instruction (method handle version)
12999 // Note: If this code changes, the corresponding ret_addr_offset() and
13000 // compute_padding() functions will have to be adjusted.
13001 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13002 match(CallStaticJava);
13003 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13004 effect(USE meth);
13005 // EBP is saved by all callees (for interpreter stack correction).
13006 // We use it here for a similar purpose, in {preserve,restore}_SP.
13007
13008 ins_cost(300);
13009 format %{ "CALL,static/MethodHandle " %}
13010 opcode(0xE8); /* E8 cd */
13011 ins_encode( pre_call_resets,
13012 preserve_SP,
13013 Java_Static_Call( meth ),
13014 restore_SP,
13015 call_epilog,
13016 post_call_FPU );
13017 ins_pipe( pipe_slow );
13018 ins_alignment(4);
13019 %}
13020
13021 // Call Java Dynamic Instruction
13022 // Note: If this code changes, the corresponding ret_addr_offset() and
13023 // compute_padding() functions will have to be adjusted.
13024 instruct CallDynamicJavaDirect(method meth) %{
13025 match(CallDynamicJava);
13026 effect(USE meth);
13027
13028 ins_cost(300);
13029 format %{ "MOV EAX,(oop)-1\n\t"
13030 "CALL,dynamic" %}
13031 opcode(0xE8); /* E8 cd */
13032 ins_encode( pre_call_resets,
13033 Java_Dynamic_Call( meth ),
13034 call_epilog,
13035 post_call_FPU );
13036 ins_pipe( pipe_slow );
13037 ins_alignment(4);
13038 %}
13039
13040 // Call Runtime Instruction
13041 instruct CallRuntimeDirect(method meth) %{
13042 match(CallRuntime );
13043 effect(USE meth);
13044
13045 ins_cost(300);
13046 format %{ "CALL,runtime " %}
13047 opcode(0xE8); /* E8 cd */
13048 // Use FFREEs to clear entries in float stack
13049 ins_encode( pre_call_resets,
13050 FFree_Float_Stack_All,
13051 Java_To_Runtime( meth ),
13052 post_call_FPU );
13053 ins_pipe( pipe_slow );
13054 %}
13055
13056 // Call runtime without safepoint
13057 instruct CallLeafDirect(method meth) %{
13058 match(CallLeaf);
13059 effect(USE meth);
13060
13061 ins_cost(300);
13062 format %{ "CALL_LEAF,runtime " %}
13063 opcode(0xE8); /* E8 cd */
13064 ins_encode( pre_call_resets,
13065 FFree_Float_Stack_All,
13066 Java_To_Runtime( meth ),
13067 Verify_FPU_For_Leaf, post_call_FPU );
13068 ins_pipe( pipe_slow );
13069 %}
13070
13071 instruct CallLeafNoFPDirect(method meth) %{
13072 match(CallLeafNoFP);
13073 effect(USE meth);
13074
13075 ins_cost(300);
13076 format %{ "CALL_LEAF_NOFP,runtime " %}
13077 opcode(0xE8); /* E8 cd */
13078 ins_encode(Java_To_Runtime(meth));
13079 ins_pipe( pipe_slow );
13080 %}
13081
13082
13083 // Return Instruction
13084 // Remove the return address & jump to it.
13085 instruct Ret() %{
13086 match(Return);
13087 format %{ "RET" %}
13088 opcode(0xC3);
13089 ins_encode(OpcP);
13090 ins_pipe( pipe_jmp );
13091 %}
13092
13093 // Tail Call; Jump from runtime stub to Java code.
13094 // Also known as an 'interprocedural jump'.
13095 // Target of jump will eventually return to caller.
13096 // TailJump below removes the return address.
13097 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13098 match(TailCall jump_target method_oop );
13099 ins_cost(300);
13100 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13101 opcode(0xFF, 0x4); /* Opcode FF /4 */
13102 ins_encode( OpcP, RegOpc(jump_target) );
13103 ins_pipe( pipe_jmp );
13104 %}
13105
13106
13107 // Tail Jump; remove the return address; jump to target.
13108 // TailCall above leaves the return address around.
13109 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13110 match( TailJump jump_target ex_oop );
13111 ins_cost(300);
13112 format %{ "POP EDX\t# pop return address into dummy\n\t"
13113 "JMP $jump_target " %}
13114 opcode(0xFF, 0x4); /* Opcode FF /4 */
13115 ins_encode( enc_pop_rdx,
13116 OpcP, RegOpc(jump_target) );
13117 ins_pipe( pipe_jmp );
13118 %}
13119
13120 // Create exception oop: created by stack-crawling runtime code.
13121 // Created exception is now available to this handler, and is setup
13122 // just prior to jumping to this handler. No code emitted.
13123 instruct CreateException( eAXRegP ex_oop )
13124 %{
13125 match(Set ex_oop (CreateEx));
13126
13127 size(0);
13128 // use the following format syntax
13129 format %{ "# exception oop is in EAX; no code emitted" %}
13130 ins_encode();
13131 ins_pipe( empty );
13132 %}
13133
13134
13135 // Rethrow exception:
13136 // The exception oop will come in the first argument position.
13137 // Then JUMP (not call) to the rethrow stub code.
13138 instruct RethrowException()
13139 %{
13140 match(Rethrow);
13141
13142 // use the following format syntax
13143 format %{ "JMP rethrow_stub" %}
13144 ins_encode(enc_rethrow);
13145 ins_pipe( pipe_jmp );
13146 %}
13147
13148 // inlined locking and unlocking
13149
13150
13151 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13152 match( Set cr (FastLock object box) );
13153 effect( TEMP tmp, TEMP scr, USE_KILL box );
13154 ins_cost(300);
13155 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13156 ins_encode( Fast_Lock(object,box,tmp,scr) );
13157 ins_pipe( pipe_slow );
13158 %}
13159
13160 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13161 match( Set cr (FastUnlock object box) );
13162 effect( TEMP tmp, USE_KILL box );
13163 ins_cost(300);
13164 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13165 ins_encode( Fast_Unlock(object,box,tmp) );
13166 ins_pipe( pipe_slow );
13167 %}
13168
13169
13170
13171 // ============================================================================
13172 // Safepoint Instruction
13173 instruct safePoint_poll(eFlagsReg cr) %{
13174 match(SafePoint);
13175 effect(KILL cr);
13176
13177 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13178 // On SPARC that might be acceptable as we can generate the address with
13179 // just a sethi, saving an or. By polling at offset 0 we can end up
13180 // putting additional pressure on the index-0 in the D$. Because of
13181 // alignment (just like the situation at hand) the lower indices tend
13182 // to see more traffic. It'd be better to change the polling address
13183 // to offset 0 of the last $line in the polling page.
13184
13185 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13186 ins_cost(125);
13187 size(6) ;
13188 ins_encode( Safepoint_Poll() );
13189 ins_pipe( ialu_reg_mem );
13190 %}
13191
13192
13193 // ============================================================================
13194 // This name is KNOWN by the ADLC and cannot be changed.
13195 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13196 // for this guy.
13197 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13198 match(Set dst (ThreadLocal));
13199 effect(DEF dst, KILL cr);
13200
13201 format %{ "MOV $dst, Thread::current()" %}
13202 ins_encode %{
13203 Register dstReg = as_Register($dst$$reg);
13204 __ get_thread(dstReg);
13205 %}
13206 ins_pipe( ialu_reg_fat );
13207 %}
13208
13209
13210
13211 //----------PEEPHOLE RULES-----------------------------------------------------
13212 // These must follow all instruction definitions as they use the names
13213 // defined in the instructions definitions.
13214 //
13215 // peepmatch ( root_instr_name [preceding_instruction]* );
13216 //
13217 // peepconstraint %{
13218 // (instruction_number.operand_name relational_op instruction_number.operand_name
13219 // [, ...] );
13220 // // instruction numbers are zero-based using left to right order in peepmatch
13221 //
13222 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13223 // // provide an instruction_number.operand_name for each operand that appears
13224 // // in the replacement instruction's match rule
13225 //
13226 // ---------VM FLAGS---------------------------------------------------------
13227 //
13228 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13229 //
13230 // Each peephole rule is given an identifying number starting with zero and
13231 // increasing by one in the order seen by the parser. An individual peephole
13232 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13233 // on the command-line.
13234 //
13235 // ---------CURRENT LIMITATIONS----------------------------------------------
13236 //
13237 // Only match adjacent instructions in same basic block
13238 // Only equality constraints
13239 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13240 // Only one replacement instruction
13241 //
13242 // ---------EXAMPLE----------------------------------------------------------
13243 //
13244 // // pertinent parts of existing instructions in architecture description
13245 // instruct movI(rRegI dst, rRegI src) %{
13246 // match(Set dst (CopyI src));
13247 // %}
13248 //
13249 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13250 // match(Set dst (AddI dst src));
13251 // effect(KILL cr);
13252 // %}
13253 //
13254 // // Change (inc mov) to lea
13255 // peephole %{
13256 // // increment preceeded by register-register move
13257 // peepmatch ( incI_eReg movI );
13258 // // require that the destination register of the increment
13259 // // match the destination register of the move
13260 // peepconstraint ( 0.dst == 1.dst );
13261 // // construct a replacement instruction that sets
13262 // // the destination to ( move's source register + one )
13263 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13264 // %}
13265 //
13266 // Implementation no longer uses movX instructions since
13267 // machine-independent system no longer uses CopyX nodes.
13268 //
13269 // peephole %{
13270 // peepmatch ( incI_eReg movI );
13271 // peepconstraint ( 0.dst == 1.dst );
13272 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13273 // %}
13274 //
13275 // peephole %{
13276 // peepmatch ( decI_eReg movI );
13277 // peepconstraint ( 0.dst == 1.dst );
13278 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13279 // %}
13280 //
13281 // peephole %{
13282 // peepmatch ( addI_eReg_imm movI );
13283 // peepconstraint ( 0.dst == 1.dst );
13284 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13285 // %}
13286 //
13287 // peephole %{
13288 // peepmatch ( addP_eReg_imm movP );
13289 // peepconstraint ( 0.dst == 1.dst );
13290 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13291 // %}
13292
13293 // // Change load of spilled value to only a spill
13294 // instruct storeI(memory mem, rRegI src) %{
13295 // match(Set mem (StoreI mem src));
13296 // %}
13297 //
13298 // instruct loadI(rRegI dst, memory mem) %{
13299 // match(Set dst (LoadI mem));
13300 // %}
13301 //
13302 peephole %{
13303 peepmatch ( loadI storeI );
13304 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13305 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13306 %}
13307
13308 //----------SMARTSPILL RULES---------------------------------------------------
13309 // These must follow all instruction definitions as they use the names
13310 // defined in the instructions definitions.