1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
186
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
201
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
215
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
228
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
241
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
244
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
247
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
250
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
253
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
256
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
259
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
262
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
277
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
290
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
304
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
318
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
321
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
324
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
327
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
342
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
356
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
369
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
372
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
375
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
378
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
381
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
384
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
387
388 %}
389
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
396
397 #define __ _masm.
398
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
402 static int clear_avx_size() {
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
404 }
405
406 // !!!!! Special hack to get all types of calls to specify the byte offset
407 // from the start of the call to the point where the return address
408 // will point.
409 int MachCallStaticJavaNode::ret_addr_offset()
410 {
411 int offset = 5; // 5 bytes from start of call to where return address points
412 offset += clear_avx_size();
413 if (_method_handle_invoke)
414 offset += preserve_SP_size();
415 return offset;
416 }
417
418 int MachCallDynamicJavaNode::ret_addr_offset()
419 {
420 int offset = 15; // 15 bytes from start of call to where return address points
421 offset += clear_avx_size();
422 return offset;
423 }
424
425 int MachCallRuntimeNode::ret_addr_offset() {
426 int offset = 13; // movq r10,#addr; callq (r10)
427 offset += clear_avx_size();
428 return offset;
429 }
430
431 // Indicate if the safepoint node needs the polling page as an input,
432 // it does if the polling page is more than disp32 away.
433 bool SafePointNode::needs_polling_address_input()
434 {
435 return Assembler::is_polling_page_far();
436 }
437
438 //
439 // Compute padding required for nodes which need alignment
440 //
441
442 // The address of the call instruction needs to be 4-byte aligned to
443 // ensure that it does not span a cache line so that it can be patched.
444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
445 {
446 current_offset += clear_avx_size(); // skip vzeroupper
447 current_offset += 1; // skip call opcode byte
448 return round_to(current_offset, alignment_required()) - current_offset;
449 }
450
451 // The address of the call instruction needs to be 4-byte aligned to
452 // ensure that it does not span a cache line so that it can be patched.
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
454 {
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
456 current_offset += clear_avx_size(); // skip vzeroupper
457 current_offset += 1; // skip call opcode byte
458 return round_to(current_offset, alignment_required()) - current_offset;
459 }
460
461 // The address of the call instruction needs to be 4-byte aligned to
462 // ensure that it does not span a cache line so that it can be patched.
463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
464 {
465 current_offset += clear_avx_size(); // skip vzeroupper
466 current_offset += 11; // skip movq instruction + call opcode byte
467 return round_to(current_offset, alignment_required()) - current_offset;
468 }
469
470 // EMIT_RM()
471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
473 cbuf.insts()->emit_int8(c);
474 }
475
476 // EMIT_CC()
477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
478 unsigned char c = (unsigned char) (f1 | f2);
479 cbuf.insts()->emit_int8(c);
480 }
481
482 // EMIT_OPCODE()
483 void emit_opcode(CodeBuffer &cbuf, int code) {
484 cbuf.insts()->emit_int8((unsigned char) code);
485 }
486
487 // EMIT_OPCODE() w/ relocation information
488 void emit_opcode(CodeBuffer &cbuf,
489 int code, relocInfo::relocType reloc, int offset, int format)
490 {
491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
492 emit_opcode(cbuf, code);
493 }
494
495 // EMIT_D8()
496 void emit_d8(CodeBuffer &cbuf, int d8) {
497 cbuf.insts()->emit_int8((unsigned char) d8);
498 }
499
500 // EMIT_D16()
501 void emit_d16(CodeBuffer &cbuf, int d16) {
502 cbuf.insts()->emit_int16(d16);
503 }
504
505 // EMIT_D32()
506 void emit_d32(CodeBuffer &cbuf, int d32) {
507 cbuf.insts()->emit_int32(d32);
508 }
509
510 // EMIT_D64()
511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
512 cbuf.insts()->emit_int64(d64);
513 }
514
515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
516 void emit_d32_reloc(CodeBuffer& cbuf,
517 int d32,
518 relocInfo::relocType reloc,
519 int format)
520 {
521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
523 cbuf.insts()->emit_int32(d32);
524 }
525
526 // emit 32 bit value and construct relocation entry from RelocationHolder
527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
528 #ifdef ASSERT
529 if (rspec.reloc()->type() == relocInfo::oop_type &&
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
533 }
534 #endif
535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
536 cbuf.insts()->emit_int32(d32);
537 }
538
539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
540 address next_ip = cbuf.insts_end() + 4;
541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
542 external_word_Relocation::spec(addr),
543 RELOC_DISP32);
544 }
545
546
547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
550 cbuf.insts()->emit_int64(d64);
551 }
552
553 // emit 64 bit value and construct relocation entry from RelocationHolder
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
555 #ifdef ASSERT
556 if (rspec.reloc()->type() == relocInfo::oop_type &&
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
560 "cannot embed scavengable oops in code");
561 }
562 #endif
563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
564 cbuf.insts()->emit_int64(d64);
565 }
566
567 // Access stack slot for load or store
568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
569 {
570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
571 if (-0x80 <= disp && disp < 0x80) {
572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
574 emit_d8(cbuf, disp); // Displacement // R/M byte
575 } else {
576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
578 emit_d32(cbuf, disp); // Displacement // R/M byte
579 }
580 }
581
582 // rRegI ereg, memory mem) %{ // emit_reg_mem
583 void encode_RegMem(CodeBuffer &cbuf,
584 int reg,
585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
586 {
587 assert(disp_reloc == relocInfo::none, "cannot have disp");
588 int regenc = reg & 7;
589 int baseenc = base & 7;
590 int indexenc = index & 7;
591
592 // There is no index & no scale, use form without SIB byte
593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
598 // If 8-bit displacement, mode 0x1
599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
600 emit_d8(cbuf, disp);
601 } else {
602 // If 32-bit displacement
603 if (base == -1) { // Special flag for absolute address
604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
605 if (disp_reloc != relocInfo::none) {
606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
607 } else {
608 emit_d32(cbuf, disp);
609 }
610 } else {
611 // Normal base + offset
612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
613 if (disp_reloc != relocInfo::none) {
614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
615 } else {
616 emit_d32(cbuf, disp);
617 }
618 }
619 }
620 } else {
621 // Else, encode with the SIB byte
622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
624 // If no displacement
625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
626 emit_rm(cbuf, scale, indexenc, baseenc);
627 } else {
628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
629 // If 8-bit displacement, mode 0x1
630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
631 emit_rm(cbuf, scale, indexenc, baseenc);
632 emit_d8(cbuf, disp);
633 } else {
634 // If 32-bit displacement
635 if (base == 0x04 ) {
636 emit_rm(cbuf, 0x2, regenc, 0x4);
637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
638 } else {
639 emit_rm(cbuf, 0x2, regenc, 0x4);
640 emit_rm(cbuf, scale, indexenc, baseenc); // *
641 }
642 if (disp_reloc != relocInfo::none) {
643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
644 } else {
645 emit_d32(cbuf, disp);
646 }
647 }
648 }
649 }
650 }
651
652 // This could be in MacroAssembler but it's fairly C2 specific
653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
654 Label exit;
655 __ jccb(Assembler::noParity, exit);
656 __ pushf();
657 //
658 // comiss/ucomiss instructions set ZF,PF,CF flags and
659 // zero OF,AF,SF for NaN values.
660 // Fixup flags by zeroing ZF,PF so that compare of NaN
661 // values returns 'less than' result (CF is set).
662 // Leave the rest of flags unchanged.
663 //
664 // 7 6 5 4 3 2 1 0
665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
666 // 0 0 1 0 1 0 1 1 (0x2B)
667 //
668 __ andq(Address(rsp, 0), 0xffffff2b);
669 __ popf();
670 __ bind(exit);
671 }
672
673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
674 Label done;
675 __ movl(dst, -1);
676 __ jcc(Assembler::parity, done);
677 __ jcc(Assembler::below, done);
678 __ setb(Assembler::notEqual, dst);
679 __ movzbl(dst, dst);
680 __ bind(done);
681 }
682
683
684 //=============================================================================
685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
686
687 int Compile::ConstantTable::calculate_table_base_offset() const {
688 return 0; // absolute addressing, no offset
689 }
690
691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
692 // Empty encoding
693 }
694
695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
696 return 0;
697 }
698
699 #ifndef PRODUCT
700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
701 st->print("# MachConstantBaseNode (empty encoding)");
702 }
703 #endif
704
705
706 //=============================================================================
707 #ifndef PRODUCT
708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
709 Compile* C = ra_->C;
710
711 int framesize = C->frame_slots() << LogBytesPerInt;
712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
713 // Remove wordSize for return addr which is already pushed.
714 framesize -= wordSize;
715
716 if (C->need_stack_bang(framesize)) {
717 framesize -= wordSize;
718 st->print("# stack bang");
719 st->print("\n\t");
720 st->print("pushq rbp\t# Save rbp");
721 if (framesize) {
722 st->print("\n\t");
723 st->print("subq rsp, #%d\t# Create frame",framesize);
724 }
725 } else {
726 st->print("subq rsp, #%d\t# Create frame",framesize);
727 st->print("\n\t");
728 framesize -= wordSize;
729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
730 }
731
732 if (VerifyStackAtCalls) {
733 st->print("\n\t");
734 framesize -= wordSize;
735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
736 #ifdef ASSERT
737 st->print("\n\t");
738 st->print("# stack alignment check");
739 #endif
740 }
741 st->cr();
742 }
743 #endif
744
745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
746 Compile* C = ra_->C;
747 MacroAssembler _masm(&cbuf);
748
749 int framesize = C->frame_slots() << LogBytesPerInt;
750
751 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
752
753 C->set_frame_complete(cbuf.insts_size());
754
755 if (C->has_mach_constant_base_node()) {
756 // NOTE: We set the table base offset here because users might be
757 // emitted before MachConstantBaseNode.
758 Compile::ConstantTable& constant_table = C->constant_table();
759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
760 }
761 }
762
763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
764 {
765 return MachNode::size(ra_); // too many variables; just compute it
766 // the hard way
767 }
768
769 int MachPrologNode::reloc() const
770 {
771 return 0; // a large enough number
772 }
773
774 //=============================================================================
775 #ifndef PRODUCT
776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
777 {
778 Compile* C = ra_->C;
779 if (C->max_vector_size() > 16) {
780 st->print("vzeroupper");
781 st->cr(); st->print("\t");
782 }
783
784 int framesize = C->frame_slots() << LogBytesPerInt;
785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
786 // Remove word for return adr already pushed
787 // and RBP
788 framesize -= 2*wordSize;
789
790 if (framesize) {
791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
792 st->print("\t");
793 }
794
795 st->print_cr("popq rbp");
796 if (do_polling() && C->is_method_compilation()) {
797 st->print("\t");
798 if (Assembler::is_polling_page_far()) {
799 st->print_cr("movq rscratch1, #polling_page_address\n\t"
800 "testl rax, [rscratch1]\t"
801 "# Safepoint: poll for GC");
802 } else {
803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
804 "# Safepoint: poll for GC");
805 }
806 }
807 }
808 #endif
809
810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
811 {
812 Compile* C = ra_->C;
813 if (C->max_vector_size() > 16) {
814 // Clear upper bits of YMM registers when current compiled code uses
815 // wide vectors to avoid AVX <-> SSE transition penalty during call.
816 MacroAssembler _masm(&cbuf);
817 __ vzeroupper();
818 }
819
820 int framesize = C->frame_slots() << LogBytesPerInt;
821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
822 // Remove word for return adr already pushed
823 // and RBP
824 framesize -= 2*wordSize;
825
826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
827
828 if (framesize) {
829 emit_opcode(cbuf, Assembler::REX_W);
830 if (framesize < 0x80) {
831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
832 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
833 emit_d8(cbuf, framesize);
834 } else {
835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
836 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
837 emit_d32(cbuf, framesize);
838 }
839 }
840
841 // popq rbp
842 emit_opcode(cbuf, 0x58 | RBP_enc);
843
844 if (do_polling() && C->is_method_compilation()) {
845 MacroAssembler _masm(&cbuf);
846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
847 if (Assembler::is_polling_page_far()) {
848 __ lea(rscratch1, polling_page);
849 __ relocate(relocInfo::poll_return_type);
850 __ testl(rax, Address(rscratch1, 0));
851 } else {
852 __ testl(rax, polling_page);
853 }
854 }
855 }
856
857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
858 {
859 return MachNode::size(ra_); // too many variables; just compute it
860 // the hard way
861 }
862
863 int MachEpilogNode::reloc() const
864 {
865 return 2; // a large enough number
866 }
867
868 const Pipeline* MachEpilogNode::pipeline() const
869 {
870 return MachNode::pipeline_class();
871 }
872
873 int MachEpilogNode::safepoint_offset() const
874 {
875 return 0;
876 }
877
878 //=============================================================================
879
880 enum RC {
881 rc_bad,
882 rc_int,
883 rc_float,
884 rc_stack
885 };
886
887 static enum RC rc_class(OptoReg::Name reg)
888 {
889 if( !OptoReg::is_valid(reg) ) return rc_bad;
890
891 if (OptoReg::is_stack(reg)) return rc_stack;
892
893 VMReg r = OptoReg::as_VMReg(reg);
894
895 if (r->is_Register()) return rc_int;
896
897 assert(r->is_XMMRegister(), "must be");
898 return rc_float;
899 }
900
901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
903 int src_hi, int dst_hi, uint ireg, outputStream* st);
904
905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
906 int stack_offset, int reg, uint ireg, outputStream* st);
907
908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
909 int dst_offset, uint ireg, outputStream* st) {
910 if (cbuf) {
911 MacroAssembler _masm(cbuf);
912 switch (ireg) {
913 case Op_VecS:
914 __ movq(Address(rsp, -8), rax);
915 __ movl(rax, Address(rsp, src_offset));
916 __ movl(Address(rsp, dst_offset), rax);
917 __ movq(rax, Address(rsp, -8));
918 break;
919 case Op_VecD:
920 __ pushq(Address(rsp, src_offset));
921 __ popq (Address(rsp, dst_offset));
922 break;
923 case Op_VecX:
924 __ pushq(Address(rsp, src_offset));
925 __ popq (Address(rsp, dst_offset));
926 __ pushq(Address(rsp, src_offset+8));
927 __ popq (Address(rsp, dst_offset+8));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 #ifndef PRODUCT
939 } else {
940 switch (ireg) {
941 case Op_VecS:
942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
943 "movl rax, [rsp + #%d]\n\t"
944 "movl [rsp + #%d], rax\n\t"
945 "movq rax, [rsp - #8]",
946 src_offset, dst_offset);
947 break;
948 case Op_VecD:
949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
950 "popq [rsp + #%d]",
951 src_offset, dst_offset);
952 break;
953 case Op_VecX:
954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
955 "popq [rsp + #%d]\n\t"
956 "pushq [rsp + #%d]\n\t"
957 "popq [rsp + #%d]",
958 src_offset, dst_offset, src_offset+8, dst_offset+8);
959 break;
960 case Op_VecY:
961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
962 "vmovdqu xmm0, [rsp + #%d]\n\t"
963 "vmovdqu [rsp + #%d], xmm0\n\t"
964 "vmovdqu xmm0, [rsp - #32]",
965 src_offset, dst_offset);
966 break;
967 default:
968 ShouldNotReachHere();
969 }
970 #endif
971 }
972 }
973
974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
975 PhaseRegAlloc* ra_,
976 bool do_size,
977 outputStream* st) const {
978 assert(cbuf != NULL || st != NULL, "sanity");
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this);
983 OptoReg::Name dst_first = ra_->get_reg_first(this);
984
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
989
990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
991 "must move at least 1 register" );
992
993 if (src_first == dst_first && src_second == dst_second) {
994 // Self copy, no move
995 return 0;
996 }
997 if (bottom_type()->isa_vect() != NULL) {
998 uint ireg = ideal_reg();
999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1002 // mem -> mem
1003 int src_offset = ra_->reg2offset(src_first);
1004 int dst_offset = ra_->reg2offset(dst_first);
1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1009 int stack_offset = ra_->reg2offset(dst_first);
1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1012 int stack_offset = ra_->reg2offset(src_first);
1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1014 } else {
1015 ShouldNotReachHere();
1016 }
1017 return 0;
1018 }
1019 if (src_first_rc == rc_stack) {
1020 // mem ->
1021 if (dst_first_rc == rc_stack) {
1022 // mem -> mem
1023 assert(src_second != dst_first, "overlap");
1024 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1026 // 64-bit
1027 int src_offset = ra_->reg2offset(src_first);
1028 int dst_offset = ra_->reg2offset(dst_first);
1029 if (cbuf) {
1030 MacroAssembler _masm(cbuf);
1031 __ pushq(Address(rsp, src_offset));
1032 __ popq (Address(rsp, dst_offset));
1033 #ifndef PRODUCT
1034 } else {
1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1036 "popq [rsp + #%d]",
1037 src_offset, dst_offset);
1038 #endif
1039 }
1040 } else {
1041 // 32-bit
1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1044 // No pushl/popl, so:
1045 int src_offset = ra_->reg2offset(src_first);
1046 int dst_offset = ra_->reg2offset(dst_first);
1047 if (cbuf) {
1048 MacroAssembler _masm(cbuf);
1049 __ movq(Address(rsp, -8), rax);
1050 __ movl(rax, Address(rsp, src_offset));
1051 __ movl(Address(rsp, dst_offset), rax);
1052 __ movq(rax, Address(rsp, -8));
1053 #ifndef PRODUCT
1054 } else {
1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1056 "movl rax, [rsp + #%d]\n\t"
1057 "movl [rsp + #%d], rax\n\t"
1058 "movq rax, [rsp - #8]",
1059 src_offset, dst_offset);
1060 #endif
1061 }
1062 }
1063 return 0;
1064 } else if (dst_first_rc == rc_int) {
1065 // mem -> gpr
1066 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1068 // 64-bit
1069 int offset = ra_->reg2offset(src_first);
1070 if (cbuf) {
1071 MacroAssembler _masm(cbuf);
1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1073 #ifndef PRODUCT
1074 } else {
1075 st->print("movq %s, [rsp + #%d]\t# spill",
1076 Matcher::regName[dst_first],
1077 offset);
1078 #endif
1079 }
1080 } else {
1081 // 32-bit
1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1084 int offset = ra_->reg2offset(src_first);
1085 if (cbuf) {
1086 MacroAssembler _masm(cbuf);
1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1088 #ifndef PRODUCT
1089 } else {
1090 st->print("movl %s, [rsp + #%d]\t# spill",
1091 Matcher::regName[dst_first],
1092 offset);
1093 #endif
1094 }
1095 }
1096 return 0;
1097 } else if (dst_first_rc == rc_float) {
1098 // mem-> xmm
1099 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1101 // 64-bit
1102 int offset = ra_->reg2offset(src_first);
1103 if (cbuf) {
1104 MacroAssembler _masm(cbuf);
1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1106 #ifndef PRODUCT
1107 } else {
1108 st->print("%s %s, [rsp + #%d]\t# spill",
1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1110 Matcher::regName[dst_first],
1111 offset);
1112 #endif
1113 }
1114 } else {
1115 // 32-bit
1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1118 int offset = ra_->reg2offset(src_first);
1119 if (cbuf) {
1120 MacroAssembler _masm(cbuf);
1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1122 #ifndef PRODUCT
1123 } else {
1124 st->print("movss %s, [rsp + #%d]\t# spill",
1125 Matcher::regName[dst_first],
1126 offset);
1127 #endif
1128 }
1129 }
1130 return 0;
1131 }
1132 } else if (src_first_rc == rc_int) {
1133 // gpr ->
1134 if (dst_first_rc == rc_stack) {
1135 // gpr -> mem
1136 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1138 // 64-bit
1139 int offset = ra_->reg2offset(dst_first);
1140 if (cbuf) {
1141 MacroAssembler _masm(cbuf);
1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1143 #ifndef PRODUCT
1144 } else {
1145 st->print("movq [rsp + #%d], %s\t# spill",
1146 offset,
1147 Matcher::regName[src_first]);
1148 #endif
1149 }
1150 } else {
1151 // 32-bit
1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1154 int offset = ra_->reg2offset(dst_first);
1155 if (cbuf) {
1156 MacroAssembler _masm(cbuf);
1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1158 #ifndef PRODUCT
1159 } else {
1160 st->print("movl [rsp + #%d], %s\t# spill",
1161 offset,
1162 Matcher::regName[src_first]);
1163 #endif
1164 }
1165 }
1166 return 0;
1167 } else if (dst_first_rc == rc_int) {
1168 // gpr -> gpr
1169 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1171 // 64-bit
1172 if (cbuf) {
1173 MacroAssembler _masm(cbuf);
1174 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1175 as_Register(Matcher::_regEncode[src_first]));
1176 #ifndef PRODUCT
1177 } else {
1178 st->print("movq %s, %s\t# spill",
1179 Matcher::regName[dst_first],
1180 Matcher::regName[src_first]);
1181 #endif
1182 }
1183 return 0;
1184 } else {
1185 // 32-bit
1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1188 if (cbuf) {
1189 MacroAssembler _masm(cbuf);
1190 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1191 as_Register(Matcher::_regEncode[src_first]));
1192 #ifndef PRODUCT
1193 } else {
1194 st->print("movl %s, %s\t# spill",
1195 Matcher::regName[dst_first],
1196 Matcher::regName[src_first]);
1197 #endif
1198 }
1199 return 0;
1200 }
1201 } else if (dst_first_rc == rc_float) {
1202 // gpr -> xmm
1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1205 // 64-bit
1206 if (cbuf) {
1207 MacroAssembler _masm(cbuf);
1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1209 #ifndef PRODUCT
1210 } else {
1211 st->print("movdq %s, %s\t# spill",
1212 Matcher::regName[dst_first],
1213 Matcher::regName[src_first]);
1214 #endif
1215 }
1216 } else {
1217 // 32-bit
1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1220 if (cbuf) {
1221 MacroAssembler _masm(cbuf);
1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1223 #ifndef PRODUCT
1224 } else {
1225 st->print("movdl %s, %s\t# spill",
1226 Matcher::regName[dst_first],
1227 Matcher::regName[src_first]);
1228 #endif
1229 }
1230 }
1231 return 0;
1232 }
1233 } else if (src_first_rc == rc_float) {
1234 // xmm ->
1235 if (dst_first_rc == rc_stack) {
1236 // xmm -> mem
1237 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1239 // 64-bit
1240 int offset = ra_->reg2offset(dst_first);
1241 if (cbuf) {
1242 MacroAssembler _masm(cbuf);
1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1244 #ifndef PRODUCT
1245 } else {
1246 st->print("movsd [rsp + #%d], %s\t# spill",
1247 offset,
1248 Matcher::regName[src_first]);
1249 #endif
1250 }
1251 } else {
1252 // 32-bit
1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1255 int offset = ra_->reg2offset(dst_first);
1256 if (cbuf) {
1257 MacroAssembler _masm(cbuf);
1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1259 #ifndef PRODUCT
1260 } else {
1261 st->print("movss [rsp + #%d], %s\t# spill",
1262 offset,
1263 Matcher::regName[src_first]);
1264 #endif
1265 }
1266 }
1267 return 0;
1268 } else if (dst_first_rc == rc_int) {
1269 // xmm -> gpr
1270 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1272 // 64-bit
1273 if (cbuf) {
1274 MacroAssembler _masm(cbuf);
1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1276 #ifndef PRODUCT
1277 } else {
1278 st->print("movdq %s, %s\t# spill",
1279 Matcher::regName[dst_first],
1280 Matcher::regName[src_first]);
1281 #endif
1282 }
1283 } else {
1284 // 32-bit
1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1287 if (cbuf) {
1288 MacroAssembler _masm(cbuf);
1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1290 #ifndef PRODUCT
1291 } else {
1292 st->print("movdl %s, %s\t# spill",
1293 Matcher::regName[dst_first],
1294 Matcher::regName[src_first]);
1295 #endif
1296 }
1297 }
1298 return 0;
1299 } else if (dst_first_rc == rc_float) {
1300 // xmm -> xmm
1301 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1303 // 64-bit
1304 if (cbuf) {
1305 MacroAssembler _masm(cbuf);
1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1307 #ifndef PRODUCT
1308 } else {
1309 st->print("%s %s, %s\t# spill",
1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1311 Matcher::regName[dst_first],
1312 Matcher::regName[src_first]);
1313 #endif
1314 }
1315 } else {
1316 // 32-bit
1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1319 if (cbuf) {
1320 MacroAssembler _masm(cbuf);
1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1322 #ifndef PRODUCT
1323 } else {
1324 st->print("%s %s, %s\t# spill",
1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1326 Matcher::regName[dst_first],
1327 Matcher::regName[src_first]);
1328 #endif
1329 }
1330 }
1331 return 0;
1332 }
1333 }
1334
1335 assert(0," foo ");
1336 Unimplemented();
1337 return 0;
1338 }
1339
1340 #ifndef PRODUCT
1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1342 implementation(NULL, ra_, false, st);
1343 }
1344 #endif
1345
1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1347 implementation(&cbuf, ra_, false, NULL);
1348 }
1349
1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1351 return MachNode::size(ra_);
1352 }
1353
1354 //=============================================================================
1355 #ifndef PRODUCT
1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1357 {
1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1359 int reg = ra_->get_reg_first(this);
1360 st->print("leaq %s, [rsp + #%d]\t# box lock",
1361 Matcher::regName[reg], offset);
1362 }
1363 #endif
1364
1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1366 {
1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1368 int reg = ra_->get_encode(this);
1369 if (offset >= 0x80) {
1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1372 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1374 emit_d32(cbuf, offset);
1375 } else {
1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1378 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1380 emit_d8(cbuf, offset);
1381 }
1382 }
1383
1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1385 {
1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1387 return (offset < 0x80) ? 5 : 8; // REX
1388 }
1389
1390 //=============================================================================
1391 #ifndef PRODUCT
1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1393 {
1394 if (UseCompressedClassPointers) {
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1398 } else {
1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1400 "# Inline cache check");
1401 }
1402 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1403 st->print_cr("\tnop\t# nops to align entry point");
1404 }
1405 #endif
1406
1407 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1408 {
1409 MacroAssembler masm(&cbuf);
1410 uint insts_size = cbuf.insts_size();
1411 if (UseCompressedClassPointers) {
1412 masm.load_klass(rscratch1, j_rarg0);
1413 masm.cmpptr(rax, rscratch1);
1414 } else {
1415 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1416 }
1417
1418 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1419
1420 /* WARNING these NOPs are critical so that verified entry point is properly
1421 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1422 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1423 if (OptoBreakpoint) {
1424 // Leave space for int3
1425 nops_cnt -= 1;
1426 }
1427 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1428 if (nops_cnt > 0)
1429 masm.nop(nops_cnt);
1430 }
1431
1432 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1433 {
1434 return MachNode::size(ra_); // too many variables; just compute it
1435 // the hard way
1436 }
1437
1438
1439 //=============================================================================
1440 uint size_exception_handler()
1441 {
1442 // NativeCall instruction size is the same as NativeJump.
1443 // Note that this value is also credited (in output.cpp) to
1444 // the size of the code section.
1445 return NativeJump::instruction_size;
1446 }
1447
1448 // Emit exception handler code.
1449 int emit_exception_handler(CodeBuffer& cbuf)
1450 {
1451
1452 // Note that the code buffer's insts_mark is always relative to insts.
1453 // That's why we must use the macroassembler to generate a handler.
1454 MacroAssembler _masm(&cbuf);
1455 address base =
1456 __ start_a_stub(size_exception_handler());
1457 if (base == NULL) return 0; // CodeBuffer::expand failed
1458 int offset = __ offset();
1459 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1460 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1461 __ end_a_stub();
1462 return offset;
1463 }
1464
1465 uint size_deopt_handler()
1466 {
1467 // three 5 byte instructions
1468 return 15;
1469 }
1470
1471 // Emit deopt handler code.
1472 int emit_deopt_handler(CodeBuffer& cbuf)
1473 {
1474
1475 // Note that the code buffer's insts_mark is always relative to insts.
1476 // That's why we must use the macroassembler to generate a handler.
1477 MacroAssembler _masm(&cbuf);
1478 address base =
1479 __ start_a_stub(size_deopt_handler());
1480 if (base == NULL) return 0; // CodeBuffer::expand failed
1481 int offset = __ offset();
1482 address the_pc = (address) __ pc();
1483 Label next;
1484 // push a "the_pc" on the stack without destroying any registers
1485 // as they all may be live.
1486
1487 // push address of "next"
1488 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1489 __ bind(next);
1490 // adjust it so it matches "the_pc"
1491 __ subptr(Address(rsp, 0), __ offset() - offset);
1492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1493 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1494 __ end_a_stub();
1495 return offset;
1496 }
1497
1498 int Matcher::regnum_to_fpu_offset(int regnum)
1499 {
1500 return regnum - 32; // The FP registers are in the second chunk
1501 }
1502
1503 // This is UltraSparc specific, true just means we have fast l2f conversion
1504 const bool Matcher::convL2FSupported(void) {
1505 return true;
1506 }
1507
1508 // Is this branch offset short enough that a short branch can be used?
1509 //
1510 // NOTE: If the platform does not provide any short branch variants, then
1511 // this method should return false for offset 0.
1512 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1513 // The passed offset is relative to address of the branch.
1514 // On 86 a branch displacement is calculated relative to address
1515 // of a next instruction.
1516 offset -= br_size;
1517
1518 // the short version of jmpConUCF2 contains multiple branches,
1519 // making the reach slightly less
1520 if (rule == jmpConUCF2_rule)
1521 return (-126 <= offset && offset <= 125);
1522 return (-128 <= offset && offset <= 127);
1523 }
1524
1525 const bool Matcher::isSimpleConstant64(jlong value) {
1526 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1527 //return value == (int) value; // Cf. storeImmL and immL32.
1528
1529 // Probably always true, even if a temp register is required.
1530 return true;
1531 }
1532
1533 // The ecx parameter to rep stosq for the ClearArray node is in words.
1534 const bool Matcher::init_array_count_is_in_bytes = false;
1535
1536 // Threshold size for cleararray.
1537 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1538
1539 // No additional cost for CMOVL.
1540 const int Matcher::long_cmove_cost() { return 0; }
1541
1542 // No CMOVF/CMOVD with SSE2
1543 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1544
1545 // Should the Matcher clone shifts on addressing modes, expecting them
1546 // to be subsumed into complex addressing expressions or compute them
1547 // into registers? True for Intel but false for most RISCs
1548 const bool Matcher::clone_shift_expressions = true;
1549
1550 // Do we need to mask the count passed to shift instructions or does
1551 // the cpu only look at the lower 5/6 bits anyway?
1552 const bool Matcher::need_masked_shift_count = false;
1553
1554 bool Matcher::narrow_oop_use_complex_address() {
1555 assert(UseCompressedOops, "only for compressed oops code");
1556 return (LogMinObjAlignmentInBytes <= 3);
1557 }
1558
1559 bool Matcher::narrow_klass_use_complex_address() {
1560 assert(UseCompressedClassPointers, "only for compressed klass code");
1561 return (LogKlassAlignmentInBytes <= 3);
1562 }
1563
1564 // Is it better to copy float constants, or load them directly from
1565 // memory? Intel can load a float constant from a direct address,
1566 // requiring no extra registers. Most RISCs will have to materialize
1567 // an address into a register first, so they would do better to copy
1568 // the constant from stack.
1569 const bool Matcher::rematerialize_float_constants = true; // XXX
1570
1571 // If CPU can load and store mis-aligned doubles directly then no
1572 // fixup is needed. Else we split the double into 2 integer pieces
1573 // and move it piece-by-piece. Only happens when passing doubles into
1574 // C code as the Java calling convention forces doubles to be aligned.
1575 const bool Matcher::misaligned_doubles_ok = true;
1576
1577 // No-op on amd64
1578 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1579
1580 // Advertise here if the CPU requires explicit rounding operations to
1581 // implement the UseStrictFP mode.
1582 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1583
1584 // Are floats conerted to double when stored to stack during deoptimization?
1585 // On x64 it is stored without convertion so we can use normal access.
1586 bool Matcher::float_in_double() { return false; }
1587
1588 // Do ints take an entire long register or just half?
1589 const bool Matcher::int_in_long = true;
1590
1591 // Return whether or not this register is ever used as an argument.
1592 // This function is used on startup to build the trampoline stubs in
1593 // generateOptoStub. Registers not mentioned will be killed by the VM
1594 // call in the trampoline, and arguments in those registers not be
1595 // available to the callee.
1596 bool Matcher::can_be_java_arg(int reg)
1597 {
1598 return
1599 reg == RDI_num || reg == RDI_H_num ||
1600 reg == RSI_num || reg == RSI_H_num ||
1601 reg == RDX_num || reg == RDX_H_num ||
1602 reg == RCX_num || reg == RCX_H_num ||
1603 reg == R8_num || reg == R8_H_num ||
1604 reg == R9_num || reg == R9_H_num ||
1605 reg == R12_num || reg == R12_H_num ||
1606 reg == XMM0_num || reg == XMM0b_num ||
1607 reg == XMM1_num || reg == XMM1b_num ||
1608 reg == XMM2_num || reg == XMM2b_num ||
1609 reg == XMM3_num || reg == XMM3b_num ||
1610 reg == XMM4_num || reg == XMM4b_num ||
1611 reg == XMM5_num || reg == XMM5b_num ||
1612 reg == XMM6_num || reg == XMM6b_num ||
1613 reg == XMM7_num || reg == XMM7b_num;
1614 }
1615
1616 bool Matcher::is_spillable_arg(int reg)
1617 {
1618 return can_be_java_arg(reg);
1619 }
1620
1621 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1622 // In 64 bit mode a code which use multiply when
1623 // devisor is constant is faster than hardware
1624 // DIV instruction (it uses MulHiL).
1625 return false;
1626 }
1627
1628 // Register for DIVI projection of divmodI
1629 RegMask Matcher::divI_proj_mask() {
1630 return INT_RAX_REG_mask();
1631 }
1632
1633 // Register for MODI projection of divmodI
1634 RegMask Matcher::modI_proj_mask() {
1635 return INT_RDX_REG_mask();
1636 }
1637
1638 // Register for DIVL projection of divmodL
1639 RegMask Matcher::divL_proj_mask() {
1640 return LONG_RAX_REG_mask();
1641 }
1642
1643 // Register for MODL projection of divmodL
1644 RegMask Matcher::modL_proj_mask() {
1645 return LONG_RDX_REG_mask();
1646 }
1647
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask();
1650 }
1651
1652 const RegMask Matcher::mathExactI_result_proj_mask() {
1653 return INT_RAX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::mathExactL_result_proj_mask() {
1657 return LONG_RAX_REG_mask();
1658 }
1659
1660 const RegMask Matcher::mathExactI_flags_proj_mask() {
1661 return INT_FLAGS_mask();
1662 }
1663
1664 %}
1665
1666 //----------ENCODING BLOCK-----------------------------------------------------
1667 // This block specifies the encoding classes used by the compiler to
1668 // output byte streams. Encoding classes are parameterized macros
1669 // used by Machine Instruction Nodes in order to generate the bit
1670 // encoding of the instruction. Operands specify their base encoding
1671 // interface with the interface keyword. There are currently
1672 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1673 // COND_INTER. REG_INTER causes an operand to generate a function
1674 // which returns its register number when queried. CONST_INTER causes
1675 // an operand to generate a function which returns the value of the
1676 // constant when queried. MEMORY_INTER causes an operand to generate
1677 // four functions which return the Base Register, the Index Register,
1678 // the Scale Value, and the Offset Value of the operand when queried.
1679 // COND_INTER causes an operand to generate six functions which return
1680 // the encoding code (ie - encoding bits for the instruction)
1681 // associated with each basic boolean condition for a conditional
1682 // instruction.
1683 //
1684 // Instructions specify two basic values for encoding. Again, a
1685 // function is available to check if the constant displacement is an
1686 // oop. They use the ins_encode keyword to specify their encoding
1687 // classes (which must be a sequence of enc_class names, and their
1688 // parameters, specified in the encoding block), and they use the
1689 // opcode keyword to specify, in order, their primary, secondary, and
1690 // tertiary opcode. Only the opcode sections which a particular
1691 // instruction needs for encoding need to be specified.
1692 encode %{
1693 // Build emit functions for each basic byte or larger field in the
1694 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1695 // from C++ code in the enc_class source block. Emit functions will
1696 // live in the main source block for now. In future, we can
1697 // generalize this by adding a syntax that specifies the sizes of
1698 // fields in an order, so that the adlc can build the emit functions
1699 // automagically
1700
1701 // Emit primary opcode
1702 enc_class OpcP
1703 %{
1704 emit_opcode(cbuf, $primary);
1705 %}
1706
1707 // Emit secondary opcode
1708 enc_class OpcS
1709 %{
1710 emit_opcode(cbuf, $secondary);
1711 %}
1712
1713 // Emit tertiary opcode
1714 enc_class OpcT
1715 %{
1716 emit_opcode(cbuf, $tertiary);
1717 %}
1718
1719 // Emit opcode directly
1720 enc_class Opcode(immI d8)
1721 %{
1722 emit_opcode(cbuf, $d8$$constant);
1723 %}
1724
1725 // Emit size prefix
1726 enc_class SizePrefix
1727 %{
1728 emit_opcode(cbuf, 0x66);
1729 %}
1730
1731 enc_class reg(rRegI reg)
1732 %{
1733 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1734 %}
1735
1736 enc_class reg_reg(rRegI dst, rRegI src)
1737 %{
1738 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1739 %}
1740
1741 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1742 %{
1743 emit_opcode(cbuf, $opcode$$constant);
1744 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1745 %}
1746
1747 enc_class cdql_enc(no_rax_rdx_RegI div)
1748 %{
1749 // Full implementation of Java idiv and irem; checks for
1750 // special case as described in JVM spec., p.243 & p.271.
1751 //
1752 // normal case special case
1753 //
1754 // input : rax: dividend min_int
1755 // reg: divisor -1
1756 //
1757 // output: rax: quotient (= rax idiv reg) min_int
1758 // rdx: remainder (= rax irem reg) 0
1759 //
1760 // Code sequnce:
1761 //
1762 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1763 // 5: 75 07/08 jne e <normal>
1764 // 7: 33 d2 xor %edx,%edx
1765 // [div >= 8 -> offset + 1]
1766 // [REX_B]
1767 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1768 // c: 74 03/04 je 11 <done>
1769 // 000000000000000e <normal>:
1770 // e: 99 cltd
1771 // [div >= 8 -> offset + 1]
1772 // [REX_B]
1773 // f: f7 f9 idiv $div
1774 // 0000000000000011 <done>:
1775
1776 // cmp $0x80000000,%eax
1777 emit_opcode(cbuf, 0x3d);
1778 emit_d8(cbuf, 0x00);
1779 emit_d8(cbuf, 0x00);
1780 emit_d8(cbuf, 0x00);
1781 emit_d8(cbuf, 0x80);
1782
1783 // jne e <normal>
1784 emit_opcode(cbuf, 0x75);
1785 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1786
1787 // xor %edx,%edx
1788 emit_opcode(cbuf, 0x33);
1789 emit_d8(cbuf, 0xD2);
1790
1791 // cmp $0xffffffffffffffff,%ecx
1792 if ($div$$reg >= 8) {
1793 emit_opcode(cbuf, Assembler::REX_B);
1794 }
1795 emit_opcode(cbuf, 0x83);
1796 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1797 emit_d8(cbuf, 0xFF);
1798
1799 // je 11 <done>
1800 emit_opcode(cbuf, 0x74);
1801 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1802
1803 // <normal>
1804 // cltd
1805 emit_opcode(cbuf, 0x99);
1806
1807 // idivl (note: must be emitted by the user of this rule)
1808 // <done>
1809 %}
1810
1811 enc_class cdqq_enc(no_rax_rdx_RegL div)
1812 %{
1813 // Full implementation of Java ldiv and lrem; checks for
1814 // special case as described in JVM spec., p.243 & p.271.
1815 //
1816 // normal case special case
1817 //
1818 // input : rax: dividend min_long
1819 // reg: divisor -1
1820 //
1821 // output: rax: quotient (= rax idiv reg) min_long
1822 // rdx: remainder (= rax irem reg) 0
1823 //
1824 // Code sequnce:
1825 //
1826 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1827 // 7: 00 00 80
1828 // a: 48 39 d0 cmp %rdx,%rax
1829 // d: 75 08 jne 17 <normal>
1830 // f: 33 d2 xor %edx,%edx
1831 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1832 // 15: 74 05 je 1c <done>
1833 // 0000000000000017 <normal>:
1834 // 17: 48 99 cqto
1835 // 19: 48 f7 f9 idiv $div
1836 // 000000000000001c <done>:
1837
1838 // mov $0x8000000000000000,%rdx
1839 emit_opcode(cbuf, Assembler::REX_W);
1840 emit_opcode(cbuf, 0xBA);
1841 emit_d8(cbuf, 0x00);
1842 emit_d8(cbuf, 0x00);
1843 emit_d8(cbuf, 0x00);
1844 emit_d8(cbuf, 0x00);
1845 emit_d8(cbuf, 0x00);
1846 emit_d8(cbuf, 0x00);
1847 emit_d8(cbuf, 0x00);
1848 emit_d8(cbuf, 0x80);
1849
1850 // cmp %rdx,%rax
1851 emit_opcode(cbuf, Assembler::REX_W);
1852 emit_opcode(cbuf, 0x39);
1853 emit_d8(cbuf, 0xD0);
1854
1855 // jne 17 <normal>
1856 emit_opcode(cbuf, 0x75);
1857 emit_d8(cbuf, 0x08);
1858
1859 // xor %edx,%edx
1860 emit_opcode(cbuf, 0x33);
1861 emit_d8(cbuf, 0xD2);
1862
1863 // cmp $0xffffffffffffffff,$div
1864 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1865 emit_opcode(cbuf, 0x83);
1866 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1867 emit_d8(cbuf, 0xFF);
1868
1869 // je 1e <done>
1870 emit_opcode(cbuf, 0x74);
1871 emit_d8(cbuf, 0x05);
1872
1873 // <normal>
1874 // cqto
1875 emit_opcode(cbuf, Assembler::REX_W);
1876 emit_opcode(cbuf, 0x99);
1877
1878 // idivq (note: must be emitted by the user of this rule)
1879 // <done>
1880 %}
1881
1882 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1883 enc_class OpcSE(immI imm)
1884 %{
1885 // Emit primary opcode and set sign-extend bit
1886 // Check for 8-bit immediate, and set sign extend bit in opcode
1887 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1888 emit_opcode(cbuf, $primary | 0x02);
1889 } else {
1890 // 32-bit immediate
1891 emit_opcode(cbuf, $primary);
1892 }
1893 %}
1894
1895 enc_class OpcSErm(rRegI dst, immI imm)
1896 %{
1897 // OpcSEr/m
1898 int dstenc = $dst$$reg;
1899 if (dstenc >= 8) {
1900 emit_opcode(cbuf, Assembler::REX_B);
1901 dstenc -= 8;
1902 }
1903 // Emit primary opcode and set sign-extend bit
1904 // Check for 8-bit immediate, and set sign extend bit in opcode
1905 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1906 emit_opcode(cbuf, $primary | 0x02);
1907 } else {
1908 // 32-bit immediate
1909 emit_opcode(cbuf, $primary);
1910 }
1911 // Emit r/m byte with secondary opcode, after primary opcode.
1912 emit_rm(cbuf, 0x3, $secondary, dstenc);
1913 %}
1914
1915 enc_class OpcSErm_wide(rRegL dst, immI imm)
1916 %{
1917 // OpcSEr/m
1918 int dstenc = $dst$$reg;
1919 if (dstenc < 8) {
1920 emit_opcode(cbuf, Assembler::REX_W);
1921 } else {
1922 emit_opcode(cbuf, Assembler::REX_WB);
1923 dstenc -= 8;
1924 }
1925 // Emit primary opcode and set sign-extend bit
1926 // Check for 8-bit immediate, and set sign extend bit in opcode
1927 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1928 emit_opcode(cbuf, $primary | 0x02);
1929 } else {
1930 // 32-bit immediate
1931 emit_opcode(cbuf, $primary);
1932 }
1933 // Emit r/m byte with secondary opcode, after primary opcode.
1934 emit_rm(cbuf, 0x3, $secondary, dstenc);
1935 %}
1936
1937 enc_class Con8or32(immI imm)
1938 %{
1939 // Check for 8-bit immediate, and set sign extend bit in opcode
1940 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1941 $$$emit8$imm$$constant;
1942 } else {
1943 // 32-bit immediate
1944 $$$emit32$imm$$constant;
1945 }
1946 %}
1947
1948 enc_class opc2_reg(rRegI dst)
1949 %{
1950 // BSWAP
1951 emit_cc(cbuf, $secondary, $dst$$reg);
1952 %}
1953
1954 enc_class opc3_reg(rRegI dst)
1955 %{
1956 // BSWAP
1957 emit_cc(cbuf, $tertiary, $dst$$reg);
1958 %}
1959
1960 enc_class reg_opc(rRegI div)
1961 %{
1962 // INC, DEC, IDIV, IMOD, JMP indirect, ...
1963 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
1964 %}
1965
1966 enc_class enc_cmov(cmpOp cop)
1967 %{
1968 // CMOV
1969 $$$emit8$primary;
1970 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1971 %}
1972
1973 enc_class enc_PartialSubtypeCheck()
1974 %{
1975 Register Rrdi = as_Register(RDI_enc); // result register
1976 Register Rrax = as_Register(RAX_enc); // super class
1977 Register Rrcx = as_Register(RCX_enc); // killed
1978 Register Rrsi = as_Register(RSI_enc); // sub class
1979 Label miss;
1980 const bool set_cond_codes = true;
1981
1982 MacroAssembler _masm(&cbuf);
1983 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
1984 NULL, &miss,
1985 /*set_cond_codes:*/ true);
1986 if ($primary) {
1987 __ xorptr(Rrdi, Rrdi);
1988 }
1989 __ bind(miss);
1990 %}
1991
1992 enc_class clear_avx %{
1993 debug_only(int off0 = cbuf.insts_size());
1994 if (ra_->C->max_vector_size() > 16) {
1995 // Clear upper bits of YMM registers when current compiled code uses
1996 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1997 MacroAssembler _masm(&cbuf);
1998 __ vzeroupper();
1999 }
2000 debug_only(int off1 = cbuf.insts_size());
2001 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2002 %}
2003
2004 enc_class Java_To_Runtime(method meth) %{
2005 // No relocation needed
2006 MacroAssembler _masm(&cbuf);
2007 __ mov64(r10, (int64_t) $meth$$method);
2008 __ call(r10);
2009 %}
2010
2011 enc_class Java_To_Interpreter(method meth)
2012 %{
2013 // CALL Java_To_Interpreter
2014 // This is the instruction starting address for relocation info.
2015 cbuf.set_insts_mark();
2016 $$$emit8$primary;
2017 // CALL directly to the runtime
2018 emit_d32_reloc(cbuf,
2019 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2020 runtime_call_Relocation::spec(),
2021 RELOC_DISP32);
2022 %}
2023
2024 enc_class Java_Static_Call(method meth)
2025 %{
2026 // JAVA STATIC CALL
2027 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2028 // determine who we intended to call.
2029 cbuf.set_insts_mark();
2030 $$$emit8$primary;
2031
2032 if (!_method) {
2033 emit_d32_reloc(cbuf,
2034 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2035 runtime_call_Relocation::spec(),
2036 RELOC_DISP32);
2037 } else if (_optimized_virtual) {
2038 emit_d32_reloc(cbuf,
2039 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2040 opt_virtual_call_Relocation::spec(),
2041 RELOC_DISP32);
2042 } else {
2043 emit_d32_reloc(cbuf,
2044 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2045 static_call_Relocation::spec(),
2046 RELOC_DISP32);
2047 }
2048 if (_method) {
2049 // Emit stub for static call.
2050 CompiledStaticCall::emit_to_interp_stub(cbuf);
2051 }
2052 %}
2053
2054 enc_class Java_Dynamic_Call(method meth) %{
2055 MacroAssembler _masm(&cbuf);
2056 __ ic_call((address)$meth$$method);
2057 %}
2058
2059 enc_class Java_Compiled_Call(method meth)
2060 %{
2061 // JAVA COMPILED CALL
2062 int disp = in_bytes(Method:: from_compiled_offset());
2063
2064 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2065 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2066
2067 // callq *disp(%rax)
2068 cbuf.set_insts_mark();
2069 $$$emit8$primary;
2070 if (disp < 0x80) {
2071 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2072 emit_d8(cbuf, disp); // Displacement
2073 } else {
2074 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2075 emit_d32(cbuf, disp); // Displacement
2076 }
2077 %}
2078
2079 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2080 %{
2081 // SAL, SAR, SHR
2082 int dstenc = $dst$$reg;
2083 if (dstenc >= 8) {
2084 emit_opcode(cbuf, Assembler::REX_B);
2085 dstenc -= 8;
2086 }
2087 $$$emit8$primary;
2088 emit_rm(cbuf, 0x3, $secondary, dstenc);
2089 $$$emit8$shift$$constant;
2090 %}
2091
2092 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2093 %{
2094 // SAL, SAR, SHR
2095 int dstenc = $dst$$reg;
2096 if (dstenc < 8) {
2097 emit_opcode(cbuf, Assembler::REX_W);
2098 } else {
2099 emit_opcode(cbuf, Assembler::REX_WB);
2100 dstenc -= 8;
2101 }
2102 $$$emit8$primary;
2103 emit_rm(cbuf, 0x3, $secondary, dstenc);
2104 $$$emit8$shift$$constant;
2105 %}
2106
2107 enc_class load_immI(rRegI dst, immI src)
2108 %{
2109 int dstenc = $dst$$reg;
2110 if (dstenc >= 8) {
2111 emit_opcode(cbuf, Assembler::REX_B);
2112 dstenc -= 8;
2113 }
2114 emit_opcode(cbuf, 0xB8 | dstenc);
2115 $$$emit32$src$$constant;
2116 %}
2117
2118 enc_class load_immL(rRegL dst, immL src)
2119 %{
2120 int dstenc = $dst$$reg;
2121 if (dstenc < 8) {
2122 emit_opcode(cbuf, Assembler::REX_W);
2123 } else {
2124 emit_opcode(cbuf, Assembler::REX_WB);
2125 dstenc -= 8;
2126 }
2127 emit_opcode(cbuf, 0xB8 | dstenc);
2128 emit_d64(cbuf, $src$$constant);
2129 %}
2130
2131 enc_class load_immUL32(rRegL dst, immUL32 src)
2132 %{
2133 // same as load_immI, but this time we care about zeroes in the high word
2134 int dstenc = $dst$$reg;
2135 if (dstenc >= 8) {
2136 emit_opcode(cbuf, Assembler::REX_B);
2137 dstenc -= 8;
2138 }
2139 emit_opcode(cbuf, 0xB8 | dstenc);
2140 $$$emit32$src$$constant;
2141 %}
2142
2143 enc_class load_immL32(rRegL dst, immL32 src)
2144 %{
2145 int dstenc = $dst$$reg;
2146 if (dstenc < 8) {
2147 emit_opcode(cbuf, Assembler::REX_W);
2148 } else {
2149 emit_opcode(cbuf, Assembler::REX_WB);
2150 dstenc -= 8;
2151 }
2152 emit_opcode(cbuf, 0xC7);
2153 emit_rm(cbuf, 0x03, 0x00, dstenc);
2154 $$$emit32$src$$constant;
2155 %}
2156
2157 enc_class load_immP31(rRegP dst, immP32 src)
2158 %{
2159 // same as load_immI, but this time we care about zeroes in the high word
2160 int dstenc = $dst$$reg;
2161 if (dstenc >= 8) {
2162 emit_opcode(cbuf, Assembler::REX_B);
2163 dstenc -= 8;
2164 }
2165 emit_opcode(cbuf, 0xB8 | dstenc);
2166 $$$emit32$src$$constant;
2167 %}
2168
2169 enc_class load_immP(rRegP dst, immP src)
2170 %{
2171 int dstenc = $dst$$reg;
2172 if (dstenc < 8) {
2173 emit_opcode(cbuf, Assembler::REX_W);
2174 } else {
2175 emit_opcode(cbuf, Assembler::REX_WB);
2176 dstenc -= 8;
2177 }
2178 emit_opcode(cbuf, 0xB8 | dstenc);
2179 // This next line should be generated from ADLC
2180 if ($src->constant_reloc() != relocInfo::none) {
2181 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2182 } else {
2183 emit_d64(cbuf, $src$$constant);
2184 }
2185 %}
2186
2187 enc_class Con32(immI src)
2188 %{
2189 // Output immediate
2190 $$$emit32$src$$constant;
2191 %}
2192
2193 enc_class Con32F_as_bits(immF src)
2194 %{
2195 // Output Float immediate bits
2196 jfloat jf = $src$$constant;
2197 jint jf_as_bits = jint_cast(jf);
2198 emit_d32(cbuf, jf_as_bits);
2199 %}
2200
2201 enc_class Con16(immI src)
2202 %{
2203 // Output immediate
2204 $$$emit16$src$$constant;
2205 %}
2206
2207 // How is this different from Con32??? XXX
2208 enc_class Con_d32(immI src)
2209 %{
2210 emit_d32(cbuf,$src$$constant);
2211 %}
2212
2213 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2214 // Output immediate memory reference
2215 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2216 emit_d32(cbuf, 0x00);
2217 %}
2218
2219 enc_class lock_prefix()
2220 %{
2221 if (os::is_MP()) {
2222 emit_opcode(cbuf, 0xF0); // lock
2223 }
2224 %}
2225
2226 enc_class REX_mem(memory mem)
2227 %{
2228 if ($mem$$base >= 8) {
2229 if ($mem$$index < 8) {
2230 emit_opcode(cbuf, Assembler::REX_B);
2231 } else {
2232 emit_opcode(cbuf, Assembler::REX_XB);
2233 }
2234 } else {
2235 if ($mem$$index >= 8) {
2236 emit_opcode(cbuf, Assembler::REX_X);
2237 }
2238 }
2239 %}
2240
2241 enc_class REX_mem_wide(memory mem)
2242 %{
2243 if ($mem$$base >= 8) {
2244 if ($mem$$index < 8) {
2245 emit_opcode(cbuf, Assembler::REX_WB);
2246 } else {
2247 emit_opcode(cbuf, Assembler::REX_WXB);
2248 }
2249 } else {
2250 if ($mem$$index < 8) {
2251 emit_opcode(cbuf, Assembler::REX_W);
2252 } else {
2253 emit_opcode(cbuf, Assembler::REX_WX);
2254 }
2255 }
2256 %}
2257
2258 // for byte regs
2259 enc_class REX_breg(rRegI reg)
2260 %{
2261 if ($reg$$reg >= 4) {
2262 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2263 }
2264 %}
2265
2266 // for byte regs
2267 enc_class REX_reg_breg(rRegI dst, rRegI src)
2268 %{
2269 if ($dst$$reg < 8) {
2270 if ($src$$reg >= 4) {
2271 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2272 }
2273 } else {
2274 if ($src$$reg < 8) {
2275 emit_opcode(cbuf, Assembler::REX_R);
2276 } else {
2277 emit_opcode(cbuf, Assembler::REX_RB);
2278 }
2279 }
2280 %}
2281
2282 // for byte regs
2283 enc_class REX_breg_mem(rRegI reg, memory mem)
2284 %{
2285 if ($reg$$reg < 8) {
2286 if ($mem$$base < 8) {
2287 if ($mem$$index >= 8) {
2288 emit_opcode(cbuf, Assembler::REX_X);
2289 } else if ($reg$$reg >= 4) {
2290 emit_opcode(cbuf, Assembler::REX);
2291 }
2292 } else {
2293 if ($mem$$index < 8) {
2294 emit_opcode(cbuf, Assembler::REX_B);
2295 } else {
2296 emit_opcode(cbuf, Assembler::REX_XB);
2297 }
2298 }
2299 } else {
2300 if ($mem$$base < 8) {
2301 if ($mem$$index < 8) {
2302 emit_opcode(cbuf, Assembler::REX_R);
2303 } else {
2304 emit_opcode(cbuf, Assembler::REX_RX);
2305 }
2306 } else {
2307 if ($mem$$index < 8) {
2308 emit_opcode(cbuf, Assembler::REX_RB);
2309 } else {
2310 emit_opcode(cbuf, Assembler::REX_RXB);
2311 }
2312 }
2313 }
2314 %}
2315
2316 enc_class REX_reg(rRegI reg)
2317 %{
2318 if ($reg$$reg >= 8) {
2319 emit_opcode(cbuf, Assembler::REX_B);
2320 }
2321 %}
2322
2323 enc_class REX_reg_wide(rRegI reg)
2324 %{
2325 if ($reg$$reg < 8) {
2326 emit_opcode(cbuf, Assembler::REX_W);
2327 } else {
2328 emit_opcode(cbuf, Assembler::REX_WB);
2329 }
2330 %}
2331
2332 enc_class REX_reg_reg(rRegI dst, rRegI src)
2333 %{
2334 if ($dst$$reg < 8) {
2335 if ($src$$reg >= 8) {
2336 emit_opcode(cbuf, Assembler::REX_B);
2337 }
2338 } else {
2339 if ($src$$reg < 8) {
2340 emit_opcode(cbuf, Assembler::REX_R);
2341 } else {
2342 emit_opcode(cbuf, Assembler::REX_RB);
2343 }
2344 }
2345 %}
2346
2347 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2348 %{
2349 if ($dst$$reg < 8) {
2350 if ($src$$reg < 8) {
2351 emit_opcode(cbuf, Assembler::REX_W);
2352 } else {
2353 emit_opcode(cbuf, Assembler::REX_WB);
2354 }
2355 } else {
2356 if ($src$$reg < 8) {
2357 emit_opcode(cbuf, Assembler::REX_WR);
2358 } else {
2359 emit_opcode(cbuf, Assembler::REX_WRB);
2360 }
2361 }
2362 %}
2363
2364 enc_class REX_reg_mem(rRegI reg, memory mem)
2365 %{
2366 if ($reg$$reg < 8) {
2367 if ($mem$$base < 8) {
2368 if ($mem$$index >= 8) {
2369 emit_opcode(cbuf, Assembler::REX_X);
2370 }
2371 } else {
2372 if ($mem$$index < 8) {
2373 emit_opcode(cbuf, Assembler::REX_B);
2374 } else {
2375 emit_opcode(cbuf, Assembler::REX_XB);
2376 }
2377 }
2378 } else {
2379 if ($mem$$base < 8) {
2380 if ($mem$$index < 8) {
2381 emit_opcode(cbuf, Assembler::REX_R);
2382 } else {
2383 emit_opcode(cbuf, Assembler::REX_RX);
2384 }
2385 } else {
2386 if ($mem$$index < 8) {
2387 emit_opcode(cbuf, Assembler::REX_RB);
2388 } else {
2389 emit_opcode(cbuf, Assembler::REX_RXB);
2390 }
2391 }
2392 }
2393 %}
2394
2395 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2396 %{
2397 if ($reg$$reg < 8) {
2398 if ($mem$$base < 8) {
2399 if ($mem$$index < 8) {
2400 emit_opcode(cbuf, Assembler::REX_W);
2401 } else {
2402 emit_opcode(cbuf, Assembler::REX_WX);
2403 }
2404 } else {
2405 if ($mem$$index < 8) {
2406 emit_opcode(cbuf, Assembler::REX_WB);
2407 } else {
2408 emit_opcode(cbuf, Assembler::REX_WXB);
2409 }
2410 }
2411 } else {
2412 if ($mem$$base < 8) {
2413 if ($mem$$index < 8) {
2414 emit_opcode(cbuf, Assembler::REX_WR);
2415 } else {
2416 emit_opcode(cbuf, Assembler::REX_WRX);
2417 }
2418 } else {
2419 if ($mem$$index < 8) {
2420 emit_opcode(cbuf, Assembler::REX_WRB);
2421 } else {
2422 emit_opcode(cbuf, Assembler::REX_WRXB);
2423 }
2424 }
2425 }
2426 %}
2427
2428 enc_class reg_mem(rRegI ereg, memory mem)
2429 %{
2430 // High registers handle in encode_RegMem
2431 int reg = $ereg$$reg;
2432 int base = $mem$$base;
2433 int index = $mem$$index;
2434 int scale = $mem$$scale;
2435 int disp = $mem$$disp;
2436 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2437
2438 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2439 %}
2440
2441 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2442 %{
2443 int rm_byte_opcode = $rm_opcode$$constant;
2444
2445 // High registers handle in encode_RegMem
2446 int base = $mem$$base;
2447 int index = $mem$$index;
2448 int scale = $mem$$scale;
2449 int displace = $mem$$disp;
2450
2451 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2452 // working with static
2453 // globals
2454 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2455 disp_reloc);
2456 %}
2457
2458 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2459 %{
2460 int reg_encoding = $dst$$reg;
2461 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2462 int index = 0x04; // 0x04 indicates no index
2463 int scale = 0x00; // 0x00 indicates no scale
2464 int displace = $src1$$constant; // 0x00 indicates no displacement
2465 relocInfo::relocType disp_reloc = relocInfo::none;
2466 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2467 disp_reloc);
2468 %}
2469
2470 enc_class neg_reg(rRegI dst)
2471 %{
2472 int dstenc = $dst$$reg;
2473 if (dstenc >= 8) {
2474 emit_opcode(cbuf, Assembler::REX_B);
2475 dstenc -= 8;
2476 }
2477 // NEG $dst
2478 emit_opcode(cbuf, 0xF7);
2479 emit_rm(cbuf, 0x3, 0x03, dstenc);
2480 %}
2481
2482 enc_class neg_reg_wide(rRegI dst)
2483 %{
2484 int dstenc = $dst$$reg;
2485 if (dstenc < 8) {
2486 emit_opcode(cbuf, Assembler::REX_W);
2487 } else {
2488 emit_opcode(cbuf, Assembler::REX_WB);
2489 dstenc -= 8;
2490 }
2491 // NEG $dst
2492 emit_opcode(cbuf, 0xF7);
2493 emit_rm(cbuf, 0x3, 0x03, dstenc);
2494 %}
2495
2496 enc_class setLT_reg(rRegI dst)
2497 %{
2498 int dstenc = $dst$$reg;
2499 if (dstenc >= 8) {
2500 emit_opcode(cbuf, Assembler::REX_B);
2501 dstenc -= 8;
2502 } else if (dstenc >= 4) {
2503 emit_opcode(cbuf, Assembler::REX);
2504 }
2505 // SETLT $dst
2506 emit_opcode(cbuf, 0x0F);
2507 emit_opcode(cbuf, 0x9C);
2508 emit_rm(cbuf, 0x3, 0x0, dstenc);
2509 %}
2510
2511 enc_class setNZ_reg(rRegI dst)
2512 %{
2513 int dstenc = $dst$$reg;
2514 if (dstenc >= 8) {
2515 emit_opcode(cbuf, Assembler::REX_B);
2516 dstenc -= 8;
2517 } else if (dstenc >= 4) {
2518 emit_opcode(cbuf, Assembler::REX);
2519 }
2520 // SETNZ $dst
2521 emit_opcode(cbuf, 0x0F);
2522 emit_opcode(cbuf, 0x95);
2523 emit_rm(cbuf, 0x3, 0x0, dstenc);
2524 %}
2525
2526
2527 // Compare the lonogs and set -1, 0, or 1 into dst
2528 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2529 %{
2530 int src1enc = $src1$$reg;
2531 int src2enc = $src2$$reg;
2532 int dstenc = $dst$$reg;
2533
2534 // cmpq $src1, $src2
2535 if (src1enc < 8) {
2536 if (src2enc < 8) {
2537 emit_opcode(cbuf, Assembler::REX_W);
2538 } else {
2539 emit_opcode(cbuf, Assembler::REX_WB);
2540 }
2541 } else {
2542 if (src2enc < 8) {
2543 emit_opcode(cbuf, Assembler::REX_WR);
2544 } else {
2545 emit_opcode(cbuf, Assembler::REX_WRB);
2546 }
2547 }
2548 emit_opcode(cbuf, 0x3B);
2549 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2550
2551 // movl $dst, -1
2552 if (dstenc >= 8) {
2553 emit_opcode(cbuf, Assembler::REX_B);
2554 }
2555 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2556 emit_d32(cbuf, -1);
2557
2558 // jl,s done
2559 emit_opcode(cbuf, 0x7C);
2560 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2561
2562 // setne $dst
2563 if (dstenc >= 4) {
2564 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2565 }
2566 emit_opcode(cbuf, 0x0F);
2567 emit_opcode(cbuf, 0x95);
2568 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2569
2570 // movzbl $dst, $dst
2571 if (dstenc >= 4) {
2572 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2573 }
2574 emit_opcode(cbuf, 0x0F);
2575 emit_opcode(cbuf, 0xB6);
2576 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2577 %}
2578
2579 enc_class Push_ResultXD(regD dst) %{
2580 MacroAssembler _masm(&cbuf);
2581 __ fstp_d(Address(rsp, 0));
2582 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2583 __ addptr(rsp, 8);
2584 %}
2585
2586 enc_class Push_SrcXD(regD src) %{
2587 MacroAssembler _masm(&cbuf);
2588 __ subptr(rsp, 8);
2589 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2590 __ fld_d(Address(rsp, 0));
2591 %}
2592
2593
2594 // obj: object to lock
2595 // box: box address (header location) -- killed
2596 // tmp: rax -- killed
2597 // scr: rbx -- killed
2598 //
2599 // What follows is a direct transliteration of fast_lock() and fast_unlock()
2600 // from i486.ad. See that file for comments.
2601 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
2602 // use the shorter encoding. (Movl clears the high-order 32-bits).
2603
2604
2605 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
2606 %{
2607 Register objReg = as_Register((int)$obj$$reg);
2608 Register boxReg = as_Register((int)$box$$reg);
2609 Register tmpReg = as_Register($tmp$$reg);
2610 Register scrReg = as_Register($scr$$reg);
2611 MacroAssembler masm(&cbuf);
2612
2613 // Verify uniqueness of register assignments -- necessary but not sufficient
2614 assert (objReg != boxReg && objReg != tmpReg &&
2615 objReg != scrReg && tmpReg != scrReg, "invariant") ;
2616
2617 if (_counters != NULL) {
2618 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2619 }
2620 if (EmitSync & 1) {
2621 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2622 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2623 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
2624 } else
2625 if (EmitSync & 2) {
2626 Label DONE_LABEL;
2627 if (UseBiasedLocking) {
2628 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2629 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
2630 }
2631 // QQQ was movl...
2632 masm.movptr(tmpReg, 0x1);
2633 masm.orptr(tmpReg, Address(objReg, 0));
2634 masm.movptr(Address(boxReg, 0), tmpReg);
2635 if (os::is_MP()) {
2636 masm.lock();
2637 }
2638 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2639 masm.jcc(Assembler::equal, DONE_LABEL);
2640
2641 // Recursive locking
2642 masm.subptr(tmpReg, rsp);
2643 masm.andptr(tmpReg, 7 - os::vm_page_size());
2644 masm.movptr(Address(boxReg, 0), tmpReg);
2645
2646 masm.bind(DONE_LABEL);
2647 masm.nop(); // avoid branch to branch
2648 } else {
2649 Label DONE_LABEL, IsInflated, Egress;
2650
2651 masm.movptr(tmpReg, Address(objReg, 0)) ;
2652 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2653 masm.jcc (Assembler::notZero, IsInflated) ;
2654
2655 // it's stack-locked, biased or neutral
2656 // TODO: optimize markword triage order to reduce the number of
2657 // conditional branches in the most common cases.
2658 // Beware -- there's a subtle invariant that fetch of the markword
2659 // at [FETCH], below, will never observe a biased encoding (*101b).
2660 // If this invariant is not held we'll suffer exclusion (safety) failure.
2661
2662 if (UseBiasedLocking && !UseOptoBiasInlining) {
2663 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
2664 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
2665 }
2666
2667 // was q will it destroy high?
2668 masm.orl (tmpReg, 1) ;
2669 masm.movptr(Address(boxReg, 0), tmpReg) ;
2670 if (os::is_MP()) { masm.lock(); }
2671 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2672 if (_counters != NULL) {
2673 masm.cond_inc32(Assembler::equal,
2674 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2675 }
2676 masm.jcc (Assembler::equal, DONE_LABEL);
2677
2678 // Recursive locking
2679 masm.subptr(tmpReg, rsp);
2680 masm.andptr(tmpReg, 7 - os::vm_page_size());
2681 masm.movptr(Address(boxReg, 0), tmpReg);
2682 if (_counters != NULL) {
2683 masm.cond_inc32(Assembler::equal,
2684 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2685 }
2686 masm.jmp (DONE_LABEL) ;
2687
2688 masm.bind (IsInflated) ;
2689 // It's inflated
2690
2691 // TODO: someday avoid the ST-before-CAS penalty by
2692 // relocating (deferring) the following ST.
2693 // We should also think about trying a CAS without having
2694 // fetched _owner. If the CAS is successful we may
2695 // avoid an RTO->RTS upgrade on the $line.
2696 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2697 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2698
2699 masm.mov (boxReg, tmpReg) ;
2700 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2701 masm.testptr(tmpReg, tmpReg) ;
2702 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2703
2704 // It's inflated and appears unlocked
2705 if (os::is_MP()) { masm.lock(); }
2706 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2707 // Intentional fall-through into DONE_LABEL ...
2708
2709 masm.bind (DONE_LABEL) ;
2710 masm.nop () ; // avoid jmp to jmp
2711 }
2712 %}
2713
2714 // obj: object to unlock
2715 // box: box address (displaced header location), killed
2716 // RBX: killed tmp; cannot be obj nor box
2717 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
2718 %{
2719
2720 Register objReg = as_Register($obj$$reg);
2721 Register boxReg = as_Register($box$$reg);
2722 Register tmpReg = as_Register($tmp$$reg);
2723 MacroAssembler masm(&cbuf);
2724
2725 if (EmitSync & 4) {
2726 masm.cmpptr(rsp, 0) ;
2727 } else
2728 if (EmitSync & 8) {
2729 Label DONE_LABEL;
2730 if (UseBiasedLocking) {
2731 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2732 }
2733
2734 // Check whether the displaced header is 0
2735 //(=> recursive unlock)
2736 masm.movptr(tmpReg, Address(boxReg, 0));
2737 masm.testptr(tmpReg, tmpReg);
2738 masm.jcc(Assembler::zero, DONE_LABEL);
2739
2740 // If not recursive lock, reset the header to displaced header
2741 if (os::is_MP()) {
2742 masm.lock();
2743 }
2744 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2745 masm.bind(DONE_LABEL);
2746 masm.nop(); // avoid branch to branch
2747 } else {
2748 Label DONE_LABEL, Stacked, CheckSucc ;
2749
2750 if (UseBiasedLocking && !UseOptoBiasInlining) {
2751 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2752 }
2753
2754 masm.movptr(tmpReg, Address(objReg, 0)) ;
2755 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
2756 masm.jcc (Assembler::zero, DONE_LABEL) ;
2757 masm.testl (tmpReg, 0x02) ;
2758 masm.jcc (Assembler::zero, Stacked) ;
2759
2760 // It's inflated
2761 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2762 masm.xorptr(boxReg, r15_thread) ;
2763 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
2764 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2765 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
2766 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
2767 masm.jcc (Assembler::notZero, CheckSucc) ;
2768 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2769 masm.jmp (DONE_LABEL) ;
2770
2771 if ((EmitSync & 65536) == 0) {
2772 Label LSuccess, LGoSlowPath ;
2773 masm.bind (CheckSucc) ;
2774 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2775 masm.jcc (Assembler::zero, LGoSlowPath) ;
2776
2777 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2778 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2779 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2780 // are all faster when the write buffer is populated.
2781 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2782 if (os::is_MP()) {
2783 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
2784 }
2785 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2786 masm.jcc (Assembler::notZero, LSuccess) ;
2787
2788 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
2789 if (os::is_MP()) { masm.lock(); }
2790 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2791 masm.jcc (Assembler::notEqual, LSuccess) ;
2792 // Intentional fall-through into slow-path
2793
2794 masm.bind (LGoSlowPath) ;
2795 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
2796 masm.jmp (DONE_LABEL) ;
2797
2798 masm.bind (LSuccess) ;
2799 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
2800 masm.jmp (DONE_LABEL) ;
2801 }
2802
2803 masm.bind (Stacked) ;
2804 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2805 if (os::is_MP()) { masm.lock(); }
2806 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2807
2808 if (EmitSync & 65536) {
2809 masm.bind (CheckSucc) ;
2810 }
2811 masm.bind(DONE_LABEL);
2812 if (EmitSync & 32768) {
2813 masm.nop(); // avoid branch to branch
2814 }
2815 }
2816 %}
2817
2818
2819 enc_class enc_rethrow()
2820 %{
2821 cbuf.set_insts_mark();
2822 emit_opcode(cbuf, 0xE9); // jmp entry
2823 emit_d32_reloc(cbuf,
2824 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2825 runtime_call_Relocation::spec(),
2826 RELOC_DISP32);
2827 %}
2828
2829 %}
2830
2831
2832
2833 //----------FRAME--------------------------------------------------------------
2834 // Definition of frame structure and management information.
2835 //
2836 // S T A C K L A Y O U T Allocators stack-slot number
2837 // | (to get allocators register number
2838 // G Owned by | | v add OptoReg::stack0())
2839 // r CALLER | |
2840 // o | +--------+ pad to even-align allocators stack-slot
2841 // w V | pad0 | numbers; owned by CALLER
2842 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2843 // h ^ | in | 5
2844 // | | args | 4 Holes in incoming args owned by SELF
2845 // | | | | 3
2846 // | | +--------+
2847 // V | | old out| Empty on Intel, window on Sparc
2848 // | old |preserve| Must be even aligned.
2849 // | SP-+--------+----> Matcher::_old_SP, even aligned
2850 // | | in | 3 area for Intel ret address
2851 // Owned by |preserve| Empty on Sparc.
2852 // SELF +--------+
2853 // | | pad2 | 2 pad to align old SP
2854 // | +--------+ 1
2855 // | | locks | 0
2856 // | +--------+----> OptoReg::stack0(), even aligned
2857 // | | pad1 | 11 pad to align new SP
2858 // | +--------+
2859 // | | | 10
2860 // | | spills | 9 spills
2861 // V | | 8 (pad0 slot for callee)
2862 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2863 // ^ | out | 7
2864 // | | args | 6 Holes in outgoing args owned by CALLEE
2865 // Owned by +--------+
2866 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2867 // | new |preserve| Must be even-aligned.
2868 // | SP-+--------+----> Matcher::_new_SP, even aligned
2869 // | | |
2870 //
2871 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2872 // known from SELF's arguments and the Java calling convention.
2873 // Region 6-7 is determined per call site.
2874 // Note 2: If the calling convention leaves holes in the incoming argument
2875 // area, those holes are owned by SELF. Holes in the outgoing area
2876 // are owned by the CALLEE. Holes should not be nessecary in the
2877 // incoming area, as the Java calling convention is completely under
2878 // the control of the AD file. Doubles can be sorted and packed to
2879 // avoid holes. Holes in the outgoing arguments may be nessecary for
2880 // varargs C calling conventions.
2881 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2882 // even aligned with pad0 as needed.
2883 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2884 // region 6-11 is even aligned; it may be padded out more so that
2885 // the region from SP to FP meets the minimum stack alignment.
2886 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2887 // alignment. Region 11, pad1, may be dynamically extended so that
2888 // SP meets the minimum alignment.
2889
2890 frame
2891 %{
2892 // What direction does stack grow in (assumed to be same for C & Java)
2893 stack_direction(TOWARDS_LOW);
2894
2895 // These three registers define part of the calling convention
2896 // between compiled code and the interpreter.
2897 inline_cache_reg(RAX); // Inline Cache Register
2898 interpreter_method_oop_reg(RBX); // Method Oop Register when
2899 // calling interpreter
2900
2901 // Optional: name the operand used by cisc-spilling to access
2902 // [stack_pointer + offset]
2903 cisc_spilling_operand_name(indOffset32);
2904
2905 // Number of stack slots consumed by locking an object
2906 sync_stack_slots(2);
2907
2908 // Compiled code's Frame Pointer
2909 frame_pointer(RSP);
2910
2911 // Interpreter stores its frame pointer in a register which is
2912 // stored to the stack by I2CAdaptors.
2913 // I2CAdaptors convert from interpreted java to compiled java.
2914 interpreter_frame_pointer(RBP);
2915
2916 // Stack alignment requirement
2917 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2918
2919 // Number of stack slots between incoming argument block and the start of
2920 // a new frame. The PROLOG must add this many slots to the stack. The
2921 // EPILOG must remove this many slots. amd64 needs two slots for
2922 // return address.
2923 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2924
2925 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2926 // for calls to C. Supports the var-args backing area for register parms.
2927 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2928
2929 // The after-PROLOG location of the return address. Location of
2930 // return address specifies a type (REG or STACK) and a number
2931 // representing the register number (i.e. - use a register name) or
2932 // stack slot.
2933 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2934 // Otherwise, it is above the locks and verification slot and alignment word
2935 return_addr(STACK - 2 +
2936 round_to((Compile::current()->in_preserve_stack_slots() +
2937 Compile::current()->fixed_slots()),
2938 stack_alignment_in_slots()));
2939
2940 // Body of function which returns an integer array locating
2941 // arguments either in registers or in stack slots. Passed an array
2942 // of ideal registers called "sig" and a "length" count. Stack-slot
2943 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2944 // arguments for a CALLEE. Incoming stack arguments are
2945 // automatically biased by the preserve_stack_slots field above.
2946
2947 calling_convention
2948 %{
2949 // No difference between ingoing/outgoing just pass false
2950 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2951 %}
2952
2953 c_calling_convention
2954 %{
2955 // This is obviously always outgoing
2956 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
2957 %}
2958
2959 // Location of compiled Java return values. Same as C for now.
2960 return_value
2961 %{
2962 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2963 "only return normal values");
2964
2965 static const int lo[Op_RegL + 1] = {
2966 0,
2967 0,
2968 RAX_num, // Op_RegN
2969 RAX_num, // Op_RegI
2970 RAX_num, // Op_RegP
2971 XMM0_num, // Op_RegF
2972 XMM0_num, // Op_RegD
2973 RAX_num // Op_RegL
2974 };
2975 static const int hi[Op_RegL + 1] = {
2976 0,
2977 0,
2978 OptoReg::Bad, // Op_RegN
2979 OptoReg::Bad, // Op_RegI
2980 RAX_H_num, // Op_RegP
2981 OptoReg::Bad, // Op_RegF
2982 XMM0b_num, // Op_RegD
2983 RAX_H_num // Op_RegL
2984 };
2985 // Excluded flags and vector registers.
2986 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
2987 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2988 %}
2989 %}
2990
2991 //----------ATTRIBUTES---------------------------------------------------------
2992 //----------Operand Attributes-------------------------------------------------
2993 op_attrib op_cost(0); // Required cost attribute
2994
2995 //----------Instruction Attributes---------------------------------------------
2996 ins_attrib ins_cost(100); // Required cost attribute
2997 ins_attrib ins_size(8); // Required size attribute (in bits)
2998 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2999 // a non-matching short branch variant
3000 // of some long branch?
3001 ins_attrib ins_alignment(1); // Required alignment attribute (must
3002 // be a power of 2) specifies the
3003 // alignment that some part of the
3004 // instruction (not necessarily the
3005 // start) requires. If > 1, a
3006 // compute_padding() function must be
3007 // provided for the instruction
3008
3009 //----------OPERANDS-----------------------------------------------------------
3010 // Operand definitions must precede instruction definitions for correct parsing
3011 // in the ADLC because operands constitute user defined types which are used in
3012 // instruction definitions.
3013
3014 //----------Simple Operands----------------------------------------------------
3015 // Immediate Operands
3016 // Integer Immediate
3017 operand immI()
3018 %{
3019 match(ConI);
3020
3021 op_cost(10);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // Constant for test vs zero
3027 operand immI0()
3028 %{
3029 predicate(n->get_int() == 0);
3030 match(ConI);
3031
3032 op_cost(0);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // Constant for increment
3038 operand immI1()
3039 %{
3040 predicate(n->get_int() == 1);
3041 match(ConI);
3042
3043 op_cost(0);
3044 format %{ %}
3045 interface(CONST_INTER);
3046 %}
3047
3048 // Constant for decrement
3049 operand immI_M1()
3050 %{
3051 predicate(n->get_int() == -1);
3052 match(ConI);
3053
3054 op_cost(0);
3055 format %{ %}
3056 interface(CONST_INTER);
3057 %}
3058
3059 // Valid scale values for addressing modes
3060 operand immI2()
3061 %{
3062 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3063 match(ConI);
3064
3065 format %{ %}
3066 interface(CONST_INTER);
3067 %}
3068
3069 operand immI8()
3070 %{
3071 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3072 match(ConI);
3073
3074 op_cost(5);
3075 format %{ %}
3076 interface(CONST_INTER);
3077 %}
3078
3079 operand immI16()
3080 %{
3081 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3082 match(ConI);
3083
3084 op_cost(10);
3085 format %{ %}
3086 interface(CONST_INTER);
3087 %}
3088
3089 // Int Immediate positive
3090 operand immU32()
3091 %{
3092 predicate(n->get_int() >= 0);
3093 match(ConI);
3094
3095 op_cost(0);
3096 format %{ %}
3097 interface(CONST_INTER);
3098 %}
3099
3100 // Constant for long shifts
3101 operand immI_32()
3102 %{
3103 predicate( n->get_int() == 32 );
3104 match(ConI);
3105
3106 op_cost(0);
3107 format %{ %}
3108 interface(CONST_INTER);
3109 %}
3110
3111 // Constant for long shifts
3112 operand immI_64()
3113 %{
3114 predicate( n->get_int() == 64 );
3115 match(ConI);
3116
3117 op_cost(0);
3118 format %{ %}
3119 interface(CONST_INTER);
3120 %}
3121
3122 // Pointer Immediate
3123 operand immP()
3124 %{
3125 match(ConP);
3126
3127 op_cost(10);
3128 format %{ %}
3129 interface(CONST_INTER);
3130 %}
3131
3132 // NULL Pointer Immediate
3133 operand immP0()
3134 %{
3135 predicate(n->get_ptr() == 0);
3136 match(ConP);
3137
3138 op_cost(5);
3139 format %{ %}
3140 interface(CONST_INTER);
3141 %}
3142
3143 // Pointer Immediate
3144 operand immN() %{
3145 match(ConN);
3146
3147 op_cost(10);
3148 format %{ %}
3149 interface(CONST_INTER);
3150 %}
3151
3152 operand immNKlass() %{
3153 match(ConNKlass);
3154
3155 op_cost(10);
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3159
3160 // NULL Pointer Immediate
3161 operand immN0() %{
3162 predicate(n->get_narrowcon() == 0);
3163 match(ConN);
3164
3165 op_cost(5);
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3169
3170 operand immP31()
3171 %{
3172 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3173 && (n->get_ptr() >> 31) == 0);
3174 match(ConP);
3175
3176 op_cost(5);
3177 format %{ %}
3178 interface(CONST_INTER);
3179 %}
3180
3181
3182 // Long Immediate
3183 operand immL()
3184 %{
3185 match(ConL);
3186
3187 op_cost(20);
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 // Long Immediate 8-bit
3193 operand immL8()
3194 %{
3195 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3196 match(ConL);
3197
3198 op_cost(5);
3199 format %{ %}
3200 interface(CONST_INTER);
3201 %}
3202
3203 // Long Immediate 32-bit unsigned
3204 operand immUL32()
3205 %{
3206 predicate(n->get_long() == (unsigned int) (n->get_long()));
3207 match(ConL);
3208
3209 op_cost(10);
3210 format %{ %}
3211 interface(CONST_INTER);
3212 %}
3213
3214 // Long Immediate 32-bit signed
3215 operand immL32()
3216 %{
3217 predicate(n->get_long() == (int) (n->get_long()));
3218 match(ConL);
3219
3220 op_cost(15);
3221 format %{ %}
3222 interface(CONST_INTER);
3223 %}
3224
3225 // Long Immediate zero
3226 operand immL0()
3227 %{
3228 predicate(n->get_long() == 0L);
3229 match(ConL);
3230
3231 op_cost(10);
3232 format %{ %}
3233 interface(CONST_INTER);
3234 %}
3235
3236 // Constant for increment
3237 operand immL1()
3238 %{
3239 predicate(n->get_long() == 1);
3240 match(ConL);
3241
3242 format %{ %}
3243 interface(CONST_INTER);
3244 %}
3245
3246 // Constant for decrement
3247 operand immL_M1()
3248 %{
3249 predicate(n->get_long() == -1);
3250 match(ConL);
3251
3252 format %{ %}
3253 interface(CONST_INTER);
3254 %}
3255
3256 // Long Immediate: the value 10
3257 operand immL10()
3258 %{
3259 predicate(n->get_long() == 10);
3260 match(ConL);
3261
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Long immediate from 0 to 127.
3267 // Used for a shorter form of long mul by 10.
3268 operand immL_127()
3269 %{
3270 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3271 match(ConL);
3272
3273 op_cost(10);
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3277
3278 // Long Immediate: low 32-bit mask
3279 operand immL_32bits()
3280 %{
3281 predicate(n->get_long() == 0xFFFFFFFFL);
3282 match(ConL);
3283 op_cost(20);
3284
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3288
3289 // Float Immediate zero
3290 operand immF0()
3291 %{
3292 predicate(jint_cast(n->getf()) == 0);
3293 match(ConF);
3294
3295 op_cost(5);
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3299
3300 // Float Immediate
3301 operand immF()
3302 %{
3303 match(ConF);
3304
3305 op_cost(15);
3306 format %{ %}
3307 interface(CONST_INTER);
3308 %}
3309
3310 // Double Immediate zero
3311 operand immD0()
3312 %{
3313 predicate(jlong_cast(n->getd()) == 0);
3314 match(ConD);
3315
3316 op_cost(5);
3317 format %{ %}
3318 interface(CONST_INTER);
3319 %}
3320
3321 // Double Immediate
3322 operand immD()
3323 %{
3324 match(ConD);
3325
3326 op_cost(15);
3327 format %{ %}
3328 interface(CONST_INTER);
3329 %}
3330
3331 // Immediates for special shifts (sign extend)
3332
3333 // Constants for increment
3334 operand immI_16()
3335 %{
3336 predicate(n->get_int() == 16);
3337 match(ConI);
3338
3339 format %{ %}
3340 interface(CONST_INTER);
3341 %}
3342
3343 operand immI_24()
3344 %{
3345 predicate(n->get_int() == 24);
3346 match(ConI);
3347
3348 format %{ %}
3349 interface(CONST_INTER);
3350 %}
3351
3352 // Constant for byte-wide masking
3353 operand immI_255()
3354 %{
3355 predicate(n->get_int() == 255);
3356 match(ConI);
3357
3358 format %{ %}
3359 interface(CONST_INTER);
3360 %}
3361
3362 // Constant for short-wide masking
3363 operand immI_65535()
3364 %{
3365 predicate(n->get_int() == 65535);
3366 match(ConI);
3367
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 // Constant for byte-wide masking
3373 operand immL_255()
3374 %{
3375 predicate(n->get_long() == 255);
3376 match(ConL);
3377
3378 format %{ %}
3379 interface(CONST_INTER);
3380 %}
3381
3382 // Constant for short-wide masking
3383 operand immL_65535()
3384 %{
3385 predicate(n->get_long() == 65535);
3386 match(ConL);
3387
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3391
3392 // Register Operands
3393 // Integer Register
3394 operand rRegI()
3395 %{
3396 constraint(ALLOC_IN_RC(int_reg));
3397 match(RegI);
3398
3399 match(rax_RegI);
3400 match(rbx_RegI);
3401 match(rcx_RegI);
3402 match(rdx_RegI);
3403 match(rdi_RegI);
3404
3405 format %{ %}
3406 interface(REG_INTER);
3407 %}
3408
3409 // Special Registers
3410 operand rax_RegI()
3411 %{
3412 constraint(ALLOC_IN_RC(int_rax_reg));
3413 match(RegI);
3414 match(rRegI);
3415
3416 format %{ "RAX" %}
3417 interface(REG_INTER);
3418 %}
3419
3420 // Special Registers
3421 operand rbx_RegI()
3422 %{
3423 constraint(ALLOC_IN_RC(int_rbx_reg));
3424 match(RegI);
3425 match(rRegI);
3426
3427 format %{ "RBX" %}
3428 interface(REG_INTER);
3429 %}
3430
3431 operand rcx_RegI()
3432 %{
3433 constraint(ALLOC_IN_RC(int_rcx_reg));
3434 match(RegI);
3435 match(rRegI);
3436
3437 format %{ "RCX" %}
3438 interface(REG_INTER);
3439 %}
3440
3441 operand rdx_RegI()
3442 %{
3443 constraint(ALLOC_IN_RC(int_rdx_reg));
3444 match(RegI);
3445 match(rRegI);
3446
3447 format %{ "RDX" %}
3448 interface(REG_INTER);
3449 %}
3450
3451 operand rdi_RegI()
3452 %{
3453 constraint(ALLOC_IN_RC(int_rdi_reg));
3454 match(RegI);
3455 match(rRegI);
3456
3457 format %{ "RDI" %}
3458 interface(REG_INTER);
3459 %}
3460
3461 operand no_rcx_RegI()
3462 %{
3463 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3464 match(RegI);
3465 match(rax_RegI);
3466 match(rbx_RegI);
3467 match(rdx_RegI);
3468 match(rdi_RegI);
3469
3470 format %{ %}
3471 interface(REG_INTER);
3472 %}
3473
3474 operand no_rax_rdx_RegI()
3475 %{
3476 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3477 match(RegI);
3478 match(rbx_RegI);
3479 match(rcx_RegI);
3480 match(rdi_RegI);
3481
3482 format %{ %}
3483 interface(REG_INTER);
3484 %}
3485
3486 // Pointer Register
3487 operand any_RegP()
3488 %{
3489 constraint(ALLOC_IN_RC(any_reg));
3490 match(RegP);
3491 match(rax_RegP);
3492 match(rbx_RegP);
3493 match(rdi_RegP);
3494 match(rsi_RegP);
3495 match(rbp_RegP);
3496 match(r15_RegP);
3497 match(rRegP);
3498
3499 format %{ %}
3500 interface(REG_INTER);
3501 %}
3502
3503 operand rRegP()
3504 %{
3505 constraint(ALLOC_IN_RC(ptr_reg));
3506 match(RegP);
3507 match(rax_RegP);
3508 match(rbx_RegP);
3509 match(rdi_RegP);
3510 match(rsi_RegP);
3511 match(rbp_RegP);
3512 match(r15_RegP); // See Q&A below about r15_RegP.
3513
3514 format %{ %}
3515 interface(REG_INTER);
3516 %}
3517
3518 operand rRegN() %{
3519 constraint(ALLOC_IN_RC(int_reg));
3520 match(RegN);
3521
3522 format %{ %}
3523 interface(REG_INTER);
3524 %}
3525
3526 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3527 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3528 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3529 // The output of an instruction is controlled by the allocator, which respects
3530 // register class masks, not match rules. Unless an instruction mentions
3531 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3532 // by the allocator as an input.
3533
3534 operand no_rax_RegP()
3535 %{
3536 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3537 match(RegP);
3538 match(rbx_RegP);
3539 match(rsi_RegP);
3540 match(rdi_RegP);
3541
3542 format %{ %}
3543 interface(REG_INTER);
3544 %}
3545
3546 operand no_rbp_RegP()
3547 %{
3548 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3549 match(RegP);
3550 match(rbx_RegP);
3551 match(rsi_RegP);
3552 match(rdi_RegP);
3553
3554 format %{ %}
3555 interface(REG_INTER);
3556 %}
3557
3558 operand no_rax_rbx_RegP()
3559 %{
3560 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3561 match(RegP);
3562 match(rsi_RegP);
3563 match(rdi_RegP);
3564
3565 format %{ %}
3566 interface(REG_INTER);
3567 %}
3568
3569 // Special Registers
3570 // Return a pointer value
3571 operand rax_RegP()
3572 %{
3573 constraint(ALLOC_IN_RC(ptr_rax_reg));
3574 match(RegP);
3575 match(rRegP);
3576
3577 format %{ %}
3578 interface(REG_INTER);
3579 %}
3580
3581 // Special Registers
3582 // Return a compressed pointer value
3583 operand rax_RegN()
3584 %{
3585 constraint(ALLOC_IN_RC(int_rax_reg));
3586 match(RegN);
3587 match(rRegN);
3588
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3592
3593 // Used in AtomicAdd
3594 operand rbx_RegP()
3595 %{
3596 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3597 match(RegP);
3598 match(rRegP);
3599
3600 format %{ %}
3601 interface(REG_INTER);
3602 %}
3603
3604 operand rsi_RegP()
3605 %{
3606 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3607 match(RegP);
3608 match(rRegP);
3609
3610 format %{ %}
3611 interface(REG_INTER);
3612 %}
3613
3614 // Used in rep stosq
3615 operand rdi_RegP()
3616 %{
3617 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3618 match(RegP);
3619 match(rRegP);
3620
3621 format %{ %}
3622 interface(REG_INTER);
3623 %}
3624
3625 operand rbp_RegP()
3626 %{
3627 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3628 match(RegP);
3629 match(rRegP);
3630
3631 format %{ %}
3632 interface(REG_INTER);
3633 %}
3634
3635 operand r15_RegP()
3636 %{
3637 constraint(ALLOC_IN_RC(ptr_r15_reg));
3638 match(RegP);
3639 match(rRegP);
3640
3641 format %{ %}
3642 interface(REG_INTER);
3643 %}
3644
3645 operand rRegL()
3646 %{
3647 constraint(ALLOC_IN_RC(long_reg));
3648 match(RegL);
3649 match(rax_RegL);
3650 match(rdx_RegL);
3651
3652 format %{ %}
3653 interface(REG_INTER);
3654 %}
3655
3656 // Special Registers
3657 operand no_rax_rdx_RegL()
3658 %{
3659 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3660 match(RegL);
3661 match(rRegL);
3662
3663 format %{ %}
3664 interface(REG_INTER);
3665 %}
3666
3667 operand no_rax_RegL()
3668 %{
3669 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3670 match(RegL);
3671 match(rRegL);
3672 match(rdx_RegL);
3673
3674 format %{ %}
3675 interface(REG_INTER);
3676 %}
3677
3678 operand no_rcx_RegL()
3679 %{
3680 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3681 match(RegL);
3682 match(rRegL);
3683
3684 format %{ %}
3685 interface(REG_INTER);
3686 %}
3687
3688 operand rax_RegL()
3689 %{
3690 constraint(ALLOC_IN_RC(long_rax_reg));
3691 match(RegL);
3692 match(rRegL);
3693
3694 format %{ "RAX" %}
3695 interface(REG_INTER);
3696 %}
3697
3698 operand rcx_RegL()
3699 %{
3700 constraint(ALLOC_IN_RC(long_rcx_reg));
3701 match(RegL);
3702 match(rRegL);
3703
3704 format %{ %}
3705 interface(REG_INTER);
3706 %}
3707
3708 operand rdx_RegL()
3709 %{
3710 constraint(ALLOC_IN_RC(long_rdx_reg));
3711 match(RegL);
3712 match(rRegL);
3713
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3717
3718 // Flags register, used as output of compare instructions
3719 operand rFlagsReg()
3720 %{
3721 constraint(ALLOC_IN_RC(int_flags));
3722 match(RegFlags);
3723
3724 format %{ "RFLAGS" %}
3725 interface(REG_INTER);
3726 %}
3727
3728 // Flags register, used as output of FLOATING POINT compare instructions
3729 operand rFlagsRegU()
3730 %{
3731 constraint(ALLOC_IN_RC(int_flags));
3732 match(RegFlags);
3733
3734 format %{ "RFLAGS_U" %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand rFlagsRegUCF() %{
3739 constraint(ALLOC_IN_RC(int_flags));
3740 match(RegFlags);
3741 predicate(false);
3742
3743 format %{ "RFLAGS_U_CF" %}
3744 interface(REG_INTER);
3745 %}
3746
3747 // Float register operands
3748 operand regF()
3749 %{
3750 constraint(ALLOC_IN_RC(float_reg));
3751 match(RegF);
3752
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3756
3757 // Double register operands
3758 operand regD()
3759 %{
3760 constraint(ALLOC_IN_RC(double_reg));
3761 match(RegD);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 //----------Memory Operands----------------------------------------------------
3768 // Direct Memory Operand
3769 // operand direct(immP addr)
3770 // %{
3771 // match(addr);
3772
3773 // format %{ "[$addr]" %}
3774 // interface(MEMORY_INTER) %{
3775 // base(0xFFFFFFFF);
3776 // index(0x4);
3777 // scale(0x0);
3778 // disp($addr);
3779 // %}
3780 // %}
3781
3782 // Indirect Memory Operand
3783 operand indirect(any_RegP reg)
3784 %{
3785 constraint(ALLOC_IN_RC(ptr_reg));
3786 match(reg);
3787
3788 format %{ "[$reg]" %}
3789 interface(MEMORY_INTER) %{
3790 base($reg);
3791 index(0x4);
3792 scale(0x0);
3793 disp(0x0);
3794 %}
3795 %}
3796
3797 // Indirect Memory Plus Short Offset Operand
3798 operand indOffset8(any_RegP reg, immL8 off)
3799 %{
3800 constraint(ALLOC_IN_RC(ptr_reg));
3801 match(AddP reg off);
3802
3803 format %{ "[$reg + $off (8-bit)]" %}
3804 interface(MEMORY_INTER) %{
3805 base($reg);
3806 index(0x4);
3807 scale(0x0);
3808 disp($off);
3809 %}
3810 %}
3811
3812 // Indirect Memory Plus Long Offset Operand
3813 operand indOffset32(any_RegP reg, immL32 off)
3814 %{
3815 constraint(ALLOC_IN_RC(ptr_reg));
3816 match(AddP reg off);
3817
3818 format %{ "[$reg + $off (32-bit)]" %}
3819 interface(MEMORY_INTER) %{
3820 base($reg);
3821 index(0x4);
3822 scale(0x0);
3823 disp($off);
3824 %}
3825 %}
3826
3827 // Indirect Memory Plus Index Register Plus Offset Operand
3828 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3829 %{
3830 constraint(ALLOC_IN_RC(ptr_reg));
3831 match(AddP (AddP reg lreg) off);
3832
3833 op_cost(10);
3834 format %{"[$reg + $off + $lreg]" %}
3835 interface(MEMORY_INTER) %{
3836 base($reg);
3837 index($lreg);
3838 scale(0x0);
3839 disp($off);
3840 %}
3841 %}
3842
3843 // Indirect Memory Plus Index Register Plus Offset Operand
3844 operand indIndex(any_RegP reg, rRegL lreg)
3845 %{
3846 constraint(ALLOC_IN_RC(ptr_reg));
3847 match(AddP reg lreg);
3848
3849 op_cost(10);
3850 format %{"[$reg + $lreg]" %}
3851 interface(MEMORY_INTER) %{
3852 base($reg);
3853 index($lreg);
3854 scale(0x0);
3855 disp(0x0);
3856 %}
3857 %}
3858
3859 // Indirect Memory Times Scale Plus Index Register
3860 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3861 %{
3862 constraint(ALLOC_IN_RC(ptr_reg));
3863 match(AddP reg (LShiftL lreg scale));
3864
3865 op_cost(10);
3866 format %{"[$reg + $lreg << $scale]" %}
3867 interface(MEMORY_INTER) %{
3868 base($reg);
3869 index($lreg);
3870 scale($scale);
3871 disp(0x0);
3872 %}
3873 %}
3874
3875 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3876 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3877 %{
3878 constraint(ALLOC_IN_RC(ptr_reg));
3879 match(AddP (AddP reg (LShiftL lreg scale)) off);
3880
3881 op_cost(10);
3882 format %{"[$reg + $off + $lreg << $scale]" %}
3883 interface(MEMORY_INTER) %{
3884 base($reg);
3885 index($lreg);
3886 scale($scale);
3887 disp($off);
3888 %}
3889 %}
3890
3891 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3892 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3893 %{
3894 constraint(ALLOC_IN_RC(ptr_reg));
3895 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3896 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3897
3898 op_cost(10);
3899 format %{"[$reg + $off + $idx << $scale]" %}
3900 interface(MEMORY_INTER) %{
3901 base($reg);
3902 index($idx);
3903 scale($scale);
3904 disp($off);
3905 %}
3906 %}
3907
3908 // Indirect Narrow Oop Plus Offset Operand
3909 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3910 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3911 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3912 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3913 constraint(ALLOC_IN_RC(ptr_reg));
3914 match(AddP (DecodeN reg) off);
3915
3916 op_cost(10);
3917 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3918 interface(MEMORY_INTER) %{
3919 base(0xc); // R12
3920 index($reg);
3921 scale(0x3);
3922 disp($off);
3923 %}
3924 %}
3925
3926 // Indirect Memory Operand
3927 operand indirectNarrow(rRegN reg)
3928 %{
3929 predicate(Universe::narrow_oop_shift() == 0);
3930 constraint(ALLOC_IN_RC(ptr_reg));
3931 match(DecodeN reg);
3932
3933 format %{ "[$reg]" %}
3934 interface(MEMORY_INTER) %{
3935 base($reg);
3936 index(0x4);
3937 scale(0x0);
3938 disp(0x0);
3939 %}
3940 %}
3941
3942 // Indirect Memory Plus Short Offset Operand
3943 operand indOffset8Narrow(rRegN reg, immL8 off)
3944 %{
3945 predicate(Universe::narrow_oop_shift() == 0);
3946 constraint(ALLOC_IN_RC(ptr_reg));
3947 match(AddP (DecodeN reg) off);
3948
3949 format %{ "[$reg + $off (8-bit)]" %}
3950 interface(MEMORY_INTER) %{
3951 base($reg);
3952 index(0x4);
3953 scale(0x0);
3954 disp($off);
3955 %}
3956 %}
3957
3958 // Indirect Memory Plus Long Offset Operand
3959 operand indOffset32Narrow(rRegN reg, immL32 off)
3960 %{
3961 predicate(Universe::narrow_oop_shift() == 0);
3962 constraint(ALLOC_IN_RC(ptr_reg));
3963 match(AddP (DecodeN reg) off);
3964
3965 format %{ "[$reg + $off (32-bit)]" %}
3966 interface(MEMORY_INTER) %{
3967 base($reg);
3968 index(0x4);
3969 scale(0x0);
3970 disp($off);
3971 %}
3972 %}
3973
3974 // Indirect Memory Plus Index Register Plus Offset Operand
3975 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3976 %{
3977 predicate(Universe::narrow_oop_shift() == 0);
3978 constraint(ALLOC_IN_RC(ptr_reg));
3979 match(AddP (AddP (DecodeN reg) lreg) off);
3980
3981 op_cost(10);
3982 format %{"[$reg + $off + $lreg]" %}
3983 interface(MEMORY_INTER) %{
3984 base($reg);
3985 index($lreg);
3986 scale(0x0);
3987 disp($off);
3988 %}
3989 %}
3990
3991 // Indirect Memory Plus Index Register Plus Offset Operand
3992 operand indIndexNarrow(rRegN reg, rRegL lreg)
3993 %{
3994 predicate(Universe::narrow_oop_shift() == 0);
3995 constraint(ALLOC_IN_RC(ptr_reg));
3996 match(AddP (DecodeN reg) lreg);
3997
3998 op_cost(10);
3999 format %{"[$reg + $lreg]" %}
4000 interface(MEMORY_INTER) %{
4001 base($reg);
4002 index($lreg);
4003 scale(0x0);
4004 disp(0x0);
4005 %}
4006 %}
4007
4008 // Indirect Memory Times Scale Plus Index Register
4009 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4010 %{
4011 predicate(Universe::narrow_oop_shift() == 0);
4012 constraint(ALLOC_IN_RC(ptr_reg));
4013 match(AddP (DecodeN reg) (LShiftL lreg scale));
4014
4015 op_cost(10);
4016 format %{"[$reg + $lreg << $scale]" %}
4017 interface(MEMORY_INTER) %{
4018 base($reg);
4019 index($lreg);
4020 scale($scale);
4021 disp(0x0);
4022 %}
4023 %}
4024
4025 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4026 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4027 %{
4028 predicate(Universe::narrow_oop_shift() == 0);
4029 constraint(ALLOC_IN_RC(ptr_reg));
4030 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4031
4032 op_cost(10);
4033 format %{"[$reg + $off + $lreg << $scale]" %}
4034 interface(MEMORY_INTER) %{
4035 base($reg);
4036 index($lreg);
4037 scale($scale);
4038 disp($off);
4039 %}
4040 %}
4041
4042 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4043 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4044 %{
4045 constraint(ALLOC_IN_RC(ptr_reg));
4046 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4047 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4048
4049 op_cost(10);
4050 format %{"[$reg + $off + $idx << $scale]" %}
4051 interface(MEMORY_INTER) %{
4052 base($reg);
4053 index($idx);
4054 scale($scale);
4055 disp($off);
4056 %}
4057 %}
4058
4059 //----------Special Memory Operands--------------------------------------------
4060 // Stack Slot Operand - This operand is used for loading and storing temporary
4061 // values on the stack where a match requires a value to
4062 // flow through memory.
4063 operand stackSlotP(sRegP reg)
4064 %{
4065 constraint(ALLOC_IN_RC(stack_slots));
4066 // No match rule because this operand is only generated in matching
4067
4068 format %{ "[$reg]" %}
4069 interface(MEMORY_INTER) %{
4070 base(0x4); // RSP
4071 index(0x4); // No Index
4072 scale(0x0); // No Scale
4073 disp($reg); // Stack Offset
4074 %}
4075 %}
4076
4077 operand stackSlotI(sRegI reg)
4078 %{
4079 constraint(ALLOC_IN_RC(stack_slots));
4080 // No match rule because this operand is only generated in matching
4081
4082 format %{ "[$reg]" %}
4083 interface(MEMORY_INTER) %{
4084 base(0x4); // RSP
4085 index(0x4); // No Index
4086 scale(0x0); // No Scale
4087 disp($reg); // Stack Offset
4088 %}
4089 %}
4090
4091 operand stackSlotF(sRegF reg)
4092 %{
4093 constraint(ALLOC_IN_RC(stack_slots));
4094 // No match rule because this operand is only generated in matching
4095
4096 format %{ "[$reg]" %}
4097 interface(MEMORY_INTER) %{
4098 base(0x4); // RSP
4099 index(0x4); // No Index
4100 scale(0x0); // No Scale
4101 disp($reg); // Stack Offset
4102 %}
4103 %}
4104
4105 operand stackSlotD(sRegD reg)
4106 %{
4107 constraint(ALLOC_IN_RC(stack_slots));
4108 // No match rule because this operand is only generated in matching
4109
4110 format %{ "[$reg]" %}
4111 interface(MEMORY_INTER) %{
4112 base(0x4); // RSP
4113 index(0x4); // No Index
4114 scale(0x0); // No Scale
4115 disp($reg); // Stack Offset
4116 %}
4117 %}
4118 operand stackSlotL(sRegL reg)
4119 %{
4120 constraint(ALLOC_IN_RC(stack_slots));
4121 // No match rule because this operand is only generated in matching
4122
4123 format %{ "[$reg]" %}
4124 interface(MEMORY_INTER) %{
4125 base(0x4); // RSP
4126 index(0x4); // No Index
4127 scale(0x0); // No Scale
4128 disp($reg); // Stack Offset
4129 %}
4130 %}
4131
4132 //----------Conditional Branch Operands----------------------------------------
4133 // Comparison Op - This is the operation of the comparison, and is limited to
4134 // the following set of codes:
4135 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4136 //
4137 // Other attributes of the comparison, such as unsignedness, are specified
4138 // by the comparison instruction that sets a condition code flags register.
4139 // That result is represented by a flags operand whose subtype is appropriate
4140 // to the unsignedness (etc.) of the comparison.
4141 //
4142 // Later, the instruction which matches both the Comparison Op (a Bool) and
4143 // the flags (produced by the Cmp) specifies the coding of the comparison op
4144 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4145
4146 // Comparision Code
4147 operand cmpOp()
4148 %{
4149 match(Bool);
4150
4151 format %{ "" %}
4152 interface(COND_INTER) %{
4153 equal(0x4, "e");
4154 not_equal(0x5, "ne");
4155 less(0xC, "l");
4156 greater_equal(0xD, "ge");
4157 less_equal(0xE, "le");
4158 greater(0xF, "g");
4159 overflow(0x0, "o");
4160 no_overflow(0x1, "no");
4161 %}
4162 %}
4163
4164 // Comparison Code, unsigned compare. Used by FP also, with
4165 // C2 (unordered) turned into GT or LT already. The other bits
4166 // C0 and C3 are turned into Carry & Zero flags.
4167 operand cmpOpU()
4168 %{
4169 match(Bool);
4170
4171 format %{ "" %}
4172 interface(COND_INTER) %{
4173 equal(0x4, "e");
4174 not_equal(0x5, "ne");
4175 less(0x2, "b");
4176 greater_equal(0x3, "nb");
4177 less_equal(0x6, "be");
4178 greater(0x7, "nbe");
4179 overflow(0x0, "o");
4180 no_overflow(0x1, "no");
4181 %}
4182 %}
4183
4184
4185 // Floating comparisons that don't require any fixup for the unordered case
4186 operand cmpOpUCF() %{
4187 match(Bool);
4188 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4189 n->as_Bool()->_test._test == BoolTest::ge ||
4190 n->as_Bool()->_test._test == BoolTest::le ||
4191 n->as_Bool()->_test._test == BoolTest::gt);
4192 format %{ "" %}
4193 interface(COND_INTER) %{
4194 equal(0x4, "e");
4195 not_equal(0x5, "ne");
4196 less(0x2, "b");
4197 greater_equal(0x3, "nb");
4198 less_equal(0x6, "be");
4199 greater(0x7, "nbe");
4200 overflow(0x0, "o");
4201 no_overflow(0x1, "no");
4202 %}
4203 %}
4204
4205
4206 // Floating comparisons that can be fixed up with extra conditional jumps
4207 operand cmpOpUCF2() %{
4208 match(Bool);
4209 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4210 n->as_Bool()->_test._test == BoolTest::eq);
4211 format %{ "" %}
4212 interface(COND_INTER) %{
4213 equal(0x4, "e");
4214 not_equal(0x5, "ne");
4215 less(0x2, "b");
4216 greater_equal(0x3, "nb");
4217 less_equal(0x6, "be");
4218 greater(0x7, "nbe");
4219 overflow(0x0, "o");
4220 no_overflow(0x1, "no");
4221 %}
4222 %}
4223
4224
4225 //----------OPERAND CLASSES----------------------------------------------------
4226 // Operand Classes are groups of operands that are used as to simplify
4227 // instruction definitions by not requiring the AD writer to specify separate
4228 // instructions for every form of operand when the instruction accepts
4229 // multiple operand types with the same basic encoding and format. The classic
4230 // case of this is memory operands.
4231
4232 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4233 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4234 indCompressedOopOffset,
4235 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4236 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4237 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4238
4239 //----------PIPELINE-----------------------------------------------------------
4240 // Rules which define the behavior of the target architectures pipeline.
4241 pipeline %{
4242
4243 //----------ATTRIBUTES---------------------------------------------------------
4244 attributes %{
4245 variable_size_instructions; // Fixed size instructions
4246 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4247 instruction_unit_size = 1; // An instruction is 1 bytes long
4248 instruction_fetch_unit_size = 16; // The processor fetches one line
4249 instruction_fetch_units = 1; // of 16 bytes
4250
4251 // List of nop instructions
4252 nops( MachNop );
4253 %}
4254
4255 //----------RESOURCES----------------------------------------------------------
4256 // Resources are the functional units available to the machine
4257
4258 // Generic P2/P3 pipeline
4259 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4260 // 3 instructions decoded per cycle.
4261 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4262 // 3 ALU op, only ALU0 handles mul instructions.
4263 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4264 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4265 BR, FPU,
4266 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4267
4268 //----------PIPELINE DESCRIPTION-----------------------------------------------
4269 // Pipeline Description specifies the stages in the machine's pipeline
4270
4271 // Generic P2/P3 pipeline
4272 pipe_desc(S0, S1, S2, S3, S4, S5);
4273
4274 //----------PIPELINE CLASSES---------------------------------------------------
4275 // Pipeline Classes describe the stages in which input and output are
4276 // referenced by the hardware pipeline.
4277
4278 // Naming convention: ialu or fpu
4279 // Then: _reg
4280 // Then: _reg if there is a 2nd register
4281 // Then: _long if it's a pair of instructions implementing a long
4282 // Then: _fat if it requires the big decoder
4283 // Or: _mem if it requires the big decoder and a memory unit.
4284
4285 // Integer ALU reg operation
4286 pipe_class ialu_reg(rRegI dst)
4287 %{
4288 single_instruction;
4289 dst : S4(write);
4290 dst : S3(read);
4291 DECODE : S0; // any decoder
4292 ALU : S3; // any alu
4293 %}
4294
4295 // Long ALU reg operation
4296 pipe_class ialu_reg_long(rRegL dst)
4297 %{
4298 instruction_count(2);
4299 dst : S4(write);
4300 dst : S3(read);
4301 DECODE : S0(2); // any 2 decoders
4302 ALU : S3(2); // both alus
4303 %}
4304
4305 // Integer ALU reg operation using big decoder
4306 pipe_class ialu_reg_fat(rRegI dst)
4307 %{
4308 single_instruction;
4309 dst : S4(write);
4310 dst : S3(read);
4311 D0 : S0; // big decoder only
4312 ALU : S3; // any alu
4313 %}
4314
4315 // Long ALU reg operation using big decoder
4316 pipe_class ialu_reg_long_fat(rRegL dst)
4317 %{
4318 instruction_count(2);
4319 dst : S4(write);
4320 dst : S3(read);
4321 D0 : S0(2); // big decoder only; twice
4322 ALU : S3(2); // any 2 alus
4323 %}
4324
4325 // Integer ALU reg-reg operation
4326 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4327 %{
4328 single_instruction;
4329 dst : S4(write);
4330 src : S3(read);
4331 DECODE : S0; // any decoder
4332 ALU : S3; // any alu
4333 %}
4334
4335 // Long ALU reg-reg operation
4336 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4337 %{
4338 instruction_count(2);
4339 dst : S4(write);
4340 src : S3(read);
4341 DECODE : S0(2); // any 2 decoders
4342 ALU : S3(2); // both alus
4343 %}
4344
4345 // Integer ALU reg-reg operation
4346 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4347 %{
4348 single_instruction;
4349 dst : S4(write);
4350 src : S3(read);
4351 D0 : S0; // big decoder only
4352 ALU : S3; // any alu
4353 %}
4354
4355 // Long ALU reg-reg operation
4356 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4357 %{
4358 instruction_count(2);
4359 dst : S4(write);
4360 src : S3(read);
4361 D0 : S0(2); // big decoder only; twice
4362 ALU : S3(2); // both alus
4363 %}
4364
4365 // Integer ALU reg-mem operation
4366 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4367 %{
4368 single_instruction;
4369 dst : S5(write);
4370 mem : S3(read);
4371 D0 : S0; // big decoder only
4372 ALU : S4; // any alu
4373 MEM : S3; // any mem
4374 %}
4375
4376 // Integer mem operation (prefetch)
4377 pipe_class ialu_mem(memory mem)
4378 %{
4379 single_instruction;
4380 mem : S3(read);
4381 D0 : S0; // big decoder only
4382 MEM : S3; // any mem
4383 %}
4384
4385 // Integer Store to Memory
4386 pipe_class ialu_mem_reg(memory mem, rRegI src)
4387 %{
4388 single_instruction;
4389 mem : S3(read);
4390 src : S5(read);
4391 D0 : S0; // big decoder only
4392 ALU : S4; // any alu
4393 MEM : S3;
4394 %}
4395
4396 // // Long Store to Memory
4397 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4398 // %{
4399 // instruction_count(2);
4400 // mem : S3(read);
4401 // src : S5(read);
4402 // D0 : S0(2); // big decoder only; twice
4403 // ALU : S4(2); // any 2 alus
4404 // MEM : S3(2); // Both mems
4405 // %}
4406
4407 // Integer Store to Memory
4408 pipe_class ialu_mem_imm(memory mem)
4409 %{
4410 single_instruction;
4411 mem : S3(read);
4412 D0 : S0; // big decoder only
4413 ALU : S4; // any alu
4414 MEM : S3;
4415 %}
4416
4417 // Integer ALU0 reg-reg operation
4418 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4419 %{
4420 single_instruction;
4421 dst : S4(write);
4422 src : S3(read);
4423 D0 : S0; // Big decoder only
4424 ALU0 : S3; // only alu0
4425 %}
4426
4427 // Integer ALU0 reg-mem operation
4428 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4429 %{
4430 single_instruction;
4431 dst : S5(write);
4432 mem : S3(read);
4433 D0 : S0; // big decoder only
4434 ALU0 : S4; // ALU0 only
4435 MEM : S3; // any mem
4436 %}
4437
4438 // Integer ALU reg-reg operation
4439 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4440 %{
4441 single_instruction;
4442 cr : S4(write);
4443 src1 : S3(read);
4444 src2 : S3(read);
4445 DECODE : S0; // any decoder
4446 ALU : S3; // any alu
4447 %}
4448
4449 // Integer ALU reg-imm operation
4450 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4451 %{
4452 single_instruction;
4453 cr : S4(write);
4454 src1 : S3(read);
4455 DECODE : S0; // any decoder
4456 ALU : S3; // any alu
4457 %}
4458
4459 // Integer ALU reg-mem operation
4460 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4461 %{
4462 single_instruction;
4463 cr : S4(write);
4464 src1 : S3(read);
4465 src2 : S3(read);
4466 D0 : S0; // big decoder only
4467 ALU : S4; // any alu
4468 MEM : S3;
4469 %}
4470
4471 // Conditional move reg-reg
4472 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4473 %{
4474 instruction_count(4);
4475 y : S4(read);
4476 q : S3(read);
4477 p : S3(read);
4478 DECODE : S0(4); // any decoder
4479 %}
4480
4481 // Conditional move reg-reg
4482 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4483 %{
4484 single_instruction;
4485 dst : S4(write);
4486 src : S3(read);
4487 cr : S3(read);
4488 DECODE : S0; // any decoder
4489 %}
4490
4491 // Conditional move reg-mem
4492 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4493 %{
4494 single_instruction;
4495 dst : S4(write);
4496 src : S3(read);
4497 cr : S3(read);
4498 DECODE : S0; // any decoder
4499 MEM : S3;
4500 %}
4501
4502 // Conditional move reg-reg long
4503 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4504 %{
4505 single_instruction;
4506 dst : S4(write);
4507 src : S3(read);
4508 cr : S3(read);
4509 DECODE : S0(2); // any 2 decoders
4510 %}
4511
4512 // XXX
4513 // // Conditional move double reg-reg
4514 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4515 // %{
4516 // single_instruction;
4517 // dst : S4(write);
4518 // src : S3(read);
4519 // cr : S3(read);
4520 // DECODE : S0; // any decoder
4521 // %}
4522
4523 // Float reg-reg operation
4524 pipe_class fpu_reg(regD dst)
4525 %{
4526 instruction_count(2);
4527 dst : S3(read);
4528 DECODE : S0(2); // any 2 decoders
4529 FPU : S3;
4530 %}
4531
4532 // Float reg-reg operation
4533 pipe_class fpu_reg_reg(regD dst, regD src)
4534 %{
4535 instruction_count(2);
4536 dst : S4(write);
4537 src : S3(read);
4538 DECODE : S0(2); // any 2 decoders
4539 FPU : S3;
4540 %}
4541
4542 // Float reg-reg operation
4543 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4544 %{
4545 instruction_count(3);
4546 dst : S4(write);
4547 src1 : S3(read);
4548 src2 : S3(read);
4549 DECODE : S0(3); // any 3 decoders
4550 FPU : S3(2);
4551 %}
4552
4553 // Float reg-reg operation
4554 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4555 %{
4556 instruction_count(4);
4557 dst : S4(write);
4558 src1 : S3(read);
4559 src2 : S3(read);
4560 src3 : S3(read);
4561 DECODE : S0(4); // any 3 decoders
4562 FPU : S3(2);
4563 %}
4564
4565 // Float reg-reg operation
4566 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4567 %{
4568 instruction_count(4);
4569 dst : S4(write);
4570 src1 : S3(read);
4571 src2 : S3(read);
4572 src3 : S3(read);
4573 DECODE : S1(3); // any 3 decoders
4574 D0 : S0; // Big decoder only
4575 FPU : S3(2);
4576 MEM : S3;
4577 %}
4578
4579 // Float reg-mem operation
4580 pipe_class fpu_reg_mem(regD dst, memory mem)
4581 %{
4582 instruction_count(2);
4583 dst : S5(write);
4584 mem : S3(read);
4585 D0 : S0; // big decoder only
4586 DECODE : S1; // any decoder for FPU POP
4587 FPU : S4;
4588 MEM : S3; // any mem
4589 %}
4590
4591 // Float reg-mem operation
4592 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4593 %{
4594 instruction_count(3);
4595 dst : S5(write);
4596 src1 : S3(read);
4597 mem : S3(read);
4598 D0 : S0; // big decoder only
4599 DECODE : S1(2); // any decoder for FPU POP
4600 FPU : S4;
4601 MEM : S3; // any mem
4602 %}
4603
4604 // Float mem-reg operation
4605 pipe_class fpu_mem_reg(memory mem, regD src)
4606 %{
4607 instruction_count(2);
4608 src : S5(read);
4609 mem : S3(read);
4610 DECODE : S0; // any decoder for FPU PUSH
4611 D0 : S1; // big decoder only
4612 FPU : S4;
4613 MEM : S3; // any mem
4614 %}
4615
4616 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4617 %{
4618 instruction_count(3);
4619 src1 : S3(read);
4620 src2 : S3(read);
4621 mem : S3(read);
4622 DECODE : S0(2); // any decoder for FPU PUSH
4623 D0 : S1; // big decoder only
4624 FPU : S4;
4625 MEM : S3; // any mem
4626 %}
4627
4628 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4629 %{
4630 instruction_count(3);
4631 src1 : S3(read);
4632 src2 : S3(read);
4633 mem : S4(read);
4634 DECODE : S0; // any decoder for FPU PUSH
4635 D0 : S0(2); // big decoder only
4636 FPU : S4;
4637 MEM : S3(2); // any mem
4638 %}
4639
4640 pipe_class fpu_mem_mem(memory dst, memory src1)
4641 %{
4642 instruction_count(2);
4643 src1 : S3(read);
4644 dst : S4(read);
4645 D0 : S0(2); // big decoder only
4646 MEM : S3(2); // any mem
4647 %}
4648
4649 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4650 %{
4651 instruction_count(3);
4652 src1 : S3(read);
4653 src2 : S3(read);
4654 dst : S4(read);
4655 D0 : S0(3); // big decoder only
4656 FPU : S4;
4657 MEM : S3(3); // any mem
4658 %}
4659
4660 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4661 %{
4662 instruction_count(3);
4663 src1 : S4(read);
4664 mem : S4(read);
4665 DECODE : S0; // any decoder for FPU PUSH
4666 D0 : S0(2); // big decoder only
4667 FPU : S4;
4668 MEM : S3(2); // any mem
4669 %}
4670
4671 // Float load constant
4672 pipe_class fpu_reg_con(regD dst)
4673 %{
4674 instruction_count(2);
4675 dst : S5(write);
4676 D0 : S0; // big decoder only for the load
4677 DECODE : S1; // any decoder for FPU POP
4678 FPU : S4;
4679 MEM : S3; // any mem
4680 %}
4681
4682 // Float load constant
4683 pipe_class fpu_reg_reg_con(regD dst, regD src)
4684 %{
4685 instruction_count(3);
4686 dst : S5(write);
4687 src : S3(read);
4688 D0 : S0; // big decoder only for the load
4689 DECODE : S1(2); // any decoder for FPU POP
4690 FPU : S4;
4691 MEM : S3; // any mem
4692 %}
4693
4694 // UnConditional branch
4695 pipe_class pipe_jmp(label labl)
4696 %{
4697 single_instruction;
4698 BR : S3;
4699 %}
4700
4701 // Conditional branch
4702 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4703 %{
4704 single_instruction;
4705 cr : S1(read);
4706 BR : S3;
4707 %}
4708
4709 // Allocation idiom
4710 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4711 %{
4712 instruction_count(1); force_serialization;
4713 fixed_latency(6);
4714 heap_ptr : S3(read);
4715 DECODE : S0(3);
4716 D0 : S2;
4717 MEM : S3;
4718 ALU : S3(2);
4719 dst : S5(write);
4720 BR : S5;
4721 %}
4722
4723 // Generic big/slow expanded idiom
4724 pipe_class pipe_slow()
4725 %{
4726 instruction_count(10); multiple_bundles; force_serialization;
4727 fixed_latency(100);
4728 D0 : S0(2);
4729 MEM : S3(2);
4730 %}
4731
4732 // The real do-nothing guy
4733 pipe_class empty()
4734 %{
4735 instruction_count(0);
4736 %}
4737
4738 // Define the class for the Nop node
4739 define
4740 %{
4741 MachNop = empty;
4742 %}
4743
4744 %}
4745
4746 //----------INSTRUCTIONS-------------------------------------------------------
4747 //
4748 // match -- States which machine-independent subtree may be replaced
4749 // by this instruction.
4750 // ins_cost -- The estimated cost of this instruction is used by instruction
4751 // selection to identify a minimum cost tree of machine
4752 // instructions that matches a tree of machine-independent
4753 // instructions.
4754 // format -- A string providing the disassembly for this instruction.
4755 // The value of an instruction's operand may be inserted
4756 // by referring to it with a '$' prefix.
4757 // opcode -- Three instruction opcodes may be provided. These are referred
4758 // to within an encode class as $primary, $secondary, and $tertiary
4759 // rrspectively. The primary opcode is commonly used to
4760 // indicate the type of machine instruction, while secondary
4761 // and tertiary are often used for prefix options or addressing
4762 // modes.
4763 // ins_encode -- A list of encode classes with parameters. The encode class
4764 // name must have been defined in an 'enc_class' specification
4765 // in the encode section of the architecture description.
4766
4767
4768 //----------Load/Store/Move Instructions---------------------------------------
4769 //----------Load Instructions--------------------------------------------------
4770
4771 // Load Byte (8 bit signed)
4772 instruct loadB(rRegI dst, memory mem)
4773 %{
4774 match(Set dst (LoadB mem));
4775
4776 ins_cost(125);
4777 format %{ "movsbl $dst, $mem\t# byte" %}
4778
4779 ins_encode %{
4780 __ movsbl($dst$$Register, $mem$$Address);
4781 %}
4782
4783 ins_pipe(ialu_reg_mem);
4784 %}
4785
4786 // Load Byte (8 bit signed) into Long Register
4787 instruct loadB2L(rRegL dst, memory mem)
4788 %{
4789 match(Set dst (ConvI2L (LoadB mem)));
4790
4791 ins_cost(125);
4792 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4793
4794 ins_encode %{
4795 __ movsbq($dst$$Register, $mem$$Address);
4796 %}
4797
4798 ins_pipe(ialu_reg_mem);
4799 %}
4800
4801 // Load Unsigned Byte (8 bit UNsigned)
4802 instruct loadUB(rRegI dst, memory mem)
4803 %{
4804 match(Set dst (LoadUB mem));
4805
4806 ins_cost(125);
4807 format %{ "movzbl $dst, $mem\t# ubyte" %}
4808
4809 ins_encode %{
4810 __ movzbl($dst$$Register, $mem$$Address);
4811 %}
4812
4813 ins_pipe(ialu_reg_mem);
4814 %}
4815
4816 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4817 instruct loadUB2L(rRegL dst, memory mem)
4818 %{
4819 match(Set dst (ConvI2L (LoadUB mem)));
4820
4821 ins_cost(125);
4822 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4823
4824 ins_encode %{
4825 __ movzbq($dst$$Register, $mem$$Address);
4826 %}
4827
4828 ins_pipe(ialu_reg_mem);
4829 %}
4830
4831 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4832 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4833 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4834 effect(KILL cr);
4835
4836 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4837 "andl $dst, $mask" %}
4838 ins_encode %{
4839 Register Rdst = $dst$$Register;
4840 __ movzbq(Rdst, $mem$$Address);
4841 __ andl(Rdst, $mask$$constant);
4842 %}
4843 ins_pipe(ialu_reg_mem);
4844 %}
4845
4846 // Load Short (16 bit signed)
4847 instruct loadS(rRegI dst, memory mem)
4848 %{
4849 match(Set dst (LoadS mem));
4850
4851 ins_cost(125);
4852 format %{ "movswl $dst, $mem\t# short" %}
4853
4854 ins_encode %{
4855 __ movswl($dst$$Register, $mem$$Address);
4856 %}
4857
4858 ins_pipe(ialu_reg_mem);
4859 %}
4860
4861 // Load Short (16 bit signed) to Byte (8 bit signed)
4862 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4863 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4864
4865 ins_cost(125);
4866 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4867 ins_encode %{
4868 __ movsbl($dst$$Register, $mem$$Address);
4869 %}
4870 ins_pipe(ialu_reg_mem);
4871 %}
4872
4873 // Load Short (16 bit signed) into Long Register
4874 instruct loadS2L(rRegL dst, memory mem)
4875 %{
4876 match(Set dst (ConvI2L (LoadS mem)));
4877
4878 ins_cost(125);
4879 format %{ "movswq $dst, $mem\t# short -> long" %}
4880
4881 ins_encode %{
4882 __ movswq($dst$$Register, $mem$$Address);
4883 %}
4884
4885 ins_pipe(ialu_reg_mem);
4886 %}
4887
4888 // Load Unsigned Short/Char (16 bit UNsigned)
4889 instruct loadUS(rRegI dst, memory mem)
4890 %{
4891 match(Set dst (LoadUS mem));
4892
4893 ins_cost(125);
4894 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4895
4896 ins_encode %{
4897 __ movzwl($dst$$Register, $mem$$Address);
4898 %}
4899
4900 ins_pipe(ialu_reg_mem);
4901 %}
4902
4903 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4904 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4905 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4906
4907 ins_cost(125);
4908 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4909 ins_encode %{
4910 __ movsbl($dst$$Register, $mem$$Address);
4911 %}
4912 ins_pipe(ialu_reg_mem);
4913 %}
4914
4915 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4916 instruct loadUS2L(rRegL dst, memory mem)
4917 %{
4918 match(Set dst (ConvI2L (LoadUS mem)));
4919
4920 ins_cost(125);
4921 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4922
4923 ins_encode %{
4924 __ movzwq($dst$$Register, $mem$$Address);
4925 %}
4926
4927 ins_pipe(ialu_reg_mem);
4928 %}
4929
4930 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4931 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4932 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4933
4934 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4935 ins_encode %{
4936 __ movzbq($dst$$Register, $mem$$Address);
4937 %}
4938 ins_pipe(ialu_reg_mem);
4939 %}
4940
4941 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4942 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4943 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4944 effect(KILL cr);
4945
4946 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4947 "andl $dst, $mask" %}
4948 ins_encode %{
4949 Register Rdst = $dst$$Register;
4950 __ movzwq(Rdst, $mem$$Address);
4951 __ andl(Rdst, $mask$$constant);
4952 %}
4953 ins_pipe(ialu_reg_mem);
4954 %}
4955
4956 // Load Integer
4957 instruct loadI(rRegI dst, memory mem)
4958 %{
4959 match(Set dst (LoadI mem));
4960
4961 ins_cost(125);
4962 format %{ "movl $dst, $mem\t# int" %}
4963
4964 ins_encode %{
4965 __ movl($dst$$Register, $mem$$Address);
4966 %}
4967
4968 ins_pipe(ialu_reg_mem);
4969 %}
4970
4971 // Load Integer (32 bit signed) to Byte (8 bit signed)
4972 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4973 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4974
4975 ins_cost(125);
4976 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4977 ins_encode %{
4978 __ movsbl($dst$$Register, $mem$$Address);
4979 %}
4980 ins_pipe(ialu_reg_mem);
4981 %}
4982
4983 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4984 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4985 match(Set dst (AndI (LoadI mem) mask));
4986
4987 ins_cost(125);
4988 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4989 ins_encode %{
4990 __ movzbl($dst$$Register, $mem$$Address);
4991 %}
4992 ins_pipe(ialu_reg_mem);
4993 %}
4994
4995 // Load Integer (32 bit signed) to Short (16 bit signed)
4996 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4997 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4998
4999 ins_cost(125);
5000 format %{ "movswl $dst, $mem\t# int -> short" %}
5001 ins_encode %{
5002 __ movswl($dst$$Register, $mem$$Address);
5003 %}
5004 ins_pipe(ialu_reg_mem);
5005 %}
5006
5007 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5008 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5009 match(Set dst (AndI (LoadI mem) mask));
5010
5011 ins_cost(125);
5012 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5013 ins_encode %{
5014 __ movzwl($dst$$Register, $mem$$Address);
5015 %}
5016 ins_pipe(ialu_reg_mem);
5017 %}
5018
5019 // Load Integer into Long Register
5020 instruct loadI2L(rRegL dst, memory mem)
5021 %{
5022 match(Set dst (ConvI2L (LoadI mem)));
5023
5024 ins_cost(125);
5025 format %{ "movslq $dst, $mem\t# int -> long" %}
5026
5027 ins_encode %{
5028 __ movslq($dst$$Register, $mem$$Address);
5029 %}
5030
5031 ins_pipe(ialu_reg_mem);
5032 %}
5033
5034 // Load Integer with mask 0xFF into Long Register
5035 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5036 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5037
5038 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5039 ins_encode %{
5040 __ movzbq($dst$$Register, $mem$$Address);
5041 %}
5042 ins_pipe(ialu_reg_mem);
5043 %}
5044
5045 // Load Integer with mask 0xFFFF into Long Register
5046 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5047 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5048
5049 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5050 ins_encode %{
5051 __ movzwq($dst$$Register, $mem$$Address);
5052 %}
5053 ins_pipe(ialu_reg_mem);
5054 %}
5055
5056 // Load Integer with a 31-bit mask into Long Register
5057 instruct loadI2L_immU32(rRegL dst, memory mem, immU32 mask, rFlagsReg cr) %{
5058 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5059 effect(KILL cr);
5060
5061 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5062 "andl $dst, $mask" %}
5063 ins_encode %{
5064 Register Rdst = $dst$$Register;
5065 __ movl(Rdst, $mem$$Address);
5066 __ andl(Rdst, $mask$$constant);
5067 %}
5068 ins_pipe(ialu_reg_mem);
5069 %}
5070
5071 // Load Unsigned Integer into Long Register
5072 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5073 %{
5074 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5075
5076 ins_cost(125);
5077 format %{ "movl $dst, $mem\t# uint -> long" %}
5078
5079 ins_encode %{
5080 __ movl($dst$$Register, $mem$$Address);
5081 %}
5082
5083 ins_pipe(ialu_reg_mem);
5084 %}
5085
5086 // Load Long
5087 instruct loadL(rRegL dst, memory mem)
5088 %{
5089 match(Set dst (LoadL mem));
5090
5091 ins_cost(125);
5092 format %{ "movq $dst, $mem\t# long" %}
5093
5094 ins_encode %{
5095 __ movq($dst$$Register, $mem$$Address);
5096 %}
5097
5098 ins_pipe(ialu_reg_mem); // XXX
5099 %}
5100
5101 // Load Range
5102 instruct loadRange(rRegI dst, memory mem)
5103 %{
5104 match(Set dst (LoadRange mem));
5105
5106 ins_cost(125); // XXX
5107 format %{ "movl $dst, $mem\t# range" %}
5108 opcode(0x8B);
5109 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5110 ins_pipe(ialu_reg_mem);
5111 %}
5112
5113 // Load Pointer
5114 instruct loadP(rRegP dst, memory mem)
5115 %{
5116 match(Set dst (LoadP mem));
5117
5118 ins_cost(125); // XXX
5119 format %{ "movq $dst, $mem\t# ptr" %}
5120 opcode(0x8B);
5121 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5122 ins_pipe(ialu_reg_mem); // XXX
5123 %}
5124
5125 // Load Compressed Pointer
5126 instruct loadN(rRegN dst, memory mem)
5127 %{
5128 match(Set dst (LoadN mem));
5129
5130 ins_cost(125); // XXX
5131 format %{ "movl $dst, $mem\t# compressed ptr" %}
5132 ins_encode %{
5133 __ movl($dst$$Register, $mem$$Address);
5134 %}
5135 ins_pipe(ialu_reg_mem); // XXX
5136 %}
5137
5138
5139 // Load Klass Pointer
5140 instruct loadKlass(rRegP dst, memory mem)
5141 %{
5142 match(Set dst (LoadKlass mem));
5143
5144 ins_cost(125); // XXX
5145 format %{ "movq $dst, $mem\t# class" %}
5146 opcode(0x8B);
5147 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5148 ins_pipe(ialu_reg_mem); // XXX
5149 %}
5150
5151 // Load narrow Klass Pointer
5152 instruct loadNKlass(rRegN dst, memory mem)
5153 %{
5154 match(Set dst (LoadNKlass mem));
5155
5156 ins_cost(125); // XXX
5157 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5158 ins_encode %{
5159 __ movl($dst$$Register, $mem$$Address);
5160 %}
5161 ins_pipe(ialu_reg_mem); // XXX
5162 %}
5163
5164 // Load Float
5165 instruct loadF(regF dst, memory mem)
5166 %{
5167 match(Set dst (LoadF mem));
5168
5169 ins_cost(145); // XXX
5170 format %{ "movss $dst, $mem\t# float" %}
5171 ins_encode %{
5172 __ movflt($dst$$XMMRegister, $mem$$Address);
5173 %}
5174 ins_pipe(pipe_slow); // XXX
5175 %}
5176
5177 // Load Double
5178 instruct loadD_partial(regD dst, memory mem)
5179 %{
5180 predicate(!UseXmmLoadAndClearUpper);
5181 match(Set dst (LoadD mem));
5182
5183 ins_cost(145); // XXX
5184 format %{ "movlpd $dst, $mem\t# double" %}
5185 ins_encode %{
5186 __ movdbl($dst$$XMMRegister, $mem$$Address);
5187 %}
5188 ins_pipe(pipe_slow); // XXX
5189 %}
5190
5191 instruct loadD(regD dst, memory mem)
5192 %{
5193 predicate(UseXmmLoadAndClearUpper);
5194 match(Set dst (LoadD mem));
5195
5196 ins_cost(145); // XXX
5197 format %{ "movsd $dst, $mem\t# double" %}
5198 ins_encode %{
5199 __ movdbl($dst$$XMMRegister, $mem$$Address);
5200 %}
5201 ins_pipe(pipe_slow); // XXX
5202 %}
5203
5204 // Load Effective Address
5205 instruct leaP8(rRegP dst, indOffset8 mem)
5206 %{
5207 match(Set dst mem);
5208
5209 ins_cost(110); // XXX
5210 format %{ "leaq $dst, $mem\t# ptr 8" %}
5211 opcode(0x8D);
5212 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5213 ins_pipe(ialu_reg_reg_fat);
5214 %}
5215
5216 instruct leaP32(rRegP dst, indOffset32 mem)
5217 %{
5218 match(Set dst mem);
5219
5220 ins_cost(110);
5221 format %{ "leaq $dst, $mem\t# ptr 32" %}
5222 opcode(0x8D);
5223 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5224 ins_pipe(ialu_reg_reg_fat);
5225 %}
5226
5227 // instruct leaPIdx(rRegP dst, indIndex mem)
5228 // %{
5229 // match(Set dst mem);
5230
5231 // ins_cost(110);
5232 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5233 // opcode(0x8D);
5234 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5235 // ins_pipe(ialu_reg_reg_fat);
5236 // %}
5237
5238 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5239 %{
5240 match(Set dst mem);
5241
5242 ins_cost(110);
5243 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5244 opcode(0x8D);
5245 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5246 ins_pipe(ialu_reg_reg_fat);
5247 %}
5248
5249 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5250 %{
5251 match(Set dst mem);
5252
5253 ins_cost(110);
5254 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5255 opcode(0x8D);
5256 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5257 ins_pipe(ialu_reg_reg_fat);
5258 %}
5259
5260 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5261 %{
5262 match(Set dst mem);
5263
5264 ins_cost(110);
5265 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5266 opcode(0x8D);
5267 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5268 ins_pipe(ialu_reg_reg_fat);
5269 %}
5270
5271 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5272 %{
5273 match(Set dst mem);
5274
5275 ins_cost(110);
5276 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5277 opcode(0x8D);
5278 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5279 ins_pipe(ialu_reg_reg_fat);
5280 %}
5281
5282 // Load Effective Address which uses Narrow (32-bits) oop
5283 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5284 %{
5285 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5286 match(Set dst mem);
5287
5288 ins_cost(110);
5289 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5290 opcode(0x8D);
5291 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5292 ins_pipe(ialu_reg_reg_fat);
5293 %}
5294
5295 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5296 %{
5297 predicate(Universe::narrow_oop_shift() == 0);
5298 match(Set dst mem);
5299
5300 ins_cost(110); // XXX
5301 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5302 opcode(0x8D);
5303 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5304 ins_pipe(ialu_reg_reg_fat);
5305 %}
5306
5307 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5308 %{
5309 predicate(Universe::narrow_oop_shift() == 0);
5310 match(Set dst mem);
5311
5312 ins_cost(110);
5313 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5314 opcode(0x8D);
5315 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5316 ins_pipe(ialu_reg_reg_fat);
5317 %}
5318
5319 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5320 %{
5321 predicate(Universe::narrow_oop_shift() == 0);
5322 match(Set dst mem);
5323
5324 ins_cost(110);
5325 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5326 opcode(0x8D);
5327 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5328 ins_pipe(ialu_reg_reg_fat);
5329 %}
5330
5331 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5332 %{
5333 predicate(Universe::narrow_oop_shift() == 0);
5334 match(Set dst mem);
5335
5336 ins_cost(110);
5337 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5338 opcode(0x8D);
5339 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5340 ins_pipe(ialu_reg_reg_fat);
5341 %}
5342
5343 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5344 %{
5345 predicate(Universe::narrow_oop_shift() == 0);
5346 match(Set dst mem);
5347
5348 ins_cost(110);
5349 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5350 opcode(0x8D);
5351 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5352 ins_pipe(ialu_reg_reg_fat);
5353 %}
5354
5355 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5356 %{
5357 predicate(Universe::narrow_oop_shift() == 0);
5358 match(Set dst mem);
5359
5360 ins_cost(110);
5361 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5362 opcode(0x8D);
5363 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5364 ins_pipe(ialu_reg_reg_fat);
5365 %}
5366
5367 instruct loadConI(rRegI dst, immI src)
5368 %{
5369 match(Set dst src);
5370
5371 format %{ "movl $dst, $src\t# int" %}
5372 ins_encode(load_immI(dst, src));
5373 ins_pipe(ialu_reg_fat); // XXX
5374 %}
5375
5376 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5377 %{
5378 match(Set dst src);
5379 effect(KILL cr);
5380
5381 ins_cost(50);
5382 format %{ "xorl $dst, $dst\t# int" %}
5383 opcode(0x33); /* + rd */
5384 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5385 ins_pipe(ialu_reg);
5386 %}
5387
5388 instruct loadConL(rRegL dst, immL src)
5389 %{
5390 match(Set dst src);
5391
5392 ins_cost(150);
5393 format %{ "movq $dst, $src\t# long" %}
5394 ins_encode(load_immL(dst, src));
5395 ins_pipe(ialu_reg);
5396 %}
5397
5398 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5399 %{
5400 match(Set dst src);
5401 effect(KILL cr);
5402
5403 ins_cost(50);
5404 format %{ "xorl $dst, $dst\t# long" %}
5405 opcode(0x33); /* + rd */
5406 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5407 ins_pipe(ialu_reg); // XXX
5408 %}
5409
5410 instruct loadConUL32(rRegL dst, immUL32 src)
5411 %{
5412 match(Set dst src);
5413
5414 ins_cost(60);
5415 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5416 ins_encode(load_immUL32(dst, src));
5417 ins_pipe(ialu_reg);
5418 %}
5419
5420 instruct loadConL32(rRegL dst, immL32 src)
5421 %{
5422 match(Set dst src);
5423
5424 ins_cost(70);
5425 format %{ "movq $dst, $src\t# long (32-bit)" %}
5426 ins_encode(load_immL32(dst, src));
5427 ins_pipe(ialu_reg);
5428 %}
5429
5430 instruct loadConP(rRegP dst, immP con) %{
5431 match(Set dst con);
5432
5433 format %{ "movq $dst, $con\t# ptr" %}
5434 ins_encode(load_immP(dst, con));
5435 ins_pipe(ialu_reg_fat); // XXX
5436 %}
5437
5438 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5439 %{
5440 match(Set dst src);
5441 effect(KILL cr);
5442
5443 ins_cost(50);
5444 format %{ "xorl $dst, $dst\t# ptr" %}
5445 opcode(0x33); /* + rd */
5446 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5447 ins_pipe(ialu_reg);
5448 %}
5449
5450 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5451 %{
5452 match(Set dst src);
5453 effect(KILL cr);
5454
5455 ins_cost(60);
5456 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5457 ins_encode(load_immP31(dst, src));
5458 ins_pipe(ialu_reg);
5459 %}
5460
5461 instruct loadConF(regF dst, immF con) %{
5462 match(Set dst con);
5463 ins_cost(125);
5464 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5465 ins_encode %{
5466 __ movflt($dst$$XMMRegister, $constantaddress($con));
5467 %}
5468 ins_pipe(pipe_slow);
5469 %}
5470
5471 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5472 match(Set dst src);
5473 effect(KILL cr);
5474 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5475 ins_encode %{
5476 __ xorq($dst$$Register, $dst$$Register);
5477 %}
5478 ins_pipe(ialu_reg);
5479 %}
5480
5481 instruct loadConN(rRegN dst, immN src) %{
5482 match(Set dst src);
5483
5484 ins_cost(125);
5485 format %{ "movl $dst, $src\t# compressed ptr" %}
5486 ins_encode %{
5487 address con = (address)$src$$constant;
5488 if (con == NULL) {
5489 ShouldNotReachHere();
5490 } else {
5491 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5492 }
5493 %}
5494 ins_pipe(ialu_reg_fat); // XXX
5495 %}
5496
5497 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5498 match(Set dst src);
5499
5500 ins_cost(125);
5501 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5502 ins_encode %{
5503 address con = (address)$src$$constant;
5504 if (con == NULL) {
5505 ShouldNotReachHere();
5506 } else {
5507 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5508 }
5509 %}
5510 ins_pipe(ialu_reg_fat); // XXX
5511 %}
5512
5513 instruct loadConF0(regF dst, immF0 src)
5514 %{
5515 match(Set dst src);
5516 ins_cost(100);
5517
5518 format %{ "xorps $dst, $dst\t# float 0.0" %}
5519 ins_encode %{
5520 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5521 %}
5522 ins_pipe(pipe_slow);
5523 %}
5524
5525 // Use the same format since predicate() can not be used here.
5526 instruct loadConD(regD dst, immD con) %{
5527 match(Set dst con);
5528 ins_cost(125);
5529 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5530 ins_encode %{
5531 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5532 %}
5533 ins_pipe(pipe_slow);
5534 %}
5535
5536 instruct loadConD0(regD dst, immD0 src)
5537 %{
5538 match(Set dst src);
5539 ins_cost(100);
5540
5541 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5542 ins_encode %{
5543 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5544 %}
5545 ins_pipe(pipe_slow);
5546 %}
5547
5548 instruct loadSSI(rRegI dst, stackSlotI src)
5549 %{
5550 match(Set dst src);
5551
5552 ins_cost(125);
5553 format %{ "movl $dst, $src\t# int stk" %}
5554 opcode(0x8B);
5555 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5556 ins_pipe(ialu_reg_mem);
5557 %}
5558
5559 instruct loadSSL(rRegL dst, stackSlotL src)
5560 %{
5561 match(Set dst src);
5562
5563 ins_cost(125);
5564 format %{ "movq $dst, $src\t# long stk" %}
5565 opcode(0x8B);
5566 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5567 ins_pipe(ialu_reg_mem);
5568 %}
5569
5570 instruct loadSSP(rRegP dst, stackSlotP src)
5571 %{
5572 match(Set dst src);
5573
5574 ins_cost(125);
5575 format %{ "movq $dst, $src\t# ptr stk" %}
5576 opcode(0x8B);
5577 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5578 ins_pipe(ialu_reg_mem);
5579 %}
5580
5581 instruct loadSSF(regF dst, stackSlotF src)
5582 %{
5583 match(Set dst src);
5584
5585 ins_cost(125);
5586 format %{ "movss $dst, $src\t# float stk" %}
5587 ins_encode %{
5588 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5589 %}
5590 ins_pipe(pipe_slow); // XXX
5591 %}
5592
5593 // Use the same format since predicate() can not be used here.
5594 instruct loadSSD(regD dst, stackSlotD src)
5595 %{
5596 match(Set dst src);
5597
5598 ins_cost(125);
5599 format %{ "movsd $dst, $src\t# double stk" %}
5600 ins_encode %{
5601 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5602 %}
5603 ins_pipe(pipe_slow); // XXX
5604 %}
5605
5606 // Prefetch instructions.
5607 // Must be safe to execute with invalid address (cannot fault).
5608
5609 instruct prefetchr( memory mem ) %{
5610 predicate(ReadPrefetchInstr==3);
5611 match(PrefetchRead mem);
5612 ins_cost(125);
5613
5614 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5615 ins_encode %{
5616 __ prefetchr($mem$$Address);
5617 %}
5618 ins_pipe(ialu_mem);
5619 %}
5620
5621 instruct prefetchrNTA( memory mem ) %{
5622 predicate(ReadPrefetchInstr==0);
5623 match(PrefetchRead mem);
5624 ins_cost(125);
5625
5626 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5627 ins_encode %{
5628 __ prefetchnta($mem$$Address);
5629 %}
5630 ins_pipe(ialu_mem);
5631 %}
5632
5633 instruct prefetchrT0( memory mem ) %{
5634 predicate(ReadPrefetchInstr==1);
5635 match(PrefetchRead mem);
5636 ins_cost(125);
5637
5638 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5639 ins_encode %{
5640 __ prefetcht0($mem$$Address);
5641 %}
5642 ins_pipe(ialu_mem);
5643 %}
5644
5645 instruct prefetchrT2( memory mem ) %{
5646 predicate(ReadPrefetchInstr==2);
5647 match(PrefetchRead mem);
5648 ins_cost(125);
5649
5650 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5651 ins_encode %{
5652 __ prefetcht2($mem$$Address);
5653 %}
5654 ins_pipe(ialu_mem);
5655 %}
5656
5657 instruct prefetchwNTA( memory mem ) %{
5658 match(PrefetchWrite mem);
5659 ins_cost(125);
5660
5661 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5662 ins_encode %{
5663 __ prefetchnta($mem$$Address);
5664 %}
5665 ins_pipe(ialu_mem);
5666 %}
5667
5668 // Prefetch instructions for allocation.
5669
5670 instruct prefetchAlloc( memory mem ) %{
5671 predicate(AllocatePrefetchInstr==3);
5672 match(PrefetchAllocation mem);
5673 ins_cost(125);
5674
5675 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5676 ins_encode %{
5677 __ prefetchw($mem$$Address);
5678 %}
5679 ins_pipe(ialu_mem);
5680 %}
5681
5682 instruct prefetchAllocNTA( memory mem ) %{
5683 predicate(AllocatePrefetchInstr==0);
5684 match(PrefetchAllocation mem);
5685 ins_cost(125);
5686
5687 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5688 ins_encode %{
5689 __ prefetchnta($mem$$Address);
5690 %}
5691 ins_pipe(ialu_mem);
5692 %}
5693
5694 instruct prefetchAllocT0( memory mem ) %{
5695 predicate(AllocatePrefetchInstr==1);
5696 match(PrefetchAllocation mem);
5697 ins_cost(125);
5698
5699 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5700 ins_encode %{
5701 __ prefetcht0($mem$$Address);
5702 %}
5703 ins_pipe(ialu_mem);
5704 %}
5705
5706 instruct prefetchAllocT2( memory mem ) %{
5707 predicate(AllocatePrefetchInstr==2);
5708 match(PrefetchAllocation mem);
5709 ins_cost(125);
5710
5711 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5712 ins_encode %{
5713 __ prefetcht2($mem$$Address);
5714 %}
5715 ins_pipe(ialu_mem);
5716 %}
5717
5718 //----------Store Instructions-------------------------------------------------
5719
5720 // Store Byte
5721 instruct storeB(memory mem, rRegI src)
5722 %{
5723 match(Set mem (StoreB mem src));
5724
5725 ins_cost(125); // XXX
5726 format %{ "movb $mem, $src\t# byte" %}
5727 opcode(0x88);
5728 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5729 ins_pipe(ialu_mem_reg);
5730 %}
5731
5732 // Store Char/Short
5733 instruct storeC(memory mem, rRegI src)
5734 %{
5735 match(Set mem (StoreC mem src));
5736
5737 ins_cost(125); // XXX
5738 format %{ "movw $mem, $src\t# char/short" %}
5739 opcode(0x89);
5740 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5741 ins_pipe(ialu_mem_reg);
5742 %}
5743
5744 // Store Integer
5745 instruct storeI(memory mem, rRegI src)
5746 %{
5747 match(Set mem (StoreI mem src));
5748
5749 ins_cost(125); // XXX
5750 format %{ "movl $mem, $src\t# int" %}
5751 opcode(0x89);
5752 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5753 ins_pipe(ialu_mem_reg);
5754 %}
5755
5756 // Store Long
5757 instruct storeL(memory mem, rRegL src)
5758 %{
5759 match(Set mem (StoreL mem src));
5760
5761 ins_cost(125); // XXX
5762 format %{ "movq $mem, $src\t# long" %}
5763 opcode(0x89);
5764 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5765 ins_pipe(ialu_mem_reg); // XXX
5766 %}
5767
5768 // Store Pointer
5769 instruct storeP(memory mem, any_RegP src)
5770 %{
5771 match(Set mem (StoreP mem src));
5772
5773 ins_cost(125); // XXX
5774 format %{ "movq $mem, $src\t# ptr" %}
5775 opcode(0x89);
5776 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5777 ins_pipe(ialu_mem_reg);
5778 %}
5779
5780 instruct storeImmP0(memory mem, immP0 zero)
5781 %{
5782 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5783 match(Set mem (StoreP mem zero));
5784
5785 ins_cost(125); // XXX
5786 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5787 ins_encode %{
5788 __ movq($mem$$Address, r12);
5789 %}
5790 ins_pipe(ialu_mem_reg);
5791 %}
5792
5793 // Store NULL Pointer, mark word, or other simple pointer constant.
5794 instruct storeImmP(memory mem, immP31 src)
5795 %{
5796 match(Set mem (StoreP mem src));
5797
5798 ins_cost(150); // XXX
5799 format %{ "movq $mem, $src\t# ptr" %}
5800 opcode(0xC7); /* C7 /0 */
5801 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5802 ins_pipe(ialu_mem_imm);
5803 %}
5804
5805 // Store Compressed Pointer
5806 instruct storeN(memory mem, rRegN src)
5807 %{
5808 match(Set mem (StoreN mem src));
5809
5810 ins_cost(125); // XXX
5811 format %{ "movl $mem, $src\t# compressed ptr" %}
5812 ins_encode %{
5813 __ movl($mem$$Address, $src$$Register);
5814 %}
5815 ins_pipe(ialu_mem_reg);
5816 %}
5817
5818 instruct storeNKlass(memory mem, rRegN src)
5819 %{
5820 match(Set mem (StoreNKlass mem src));
5821
5822 ins_cost(125); // XXX
5823 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5824 ins_encode %{
5825 __ movl($mem$$Address, $src$$Register);
5826 %}
5827 ins_pipe(ialu_mem_reg);
5828 %}
5829
5830 instruct storeImmN0(memory mem, immN0 zero)
5831 %{
5832 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5833 match(Set mem (StoreN mem zero));
5834
5835 ins_cost(125); // XXX
5836 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5837 ins_encode %{
5838 __ movl($mem$$Address, r12);
5839 %}
5840 ins_pipe(ialu_mem_reg);
5841 %}
5842
5843 instruct storeImmN(memory mem, immN src)
5844 %{
5845 match(Set mem (StoreN mem src));
5846
5847 ins_cost(150); // XXX
5848 format %{ "movl $mem, $src\t# compressed ptr" %}
5849 ins_encode %{
5850 address con = (address)$src$$constant;
5851 if (con == NULL) {
5852 __ movl($mem$$Address, (int32_t)0);
5853 } else {
5854 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5855 }
5856 %}
5857 ins_pipe(ialu_mem_imm);
5858 %}
5859
5860 instruct storeImmNKlass(memory mem, immNKlass src)
5861 %{
5862 match(Set mem (StoreNKlass mem src));
5863
5864 ins_cost(150); // XXX
5865 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5866 ins_encode %{
5867 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5868 %}
5869 ins_pipe(ialu_mem_imm);
5870 %}
5871
5872 // Store Integer Immediate
5873 instruct storeImmI0(memory mem, immI0 zero)
5874 %{
5875 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5876 match(Set mem (StoreI mem zero));
5877
5878 ins_cost(125); // XXX
5879 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5880 ins_encode %{
5881 __ movl($mem$$Address, r12);
5882 %}
5883 ins_pipe(ialu_mem_reg);
5884 %}
5885
5886 instruct storeImmI(memory mem, immI src)
5887 %{
5888 match(Set mem (StoreI mem src));
5889
5890 ins_cost(150);
5891 format %{ "movl $mem, $src\t# int" %}
5892 opcode(0xC7); /* C7 /0 */
5893 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5894 ins_pipe(ialu_mem_imm);
5895 %}
5896
5897 // Store Long Immediate
5898 instruct storeImmL0(memory mem, immL0 zero)
5899 %{
5900 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5901 match(Set mem (StoreL mem zero));
5902
5903 ins_cost(125); // XXX
5904 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5905 ins_encode %{
5906 __ movq($mem$$Address, r12);
5907 %}
5908 ins_pipe(ialu_mem_reg);
5909 %}
5910
5911 instruct storeImmL(memory mem, immL32 src)
5912 %{
5913 match(Set mem (StoreL mem src));
5914
5915 ins_cost(150);
5916 format %{ "movq $mem, $src\t# long" %}
5917 opcode(0xC7); /* C7 /0 */
5918 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5919 ins_pipe(ialu_mem_imm);
5920 %}
5921
5922 // Store Short/Char Immediate
5923 instruct storeImmC0(memory mem, immI0 zero)
5924 %{
5925 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5926 match(Set mem (StoreC mem zero));
5927
5928 ins_cost(125); // XXX
5929 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5930 ins_encode %{
5931 __ movw($mem$$Address, r12);
5932 %}
5933 ins_pipe(ialu_mem_reg);
5934 %}
5935
5936 instruct storeImmI16(memory mem, immI16 src)
5937 %{
5938 predicate(UseStoreImmI16);
5939 match(Set mem (StoreC mem src));
5940
5941 ins_cost(150);
5942 format %{ "movw $mem, $src\t# short/char" %}
5943 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5944 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5945 ins_pipe(ialu_mem_imm);
5946 %}
5947
5948 // Store Byte Immediate
5949 instruct storeImmB0(memory mem, immI0 zero)
5950 %{
5951 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5952 match(Set mem (StoreB mem zero));
5953
5954 ins_cost(125); // XXX
5955 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5956 ins_encode %{
5957 __ movb($mem$$Address, r12);
5958 %}
5959 ins_pipe(ialu_mem_reg);
5960 %}
5961
5962 instruct storeImmB(memory mem, immI8 src)
5963 %{
5964 match(Set mem (StoreB mem src));
5965
5966 ins_cost(150); // XXX
5967 format %{ "movb $mem, $src\t# byte" %}
5968 opcode(0xC6); /* C6 /0 */
5969 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5970 ins_pipe(ialu_mem_imm);
5971 %}
5972
5973 // Store CMS card-mark Immediate
5974 instruct storeImmCM0_reg(memory mem, immI0 zero)
5975 %{
5976 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5977 match(Set mem (StoreCM mem zero));
5978
5979 ins_cost(125); // XXX
5980 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5981 ins_encode %{
5982 __ movb($mem$$Address, r12);
5983 %}
5984 ins_pipe(ialu_mem_reg);
5985 %}
5986
5987 instruct storeImmCM0(memory mem, immI0 src)
5988 %{
5989 match(Set mem (StoreCM mem src));
5990
5991 ins_cost(150); // XXX
5992 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5993 opcode(0xC6); /* C6 /0 */
5994 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5995 ins_pipe(ialu_mem_imm);
5996 %}
5997
5998 // Store Float
5999 instruct storeF(memory mem, regF src)
6000 %{
6001 match(Set mem (StoreF mem src));
6002
6003 ins_cost(95); // XXX
6004 format %{ "movss $mem, $src\t# float" %}
6005 ins_encode %{
6006 __ movflt($mem$$Address, $src$$XMMRegister);
6007 %}
6008 ins_pipe(pipe_slow); // XXX
6009 %}
6010
6011 // Store immediate Float value (it is faster than store from XMM register)
6012 instruct storeF0(memory mem, immF0 zero)
6013 %{
6014 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6015 match(Set mem (StoreF mem zero));
6016
6017 ins_cost(25); // XXX
6018 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6019 ins_encode %{
6020 __ movl($mem$$Address, r12);
6021 %}
6022 ins_pipe(ialu_mem_reg);
6023 %}
6024
6025 instruct storeF_imm(memory mem, immF src)
6026 %{
6027 match(Set mem (StoreF mem src));
6028
6029 ins_cost(50);
6030 format %{ "movl $mem, $src\t# float" %}
6031 opcode(0xC7); /* C7 /0 */
6032 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6033 ins_pipe(ialu_mem_imm);
6034 %}
6035
6036 // Store Double
6037 instruct storeD(memory mem, regD src)
6038 %{
6039 match(Set mem (StoreD mem src));
6040
6041 ins_cost(95); // XXX
6042 format %{ "movsd $mem, $src\t# double" %}
6043 ins_encode %{
6044 __ movdbl($mem$$Address, $src$$XMMRegister);
6045 %}
6046 ins_pipe(pipe_slow); // XXX
6047 %}
6048
6049 // Store immediate double 0.0 (it is faster than store from XMM register)
6050 instruct storeD0_imm(memory mem, immD0 src)
6051 %{
6052 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6053 match(Set mem (StoreD mem src));
6054
6055 ins_cost(50);
6056 format %{ "movq $mem, $src\t# double 0." %}
6057 opcode(0xC7); /* C7 /0 */
6058 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6059 ins_pipe(ialu_mem_imm);
6060 %}
6061
6062 instruct storeD0(memory mem, immD0 zero)
6063 %{
6064 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6065 match(Set mem (StoreD mem zero));
6066
6067 ins_cost(25); // XXX
6068 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6069 ins_encode %{
6070 __ movq($mem$$Address, r12);
6071 %}
6072 ins_pipe(ialu_mem_reg);
6073 %}
6074
6075 instruct storeSSI(stackSlotI dst, rRegI src)
6076 %{
6077 match(Set dst src);
6078
6079 ins_cost(100);
6080 format %{ "movl $dst, $src\t# int stk" %}
6081 opcode(0x89);
6082 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6083 ins_pipe( ialu_mem_reg );
6084 %}
6085
6086 instruct storeSSL(stackSlotL dst, rRegL src)
6087 %{
6088 match(Set dst src);
6089
6090 ins_cost(100);
6091 format %{ "movq $dst, $src\t# long stk" %}
6092 opcode(0x89);
6093 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6094 ins_pipe(ialu_mem_reg);
6095 %}
6096
6097 instruct storeSSP(stackSlotP dst, rRegP src)
6098 %{
6099 match(Set dst src);
6100
6101 ins_cost(100);
6102 format %{ "movq $dst, $src\t# ptr stk" %}
6103 opcode(0x89);
6104 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6105 ins_pipe(ialu_mem_reg);
6106 %}
6107
6108 instruct storeSSF(stackSlotF dst, regF src)
6109 %{
6110 match(Set dst src);
6111
6112 ins_cost(95); // XXX
6113 format %{ "movss $dst, $src\t# float stk" %}
6114 ins_encode %{
6115 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6116 %}
6117 ins_pipe(pipe_slow); // XXX
6118 %}
6119
6120 instruct storeSSD(stackSlotD dst, regD src)
6121 %{
6122 match(Set dst src);
6123
6124 ins_cost(95); // XXX
6125 format %{ "movsd $dst, $src\t# double stk" %}
6126 ins_encode %{
6127 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6128 %}
6129 ins_pipe(pipe_slow); // XXX
6130 %}
6131
6132 //----------BSWAP Instructions-------------------------------------------------
6133 instruct bytes_reverse_int(rRegI dst) %{
6134 match(Set dst (ReverseBytesI dst));
6135
6136 format %{ "bswapl $dst" %}
6137 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6138 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6139 ins_pipe( ialu_reg );
6140 %}
6141
6142 instruct bytes_reverse_long(rRegL dst) %{
6143 match(Set dst (ReverseBytesL dst));
6144
6145 format %{ "bswapq $dst" %}
6146 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6147 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6148 ins_pipe( ialu_reg);
6149 %}
6150
6151 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6152 match(Set dst (ReverseBytesUS dst));
6153 effect(KILL cr);
6154
6155 format %{ "bswapl $dst\n\t"
6156 "shrl $dst,16\n\t" %}
6157 ins_encode %{
6158 __ bswapl($dst$$Register);
6159 __ shrl($dst$$Register, 16);
6160 %}
6161 ins_pipe( ialu_reg );
6162 %}
6163
6164 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6165 match(Set dst (ReverseBytesS dst));
6166 effect(KILL cr);
6167
6168 format %{ "bswapl $dst\n\t"
6169 "sar $dst,16\n\t" %}
6170 ins_encode %{
6171 __ bswapl($dst$$Register);
6172 __ sarl($dst$$Register, 16);
6173 %}
6174 ins_pipe( ialu_reg );
6175 %}
6176
6177 //---------- Zeros Count Instructions ------------------------------------------
6178
6179 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6180 predicate(UseCountLeadingZerosInstruction);
6181 match(Set dst (CountLeadingZerosI src));
6182 effect(KILL cr);
6183
6184 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6185 ins_encode %{
6186 __ lzcntl($dst$$Register, $src$$Register);
6187 %}
6188 ins_pipe(ialu_reg);
6189 %}
6190
6191 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6192 predicate(!UseCountLeadingZerosInstruction);
6193 match(Set dst (CountLeadingZerosI src));
6194 effect(KILL cr);
6195
6196 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6197 "jnz skip\n\t"
6198 "movl $dst, -1\n"
6199 "skip:\n\t"
6200 "negl $dst\n\t"
6201 "addl $dst, 31" %}
6202 ins_encode %{
6203 Register Rdst = $dst$$Register;
6204 Register Rsrc = $src$$Register;
6205 Label skip;
6206 __ bsrl(Rdst, Rsrc);
6207 __ jccb(Assembler::notZero, skip);
6208 __ movl(Rdst, -1);
6209 __ bind(skip);
6210 __ negl(Rdst);
6211 __ addl(Rdst, BitsPerInt - 1);
6212 %}
6213 ins_pipe(ialu_reg);
6214 %}
6215
6216 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6217 predicate(UseCountLeadingZerosInstruction);
6218 match(Set dst (CountLeadingZerosL src));
6219 effect(KILL cr);
6220
6221 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6222 ins_encode %{
6223 __ lzcntq($dst$$Register, $src$$Register);
6224 %}
6225 ins_pipe(ialu_reg);
6226 %}
6227
6228 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6229 predicate(!UseCountLeadingZerosInstruction);
6230 match(Set dst (CountLeadingZerosL src));
6231 effect(KILL cr);
6232
6233 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6234 "jnz skip\n\t"
6235 "movl $dst, -1\n"
6236 "skip:\n\t"
6237 "negl $dst\n\t"
6238 "addl $dst, 63" %}
6239 ins_encode %{
6240 Register Rdst = $dst$$Register;
6241 Register Rsrc = $src$$Register;
6242 Label skip;
6243 __ bsrq(Rdst, Rsrc);
6244 __ jccb(Assembler::notZero, skip);
6245 __ movl(Rdst, -1);
6246 __ bind(skip);
6247 __ negl(Rdst);
6248 __ addl(Rdst, BitsPerLong - 1);
6249 %}
6250 ins_pipe(ialu_reg);
6251 %}
6252
6253 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6254 match(Set dst (CountTrailingZerosI src));
6255 effect(KILL cr);
6256
6257 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6258 "jnz done\n\t"
6259 "movl $dst, 32\n"
6260 "done:" %}
6261 ins_encode %{
6262 Register Rdst = $dst$$Register;
6263 Label done;
6264 __ bsfl(Rdst, $src$$Register);
6265 __ jccb(Assembler::notZero, done);
6266 __ movl(Rdst, BitsPerInt);
6267 __ bind(done);
6268 %}
6269 ins_pipe(ialu_reg);
6270 %}
6271
6272 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6273 match(Set dst (CountTrailingZerosL src));
6274 effect(KILL cr);
6275
6276 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6277 "jnz done\n\t"
6278 "movl $dst, 64\n"
6279 "done:" %}
6280 ins_encode %{
6281 Register Rdst = $dst$$Register;
6282 Label done;
6283 __ bsfq(Rdst, $src$$Register);
6284 __ jccb(Assembler::notZero, done);
6285 __ movl(Rdst, BitsPerLong);
6286 __ bind(done);
6287 %}
6288 ins_pipe(ialu_reg);
6289 %}
6290
6291
6292 //---------- Population Count Instructions -------------------------------------
6293
6294 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6295 predicate(UsePopCountInstruction);
6296 match(Set dst (PopCountI src));
6297 effect(KILL cr);
6298
6299 format %{ "popcnt $dst, $src" %}
6300 ins_encode %{
6301 __ popcntl($dst$$Register, $src$$Register);
6302 %}
6303 ins_pipe(ialu_reg);
6304 %}
6305
6306 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6307 predicate(UsePopCountInstruction);
6308 match(Set dst (PopCountI (LoadI mem)));
6309 effect(KILL cr);
6310
6311 format %{ "popcnt $dst, $mem" %}
6312 ins_encode %{
6313 __ popcntl($dst$$Register, $mem$$Address);
6314 %}
6315 ins_pipe(ialu_reg);
6316 %}
6317
6318 // Note: Long.bitCount(long) returns an int.
6319 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6320 predicate(UsePopCountInstruction);
6321 match(Set dst (PopCountL src));
6322 effect(KILL cr);
6323
6324 format %{ "popcnt $dst, $src" %}
6325 ins_encode %{
6326 __ popcntq($dst$$Register, $src$$Register);
6327 %}
6328 ins_pipe(ialu_reg);
6329 %}
6330
6331 // Note: Long.bitCount(long) returns an int.
6332 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6333 predicate(UsePopCountInstruction);
6334 match(Set dst (PopCountL (LoadL mem)));
6335 effect(KILL cr);
6336
6337 format %{ "popcnt $dst, $mem" %}
6338 ins_encode %{
6339 __ popcntq($dst$$Register, $mem$$Address);
6340 %}
6341 ins_pipe(ialu_reg);
6342 %}
6343
6344
6345 //----------MemBar Instructions-----------------------------------------------
6346 // Memory barrier flavors
6347
6348 instruct membar_acquire()
6349 %{
6350 match(MemBarAcquire);
6351 ins_cost(0);
6352
6353 size(0);
6354 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6355 ins_encode();
6356 ins_pipe(empty);
6357 %}
6358
6359 instruct membar_acquire_lock()
6360 %{
6361 match(MemBarAcquireLock);
6362 ins_cost(0);
6363
6364 size(0);
6365 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6366 ins_encode();
6367 ins_pipe(empty);
6368 %}
6369
6370 instruct membar_release()
6371 %{
6372 match(MemBarRelease);
6373 ins_cost(0);
6374
6375 size(0);
6376 format %{ "MEMBAR-release ! (empty encoding)" %}
6377 ins_encode();
6378 ins_pipe(empty);
6379 %}
6380
6381 instruct membar_release_lock()
6382 %{
6383 match(MemBarReleaseLock);
6384 ins_cost(0);
6385
6386 size(0);
6387 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6388 ins_encode();
6389 ins_pipe(empty);
6390 %}
6391
6392 instruct membar_volatile(rFlagsReg cr) %{
6393 match(MemBarVolatile);
6394 effect(KILL cr);
6395 ins_cost(400);
6396
6397 format %{
6398 $$template
6399 if (os::is_MP()) {
6400 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6401 } else {
6402 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6403 }
6404 %}
6405 ins_encode %{
6406 __ membar(Assembler::StoreLoad);
6407 %}
6408 ins_pipe(pipe_slow);
6409 %}
6410
6411 instruct unnecessary_membar_volatile()
6412 %{
6413 match(MemBarVolatile);
6414 predicate(Matcher::post_store_load_barrier(n));
6415 ins_cost(0);
6416
6417 size(0);
6418 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6419 ins_encode();
6420 ins_pipe(empty);
6421 %}
6422
6423 instruct membar_storestore() %{
6424 match(MemBarStoreStore);
6425 ins_cost(0);
6426
6427 size(0);
6428 format %{ "MEMBAR-storestore (empty encoding)" %}
6429 ins_encode( );
6430 ins_pipe(empty);
6431 %}
6432
6433 //----------Move Instructions--------------------------------------------------
6434
6435 instruct castX2P(rRegP dst, rRegL src)
6436 %{
6437 match(Set dst (CastX2P src));
6438
6439 format %{ "movq $dst, $src\t# long->ptr" %}
6440 ins_encode %{
6441 if ($dst$$reg != $src$$reg) {
6442 __ movptr($dst$$Register, $src$$Register);
6443 }
6444 %}
6445 ins_pipe(ialu_reg_reg); // XXX
6446 %}
6447
6448 instruct castP2X(rRegL dst, rRegP src)
6449 %{
6450 match(Set dst (CastP2X src));
6451
6452 format %{ "movq $dst, $src\t# ptr -> long" %}
6453 ins_encode %{
6454 if ($dst$$reg != $src$$reg) {
6455 __ movptr($dst$$Register, $src$$Register);
6456 }
6457 %}
6458 ins_pipe(ialu_reg_reg); // XXX
6459 %}
6460
6461 // Convert oop into int for vectors alignment masking
6462 instruct convP2I(rRegI dst, rRegP src)
6463 %{
6464 match(Set dst (ConvL2I (CastP2X src)));
6465
6466 format %{ "movl $dst, $src\t# ptr -> int" %}
6467 ins_encode %{
6468 __ movl($dst$$Register, $src$$Register);
6469 %}
6470 ins_pipe(ialu_reg_reg); // XXX
6471 %}
6472
6473 // Convert compressed oop into int for vectors alignment masking
6474 // in case of 32bit oops (heap < 4Gb).
6475 instruct convN2I(rRegI dst, rRegN src)
6476 %{
6477 predicate(Universe::narrow_oop_shift() == 0);
6478 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6479
6480 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6481 ins_encode %{
6482 __ movl($dst$$Register, $src$$Register);
6483 %}
6484 ins_pipe(ialu_reg_reg); // XXX
6485 %}
6486
6487 // Convert oop pointer into compressed form
6488 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6489 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6490 match(Set dst (EncodeP src));
6491 effect(KILL cr);
6492 format %{ "encode_heap_oop $dst,$src" %}
6493 ins_encode %{
6494 Register s = $src$$Register;
6495 Register d = $dst$$Register;
6496 if (s != d) {
6497 __ movq(d, s);
6498 }
6499 __ encode_heap_oop(d);
6500 %}
6501 ins_pipe(ialu_reg_long);
6502 %}
6503
6504 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6505 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6506 match(Set dst (EncodeP src));
6507 effect(KILL cr);
6508 format %{ "encode_heap_oop_not_null $dst,$src" %}
6509 ins_encode %{
6510 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6511 %}
6512 ins_pipe(ialu_reg_long);
6513 %}
6514
6515 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6516 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6517 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6518 match(Set dst (DecodeN src));
6519 effect(KILL cr);
6520 format %{ "decode_heap_oop $dst,$src" %}
6521 ins_encode %{
6522 Register s = $src$$Register;
6523 Register d = $dst$$Register;
6524 if (s != d) {
6525 __ movq(d, s);
6526 }
6527 __ decode_heap_oop(d);
6528 %}
6529 ins_pipe(ialu_reg_long);
6530 %}
6531
6532 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6533 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6534 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6535 match(Set dst (DecodeN src));
6536 effect(KILL cr);
6537 format %{ "decode_heap_oop_not_null $dst,$src" %}
6538 ins_encode %{
6539 Register s = $src$$Register;
6540 Register d = $dst$$Register;
6541 if (s != d) {
6542 __ decode_heap_oop_not_null(d, s);
6543 } else {
6544 __ decode_heap_oop_not_null(d);
6545 }
6546 %}
6547 ins_pipe(ialu_reg_long);
6548 %}
6549
6550 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6551 match(Set dst (EncodePKlass src));
6552 effect(KILL cr);
6553 format %{ "encode_klass_not_null $dst,$src" %}
6554 ins_encode %{
6555 __ encode_klass_not_null($dst$$Register, $src$$Register);
6556 %}
6557 ins_pipe(ialu_reg_long);
6558 %}
6559
6560 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6561 match(Set dst (DecodeNKlass src));
6562 effect(KILL cr);
6563 format %{ "decode_klass_not_null $dst,$src" %}
6564 ins_encode %{
6565 Register s = $src$$Register;
6566 Register d = $dst$$Register;
6567 if (s != d) {
6568 __ decode_klass_not_null(d, s);
6569 } else {
6570 __ decode_klass_not_null(d);
6571 }
6572 %}
6573 ins_pipe(ialu_reg_long);
6574 %}
6575
6576
6577 //----------Conditional Move---------------------------------------------------
6578 // Jump
6579 // dummy instruction for generating temp registers
6580 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6581 match(Jump (LShiftL switch_val shift));
6582 ins_cost(350);
6583 predicate(false);
6584 effect(TEMP dest);
6585
6586 format %{ "leaq $dest, [$constantaddress]\n\t"
6587 "jmp [$dest + $switch_val << $shift]\n\t" %}
6588 ins_encode %{
6589 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6590 // to do that and the compiler is using that register as one it can allocate.
6591 // So we build it all by hand.
6592 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6593 // ArrayAddress dispatch(table, index);
6594 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6595 __ lea($dest$$Register, $constantaddress);
6596 __ jmp(dispatch);
6597 %}
6598 ins_pipe(pipe_jmp);
6599 %}
6600
6601 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6602 match(Jump (AddL (LShiftL switch_val shift) offset));
6603 ins_cost(350);
6604 effect(TEMP dest);
6605
6606 format %{ "leaq $dest, [$constantaddress]\n\t"
6607 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6608 ins_encode %{
6609 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6610 // to do that and the compiler is using that register as one it can allocate.
6611 // So we build it all by hand.
6612 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6613 // ArrayAddress dispatch(table, index);
6614 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6615 __ lea($dest$$Register, $constantaddress);
6616 __ jmp(dispatch);
6617 %}
6618 ins_pipe(pipe_jmp);
6619 %}
6620
6621 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6622 match(Jump switch_val);
6623 ins_cost(350);
6624 effect(TEMP dest);
6625
6626 format %{ "leaq $dest, [$constantaddress]\n\t"
6627 "jmp [$dest + $switch_val]\n\t" %}
6628 ins_encode %{
6629 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6630 // to do that and the compiler is using that register as one it can allocate.
6631 // So we build it all by hand.
6632 // Address index(noreg, switch_reg, Address::times_1);
6633 // ArrayAddress dispatch(table, index);
6634 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6635 __ lea($dest$$Register, $constantaddress);
6636 __ jmp(dispatch);
6637 %}
6638 ins_pipe(pipe_jmp);
6639 %}
6640
6641 // Conditional move
6642 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6643 %{
6644 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6645
6646 ins_cost(200); // XXX
6647 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6648 opcode(0x0F, 0x40);
6649 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6650 ins_pipe(pipe_cmov_reg);
6651 %}
6652
6653 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6654 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6655
6656 ins_cost(200); // XXX
6657 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6658 opcode(0x0F, 0x40);
6659 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6660 ins_pipe(pipe_cmov_reg);
6661 %}
6662
6663 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6664 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6665 ins_cost(200);
6666 expand %{
6667 cmovI_regU(cop, cr, dst, src);
6668 %}
6669 %}
6670
6671 // Conditional move
6672 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6673 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6674
6675 ins_cost(250); // XXX
6676 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6677 opcode(0x0F, 0x40);
6678 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6679 ins_pipe(pipe_cmov_mem);
6680 %}
6681
6682 // Conditional move
6683 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6684 %{
6685 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6686
6687 ins_cost(250); // XXX
6688 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6689 opcode(0x0F, 0x40);
6690 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6691 ins_pipe(pipe_cmov_mem);
6692 %}
6693
6694 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6695 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6696 ins_cost(250);
6697 expand %{
6698 cmovI_memU(cop, cr, dst, src);
6699 %}
6700 %}
6701
6702 // Conditional move
6703 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6704 %{
6705 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6706
6707 ins_cost(200); // XXX
6708 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6709 opcode(0x0F, 0x40);
6710 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6711 ins_pipe(pipe_cmov_reg);
6712 %}
6713
6714 // Conditional move
6715 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6716 %{
6717 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6718
6719 ins_cost(200); // XXX
6720 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6721 opcode(0x0F, 0x40);
6722 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6723 ins_pipe(pipe_cmov_reg);
6724 %}
6725
6726 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6727 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6728 ins_cost(200);
6729 expand %{
6730 cmovN_regU(cop, cr, dst, src);
6731 %}
6732 %}
6733
6734 // Conditional move
6735 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6736 %{
6737 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6738
6739 ins_cost(200); // XXX
6740 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6741 opcode(0x0F, 0x40);
6742 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6743 ins_pipe(pipe_cmov_reg); // XXX
6744 %}
6745
6746 // Conditional move
6747 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6748 %{
6749 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6750
6751 ins_cost(200); // XXX
6752 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6753 opcode(0x0F, 0x40);
6754 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6755 ins_pipe(pipe_cmov_reg); // XXX
6756 %}
6757
6758 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6759 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6760 ins_cost(200);
6761 expand %{
6762 cmovP_regU(cop, cr, dst, src);
6763 %}
6764 %}
6765
6766 // DISABLED: Requires the ADLC to emit a bottom_type call that
6767 // correctly meets the two pointer arguments; one is an incoming
6768 // register but the other is a memory operand. ALSO appears to
6769 // be buggy with implicit null checks.
6770 //
6771 //// Conditional move
6772 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6773 //%{
6774 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6775 // ins_cost(250);
6776 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6777 // opcode(0x0F,0x40);
6778 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6779 // ins_pipe( pipe_cmov_mem );
6780 //%}
6781 //
6782 //// Conditional move
6783 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6784 //%{
6785 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6786 // ins_cost(250);
6787 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6788 // opcode(0x0F,0x40);
6789 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6790 // ins_pipe( pipe_cmov_mem );
6791 //%}
6792
6793 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6794 %{
6795 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6796
6797 ins_cost(200); // XXX
6798 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6799 opcode(0x0F, 0x40);
6800 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6801 ins_pipe(pipe_cmov_reg); // XXX
6802 %}
6803
6804 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6805 %{
6806 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6807
6808 ins_cost(200); // XXX
6809 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6810 opcode(0x0F, 0x40);
6811 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6812 ins_pipe(pipe_cmov_mem); // XXX
6813 %}
6814
6815 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6816 %{
6817 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6818
6819 ins_cost(200); // XXX
6820 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6821 opcode(0x0F, 0x40);
6822 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6823 ins_pipe(pipe_cmov_reg); // XXX
6824 %}
6825
6826 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6827 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6828 ins_cost(200);
6829 expand %{
6830 cmovL_regU(cop, cr, dst, src);
6831 %}
6832 %}
6833
6834 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6835 %{
6836 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6837
6838 ins_cost(200); // XXX
6839 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6840 opcode(0x0F, 0x40);
6841 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6842 ins_pipe(pipe_cmov_mem); // XXX
6843 %}
6844
6845 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6846 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6847 ins_cost(200);
6848 expand %{
6849 cmovL_memU(cop, cr, dst, src);
6850 %}
6851 %}
6852
6853 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6854 %{
6855 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6856
6857 ins_cost(200); // XXX
6858 format %{ "jn$cop skip\t# signed cmove float\n\t"
6859 "movss $dst, $src\n"
6860 "skip:" %}
6861 ins_encode %{
6862 Label Lskip;
6863 // Invert sense of branch from sense of CMOV
6864 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6865 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6866 __ bind(Lskip);
6867 %}
6868 ins_pipe(pipe_slow);
6869 %}
6870
6871 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6872 // %{
6873 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6874
6875 // ins_cost(200); // XXX
6876 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6877 // "movss $dst, $src\n"
6878 // "skip:" %}
6879 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6880 // ins_pipe(pipe_slow);
6881 // %}
6882
6883 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6884 %{
6885 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6886
6887 ins_cost(200); // XXX
6888 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6889 "movss $dst, $src\n"
6890 "skip:" %}
6891 ins_encode %{
6892 Label Lskip;
6893 // Invert sense of branch from sense of CMOV
6894 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6895 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6896 __ bind(Lskip);
6897 %}
6898 ins_pipe(pipe_slow);
6899 %}
6900
6901 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6902 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6903 ins_cost(200);
6904 expand %{
6905 cmovF_regU(cop, cr, dst, src);
6906 %}
6907 %}
6908
6909 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6910 %{
6911 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6912
6913 ins_cost(200); // XXX
6914 format %{ "jn$cop skip\t# signed cmove double\n\t"
6915 "movsd $dst, $src\n"
6916 "skip:" %}
6917 ins_encode %{
6918 Label Lskip;
6919 // Invert sense of branch from sense of CMOV
6920 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6921 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6922 __ bind(Lskip);
6923 %}
6924 ins_pipe(pipe_slow);
6925 %}
6926
6927 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6928 %{
6929 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6930
6931 ins_cost(200); // XXX
6932 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6933 "movsd $dst, $src\n"
6934 "skip:" %}
6935 ins_encode %{
6936 Label Lskip;
6937 // Invert sense of branch from sense of CMOV
6938 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6939 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6940 __ bind(Lskip);
6941 %}
6942 ins_pipe(pipe_slow);
6943 %}
6944
6945 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6946 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6947 ins_cost(200);
6948 expand %{
6949 cmovD_regU(cop, cr, dst, src);
6950 %}
6951 %}
6952
6953 //----------Arithmetic Instructions--------------------------------------------
6954 //----------Addition Instructions----------------------------------------------
6955
6956 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
6957 %{
6958 match(AddExactI dst src);
6959 effect(DEF cr);
6960
6961 format %{ "addl $dst, $src\t# addExact int" %}
6962 ins_encode %{
6963 __ addl($dst$$Register, $src$$Register);
6964 %}
6965 ins_pipe(ialu_reg_reg);
6966 %}
6967
6968 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6969 %{
6970 match(AddExactI dst src);
6971 effect(DEF cr);
6972
6973 format %{ "addl $dst, $src\t# addExact int" %}
6974 ins_encode %{
6975 __ addl($dst$$Register, $src$$constant);
6976 %}
6977 ins_pipe(ialu_reg_reg);
6978 %}
6979
6980 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
6981 %{
6982 match(AddExactI dst (LoadI src));
6983 effect(DEF cr);
6984
6985 ins_cost(125); // XXX
6986 format %{ "addl $dst, $src\t# addExact int" %}
6987 ins_encode %{
6988 __ addl($dst$$Register, $src$$Address);
6989 %}
6990
6991 ins_pipe(ialu_reg_mem);
6992 %}
6993
6994 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
6995 %{
6996 match(AddExactL dst src);
6997 effect(DEF cr);
6998
6999 format %{ "addq $dst, $src\t# addExact long" %}
7000 ins_encode %{
7001 __ addq($dst$$Register, $src$$Register);
7002 %}
7003 ins_pipe(ialu_reg_reg);
7004 %}
7005
7006 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7007 %{
7008 match(AddExactL dst src);
7009 effect(DEF cr);
7010
7011 format %{ "addq $dst, $src\t# addExact long" %}
7012 ins_encode %{
7013 __ addq($dst$$Register, $src$$constant);
7014 %}
7015 ins_pipe(ialu_reg_reg);
7016 %}
7017
7018 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
7019 %{
7020 match(AddExactL dst (LoadL src));
7021 effect(DEF cr);
7022
7023 ins_cost(125); // XXX
7024 format %{ "addq $dst, $src\t# addExact long" %}
7025 ins_encode %{
7026 __ addq($dst$$Register, $src$$Address);
7027 %}
7028
7029 ins_pipe(ialu_reg_mem);
7030 %}
7031
7032 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7033 %{
7034 match(Set dst (AddI dst src));
7035 effect(KILL cr);
7036
7037 format %{ "addl $dst, $src\t# int" %}
7038 opcode(0x03);
7039 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7040 ins_pipe(ialu_reg_reg);
7041 %}
7042
7043 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7044 %{
7045 match(Set dst (AddI dst src));
7046 effect(KILL cr);
7047
7048 format %{ "addl $dst, $src\t# int" %}
7049 opcode(0x81, 0x00); /* /0 id */
7050 ins_encode(OpcSErm(dst, src), Con8or32(src));
7051 ins_pipe( ialu_reg );
7052 %}
7053
7054 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7055 %{
7056 match(Set dst (AddI dst (LoadI src)));
7057 effect(KILL cr);
7058
7059 ins_cost(125); // XXX
7060 format %{ "addl $dst, $src\t# int" %}
7061 opcode(0x03);
7062 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7063 ins_pipe(ialu_reg_mem);
7064 %}
7065
7066 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7067 %{
7068 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7069 effect(KILL cr);
7070
7071 ins_cost(150); // XXX
7072 format %{ "addl $dst, $src\t# int" %}
7073 opcode(0x01); /* Opcode 01 /r */
7074 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7075 ins_pipe(ialu_mem_reg);
7076 %}
7077
7078 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7079 %{
7080 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7081 effect(KILL cr);
7082
7083 ins_cost(125); // XXX
7084 format %{ "addl $dst, $src\t# int" %}
7085 opcode(0x81); /* Opcode 81 /0 id */
7086 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7087 ins_pipe(ialu_mem_imm);
7088 %}
7089
7090 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7091 %{
7092 predicate(UseIncDec);
7093 match(Set dst (AddI dst src));
7094 effect(KILL cr);
7095
7096 format %{ "incl $dst\t# int" %}
7097 opcode(0xFF, 0x00); // FF /0
7098 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7099 ins_pipe(ialu_reg);
7100 %}
7101
7102 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7103 %{
7104 predicate(UseIncDec);
7105 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7106 effect(KILL cr);
7107
7108 ins_cost(125); // XXX
7109 format %{ "incl $dst\t# int" %}
7110 opcode(0xFF); /* Opcode FF /0 */
7111 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7112 ins_pipe(ialu_mem_imm);
7113 %}
7114
7115 // XXX why does that use AddI
7116 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7117 %{
7118 predicate(UseIncDec);
7119 match(Set dst (AddI dst src));
7120 effect(KILL cr);
7121
7122 format %{ "decl $dst\t# int" %}
7123 opcode(0xFF, 0x01); // FF /1
7124 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7125 ins_pipe(ialu_reg);
7126 %}
7127
7128 // XXX why does that use AddI
7129 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7130 %{
7131 predicate(UseIncDec);
7132 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7133 effect(KILL cr);
7134
7135 ins_cost(125); // XXX
7136 format %{ "decl $dst\t# int" %}
7137 opcode(0xFF); /* Opcode FF /1 */
7138 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7139 ins_pipe(ialu_mem_imm);
7140 %}
7141
7142 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7143 %{
7144 match(Set dst (AddI src0 src1));
7145
7146 ins_cost(110);
7147 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7148 opcode(0x8D); /* 0x8D /r */
7149 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7150 ins_pipe(ialu_reg_reg);
7151 %}
7152
7153 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7154 %{
7155 match(Set dst (AddL dst src));
7156 effect(KILL cr);
7157
7158 format %{ "addq $dst, $src\t# long" %}
7159 opcode(0x03);
7160 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7161 ins_pipe(ialu_reg_reg);
7162 %}
7163
7164 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7165 %{
7166 match(Set dst (AddL dst src));
7167 effect(KILL cr);
7168
7169 format %{ "addq $dst, $src\t# long" %}
7170 opcode(0x81, 0x00); /* /0 id */
7171 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7172 ins_pipe( ialu_reg );
7173 %}
7174
7175 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7176 %{
7177 match(Set dst (AddL dst (LoadL src)));
7178 effect(KILL cr);
7179
7180 ins_cost(125); // XXX
7181 format %{ "addq $dst, $src\t# long" %}
7182 opcode(0x03);
7183 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7184 ins_pipe(ialu_reg_mem);
7185 %}
7186
7187 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7188 %{
7189 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7190 effect(KILL cr);
7191
7192 ins_cost(150); // XXX
7193 format %{ "addq $dst, $src\t# long" %}
7194 opcode(0x01); /* Opcode 01 /r */
7195 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7196 ins_pipe(ialu_mem_reg);
7197 %}
7198
7199 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7200 %{
7201 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7202 effect(KILL cr);
7203
7204 ins_cost(125); // XXX
7205 format %{ "addq $dst, $src\t# long" %}
7206 opcode(0x81); /* Opcode 81 /0 id */
7207 ins_encode(REX_mem_wide(dst),
7208 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7209 ins_pipe(ialu_mem_imm);
7210 %}
7211
7212 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7213 %{
7214 predicate(UseIncDec);
7215 match(Set dst (AddL dst src));
7216 effect(KILL cr);
7217
7218 format %{ "incq $dst\t# long" %}
7219 opcode(0xFF, 0x00); // FF /0
7220 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7221 ins_pipe(ialu_reg);
7222 %}
7223
7224 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7225 %{
7226 predicate(UseIncDec);
7227 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7228 effect(KILL cr);
7229
7230 ins_cost(125); // XXX
7231 format %{ "incq $dst\t# long" %}
7232 opcode(0xFF); /* Opcode FF /0 */
7233 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7234 ins_pipe(ialu_mem_imm);
7235 %}
7236
7237 // XXX why does that use AddL
7238 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7239 %{
7240 predicate(UseIncDec);
7241 match(Set dst (AddL dst src));
7242 effect(KILL cr);
7243
7244 format %{ "decq $dst\t# long" %}
7245 opcode(0xFF, 0x01); // FF /1
7246 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7247 ins_pipe(ialu_reg);
7248 %}
7249
7250 // XXX why does that use AddL
7251 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7252 %{
7253 predicate(UseIncDec);
7254 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7255 effect(KILL cr);
7256
7257 ins_cost(125); // XXX
7258 format %{ "decq $dst\t# long" %}
7259 opcode(0xFF); /* Opcode FF /1 */
7260 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7261 ins_pipe(ialu_mem_imm);
7262 %}
7263
7264 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7265 %{
7266 match(Set dst (AddL src0 src1));
7267
7268 ins_cost(110);
7269 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7270 opcode(0x8D); /* 0x8D /r */
7271 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7272 ins_pipe(ialu_reg_reg);
7273 %}
7274
7275 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7276 %{
7277 match(Set dst (AddP dst src));
7278 effect(KILL cr);
7279
7280 format %{ "addq $dst, $src\t# ptr" %}
7281 opcode(0x03);
7282 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7283 ins_pipe(ialu_reg_reg);
7284 %}
7285
7286 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7287 %{
7288 match(Set dst (AddP dst src));
7289 effect(KILL cr);
7290
7291 format %{ "addq $dst, $src\t# ptr" %}
7292 opcode(0x81, 0x00); /* /0 id */
7293 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7294 ins_pipe( ialu_reg );
7295 %}
7296
7297 // XXX addP mem ops ????
7298
7299 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7300 %{
7301 match(Set dst (AddP src0 src1));
7302
7303 ins_cost(110);
7304 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7305 opcode(0x8D); /* 0x8D /r */
7306 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7307 ins_pipe(ialu_reg_reg);
7308 %}
7309
7310 instruct checkCastPP(rRegP dst)
7311 %{
7312 match(Set dst (CheckCastPP dst));
7313
7314 size(0);
7315 format %{ "# checkcastPP of $dst" %}
7316 ins_encode(/* empty encoding */);
7317 ins_pipe(empty);
7318 %}
7319
7320 instruct castPP(rRegP dst)
7321 %{
7322 match(Set dst (CastPP dst));
7323
7324 size(0);
7325 format %{ "# castPP of $dst" %}
7326 ins_encode(/* empty encoding */);
7327 ins_pipe(empty);
7328 %}
7329
7330 instruct castII(rRegI dst)
7331 %{
7332 match(Set dst (CastII dst));
7333
7334 size(0);
7335 format %{ "# castII of $dst" %}
7336 ins_encode(/* empty encoding */);
7337 ins_cost(0);
7338 ins_pipe(empty);
7339 %}
7340
7341 // LoadP-locked same as a regular LoadP when used with compare-swap
7342 instruct loadPLocked(rRegP dst, memory mem)
7343 %{
7344 match(Set dst (LoadPLocked mem));
7345
7346 ins_cost(125); // XXX
7347 format %{ "movq $dst, $mem\t# ptr locked" %}
7348 opcode(0x8B);
7349 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7350 ins_pipe(ialu_reg_mem); // XXX
7351 %}
7352
7353 // Conditional-store of the updated heap-top.
7354 // Used during allocation of the shared heap.
7355 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7356
7357 instruct storePConditional(memory heap_top_ptr,
7358 rax_RegP oldval, rRegP newval,
7359 rFlagsReg cr)
7360 %{
7361 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7362
7363 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7364 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7365 opcode(0x0F, 0xB1);
7366 ins_encode(lock_prefix,
7367 REX_reg_mem_wide(newval, heap_top_ptr),
7368 OpcP, OpcS,
7369 reg_mem(newval, heap_top_ptr));
7370 ins_pipe(pipe_cmpxchg);
7371 %}
7372
7373 // Conditional-store of an int value.
7374 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7375 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7376 %{
7377 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7378 effect(KILL oldval);
7379
7380 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7381 opcode(0x0F, 0xB1);
7382 ins_encode(lock_prefix,
7383 REX_reg_mem(newval, mem),
7384 OpcP, OpcS,
7385 reg_mem(newval, mem));
7386 ins_pipe(pipe_cmpxchg);
7387 %}
7388
7389 // Conditional-store of a long value.
7390 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7391 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7392 %{
7393 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7394 effect(KILL oldval);
7395
7396 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7397 opcode(0x0F, 0xB1);
7398 ins_encode(lock_prefix,
7399 REX_reg_mem_wide(newval, mem),
7400 OpcP, OpcS,
7401 reg_mem(newval, mem));
7402 ins_pipe(pipe_cmpxchg);
7403 %}
7404
7405
7406 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7407 instruct compareAndSwapP(rRegI res,
7408 memory mem_ptr,
7409 rax_RegP oldval, rRegP newval,
7410 rFlagsReg cr)
7411 %{
7412 predicate(VM_Version::supports_cx8());
7413 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7414 effect(KILL cr, KILL oldval);
7415
7416 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7417 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7418 "sete $res\n\t"
7419 "movzbl $res, $res" %}
7420 opcode(0x0F, 0xB1);
7421 ins_encode(lock_prefix,
7422 REX_reg_mem_wide(newval, mem_ptr),
7423 OpcP, OpcS,
7424 reg_mem(newval, mem_ptr),
7425 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7426 REX_reg_breg(res, res), // movzbl
7427 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7428 ins_pipe( pipe_cmpxchg );
7429 %}
7430
7431 instruct compareAndSwapL(rRegI res,
7432 memory mem_ptr,
7433 rax_RegL oldval, rRegL newval,
7434 rFlagsReg cr)
7435 %{
7436 predicate(VM_Version::supports_cx8());
7437 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7438 effect(KILL cr, KILL oldval);
7439
7440 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7441 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7442 "sete $res\n\t"
7443 "movzbl $res, $res" %}
7444 opcode(0x0F, 0xB1);
7445 ins_encode(lock_prefix,
7446 REX_reg_mem_wide(newval, mem_ptr),
7447 OpcP, OpcS,
7448 reg_mem(newval, mem_ptr),
7449 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7450 REX_reg_breg(res, res), // movzbl
7451 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7452 ins_pipe( pipe_cmpxchg );
7453 %}
7454
7455 instruct compareAndSwapI(rRegI res,
7456 memory mem_ptr,
7457 rax_RegI oldval, rRegI newval,
7458 rFlagsReg cr)
7459 %{
7460 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7461 effect(KILL cr, KILL oldval);
7462
7463 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7464 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7465 "sete $res\n\t"
7466 "movzbl $res, $res" %}
7467 opcode(0x0F, 0xB1);
7468 ins_encode(lock_prefix,
7469 REX_reg_mem(newval, mem_ptr),
7470 OpcP, OpcS,
7471 reg_mem(newval, mem_ptr),
7472 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7473 REX_reg_breg(res, res), // movzbl
7474 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7475 ins_pipe( pipe_cmpxchg );
7476 %}
7477
7478
7479 instruct compareAndSwapN(rRegI res,
7480 memory mem_ptr,
7481 rax_RegN oldval, rRegN newval,
7482 rFlagsReg cr) %{
7483 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7484 effect(KILL cr, KILL oldval);
7485
7486 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7487 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7488 "sete $res\n\t"
7489 "movzbl $res, $res" %}
7490 opcode(0x0F, 0xB1);
7491 ins_encode(lock_prefix,
7492 REX_reg_mem(newval, mem_ptr),
7493 OpcP, OpcS,
7494 reg_mem(newval, mem_ptr),
7495 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7496 REX_reg_breg(res, res), // movzbl
7497 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7498 ins_pipe( pipe_cmpxchg );
7499 %}
7500
7501 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7502 predicate(n->as_LoadStore()->result_not_used());
7503 match(Set dummy (GetAndAddI mem add));
7504 effect(KILL cr);
7505 format %{ "ADDL [$mem],$add" %}
7506 ins_encode %{
7507 if (os::is_MP()) { __ lock(); }
7508 __ addl($mem$$Address, $add$$constant);
7509 %}
7510 ins_pipe( pipe_cmpxchg );
7511 %}
7512
7513 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7514 match(Set newval (GetAndAddI mem newval));
7515 effect(KILL cr);
7516 format %{ "XADDL [$mem],$newval" %}
7517 ins_encode %{
7518 if (os::is_MP()) { __ lock(); }
7519 __ xaddl($mem$$Address, $newval$$Register);
7520 %}
7521 ins_pipe( pipe_cmpxchg );
7522 %}
7523
7524 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7525 predicate(n->as_LoadStore()->result_not_used());
7526 match(Set dummy (GetAndAddL mem add));
7527 effect(KILL cr);
7528 format %{ "ADDQ [$mem],$add" %}
7529 ins_encode %{
7530 if (os::is_MP()) { __ lock(); }
7531 __ addq($mem$$Address, $add$$constant);
7532 %}
7533 ins_pipe( pipe_cmpxchg );
7534 %}
7535
7536 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7537 match(Set newval (GetAndAddL mem newval));
7538 effect(KILL cr);
7539 format %{ "XADDQ [$mem],$newval" %}
7540 ins_encode %{
7541 if (os::is_MP()) { __ lock(); }
7542 __ xaddq($mem$$Address, $newval$$Register);
7543 %}
7544 ins_pipe( pipe_cmpxchg );
7545 %}
7546
7547 instruct xchgI( memory mem, rRegI newval) %{
7548 match(Set newval (GetAndSetI mem newval));
7549 format %{ "XCHGL $newval,[$mem]" %}
7550 ins_encode %{
7551 __ xchgl($newval$$Register, $mem$$Address);
7552 %}
7553 ins_pipe( pipe_cmpxchg );
7554 %}
7555
7556 instruct xchgL( memory mem, rRegL newval) %{
7557 match(Set newval (GetAndSetL mem newval));
7558 format %{ "XCHGL $newval,[$mem]" %}
7559 ins_encode %{
7560 __ xchgq($newval$$Register, $mem$$Address);
7561 %}
7562 ins_pipe( pipe_cmpxchg );
7563 %}
7564
7565 instruct xchgP( memory mem, rRegP newval) %{
7566 match(Set newval (GetAndSetP mem newval));
7567 format %{ "XCHGQ $newval,[$mem]" %}
7568 ins_encode %{
7569 __ xchgq($newval$$Register, $mem$$Address);
7570 %}
7571 ins_pipe( pipe_cmpxchg );
7572 %}
7573
7574 instruct xchgN( memory mem, rRegN newval) %{
7575 match(Set newval (GetAndSetN mem newval));
7576 format %{ "XCHGL $newval,$mem]" %}
7577 ins_encode %{
7578 __ xchgl($newval$$Register, $mem$$Address);
7579 %}
7580 ins_pipe( pipe_cmpxchg );
7581 %}
7582
7583 //----------Subtraction Instructions-------------------------------------------
7584
7585 // Integer Subtraction Instructions
7586 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7587 %{
7588 match(Set dst (SubI dst src));
7589 effect(KILL cr);
7590
7591 format %{ "subl $dst, $src\t# int" %}
7592 opcode(0x2B);
7593 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7594 ins_pipe(ialu_reg_reg);
7595 %}
7596
7597 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7598 %{
7599 match(Set dst (SubI dst src));
7600 effect(KILL cr);
7601
7602 format %{ "subl $dst, $src\t# int" %}
7603 opcode(0x81, 0x05); /* Opcode 81 /5 */
7604 ins_encode(OpcSErm(dst, src), Con8or32(src));
7605 ins_pipe(ialu_reg);
7606 %}
7607
7608 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7609 %{
7610 match(Set dst (SubI dst (LoadI src)));
7611 effect(KILL cr);
7612
7613 ins_cost(125);
7614 format %{ "subl $dst, $src\t# int" %}
7615 opcode(0x2B);
7616 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7617 ins_pipe(ialu_reg_mem);
7618 %}
7619
7620 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7621 %{
7622 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7623 effect(KILL cr);
7624
7625 ins_cost(150);
7626 format %{ "subl $dst, $src\t# int" %}
7627 opcode(0x29); /* Opcode 29 /r */
7628 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7629 ins_pipe(ialu_mem_reg);
7630 %}
7631
7632 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7633 %{
7634 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7635 effect(KILL cr);
7636
7637 ins_cost(125); // XXX
7638 format %{ "subl $dst, $src\t# int" %}
7639 opcode(0x81); /* Opcode 81 /5 id */
7640 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7641 ins_pipe(ialu_mem_imm);
7642 %}
7643
7644 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7645 %{
7646 match(SubExactI dst src);
7647 effect(DEF cr);
7648
7649 format %{ "subl $dst, $src\t# subExact int" %}
7650 ins_encode %{
7651 __ subl($dst$$Register, $src$$Register);
7652 %}
7653 ins_pipe(ialu_reg_reg);
7654 %}
7655
7656 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
7657 %{
7658 match(SubExactI dst src);
7659 effect(DEF cr);
7660
7661 format %{ "subl $dst, $src\t# subExact int" %}
7662 ins_encode %{
7663 __ subl($dst$$Register, $src$$constant);
7664 %}
7665 ins_pipe(ialu_reg_reg);
7666 %}
7667
7668 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7669 %{
7670 match(SubExactI dst (LoadI src));
7671 effect(DEF cr);
7672
7673 ins_cost(125);
7674 format %{ "subl $dst, $src\t# subExact int" %}
7675 ins_encode %{
7676 __ subl($dst$$Register, $src$$Address);
7677 %}
7678 ins_pipe(ialu_reg_mem);
7679 %}
7680
7681 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7682 %{
7683 match(SubExactL dst src);
7684 effect(DEF cr);
7685
7686 format %{ "subq $dst, $src\t# subExact long" %}
7687 ins_encode %{
7688 __ subq($dst$$Register, $src$$Register);
7689 %}
7690 ins_pipe(ialu_reg_reg);
7691 %}
7692
7693 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7694 %{
7695 match(SubExactL dst (LoadL src));
7696 effect(DEF cr);
7697
7698 format %{ "subq $dst, $src\t# subExact long" %}
7699 ins_encode %{
7700 __ subq($dst$$Register, $src$$constant);
7701 %}
7702 ins_pipe(ialu_reg_reg);
7703 %}
7704
7705 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7706 %{
7707 match(SubExactI dst src);
7708 effect(DEF cr);
7709
7710 ins_cost(125);
7711 format %{ "subq $dst, $src\t# subExact long" %}
7712 ins_encode %{
7713 __ subq($dst$$Register, $src$$Address);
7714 %}
7715 ins_pipe(ialu_reg_mem);
7716 %}
7717
7718 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7719 %{
7720 match(Set dst (SubL dst src));
7721 effect(KILL cr);
7722
7723 format %{ "subq $dst, $src\t# long" %}
7724 opcode(0x2B);
7725 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7726 ins_pipe(ialu_reg_reg);
7727 %}
7728
7729 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7730 %{
7731 match(Set dst (SubL dst src));
7732 effect(KILL cr);
7733
7734 format %{ "subq $dst, $src\t# long" %}
7735 opcode(0x81, 0x05); /* Opcode 81 /5 */
7736 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7737 ins_pipe(ialu_reg);
7738 %}
7739
7740 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7741 %{
7742 match(Set dst (SubL dst (LoadL src)));
7743 effect(KILL cr);
7744
7745 ins_cost(125);
7746 format %{ "subq $dst, $src\t# long" %}
7747 opcode(0x2B);
7748 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7749 ins_pipe(ialu_reg_mem);
7750 %}
7751
7752 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7753 %{
7754 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7755 effect(KILL cr);
7756
7757 ins_cost(150);
7758 format %{ "subq $dst, $src\t# long" %}
7759 opcode(0x29); /* Opcode 29 /r */
7760 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7761 ins_pipe(ialu_mem_reg);
7762 %}
7763
7764 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7765 %{
7766 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7767 effect(KILL cr);
7768
7769 ins_cost(125); // XXX
7770 format %{ "subq $dst, $src\t# long" %}
7771 opcode(0x81); /* Opcode 81 /5 id */
7772 ins_encode(REX_mem_wide(dst),
7773 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7774 ins_pipe(ialu_mem_imm);
7775 %}
7776
7777 // Subtract from a pointer
7778 // XXX hmpf???
7779 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7780 %{
7781 match(Set dst (AddP dst (SubI zero src)));
7782 effect(KILL cr);
7783
7784 format %{ "subq $dst, $src\t# ptr - int" %}
7785 opcode(0x2B);
7786 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7787 ins_pipe(ialu_reg_reg);
7788 %}
7789
7790 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7791 %{
7792 match(Set dst (SubI zero dst));
7793 effect(KILL cr);
7794
7795 format %{ "negl $dst\t# int" %}
7796 opcode(0xF7, 0x03); // Opcode F7 /3
7797 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7798 ins_pipe(ialu_reg);
7799 %}
7800
7801 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7802 %{
7803 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7804 effect(KILL cr);
7805
7806 format %{ "negl $dst\t# int" %}
7807 opcode(0xF7, 0x03); // Opcode F7 /3
7808 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7809 ins_pipe(ialu_reg);
7810 %}
7811
7812 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7813 %{
7814 match(Set dst (SubL zero dst));
7815 effect(KILL cr);
7816
7817 format %{ "negq $dst\t# long" %}
7818 opcode(0xF7, 0x03); // Opcode F7 /3
7819 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7820 ins_pipe(ialu_reg);
7821 %}
7822
7823 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7824 %{
7825 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7826 effect(KILL cr);
7827
7828 format %{ "negq $dst\t# long" %}
7829 opcode(0xF7, 0x03); // Opcode F7 /3
7830 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7831 ins_pipe(ialu_reg);
7832 %}
7833
7834 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
7835 %{
7836 match(NegExactI dst);
7837 effect(KILL cr);
7838
7839 format %{ "negl $dst\t# negExact int" %}
7840 ins_encode %{
7841 __ negl($dst$$Register);
7842 %}
7843 ins_pipe(ialu_reg);
7844 %}
7845
7846 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
7847 %{
7848 match(NegExactL dst);
7849 effect(KILL cr);
7850
7851 format %{ "negq $dst\t# negExact long" %}
7852 ins_encode %{
7853 __ negq($dst$$Register);
7854 %}
7855 ins_pipe(ialu_reg);
7856 %}
7857
7858
7859 //----------Multiplication/Division Instructions-------------------------------
7860 // Integer Multiplication Instructions
7861 // Multiply Register
7862
7863 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7864 %{
7865 match(Set dst (MulI dst src));
7866 effect(KILL cr);
7867
7868 ins_cost(300);
7869 format %{ "imull $dst, $src\t# int" %}
7870 opcode(0x0F, 0xAF);
7871 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7872 ins_pipe(ialu_reg_reg_alu0);
7873 %}
7874
7875 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7876 %{
7877 match(Set dst (MulI src imm));
7878 effect(KILL cr);
7879
7880 ins_cost(300);
7881 format %{ "imull $dst, $src, $imm\t# int" %}
7882 opcode(0x69); /* 69 /r id */
7883 ins_encode(REX_reg_reg(dst, src),
7884 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7885 ins_pipe(ialu_reg_reg_alu0);
7886 %}
7887
7888 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7889 %{
7890 match(Set dst (MulI dst (LoadI src)));
7891 effect(KILL cr);
7892
7893 ins_cost(350);
7894 format %{ "imull $dst, $src\t# int" %}
7895 opcode(0x0F, 0xAF);
7896 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7897 ins_pipe(ialu_reg_mem_alu0);
7898 %}
7899
7900 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7901 %{
7902 match(Set dst (MulI (LoadI src) imm));
7903 effect(KILL cr);
7904
7905 ins_cost(300);
7906 format %{ "imull $dst, $src, $imm\t# int" %}
7907 opcode(0x69); /* 69 /r id */
7908 ins_encode(REX_reg_mem(dst, src),
7909 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7910 ins_pipe(ialu_reg_mem_alu0);
7911 %}
7912
7913 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7914 %{
7915 match(Set dst (MulL dst src));
7916 effect(KILL cr);
7917
7918 ins_cost(300);
7919 format %{ "imulq $dst, $src\t# long" %}
7920 opcode(0x0F, 0xAF);
7921 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7922 ins_pipe(ialu_reg_reg_alu0);
7923 %}
7924
7925 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7926 %{
7927 match(Set dst (MulL src imm));
7928 effect(KILL cr);
7929
7930 ins_cost(300);
7931 format %{ "imulq $dst, $src, $imm\t# long" %}
7932 opcode(0x69); /* 69 /r id */
7933 ins_encode(REX_reg_reg_wide(dst, src),
7934 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7935 ins_pipe(ialu_reg_reg_alu0);
7936 %}
7937
7938 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7939 %{
7940 match(Set dst (MulL dst (LoadL src)));
7941 effect(KILL cr);
7942
7943 ins_cost(350);
7944 format %{ "imulq $dst, $src\t# long" %}
7945 opcode(0x0F, 0xAF);
7946 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7947 ins_pipe(ialu_reg_mem_alu0);
7948 %}
7949
7950 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7951 %{
7952 match(Set dst (MulL (LoadL src) imm));
7953 effect(KILL cr);
7954
7955 ins_cost(300);
7956 format %{ "imulq $dst, $src, $imm\t# long" %}
7957 opcode(0x69); /* 69 /r id */
7958 ins_encode(REX_reg_mem_wide(dst, src),
7959 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7960 ins_pipe(ialu_reg_mem_alu0);
7961 %}
7962
7963 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7964 %{
7965 match(Set dst (MulHiL src rax));
7966 effect(USE_KILL rax, KILL cr);
7967
7968 ins_cost(300);
7969 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7970 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7971 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7972 ins_pipe(ialu_reg_reg_alu0);
7973 %}
7974
7975
7976 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7977 %{
7978 match(MulExactI dst src);
7979 effect(DEF cr);
7980
7981 ins_cost(300);
7982 format %{ "imull $dst, $src\t# mulExact int" %}
7983 ins_encode %{
7984 __ imull($dst$$Register, $src$$Register);
7985 %}
7986 ins_pipe(ialu_reg_reg_alu0);
7987 %}
7988
7989
7990 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
7991 %{
7992 match(MulExactI src imm);
7993 effect(DEF cr);
7994
7995 ins_cost(300);
7996 format %{ "imull $dst, $src, $imm\t# mulExact int" %}
7997 ins_encode %{
7998 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7999 %}
8000 ins_pipe(ialu_reg_reg_alu0);
8001 %}
8002
8003 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
8004 %{
8005 match(MulExactI dst (LoadI src));
8006 effect(DEF cr);
8007
8008 ins_cost(350);
8009 format %{ "imull $dst, $src\t# mulExact int" %}
8010 ins_encode %{
8011 __ imull($dst$$Register, $src$$Address);
8012 %}
8013 ins_pipe(ialu_reg_mem_alu0);
8014 %}
8015
8016 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
8017 %{
8018 match(MulExactL dst src);
8019 effect(DEF cr);
8020
8021 ins_cost(300);
8022 format %{ "imulq $dst, $src\t# mulExact long" %}
8023 ins_encode %{
8024 __ imulq($dst$$Register, $src$$Register);
8025 %}
8026 ins_pipe(ialu_reg_reg_alu0);
8027 %}
8028
8029 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8030 %{
8031 match(MulExactL src imm);
8032 effect(DEF cr);
8033
8034 ins_cost(300);
8035 format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
8036 ins_encode %{
8037 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8038 %}
8039 ins_pipe(ialu_reg_reg_alu0);
8040 %}
8041
8042 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
8043 %{
8044 match(MulExactL dst (LoadL src));
8045 effect(DEF cr);
8046
8047 ins_cost(350);
8048 format %{ "imulq $dst, $src\t# mulExact long" %}
8049 ins_encode %{
8050 __ imulq($dst$$Register, $src$$Address);
8051 %}
8052 ins_pipe(ialu_reg_mem_alu0);
8053 %}
8054
8055 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8056 rFlagsReg cr)
8057 %{
8058 match(Set rax (DivI rax div));
8059 effect(KILL rdx, KILL cr);
8060
8061 ins_cost(30*100+10*100); // XXX
8062 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8063 "jne,s normal\n\t"
8064 "xorl rdx, rdx\n\t"
8065 "cmpl $div, -1\n\t"
8066 "je,s done\n"
8067 "normal: cdql\n\t"
8068 "idivl $div\n"
8069 "done:" %}
8070 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8071 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8072 ins_pipe(ialu_reg_reg_alu0);
8073 %}
8074
8075 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8076 rFlagsReg cr)
8077 %{
8078 match(Set rax (DivL rax div));
8079 effect(KILL rdx, KILL cr);
8080
8081 ins_cost(30*100+10*100); // XXX
8082 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8083 "cmpq rax, rdx\n\t"
8084 "jne,s normal\n\t"
8085 "xorl rdx, rdx\n\t"
8086 "cmpq $div, -1\n\t"
8087 "je,s done\n"
8088 "normal: cdqq\n\t"
8089 "idivq $div\n"
8090 "done:" %}
8091 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8092 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8093 ins_pipe(ialu_reg_reg_alu0);
8094 %}
8095
8096 // Integer DIVMOD with Register, both quotient and mod results
8097 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8098 rFlagsReg cr)
8099 %{
8100 match(DivModI rax div);
8101 effect(KILL cr);
8102
8103 ins_cost(30*100+10*100); // XXX
8104 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8105 "jne,s normal\n\t"
8106 "xorl rdx, rdx\n\t"
8107 "cmpl $div, -1\n\t"
8108 "je,s done\n"
8109 "normal: cdql\n\t"
8110 "idivl $div\n"
8111 "done:" %}
8112 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8113 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8114 ins_pipe(pipe_slow);
8115 %}
8116
8117 // Long DIVMOD with Register, both quotient and mod results
8118 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8119 rFlagsReg cr)
8120 %{
8121 match(DivModL rax div);
8122 effect(KILL cr);
8123
8124 ins_cost(30*100+10*100); // XXX
8125 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8126 "cmpq rax, rdx\n\t"
8127 "jne,s normal\n\t"
8128 "xorl rdx, rdx\n\t"
8129 "cmpq $div, -1\n\t"
8130 "je,s done\n"
8131 "normal: cdqq\n\t"
8132 "idivq $div\n"
8133 "done:" %}
8134 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8135 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8136 ins_pipe(pipe_slow);
8137 %}
8138
8139 //----------- DivL-By-Constant-Expansions--------------------------------------
8140 // DivI cases are handled by the compiler
8141
8142 // Magic constant, reciprocal of 10
8143 instruct loadConL_0x6666666666666667(rRegL dst)
8144 %{
8145 effect(DEF dst);
8146
8147 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8148 ins_encode(load_immL(dst, 0x6666666666666667));
8149 ins_pipe(ialu_reg);
8150 %}
8151
8152 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8153 %{
8154 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8155
8156 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8157 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8158 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8159 ins_pipe(ialu_reg_reg_alu0);
8160 %}
8161
8162 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8163 %{
8164 effect(USE_DEF dst, KILL cr);
8165
8166 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8167 opcode(0xC1, 0x7); /* C1 /7 ib */
8168 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8169 ins_pipe(ialu_reg);
8170 %}
8171
8172 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8173 %{
8174 effect(USE_DEF dst, KILL cr);
8175
8176 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8177 opcode(0xC1, 0x7); /* C1 /7 ib */
8178 ins_encode(reg_opc_imm_wide(dst, 0x2));
8179 ins_pipe(ialu_reg);
8180 %}
8181
8182 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8183 %{
8184 match(Set dst (DivL src div));
8185
8186 ins_cost((5+8)*100);
8187 expand %{
8188 rax_RegL rax; // Killed temp
8189 rFlagsReg cr; // Killed
8190 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8191 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8192 sarL_rReg_63(src, cr); // sarq src, 63
8193 sarL_rReg_2(dst, cr); // sarq rdx, 2
8194 subL_rReg(dst, src, cr); // subl rdx, src
8195 %}
8196 %}
8197
8198 //-----------------------------------------------------------------------------
8199
8200 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8201 rFlagsReg cr)
8202 %{
8203 match(Set rdx (ModI rax div));
8204 effect(KILL rax, KILL cr);
8205
8206 ins_cost(300); // XXX
8207 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8208 "jne,s normal\n\t"
8209 "xorl rdx, rdx\n\t"
8210 "cmpl $div, -1\n\t"
8211 "je,s done\n"
8212 "normal: cdql\n\t"
8213 "idivl $div\n"
8214 "done:" %}
8215 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8216 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8217 ins_pipe(ialu_reg_reg_alu0);
8218 %}
8219
8220 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8221 rFlagsReg cr)
8222 %{
8223 match(Set rdx (ModL rax div));
8224 effect(KILL rax, KILL cr);
8225
8226 ins_cost(300); // XXX
8227 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8228 "cmpq rax, rdx\n\t"
8229 "jne,s normal\n\t"
8230 "xorl rdx, rdx\n\t"
8231 "cmpq $div, -1\n\t"
8232 "je,s done\n"
8233 "normal: cdqq\n\t"
8234 "idivq $div\n"
8235 "done:" %}
8236 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8237 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8238 ins_pipe(ialu_reg_reg_alu0);
8239 %}
8240
8241 // Integer Shift Instructions
8242 // Shift Left by one
8243 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8244 %{
8245 match(Set dst (LShiftI dst shift));
8246 effect(KILL cr);
8247
8248 format %{ "sall $dst, $shift" %}
8249 opcode(0xD1, 0x4); /* D1 /4 */
8250 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8251 ins_pipe(ialu_reg);
8252 %}
8253
8254 // Shift Left by one
8255 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8256 %{
8257 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8258 effect(KILL cr);
8259
8260 format %{ "sall $dst, $shift\t" %}
8261 opcode(0xD1, 0x4); /* D1 /4 */
8262 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8263 ins_pipe(ialu_mem_imm);
8264 %}
8265
8266 // Shift Left by 8-bit immediate
8267 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8268 %{
8269 match(Set dst (LShiftI dst shift));
8270 effect(KILL cr);
8271
8272 format %{ "sall $dst, $shift" %}
8273 opcode(0xC1, 0x4); /* C1 /4 ib */
8274 ins_encode(reg_opc_imm(dst, shift));
8275 ins_pipe(ialu_reg);
8276 %}
8277
8278 // Shift Left by 8-bit immediate
8279 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8280 %{
8281 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8282 effect(KILL cr);
8283
8284 format %{ "sall $dst, $shift" %}
8285 opcode(0xC1, 0x4); /* C1 /4 ib */
8286 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8287 ins_pipe(ialu_mem_imm);
8288 %}
8289
8290 // Shift Left by variable
8291 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8292 %{
8293 match(Set dst (LShiftI dst shift));
8294 effect(KILL cr);
8295
8296 format %{ "sall $dst, $shift" %}
8297 opcode(0xD3, 0x4); /* D3 /4 */
8298 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8299 ins_pipe(ialu_reg_reg);
8300 %}
8301
8302 // Shift Left by variable
8303 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8304 %{
8305 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8306 effect(KILL cr);
8307
8308 format %{ "sall $dst, $shift" %}
8309 opcode(0xD3, 0x4); /* D3 /4 */
8310 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8311 ins_pipe(ialu_mem_reg);
8312 %}
8313
8314 // Arithmetic shift right by one
8315 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8316 %{
8317 match(Set dst (RShiftI dst shift));
8318 effect(KILL cr);
8319
8320 format %{ "sarl $dst, $shift" %}
8321 opcode(0xD1, 0x7); /* D1 /7 */
8322 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8323 ins_pipe(ialu_reg);
8324 %}
8325
8326 // Arithmetic shift right by one
8327 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8328 %{
8329 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8330 effect(KILL cr);
8331
8332 format %{ "sarl $dst, $shift" %}
8333 opcode(0xD1, 0x7); /* D1 /7 */
8334 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8335 ins_pipe(ialu_mem_imm);
8336 %}
8337
8338 // Arithmetic Shift Right by 8-bit immediate
8339 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8340 %{
8341 match(Set dst (RShiftI dst shift));
8342 effect(KILL cr);
8343
8344 format %{ "sarl $dst, $shift" %}
8345 opcode(0xC1, 0x7); /* C1 /7 ib */
8346 ins_encode(reg_opc_imm(dst, shift));
8347 ins_pipe(ialu_mem_imm);
8348 %}
8349
8350 // Arithmetic Shift Right by 8-bit immediate
8351 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8352 %{
8353 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8354 effect(KILL cr);
8355
8356 format %{ "sarl $dst, $shift" %}
8357 opcode(0xC1, 0x7); /* C1 /7 ib */
8358 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8359 ins_pipe(ialu_mem_imm);
8360 %}
8361
8362 // Arithmetic Shift Right by variable
8363 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8364 %{
8365 match(Set dst (RShiftI dst shift));
8366 effect(KILL cr);
8367
8368 format %{ "sarl $dst, $shift" %}
8369 opcode(0xD3, 0x7); /* D3 /7 */
8370 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8371 ins_pipe(ialu_reg_reg);
8372 %}
8373
8374 // Arithmetic Shift Right by variable
8375 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8376 %{
8377 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8378 effect(KILL cr);
8379
8380 format %{ "sarl $dst, $shift" %}
8381 opcode(0xD3, 0x7); /* D3 /7 */
8382 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8383 ins_pipe(ialu_mem_reg);
8384 %}
8385
8386 // Logical shift right by one
8387 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8388 %{
8389 match(Set dst (URShiftI dst shift));
8390 effect(KILL cr);
8391
8392 format %{ "shrl $dst, $shift" %}
8393 opcode(0xD1, 0x5); /* D1 /5 */
8394 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8395 ins_pipe(ialu_reg);
8396 %}
8397
8398 // Logical shift right by one
8399 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8400 %{
8401 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8402 effect(KILL cr);
8403
8404 format %{ "shrl $dst, $shift" %}
8405 opcode(0xD1, 0x5); /* D1 /5 */
8406 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8407 ins_pipe(ialu_mem_imm);
8408 %}
8409
8410 // Logical Shift Right by 8-bit immediate
8411 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8412 %{
8413 match(Set dst (URShiftI dst shift));
8414 effect(KILL cr);
8415
8416 format %{ "shrl $dst, $shift" %}
8417 opcode(0xC1, 0x5); /* C1 /5 ib */
8418 ins_encode(reg_opc_imm(dst, shift));
8419 ins_pipe(ialu_reg);
8420 %}
8421
8422 // Logical Shift Right by 8-bit immediate
8423 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8424 %{
8425 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8426 effect(KILL cr);
8427
8428 format %{ "shrl $dst, $shift" %}
8429 opcode(0xC1, 0x5); /* C1 /5 ib */
8430 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8431 ins_pipe(ialu_mem_imm);
8432 %}
8433
8434 // Logical Shift Right by variable
8435 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8436 %{
8437 match(Set dst (URShiftI dst shift));
8438 effect(KILL cr);
8439
8440 format %{ "shrl $dst, $shift" %}
8441 opcode(0xD3, 0x5); /* D3 /5 */
8442 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8443 ins_pipe(ialu_reg_reg);
8444 %}
8445
8446 // Logical Shift Right by variable
8447 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8448 %{
8449 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8450 effect(KILL cr);
8451
8452 format %{ "shrl $dst, $shift" %}
8453 opcode(0xD3, 0x5); /* D3 /5 */
8454 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8455 ins_pipe(ialu_mem_reg);
8456 %}
8457
8458 // Long Shift Instructions
8459 // Shift Left by one
8460 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8461 %{
8462 match(Set dst (LShiftL dst shift));
8463 effect(KILL cr);
8464
8465 format %{ "salq $dst, $shift" %}
8466 opcode(0xD1, 0x4); /* D1 /4 */
8467 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8468 ins_pipe(ialu_reg);
8469 %}
8470
8471 // Shift Left by one
8472 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8473 %{
8474 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8475 effect(KILL cr);
8476
8477 format %{ "salq $dst, $shift" %}
8478 opcode(0xD1, 0x4); /* D1 /4 */
8479 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8480 ins_pipe(ialu_mem_imm);
8481 %}
8482
8483 // Shift Left by 8-bit immediate
8484 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8485 %{
8486 match(Set dst (LShiftL dst shift));
8487 effect(KILL cr);
8488
8489 format %{ "salq $dst, $shift" %}
8490 opcode(0xC1, 0x4); /* C1 /4 ib */
8491 ins_encode(reg_opc_imm_wide(dst, shift));
8492 ins_pipe(ialu_reg);
8493 %}
8494
8495 // Shift Left by 8-bit immediate
8496 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8497 %{
8498 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8499 effect(KILL cr);
8500
8501 format %{ "salq $dst, $shift" %}
8502 opcode(0xC1, 0x4); /* C1 /4 ib */
8503 ins_encode(REX_mem_wide(dst), OpcP,
8504 RM_opc_mem(secondary, dst), Con8or32(shift));
8505 ins_pipe(ialu_mem_imm);
8506 %}
8507
8508 // Shift Left by variable
8509 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8510 %{
8511 match(Set dst (LShiftL dst shift));
8512 effect(KILL cr);
8513
8514 format %{ "salq $dst, $shift" %}
8515 opcode(0xD3, 0x4); /* D3 /4 */
8516 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8517 ins_pipe(ialu_reg_reg);
8518 %}
8519
8520 // Shift Left by variable
8521 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8522 %{
8523 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8524 effect(KILL cr);
8525
8526 format %{ "salq $dst, $shift" %}
8527 opcode(0xD3, 0x4); /* D3 /4 */
8528 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8529 ins_pipe(ialu_mem_reg);
8530 %}
8531
8532 // Arithmetic shift right by one
8533 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8534 %{
8535 match(Set dst (RShiftL dst shift));
8536 effect(KILL cr);
8537
8538 format %{ "sarq $dst, $shift" %}
8539 opcode(0xD1, 0x7); /* D1 /7 */
8540 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8541 ins_pipe(ialu_reg);
8542 %}
8543
8544 // Arithmetic shift right by one
8545 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8546 %{
8547 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8548 effect(KILL cr);
8549
8550 format %{ "sarq $dst, $shift" %}
8551 opcode(0xD1, 0x7); /* D1 /7 */
8552 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8553 ins_pipe(ialu_mem_imm);
8554 %}
8555
8556 // Arithmetic Shift Right by 8-bit immediate
8557 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8558 %{
8559 match(Set dst (RShiftL dst shift));
8560 effect(KILL cr);
8561
8562 format %{ "sarq $dst, $shift" %}
8563 opcode(0xC1, 0x7); /* C1 /7 ib */
8564 ins_encode(reg_opc_imm_wide(dst, shift));
8565 ins_pipe(ialu_mem_imm);
8566 %}
8567
8568 // Arithmetic Shift Right by 8-bit immediate
8569 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8570 %{
8571 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8572 effect(KILL cr);
8573
8574 format %{ "sarq $dst, $shift" %}
8575 opcode(0xC1, 0x7); /* C1 /7 ib */
8576 ins_encode(REX_mem_wide(dst), OpcP,
8577 RM_opc_mem(secondary, dst), Con8or32(shift));
8578 ins_pipe(ialu_mem_imm);
8579 %}
8580
8581 // Arithmetic Shift Right by variable
8582 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8583 %{
8584 match(Set dst (RShiftL dst shift));
8585 effect(KILL cr);
8586
8587 format %{ "sarq $dst, $shift" %}
8588 opcode(0xD3, 0x7); /* D3 /7 */
8589 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8590 ins_pipe(ialu_reg_reg);
8591 %}
8592
8593 // Arithmetic Shift Right by variable
8594 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8595 %{
8596 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8597 effect(KILL cr);
8598
8599 format %{ "sarq $dst, $shift" %}
8600 opcode(0xD3, 0x7); /* D3 /7 */
8601 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8602 ins_pipe(ialu_mem_reg);
8603 %}
8604
8605 // Logical shift right by one
8606 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8607 %{
8608 match(Set dst (URShiftL dst shift));
8609 effect(KILL cr);
8610
8611 format %{ "shrq $dst, $shift" %}
8612 opcode(0xD1, 0x5); /* D1 /5 */
8613 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8614 ins_pipe(ialu_reg);
8615 %}
8616
8617 // Logical shift right by one
8618 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8619 %{
8620 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8621 effect(KILL cr);
8622
8623 format %{ "shrq $dst, $shift" %}
8624 opcode(0xD1, 0x5); /* D1 /5 */
8625 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8626 ins_pipe(ialu_mem_imm);
8627 %}
8628
8629 // Logical Shift Right by 8-bit immediate
8630 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8631 %{
8632 match(Set dst (URShiftL dst shift));
8633 effect(KILL cr);
8634
8635 format %{ "shrq $dst, $shift" %}
8636 opcode(0xC1, 0x5); /* C1 /5 ib */
8637 ins_encode(reg_opc_imm_wide(dst, shift));
8638 ins_pipe(ialu_reg);
8639 %}
8640
8641
8642 // Logical Shift Right by 8-bit immediate
8643 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8644 %{
8645 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8646 effect(KILL cr);
8647
8648 format %{ "shrq $dst, $shift" %}
8649 opcode(0xC1, 0x5); /* C1 /5 ib */
8650 ins_encode(REX_mem_wide(dst), OpcP,
8651 RM_opc_mem(secondary, dst), Con8or32(shift));
8652 ins_pipe(ialu_mem_imm);
8653 %}
8654
8655 // Logical Shift Right by variable
8656 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8657 %{
8658 match(Set dst (URShiftL dst shift));
8659 effect(KILL cr);
8660
8661 format %{ "shrq $dst, $shift" %}
8662 opcode(0xD3, 0x5); /* D3 /5 */
8663 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8664 ins_pipe(ialu_reg_reg);
8665 %}
8666
8667 // Logical Shift Right by variable
8668 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8669 %{
8670 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8671 effect(KILL cr);
8672
8673 format %{ "shrq $dst, $shift" %}
8674 opcode(0xD3, 0x5); /* D3 /5 */
8675 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8676 ins_pipe(ialu_mem_reg);
8677 %}
8678
8679 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8680 // This idiom is used by the compiler for the i2b bytecode.
8681 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8682 %{
8683 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8684
8685 format %{ "movsbl $dst, $src\t# i2b" %}
8686 opcode(0x0F, 0xBE);
8687 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8688 ins_pipe(ialu_reg_reg);
8689 %}
8690
8691 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8692 // This idiom is used by the compiler the i2s bytecode.
8693 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8694 %{
8695 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8696
8697 format %{ "movswl $dst, $src\t# i2s" %}
8698 opcode(0x0F, 0xBF);
8699 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8700 ins_pipe(ialu_reg_reg);
8701 %}
8702
8703 // ROL/ROR instructions
8704
8705 // ROL expand
8706 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8707 effect(KILL cr, USE_DEF dst);
8708
8709 format %{ "roll $dst" %}
8710 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8711 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8712 ins_pipe(ialu_reg);
8713 %}
8714
8715 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8716 effect(USE_DEF dst, USE shift, KILL cr);
8717
8718 format %{ "roll $dst, $shift" %}
8719 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8720 ins_encode( reg_opc_imm(dst, shift) );
8721 ins_pipe(ialu_reg);
8722 %}
8723
8724 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8725 %{
8726 effect(USE_DEF dst, USE shift, KILL cr);
8727
8728 format %{ "roll $dst, $shift" %}
8729 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8730 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8731 ins_pipe(ialu_reg_reg);
8732 %}
8733 // end of ROL expand
8734
8735 // Rotate Left by one
8736 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8737 %{
8738 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8739
8740 expand %{
8741 rolI_rReg_imm1(dst, cr);
8742 %}
8743 %}
8744
8745 // Rotate Left by 8-bit immediate
8746 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8747 %{
8748 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8749 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8750
8751 expand %{
8752 rolI_rReg_imm8(dst, lshift, cr);
8753 %}
8754 %}
8755
8756 // Rotate Left by variable
8757 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8758 %{
8759 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8760
8761 expand %{
8762 rolI_rReg_CL(dst, shift, cr);
8763 %}
8764 %}
8765
8766 // Rotate Left by variable
8767 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8768 %{
8769 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8770
8771 expand %{
8772 rolI_rReg_CL(dst, shift, cr);
8773 %}
8774 %}
8775
8776 // ROR expand
8777 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8778 %{
8779 effect(USE_DEF dst, KILL cr);
8780
8781 format %{ "rorl $dst" %}
8782 opcode(0xD1, 0x1); /* D1 /1 */
8783 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8784 ins_pipe(ialu_reg);
8785 %}
8786
8787 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8788 %{
8789 effect(USE_DEF dst, USE shift, KILL cr);
8790
8791 format %{ "rorl $dst, $shift" %}
8792 opcode(0xC1, 0x1); /* C1 /1 ib */
8793 ins_encode(reg_opc_imm(dst, shift));
8794 ins_pipe(ialu_reg);
8795 %}
8796
8797 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8798 %{
8799 effect(USE_DEF dst, USE shift, KILL cr);
8800
8801 format %{ "rorl $dst, $shift" %}
8802 opcode(0xD3, 0x1); /* D3 /1 */
8803 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8804 ins_pipe(ialu_reg_reg);
8805 %}
8806 // end of ROR expand
8807
8808 // Rotate Right by one
8809 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8810 %{
8811 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8812
8813 expand %{
8814 rorI_rReg_imm1(dst, cr);
8815 %}
8816 %}
8817
8818 // Rotate Right by 8-bit immediate
8819 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8820 %{
8821 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8822 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8823
8824 expand %{
8825 rorI_rReg_imm8(dst, rshift, cr);
8826 %}
8827 %}
8828
8829 // Rotate Right by variable
8830 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8831 %{
8832 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8833
8834 expand %{
8835 rorI_rReg_CL(dst, shift, cr);
8836 %}
8837 %}
8838
8839 // Rotate Right by variable
8840 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8841 %{
8842 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8843
8844 expand %{
8845 rorI_rReg_CL(dst, shift, cr);
8846 %}
8847 %}
8848
8849 // for long rotate
8850 // ROL expand
8851 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8852 effect(USE_DEF dst, KILL cr);
8853
8854 format %{ "rolq $dst" %}
8855 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8856 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8857 ins_pipe(ialu_reg);
8858 %}
8859
8860 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8861 effect(USE_DEF dst, USE shift, KILL cr);
8862
8863 format %{ "rolq $dst, $shift" %}
8864 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8865 ins_encode( reg_opc_imm_wide(dst, shift) );
8866 ins_pipe(ialu_reg);
8867 %}
8868
8869 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8870 %{
8871 effect(USE_DEF dst, USE shift, KILL cr);
8872
8873 format %{ "rolq $dst, $shift" %}
8874 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8875 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8876 ins_pipe(ialu_reg_reg);
8877 %}
8878 // end of ROL expand
8879
8880 // Rotate Left by one
8881 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8882 %{
8883 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8884
8885 expand %{
8886 rolL_rReg_imm1(dst, cr);
8887 %}
8888 %}
8889
8890 // Rotate Left by 8-bit immediate
8891 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8892 %{
8893 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8894 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8895
8896 expand %{
8897 rolL_rReg_imm8(dst, lshift, cr);
8898 %}
8899 %}
8900
8901 // Rotate Left by variable
8902 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8903 %{
8904 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8905
8906 expand %{
8907 rolL_rReg_CL(dst, shift, cr);
8908 %}
8909 %}
8910
8911 // Rotate Left by variable
8912 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8913 %{
8914 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8915
8916 expand %{
8917 rolL_rReg_CL(dst, shift, cr);
8918 %}
8919 %}
8920
8921 // ROR expand
8922 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8923 %{
8924 effect(USE_DEF dst, KILL cr);
8925
8926 format %{ "rorq $dst" %}
8927 opcode(0xD1, 0x1); /* D1 /1 */
8928 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8929 ins_pipe(ialu_reg);
8930 %}
8931
8932 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8933 %{
8934 effect(USE_DEF dst, USE shift, KILL cr);
8935
8936 format %{ "rorq $dst, $shift" %}
8937 opcode(0xC1, 0x1); /* C1 /1 ib */
8938 ins_encode(reg_opc_imm_wide(dst, shift));
8939 ins_pipe(ialu_reg);
8940 %}
8941
8942 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8943 %{
8944 effect(USE_DEF dst, USE shift, KILL cr);
8945
8946 format %{ "rorq $dst, $shift" %}
8947 opcode(0xD3, 0x1); /* D3 /1 */
8948 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8949 ins_pipe(ialu_reg_reg);
8950 %}
8951 // end of ROR expand
8952
8953 // Rotate Right by one
8954 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8955 %{
8956 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8957
8958 expand %{
8959 rorL_rReg_imm1(dst, cr);
8960 %}
8961 %}
8962
8963 // Rotate Right by 8-bit immediate
8964 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8965 %{
8966 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8967 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8968
8969 expand %{
8970 rorL_rReg_imm8(dst, rshift, cr);
8971 %}
8972 %}
8973
8974 // Rotate Right by variable
8975 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8976 %{
8977 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8978
8979 expand %{
8980 rorL_rReg_CL(dst, shift, cr);
8981 %}
8982 %}
8983
8984 // Rotate Right by variable
8985 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8986 %{
8987 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8988
8989 expand %{
8990 rorL_rReg_CL(dst, shift, cr);
8991 %}
8992 %}
8993
8994 // Logical Instructions
8995
8996 // Integer Logical Instructions
8997
8998 // And Instructions
8999 // And Register with Register
9000 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9001 %{
9002 match(Set dst (AndI dst src));
9003 effect(KILL cr);
9004
9005 format %{ "andl $dst, $src\t# int" %}
9006 opcode(0x23);
9007 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9008 ins_pipe(ialu_reg_reg);
9009 %}
9010
9011 // And Register with Immediate 255
9012 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9013 %{
9014 match(Set dst (AndI dst src));
9015
9016 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9017 opcode(0x0F, 0xB6);
9018 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9019 ins_pipe(ialu_reg);
9020 %}
9021
9022 // And Register with Immediate 255 and promote to long
9023 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9024 %{
9025 match(Set dst (ConvI2L (AndI src mask)));
9026
9027 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9028 opcode(0x0F, 0xB6);
9029 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9030 ins_pipe(ialu_reg);
9031 %}
9032
9033 // And Register with Immediate 65535
9034 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9035 %{
9036 match(Set dst (AndI dst src));
9037
9038 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9039 opcode(0x0F, 0xB7);
9040 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9041 ins_pipe(ialu_reg);
9042 %}
9043
9044 // And Register with Immediate 65535 and promote to long
9045 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9046 %{
9047 match(Set dst (ConvI2L (AndI src mask)));
9048
9049 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9050 opcode(0x0F, 0xB7);
9051 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9052 ins_pipe(ialu_reg);
9053 %}
9054
9055 // And Register with Immediate
9056 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9057 %{
9058 match(Set dst (AndI dst src));
9059 effect(KILL cr);
9060
9061 format %{ "andl $dst, $src\t# int" %}
9062 opcode(0x81, 0x04); /* Opcode 81 /4 */
9063 ins_encode(OpcSErm(dst, src), Con8or32(src));
9064 ins_pipe(ialu_reg);
9065 %}
9066
9067 // And Register with Memory
9068 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9069 %{
9070 match(Set dst (AndI dst (LoadI src)));
9071 effect(KILL cr);
9072
9073 ins_cost(125);
9074 format %{ "andl $dst, $src\t# int" %}
9075 opcode(0x23);
9076 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9077 ins_pipe(ialu_reg_mem);
9078 %}
9079
9080 // And Memory with Register
9081 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9082 %{
9083 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9084 effect(KILL cr);
9085
9086 ins_cost(150);
9087 format %{ "andl $dst, $src\t# int" %}
9088 opcode(0x21); /* Opcode 21 /r */
9089 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9090 ins_pipe(ialu_mem_reg);
9091 %}
9092
9093 // And Memory with Immediate
9094 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9095 %{
9096 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9097 effect(KILL cr);
9098
9099 ins_cost(125);
9100 format %{ "andl $dst, $src\t# int" %}
9101 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9102 ins_encode(REX_mem(dst), OpcSE(src),
9103 RM_opc_mem(secondary, dst), Con8or32(src));
9104 ins_pipe(ialu_mem_imm);
9105 %}
9106
9107 // Or Instructions
9108 // Or Register with Register
9109 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9110 %{
9111 match(Set dst (OrI dst src));
9112 effect(KILL cr);
9113
9114 format %{ "orl $dst, $src\t# int" %}
9115 opcode(0x0B);
9116 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9117 ins_pipe(ialu_reg_reg);
9118 %}
9119
9120 // Or Register with Immediate
9121 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9122 %{
9123 match(Set dst (OrI dst src));
9124 effect(KILL cr);
9125
9126 format %{ "orl $dst, $src\t# int" %}
9127 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9128 ins_encode(OpcSErm(dst, src), Con8or32(src));
9129 ins_pipe(ialu_reg);
9130 %}
9131
9132 // Or Register with Memory
9133 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9134 %{
9135 match(Set dst (OrI dst (LoadI src)));
9136 effect(KILL cr);
9137
9138 ins_cost(125);
9139 format %{ "orl $dst, $src\t# int" %}
9140 opcode(0x0B);
9141 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9142 ins_pipe(ialu_reg_mem);
9143 %}
9144
9145 // Or Memory with Register
9146 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9147 %{
9148 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9149 effect(KILL cr);
9150
9151 ins_cost(150);
9152 format %{ "orl $dst, $src\t# int" %}
9153 opcode(0x09); /* Opcode 09 /r */
9154 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9155 ins_pipe(ialu_mem_reg);
9156 %}
9157
9158 // Or Memory with Immediate
9159 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9160 %{
9161 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9162 effect(KILL cr);
9163
9164 ins_cost(125);
9165 format %{ "orl $dst, $src\t# int" %}
9166 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9167 ins_encode(REX_mem(dst), OpcSE(src),
9168 RM_opc_mem(secondary, dst), Con8or32(src));
9169 ins_pipe(ialu_mem_imm);
9170 %}
9171
9172 // Xor Instructions
9173 // Xor Register with Register
9174 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9175 %{
9176 match(Set dst (XorI dst src));
9177 effect(KILL cr);
9178
9179 format %{ "xorl $dst, $src\t# int" %}
9180 opcode(0x33);
9181 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9182 ins_pipe(ialu_reg_reg);
9183 %}
9184
9185 // Xor Register with Immediate -1
9186 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9187 match(Set dst (XorI dst imm));
9188
9189 format %{ "not $dst" %}
9190 ins_encode %{
9191 __ notl($dst$$Register);
9192 %}
9193 ins_pipe(ialu_reg);
9194 %}
9195
9196 // Xor Register with Immediate
9197 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9198 %{
9199 match(Set dst (XorI dst src));
9200 effect(KILL cr);
9201
9202 format %{ "xorl $dst, $src\t# int" %}
9203 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9204 ins_encode(OpcSErm(dst, src), Con8or32(src));
9205 ins_pipe(ialu_reg);
9206 %}
9207
9208 // Xor Register with Memory
9209 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9210 %{
9211 match(Set dst (XorI dst (LoadI src)));
9212 effect(KILL cr);
9213
9214 ins_cost(125);
9215 format %{ "xorl $dst, $src\t# int" %}
9216 opcode(0x33);
9217 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9218 ins_pipe(ialu_reg_mem);
9219 %}
9220
9221 // Xor Memory with Register
9222 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9223 %{
9224 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9225 effect(KILL cr);
9226
9227 ins_cost(150);
9228 format %{ "xorl $dst, $src\t# int" %}
9229 opcode(0x31); /* Opcode 31 /r */
9230 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9231 ins_pipe(ialu_mem_reg);
9232 %}
9233
9234 // Xor Memory with Immediate
9235 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9236 %{
9237 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9238 effect(KILL cr);
9239
9240 ins_cost(125);
9241 format %{ "xorl $dst, $src\t# int" %}
9242 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9243 ins_encode(REX_mem(dst), OpcSE(src),
9244 RM_opc_mem(secondary, dst), Con8or32(src));
9245 ins_pipe(ialu_mem_imm);
9246 %}
9247
9248
9249 // Long Logical Instructions
9250
9251 // And Instructions
9252 // And Register with Register
9253 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9254 %{
9255 match(Set dst (AndL dst src));
9256 effect(KILL cr);
9257
9258 format %{ "andq $dst, $src\t# long" %}
9259 opcode(0x23);
9260 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9261 ins_pipe(ialu_reg_reg);
9262 %}
9263
9264 // And Register with Immediate 255
9265 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9266 %{
9267 match(Set dst (AndL dst src));
9268
9269 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9270 opcode(0x0F, 0xB6);
9271 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9272 ins_pipe(ialu_reg);
9273 %}
9274
9275 // And Register with Immediate 65535
9276 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9277 %{
9278 match(Set dst (AndL dst src));
9279
9280 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9281 opcode(0x0F, 0xB7);
9282 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9283 ins_pipe(ialu_reg);
9284 %}
9285
9286 // And Register with Immediate
9287 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9288 %{
9289 match(Set dst (AndL dst src));
9290 effect(KILL cr);
9291
9292 format %{ "andq $dst, $src\t# long" %}
9293 opcode(0x81, 0x04); /* Opcode 81 /4 */
9294 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9295 ins_pipe(ialu_reg);
9296 %}
9297
9298 // And Register with Memory
9299 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9300 %{
9301 match(Set dst (AndL dst (LoadL src)));
9302 effect(KILL cr);
9303
9304 ins_cost(125);
9305 format %{ "andq $dst, $src\t# long" %}
9306 opcode(0x23);
9307 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9308 ins_pipe(ialu_reg_mem);
9309 %}
9310
9311 // And Memory with Register
9312 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9313 %{
9314 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9315 effect(KILL cr);
9316
9317 ins_cost(150);
9318 format %{ "andq $dst, $src\t# long" %}
9319 opcode(0x21); /* Opcode 21 /r */
9320 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9321 ins_pipe(ialu_mem_reg);
9322 %}
9323
9324 // And Memory with Immediate
9325 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9326 %{
9327 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9328 effect(KILL cr);
9329
9330 ins_cost(125);
9331 format %{ "andq $dst, $src\t# long" %}
9332 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9333 ins_encode(REX_mem_wide(dst), OpcSE(src),
9334 RM_opc_mem(secondary, dst), Con8or32(src));
9335 ins_pipe(ialu_mem_imm);
9336 %}
9337
9338 // Or Instructions
9339 // Or Register with Register
9340 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9341 %{
9342 match(Set dst (OrL dst src));
9343 effect(KILL cr);
9344
9345 format %{ "orq $dst, $src\t# long" %}
9346 opcode(0x0B);
9347 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9348 ins_pipe(ialu_reg_reg);
9349 %}
9350
9351 // Use any_RegP to match R15 (TLS register) without spilling.
9352 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9353 match(Set dst (OrL dst (CastP2X src)));
9354 effect(KILL cr);
9355
9356 format %{ "orq $dst, $src\t# long" %}
9357 opcode(0x0B);
9358 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9359 ins_pipe(ialu_reg_reg);
9360 %}
9361
9362
9363 // Or Register with Immediate
9364 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9365 %{
9366 match(Set dst (OrL dst src));
9367 effect(KILL cr);
9368
9369 format %{ "orq $dst, $src\t# long" %}
9370 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9371 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9372 ins_pipe(ialu_reg);
9373 %}
9374
9375 // Or Register with Memory
9376 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9377 %{
9378 match(Set dst (OrL dst (LoadL src)));
9379 effect(KILL cr);
9380
9381 ins_cost(125);
9382 format %{ "orq $dst, $src\t# long" %}
9383 opcode(0x0B);
9384 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9385 ins_pipe(ialu_reg_mem);
9386 %}
9387
9388 // Or Memory with Register
9389 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9390 %{
9391 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9392 effect(KILL cr);
9393
9394 ins_cost(150);
9395 format %{ "orq $dst, $src\t# long" %}
9396 opcode(0x09); /* Opcode 09 /r */
9397 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9398 ins_pipe(ialu_mem_reg);
9399 %}
9400
9401 // Or Memory with Immediate
9402 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9403 %{
9404 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9405 effect(KILL cr);
9406
9407 ins_cost(125);
9408 format %{ "orq $dst, $src\t# long" %}
9409 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9410 ins_encode(REX_mem_wide(dst), OpcSE(src),
9411 RM_opc_mem(secondary, dst), Con8or32(src));
9412 ins_pipe(ialu_mem_imm);
9413 %}
9414
9415 // Xor Instructions
9416 // Xor Register with Register
9417 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9418 %{
9419 match(Set dst (XorL dst src));
9420 effect(KILL cr);
9421
9422 format %{ "xorq $dst, $src\t# long" %}
9423 opcode(0x33);
9424 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9425 ins_pipe(ialu_reg_reg);
9426 %}
9427
9428 // Xor Register with Immediate -1
9429 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9430 match(Set dst (XorL dst imm));
9431
9432 format %{ "notq $dst" %}
9433 ins_encode %{
9434 __ notq($dst$$Register);
9435 %}
9436 ins_pipe(ialu_reg);
9437 %}
9438
9439 // Xor Register with Immediate
9440 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9441 %{
9442 match(Set dst (XorL dst src));
9443 effect(KILL cr);
9444
9445 format %{ "xorq $dst, $src\t# long" %}
9446 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9447 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9448 ins_pipe(ialu_reg);
9449 %}
9450
9451 // Xor Register with Memory
9452 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9453 %{
9454 match(Set dst (XorL dst (LoadL src)));
9455 effect(KILL cr);
9456
9457 ins_cost(125);
9458 format %{ "xorq $dst, $src\t# long" %}
9459 opcode(0x33);
9460 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9461 ins_pipe(ialu_reg_mem);
9462 %}
9463
9464 // Xor Memory with Register
9465 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9466 %{
9467 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9468 effect(KILL cr);
9469
9470 ins_cost(150);
9471 format %{ "xorq $dst, $src\t# long" %}
9472 opcode(0x31); /* Opcode 31 /r */
9473 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9474 ins_pipe(ialu_mem_reg);
9475 %}
9476
9477 // Xor Memory with Immediate
9478 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9479 %{
9480 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9481 effect(KILL cr);
9482
9483 ins_cost(125);
9484 format %{ "xorq $dst, $src\t# long" %}
9485 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9486 ins_encode(REX_mem_wide(dst), OpcSE(src),
9487 RM_opc_mem(secondary, dst), Con8or32(src));
9488 ins_pipe(ialu_mem_imm);
9489 %}
9490
9491 // Convert Int to Boolean
9492 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9493 %{
9494 match(Set dst (Conv2B src));
9495 effect(KILL cr);
9496
9497 format %{ "testl $src, $src\t# ci2b\n\t"
9498 "setnz $dst\n\t"
9499 "movzbl $dst, $dst" %}
9500 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9501 setNZ_reg(dst),
9502 REX_reg_breg(dst, dst), // movzbl
9503 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9504 ins_pipe(pipe_slow); // XXX
9505 %}
9506
9507 // Convert Pointer to Boolean
9508 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9509 %{
9510 match(Set dst (Conv2B src));
9511 effect(KILL cr);
9512
9513 format %{ "testq $src, $src\t# cp2b\n\t"
9514 "setnz $dst\n\t"
9515 "movzbl $dst, $dst" %}
9516 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9517 setNZ_reg(dst),
9518 REX_reg_breg(dst, dst), // movzbl
9519 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9520 ins_pipe(pipe_slow); // XXX
9521 %}
9522
9523 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9524 %{
9525 match(Set dst (CmpLTMask p q));
9526 effect(KILL cr);
9527
9528 ins_cost(400);
9529 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9530 "setlt $dst\n\t"
9531 "movzbl $dst, $dst\n\t"
9532 "negl $dst" %}
9533 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9534 setLT_reg(dst),
9535 REX_reg_breg(dst, dst), // movzbl
9536 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9537 neg_reg(dst));
9538 ins_pipe(pipe_slow);
9539 %}
9540
9541 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9542 %{
9543 match(Set dst (CmpLTMask dst zero));
9544 effect(KILL cr);
9545
9546 ins_cost(100);
9547 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9548 ins_encode %{
9549 __ sarl($dst$$Register, 31);
9550 %}
9551 ins_pipe(ialu_reg);
9552 %}
9553
9554 /* Better to save a register than avoid a branch */
9555 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9556 %{
9557 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9558 effect(KILL cr);
9559 ins_cost(300);
9560 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9561 "jge done\n\t"
9562 "addl $p,$y\n"
9563 "done: " %}
9564 ins_encode %{
9565 Register Rp = $p$$Register;
9566 Register Rq = $q$$Register;
9567 Register Ry = $y$$Register;
9568 Label done;
9569 __ subl(Rp, Rq);
9570 __ jccb(Assembler::greaterEqual, done);
9571 __ addl(Rp, Ry);
9572 __ bind(done);
9573 %}
9574 ins_pipe(pipe_cmplt);
9575 %}
9576
9577 /* Better to save a register than avoid a branch */
9578 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9579 %{
9580 match(Set y (AndI (CmpLTMask p q) y));
9581 effect(KILL cr);
9582
9583 ins_cost(300);
9584
9585 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9586 "jlt done\n\t"
9587 "xorl $y, $y\n"
9588 "done: " %}
9589 ins_encode %{
9590 Register Rp = $p$$Register;
9591 Register Rq = $q$$Register;
9592 Register Ry = $y$$Register;
9593 Label done;
9594 __ cmpl(Rp, Rq);
9595 __ jccb(Assembler::less, done);
9596 __ xorl(Ry, Ry);
9597 __ bind(done);
9598 %}
9599 ins_pipe(pipe_cmplt);
9600 %}
9601
9602
9603 //---------- FP Instructions------------------------------------------------
9604
9605 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9606 %{
9607 match(Set cr (CmpF src1 src2));
9608
9609 ins_cost(145);
9610 format %{ "ucomiss $src1, $src2\n\t"
9611 "jnp,s exit\n\t"
9612 "pushfq\t# saw NaN, set CF\n\t"
9613 "andq [rsp], #0xffffff2b\n\t"
9614 "popfq\n"
9615 "exit:" %}
9616 ins_encode %{
9617 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9618 emit_cmpfp_fixup(_masm);
9619 %}
9620 ins_pipe(pipe_slow);
9621 %}
9622
9623 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9624 match(Set cr (CmpF src1 src2));
9625
9626 ins_cost(100);
9627 format %{ "ucomiss $src1, $src2" %}
9628 ins_encode %{
9629 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9630 %}
9631 ins_pipe(pipe_slow);
9632 %}
9633
9634 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9635 %{
9636 match(Set cr (CmpF src1 (LoadF src2)));
9637
9638 ins_cost(145);
9639 format %{ "ucomiss $src1, $src2\n\t"
9640 "jnp,s exit\n\t"
9641 "pushfq\t# saw NaN, set CF\n\t"
9642 "andq [rsp], #0xffffff2b\n\t"
9643 "popfq\n"
9644 "exit:" %}
9645 ins_encode %{
9646 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9647 emit_cmpfp_fixup(_masm);
9648 %}
9649 ins_pipe(pipe_slow);
9650 %}
9651
9652 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9653 match(Set cr (CmpF src1 (LoadF src2)));
9654
9655 ins_cost(100);
9656 format %{ "ucomiss $src1, $src2" %}
9657 ins_encode %{
9658 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9659 %}
9660 ins_pipe(pipe_slow);
9661 %}
9662
9663 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9664 match(Set cr (CmpF src con));
9665
9666 ins_cost(145);
9667 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9668 "jnp,s exit\n\t"
9669 "pushfq\t# saw NaN, set CF\n\t"
9670 "andq [rsp], #0xffffff2b\n\t"
9671 "popfq\n"
9672 "exit:" %}
9673 ins_encode %{
9674 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9675 emit_cmpfp_fixup(_masm);
9676 %}
9677 ins_pipe(pipe_slow);
9678 %}
9679
9680 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9681 match(Set cr (CmpF src con));
9682 ins_cost(100);
9683 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9684 ins_encode %{
9685 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9686 %}
9687 ins_pipe(pipe_slow);
9688 %}
9689
9690 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9691 %{
9692 match(Set cr (CmpD src1 src2));
9693
9694 ins_cost(145);
9695 format %{ "ucomisd $src1, $src2\n\t"
9696 "jnp,s exit\n\t"
9697 "pushfq\t# saw NaN, set CF\n\t"
9698 "andq [rsp], #0xffffff2b\n\t"
9699 "popfq\n"
9700 "exit:" %}
9701 ins_encode %{
9702 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9703 emit_cmpfp_fixup(_masm);
9704 %}
9705 ins_pipe(pipe_slow);
9706 %}
9707
9708 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9709 match(Set cr (CmpD src1 src2));
9710
9711 ins_cost(100);
9712 format %{ "ucomisd $src1, $src2 test" %}
9713 ins_encode %{
9714 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9715 %}
9716 ins_pipe(pipe_slow);
9717 %}
9718
9719 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9720 %{
9721 match(Set cr (CmpD src1 (LoadD src2)));
9722
9723 ins_cost(145);
9724 format %{ "ucomisd $src1, $src2\n\t"
9725 "jnp,s exit\n\t"
9726 "pushfq\t# saw NaN, set CF\n\t"
9727 "andq [rsp], #0xffffff2b\n\t"
9728 "popfq\n"
9729 "exit:" %}
9730 ins_encode %{
9731 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9732 emit_cmpfp_fixup(_masm);
9733 %}
9734 ins_pipe(pipe_slow);
9735 %}
9736
9737 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9738 match(Set cr (CmpD src1 (LoadD src2)));
9739
9740 ins_cost(100);
9741 format %{ "ucomisd $src1, $src2" %}
9742 ins_encode %{
9743 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9744 %}
9745 ins_pipe(pipe_slow);
9746 %}
9747
9748 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9749 match(Set cr (CmpD src con));
9750
9751 ins_cost(145);
9752 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9753 "jnp,s exit\n\t"
9754 "pushfq\t# saw NaN, set CF\n\t"
9755 "andq [rsp], #0xffffff2b\n\t"
9756 "popfq\n"
9757 "exit:" %}
9758 ins_encode %{
9759 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9760 emit_cmpfp_fixup(_masm);
9761 %}
9762 ins_pipe(pipe_slow);
9763 %}
9764
9765 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9766 match(Set cr (CmpD src con));
9767 ins_cost(100);
9768 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9769 ins_encode %{
9770 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9771 %}
9772 ins_pipe(pipe_slow);
9773 %}
9774
9775 // Compare into -1,0,1
9776 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9777 %{
9778 match(Set dst (CmpF3 src1 src2));
9779 effect(KILL cr);
9780
9781 ins_cost(275);
9782 format %{ "ucomiss $src1, $src2\n\t"
9783 "movl $dst, #-1\n\t"
9784 "jp,s done\n\t"
9785 "jb,s done\n\t"
9786 "setne $dst\n\t"
9787 "movzbl $dst, $dst\n"
9788 "done:" %}
9789 ins_encode %{
9790 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9791 emit_cmpfp3(_masm, $dst$$Register);
9792 %}
9793 ins_pipe(pipe_slow);
9794 %}
9795
9796 // Compare into -1,0,1
9797 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9798 %{
9799 match(Set dst (CmpF3 src1 (LoadF src2)));
9800 effect(KILL cr);
9801
9802 ins_cost(275);
9803 format %{ "ucomiss $src1, $src2\n\t"
9804 "movl $dst, #-1\n\t"
9805 "jp,s done\n\t"
9806 "jb,s done\n\t"
9807 "setne $dst\n\t"
9808 "movzbl $dst, $dst\n"
9809 "done:" %}
9810 ins_encode %{
9811 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9812 emit_cmpfp3(_masm, $dst$$Register);
9813 %}
9814 ins_pipe(pipe_slow);
9815 %}
9816
9817 // Compare into -1,0,1
9818 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9819 match(Set dst (CmpF3 src con));
9820 effect(KILL cr);
9821
9822 ins_cost(275);
9823 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9824 "movl $dst, #-1\n\t"
9825 "jp,s done\n\t"
9826 "jb,s done\n\t"
9827 "setne $dst\n\t"
9828 "movzbl $dst, $dst\n"
9829 "done:" %}
9830 ins_encode %{
9831 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9832 emit_cmpfp3(_masm, $dst$$Register);
9833 %}
9834 ins_pipe(pipe_slow);
9835 %}
9836
9837 // Compare into -1,0,1
9838 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9839 %{
9840 match(Set dst (CmpD3 src1 src2));
9841 effect(KILL cr);
9842
9843 ins_cost(275);
9844 format %{ "ucomisd $src1, $src2\n\t"
9845 "movl $dst, #-1\n\t"
9846 "jp,s done\n\t"
9847 "jb,s done\n\t"
9848 "setne $dst\n\t"
9849 "movzbl $dst, $dst\n"
9850 "done:" %}
9851 ins_encode %{
9852 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9853 emit_cmpfp3(_masm, $dst$$Register);
9854 %}
9855 ins_pipe(pipe_slow);
9856 %}
9857
9858 // Compare into -1,0,1
9859 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9860 %{
9861 match(Set dst (CmpD3 src1 (LoadD src2)));
9862 effect(KILL cr);
9863
9864 ins_cost(275);
9865 format %{ "ucomisd $src1, $src2\n\t"
9866 "movl $dst, #-1\n\t"
9867 "jp,s done\n\t"
9868 "jb,s done\n\t"
9869 "setne $dst\n\t"
9870 "movzbl $dst, $dst\n"
9871 "done:" %}
9872 ins_encode %{
9873 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9874 emit_cmpfp3(_masm, $dst$$Register);
9875 %}
9876 ins_pipe(pipe_slow);
9877 %}
9878
9879 // Compare into -1,0,1
9880 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9881 match(Set dst (CmpD3 src con));
9882 effect(KILL cr);
9883
9884 ins_cost(275);
9885 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9886 "movl $dst, #-1\n\t"
9887 "jp,s done\n\t"
9888 "jb,s done\n\t"
9889 "setne $dst\n\t"
9890 "movzbl $dst, $dst\n"
9891 "done:" %}
9892 ins_encode %{
9893 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9894 emit_cmpfp3(_masm, $dst$$Register);
9895 %}
9896 ins_pipe(pipe_slow);
9897 %}
9898
9899 // -----------Trig and Trancendental Instructions------------------------------
9900 instruct cosD_reg(regD dst) %{
9901 match(Set dst (CosD dst));
9902
9903 format %{ "dcos $dst\n\t" %}
9904 opcode(0xD9, 0xFF);
9905 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9906 ins_pipe( pipe_slow );
9907 %}
9908
9909 instruct sinD_reg(regD dst) %{
9910 match(Set dst (SinD dst));
9911
9912 format %{ "dsin $dst\n\t" %}
9913 opcode(0xD9, 0xFE);
9914 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9915 ins_pipe( pipe_slow );
9916 %}
9917
9918 instruct tanD_reg(regD dst) %{
9919 match(Set dst (TanD dst));
9920
9921 format %{ "dtan $dst\n\t" %}
9922 ins_encode( Push_SrcXD(dst),
9923 Opcode(0xD9), Opcode(0xF2), //fptan
9924 Opcode(0xDD), Opcode(0xD8), //fstp st
9925 Push_ResultXD(dst) );
9926 ins_pipe( pipe_slow );
9927 %}
9928
9929 instruct log10D_reg(regD dst) %{
9930 // The source and result Double operands in XMM registers
9931 match(Set dst (Log10D dst));
9932 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9933 // fyl2x ; compute log_10(2) * log_2(x)
9934 format %{ "fldlg2\t\t\t#Log10\n\t"
9935 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9936 %}
9937 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9938 Push_SrcXD(dst),
9939 Opcode(0xD9), Opcode(0xF1), // fyl2x
9940 Push_ResultXD(dst));
9941
9942 ins_pipe( pipe_slow );
9943 %}
9944
9945 instruct logD_reg(regD dst) %{
9946 // The source and result Double operands in XMM registers
9947 match(Set dst (LogD dst));
9948 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9949 // fyl2x ; compute log_e(2) * log_2(x)
9950 format %{ "fldln2\t\t\t#Log_e\n\t"
9951 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9952 %}
9953 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9954 Push_SrcXD(dst),
9955 Opcode(0xD9), Opcode(0xF1), // fyl2x
9956 Push_ResultXD(dst));
9957 ins_pipe( pipe_slow );
9958 %}
9959
9960 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9961 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9962 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9963 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9964 ins_encode %{
9965 __ subptr(rsp, 8);
9966 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9967 __ fld_d(Address(rsp, 0));
9968 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9969 __ fld_d(Address(rsp, 0));
9970 __ fast_pow();
9971 __ fstp_d(Address(rsp, 0));
9972 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9973 __ addptr(rsp, 8);
9974 %}
9975 ins_pipe( pipe_slow );
9976 %}
9977
9978 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9979 match(Set dst (ExpD src));
9980 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9981 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9982 ins_encode %{
9983 __ subptr(rsp, 8);
9984 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9985 __ fld_d(Address(rsp, 0));
9986 __ fast_exp();
9987 __ fstp_d(Address(rsp, 0));
9988 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9989 __ addptr(rsp, 8);
9990 %}
9991 ins_pipe( pipe_slow );
9992 %}
9993
9994 //----------Arithmetic Conversion Instructions---------------------------------
9995
9996 instruct roundFloat_nop(regF dst)
9997 %{
9998 match(Set dst (RoundFloat dst));
9999
10000 ins_cost(0);
10001 ins_encode();
10002 ins_pipe(empty);
10003 %}
10004
10005 instruct roundDouble_nop(regD dst)
10006 %{
10007 match(Set dst (RoundDouble dst));
10008
10009 ins_cost(0);
10010 ins_encode();
10011 ins_pipe(empty);
10012 %}
10013
10014 instruct convF2D_reg_reg(regD dst, regF src)
10015 %{
10016 match(Set dst (ConvF2D src));
10017
10018 format %{ "cvtss2sd $dst, $src" %}
10019 ins_encode %{
10020 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10021 %}
10022 ins_pipe(pipe_slow); // XXX
10023 %}
10024
10025 instruct convF2D_reg_mem(regD dst, memory src)
10026 %{
10027 match(Set dst (ConvF2D (LoadF src)));
10028
10029 format %{ "cvtss2sd $dst, $src" %}
10030 ins_encode %{
10031 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10032 %}
10033 ins_pipe(pipe_slow); // XXX
10034 %}
10035
10036 instruct convD2F_reg_reg(regF dst, regD src)
10037 %{
10038 match(Set dst (ConvD2F src));
10039
10040 format %{ "cvtsd2ss $dst, $src" %}
10041 ins_encode %{
10042 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10043 %}
10044 ins_pipe(pipe_slow); // XXX
10045 %}
10046
10047 instruct convD2F_reg_mem(regF dst, memory src)
10048 %{
10049 match(Set dst (ConvD2F (LoadD src)));
10050
10051 format %{ "cvtsd2ss $dst, $src" %}
10052 ins_encode %{
10053 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10054 %}
10055 ins_pipe(pipe_slow); // XXX
10056 %}
10057
10058 // XXX do mem variants
10059 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10060 %{
10061 match(Set dst (ConvF2I src));
10062 effect(KILL cr);
10063
10064 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10065 "cmpl $dst, #0x80000000\n\t"
10066 "jne,s done\n\t"
10067 "subq rsp, #8\n\t"
10068 "movss [rsp], $src\n\t"
10069 "call f2i_fixup\n\t"
10070 "popq $dst\n"
10071 "done: "%}
10072 ins_encode %{
10073 Label done;
10074 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10075 __ cmpl($dst$$Register, 0x80000000);
10076 __ jccb(Assembler::notEqual, done);
10077 __ subptr(rsp, 8);
10078 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10079 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10080 __ pop($dst$$Register);
10081 __ bind(done);
10082 %}
10083 ins_pipe(pipe_slow);
10084 %}
10085
10086 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10087 %{
10088 match(Set dst (ConvF2L src));
10089 effect(KILL cr);
10090
10091 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10092 "cmpq $dst, [0x8000000000000000]\n\t"
10093 "jne,s done\n\t"
10094 "subq rsp, #8\n\t"
10095 "movss [rsp], $src\n\t"
10096 "call f2l_fixup\n\t"
10097 "popq $dst\n"
10098 "done: "%}
10099 ins_encode %{
10100 Label done;
10101 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10102 __ cmp64($dst$$Register,
10103 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10104 __ jccb(Assembler::notEqual, done);
10105 __ subptr(rsp, 8);
10106 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10107 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10108 __ pop($dst$$Register);
10109 __ bind(done);
10110 %}
10111 ins_pipe(pipe_slow);
10112 %}
10113
10114 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10115 %{
10116 match(Set dst (ConvD2I src));
10117 effect(KILL cr);
10118
10119 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10120 "cmpl $dst, #0x80000000\n\t"
10121 "jne,s done\n\t"
10122 "subq rsp, #8\n\t"
10123 "movsd [rsp], $src\n\t"
10124 "call d2i_fixup\n\t"
10125 "popq $dst\n"
10126 "done: "%}
10127 ins_encode %{
10128 Label done;
10129 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10130 __ cmpl($dst$$Register, 0x80000000);
10131 __ jccb(Assembler::notEqual, done);
10132 __ subptr(rsp, 8);
10133 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10134 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10135 __ pop($dst$$Register);
10136 __ bind(done);
10137 %}
10138 ins_pipe(pipe_slow);
10139 %}
10140
10141 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10142 %{
10143 match(Set dst (ConvD2L src));
10144 effect(KILL cr);
10145
10146 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10147 "cmpq $dst, [0x8000000000000000]\n\t"
10148 "jne,s done\n\t"
10149 "subq rsp, #8\n\t"
10150 "movsd [rsp], $src\n\t"
10151 "call d2l_fixup\n\t"
10152 "popq $dst\n"
10153 "done: "%}
10154 ins_encode %{
10155 Label done;
10156 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10157 __ cmp64($dst$$Register,
10158 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10159 __ jccb(Assembler::notEqual, done);
10160 __ subptr(rsp, 8);
10161 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10162 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10163 __ pop($dst$$Register);
10164 __ bind(done);
10165 %}
10166 ins_pipe(pipe_slow);
10167 %}
10168
10169 instruct convI2F_reg_reg(regF dst, rRegI src)
10170 %{
10171 predicate(!UseXmmI2F);
10172 match(Set dst (ConvI2F src));
10173
10174 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10175 ins_encode %{
10176 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10177 %}
10178 ins_pipe(pipe_slow); // XXX
10179 %}
10180
10181 instruct convI2F_reg_mem(regF dst, memory src)
10182 %{
10183 match(Set dst (ConvI2F (LoadI src)));
10184
10185 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10186 ins_encode %{
10187 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10188 %}
10189 ins_pipe(pipe_slow); // XXX
10190 %}
10191
10192 instruct convI2D_reg_reg(regD dst, rRegI src)
10193 %{
10194 predicate(!UseXmmI2D);
10195 match(Set dst (ConvI2D src));
10196
10197 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10198 ins_encode %{
10199 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10200 %}
10201 ins_pipe(pipe_slow); // XXX
10202 %}
10203
10204 instruct convI2D_reg_mem(regD dst, memory src)
10205 %{
10206 match(Set dst (ConvI2D (LoadI src)));
10207
10208 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10209 ins_encode %{
10210 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10211 %}
10212 ins_pipe(pipe_slow); // XXX
10213 %}
10214
10215 instruct convXI2F_reg(regF dst, rRegI src)
10216 %{
10217 predicate(UseXmmI2F);
10218 match(Set dst (ConvI2F src));
10219
10220 format %{ "movdl $dst, $src\n\t"
10221 "cvtdq2psl $dst, $dst\t# i2f" %}
10222 ins_encode %{
10223 __ movdl($dst$$XMMRegister, $src$$Register);
10224 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10225 %}
10226 ins_pipe(pipe_slow); // XXX
10227 %}
10228
10229 instruct convXI2D_reg(regD dst, rRegI src)
10230 %{
10231 predicate(UseXmmI2D);
10232 match(Set dst (ConvI2D src));
10233
10234 format %{ "movdl $dst, $src\n\t"
10235 "cvtdq2pdl $dst, $dst\t# i2d" %}
10236 ins_encode %{
10237 __ movdl($dst$$XMMRegister, $src$$Register);
10238 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10239 %}
10240 ins_pipe(pipe_slow); // XXX
10241 %}
10242
10243 instruct convL2F_reg_reg(regF dst, rRegL src)
10244 %{
10245 match(Set dst (ConvL2F src));
10246
10247 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10248 ins_encode %{
10249 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10250 %}
10251 ins_pipe(pipe_slow); // XXX
10252 %}
10253
10254 instruct convL2F_reg_mem(regF dst, memory src)
10255 %{
10256 match(Set dst (ConvL2F (LoadL src)));
10257
10258 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10259 ins_encode %{
10260 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10261 %}
10262 ins_pipe(pipe_slow); // XXX
10263 %}
10264
10265 instruct convL2D_reg_reg(regD dst, rRegL src)
10266 %{
10267 match(Set dst (ConvL2D src));
10268
10269 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10270 ins_encode %{
10271 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10272 %}
10273 ins_pipe(pipe_slow); // XXX
10274 %}
10275
10276 instruct convL2D_reg_mem(regD dst, memory src)
10277 %{
10278 match(Set dst (ConvL2D (LoadL src)));
10279
10280 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10281 ins_encode %{
10282 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10283 %}
10284 ins_pipe(pipe_slow); // XXX
10285 %}
10286
10287 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10288 %{
10289 match(Set dst (ConvI2L src));
10290
10291 ins_cost(125);
10292 format %{ "movslq $dst, $src\t# i2l" %}
10293 ins_encode %{
10294 __ movslq($dst$$Register, $src$$Register);
10295 %}
10296 ins_pipe(ialu_reg_reg);
10297 %}
10298
10299 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10300 // %{
10301 // match(Set dst (ConvI2L src));
10302 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10303 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10304 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10305 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10306 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10307 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10308
10309 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10310 // ins_encode(enc_copy(dst, src));
10311 // // opcode(0x63); // needs REX.W
10312 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10313 // ins_pipe(ialu_reg_reg);
10314 // %}
10315
10316 // Zero-extend convert int to long
10317 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10318 %{
10319 match(Set dst (AndL (ConvI2L src) mask));
10320
10321 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10322 ins_encode %{
10323 if ($dst$$reg != $src$$reg) {
10324 __ movl($dst$$Register, $src$$Register);
10325 }
10326 %}
10327 ins_pipe(ialu_reg_reg);
10328 %}
10329
10330 // Zero-extend convert int to long
10331 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10332 %{
10333 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10334
10335 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10336 ins_encode %{
10337 __ movl($dst$$Register, $src$$Address);
10338 %}
10339 ins_pipe(ialu_reg_mem);
10340 %}
10341
10342 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10343 %{
10344 match(Set dst (AndL src mask));
10345
10346 format %{ "movl $dst, $src\t# zero-extend long" %}
10347 ins_encode %{
10348 __ movl($dst$$Register, $src$$Register);
10349 %}
10350 ins_pipe(ialu_reg_reg);
10351 %}
10352
10353 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10354 %{
10355 match(Set dst (ConvL2I src));
10356
10357 format %{ "movl $dst, $src\t# l2i" %}
10358 ins_encode %{
10359 __ movl($dst$$Register, $src$$Register);
10360 %}
10361 ins_pipe(ialu_reg_reg);
10362 %}
10363
10364
10365 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10366 match(Set dst (MoveF2I src));
10367 effect(DEF dst, USE src);
10368
10369 ins_cost(125);
10370 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10371 ins_encode %{
10372 __ movl($dst$$Register, Address(rsp, $src$$disp));
10373 %}
10374 ins_pipe(ialu_reg_mem);
10375 %}
10376
10377 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10378 match(Set dst (MoveI2F src));
10379 effect(DEF dst, USE src);
10380
10381 ins_cost(125);
10382 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10383 ins_encode %{
10384 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10385 %}
10386 ins_pipe(pipe_slow);
10387 %}
10388
10389 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10390 match(Set dst (MoveD2L src));
10391 effect(DEF dst, USE src);
10392
10393 ins_cost(125);
10394 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10395 ins_encode %{
10396 __ movq($dst$$Register, Address(rsp, $src$$disp));
10397 %}
10398 ins_pipe(ialu_reg_mem);
10399 %}
10400
10401 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10402 predicate(!UseXmmLoadAndClearUpper);
10403 match(Set dst (MoveL2D src));
10404 effect(DEF dst, USE src);
10405
10406 ins_cost(125);
10407 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10408 ins_encode %{
10409 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10410 %}
10411 ins_pipe(pipe_slow);
10412 %}
10413
10414 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10415 predicate(UseXmmLoadAndClearUpper);
10416 match(Set dst (MoveL2D src));
10417 effect(DEF dst, USE src);
10418
10419 ins_cost(125);
10420 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10421 ins_encode %{
10422 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10423 %}
10424 ins_pipe(pipe_slow);
10425 %}
10426
10427
10428 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10429 match(Set dst (MoveF2I src));
10430 effect(DEF dst, USE src);
10431
10432 ins_cost(95); // XXX
10433 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10434 ins_encode %{
10435 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10436 %}
10437 ins_pipe(pipe_slow);
10438 %}
10439
10440 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10441 match(Set dst (MoveI2F src));
10442 effect(DEF dst, USE src);
10443
10444 ins_cost(100);
10445 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10446 ins_encode %{
10447 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10448 %}
10449 ins_pipe( ialu_mem_reg );
10450 %}
10451
10452 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10453 match(Set dst (MoveD2L src));
10454 effect(DEF dst, USE src);
10455
10456 ins_cost(95); // XXX
10457 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10458 ins_encode %{
10459 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10460 %}
10461 ins_pipe(pipe_slow);
10462 %}
10463
10464 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10465 match(Set dst (MoveL2D src));
10466 effect(DEF dst, USE src);
10467
10468 ins_cost(100);
10469 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10470 ins_encode %{
10471 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10472 %}
10473 ins_pipe(ialu_mem_reg);
10474 %}
10475
10476 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10477 match(Set dst (MoveF2I src));
10478 effect(DEF dst, USE src);
10479 ins_cost(85);
10480 format %{ "movd $dst,$src\t# MoveF2I" %}
10481 ins_encode %{
10482 __ movdl($dst$$Register, $src$$XMMRegister);
10483 %}
10484 ins_pipe( pipe_slow );
10485 %}
10486
10487 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10488 match(Set dst (MoveD2L src));
10489 effect(DEF dst, USE src);
10490 ins_cost(85);
10491 format %{ "movd $dst,$src\t# MoveD2L" %}
10492 ins_encode %{
10493 __ movdq($dst$$Register, $src$$XMMRegister);
10494 %}
10495 ins_pipe( pipe_slow );
10496 %}
10497
10498 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10499 match(Set dst (MoveI2F src));
10500 effect(DEF dst, USE src);
10501 ins_cost(100);
10502 format %{ "movd $dst,$src\t# MoveI2F" %}
10503 ins_encode %{
10504 __ movdl($dst$$XMMRegister, $src$$Register);
10505 %}
10506 ins_pipe( pipe_slow );
10507 %}
10508
10509 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10510 match(Set dst (MoveL2D src));
10511 effect(DEF dst, USE src);
10512 ins_cost(100);
10513 format %{ "movd $dst,$src\t# MoveL2D" %}
10514 ins_encode %{
10515 __ movdq($dst$$XMMRegister, $src$$Register);
10516 %}
10517 ins_pipe( pipe_slow );
10518 %}
10519
10520
10521 // =======================================================================
10522 // fast clearing of an array
10523 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10524 rFlagsReg cr)
10525 %{
10526 predicate(!UseFastStosb);
10527 match(Set dummy (ClearArray cnt base));
10528 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10529
10530 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10531 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10532 ins_encode %{
10533 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10534 %}
10535 ins_pipe(pipe_slow);
10536 %}
10537
10538 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10539 rFlagsReg cr)
10540 %{
10541 predicate(UseFastStosb);
10542 match(Set dummy (ClearArray cnt base));
10543 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10544 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10545 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10546 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10547 ins_encode %{
10548 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10549 %}
10550 ins_pipe( pipe_slow );
10551 %}
10552
10553 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10554 rax_RegI result, regD tmp1, rFlagsReg cr)
10555 %{
10556 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10557 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10558
10559 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10560 ins_encode %{
10561 __ string_compare($str1$$Register, $str2$$Register,
10562 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10563 $tmp1$$XMMRegister);
10564 %}
10565 ins_pipe( pipe_slow );
10566 %}
10567
10568 // fast search of substring with known size.
10569 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10570 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10571 %{
10572 predicate(UseSSE42Intrinsics);
10573 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10574 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10575
10576 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10577 ins_encode %{
10578 int icnt2 = (int)$int_cnt2$$constant;
10579 if (icnt2 >= 8) {
10580 // IndexOf for constant substrings with size >= 8 elements
10581 // which don't need to be loaded through stack.
10582 __ string_indexofC8($str1$$Register, $str2$$Register,
10583 $cnt1$$Register, $cnt2$$Register,
10584 icnt2, $result$$Register,
10585 $vec$$XMMRegister, $tmp$$Register);
10586 } else {
10587 // Small strings are loaded through stack if they cross page boundary.
10588 __ string_indexof($str1$$Register, $str2$$Register,
10589 $cnt1$$Register, $cnt2$$Register,
10590 icnt2, $result$$Register,
10591 $vec$$XMMRegister, $tmp$$Register);
10592 }
10593 %}
10594 ins_pipe( pipe_slow );
10595 %}
10596
10597 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10598 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10599 %{
10600 predicate(UseSSE42Intrinsics);
10601 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10602 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10603
10604 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10605 ins_encode %{
10606 __ string_indexof($str1$$Register, $str2$$Register,
10607 $cnt1$$Register, $cnt2$$Register,
10608 (-1), $result$$Register,
10609 $vec$$XMMRegister, $tmp$$Register);
10610 %}
10611 ins_pipe( pipe_slow );
10612 %}
10613
10614 // fast string equals
10615 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10616 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10617 %{
10618 match(Set result (StrEquals (Binary str1 str2) cnt));
10619 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10620
10621 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10622 ins_encode %{
10623 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10624 $cnt$$Register, $result$$Register, $tmp3$$Register,
10625 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10626 %}
10627 ins_pipe( pipe_slow );
10628 %}
10629
10630 // fast array equals
10631 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10632 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10633 %{
10634 match(Set result (AryEq ary1 ary2));
10635 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10636 //ins_cost(300);
10637
10638 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10639 ins_encode %{
10640 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10641 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10642 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10643 %}
10644 ins_pipe( pipe_slow );
10645 %}
10646
10647 // encode char[] to byte[] in ISO_8859_1
10648 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10649 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10650 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10651 match(Set result (EncodeISOArray src (Binary dst len)));
10652 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10653
10654 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10655 ins_encode %{
10656 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10657 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10658 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10659 %}
10660 ins_pipe( pipe_slow );
10661 %}
10662
10663
10664 //----------Control Flow Instructions------------------------------------------
10665 // Signed compare Instructions
10666
10667 // XXX more variants!!
10668 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10669 %{
10670 match(Set cr (CmpI op1 op2));
10671 effect(DEF cr, USE op1, USE op2);
10672
10673 format %{ "cmpl $op1, $op2" %}
10674 opcode(0x3B); /* Opcode 3B /r */
10675 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10676 ins_pipe(ialu_cr_reg_reg);
10677 %}
10678
10679 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10680 %{
10681 match(Set cr (CmpI op1 op2));
10682
10683 format %{ "cmpl $op1, $op2" %}
10684 opcode(0x81, 0x07); /* Opcode 81 /7 */
10685 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10686 ins_pipe(ialu_cr_reg_imm);
10687 %}
10688
10689 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10690 %{
10691 match(Set cr (CmpI op1 (LoadI op2)));
10692
10693 ins_cost(500); // XXX
10694 format %{ "cmpl $op1, $op2" %}
10695 opcode(0x3B); /* Opcode 3B /r */
10696 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10697 ins_pipe(ialu_cr_reg_mem);
10698 %}
10699
10700 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10701 %{
10702 match(Set cr (CmpI src zero));
10703
10704 format %{ "testl $src, $src" %}
10705 opcode(0x85);
10706 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10707 ins_pipe(ialu_cr_reg_imm);
10708 %}
10709
10710 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10711 %{
10712 match(Set cr (CmpI (AndI src con) zero));
10713
10714 format %{ "testl $src, $con" %}
10715 opcode(0xF7, 0x00);
10716 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10717 ins_pipe(ialu_cr_reg_imm);
10718 %}
10719
10720 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10721 %{
10722 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10723
10724 format %{ "testl $src, $mem" %}
10725 opcode(0x85);
10726 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10727 ins_pipe(ialu_cr_reg_mem);
10728 %}
10729
10730 // Unsigned compare Instructions; really, same as signed except they
10731 // produce an rFlagsRegU instead of rFlagsReg.
10732 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10733 %{
10734 match(Set cr (CmpU op1 op2));
10735
10736 format %{ "cmpl $op1, $op2\t# unsigned" %}
10737 opcode(0x3B); /* Opcode 3B /r */
10738 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10739 ins_pipe(ialu_cr_reg_reg);
10740 %}
10741
10742 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10743 %{
10744 match(Set cr (CmpU op1 op2));
10745
10746 format %{ "cmpl $op1, $op2\t# unsigned" %}
10747 opcode(0x81,0x07); /* Opcode 81 /7 */
10748 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10749 ins_pipe(ialu_cr_reg_imm);
10750 %}
10751
10752 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10753 %{
10754 match(Set cr (CmpU op1 (LoadI op2)));
10755
10756 ins_cost(500); // XXX
10757 format %{ "cmpl $op1, $op2\t# unsigned" %}
10758 opcode(0x3B); /* Opcode 3B /r */
10759 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10760 ins_pipe(ialu_cr_reg_mem);
10761 %}
10762
10763 // // // Cisc-spilled version of cmpU_rReg
10764 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10765 // //%{
10766 // // match(Set cr (CmpU (LoadI op1) op2));
10767 // //
10768 // // format %{ "CMPu $op1,$op2" %}
10769 // // ins_cost(500);
10770 // // opcode(0x39); /* Opcode 39 /r */
10771 // // ins_encode( OpcP, reg_mem( op1, op2) );
10772 // //%}
10773
10774 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10775 %{
10776 match(Set cr (CmpU src zero));
10777
10778 format %{ "testl $src, $src\t# unsigned" %}
10779 opcode(0x85);
10780 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10781 ins_pipe(ialu_cr_reg_imm);
10782 %}
10783
10784 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10785 %{
10786 match(Set cr (CmpP op1 op2));
10787
10788 format %{ "cmpq $op1, $op2\t# ptr" %}
10789 opcode(0x3B); /* Opcode 3B /r */
10790 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10791 ins_pipe(ialu_cr_reg_reg);
10792 %}
10793
10794 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10795 %{
10796 match(Set cr (CmpP op1 (LoadP op2)));
10797
10798 ins_cost(500); // XXX
10799 format %{ "cmpq $op1, $op2\t# ptr" %}
10800 opcode(0x3B); /* Opcode 3B /r */
10801 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10802 ins_pipe(ialu_cr_reg_mem);
10803 %}
10804
10805 // // // Cisc-spilled version of cmpP_rReg
10806 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10807 // //%{
10808 // // match(Set cr (CmpP (LoadP op1) op2));
10809 // //
10810 // // format %{ "CMPu $op1,$op2" %}
10811 // // ins_cost(500);
10812 // // opcode(0x39); /* Opcode 39 /r */
10813 // // ins_encode( OpcP, reg_mem( op1, op2) );
10814 // //%}
10815
10816 // XXX this is generalized by compP_rReg_mem???
10817 // Compare raw pointer (used in out-of-heap check).
10818 // Only works because non-oop pointers must be raw pointers
10819 // and raw pointers have no anti-dependencies.
10820 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10821 %{
10822 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10823 match(Set cr (CmpP op1 (LoadP op2)));
10824
10825 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10826 opcode(0x3B); /* Opcode 3B /r */
10827 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10828 ins_pipe(ialu_cr_reg_mem);
10829 %}
10830
10831 // This will generate a signed flags result. This should be OK since
10832 // any compare to a zero should be eq/neq.
10833 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10834 %{
10835 match(Set cr (CmpP src zero));
10836
10837 format %{ "testq $src, $src\t# ptr" %}
10838 opcode(0x85);
10839 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10840 ins_pipe(ialu_cr_reg_imm);
10841 %}
10842
10843 // This will generate a signed flags result. This should be OK since
10844 // any compare to a zero should be eq/neq.
10845 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10846 %{
10847 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10848 match(Set cr (CmpP (LoadP op) zero));
10849
10850 ins_cost(500); // XXX
10851 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10852 opcode(0xF7); /* Opcode F7 /0 */
10853 ins_encode(REX_mem_wide(op),
10854 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10855 ins_pipe(ialu_cr_reg_imm);
10856 %}
10857
10858 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10859 %{
10860 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10861 match(Set cr (CmpP (LoadP mem) zero));
10862
10863 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10864 ins_encode %{
10865 __ cmpq(r12, $mem$$Address);
10866 %}
10867 ins_pipe(ialu_cr_reg_mem);
10868 %}
10869
10870 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10871 %{
10872 match(Set cr (CmpN op1 op2));
10873
10874 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10875 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10876 ins_pipe(ialu_cr_reg_reg);
10877 %}
10878
10879 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10880 %{
10881 match(Set cr (CmpN src (LoadN mem)));
10882
10883 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10884 ins_encode %{
10885 __ cmpl($src$$Register, $mem$$Address);
10886 %}
10887 ins_pipe(ialu_cr_reg_mem);
10888 %}
10889
10890 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10891 match(Set cr (CmpN op1 op2));
10892
10893 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10894 ins_encode %{
10895 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10896 %}
10897 ins_pipe(ialu_cr_reg_imm);
10898 %}
10899
10900 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10901 %{
10902 match(Set cr (CmpN src (LoadN mem)));
10903
10904 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10905 ins_encode %{
10906 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10907 %}
10908 ins_pipe(ialu_cr_reg_mem);
10909 %}
10910
10911 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10912 match(Set cr (CmpN op1 op2));
10913
10914 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10915 ins_encode %{
10916 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10917 %}
10918 ins_pipe(ialu_cr_reg_imm);
10919 %}
10920
10921 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10922 %{
10923 match(Set cr (CmpN src (LoadNKlass mem)));
10924
10925 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10926 ins_encode %{
10927 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10928 %}
10929 ins_pipe(ialu_cr_reg_mem);
10930 %}
10931
10932 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10933 match(Set cr (CmpN src zero));
10934
10935 format %{ "testl $src, $src\t# compressed ptr" %}
10936 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10937 ins_pipe(ialu_cr_reg_imm);
10938 %}
10939
10940 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10941 %{
10942 predicate(Universe::narrow_oop_base() != NULL);
10943 match(Set cr (CmpN (LoadN mem) zero));
10944
10945 ins_cost(500); // XXX
10946 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10947 ins_encode %{
10948 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10949 %}
10950 ins_pipe(ialu_cr_reg_mem);
10951 %}
10952
10953 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10954 %{
10955 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
10956 match(Set cr (CmpN (LoadN mem) zero));
10957
10958 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10959 ins_encode %{
10960 __ cmpl(r12, $mem$$Address);
10961 %}
10962 ins_pipe(ialu_cr_reg_mem);
10963 %}
10964
10965 // Yanked all unsigned pointer compare operations.
10966 // Pointer compares are done with CmpP which is already unsigned.
10967
10968 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10969 %{
10970 match(Set cr (CmpL op1 op2));
10971
10972 format %{ "cmpq $op1, $op2" %}
10973 opcode(0x3B); /* Opcode 3B /r */
10974 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10975 ins_pipe(ialu_cr_reg_reg);
10976 %}
10977
10978 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10979 %{
10980 match(Set cr (CmpL op1 op2));
10981
10982 format %{ "cmpq $op1, $op2" %}
10983 opcode(0x81, 0x07); /* Opcode 81 /7 */
10984 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10985 ins_pipe(ialu_cr_reg_imm);
10986 %}
10987
10988 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10989 %{
10990 match(Set cr (CmpL op1 (LoadL op2)));
10991
10992 format %{ "cmpq $op1, $op2" %}
10993 opcode(0x3B); /* Opcode 3B /r */
10994 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10995 ins_pipe(ialu_cr_reg_mem);
10996 %}
10997
10998 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10999 %{
11000 match(Set cr (CmpL src zero));
11001
11002 format %{ "testq $src, $src" %}
11003 opcode(0x85);
11004 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11005 ins_pipe(ialu_cr_reg_imm);
11006 %}
11007
11008 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11009 %{
11010 match(Set cr (CmpL (AndL src con) zero));
11011
11012 format %{ "testq $src, $con\t# long" %}
11013 opcode(0xF7, 0x00);
11014 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11015 ins_pipe(ialu_cr_reg_imm);
11016 %}
11017
11018 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11019 %{
11020 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11021
11022 format %{ "testq $src, $mem" %}
11023 opcode(0x85);
11024 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11025 ins_pipe(ialu_cr_reg_mem);
11026 %}
11027
11028 // Manifest a CmpL result in an integer register. Very painful.
11029 // This is the test to avoid.
11030 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11031 %{
11032 match(Set dst (CmpL3 src1 src2));
11033 effect(KILL flags);
11034
11035 ins_cost(275); // XXX
11036 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11037 "movl $dst, -1\n\t"
11038 "jl,s done\n\t"
11039 "setne $dst\n\t"
11040 "movzbl $dst, $dst\n\t"
11041 "done:" %}
11042 ins_encode(cmpl3_flag(src1, src2, dst));
11043 ins_pipe(pipe_slow);
11044 %}
11045
11046 //----------Max and Min--------------------------------------------------------
11047 // Min Instructions
11048
11049 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11050 %{
11051 effect(USE_DEF dst, USE src, USE cr);
11052
11053 format %{ "cmovlgt $dst, $src\t# min" %}
11054 opcode(0x0F, 0x4F);
11055 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11056 ins_pipe(pipe_cmov_reg);
11057 %}
11058
11059
11060 instruct minI_rReg(rRegI dst, rRegI src)
11061 %{
11062 match(Set dst (MinI dst src));
11063
11064 ins_cost(200);
11065 expand %{
11066 rFlagsReg cr;
11067 compI_rReg(cr, dst, src);
11068 cmovI_reg_g(dst, src, cr);
11069 %}
11070 %}
11071
11072 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11073 %{
11074 effect(USE_DEF dst, USE src, USE cr);
11075
11076 format %{ "cmovllt $dst, $src\t# max" %}
11077 opcode(0x0F, 0x4C);
11078 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11079 ins_pipe(pipe_cmov_reg);
11080 %}
11081
11082
11083 instruct maxI_rReg(rRegI dst, rRegI src)
11084 %{
11085 match(Set dst (MaxI dst src));
11086
11087 ins_cost(200);
11088 expand %{
11089 rFlagsReg cr;
11090 compI_rReg(cr, dst, src);
11091 cmovI_reg_l(dst, src, cr);
11092 %}
11093 %}
11094
11095 // ============================================================================
11096 // Branch Instructions
11097
11098 // Jump Direct - Label defines a relative address from JMP+1
11099 instruct jmpDir(label labl)
11100 %{
11101 match(Goto);
11102 effect(USE labl);
11103
11104 ins_cost(300);
11105 format %{ "jmp $labl" %}
11106 size(5);
11107 ins_encode %{
11108 Label* L = $labl$$label;
11109 __ jmp(*L, false); // Always long jump
11110 %}
11111 ins_pipe(pipe_jmp);
11112 %}
11113
11114 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11115 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11116 %{
11117 match(If cop cr);
11118 effect(USE labl);
11119
11120 ins_cost(300);
11121 format %{ "j$cop $labl" %}
11122 size(6);
11123 ins_encode %{
11124 Label* L = $labl$$label;
11125 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11126 %}
11127 ins_pipe(pipe_jcc);
11128 %}
11129
11130 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11131 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11132 %{
11133 match(CountedLoopEnd cop cr);
11134 effect(USE labl);
11135
11136 ins_cost(300);
11137 format %{ "j$cop $labl\t# loop end" %}
11138 size(6);
11139 ins_encode %{
11140 Label* L = $labl$$label;
11141 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11142 %}
11143 ins_pipe(pipe_jcc);
11144 %}
11145
11146 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11147 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11148 match(CountedLoopEnd cop cmp);
11149 effect(USE labl);
11150
11151 ins_cost(300);
11152 format %{ "j$cop,u $labl\t# loop end" %}
11153 size(6);
11154 ins_encode %{
11155 Label* L = $labl$$label;
11156 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11157 %}
11158 ins_pipe(pipe_jcc);
11159 %}
11160
11161 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11162 match(CountedLoopEnd cop cmp);
11163 effect(USE labl);
11164
11165 ins_cost(200);
11166 format %{ "j$cop,u $labl\t# loop end" %}
11167 size(6);
11168 ins_encode %{
11169 Label* L = $labl$$label;
11170 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11171 %}
11172 ins_pipe(pipe_jcc);
11173 %}
11174
11175 // Jump Direct Conditional - using unsigned comparison
11176 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11177 match(If cop cmp);
11178 effect(USE labl);
11179
11180 ins_cost(300);
11181 format %{ "j$cop,u $labl" %}
11182 size(6);
11183 ins_encode %{
11184 Label* L = $labl$$label;
11185 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11186 %}
11187 ins_pipe(pipe_jcc);
11188 %}
11189
11190 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11191 match(If cop cmp);
11192 effect(USE labl);
11193
11194 ins_cost(200);
11195 format %{ "j$cop,u $labl" %}
11196 size(6);
11197 ins_encode %{
11198 Label* L = $labl$$label;
11199 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11200 %}
11201 ins_pipe(pipe_jcc);
11202 %}
11203
11204 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11205 match(If cop cmp);
11206 effect(USE labl);
11207
11208 ins_cost(200);
11209 format %{ $$template
11210 if ($cop$$cmpcode == Assembler::notEqual) {
11211 $$emit$$"jp,u $labl\n\t"
11212 $$emit$$"j$cop,u $labl"
11213 } else {
11214 $$emit$$"jp,u done\n\t"
11215 $$emit$$"j$cop,u $labl\n\t"
11216 $$emit$$"done:"
11217 }
11218 %}
11219 ins_encode %{
11220 Label* l = $labl$$label;
11221 if ($cop$$cmpcode == Assembler::notEqual) {
11222 __ jcc(Assembler::parity, *l, false);
11223 __ jcc(Assembler::notEqual, *l, false);
11224 } else if ($cop$$cmpcode == Assembler::equal) {
11225 Label done;
11226 __ jccb(Assembler::parity, done);
11227 __ jcc(Assembler::equal, *l, false);
11228 __ bind(done);
11229 } else {
11230 ShouldNotReachHere();
11231 }
11232 %}
11233 ins_pipe(pipe_jcc);
11234 %}
11235
11236 // ============================================================================
11237 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11238 // superklass array for an instance of the superklass. Set a hidden
11239 // internal cache on a hit (cache is checked with exposed code in
11240 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11241 // encoding ALSO sets flags.
11242
11243 instruct partialSubtypeCheck(rdi_RegP result,
11244 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11245 rFlagsReg cr)
11246 %{
11247 match(Set result (PartialSubtypeCheck sub super));
11248 effect(KILL rcx, KILL cr);
11249
11250 ins_cost(1100); // slightly larger than the next version
11251 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11252 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11253 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11254 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11255 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11256 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11257 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11258 "miss:\t" %}
11259
11260 opcode(0x1); // Force a XOR of RDI
11261 ins_encode(enc_PartialSubtypeCheck());
11262 ins_pipe(pipe_slow);
11263 %}
11264
11265 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11266 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11267 immP0 zero,
11268 rdi_RegP result)
11269 %{
11270 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11271 effect(KILL rcx, KILL result);
11272
11273 ins_cost(1000);
11274 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11275 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11276 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11277 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11278 "jne,s miss\t\t# Missed: flags nz\n\t"
11279 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11280 "miss:\t" %}
11281
11282 opcode(0x0); // No need to XOR RDI
11283 ins_encode(enc_PartialSubtypeCheck());
11284 ins_pipe(pipe_slow);
11285 %}
11286
11287 // ============================================================================
11288 // Branch Instructions -- short offset versions
11289 //
11290 // These instructions are used to replace jumps of a long offset (the default
11291 // match) with jumps of a shorter offset. These instructions are all tagged
11292 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11293 // match rules in general matching. Instead, the ADLC generates a conversion
11294 // method in the MachNode which can be used to do in-place replacement of the
11295 // long variant with the shorter variant. The compiler will determine if a
11296 // branch can be taken by the is_short_branch_offset() predicate in the machine
11297 // specific code section of the file.
11298
11299 // Jump Direct - Label defines a relative address from JMP+1
11300 instruct jmpDir_short(label labl) %{
11301 match(Goto);
11302 effect(USE labl);
11303
11304 ins_cost(300);
11305 format %{ "jmp,s $labl" %}
11306 size(2);
11307 ins_encode %{
11308 Label* L = $labl$$label;
11309 __ jmpb(*L);
11310 %}
11311 ins_pipe(pipe_jmp);
11312 ins_short_branch(1);
11313 %}
11314
11315 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11316 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11317 match(If cop cr);
11318 effect(USE labl);
11319
11320 ins_cost(300);
11321 format %{ "j$cop,s $labl" %}
11322 size(2);
11323 ins_encode %{
11324 Label* L = $labl$$label;
11325 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11326 %}
11327 ins_pipe(pipe_jcc);
11328 ins_short_branch(1);
11329 %}
11330
11331 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11332 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11333 match(CountedLoopEnd cop cr);
11334 effect(USE labl);
11335
11336 ins_cost(300);
11337 format %{ "j$cop,s $labl\t# loop end" %}
11338 size(2);
11339 ins_encode %{
11340 Label* L = $labl$$label;
11341 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11342 %}
11343 ins_pipe(pipe_jcc);
11344 ins_short_branch(1);
11345 %}
11346
11347 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11348 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11349 match(CountedLoopEnd cop cmp);
11350 effect(USE labl);
11351
11352 ins_cost(300);
11353 format %{ "j$cop,us $labl\t# loop end" %}
11354 size(2);
11355 ins_encode %{
11356 Label* L = $labl$$label;
11357 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11358 %}
11359 ins_pipe(pipe_jcc);
11360 ins_short_branch(1);
11361 %}
11362
11363 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11364 match(CountedLoopEnd cop cmp);
11365 effect(USE labl);
11366
11367 ins_cost(300);
11368 format %{ "j$cop,us $labl\t# loop end" %}
11369 size(2);
11370 ins_encode %{
11371 Label* L = $labl$$label;
11372 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11373 %}
11374 ins_pipe(pipe_jcc);
11375 ins_short_branch(1);
11376 %}
11377
11378 // Jump Direct Conditional - using unsigned comparison
11379 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11380 match(If cop cmp);
11381 effect(USE labl);
11382
11383 ins_cost(300);
11384 format %{ "j$cop,us $labl" %}
11385 size(2);
11386 ins_encode %{
11387 Label* L = $labl$$label;
11388 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11389 %}
11390 ins_pipe(pipe_jcc);
11391 ins_short_branch(1);
11392 %}
11393
11394 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11395 match(If cop cmp);
11396 effect(USE labl);
11397
11398 ins_cost(300);
11399 format %{ "j$cop,us $labl" %}
11400 size(2);
11401 ins_encode %{
11402 Label* L = $labl$$label;
11403 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11404 %}
11405 ins_pipe(pipe_jcc);
11406 ins_short_branch(1);
11407 %}
11408
11409 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11410 match(If cop cmp);
11411 effect(USE labl);
11412
11413 ins_cost(300);
11414 format %{ $$template
11415 if ($cop$$cmpcode == Assembler::notEqual) {
11416 $$emit$$"jp,u,s $labl\n\t"
11417 $$emit$$"j$cop,u,s $labl"
11418 } else {
11419 $$emit$$"jp,u,s done\n\t"
11420 $$emit$$"j$cop,u,s $labl\n\t"
11421 $$emit$$"done:"
11422 }
11423 %}
11424 size(4);
11425 ins_encode %{
11426 Label* l = $labl$$label;
11427 if ($cop$$cmpcode == Assembler::notEqual) {
11428 __ jccb(Assembler::parity, *l);
11429 __ jccb(Assembler::notEqual, *l);
11430 } else if ($cop$$cmpcode == Assembler::equal) {
11431 Label done;
11432 __ jccb(Assembler::parity, done);
11433 __ jccb(Assembler::equal, *l);
11434 __ bind(done);
11435 } else {
11436 ShouldNotReachHere();
11437 }
11438 %}
11439 ins_pipe(pipe_jcc);
11440 ins_short_branch(1);
11441 %}
11442
11443 // ============================================================================
11444 // inlined locking and unlocking
11445
11446 instruct cmpFastLock(rFlagsReg cr,
11447 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
11448 %{
11449 match(Set cr (FastLock object box));
11450 effect(TEMP tmp, TEMP scr, USE_KILL box);
11451
11452 ins_cost(300);
11453 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11454 ins_encode(Fast_Lock(object, box, tmp, scr));
11455 ins_pipe(pipe_slow);
11456 %}
11457
11458 instruct cmpFastUnlock(rFlagsReg cr,
11459 rRegP object, rax_RegP box, rRegP tmp)
11460 %{
11461 match(Set cr (FastUnlock object box));
11462 effect(TEMP tmp, USE_KILL box);
11463
11464 ins_cost(300);
11465 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11466 ins_encode(Fast_Unlock(object, box, tmp));
11467 ins_pipe(pipe_slow);
11468 %}
11469
11470
11471 // ============================================================================
11472 // Safepoint Instructions
11473 instruct safePoint_poll(rFlagsReg cr)
11474 %{
11475 predicate(!Assembler::is_polling_page_far());
11476 match(SafePoint);
11477 effect(KILL cr);
11478
11479 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11480 "# Safepoint: poll for GC" %}
11481 ins_cost(125);
11482 ins_encode %{
11483 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11484 __ testl(rax, addr);
11485 %}
11486 ins_pipe(ialu_reg_mem);
11487 %}
11488
11489 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11490 %{
11491 predicate(Assembler::is_polling_page_far());
11492 match(SafePoint poll);
11493 effect(KILL cr, USE poll);
11494
11495 format %{ "testl rax, [$poll]\t"
11496 "# Safepoint: poll for GC" %}
11497 ins_cost(125);
11498 ins_encode %{
11499 __ relocate(relocInfo::poll_type);
11500 __ testl(rax, Address($poll$$Register, 0));
11501 %}
11502 ins_pipe(ialu_reg_mem);
11503 %}
11504
11505 // ============================================================================
11506 // Procedure Call/Return Instructions
11507 // Call Java Static Instruction
11508 // Note: If this code changes, the corresponding ret_addr_offset() and
11509 // compute_padding() functions will have to be adjusted.
11510 instruct CallStaticJavaDirect(method meth) %{
11511 match(CallStaticJava);
11512 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11513 effect(USE meth);
11514
11515 ins_cost(300);
11516 format %{ "call,static " %}
11517 opcode(0xE8); /* E8 cd */
11518 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11519 ins_pipe(pipe_slow);
11520 ins_alignment(4);
11521 %}
11522
11523 // Call Java Static Instruction (method handle version)
11524 // Note: If this code changes, the corresponding ret_addr_offset() and
11525 // compute_padding() functions will have to be adjusted.
11526 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11527 match(CallStaticJava);
11528 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11529 effect(USE meth);
11530 // RBP is saved by all callees (for interpreter stack correction).
11531 // We use it here for a similar purpose, in {preserve,restore}_SP.
11532
11533 ins_cost(300);
11534 format %{ "call,static/MethodHandle " %}
11535 opcode(0xE8); /* E8 cd */
11536 ins_encode(clear_avx, preserve_SP,
11537 Java_Static_Call(meth),
11538 restore_SP,
11539 call_epilog);
11540 ins_pipe(pipe_slow);
11541 ins_alignment(4);
11542 %}
11543
11544 // Call Java Dynamic Instruction
11545 // Note: If this code changes, the corresponding ret_addr_offset() and
11546 // compute_padding() functions will have to be adjusted.
11547 instruct CallDynamicJavaDirect(method meth)
11548 %{
11549 match(CallDynamicJava);
11550 effect(USE meth);
11551
11552 ins_cost(300);
11553 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11554 "call,dynamic " %}
11555 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11556 ins_pipe(pipe_slow);
11557 ins_alignment(4);
11558 %}
11559
11560 // Call Runtime Instruction
11561 instruct CallRuntimeDirect(method meth)
11562 %{
11563 match(CallRuntime);
11564 effect(USE meth);
11565
11566 ins_cost(300);
11567 format %{ "call,runtime " %}
11568 ins_encode(clear_avx, Java_To_Runtime(meth));
11569 ins_pipe(pipe_slow);
11570 %}
11571
11572 // Call runtime without safepoint
11573 instruct CallLeafDirect(method meth)
11574 %{
11575 match(CallLeaf);
11576 effect(USE meth);
11577
11578 ins_cost(300);
11579 format %{ "call_leaf,runtime " %}
11580 ins_encode(clear_avx, Java_To_Runtime(meth));
11581 ins_pipe(pipe_slow);
11582 %}
11583
11584 // Call runtime without safepoint
11585 instruct CallLeafNoFPDirect(method meth)
11586 %{
11587 match(CallLeafNoFP);
11588 effect(USE meth);
11589
11590 ins_cost(300);
11591 format %{ "call_leaf_nofp,runtime " %}
11592 ins_encode(Java_To_Runtime(meth));
11593 ins_pipe(pipe_slow);
11594 %}
11595
11596 // Return Instruction
11597 // Remove the return address & jump to it.
11598 // Notice: We always emit a nop after a ret to make sure there is room
11599 // for safepoint patching
11600 instruct Ret()
11601 %{
11602 match(Return);
11603
11604 format %{ "ret" %}
11605 opcode(0xC3);
11606 ins_encode(OpcP);
11607 ins_pipe(pipe_jmp);
11608 %}
11609
11610 // Tail Call; Jump from runtime stub to Java code.
11611 // Also known as an 'interprocedural jump'.
11612 // Target of jump will eventually return to caller.
11613 // TailJump below removes the return address.
11614 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11615 %{
11616 match(TailCall jump_target method_oop);
11617
11618 ins_cost(300);
11619 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11620 opcode(0xFF, 0x4); /* Opcode FF /4 */
11621 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11622 ins_pipe(pipe_jmp);
11623 %}
11624
11625 // Tail Jump; remove the return address; jump to target.
11626 // TailCall above leaves the return address around.
11627 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11628 %{
11629 match(TailJump jump_target ex_oop);
11630
11631 ins_cost(300);
11632 format %{ "popq rdx\t# pop return address\n\t"
11633 "jmp $jump_target" %}
11634 opcode(0xFF, 0x4); /* Opcode FF /4 */
11635 ins_encode(Opcode(0x5a), // popq rdx
11636 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11637 ins_pipe(pipe_jmp);
11638 %}
11639
11640 // Create exception oop: created by stack-crawling runtime code.
11641 // Created exception is now available to this handler, and is setup
11642 // just prior to jumping to this handler. No code emitted.
11643 instruct CreateException(rax_RegP ex_oop)
11644 %{
11645 match(Set ex_oop (CreateEx));
11646
11647 size(0);
11648 // use the following format syntax
11649 format %{ "# exception oop is in rax; no code emitted" %}
11650 ins_encode();
11651 ins_pipe(empty);
11652 %}
11653
11654 // Rethrow exception:
11655 // The exception oop will come in the first argument position.
11656 // Then JUMP (not call) to the rethrow stub code.
11657 instruct RethrowException()
11658 %{
11659 match(Rethrow);
11660
11661 // use the following format syntax
11662 format %{ "jmp rethrow_stub" %}
11663 ins_encode(enc_rethrow);
11664 ins_pipe(pipe_jmp);
11665 %}
11666
11667
11668 // ============================================================================
11669 // This name is KNOWN by the ADLC and cannot be changed.
11670 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11671 // for this guy.
11672 instruct tlsLoadP(r15_RegP dst) %{
11673 match(Set dst (ThreadLocal));
11674 effect(DEF dst);
11675
11676 size(0);
11677 format %{ "# TLS is in R15" %}
11678 ins_encode( /*empty encoding*/ );
11679 ins_pipe(ialu_reg_reg);
11680 %}
11681
11682
11683 //----------PEEPHOLE RULES-----------------------------------------------------
11684 // These must follow all instruction definitions as they use the names
11685 // defined in the instructions definitions.
11686 //
11687 // peepmatch ( root_instr_name [preceding_instruction]* );
11688 //
11689 // peepconstraint %{
11690 // (instruction_number.operand_name relational_op instruction_number.operand_name
11691 // [, ...] );
11692 // // instruction numbers are zero-based using left to right order in peepmatch
11693 //
11694 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11695 // // provide an instruction_number.operand_name for each operand that appears
11696 // // in the replacement instruction's match rule
11697 //
11698 // ---------VM FLAGS---------------------------------------------------------
11699 //
11700 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11701 //
11702 // Each peephole rule is given an identifying number starting with zero and
11703 // increasing by one in the order seen by the parser. An individual peephole
11704 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11705 // on the command-line.
11706 //
11707 // ---------CURRENT LIMITATIONS----------------------------------------------
11708 //
11709 // Only match adjacent instructions in same basic block
11710 // Only equality constraints
11711 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11712 // Only one replacement instruction
11713 //
11714 // ---------EXAMPLE----------------------------------------------------------
11715 //
11716 // // pertinent parts of existing instructions in architecture description
11717 // instruct movI(rRegI dst, rRegI src)
11718 // %{
11719 // match(Set dst (CopyI src));
11720 // %}
11721 //
11722 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11723 // %{
11724 // match(Set dst (AddI dst src));
11725 // effect(KILL cr);
11726 // %}
11727 //
11728 // // Change (inc mov) to lea
11729 // peephole %{
11730 // // increment preceeded by register-register move
11731 // peepmatch ( incI_rReg movI );
11732 // // require that the destination register of the increment
11733 // // match the destination register of the move
11734 // peepconstraint ( 0.dst == 1.dst );
11735 // // construct a replacement instruction that sets
11736 // // the destination to ( move's source register + one )
11737 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11738 // %}
11739 //
11740
11741 // Implementation no longer uses movX instructions since
11742 // machine-independent system no longer uses CopyX nodes.
11743 //
11744 // peephole
11745 // %{
11746 // peepmatch (incI_rReg movI);
11747 // peepconstraint (0.dst == 1.dst);
11748 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11749 // %}
11750
11751 // peephole
11752 // %{
11753 // peepmatch (decI_rReg movI);
11754 // peepconstraint (0.dst == 1.dst);
11755 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11756 // %}
11757
11758 // peephole
11759 // %{
11760 // peepmatch (addI_rReg_imm movI);
11761 // peepconstraint (0.dst == 1.dst);
11762 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11763 // %}
11764
11765 // peephole
11766 // %{
11767 // peepmatch (incL_rReg movL);
11768 // peepconstraint (0.dst == 1.dst);
11769 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11770 // %}
11771
11772 // peephole
11773 // %{
11774 // peepmatch (decL_rReg movL);
11775 // peepconstraint (0.dst == 1.dst);
11776 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11777 // %}
11778
11779 // peephole
11780 // %{
11781 // peepmatch (addL_rReg_imm movL);
11782 // peepconstraint (0.dst == 1.dst);
11783 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11784 // %}
11785
11786 // peephole
11787 // %{
11788 // peepmatch (addP_rReg_imm movP);
11789 // peepconstraint (0.dst == 1.dst);
11790 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11791 // %}
11792
11793 // // Change load of spilled value to only a spill
11794 // instruct storeI(memory mem, rRegI src)
11795 // %{
11796 // match(Set mem (StoreI mem src));
11797 // %}
11798 //
11799 // instruct loadI(rRegI dst, memory mem)
11800 // %{
11801 // match(Set dst (LoadI mem));
11802 // %}
11803 //
11804
11805 peephole
11806 %{
11807 peepmatch (loadI storeI);
11808 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11809 peepreplace (storeI(1.mem 1.mem 1.src));
11810 %}
11811
11812 peephole
11813 %{
11814 peepmatch (loadL storeL);
11815 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11816 peepreplace (storeL(1.mem 1.mem 1.src));
11817 %}
11818
11819 //----------SMARTSPILL RULES---------------------------------------------------
11820 // These must follow all instruction definitions as they use the names
11821 // defined in the instructions definitions.