5709 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5710 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5711
5712 size(2*4);
5713 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5714 "AND $dst,$mask,$dst" %}
5715 ins_encode %{
5716 Register Rdst = $dst$$Register;
5717 __ lduh($mem$$Address, Rdst);
5718 __ and3(Rdst, $mask$$constant, Rdst);
5719 %}
5720 ins_pipe(iload_mem);
5721 %}
5722
5723 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5724 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5725 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5726 effect(TEMP dst, TEMP tmp);
5727 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5728
5729 size((3+1)*4); // set may use two instructions.
5730 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5731 "SET $mask,$tmp\n\t"
5732 "AND $dst,$tmp,$dst" %}
5733 ins_encode %{
5734 Register Rdst = $dst$$Register;
5735 Register Rtmp = $tmp$$Register;
5736 __ lduh($mem$$Address, Rdst);
5737 __ set($mask$$constant, Rtmp);
5738 __ and3(Rdst, Rtmp, Rdst);
5739 %}
5740 ins_pipe(iload_mem);
5741 %}
5742
5743 // Load Integer
5744 instruct loadI(iRegI dst, memory mem) %{
5745 match(Set dst (LoadI mem));
5746 ins_cost(MEMORY_REF_COST);
5747
5748 size(4);
5749 format %{ "LDUW $mem,$dst\t! int" %}
5853 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5854 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5855
5856 size(2*4);
5857 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5858 "AND $dst,$mask,$dst" %}
5859 ins_encode %{
5860 Register Rdst = $dst$$Register;
5861 __ lduw($mem$$Address, Rdst);
5862 __ and3(Rdst, $mask$$constant, Rdst);
5863 %}
5864 ins_pipe(iload_mem);
5865 %}
5866
5867 // Load Integer with a 32-bit mask into a Long Register
5868 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5869 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5870 effect(TEMP dst, TEMP tmp);
5871 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5872
5873 size((3+1)*4); // set may use two instructions.
5874 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5875 "SET $mask,$tmp\n\t"
5876 "AND $dst,$tmp,$dst" %}
5877 ins_encode %{
5878 Register Rdst = $dst$$Register;
5879 Register Rtmp = $tmp$$Register;
5880 __ lduw($mem$$Address, Rdst);
5881 __ set($mask$$constant, Rtmp);
5882 __ and3(Rdst, Rtmp, Rdst);
5883 %}
5884 ins_pipe(iload_mem);
5885 %}
5886
5887 // Load Unsigned Integer into a Long Register
5888 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5889 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5890 ins_cost(MEMORY_REF_COST);
5891
5892 size(4);
5893 format %{ "LDUW $mem,$dst\t! uint -> long" %}
|
5709 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5710 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5711
5712 size(2*4);
5713 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5714 "AND $dst,$mask,$dst" %}
5715 ins_encode %{
5716 Register Rdst = $dst$$Register;
5717 __ lduh($mem$$Address, Rdst);
5718 __ and3(Rdst, $mask$$constant, Rdst);
5719 %}
5720 ins_pipe(iload_mem);
5721 %}
5722
5723 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5724 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5725 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5726 effect(TEMP dst, TEMP tmp);
5727 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5728
5729 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5730 "SET $mask,$tmp\n\t"
5731 "AND $dst,$tmp,$dst" %}
5732 ins_encode %{
5733 Register Rdst = $dst$$Register;
5734 Register Rtmp = $tmp$$Register;
5735 __ lduh($mem$$Address, Rdst);
5736 __ set($mask$$constant, Rtmp);
5737 __ and3(Rdst, Rtmp, Rdst);
5738 %}
5739 ins_pipe(iload_mem);
5740 %}
5741
5742 // Load Integer
5743 instruct loadI(iRegI dst, memory mem) %{
5744 match(Set dst (LoadI mem));
5745 ins_cost(MEMORY_REF_COST);
5746
5747 size(4);
5748 format %{ "LDUW $mem,$dst\t! int" %}
5852 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5853 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5854
5855 size(2*4);
5856 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5857 "AND $dst,$mask,$dst" %}
5858 ins_encode %{
5859 Register Rdst = $dst$$Register;
5860 __ lduw($mem$$Address, Rdst);
5861 __ and3(Rdst, $mask$$constant, Rdst);
5862 %}
5863 ins_pipe(iload_mem);
5864 %}
5865
5866 // Load Integer with a 32-bit mask into a Long Register
5867 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5868 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5869 effect(TEMP dst, TEMP tmp);
5870 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5871
5872 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5873 "SET $mask,$tmp\n\t"
5874 "AND $dst,$tmp,$dst" %}
5875 ins_encode %{
5876 Register Rdst = $dst$$Register;
5877 Register Rtmp = $tmp$$Register;
5878 __ lduw($mem$$Address, Rdst);
5879 __ set($mask$$constant, Rtmp);
5880 __ and3(Rdst, Rtmp, Rdst);
5881 %}
5882 ins_pipe(iload_mem);
5883 %}
5884
5885 // Load Unsigned Integer into a Long Register
5886 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5887 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5888 ins_cost(MEMORY_REF_COST);
5889
5890 size(4);
5891 format %{ "LDUW $mem,$dst\t! uint -> long" %}
|