1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
94
95 // Implementation of Address
96
97 #ifdef _LP64
98
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
105
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
134
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
143
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
152
153 #endif // _LP64
154
155
156
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
176
177 // Implementation of Assembler
178
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
182
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
189
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
199
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
208
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
216
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
226
227
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
242
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
252
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
267
268
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
274
275
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
281
282 // Encode the registers as needed in the fields they are used in
283
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
287
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
366
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
370
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
382
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
393
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
399
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
402
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
406
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
413
414 // If "which" is end_pc_operand, find the end of the instruction.
415
416 address ip = inst;
417 bool is_64bit = false;
418
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
421
422 again_after_prefix:
423 switch (0xFF & *ip++) {
424
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
431
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
442
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
454
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
466
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
475
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
482
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
519
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
530 #endif // _LP64
531 return ip;
532
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
538
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
547
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
553
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
567
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
583
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
589
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
594
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
603
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
610
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
616
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
626
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
641
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
649
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
665
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
668
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
688
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
700
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
706
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
710
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
737
738 default:
739 ShouldNotReachHere();
740
741 #undef REP8
742 #undef REP16
743 }
744
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
753
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
765
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
773
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
780
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
787
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
796
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
801
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
805
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
813
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
818
819
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
825
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
843
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
850
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
857
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
862
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
868
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
874
875
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
882
883
884 // Now the Assembler instructions (identical for 32/64 bits)
885
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
891
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
898
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
903
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
910
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
915
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
921
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
928
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
933
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
940
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
945
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
954
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
964
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
985
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
990
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1013
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1020
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1028
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1035
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1043
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1050
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1058
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1065
1066
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1116 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1117 emit_int8(0x0F);
1118 emit_int8((unsigned char)0xBD);
1119 emit_int8((unsigned char)(0xC0 | encode));
1120 }
1121
1122 void Assembler::bswapl(Register reg) { // bswap
1123 int encode = prefix_and_encode(reg->encoding());
1124 emit_int8(0x0F);
1125 emit_int8((unsigned char)(0xC8 | encode));
1126 }
1127
1128 void Assembler::blsil(Register dst, Register src) {
1129 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1130 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1131 emit_int8((unsigned char)0xF3);
1132 emit_int8((unsigned char)(0xC0 | encode));
1133 }
1134
1135 void Assembler::blsil(Register dst, Address src) {
1136 InstructionMark im(this);
1137 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1138 vex_prefix_0F38(rbx, dst, src);
1139 emit_int8((unsigned char)0xF3);
1140 emit_operand(rbx, src);
1141 }
1142
1143 void Assembler::blsmskl(Register dst, Register src) {
1144 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1145 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1146 emit_int8((unsigned char)0xF3);
1147 emit_int8((unsigned char)(0xC0 | encode));
1148 }
1149
1150 void Assembler::blsmskl(Register dst, Address src) {
1151 InstructionMark im(this);
1152 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1153 vex_prefix_0F38(rdx, dst, src);
1154 emit_int8((unsigned char)0xF3);
1155 emit_operand(rdx, src);
1156 }
1157
1158 void Assembler::blsrl(Register dst, Register src) {
1159 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1160 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1161 emit_int8((unsigned char)0xF3);
1162 emit_int8((unsigned char)(0xC0 | encode));
1163 }
1164
1165 void Assembler::blsrl(Register dst, Address src) {
1166 InstructionMark im(this);
1167 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1168 vex_prefix_0F38(rcx, dst, src);
1169 emit_int8((unsigned char)0xF3);
1170 emit_operand(rcx, src);
1171 }
1172
1173 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1174 // suspect disp32 is always good
1175 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1176
1177 if (L.is_bound()) {
1178 const int long_size = 5;
1179 int offs = (int)( target(L) - pc() );
1180 assert(offs <= 0, "assembler error");
1181 InstructionMark im(this);
1182 // 1110 1000 #32-bit disp
1183 emit_int8((unsigned char)0xE8);
1184 emit_data(offs - long_size, rtype, operand);
1185 } else {
1186 InstructionMark im(this);
1187 // 1110 1000 #32-bit disp
1188 L.add_patch_at(code(), locator());
1189
1190 emit_int8((unsigned char)0xE8);
1191 emit_data(int(0), rtype, operand);
1192 }
1193 }
1194
1195 void Assembler::call(Register dst) {
1196 int encode = prefix_and_encode(dst->encoding());
1197 emit_int8((unsigned char)0xFF);
1198 emit_int8((unsigned char)(0xD0 | encode));
1199 }
1200
1201
1202 void Assembler::call(Address adr) {
1203 InstructionMark im(this);
1204 prefix(adr);
1205 emit_int8((unsigned char)0xFF);
1206 emit_operand(rdx, adr);
1207 }
1208
1209 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1210 assert(entry != NULL, "call most probably wrong");
1211 InstructionMark im(this);
1212 emit_int8((unsigned char)0xE8);
1213 intptr_t disp = entry - (pc() + sizeof(int32_t));
1214 assert(is_simm32(disp), "must be 32bit offset (call2)");
1215 // Technically, should use call32_operand, but this format is
1216 // implied by the fact that we're emitting a call instruction.
1217
1218 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1219 emit_data((int) disp, rspec, operand);
1220 }
1221
1222 void Assembler::cdql() {
1223 emit_int8((unsigned char)0x99);
1224 }
1225
1226 void Assembler::cld() {
1227 emit_int8((unsigned char)0xFC);
1228 }
1229
1230 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1231 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1232 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1233 emit_int8(0x0F);
1234 emit_int8(0x40 | cc);
1235 emit_int8((unsigned char)(0xC0 | encode));
1236 }
1237
1238
1239 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1240 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1241 prefix(src, dst);
1242 emit_int8(0x0F);
1243 emit_int8(0x40 | cc);
1244 emit_operand(dst, src);
1245 }
1246
1247 void Assembler::cmpb(Address dst, int imm8) {
1248 InstructionMark im(this);
1249 prefix(dst);
1250 emit_int8((unsigned char)0x80);
1251 emit_operand(rdi, dst, 1);
1252 emit_int8(imm8);
1253 }
1254
1255 void Assembler::cmpl(Address dst, int32_t imm32) {
1256 InstructionMark im(this);
1257 prefix(dst);
1258 emit_int8((unsigned char)0x81);
1259 emit_operand(rdi, dst, 4);
1260 emit_int32(imm32);
1261 }
1262
1263 void Assembler::cmpl(Register dst, int32_t imm32) {
1264 prefix(dst);
1265 emit_arith(0x81, 0xF8, dst, imm32);
1266 }
1267
1268 void Assembler::cmpl(Register dst, Register src) {
1269 (void) prefix_and_encode(dst->encoding(), src->encoding());
1270 emit_arith(0x3B, 0xC0, dst, src);
1271 }
1272
1273
1274 void Assembler::cmpl(Register dst, Address src) {
1275 InstructionMark im(this);
1276 prefix(src, dst);
1277 emit_int8((unsigned char)0x3B);
1278 emit_operand(dst, src);
1279 }
1280
1281 void Assembler::cmpw(Address dst, int imm16) {
1282 InstructionMark im(this);
1283 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1284 emit_int8(0x66);
1285 emit_int8((unsigned char)0x81);
1286 emit_operand(rdi, dst, 2);
1287 emit_int16(imm16);
1288 }
1289
1290 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1291 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1292 // The ZF is set if the compared values were equal, and cleared otherwise.
1293 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1294 InstructionMark im(this);
1295 prefix(adr, reg);
1296 emit_int8(0x0F);
1297 emit_int8((unsigned char)0xB1);
1298 emit_operand(reg, adr);
1299 }
1300
1301 void Assembler::comisd(XMMRegister dst, Address src) {
1302 // NOTE: dbx seems to decode this as comiss even though the
1303 // 0x66 is there. Strangly ucomisd comes out correct
1304 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1305 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1306 }
1307
1308 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1309 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1310 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1311 }
1312
1313 void Assembler::comiss(XMMRegister dst, Address src) {
1314 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1315 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1316 }
1317
1318 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1319 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1320 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1321 }
1322
1323 void Assembler::cpuid() {
1324 emit_int8(0x0F);
1325 emit_int8((unsigned char)0xA2);
1326 }
1327
1328 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1330 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1331 }
1332
1333 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1335 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1336 }
1337
1338 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1340 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1341 }
1342
1343 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1345 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1346 }
1347
1348 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1351 emit_int8(0x2A);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1356 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1357 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1358 }
1359
1360 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1361 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1362 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1363 emit_int8(0x2A);
1364 emit_int8((unsigned char)(0xC0 | encode));
1365 }
1366
1367 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1368 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1369 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1370 }
1371
1372 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1374 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1375 }
1376
1377 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1379 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1380 }
1381
1382
1383 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1385 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1386 emit_int8(0x2C);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1391 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1392 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1393 emit_int8(0x2C);
1394 emit_int8((unsigned char)(0xC0 | encode));
1395 }
1396
1397 void Assembler::decl(Address dst) {
1398 // Don't use it directly. Use MacroAssembler::decrement() instead.
1399 InstructionMark im(this);
1400 prefix(dst);
1401 emit_int8((unsigned char)0xFF);
1402 emit_operand(rcx, dst);
1403 }
1404
1405 void Assembler::divsd(XMMRegister dst, Address src) {
1406 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1407 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1408 }
1409
1410 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1412 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1413 }
1414
1415 void Assembler::divss(XMMRegister dst, Address src) {
1416 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1417 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1418 }
1419
1420 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1421 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1422 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1423 }
1424
1425 void Assembler::emms() {
1426 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1427 emit_int8(0x0F);
1428 emit_int8(0x77);
1429 }
1430
1431 void Assembler::hlt() {
1432 emit_int8((unsigned char)0xF4);
1433 }
1434
1435 void Assembler::idivl(Register src) {
1436 int encode = prefix_and_encode(src->encoding());
1437 emit_int8((unsigned char)0xF7);
1438 emit_int8((unsigned char)(0xF8 | encode));
1439 }
1440
1441 void Assembler::divl(Register src) { // Unsigned
1442 int encode = prefix_and_encode(src->encoding());
1443 emit_int8((unsigned char)0xF7);
1444 emit_int8((unsigned char)(0xF0 | encode));
1445 }
1446
1447 void Assembler::imull(Register dst, Register src) {
1448 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1449 emit_int8(0x0F);
1450 emit_int8((unsigned char)0xAF);
1451 emit_int8((unsigned char)(0xC0 | encode));
1452 }
1453
1454
1455 void Assembler::imull(Register dst, Register src, int value) {
1456 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1457 if (is8bit(value)) {
1458 emit_int8(0x6B);
1459 emit_int8((unsigned char)(0xC0 | encode));
1460 emit_int8(value & 0xFF);
1461 } else {
1462 emit_int8(0x69);
1463 emit_int8((unsigned char)(0xC0 | encode));
1464 emit_int32(value);
1465 }
1466 }
1467
1468 void Assembler::imull(Register dst, Address src) {
1469 InstructionMark im(this);
1470 prefix(src, dst);
1471 emit_int8(0x0F);
1472 emit_int8((unsigned char) 0xAF);
1473 emit_operand(dst, src);
1474 }
1475
1476
1477 void Assembler::incl(Address dst) {
1478 // Don't use it directly. Use MacroAssembler::increment() instead.
1479 InstructionMark im(this);
1480 prefix(dst);
1481 emit_int8((unsigned char)0xFF);
1482 emit_operand(rax, dst);
1483 }
1484
1485 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1486 InstructionMark im(this);
1487 assert((0 <= cc) && (cc < 16), "illegal cc");
1488 if (L.is_bound()) {
1489 address dst = target(L);
1490 assert(dst != NULL, "jcc most probably wrong");
1491
1492 const int short_size = 2;
1493 const int long_size = 6;
1494 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1495 if (maybe_short && is8bit(offs - short_size)) {
1496 // 0111 tttn #8-bit disp
1497 emit_int8(0x70 | cc);
1498 emit_int8((offs - short_size) & 0xFF);
1499 } else {
1500 // 0000 1111 1000 tttn #32-bit disp
1501 assert(is_simm32(offs - long_size),
1502 "must be 32bit offset (call4)");
1503 emit_int8(0x0F);
1504 emit_int8((unsigned char)(0x80 | cc));
1505 emit_int32(offs - long_size);
1506 }
1507 } else {
1508 // Note: could eliminate cond. jumps to this jump if condition
1509 // is the same however, seems to be rather unlikely case.
1510 // Note: use jccb() if label to be bound is very close to get
1511 // an 8-bit displacement
1512 L.add_patch_at(code(), locator());
1513 emit_int8(0x0F);
1514 emit_int8((unsigned char)(0x80 | cc));
1515 emit_int32(0);
1516 }
1517 }
1518
1519 void Assembler::jccb(Condition cc, Label& L) {
1520 if (L.is_bound()) {
1521 const int short_size = 2;
1522 address entry = target(L);
1523 #ifdef ASSERT
1524 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1525 intptr_t delta = short_branch_delta();
1526 if (delta != 0) {
1527 dist += (dist < 0 ? (-delta) :delta);
1528 }
1529 assert(is8bit(dist), "Dispacement too large for a short jmp");
1530 #endif
1531 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1532 // 0111 tttn #8-bit disp
1533 emit_int8(0x70 | cc);
1534 emit_int8((offs - short_size) & 0xFF);
1535 } else {
1536 InstructionMark im(this);
1537 L.add_patch_at(code(), locator());
1538 emit_int8(0x70 | cc);
1539 emit_int8(0);
1540 }
1541 }
1542
1543 void Assembler::jmp(Address adr) {
1544 InstructionMark im(this);
1545 prefix(adr);
1546 emit_int8((unsigned char)0xFF);
1547 emit_operand(rsp, adr);
1548 }
1549
1550 void Assembler::jmp(Label& L, bool maybe_short) {
1551 if (L.is_bound()) {
1552 address entry = target(L);
1553 assert(entry != NULL, "jmp most probably wrong");
1554 InstructionMark im(this);
1555 const int short_size = 2;
1556 const int long_size = 5;
1557 intptr_t offs = entry - pc();
1558 if (maybe_short && is8bit(offs - short_size)) {
1559 emit_int8((unsigned char)0xEB);
1560 emit_int8((offs - short_size) & 0xFF);
1561 } else {
1562 emit_int8((unsigned char)0xE9);
1563 emit_int32(offs - long_size);
1564 }
1565 } else {
1566 // By default, forward jumps are always 32-bit displacements, since
1567 // we can't yet know where the label will be bound. If you're sure that
1568 // the forward jump will not run beyond 256 bytes, use jmpb to
1569 // force an 8-bit displacement.
1570 InstructionMark im(this);
1571 L.add_patch_at(code(), locator());
1572 emit_int8((unsigned char)0xE9);
1573 emit_int32(0);
1574 }
1575 }
1576
1577 void Assembler::jmp(Register entry) {
1578 int encode = prefix_and_encode(entry->encoding());
1579 emit_int8((unsigned char)0xFF);
1580 emit_int8((unsigned char)(0xE0 | encode));
1581 }
1582
1583 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1584 InstructionMark im(this);
1585 emit_int8((unsigned char)0xE9);
1586 assert(dest != NULL, "must have a target");
1587 intptr_t disp = dest - (pc() + sizeof(int32_t));
1588 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1589 emit_data(disp, rspec.reloc(), call32_operand);
1590 }
1591
1592 void Assembler::jmpb(Label& L) {
1593 if (L.is_bound()) {
1594 const int short_size = 2;
1595 address entry = target(L);
1596 assert(entry != NULL, "jmp most probably wrong");
1597 #ifdef ASSERT
1598 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1599 intptr_t delta = short_branch_delta();
1600 if (delta != 0) {
1601 dist += (dist < 0 ? (-delta) :delta);
1602 }
1603 assert(is8bit(dist), "Dispacement too large for a short jmp");
1604 #endif
1605 intptr_t offs = entry - pc();
1606 emit_int8((unsigned char)0xEB);
1607 emit_int8((offs - short_size) & 0xFF);
1608 } else {
1609 InstructionMark im(this);
1610 L.add_patch_at(code(), locator());
1611 emit_int8((unsigned char)0xEB);
1612 emit_int8(0);
1613 }
1614 }
1615
1616 void Assembler::ldmxcsr( Address src) {
1617 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1618 InstructionMark im(this);
1619 prefix(src);
1620 emit_int8(0x0F);
1621 emit_int8((unsigned char)0xAE);
1622 emit_operand(as_Register(2), src);
1623 }
1624
1625 void Assembler::leal(Register dst, Address src) {
1626 InstructionMark im(this);
1627 #ifdef _LP64
1628 emit_int8(0x67); // addr32
1629 prefix(src, dst);
1630 #endif // LP64
1631 emit_int8((unsigned char)0x8D);
1632 emit_operand(dst, src);
1633 }
1634
1635 void Assembler::lfence() {
1636 emit_int8(0x0F);
1637 emit_int8((unsigned char)0xAE);
1638 emit_int8((unsigned char)0xE8);
1639 }
1640
1641 void Assembler::lock() {
1642 emit_int8((unsigned char)0xF0);
1643 }
1644
1645 void Assembler::lzcntl(Register dst, Register src) {
1646 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1647 emit_int8((unsigned char)0xF3);
1648 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1649 emit_int8(0x0F);
1650 emit_int8((unsigned char)0xBD);
1651 emit_int8((unsigned char)(0xC0 | encode));
1652 }
1653
1654 // Emit mfence instruction
1655 void Assembler::mfence() {
1656 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1657 emit_int8(0x0F);
1658 emit_int8((unsigned char)0xAE);
1659 emit_int8((unsigned char)0xF0);
1660 }
1661
1662 void Assembler::mov(Register dst, Register src) {
1663 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1664 }
1665
1666 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1668 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1669 }
1670
1671 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1673 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1674 }
1675
1676 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1677 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1678 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1679 emit_int8(0x16);
1680 emit_int8((unsigned char)(0xC0 | encode));
1681 }
1682
1683 void Assembler::movb(Register dst, Address src) {
1684 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1685 InstructionMark im(this);
1686 prefix(src, dst, true);
1687 emit_int8((unsigned char)0x8A);
1688 emit_operand(dst, src);
1689 }
1690
1691
1692 void Assembler::movb(Address dst, int imm8) {
1693 InstructionMark im(this);
1694 prefix(dst);
1695 emit_int8((unsigned char)0xC6);
1696 emit_operand(rax, dst, 1);
1697 emit_int8(imm8);
1698 }
1699
1700
1701 void Assembler::movb(Address dst, Register src) {
1702 assert(src->has_byte_register(), "must have byte register");
1703 InstructionMark im(this);
1704 prefix(dst, src, true);
1705 emit_int8((unsigned char)0x88);
1706 emit_operand(src, dst);
1707 }
1708
1709 void Assembler::movdl(XMMRegister dst, Register src) {
1710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1711 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1712 emit_int8(0x6E);
1713 emit_int8((unsigned char)(0xC0 | encode));
1714 }
1715
1716 void Assembler::movdl(Register dst, XMMRegister src) {
1717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1718 // swap src/dst to get correct prefix
1719 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1720 emit_int8(0x7E);
1721 emit_int8((unsigned char)(0xC0 | encode));
1722 }
1723
1724 void Assembler::movdl(XMMRegister dst, Address src) {
1725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1726 InstructionMark im(this);
1727 simd_prefix(dst, src, VEX_SIMD_66);
1728 emit_int8(0x6E);
1729 emit_operand(dst, src);
1730 }
1731
1732 void Assembler::movdl(Address dst, XMMRegister src) {
1733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1734 InstructionMark im(this);
1735 simd_prefix(dst, src, VEX_SIMD_66);
1736 emit_int8(0x7E);
1737 emit_operand(src, dst);
1738 }
1739
1740 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1742 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1743 }
1744
1745 void Assembler::movdqa(XMMRegister dst, Address src) {
1746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1747 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1748 }
1749
1750 void Assembler::movdqu(XMMRegister dst, Address src) {
1751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1752 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1753 }
1754
1755 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1756 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1757 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1758 }
1759
1760 void Assembler::movdqu(Address dst, XMMRegister src) {
1761 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1762 InstructionMark im(this);
1763 simd_prefix(dst, src, VEX_SIMD_F3);
1764 emit_int8(0x7F);
1765 emit_operand(src, dst);
1766 }
1767
1768 // Move Unaligned 256bit Vector
1769 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1770 assert(UseAVX, "");
1771 bool vector256 = true;
1772 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1773 emit_int8(0x6F);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1778 assert(UseAVX, "");
1779 InstructionMark im(this);
1780 bool vector256 = true;
1781 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1782 emit_int8(0x6F);
1783 emit_operand(dst, src);
1784 }
1785
1786 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1787 assert(UseAVX, "");
1788 InstructionMark im(this);
1789 bool vector256 = true;
1790 // swap src<->dst for encoding
1791 assert(src != xnoreg, "sanity");
1792 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1793 emit_int8(0x7F);
1794 emit_operand(src, dst);
1795 }
1796
1797 // Uses zero extension on 64bit
1798
1799 void Assembler::movl(Register dst, int32_t imm32) {
1800 int encode = prefix_and_encode(dst->encoding());
1801 emit_int8((unsigned char)(0xB8 | encode));
1802 emit_int32(imm32);
1803 }
1804
1805 void Assembler::movl(Register dst, Register src) {
1806 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1807 emit_int8((unsigned char)0x8B);
1808 emit_int8((unsigned char)(0xC0 | encode));
1809 }
1810
1811 void Assembler::movl(Register dst, Address src) {
1812 InstructionMark im(this);
1813 prefix(src, dst);
1814 emit_int8((unsigned char)0x8B);
1815 emit_operand(dst, src);
1816 }
1817
1818 void Assembler::movl(Address dst, int32_t imm32) {
1819 InstructionMark im(this);
1820 prefix(dst);
1821 emit_int8((unsigned char)0xC7);
1822 emit_operand(rax, dst, 4);
1823 emit_int32(imm32);
1824 }
1825
1826 void Assembler::movl(Address dst, Register src) {
1827 InstructionMark im(this);
1828 prefix(dst, src);
1829 emit_int8((unsigned char)0x89);
1830 emit_operand(src, dst);
1831 }
1832
1833 // New cpus require to use movsd and movss to avoid partial register stall
1834 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1835 // The selection is done in MacroAssembler::movdbl() and movflt().
1836 void Assembler::movlpd(XMMRegister dst, Address src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1839 }
1840
1841 void Assembler::movq( MMXRegister dst, Address src ) {
1842 assert( VM_Version::supports_mmx(), "" );
1843 emit_int8(0x0F);
1844 emit_int8(0x6F);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::movq( Address dst, MMXRegister src ) {
1849 assert( VM_Version::supports_mmx(), "" );
1850 emit_int8(0x0F);
1851 emit_int8(0x7F);
1852 // workaround gcc (3.2.1-7a) bug
1853 // In that version of gcc with only an emit_operand(MMX, Address)
1854 // gcc will tail jump and try and reverse the parameters completely
1855 // obliterating dst in the process. By having a version available
1856 // that doesn't need to swap the args at the tail jump the bug is
1857 // avoided.
1858 emit_operand(dst, src);
1859 }
1860
1861 void Assembler::movq(XMMRegister dst, Address src) {
1862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1863 InstructionMark im(this);
1864 simd_prefix(dst, src, VEX_SIMD_F3);
1865 emit_int8(0x7E);
1866 emit_operand(dst, src);
1867 }
1868
1869 void Assembler::movq(Address dst, XMMRegister src) {
1870 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1871 InstructionMark im(this);
1872 simd_prefix(dst, src, VEX_SIMD_66);
1873 emit_int8((unsigned char)0xD6);
1874 emit_operand(src, dst);
1875 }
1876
1877 void Assembler::movsbl(Register dst, Address src) { // movsxb
1878 InstructionMark im(this);
1879 prefix(src, dst);
1880 emit_int8(0x0F);
1881 emit_int8((unsigned char)0xBE);
1882 emit_operand(dst, src);
1883 }
1884
1885 void Assembler::movsbl(Register dst, Register src) { // movsxb
1886 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1887 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1888 emit_int8(0x0F);
1889 emit_int8((unsigned char)0xBE);
1890 emit_int8((unsigned char)(0xC0 | encode));
1891 }
1892
1893 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1894 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1895 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1896 }
1897
1898 void Assembler::movsd(XMMRegister dst, Address src) {
1899 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1900 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1901 }
1902
1903 void Assembler::movsd(Address dst, XMMRegister src) {
1904 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1905 InstructionMark im(this);
1906 simd_prefix(dst, src, VEX_SIMD_F2);
1907 emit_int8(0x11);
1908 emit_operand(src, dst);
1909 }
1910
1911 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1912 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1913 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1914 }
1915
1916 void Assembler::movss(XMMRegister dst, Address src) {
1917 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1918 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1919 }
1920
1921 void Assembler::movss(Address dst, XMMRegister src) {
1922 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1923 InstructionMark im(this);
1924 simd_prefix(dst, src, VEX_SIMD_F3);
1925 emit_int8(0x11);
1926 emit_operand(src, dst);
1927 }
1928
1929 void Assembler::movswl(Register dst, Address src) { // movsxw
1930 InstructionMark im(this);
1931 prefix(src, dst);
1932 emit_int8(0x0F);
1933 emit_int8((unsigned char)0xBF);
1934 emit_operand(dst, src);
1935 }
1936
1937 void Assembler::movswl(Register dst, Register src) { // movsxw
1938 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1939 emit_int8(0x0F);
1940 emit_int8((unsigned char)0xBF);
1941 emit_int8((unsigned char)(0xC0 | encode));
1942 }
1943
1944 void Assembler::movw(Address dst, int imm16) {
1945 InstructionMark im(this);
1946
1947 emit_int8(0x66); // switch to 16-bit mode
1948 prefix(dst);
1949 emit_int8((unsigned char)0xC7);
1950 emit_operand(rax, dst, 2);
1951 emit_int16(imm16);
1952 }
1953
1954 void Assembler::movw(Register dst, Address src) {
1955 InstructionMark im(this);
1956 emit_int8(0x66);
1957 prefix(src, dst);
1958 emit_int8((unsigned char)0x8B);
1959 emit_operand(dst, src);
1960 }
1961
1962 void Assembler::movw(Address dst, Register src) {
1963 InstructionMark im(this);
1964 emit_int8(0x66);
1965 prefix(dst, src);
1966 emit_int8((unsigned char)0x89);
1967 emit_operand(src, dst);
1968 }
1969
1970 void Assembler::movzbl(Register dst, Address src) { // movzxb
1971 InstructionMark im(this);
1972 prefix(src, dst);
1973 emit_int8(0x0F);
1974 emit_int8((unsigned char)0xB6);
1975 emit_operand(dst, src);
1976 }
1977
1978 void Assembler::movzbl(Register dst, Register src) { // movzxb
1979 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1980 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1981 emit_int8(0x0F);
1982 emit_int8((unsigned char)0xB6);
1983 emit_int8(0xC0 | encode);
1984 }
1985
1986 void Assembler::movzwl(Register dst, Address src) { // movzxw
1987 InstructionMark im(this);
1988 prefix(src, dst);
1989 emit_int8(0x0F);
1990 emit_int8((unsigned char)0xB7);
1991 emit_operand(dst, src);
1992 }
1993
1994 void Assembler::movzwl(Register dst, Register src) { // movzxw
1995 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1996 emit_int8(0x0F);
1997 emit_int8((unsigned char)0xB7);
1998 emit_int8(0xC0 | encode);
1999 }
2000
2001 void Assembler::mull(Address src) {
2002 InstructionMark im(this);
2003 prefix(src);
2004 emit_int8((unsigned char)0xF7);
2005 emit_operand(rsp, src);
2006 }
2007
2008 void Assembler::mull(Register src) {
2009 int encode = prefix_and_encode(src->encoding());
2010 emit_int8((unsigned char)0xF7);
2011 emit_int8((unsigned char)(0xE0 | encode));
2012 }
2013
2014 void Assembler::mulsd(XMMRegister dst, Address src) {
2015 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2016 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2017 }
2018
2019 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2020 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2021 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2022 }
2023
2024 void Assembler::mulss(XMMRegister dst, Address src) {
2025 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2026 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2027 }
2028
2029 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2030 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2031 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2032 }
2033
2034 void Assembler::negl(Register dst) {
2035 int encode = prefix_and_encode(dst->encoding());
2036 emit_int8((unsigned char)0xF7);
2037 emit_int8((unsigned char)(0xD8 | encode));
2038 }
2039
2040 void Assembler::nop(int i) {
2041 #ifdef ASSERT
2042 assert(i > 0, " ");
2043 // The fancy nops aren't currently recognized by debuggers making it a
2044 // pain to disassemble code while debugging. If asserts are on clearly
2045 // speed is not an issue so simply use the single byte traditional nop
2046 // to do alignment.
2047
2048 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2049 return;
2050
2051 #endif // ASSERT
2052
2053 if (UseAddressNop && VM_Version::is_intel()) {
2054 //
2055 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2056 // 1: 0x90
2057 // 2: 0x66 0x90
2058 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2059 // 4: 0x0F 0x1F 0x40 0x00
2060 // 5: 0x0F 0x1F 0x44 0x00 0x00
2061 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2062 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2063 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2064 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2065 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2066 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2067
2068 // The rest coding is Intel specific - don't use consecutive address nops
2069
2070 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2071 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2072 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2073 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2074
2075 while(i >= 15) {
2076 // For Intel don't generate consecutive addess nops (mix with regular nops)
2077 i -= 15;
2078 emit_int8(0x66); // size prefix
2079 emit_int8(0x66); // size prefix
2080 emit_int8(0x66); // size prefix
2081 addr_nop_8();
2082 emit_int8(0x66); // size prefix
2083 emit_int8(0x66); // size prefix
2084 emit_int8(0x66); // size prefix
2085 emit_int8((unsigned char)0x90);
2086 // nop
2087 }
2088 switch (i) {
2089 case 14:
2090 emit_int8(0x66); // size prefix
2091 case 13:
2092 emit_int8(0x66); // size prefix
2093 case 12:
2094 addr_nop_8();
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 emit_int8(0x66); // size prefix
2098 emit_int8((unsigned char)0x90);
2099 // nop
2100 break;
2101 case 11:
2102 emit_int8(0x66); // size prefix
2103 case 10:
2104 emit_int8(0x66); // size prefix
2105 case 9:
2106 emit_int8(0x66); // size prefix
2107 case 8:
2108 addr_nop_8();
2109 break;
2110 case 7:
2111 addr_nop_7();
2112 break;
2113 case 6:
2114 emit_int8(0x66); // size prefix
2115 case 5:
2116 addr_nop_5();
2117 break;
2118 case 4:
2119 addr_nop_4();
2120 break;
2121 case 3:
2122 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2123 emit_int8(0x66); // size prefix
2124 case 2:
2125 emit_int8(0x66); // size prefix
2126 case 1:
2127 emit_int8((unsigned char)0x90);
2128 // nop
2129 break;
2130 default:
2131 assert(i == 0, " ");
2132 }
2133 return;
2134 }
2135 if (UseAddressNop && VM_Version::is_amd()) {
2136 //
2137 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2138 // 1: 0x90
2139 // 2: 0x66 0x90
2140 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2141 // 4: 0x0F 0x1F 0x40 0x00
2142 // 5: 0x0F 0x1F 0x44 0x00 0x00
2143 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2144 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2145 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2146 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2147 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2148 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2149
2150 // The rest coding is AMD specific - use consecutive address nops
2151
2152 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2153 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2154 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2155 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2156 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2157 // Size prefixes (0x66) are added for larger sizes
2158
2159 while(i >= 22) {
2160 i -= 11;
2161 emit_int8(0x66); // size prefix
2162 emit_int8(0x66); // size prefix
2163 emit_int8(0x66); // size prefix
2164 addr_nop_8();
2165 }
2166 // Generate first nop for size between 21-12
2167 switch (i) {
2168 case 21:
2169 i -= 1;
2170 emit_int8(0x66); // size prefix
2171 case 20:
2172 case 19:
2173 i -= 1;
2174 emit_int8(0x66); // size prefix
2175 case 18:
2176 case 17:
2177 i -= 1;
2178 emit_int8(0x66); // size prefix
2179 case 16:
2180 case 15:
2181 i -= 8;
2182 addr_nop_8();
2183 break;
2184 case 14:
2185 case 13:
2186 i -= 7;
2187 addr_nop_7();
2188 break;
2189 case 12:
2190 i -= 6;
2191 emit_int8(0x66); // size prefix
2192 addr_nop_5();
2193 break;
2194 default:
2195 assert(i < 12, " ");
2196 }
2197
2198 // Generate second nop for size between 11-1
2199 switch (i) {
2200 case 11:
2201 emit_int8(0x66); // size prefix
2202 case 10:
2203 emit_int8(0x66); // size prefix
2204 case 9:
2205 emit_int8(0x66); // size prefix
2206 case 8:
2207 addr_nop_8();
2208 break;
2209 case 7:
2210 addr_nop_7();
2211 break;
2212 case 6:
2213 emit_int8(0x66); // size prefix
2214 case 5:
2215 addr_nop_5();
2216 break;
2217 case 4:
2218 addr_nop_4();
2219 break;
2220 case 3:
2221 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2222 emit_int8(0x66); // size prefix
2223 case 2:
2224 emit_int8(0x66); // size prefix
2225 case 1:
2226 emit_int8((unsigned char)0x90);
2227 // nop
2228 break;
2229 default:
2230 assert(i == 0, " ");
2231 }
2232 return;
2233 }
2234
2235 // Using nops with size prefixes "0x66 0x90".
2236 // From AMD Optimization Guide:
2237 // 1: 0x90
2238 // 2: 0x66 0x90
2239 // 3: 0x66 0x66 0x90
2240 // 4: 0x66 0x66 0x66 0x90
2241 // 5: 0x66 0x66 0x90 0x66 0x90
2242 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2243 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2244 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2245 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2246 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2247 //
2248 while(i > 12) {
2249 i -= 4;
2250 emit_int8(0x66); // size prefix
2251 emit_int8(0x66);
2252 emit_int8(0x66);
2253 emit_int8((unsigned char)0x90);
2254 // nop
2255 }
2256 // 1 - 12 nops
2257 if(i > 8) {
2258 if(i > 9) {
2259 i -= 1;
2260 emit_int8(0x66);
2261 }
2262 i -= 3;
2263 emit_int8(0x66);
2264 emit_int8(0x66);
2265 emit_int8((unsigned char)0x90);
2266 }
2267 // 1 - 8 nops
2268 if(i > 4) {
2269 if(i > 6) {
2270 i -= 1;
2271 emit_int8(0x66);
2272 }
2273 i -= 3;
2274 emit_int8(0x66);
2275 emit_int8(0x66);
2276 emit_int8((unsigned char)0x90);
2277 }
2278 switch (i) {
2279 case 4:
2280 emit_int8(0x66);
2281 case 3:
2282 emit_int8(0x66);
2283 case 2:
2284 emit_int8(0x66);
2285 case 1:
2286 emit_int8((unsigned char)0x90);
2287 break;
2288 default:
2289 assert(i == 0, " ");
2290 }
2291 }
2292
2293 void Assembler::notl(Register dst) {
2294 int encode = prefix_and_encode(dst->encoding());
2295 emit_int8((unsigned char)0xF7);
2296 emit_int8((unsigned char)(0xD0 | encode));
2297 }
2298
2299 void Assembler::orl(Address dst, int32_t imm32) {
2300 InstructionMark im(this);
2301 prefix(dst);
2302 emit_arith_operand(0x81, rcx, dst, imm32);
2303 }
2304
2305 void Assembler::orl(Register dst, int32_t imm32) {
2306 prefix(dst);
2307 emit_arith(0x81, 0xC8, dst, imm32);
2308 }
2309
2310 void Assembler::orl(Register dst, Address src) {
2311 InstructionMark im(this);
2312 prefix(src, dst);
2313 emit_int8(0x0B);
2314 emit_operand(dst, src);
2315 }
2316
2317 void Assembler::orl(Register dst, Register src) {
2318 (void) prefix_and_encode(dst->encoding(), src->encoding());
2319 emit_arith(0x0B, 0xC0, dst, src);
2320 }
2321
2322 void Assembler::packuswb(XMMRegister dst, Address src) {
2323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2324 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2325 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2326 }
2327
2328 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2330 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2331 }
2332
2333 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2334 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2335 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2336 }
2337
2338 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2339 assert(VM_Version::supports_avx2(), "");
2340 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2341 emit_int8(0x00);
2342 emit_int8(0xC0 | encode);
2343 emit_int8(imm8);
2344 }
2345
2346 void Assembler::pause() {
2347 emit_int8((unsigned char)0xF3);
2348 emit_int8((unsigned char)0x90);
2349 }
2350
2351 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2352 assert(VM_Version::supports_sse4_2(), "");
2353 InstructionMark im(this);
2354 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2355 emit_int8(0x61);
2356 emit_operand(dst, src);
2357 emit_int8(imm8);
2358 }
2359
2360 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2361 assert(VM_Version::supports_sse4_2(), "");
2362 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2363 emit_int8(0x61);
2364 emit_int8((unsigned char)(0xC0 | encode));
2365 emit_int8(imm8);
2366 }
2367
2368 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2369 assert(VM_Version::supports_sse4_1(), "");
2370 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2371 emit_int8(0x16);
2372 emit_int8((unsigned char)(0xC0 | encode));
2373 emit_int8(imm8);
2374 }
2375
2376 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2377 assert(VM_Version::supports_sse4_1(), "");
2378 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2379 emit_int8(0x16);
2380 emit_int8((unsigned char)(0xC0 | encode));
2381 emit_int8(imm8);
2382 }
2383
2384 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2385 assert(VM_Version::supports_sse4_1(), "");
2386 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2387 emit_int8(0x22);
2388 emit_int8((unsigned char)(0xC0 | encode));
2389 emit_int8(imm8);
2390 }
2391
2392 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2393 assert(VM_Version::supports_sse4_1(), "");
2394 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2395 emit_int8(0x22);
2396 emit_int8((unsigned char)(0xC0 | encode));
2397 emit_int8(imm8);
2398 }
2399
2400 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2401 assert(VM_Version::supports_sse4_1(), "");
2402 InstructionMark im(this);
2403 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2404 emit_int8(0x30);
2405 emit_operand(dst, src);
2406 }
2407
2408 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2409 assert(VM_Version::supports_sse4_1(), "");
2410 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2411 emit_int8(0x30);
2412 emit_int8((unsigned char)(0xC0 | encode));
2413 }
2414
2415 // generic
2416 void Assembler::pop(Register dst) {
2417 int encode = prefix_and_encode(dst->encoding());
2418 emit_int8(0x58 | encode);
2419 }
2420
2421 void Assembler::popcntl(Register dst, Address src) {
2422 assert(VM_Version::supports_popcnt(), "must support");
2423 InstructionMark im(this);
2424 emit_int8((unsigned char)0xF3);
2425 prefix(src, dst);
2426 emit_int8(0x0F);
2427 emit_int8((unsigned char)0xB8);
2428 emit_operand(dst, src);
2429 }
2430
2431 void Assembler::popcntl(Register dst, Register src) {
2432 assert(VM_Version::supports_popcnt(), "must support");
2433 emit_int8((unsigned char)0xF3);
2434 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2435 emit_int8(0x0F);
2436 emit_int8((unsigned char)0xB8);
2437 emit_int8((unsigned char)(0xC0 | encode));
2438 }
2439
2440 void Assembler::popf() {
2441 emit_int8((unsigned char)0x9D);
2442 }
2443
2444 #ifndef _LP64 // no 32bit push/pop on amd64
2445 void Assembler::popl(Address dst) {
2446 // NOTE: this will adjust stack by 8byte on 64bits
2447 InstructionMark im(this);
2448 prefix(dst);
2449 emit_int8((unsigned char)0x8F);
2450 emit_operand(rax, dst);
2451 }
2452 #endif
2453
2454 void Assembler::prefetch_prefix(Address src) {
2455 prefix(src);
2456 emit_int8(0x0F);
2457 }
2458
2459 void Assembler::prefetchnta(Address src) {
2460 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2461 InstructionMark im(this);
2462 prefetch_prefix(src);
2463 emit_int8(0x18);
2464 emit_operand(rax, src); // 0, src
2465 }
2466
2467 void Assembler::prefetchr(Address src) {
2468 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2469 InstructionMark im(this);
2470 prefetch_prefix(src);
2471 emit_int8(0x0D);
2472 emit_operand(rax, src); // 0, src
2473 }
2474
2475 void Assembler::prefetcht0(Address src) {
2476 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2477 InstructionMark im(this);
2478 prefetch_prefix(src);
2479 emit_int8(0x18);
2480 emit_operand(rcx, src); // 1, src
2481 }
2482
2483 void Assembler::prefetcht1(Address src) {
2484 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2485 InstructionMark im(this);
2486 prefetch_prefix(src);
2487 emit_int8(0x18);
2488 emit_operand(rdx, src); // 2, src
2489 }
2490
2491 void Assembler::prefetcht2(Address src) {
2492 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2493 InstructionMark im(this);
2494 prefetch_prefix(src);
2495 emit_int8(0x18);
2496 emit_operand(rbx, src); // 3, src
2497 }
2498
2499 void Assembler::prefetchw(Address src) {
2500 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2501 InstructionMark im(this);
2502 prefetch_prefix(src);
2503 emit_int8(0x0D);
2504 emit_operand(rcx, src); // 1, src
2505 }
2506
2507 void Assembler::prefix(Prefix p) {
2508 emit_int8(p);
2509 }
2510
2511 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2512 assert(VM_Version::supports_ssse3(), "");
2513 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2514 emit_int8(0x00);
2515 emit_int8((unsigned char)(0xC0 | encode));
2516 }
2517
2518 void Assembler::pshufb(XMMRegister dst, Address src) {
2519 assert(VM_Version::supports_ssse3(), "");
2520 InstructionMark im(this);
2521 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2522 emit_int8(0x00);
2523 emit_operand(dst, src);
2524 }
2525
2526 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2527 assert(isByte(mode), "invalid value");
2528 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2529 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2530 emit_int8(mode & 0xFF);
2531
2532 }
2533
2534 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2535 assert(isByte(mode), "invalid value");
2536 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2537 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2538 InstructionMark im(this);
2539 simd_prefix(dst, src, VEX_SIMD_66);
2540 emit_int8(0x70);
2541 emit_operand(dst, src);
2542 emit_int8(mode & 0xFF);
2543 }
2544
2545 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2546 assert(isByte(mode), "invalid value");
2547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2548 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2549 emit_int8(mode & 0xFF);
2550 }
2551
2552 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2553 assert(isByte(mode), "invalid value");
2554 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2555 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2556 InstructionMark im(this);
2557 simd_prefix(dst, src, VEX_SIMD_F2);
2558 emit_int8(0x70);
2559 emit_operand(dst, src);
2560 emit_int8(mode & 0xFF);
2561 }
2562
2563 void Assembler::psrldq(XMMRegister dst, int shift) {
2564 // Shift 128 bit value in xmm register by number of bytes.
2565 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2566 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2567 emit_int8(0x73);
2568 emit_int8((unsigned char)(0xC0 | encode));
2569 emit_int8(shift);
2570 }
2571
2572 void Assembler::ptest(XMMRegister dst, Address src) {
2573 assert(VM_Version::supports_sse4_1(), "");
2574 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2575 InstructionMark im(this);
2576 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2577 emit_int8(0x17);
2578 emit_operand(dst, src);
2579 }
2580
2581 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2582 assert(VM_Version::supports_sse4_1(), "");
2583 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2584 emit_int8(0x17);
2585 emit_int8((unsigned char)(0xC0 | encode));
2586 }
2587
2588 void Assembler::vptest(XMMRegister dst, Address src) {
2589 assert(VM_Version::supports_avx(), "");
2590 InstructionMark im(this);
2591 bool vector256 = true;
2592 assert(dst != xnoreg, "sanity");
2593 int dst_enc = dst->encoding();
2594 // swap src<->dst for encoding
2595 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2596 emit_int8(0x17);
2597 emit_operand(dst, src);
2598 }
2599
2600 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2601 assert(VM_Version::supports_avx(), "");
2602 bool vector256 = true;
2603 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2604 emit_int8(0x17);
2605 emit_int8((unsigned char)(0xC0 | encode));
2606 }
2607
2608 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2610 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2611 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2612 }
2613
2614 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2616 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2617 }
2618
2619 void Assembler::punpckldq(XMMRegister dst, Address src) {
2620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2621 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2622 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2623 }
2624
2625 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2627 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2628 }
2629
2630 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2632 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2633 }
2634
2635 void Assembler::push(int32_t imm32) {
2636 // in 64bits we push 64bits onto the stack but only
2637 // take a 32bit immediate
2638 emit_int8(0x68);
2639 emit_int32(imm32);
2640 }
2641
2642 void Assembler::push(Register src) {
2643 int encode = prefix_and_encode(src->encoding());
2644
2645 emit_int8(0x50 | encode);
2646 }
2647
2648 void Assembler::pushf() {
2649 emit_int8((unsigned char)0x9C);
2650 }
2651
2652 #ifndef _LP64 // no 32bit push/pop on amd64
2653 void Assembler::pushl(Address src) {
2654 // Note this will push 64bit on 64bit
2655 InstructionMark im(this);
2656 prefix(src);
2657 emit_int8((unsigned char)0xFF);
2658 emit_operand(rsi, src);
2659 }
2660 #endif
2661
2662 void Assembler::rcll(Register dst, int imm8) {
2663 assert(isShiftCount(imm8), "illegal shift count");
2664 int encode = prefix_and_encode(dst->encoding());
2665 if (imm8 == 1) {
2666 emit_int8((unsigned char)0xD1);
2667 emit_int8((unsigned char)(0xD0 | encode));
2668 } else {
2669 emit_int8((unsigned char)0xC1);
2670 emit_int8((unsigned char)0xD0 | encode);
2671 emit_int8(imm8);
2672 }
2673 }
2674
2675 void Assembler::rdtsc() {
2676 emit_int8((unsigned char)0x0F);
2677 emit_int8((unsigned char)0x31);
2678 }
2679
2680 // copies data from [esi] to [edi] using rcx pointer sized words
2681 // generic
2682 void Assembler::rep_mov() {
2683 emit_int8((unsigned char)0xF3);
2684 // MOVSQ
2685 LP64_ONLY(prefix(REX_W));
2686 emit_int8((unsigned char)0xA5);
2687 }
2688
2689 // sets rcx bytes with rax, value at [edi]
2690 void Assembler::rep_stosb() {
2691 emit_int8((unsigned char)0xF3); // REP
2692 LP64_ONLY(prefix(REX_W));
2693 emit_int8((unsigned char)0xAA); // STOSB
2694 }
2695
2696 // sets rcx pointer sized words with rax, value at [edi]
2697 // generic
2698 void Assembler::rep_stos() {
2699 emit_int8((unsigned char)0xF3); // REP
2700 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2701 emit_int8((unsigned char)0xAB);
2702 }
2703
2704 // scans rcx pointer sized words at [edi] for occurance of rax,
2705 // generic
2706 void Assembler::repne_scan() { // repne_scan
2707 emit_int8((unsigned char)0xF2);
2708 // SCASQ
2709 LP64_ONLY(prefix(REX_W));
2710 emit_int8((unsigned char)0xAF);
2711 }
2712
2713 #ifdef _LP64
2714 // scans rcx 4 byte words at [edi] for occurance of rax,
2715 // generic
2716 void Assembler::repne_scanl() { // repne_scan
2717 emit_int8((unsigned char)0xF2);
2718 // SCASL
2719 emit_int8((unsigned char)0xAF);
2720 }
2721 #endif
2722
2723 void Assembler::ret(int imm16) {
2724 if (imm16 == 0) {
2725 emit_int8((unsigned char)0xC3);
2726 } else {
2727 emit_int8((unsigned char)0xC2);
2728 emit_int16(imm16);
2729 }
2730 }
2731
2732 void Assembler::sahf() {
2733 #ifdef _LP64
2734 // Not supported in 64bit mode
2735 ShouldNotReachHere();
2736 #endif
2737 emit_int8((unsigned char)0x9E);
2738 }
2739
2740 void Assembler::sarl(Register dst, int imm8) {
2741 int encode = prefix_and_encode(dst->encoding());
2742 assert(isShiftCount(imm8), "illegal shift count");
2743 if (imm8 == 1) {
2744 emit_int8((unsigned char)0xD1);
2745 emit_int8((unsigned char)(0xF8 | encode));
2746 } else {
2747 emit_int8((unsigned char)0xC1);
2748 emit_int8((unsigned char)(0xF8 | encode));
2749 emit_int8(imm8);
2750 }
2751 }
2752
2753 void Assembler::sarl(Register dst) {
2754 int encode = prefix_and_encode(dst->encoding());
2755 emit_int8((unsigned char)0xD3);
2756 emit_int8((unsigned char)(0xF8 | encode));
2757 }
2758
2759 void Assembler::sbbl(Address dst, int32_t imm32) {
2760 InstructionMark im(this);
2761 prefix(dst);
2762 emit_arith_operand(0x81, rbx, dst, imm32);
2763 }
2764
2765 void Assembler::sbbl(Register dst, int32_t imm32) {
2766 prefix(dst);
2767 emit_arith(0x81, 0xD8, dst, imm32);
2768 }
2769
2770
2771 void Assembler::sbbl(Register dst, Address src) {
2772 InstructionMark im(this);
2773 prefix(src, dst);
2774 emit_int8(0x1B);
2775 emit_operand(dst, src);
2776 }
2777
2778 void Assembler::sbbl(Register dst, Register src) {
2779 (void) prefix_and_encode(dst->encoding(), src->encoding());
2780 emit_arith(0x1B, 0xC0, dst, src);
2781 }
2782
2783 void Assembler::setb(Condition cc, Register dst) {
2784 assert(0 <= cc && cc < 16, "illegal cc");
2785 int encode = prefix_and_encode(dst->encoding(), true);
2786 emit_int8(0x0F);
2787 emit_int8((unsigned char)0x90 | cc);
2788 emit_int8((unsigned char)(0xC0 | encode));
2789 }
2790
2791 void Assembler::shll(Register dst, int imm8) {
2792 assert(isShiftCount(imm8), "illegal shift count");
2793 int encode = prefix_and_encode(dst->encoding());
2794 if (imm8 == 1 ) {
2795 emit_int8((unsigned char)0xD1);
2796 emit_int8((unsigned char)(0xE0 | encode));
2797 } else {
2798 emit_int8((unsigned char)0xC1);
2799 emit_int8((unsigned char)(0xE0 | encode));
2800 emit_int8(imm8);
2801 }
2802 }
2803
2804 void Assembler::shll(Register dst) {
2805 int encode = prefix_and_encode(dst->encoding());
2806 emit_int8((unsigned char)0xD3);
2807 emit_int8((unsigned char)(0xE0 | encode));
2808 }
2809
2810 void Assembler::shrl(Register dst, int imm8) {
2811 assert(isShiftCount(imm8), "illegal shift count");
2812 int encode = prefix_and_encode(dst->encoding());
2813 emit_int8((unsigned char)0xC1);
2814 emit_int8((unsigned char)(0xE8 | encode));
2815 emit_int8(imm8);
2816 }
2817
2818 void Assembler::shrl(Register dst) {
2819 int encode = prefix_and_encode(dst->encoding());
2820 emit_int8((unsigned char)0xD3);
2821 emit_int8((unsigned char)(0xE8 | encode));
2822 }
2823
2824 // copies a single word from [esi] to [edi]
2825 void Assembler::smovl() {
2826 emit_int8((unsigned char)0xA5);
2827 }
2828
2829 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2830 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2831 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2832 }
2833
2834 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2835 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2836 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2837 }
2838
2839 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2840 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2841 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2842 }
2843
2844 void Assembler::std() {
2845 emit_int8((unsigned char)0xFD);
2846 }
2847
2848 void Assembler::sqrtss(XMMRegister dst, Address src) {
2849 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2850 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2851 }
2852
2853 void Assembler::stmxcsr( Address dst) {
2854 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2855 InstructionMark im(this);
2856 prefix(dst);
2857 emit_int8(0x0F);
2858 emit_int8((unsigned char)0xAE);
2859 emit_operand(as_Register(3), dst);
2860 }
2861
2862 void Assembler::subl(Address dst, int32_t imm32) {
2863 InstructionMark im(this);
2864 prefix(dst);
2865 emit_arith_operand(0x81, rbp, dst, imm32);
2866 }
2867
2868 void Assembler::subl(Address dst, Register src) {
2869 InstructionMark im(this);
2870 prefix(dst, src);
2871 emit_int8(0x29);
2872 emit_operand(src, dst);
2873 }
2874
2875 void Assembler::subl(Register dst, int32_t imm32) {
2876 prefix(dst);
2877 emit_arith(0x81, 0xE8, dst, imm32);
2878 }
2879
2880 // Force generation of a 4 byte immediate value even if it fits into 8bit
2881 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2882 prefix(dst);
2883 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2884 }
2885
2886 void Assembler::subl(Register dst, Address src) {
2887 InstructionMark im(this);
2888 prefix(src, dst);
2889 emit_int8(0x2B);
2890 emit_operand(dst, src);
2891 }
2892
2893 void Assembler::subl(Register dst, Register src) {
2894 (void) prefix_and_encode(dst->encoding(), src->encoding());
2895 emit_arith(0x2B, 0xC0, dst, src);
2896 }
2897
2898 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2899 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2900 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2901 }
2902
2903 void Assembler::subsd(XMMRegister dst, Address src) {
2904 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2905 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2906 }
2907
2908 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2909 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2910 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2911 }
2912
2913 void Assembler::subss(XMMRegister dst, Address src) {
2914 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2915 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2916 }
2917
2918 void Assembler::testb(Register dst, int imm8) {
2919 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2920 (void) prefix_and_encode(dst->encoding(), true);
2921 emit_arith_b(0xF6, 0xC0, dst, imm8);
2922 }
2923
2924 void Assembler::testl(Register dst, int32_t imm32) {
2925 // not using emit_arith because test
2926 // doesn't support sign-extension of
2927 // 8bit operands
2928 int encode = dst->encoding();
2929 if (encode == 0) {
2930 emit_int8((unsigned char)0xA9);
2931 } else {
2932 encode = prefix_and_encode(encode);
2933 emit_int8((unsigned char)0xF7);
2934 emit_int8((unsigned char)(0xC0 | encode));
2935 }
2936 emit_int32(imm32);
2937 }
2938
2939 void Assembler::testl(Register dst, Register src) {
2940 (void) prefix_and_encode(dst->encoding(), src->encoding());
2941 emit_arith(0x85, 0xC0, dst, src);
2942 }
2943
2944 void Assembler::testl(Register dst, Address src) {
2945 InstructionMark im(this);
2946 prefix(src, dst);
2947 emit_int8((unsigned char)0x85);
2948 emit_operand(dst, src);
2949 }
2950
2951 void Assembler::tzcntl(Register dst, Register src) {
2952 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2953 emit_int8((unsigned char)0xF3);
2954 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2955 emit_int8(0x0F);
2956 emit_int8((unsigned char)0xBC);
2957 emit_int8((unsigned char)0xC0 | encode);
2958 }
2959
2960 void Assembler::tzcntq(Register dst, Register src) {
2961 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2962 emit_int8((unsigned char)0xF3);
2963 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2964 emit_int8(0x0F);
2965 emit_int8((unsigned char)0xBC);
2966 emit_int8((unsigned char)(0xC0 | encode));
2967 }
2968
2969 void Assembler::ucomisd(XMMRegister dst, Address src) {
2970 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2971 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2972 }
2973
2974 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2976 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2977 }
2978
2979 void Assembler::ucomiss(XMMRegister dst, Address src) {
2980 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2981 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2982 }
2983
2984 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2985 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2986 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2987 }
2988
2989 void Assembler::xabort(int8_t imm8) {
2990 emit_int8((unsigned char)0xC6);
2991 emit_int8((unsigned char)0xF8);
2992 emit_int8((unsigned char)(imm8 & 0xFF));
2993 }
2994
2995 void Assembler::xaddl(Address dst, Register src) {
2996 InstructionMark im(this);
2997 prefix(dst, src);
2998 emit_int8(0x0F);
2999 emit_int8((unsigned char)0xC1);
3000 emit_operand(src, dst);
3001 }
3002
3003 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3004 InstructionMark im(this);
3005 relocate(rtype);
3006 if (abort.is_bound()) {
3007 address entry = target(abort);
3008 assert(entry != NULL, "abort entry NULL");
3009 intptr_t offset = entry - pc();
3010 emit_int8((unsigned char)0xC7);
3011 emit_int8((unsigned char)0xF8);
3012 emit_int32(offset - 6); // 2 opcode + 4 address
3013 } else {
3014 abort.add_patch_at(code(), locator());
3015 emit_int8((unsigned char)0xC7);
3016 emit_int8((unsigned char)0xF8);
3017 emit_int32(0);
3018 }
3019 }
3020
3021 void Assembler::xchgl(Register dst, Address src) { // xchg
3022 InstructionMark im(this);
3023 prefix(src, dst);
3024 emit_int8((unsigned char)0x87);
3025 emit_operand(dst, src);
3026 }
3027
3028 void Assembler::xchgl(Register dst, Register src) {
3029 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3030 emit_int8((unsigned char)0x87);
3031 emit_int8((unsigned char)(0xC0 | encode));
3032 }
3033
3034 void Assembler::xend() {
3035 emit_int8((unsigned char)0x0F);
3036 emit_int8((unsigned char)0x01);
3037 emit_int8((unsigned char)0xD5);
3038 }
3039
3040 void Assembler::xgetbv() {
3041 emit_int8(0x0F);
3042 emit_int8(0x01);
3043 emit_int8((unsigned char)0xD0);
3044 }
3045
3046 void Assembler::xorl(Register dst, int32_t imm32) {
3047 prefix(dst);
3048 emit_arith(0x81, 0xF0, dst, imm32);
3049 }
3050
3051 void Assembler::xorl(Register dst, Address src) {
3052 InstructionMark im(this);
3053 prefix(src, dst);
3054 emit_int8(0x33);
3055 emit_operand(dst, src);
3056 }
3057
3058 void Assembler::xorl(Register dst, Register src) {
3059 (void) prefix_and_encode(dst->encoding(), src->encoding());
3060 emit_arith(0x33, 0xC0, dst, src);
3061 }
3062
3063
3064 // AVX 3-operands scalar float-point arithmetic instructions
3065
3066 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3067 assert(VM_Version::supports_avx(), "");
3068 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3069 }
3070
3071 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3072 assert(VM_Version::supports_avx(), "");
3073 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3074 }
3075
3076 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3077 assert(VM_Version::supports_avx(), "");
3078 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3079 }
3080
3081 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3082 assert(VM_Version::supports_avx(), "");
3083 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3084 }
3085
3086 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3087 assert(VM_Version::supports_avx(), "");
3088 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3089 }
3090
3091 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3092 assert(VM_Version::supports_avx(), "");
3093 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3094 }
3095
3096 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3097 assert(VM_Version::supports_avx(), "");
3098 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3099 }
3100
3101 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3102 assert(VM_Version::supports_avx(), "");
3103 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3104 }
3105
3106 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3107 assert(VM_Version::supports_avx(), "");
3108 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3109 }
3110
3111 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3112 assert(VM_Version::supports_avx(), "");
3113 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3114 }
3115
3116 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3117 assert(VM_Version::supports_avx(), "");
3118 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3119 }
3120
3121 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3122 assert(VM_Version::supports_avx(), "");
3123 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3124 }
3125
3126 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3127 assert(VM_Version::supports_avx(), "");
3128 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3129 }
3130
3131 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3132 assert(VM_Version::supports_avx(), "");
3133 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3134 }
3135
3136 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3137 assert(VM_Version::supports_avx(), "");
3138 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3139 }
3140
3141 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3142 assert(VM_Version::supports_avx(), "");
3143 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3144 }
3145
3146 //====================VECTOR ARITHMETIC=====================================
3147
3148 // Float-point vector arithmetic
3149
3150 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3151 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3152 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3153 }
3154
3155 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3156 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3157 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3158 }
3159
3160 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3161 assert(VM_Version::supports_avx(), "");
3162 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3163 }
3164
3165 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3166 assert(VM_Version::supports_avx(), "");
3167 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3168 }
3169
3170 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3171 assert(VM_Version::supports_avx(), "");
3172 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3173 }
3174
3175 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3176 assert(VM_Version::supports_avx(), "");
3177 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3178 }
3179
3180 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3181 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3182 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3183 }
3184
3185 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3186 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3187 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3188 }
3189
3190 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3191 assert(VM_Version::supports_avx(), "");
3192 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3193 }
3194
3195 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3196 assert(VM_Version::supports_avx(), "");
3197 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3198 }
3199
3200 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3201 assert(VM_Version::supports_avx(), "");
3202 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3203 }
3204
3205 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3206 assert(VM_Version::supports_avx(), "");
3207 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3208 }
3209
3210 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3211 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3212 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3213 }
3214
3215 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3216 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3217 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3218 }
3219
3220 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3221 assert(VM_Version::supports_avx(), "");
3222 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3223 }
3224
3225 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3226 assert(VM_Version::supports_avx(), "");
3227 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3228 }
3229
3230 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3231 assert(VM_Version::supports_avx(), "");
3232 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3233 }
3234
3235 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3236 assert(VM_Version::supports_avx(), "");
3237 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3238 }
3239
3240 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3242 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3243 }
3244
3245 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3247 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3248 }
3249
3250 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3251 assert(VM_Version::supports_avx(), "");
3252 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3253 }
3254
3255 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3256 assert(VM_Version::supports_avx(), "");
3257 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3258 }
3259
3260 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3261 assert(VM_Version::supports_avx(), "");
3262 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3263 }
3264
3265 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3266 assert(VM_Version::supports_avx(), "");
3267 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3268 }
3269
3270 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3272 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3273 }
3274
3275 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3276 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3277 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3278 }
3279
3280 void Assembler::andps(XMMRegister dst, Address src) {
3281 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3282 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3283 }
3284
3285 void Assembler::andpd(XMMRegister dst, Address src) {
3286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3287 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3288 }
3289
3290 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3291 assert(VM_Version::supports_avx(), "");
3292 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3293 }
3294
3295 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3296 assert(VM_Version::supports_avx(), "");
3297 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3298 }
3299
3300 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3301 assert(VM_Version::supports_avx(), "");
3302 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3303 }
3304
3305 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3306 assert(VM_Version::supports_avx(), "");
3307 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3308 }
3309
3310 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3311 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3312 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3313 }
3314
3315 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3316 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3317 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3318 }
3319
3320 void Assembler::xorpd(XMMRegister dst, Address src) {
3321 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3322 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3323 }
3324
3325 void Assembler::xorps(XMMRegister dst, Address src) {
3326 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3327 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3328 }
3329
3330 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3331 assert(VM_Version::supports_avx(), "");
3332 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3333 }
3334
3335 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3336 assert(VM_Version::supports_avx(), "");
3337 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3338 }
3339
3340 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3341 assert(VM_Version::supports_avx(), "");
3342 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3343 }
3344
3345 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3346 assert(VM_Version::supports_avx(), "");
3347 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3348 }
3349
3350
3351 // Integer vector arithmetic
3352 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3354 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3355 }
3356
3357 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3358 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3359 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3360 }
3361
3362 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3363 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3364 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3365 }
3366
3367 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3368 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3369 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3370 }
3371
3372 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3373 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3374 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3375 }
3376
3377 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3378 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3379 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3380 }
3381
3382 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3383 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3384 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3385 }
3386
3387 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3388 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3389 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3390 }
3391
3392 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3393 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3394 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3395 }
3396
3397 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3398 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3399 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3400 }
3401
3402 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3403 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3404 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3405 }
3406
3407 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3408 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3409 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3410 }
3411
3412 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3413 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3414 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3415 }
3416
3417 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3418 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3419 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3420 }
3421
3422 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3424 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3425 }
3426
3427 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3428 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3429 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3430 }
3431
3432 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3433 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3434 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3435 }
3436
3437 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3438 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3439 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3440 }
3441
3442 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3443 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3444 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3445 }
3446
3447 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3448 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3449 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3450 }
3451
3452 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3453 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3454 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3455 }
3456
3457 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3458 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3459 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3460 }
3461
3462 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3463 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3464 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3465 }
3466
3467 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3468 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3469 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3470 }
3471
3472 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3473 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3474 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3475 }
3476
3477 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3478 assert(VM_Version::supports_sse4_1(), "");
3479 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3480 emit_int8(0x40);
3481 emit_int8((unsigned char)(0xC0 | encode));
3482 }
3483
3484 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3485 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3486 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3487 }
3488
3489 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3490 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3491 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3492 emit_int8(0x40);
3493 emit_int8((unsigned char)(0xC0 | encode));
3494 }
3495
3496 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3497 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3498 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3499 }
3500
3501 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3502 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3503 InstructionMark im(this);
3504 int dst_enc = dst->encoding();
3505 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3506 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3507 emit_int8(0x40);
3508 emit_operand(dst, src);
3509 }
3510
3511 // Shift packed integers left by specified number of bits.
3512 void Assembler::psllw(XMMRegister dst, int shift) {
3513 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3514 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3515 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3516 emit_int8(0x71);
3517 emit_int8((unsigned char)(0xC0 | encode));
3518 emit_int8(shift & 0xFF);
3519 }
3520
3521 void Assembler::pslld(XMMRegister dst, int shift) {
3522 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3523 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3524 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3525 emit_int8(0x72);
3526 emit_int8((unsigned char)(0xC0 | encode));
3527 emit_int8(shift & 0xFF);
3528 }
3529
3530 void Assembler::psllq(XMMRegister dst, int shift) {
3531 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3532 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3533 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3534 emit_int8(0x73);
3535 emit_int8((unsigned char)(0xC0 | encode));
3536 emit_int8(shift & 0xFF);
3537 }
3538
3539 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3540 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3541 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3542 }
3543
3544 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3545 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3546 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3547 }
3548
3549 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3550 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3551 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3552 }
3553
3554 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3555 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3556 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3557 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3558 emit_int8(shift & 0xFF);
3559 }
3560
3561 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3562 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3563 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3564 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3565 emit_int8(shift & 0xFF);
3566 }
3567
3568 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3569 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3570 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3571 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3572 emit_int8(shift & 0xFF);
3573 }
3574
3575 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3576 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3577 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3578 }
3579
3580 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3581 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3582 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3583 }
3584
3585 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3586 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3587 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3588 }
3589
3590 // Shift packed integers logically right by specified number of bits.
3591 void Assembler::psrlw(XMMRegister dst, int shift) {
3592 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3593 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3594 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3595 emit_int8(0x71);
3596 emit_int8((unsigned char)(0xC0 | encode));
3597 emit_int8(shift & 0xFF);
3598 }
3599
3600 void Assembler::psrld(XMMRegister dst, int shift) {
3601 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3602 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3603 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3604 emit_int8(0x72);
3605 emit_int8((unsigned char)(0xC0 | encode));
3606 emit_int8(shift & 0xFF);
3607 }
3608
3609 void Assembler::psrlq(XMMRegister dst, int shift) {
3610 // Do not confuse it with psrldq SSE2 instruction which
3611 // shifts 128 bit value in xmm register by number of bytes.
3612 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3613 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3614 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3615 emit_int8(0x73);
3616 emit_int8((unsigned char)(0xC0 | encode));
3617 emit_int8(shift & 0xFF);
3618 }
3619
3620 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3622 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3623 }
3624
3625 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3627 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3628 }
3629
3630 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3632 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3633 }
3634
3635 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3636 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3637 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3638 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3639 emit_int8(shift & 0xFF);
3640 }
3641
3642 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3643 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3644 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3645 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3646 emit_int8(shift & 0xFF);
3647 }
3648
3649 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3650 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3651 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3652 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3653 emit_int8(shift & 0xFF);
3654 }
3655
3656 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3657 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3658 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3659 }
3660
3661 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3662 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3663 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3664 }
3665
3666 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3667 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3668 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3669 }
3670
3671 // Shift packed integers arithmetically right by specified number of bits.
3672 void Assembler::psraw(XMMRegister dst, int shift) {
3673 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3674 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3675 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3676 emit_int8(0x71);
3677 emit_int8((unsigned char)(0xC0 | encode));
3678 emit_int8(shift & 0xFF);
3679 }
3680
3681 void Assembler::psrad(XMMRegister dst, int shift) {
3682 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3683 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3684 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3685 emit_int8(0x72);
3686 emit_int8((unsigned char)(0xC0 | encode));
3687 emit_int8(shift & 0xFF);
3688 }
3689
3690 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3691 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3692 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3693 }
3694
3695 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3696 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3697 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3698 }
3699
3700 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3701 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3702 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3703 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3704 emit_int8(shift & 0xFF);
3705 }
3706
3707 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3708 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3709 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3710 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3711 emit_int8(shift & 0xFF);
3712 }
3713
3714 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3715 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3716 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3717 }
3718
3719 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3720 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3721 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3722 }
3723
3724
3725 // AND packed integers
3726 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3727 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3728 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3729 }
3730
3731 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3732 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3733 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3734 }
3735
3736 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3737 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3738 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3739 }
3740
3741 void Assembler::por(XMMRegister dst, XMMRegister src) {
3742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3743 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3744 }
3745
3746 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3747 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3748 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3749 }
3750
3751 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3752 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3753 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3754 }
3755
3756 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3758 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3759 }
3760
3761 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3762 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3763 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3764 }
3765
3766 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3767 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3768 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3769 }
3770
3771
3772 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3773 assert(VM_Version::supports_avx(), "");
3774 bool vector256 = true;
3775 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3776 emit_int8(0x18);
3777 emit_int8((unsigned char)(0xC0 | encode));
3778 // 0x00 - insert into lower 128 bits
3779 // 0x01 - insert into upper 128 bits
3780 emit_int8(0x01);
3781 }
3782
3783 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3784 assert(VM_Version::supports_avx(), "");
3785 InstructionMark im(this);
3786 bool vector256 = true;
3787 assert(dst != xnoreg, "sanity");
3788 int dst_enc = dst->encoding();
3789 // swap src<->dst for encoding
3790 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3791 emit_int8(0x18);
3792 emit_operand(dst, src);
3793 // 0x01 - insert into upper 128 bits
3794 emit_int8(0x01);
3795 }
3796
3797 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3798 assert(VM_Version::supports_avx(), "");
3799 InstructionMark im(this);
3800 bool vector256 = true;
3801 assert(src != xnoreg, "sanity");
3802 int src_enc = src->encoding();
3803 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3804 emit_int8(0x19);
3805 emit_operand(src, dst);
3806 // 0x01 - extract from upper 128 bits
3807 emit_int8(0x01);
3808 }
3809
3810 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3811 assert(VM_Version::supports_avx2(), "");
3812 bool vector256 = true;
3813 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3814 emit_int8(0x38);
3815 emit_int8((unsigned char)(0xC0 | encode));
3816 // 0x00 - insert into lower 128 bits
3817 // 0x01 - insert into upper 128 bits
3818 emit_int8(0x01);
3819 }
3820
3821 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3822 assert(VM_Version::supports_avx2(), "");
3823 InstructionMark im(this);
3824 bool vector256 = true;
3825 assert(dst != xnoreg, "sanity");
3826 int dst_enc = dst->encoding();
3827 // swap src<->dst for encoding
3828 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3829 emit_int8(0x38);
3830 emit_operand(dst, src);
3831 // 0x01 - insert into upper 128 bits
3832 emit_int8(0x01);
3833 }
3834
3835 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3836 assert(VM_Version::supports_avx2(), "");
3837 InstructionMark im(this);
3838 bool vector256 = true;
3839 assert(src != xnoreg, "sanity");
3840 int src_enc = src->encoding();
3841 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3842 emit_int8(0x39);
3843 emit_operand(src, dst);
3844 // 0x01 - extract from upper 128 bits
3845 emit_int8(0x01);
3846 }
3847
3848 // duplicate 4-bytes integer data from src into 8 locations in dest
3849 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3850 assert(VM_Version::supports_avx2(), "");
3851 bool vector256 = true;
3852 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3853 emit_int8(0x58);
3854 emit_int8((unsigned char)(0xC0 | encode));
3855 }
3856
3857 // Carry-Less Multiplication Quadword
3858 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3859 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3860 bool vector256 = false;
3861 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3862 emit_int8(0x44);
3863 emit_int8((unsigned char)(0xC0 | encode));
3864 emit_int8((unsigned char)mask);
3865 }
3866
3867 void Assembler::vzeroupper() {
3868 assert(VM_Version::supports_avx(), "");
3869 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3870 emit_int8(0x77);
3871 }
3872
3873
3874 #ifndef _LP64
3875 // 32bit only pieces of the assembler
3876
3877 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3878 // NO PREFIX AS NEVER 64BIT
3879 InstructionMark im(this);
3880 emit_int8((unsigned char)0x81);
3881 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3882 emit_data(imm32, rspec, 0);
3883 }
3884
3885 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3886 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3887 InstructionMark im(this);
3888 emit_int8((unsigned char)0x81);
3889 emit_operand(rdi, src1);
3890 emit_data(imm32, rspec, 0);
3891 }
3892
3893 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3894 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3895 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3896 void Assembler::cmpxchg8(Address adr) {
3897 InstructionMark im(this);
3898 emit_int8(0x0F);
3899 emit_int8((unsigned char)0xC7);
3900 emit_operand(rcx, adr);
3901 }
3902
3903 void Assembler::decl(Register dst) {
3904 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3905 emit_int8(0x48 | dst->encoding());
3906 }
3907
3908 #endif // _LP64
3909
3910 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3911
3912 void Assembler::fabs() {
3913 emit_int8((unsigned char)0xD9);
3914 emit_int8((unsigned char)0xE1);
3915 }
3916
3917 void Assembler::fadd(int i) {
3918 emit_farith(0xD8, 0xC0, i);
3919 }
3920
3921 void Assembler::fadd_d(Address src) {
3922 InstructionMark im(this);
3923 emit_int8((unsigned char)0xDC);
3924 emit_operand32(rax, src);
3925 }
3926
3927 void Assembler::fadd_s(Address src) {
3928 InstructionMark im(this);
3929 emit_int8((unsigned char)0xD8);
3930 emit_operand32(rax, src);
3931 }
3932
3933 void Assembler::fadda(int i) {
3934 emit_farith(0xDC, 0xC0, i);
3935 }
3936
3937 void Assembler::faddp(int i) {
3938 emit_farith(0xDE, 0xC0, i);
3939 }
3940
3941 void Assembler::fchs() {
3942 emit_int8((unsigned char)0xD9);
3943 emit_int8((unsigned char)0xE0);
3944 }
3945
3946 void Assembler::fcom(int i) {
3947 emit_farith(0xD8, 0xD0, i);
3948 }
3949
3950 void Assembler::fcomp(int i) {
3951 emit_farith(0xD8, 0xD8, i);
3952 }
3953
3954 void Assembler::fcomp_d(Address src) {
3955 InstructionMark im(this);
3956 emit_int8((unsigned char)0xDC);
3957 emit_operand32(rbx, src);
3958 }
3959
3960 void Assembler::fcomp_s(Address src) {
3961 InstructionMark im(this);
3962 emit_int8((unsigned char)0xD8);
3963 emit_operand32(rbx, src);
3964 }
3965
3966 void Assembler::fcompp() {
3967 emit_int8((unsigned char)0xDE);
3968 emit_int8((unsigned char)0xD9);
3969 }
3970
3971 void Assembler::fcos() {
3972 emit_int8((unsigned char)0xD9);
3973 emit_int8((unsigned char)0xFF);
3974 }
3975
3976 void Assembler::fdecstp() {
3977 emit_int8((unsigned char)0xD9);
3978 emit_int8((unsigned char)0xF6);
3979 }
3980
3981 void Assembler::fdiv(int i) {
3982 emit_farith(0xD8, 0xF0, i);
3983 }
3984
3985 void Assembler::fdiv_d(Address src) {
3986 InstructionMark im(this);
3987 emit_int8((unsigned char)0xDC);
3988 emit_operand32(rsi, src);
3989 }
3990
3991 void Assembler::fdiv_s(Address src) {
3992 InstructionMark im(this);
3993 emit_int8((unsigned char)0xD8);
3994 emit_operand32(rsi, src);
3995 }
3996
3997 void Assembler::fdiva(int i) {
3998 emit_farith(0xDC, 0xF8, i);
3999 }
4000
4001 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
4002 // is erroneous for some of the floating-point instructions below.
4003
4004 void Assembler::fdivp(int i) {
4005 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
4006 }
4007
4008 void Assembler::fdivr(int i) {
4009 emit_farith(0xD8, 0xF8, i);
4010 }
4011
4012 void Assembler::fdivr_d(Address src) {
4013 InstructionMark im(this);
4014 emit_int8((unsigned char)0xDC);
4015 emit_operand32(rdi, src);
4016 }
4017
4018 void Assembler::fdivr_s(Address src) {
4019 InstructionMark im(this);
4020 emit_int8((unsigned char)0xD8);
4021 emit_operand32(rdi, src);
4022 }
4023
4024 void Assembler::fdivra(int i) {
4025 emit_farith(0xDC, 0xF0, i);
4026 }
4027
4028 void Assembler::fdivrp(int i) {
4029 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
4030 }
4031
4032 void Assembler::ffree(int i) {
4033 emit_farith(0xDD, 0xC0, i);
4034 }
4035
4036 void Assembler::fild_d(Address adr) {
4037 InstructionMark im(this);
4038 emit_int8((unsigned char)0xDF);
4039 emit_operand32(rbp, adr);
4040 }
4041
4042 void Assembler::fild_s(Address adr) {
4043 InstructionMark im(this);
4044 emit_int8((unsigned char)0xDB);
4045 emit_operand32(rax, adr);
4046 }
4047
4048 void Assembler::fincstp() {
4049 emit_int8((unsigned char)0xD9);
4050 emit_int8((unsigned char)0xF7);
4051 }
4052
4053 void Assembler::finit() {
4054 emit_int8((unsigned char)0x9B);
4055 emit_int8((unsigned char)0xDB);
4056 emit_int8((unsigned char)0xE3);
4057 }
4058
4059 void Assembler::fist_s(Address adr) {
4060 InstructionMark im(this);
4061 emit_int8((unsigned char)0xDB);
4062 emit_operand32(rdx, adr);
4063 }
4064
4065 void Assembler::fistp_d(Address adr) {
4066 InstructionMark im(this);
4067 emit_int8((unsigned char)0xDF);
4068 emit_operand32(rdi, adr);
4069 }
4070
4071 void Assembler::fistp_s(Address adr) {
4072 InstructionMark im(this);
4073 emit_int8((unsigned char)0xDB);
4074 emit_operand32(rbx, adr);
4075 }
4076
4077 void Assembler::fld1() {
4078 emit_int8((unsigned char)0xD9);
4079 emit_int8((unsigned char)0xE8);
4080 }
4081
4082 void Assembler::fld_d(Address adr) {
4083 InstructionMark im(this);
4084 emit_int8((unsigned char)0xDD);
4085 emit_operand32(rax, adr);
4086 }
4087
4088 void Assembler::fld_s(Address adr) {
4089 InstructionMark im(this);
4090 emit_int8((unsigned char)0xD9);
4091 emit_operand32(rax, adr);
4092 }
4093
4094
4095 void Assembler::fld_s(int index) {
4096 emit_farith(0xD9, 0xC0, index);
4097 }
4098
4099 void Assembler::fld_x(Address adr) {
4100 InstructionMark im(this);
4101 emit_int8((unsigned char)0xDB);
4102 emit_operand32(rbp, adr);
4103 }
4104
4105 void Assembler::fldcw(Address src) {
4106 InstructionMark im(this);
4107 emit_int8((unsigned char)0xD9);
4108 emit_operand32(rbp, src);
4109 }
4110
4111 void Assembler::fldenv(Address src) {
4112 InstructionMark im(this);
4113 emit_int8((unsigned char)0xD9);
4114 emit_operand32(rsp, src);
4115 }
4116
4117 void Assembler::fldlg2() {
4118 emit_int8((unsigned char)0xD9);
4119 emit_int8((unsigned char)0xEC);
4120 }
4121
4122 void Assembler::fldln2() {
4123 emit_int8((unsigned char)0xD9);
4124 emit_int8((unsigned char)0xED);
4125 }
4126
4127 void Assembler::fldz() {
4128 emit_int8((unsigned char)0xD9);
4129 emit_int8((unsigned char)0xEE);
4130 }
4131
4132 void Assembler::flog() {
4133 fldln2();
4134 fxch();
4135 fyl2x();
4136 }
4137
4138 void Assembler::flog10() {
4139 fldlg2();
4140 fxch();
4141 fyl2x();
4142 }
4143
4144 void Assembler::fmul(int i) {
4145 emit_farith(0xD8, 0xC8, i);
4146 }
4147
4148 void Assembler::fmul_d(Address src) {
4149 InstructionMark im(this);
4150 emit_int8((unsigned char)0xDC);
4151 emit_operand32(rcx, src);
4152 }
4153
4154 void Assembler::fmul_s(Address src) {
4155 InstructionMark im(this);
4156 emit_int8((unsigned char)0xD8);
4157 emit_operand32(rcx, src);
4158 }
4159
4160 void Assembler::fmula(int i) {
4161 emit_farith(0xDC, 0xC8, i);
4162 }
4163
4164 void Assembler::fmulp(int i) {
4165 emit_farith(0xDE, 0xC8, i);
4166 }
4167
4168 void Assembler::fnsave(Address dst) {
4169 InstructionMark im(this);
4170 emit_int8((unsigned char)0xDD);
4171 emit_operand32(rsi, dst);
4172 }
4173
4174 void Assembler::fnstcw(Address src) {
4175 InstructionMark im(this);
4176 emit_int8((unsigned char)0x9B);
4177 emit_int8((unsigned char)0xD9);
4178 emit_operand32(rdi, src);
4179 }
4180
4181 void Assembler::fnstsw_ax() {
4182 emit_int8((unsigned char)0xDF);
4183 emit_int8((unsigned char)0xE0);
4184 }
4185
4186 void Assembler::fprem() {
4187 emit_int8((unsigned char)0xD9);
4188 emit_int8((unsigned char)0xF8);
4189 }
4190
4191 void Assembler::fprem1() {
4192 emit_int8((unsigned char)0xD9);
4193 emit_int8((unsigned char)0xF5);
4194 }
4195
4196 void Assembler::frstor(Address src) {
4197 InstructionMark im(this);
4198 emit_int8((unsigned char)0xDD);
4199 emit_operand32(rsp, src);
4200 }
4201
4202 void Assembler::fsin() {
4203 emit_int8((unsigned char)0xD9);
4204 emit_int8((unsigned char)0xFE);
4205 }
4206
4207 void Assembler::fsqrt() {
4208 emit_int8((unsigned char)0xD9);
4209 emit_int8((unsigned char)0xFA);
4210 }
4211
4212 void Assembler::fst_d(Address adr) {
4213 InstructionMark im(this);
4214 emit_int8((unsigned char)0xDD);
4215 emit_operand32(rdx, adr);
4216 }
4217
4218 void Assembler::fst_s(Address adr) {
4219 InstructionMark im(this);
4220 emit_int8((unsigned char)0xD9);
4221 emit_operand32(rdx, adr);
4222 }
4223
4224 void Assembler::fstp_d(Address adr) {
4225 InstructionMark im(this);
4226 emit_int8((unsigned char)0xDD);
4227 emit_operand32(rbx, adr);
4228 }
4229
4230 void Assembler::fstp_d(int index) {
4231 emit_farith(0xDD, 0xD8, index);
4232 }
4233
4234 void Assembler::fstp_s(Address adr) {
4235 InstructionMark im(this);
4236 emit_int8((unsigned char)0xD9);
4237 emit_operand32(rbx, adr);
4238 }
4239
4240 void Assembler::fstp_x(Address adr) {
4241 InstructionMark im(this);
4242 emit_int8((unsigned char)0xDB);
4243 emit_operand32(rdi, adr);
4244 }
4245
4246 void Assembler::fsub(int i) {
4247 emit_farith(0xD8, 0xE0, i);
4248 }
4249
4250 void Assembler::fsub_d(Address src) {
4251 InstructionMark im(this);
4252 emit_int8((unsigned char)0xDC);
4253 emit_operand32(rsp, src);
4254 }
4255
4256 void Assembler::fsub_s(Address src) {
4257 InstructionMark im(this);
4258 emit_int8((unsigned char)0xD8);
4259 emit_operand32(rsp, src);
4260 }
4261
4262 void Assembler::fsuba(int i) {
4263 emit_farith(0xDC, 0xE8, i);
4264 }
4265
4266 void Assembler::fsubp(int i) {
4267 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4268 }
4269
4270 void Assembler::fsubr(int i) {
4271 emit_farith(0xD8, 0xE8, i);
4272 }
4273
4274 void Assembler::fsubr_d(Address src) {
4275 InstructionMark im(this);
4276 emit_int8((unsigned char)0xDC);
4277 emit_operand32(rbp, src);
4278 }
4279
4280 void Assembler::fsubr_s(Address src) {
4281 InstructionMark im(this);
4282 emit_int8((unsigned char)0xD8);
4283 emit_operand32(rbp, src);
4284 }
4285
4286 void Assembler::fsubra(int i) {
4287 emit_farith(0xDC, 0xE0, i);
4288 }
4289
4290 void Assembler::fsubrp(int i) {
4291 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4292 }
4293
4294 void Assembler::ftan() {
4295 emit_int8((unsigned char)0xD9);
4296 emit_int8((unsigned char)0xF2);
4297 emit_int8((unsigned char)0xDD);
4298 emit_int8((unsigned char)0xD8);
4299 }
4300
4301 void Assembler::ftst() {
4302 emit_int8((unsigned char)0xD9);
4303 emit_int8((unsigned char)0xE4);
4304 }
4305
4306 void Assembler::fucomi(int i) {
4307 // make sure the instruction is supported (introduced for P6, together with cmov)
4308 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4309 emit_farith(0xDB, 0xE8, i);
4310 }
4311
4312 void Assembler::fucomip(int i) {
4313 // make sure the instruction is supported (introduced for P6, together with cmov)
4314 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4315 emit_farith(0xDF, 0xE8, i);
4316 }
4317
4318 void Assembler::fwait() {
4319 emit_int8((unsigned char)0x9B);
4320 }
4321
4322 void Assembler::fxch(int i) {
4323 emit_farith(0xD9, 0xC8, i);
4324 }
4325
4326 void Assembler::fyl2x() {
4327 emit_int8((unsigned char)0xD9);
4328 emit_int8((unsigned char)0xF1);
4329 }
4330
4331 void Assembler::frndint() {
4332 emit_int8((unsigned char)0xD9);
4333 emit_int8((unsigned char)0xFC);
4334 }
4335
4336 void Assembler::f2xm1() {
4337 emit_int8((unsigned char)0xD9);
4338 emit_int8((unsigned char)0xF0);
4339 }
4340
4341 void Assembler::fldl2e() {
4342 emit_int8((unsigned char)0xD9);
4343 emit_int8((unsigned char)0xEA);
4344 }
4345
4346 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4347 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4348 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4349 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4350
4351 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4352 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4353 if (pre > 0) {
4354 emit_int8(simd_pre[pre]);
4355 }
4356 if (rex_w) {
4357 prefixq(adr, xreg);
4358 } else {
4359 prefix(adr, xreg);
4360 }
4361 if (opc > 0) {
4362 emit_int8(0x0F);
4363 int opc2 = simd_opc[opc];
4364 if (opc2 > 0) {
4365 emit_int8(opc2);
4366 }
4367 }
4368 }
4369
4370 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4371 if (pre > 0) {
4372 emit_int8(simd_pre[pre]);
4373 }
4374 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4375 prefix_and_encode(dst_enc, src_enc);
4376 if (opc > 0) {
4377 emit_int8(0x0F);
4378 int opc2 = simd_opc[opc];
4379 if (opc2 > 0) {
4380 emit_int8(opc2);
4381 }
4382 }
4383 return encode;
4384 }
4385
4386
4387 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4388 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4389 prefix(VEX_3bytes);
4390
4391 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4392 byte1 = (~byte1) & 0xE0;
4393 byte1 |= opc;
4394 emit_int8(byte1);
4395
4396 int byte2 = ((~nds_enc) & 0xf) << 3;
4397 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4398 emit_int8(byte2);
4399 } else {
4400 prefix(VEX_2bytes);
4401
4402 int byte1 = vex_r ? VEX_R : 0;
4403 byte1 = (~byte1) & 0x80;
4404 byte1 |= ((~nds_enc) & 0xf) << 3;
4405 byte1 |= (vector256 ? 4 : 0) | pre;
4406 emit_int8(byte1);
4407 }
4408 }
4409
4410 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4411 bool vex_r = (xreg_enc >= 8);
4412 bool vex_b = adr.base_needs_rex();
4413 bool vex_x = adr.index_needs_rex();
4414 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4415 }
4416
4417 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4418 bool vex_r = (dst_enc >= 8);
4419 bool vex_b = (src_enc >= 8);
4420 bool vex_x = false;
4421 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4422 return (((dst_enc & 7) << 3) | (src_enc & 7));
4423 }
4424
4425
4426 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4427 if (UseAVX > 0) {
4428 int xreg_enc = xreg->encoding();
4429 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4430 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4431 } else {
4432 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4433 rex_prefix(adr, xreg, pre, opc, rex_w);
4434 }
4435 }
4436
4437 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4438 int dst_enc = dst->encoding();
4439 int src_enc = src->encoding();
4440 if (UseAVX > 0) {
4441 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4442 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4443 } else {
4444 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4445 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4446 }
4447 }
4448
4449 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4450 InstructionMark im(this);
4451 simd_prefix(dst, dst, src, pre);
4452 emit_int8(opcode);
4453 emit_operand(dst, src);
4454 }
4455
4456 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4457 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4458 emit_int8(opcode);
4459 emit_int8((unsigned char)(0xC0 | encode));
4460 }
4461
4462 // Versions with no second source register (non-destructive source).
4463 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4464 InstructionMark im(this);
4465 simd_prefix(dst, xnoreg, src, pre);
4466 emit_int8(opcode);
4467 emit_operand(dst, src);
4468 }
4469
4470 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4471 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4472 emit_int8(opcode);
4473 emit_int8((unsigned char)(0xC0 | encode));
4474 }
4475
4476 // 3-operands AVX instructions
4477 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4478 Address src, VexSimdPrefix pre, bool vector256) {
4479 InstructionMark im(this);
4480 vex_prefix(dst, nds, src, pre, vector256);
4481 emit_int8(opcode);
4482 emit_operand(dst, src);
4483 }
4484
4485 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4486 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4487 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4488 emit_int8(opcode);
4489 emit_int8((unsigned char)(0xC0 | encode));
4490 }
4491
4492 #ifndef _LP64
4493
4494 void Assembler::incl(Register dst) {
4495 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4496 emit_int8(0x40 | dst->encoding());
4497 }
4498
4499 void Assembler::lea(Register dst, Address src) {
4500 leal(dst, src);
4501 }
4502
4503 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4504 InstructionMark im(this);
4505 emit_int8((unsigned char)0xC7);
4506 emit_operand(rax, dst);
4507 emit_data((int)imm32, rspec, 0);
4508 }
4509
4510 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4511 InstructionMark im(this);
4512 int encode = prefix_and_encode(dst->encoding());
4513 emit_int8((unsigned char)(0xB8 | encode));
4514 emit_data((int)imm32, rspec, 0);
4515 }
4516
4517 void Assembler::popa() { // 32bit
4518 emit_int8(0x61);
4519 }
4520
4521 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4522 InstructionMark im(this);
4523 emit_int8(0x68);
4524 emit_data(imm32, rspec, 0);
4525 }
4526
4527 void Assembler::pusha() { // 32bit
4528 emit_int8(0x60);
4529 }
4530
4531 void Assembler::set_byte_if_not_zero(Register dst) {
4532 emit_int8(0x0F);
4533 emit_int8((unsigned char)0x95);
4534 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4535 }
4536
4537 void Assembler::shldl(Register dst, Register src) {
4538 emit_int8(0x0F);
4539 emit_int8((unsigned char)0xA5);
4540 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4541 }
4542
4543 void Assembler::shrdl(Register dst, Register src) {
4544 emit_int8(0x0F);
4545 emit_int8((unsigned char)0xAD);
4546 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4547 }
4548
4549 #else // LP64
4550
4551 void Assembler::set_byte_if_not_zero(Register dst) {
4552 int enc = prefix_and_encode(dst->encoding(), true);
4553 emit_int8(0x0F);
4554 emit_int8((unsigned char)0x95);
4555 emit_int8((unsigned char)(0xE0 | enc));
4556 }
4557
4558 // 64bit only pieces of the assembler
4559 // This should only be used by 64bit instructions that can use rip-relative
4560 // it cannot be used by instructions that want an immediate value.
4561
4562 bool Assembler::reachable(AddressLiteral adr) {
4563 int64_t disp;
4564 // None will force a 64bit literal to the code stream. Likely a placeholder
4565 // for something that will be patched later and we need to certain it will
4566 // always be reachable.
4567 if (adr.reloc() == relocInfo::none) {
4568 return false;
4569 }
4570 if (adr.reloc() == relocInfo::internal_word_type) {
4571 // This should be rip relative and easily reachable.
4572 return true;
4573 }
4574 if (adr.reloc() == relocInfo::virtual_call_type ||
4575 adr.reloc() == relocInfo::opt_virtual_call_type ||
4576 adr.reloc() == relocInfo::static_call_type ||
4577 adr.reloc() == relocInfo::static_stub_type ) {
4578 // This should be rip relative within the code cache and easily
4579 // reachable until we get huge code caches. (At which point
4580 // ic code is going to have issues).
4581 return true;
4582 }
4583 if (adr.reloc() != relocInfo::external_word_type &&
4584 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4585 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4586 adr.reloc() != relocInfo::runtime_call_type ) {
4587 return false;
4588 }
4589
4590 // Stress the correction code
4591 if (ForceUnreachable) {
4592 // Must be runtimecall reloc, see if it is in the codecache
4593 // Flipping stuff in the codecache to be unreachable causes issues
4594 // with things like inline caches where the additional instructions
4595 // are not handled.
4596 if (CodeCache::find_blob(adr._target) == NULL) {
4597 return false;
4598 }
4599 }
4600 // For external_word_type/runtime_call_type if it is reachable from where we
4601 // are now (possibly a temp buffer) and where we might end up
4602 // anywhere in the codeCache then we are always reachable.
4603 // This would have to change if we ever save/restore shared code
4604 // to be more pessimistic.
4605 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4606 if (!is_simm32(disp)) return false;
4607 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4608 if (!is_simm32(disp)) return false;
4609
4610 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4611
4612 // Because rip relative is a disp + address_of_next_instruction and we
4613 // don't know the value of address_of_next_instruction we apply a fudge factor
4614 // to make sure we will be ok no matter the size of the instruction we get placed into.
4615 // We don't have to fudge the checks above here because they are already worst case.
4616
4617 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4618 // + 4 because better safe than sorry.
4619 const int fudge = 12 + 4;
4620 if (disp < 0) {
4621 disp -= fudge;
4622 } else {
4623 disp += fudge;
4624 }
4625 return is_simm32(disp);
4626 }
4627
4628 // Check if the polling page is not reachable from the code cache using rip-relative
4629 // addressing.
4630 bool Assembler::is_polling_page_far() {
4631 intptr_t addr = (intptr_t)os::get_polling_page();
4632 return ForceUnreachable ||
4633 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4634 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4635 }
4636
4637 void Assembler::emit_data64(jlong data,
4638 relocInfo::relocType rtype,
4639 int format) {
4640 if (rtype == relocInfo::none) {
4641 emit_int64(data);
4642 } else {
4643 emit_data64(data, Relocation::spec_simple(rtype), format);
4644 }
4645 }
4646
4647 void Assembler::emit_data64(jlong data,
4648 RelocationHolder const& rspec,
4649 int format) {
4650 assert(imm_operand == 0, "default format must be immediate in this file");
4651 assert(imm_operand == format, "must be immediate");
4652 assert(inst_mark() != NULL, "must be inside InstructionMark");
4653 // Do not use AbstractAssembler::relocate, which is not intended for
4654 // embedded words. Instead, relocate to the enclosing instruction.
4655 code_section()->relocate(inst_mark(), rspec, format);
4656 #ifdef ASSERT
4657 check_relocation(rspec, format);
4658 #endif
4659 emit_int64(data);
4660 }
4661
4662 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4663 if (reg_enc >= 8) {
4664 prefix(REX_B);
4665 reg_enc -= 8;
4666 } else if (byteinst && reg_enc >= 4) {
4667 prefix(REX);
4668 }
4669 return reg_enc;
4670 }
4671
4672 int Assembler::prefixq_and_encode(int reg_enc) {
4673 if (reg_enc < 8) {
4674 prefix(REX_W);
4675 } else {
4676 prefix(REX_WB);
4677 reg_enc -= 8;
4678 }
4679 return reg_enc;
4680 }
4681
4682 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4683 if (dst_enc < 8) {
4684 if (src_enc >= 8) {
4685 prefix(REX_B);
4686 src_enc -= 8;
4687 } else if (byteinst && src_enc >= 4) {
4688 prefix(REX);
4689 }
4690 } else {
4691 if (src_enc < 8) {
4692 prefix(REX_R);
4693 } else {
4694 prefix(REX_RB);
4695 src_enc -= 8;
4696 }
4697 dst_enc -= 8;
4698 }
4699 return dst_enc << 3 | src_enc;
4700 }
4701
4702 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4703 if (dst_enc < 8) {
4704 if (src_enc < 8) {
4705 prefix(REX_W);
4706 } else {
4707 prefix(REX_WB);
4708 src_enc -= 8;
4709 }
4710 } else {
4711 if (src_enc < 8) {
4712 prefix(REX_WR);
4713 } else {
4714 prefix(REX_WRB);
4715 src_enc -= 8;
4716 }
4717 dst_enc -= 8;
4718 }
4719 return dst_enc << 3 | src_enc;
4720 }
4721
4722 void Assembler::prefix(Register reg) {
4723 if (reg->encoding() >= 8) {
4724 prefix(REX_B);
4725 }
4726 }
4727
4728 void Assembler::prefix(Address adr) {
4729 if (adr.base_needs_rex()) {
4730 if (adr.index_needs_rex()) {
4731 prefix(REX_XB);
4732 } else {
4733 prefix(REX_B);
4734 }
4735 } else {
4736 if (adr.index_needs_rex()) {
4737 prefix(REX_X);
4738 }
4739 }
4740 }
4741
4742 void Assembler::prefixq(Address adr) {
4743 if (adr.base_needs_rex()) {
4744 if (adr.index_needs_rex()) {
4745 prefix(REX_WXB);
4746 } else {
4747 prefix(REX_WB);
4748 }
4749 } else {
4750 if (adr.index_needs_rex()) {
4751 prefix(REX_WX);
4752 } else {
4753 prefix(REX_W);
4754 }
4755 }
4756 }
4757
4758
4759 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4760 if (reg->encoding() < 8) {
4761 if (adr.base_needs_rex()) {
4762 if (adr.index_needs_rex()) {
4763 prefix(REX_XB);
4764 } else {
4765 prefix(REX_B);
4766 }
4767 } else {
4768 if (adr.index_needs_rex()) {
4769 prefix(REX_X);
4770 } else if (byteinst && reg->encoding() >= 4 ) {
4771 prefix(REX);
4772 }
4773 }
4774 } else {
4775 if (adr.base_needs_rex()) {
4776 if (adr.index_needs_rex()) {
4777 prefix(REX_RXB);
4778 } else {
4779 prefix(REX_RB);
4780 }
4781 } else {
4782 if (adr.index_needs_rex()) {
4783 prefix(REX_RX);
4784 } else {
4785 prefix(REX_R);
4786 }
4787 }
4788 }
4789 }
4790
4791 void Assembler::prefixq(Address adr, Register src) {
4792 if (src->encoding() < 8) {
4793 if (adr.base_needs_rex()) {
4794 if (adr.index_needs_rex()) {
4795 prefix(REX_WXB);
4796 } else {
4797 prefix(REX_WB);
4798 }
4799 } else {
4800 if (adr.index_needs_rex()) {
4801 prefix(REX_WX);
4802 } else {
4803 prefix(REX_W);
4804 }
4805 }
4806 } else {
4807 if (adr.base_needs_rex()) {
4808 if (adr.index_needs_rex()) {
4809 prefix(REX_WRXB);
4810 } else {
4811 prefix(REX_WRB);
4812 }
4813 } else {
4814 if (adr.index_needs_rex()) {
4815 prefix(REX_WRX);
4816 } else {
4817 prefix(REX_WR);
4818 }
4819 }
4820 }
4821 }
4822
4823 void Assembler::prefix(Address adr, XMMRegister reg) {
4824 if (reg->encoding() < 8) {
4825 if (adr.base_needs_rex()) {
4826 if (adr.index_needs_rex()) {
4827 prefix(REX_XB);
4828 } else {
4829 prefix(REX_B);
4830 }
4831 } else {
4832 if (adr.index_needs_rex()) {
4833 prefix(REX_X);
4834 }
4835 }
4836 } else {
4837 if (adr.base_needs_rex()) {
4838 if (adr.index_needs_rex()) {
4839 prefix(REX_RXB);
4840 } else {
4841 prefix(REX_RB);
4842 }
4843 } else {
4844 if (adr.index_needs_rex()) {
4845 prefix(REX_RX);
4846 } else {
4847 prefix(REX_R);
4848 }
4849 }
4850 }
4851 }
4852
4853 void Assembler::prefixq(Address adr, XMMRegister src) {
4854 if (src->encoding() < 8) {
4855 if (adr.base_needs_rex()) {
4856 if (adr.index_needs_rex()) {
4857 prefix(REX_WXB);
4858 } else {
4859 prefix(REX_WB);
4860 }
4861 } else {
4862 if (adr.index_needs_rex()) {
4863 prefix(REX_WX);
4864 } else {
4865 prefix(REX_W);
4866 }
4867 }
4868 } else {
4869 if (adr.base_needs_rex()) {
4870 if (adr.index_needs_rex()) {
4871 prefix(REX_WRXB);
4872 } else {
4873 prefix(REX_WRB);
4874 }
4875 } else {
4876 if (adr.index_needs_rex()) {
4877 prefix(REX_WRX);
4878 } else {
4879 prefix(REX_WR);
4880 }
4881 }
4882 }
4883 }
4884
4885 void Assembler::adcq(Register dst, int32_t imm32) {
4886 (void) prefixq_and_encode(dst->encoding());
4887 emit_arith(0x81, 0xD0, dst, imm32);
4888 }
4889
4890 void Assembler::adcq(Register dst, Address src) {
4891 InstructionMark im(this);
4892 prefixq(src, dst);
4893 emit_int8(0x13);
4894 emit_operand(dst, src);
4895 }
4896
4897 void Assembler::adcq(Register dst, Register src) {
4898 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4899 emit_arith(0x13, 0xC0, dst, src);
4900 }
4901
4902 void Assembler::addq(Address dst, int32_t imm32) {
4903 InstructionMark im(this);
4904 prefixq(dst);
4905 emit_arith_operand(0x81, rax, dst,imm32);
4906 }
4907
4908 void Assembler::addq(Address dst, Register src) {
4909 InstructionMark im(this);
4910 prefixq(dst, src);
4911 emit_int8(0x01);
4912 emit_operand(src, dst);
4913 }
4914
4915 void Assembler::addq(Register dst, int32_t imm32) {
4916 (void) prefixq_and_encode(dst->encoding());
4917 emit_arith(0x81, 0xC0, dst, imm32);
4918 }
4919
4920 void Assembler::addq(Register dst, Address src) {
4921 InstructionMark im(this);
4922 prefixq(src, dst);
4923 emit_int8(0x03);
4924 emit_operand(dst, src);
4925 }
4926
4927 void Assembler::addq(Register dst, Register src) {
4928 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4929 emit_arith(0x03, 0xC0, dst, src);
4930 }
4931
4932 void Assembler::andq(Address dst, int32_t imm32) {
4933 InstructionMark im(this);
4934 prefixq(dst);
4935 emit_int8((unsigned char)0x81);
4936 emit_operand(rsp, dst, 4);
4937 emit_int32(imm32);
4938 }
4939
4940 void Assembler::andq(Register dst, int32_t imm32) {
4941 (void) prefixq_and_encode(dst->encoding());
4942 emit_arith(0x81, 0xE0, dst, imm32);
4943 }
4944
4945 void Assembler::andq(Register dst, Address src) {
4946 InstructionMark im(this);
4947 prefixq(src, dst);
4948 emit_int8(0x23);
4949 emit_operand(dst, src);
4950 }
4951
4952 void Assembler::andq(Register dst, Register src) {
4953 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4954 emit_arith(0x23, 0xC0, dst, src);
4955 }
4956
4957 void Assembler::andnq(Register dst, Register src1, Register src2) {
4958 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4959 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4960 emit_int8((unsigned char)0xF2);
4961 emit_int8((unsigned char)(0xC0 | encode));
4962 }
4963
4964 void Assembler::andnq(Register dst, Register src1, Address src2) {
4965 InstructionMark im(this);
4966 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4967 vex_prefix_0F38_q(dst, src1, src2);
4968 emit_int8((unsigned char)0xF2);
4969 emit_operand(dst, src2);
4970 }
4971
4972 void Assembler::bsfq(Register dst, Register src) {
4973 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4974 emit_int8(0x0F);
4975 emit_int8((unsigned char)0xBC);
4976 emit_int8((unsigned char)(0xC0 | encode));
4977 }
4978
4979 void Assembler::bsrq(Register dst, Register src) {
4980 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4981 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4982 emit_int8(0x0F);
4983 emit_int8((unsigned char)0xBD);
4984 emit_int8((unsigned char)(0xC0 | encode));
4985 }
4986
4987 void Assembler::bswapq(Register reg) {
4988 int encode = prefixq_and_encode(reg->encoding());
4989 emit_int8(0x0F);
4990 emit_int8((unsigned char)(0xC8 | encode));
4991 }
4992
4993 void Assembler::blsiq(Register dst, Register src) {
4994 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4995 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4996 emit_int8((unsigned char)0xF3);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 }
4999
5000 void Assembler::blsiq(Register dst, Address src) {
5001 InstructionMark im(this);
5002 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5003 vex_prefix_0F38_q(rbx, dst, src);
5004 emit_int8((unsigned char)0xF3);
5005 emit_operand(rbx, src);
5006 }
5007
5008 void Assembler::blsmskq(Register dst, Register src) {
5009 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5010 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
5011 emit_int8((unsigned char)0xF3);
5012 emit_int8((unsigned char)(0xC0 | encode));
5013 }
5014
5015 void Assembler::blsmskq(Register dst, Address src) {
5016 InstructionMark im(this);
5017 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5018 vex_prefix_0F38_q(rdx, dst, src);
5019 emit_int8((unsigned char)0xF3);
5020 emit_operand(rdx, src);
5021 }
5022
5023 void Assembler::blsrq(Register dst, Register src) {
5024 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5025 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
5026 emit_int8((unsigned char)0xF3);
5027 emit_int8((unsigned char)(0xC0 | encode));
5028 }
5029
5030 void Assembler::blsrq(Register dst, Address src) {
5031 InstructionMark im(this);
5032 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5033 vex_prefix_0F38_q(rcx, dst, src);
5034 emit_int8((unsigned char)0xF3);
5035 emit_operand(rcx, src);
5036 }
5037
5038 void Assembler::cdqq() {
5039 prefix(REX_W);
5040 emit_int8((unsigned char)0x99);
5041 }
5042
5043 void Assembler::clflush(Address adr) {
5044 prefix(adr);
5045 emit_int8(0x0F);
5046 emit_int8((unsigned char)0xAE);
5047 emit_operand(rdi, adr);
5048 }
5049
5050 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5051 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5052 emit_int8(0x0F);
5053 emit_int8(0x40 | cc);
5054 emit_int8((unsigned char)(0xC0 | encode));
5055 }
5056
5057 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5058 InstructionMark im(this);
5059 prefixq(src, dst);
5060 emit_int8(0x0F);
5061 emit_int8(0x40 | cc);
5062 emit_operand(dst, src);
5063 }
5064
5065 void Assembler::cmpq(Address dst, int32_t imm32) {
5066 InstructionMark im(this);
5067 prefixq(dst);
5068 emit_int8((unsigned char)0x81);
5069 emit_operand(rdi, dst, 4);
5070 emit_int32(imm32);
5071 }
5072
5073 void Assembler::cmpq(Register dst, int32_t imm32) {
5074 (void) prefixq_and_encode(dst->encoding());
5075 emit_arith(0x81, 0xF8, dst, imm32);
5076 }
5077
5078 void Assembler::cmpq(Address dst, Register src) {
5079 InstructionMark im(this);
5080 prefixq(dst, src);
5081 emit_int8(0x3B);
5082 emit_operand(src, dst);
5083 }
5084
5085 void Assembler::cmpq(Register dst, Register src) {
5086 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5087 emit_arith(0x3B, 0xC0, dst, src);
5088 }
5089
5090 void Assembler::cmpq(Register dst, Address src) {
5091 InstructionMark im(this);
5092 prefixq(src, dst);
5093 emit_int8(0x3B);
5094 emit_operand(dst, src);
5095 }
5096
5097 void Assembler::cmpxchgq(Register reg, Address adr) {
5098 InstructionMark im(this);
5099 prefixq(adr, reg);
5100 emit_int8(0x0F);
5101 emit_int8((unsigned char)0xB1);
5102 emit_operand(reg, adr);
5103 }
5104
5105 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5106 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5107 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5108 emit_int8(0x2A);
5109 emit_int8((unsigned char)(0xC0 | encode));
5110 }
5111
5112 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5114 InstructionMark im(this);
5115 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5116 emit_int8(0x2A);
5117 emit_operand(dst, src);
5118 }
5119
5120 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5121 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5122 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5123 emit_int8(0x2A);
5124 emit_int8((unsigned char)(0xC0 | encode));
5125 }
5126
5127 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5128 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5129 InstructionMark im(this);
5130 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5131 emit_int8(0x2A);
5132 emit_operand(dst, src);
5133 }
5134
5135 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5136 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5137 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5138 emit_int8(0x2C);
5139 emit_int8((unsigned char)(0xC0 | encode));
5140 }
5141
5142 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5143 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5144 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5145 emit_int8(0x2C);
5146 emit_int8((unsigned char)(0xC0 | encode));
5147 }
5148
5149 void Assembler::decl(Register dst) {
5150 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5151 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5152 int encode = prefix_and_encode(dst->encoding());
5153 emit_int8((unsigned char)0xFF);
5154 emit_int8((unsigned char)(0xC8 | encode));
5155 }
5156
5157 void Assembler::decq(Register dst) {
5158 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5159 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5160 int encode = prefixq_and_encode(dst->encoding());
5161 emit_int8((unsigned char)0xFF);
5162 emit_int8(0xC8 | encode);
5163 }
5164
5165 void Assembler::decq(Address dst) {
5166 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5167 InstructionMark im(this);
5168 prefixq(dst);
5169 emit_int8((unsigned char)0xFF);
5170 emit_operand(rcx, dst);
5171 }
5172
5173 void Assembler::fxrstor(Address src) {
5174 prefixq(src);
5175 emit_int8(0x0F);
5176 emit_int8((unsigned char)0xAE);
5177 emit_operand(as_Register(1), src);
5178 }
5179
5180 void Assembler::fxsave(Address dst) {
5181 prefixq(dst);
5182 emit_int8(0x0F);
5183 emit_int8((unsigned char)0xAE);
5184 emit_operand(as_Register(0), dst);
5185 }
5186
5187 void Assembler::idivq(Register src) {
5188 int encode = prefixq_and_encode(src->encoding());
5189 emit_int8((unsigned char)0xF7);
5190 emit_int8((unsigned char)(0xF8 | encode));
5191 }
5192
5193 void Assembler::imulq(Register dst, Register src) {
5194 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5195 emit_int8(0x0F);
5196 emit_int8((unsigned char)0xAF);
5197 emit_int8((unsigned char)(0xC0 | encode));
5198 }
5199
5200 void Assembler::imulq(Register dst, Register src, int value) {
5201 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5202 if (is8bit(value)) {
5203 emit_int8(0x6B);
5204 emit_int8((unsigned char)(0xC0 | encode));
5205 emit_int8(value & 0xFF);
5206 } else {
5207 emit_int8(0x69);
5208 emit_int8((unsigned char)(0xC0 | encode));
5209 emit_int32(value);
5210 }
5211 }
5212
5213 void Assembler::imulq(Register dst, Address src) {
5214 InstructionMark im(this);
5215 prefixq(src, dst);
5216 emit_int8(0x0F);
5217 emit_int8((unsigned char) 0xAF);
5218 emit_operand(dst, src);
5219 }
5220
5221 void Assembler::incl(Register dst) {
5222 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5223 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5224 int encode = prefix_and_encode(dst->encoding());
5225 emit_int8((unsigned char)0xFF);
5226 emit_int8((unsigned char)(0xC0 | encode));
5227 }
5228
5229 void Assembler::incq(Register dst) {
5230 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5231 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5232 int encode = prefixq_and_encode(dst->encoding());
5233 emit_int8((unsigned char)0xFF);
5234 emit_int8((unsigned char)(0xC0 | encode));
5235 }
5236
5237 void Assembler::incq(Address dst) {
5238 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5239 InstructionMark im(this);
5240 prefixq(dst);
5241 emit_int8((unsigned char)0xFF);
5242 emit_operand(rax, dst);
5243 }
5244
5245 void Assembler::lea(Register dst, Address src) {
5246 leaq(dst, src);
5247 }
5248
5249 void Assembler::leaq(Register dst, Address src) {
5250 InstructionMark im(this);
5251 prefixq(src, dst);
5252 emit_int8((unsigned char)0x8D);
5253 emit_operand(dst, src);
5254 }
5255
5256 void Assembler::mov64(Register dst, int64_t imm64) {
5257 InstructionMark im(this);
5258 int encode = prefixq_and_encode(dst->encoding());
5259 emit_int8((unsigned char)(0xB8 | encode));
5260 emit_int64(imm64);
5261 }
5262
5263 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5264 InstructionMark im(this);
5265 int encode = prefixq_and_encode(dst->encoding());
5266 emit_int8(0xB8 | encode);
5267 emit_data64(imm64, rspec);
5268 }
5269
5270 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5271 InstructionMark im(this);
5272 int encode = prefix_and_encode(dst->encoding());
5273 emit_int8((unsigned char)(0xB8 | encode));
5274 emit_data((int)imm32, rspec, narrow_oop_operand);
5275 }
5276
5277 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5278 InstructionMark im(this);
5279 prefix(dst);
5280 emit_int8((unsigned char)0xC7);
5281 emit_operand(rax, dst, 4);
5282 emit_data((int)imm32, rspec, narrow_oop_operand);
5283 }
5284
5285 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5286 InstructionMark im(this);
5287 int encode = prefix_and_encode(src1->encoding());
5288 emit_int8((unsigned char)0x81);
5289 emit_int8((unsigned char)(0xF8 | encode));
5290 emit_data((int)imm32, rspec, narrow_oop_operand);
5291 }
5292
5293 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5294 InstructionMark im(this);
5295 prefix(src1);
5296 emit_int8((unsigned char)0x81);
5297 emit_operand(rax, src1, 4);
5298 emit_data((int)imm32, rspec, narrow_oop_operand);
5299 }
5300
5301 void Assembler::lzcntq(Register dst, Register src) {
5302 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5303 emit_int8((unsigned char)0xF3);
5304 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5305 emit_int8(0x0F);
5306 emit_int8((unsigned char)0xBD);
5307 emit_int8((unsigned char)(0xC0 | encode));
5308 }
5309
5310 void Assembler::movdq(XMMRegister dst, Register src) {
5311 // table D-1 says MMX/SSE2
5312 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5313 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5314 emit_int8(0x6E);
5315 emit_int8((unsigned char)(0xC0 | encode));
5316 }
5317
5318 void Assembler::movdq(Register dst, XMMRegister src) {
5319 // table D-1 says MMX/SSE2
5320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5321 // swap src/dst to get correct prefix
5322 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5323 emit_int8(0x7E);
5324 emit_int8((unsigned char)(0xC0 | encode));
5325 }
5326
5327 void Assembler::movq(Register dst, Register src) {
5328 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5329 emit_int8((unsigned char)0x8B);
5330 emit_int8((unsigned char)(0xC0 | encode));
5331 }
5332
5333 void Assembler::movq(Register dst, Address src) {
5334 InstructionMark im(this);
5335 prefixq(src, dst);
5336 emit_int8((unsigned char)0x8B);
5337 emit_operand(dst, src);
5338 }
5339
5340 void Assembler::movq(Address dst, Register src) {
5341 InstructionMark im(this);
5342 prefixq(dst, src);
5343 emit_int8((unsigned char)0x89);
5344 emit_operand(src, dst);
5345 }
5346
5347 void Assembler::movsbq(Register dst, Address src) {
5348 InstructionMark im(this);
5349 prefixq(src, dst);
5350 emit_int8(0x0F);
5351 emit_int8((unsigned char)0xBE);
5352 emit_operand(dst, src);
5353 }
5354
5355 void Assembler::movsbq(Register dst, Register src) {
5356 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5357 emit_int8(0x0F);
5358 emit_int8((unsigned char)0xBE);
5359 emit_int8((unsigned char)(0xC0 | encode));
5360 }
5361
5362 void Assembler::movslq(Register dst, int32_t imm32) {
5363 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5364 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5365 // as a result we shouldn't use until tested at runtime...
5366 ShouldNotReachHere();
5367 InstructionMark im(this);
5368 int encode = prefixq_and_encode(dst->encoding());
5369 emit_int8((unsigned char)(0xC7 | encode));
5370 emit_int32(imm32);
5371 }
5372
5373 void Assembler::movslq(Address dst, int32_t imm32) {
5374 assert(is_simm32(imm32), "lost bits");
5375 InstructionMark im(this);
5376 prefixq(dst);
5377 emit_int8((unsigned char)0xC7);
5378 emit_operand(rax, dst, 4);
5379 emit_int32(imm32);
5380 }
5381
5382 void Assembler::movslq(Register dst, Address src) {
5383 InstructionMark im(this);
5384 prefixq(src, dst);
5385 emit_int8(0x63);
5386 emit_operand(dst, src);
5387 }
5388
5389 void Assembler::movslq(Register dst, Register src) {
5390 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5391 emit_int8(0x63);
5392 emit_int8((unsigned char)(0xC0 | encode));
5393 }
5394
5395 void Assembler::movswq(Register dst, Address src) {
5396 InstructionMark im(this);
5397 prefixq(src, dst);
5398 emit_int8(0x0F);
5399 emit_int8((unsigned char)0xBF);
5400 emit_operand(dst, src);
5401 }
5402
5403 void Assembler::movswq(Register dst, Register src) {
5404 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5405 emit_int8((unsigned char)0x0F);
5406 emit_int8((unsigned char)0xBF);
5407 emit_int8((unsigned char)(0xC0 | encode));
5408 }
5409
5410 void Assembler::movzbq(Register dst, Address src) {
5411 InstructionMark im(this);
5412 prefixq(src, dst);
5413 emit_int8((unsigned char)0x0F);
5414 emit_int8((unsigned char)0xB6);
5415 emit_operand(dst, src);
5416 }
5417
5418 void Assembler::movzbq(Register dst, Register src) {
5419 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5420 emit_int8(0x0F);
5421 emit_int8((unsigned char)0xB6);
5422 emit_int8(0xC0 | encode);
5423 }
5424
5425 void Assembler::movzwq(Register dst, Address src) {
5426 InstructionMark im(this);
5427 prefixq(src, dst);
5428 emit_int8((unsigned char)0x0F);
5429 emit_int8((unsigned char)0xB7);
5430 emit_operand(dst, src);
5431 }
5432
5433 void Assembler::movzwq(Register dst, Register src) {
5434 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5435 emit_int8((unsigned char)0x0F);
5436 emit_int8((unsigned char)0xB7);
5437 emit_int8((unsigned char)(0xC0 | encode));
5438 }
5439
5440 void Assembler::negq(Register dst) {
5441 int encode = prefixq_and_encode(dst->encoding());
5442 emit_int8((unsigned char)0xF7);
5443 emit_int8((unsigned char)(0xD8 | encode));
5444 }
5445
5446 void Assembler::notq(Register dst) {
5447 int encode = prefixq_and_encode(dst->encoding());
5448 emit_int8((unsigned char)0xF7);
5449 emit_int8((unsigned char)(0xD0 | encode));
5450 }
5451
5452 void Assembler::orq(Address dst, int32_t imm32) {
5453 InstructionMark im(this);
5454 prefixq(dst);
5455 emit_int8((unsigned char)0x81);
5456 emit_operand(rcx, dst, 4);
5457 emit_int32(imm32);
5458 }
5459
5460 void Assembler::orq(Register dst, int32_t imm32) {
5461 (void) prefixq_and_encode(dst->encoding());
5462 emit_arith(0x81, 0xC8, dst, imm32);
5463 }
5464
5465 void Assembler::orq(Register dst, Address src) {
5466 InstructionMark im(this);
5467 prefixq(src, dst);
5468 emit_int8(0x0B);
5469 emit_operand(dst, src);
5470 }
5471
5472 void Assembler::orq(Register dst, Register src) {
5473 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5474 emit_arith(0x0B, 0xC0, dst, src);
5475 }
5476
5477 void Assembler::popa() { // 64bit
5478 movq(r15, Address(rsp, 0));
5479 movq(r14, Address(rsp, wordSize));
5480 movq(r13, Address(rsp, 2 * wordSize));
5481 movq(r12, Address(rsp, 3 * wordSize));
5482 movq(r11, Address(rsp, 4 * wordSize));
5483 movq(r10, Address(rsp, 5 * wordSize));
5484 movq(r9, Address(rsp, 6 * wordSize));
5485 movq(r8, Address(rsp, 7 * wordSize));
5486 movq(rdi, Address(rsp, 8 * wordSize));
5487 movq(rsi, Address(rsp, 9 * wordSize));
5488 movq(rbp, Address(rsp, 10 * wordSize));
5489 // skip rsp
5490 movq(rbx, Address(rsp, 12 * wordSize));
5491 movq(rdx, Address(rsp, 13 * wordSize));
5492 movq(rcx, Address(rsp, 14 * wordSize));
5493 movq(rax, Address(rsp, 15 * wordSize));
5494
5495 addq(rsp, 16 * wordSize);
5496 }
5497
5498 void Assembler::popcntq(Register dst, Address src) {
5499 assert(VM_Version::supports_popcnt(), "must support");
5500 InstructionMark im(this);
5501 emit_int8((unsigned char)0xF3);
5502 prefixq(src, dst);
5503 emit_int8((unsigned char)0x0F);
5504 emit_int8((unsigned char)0xB8);
5505 emit_operand(dst, src);
5506 }
5507
5508 void Assembler::popcntq(Register dst, Register src) {
5509 assert(VM_Version::supports_popcnt(), "must support");
5510 emit_int8((unsigned char)0xF3);
5511 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5512 emit_int8((unsigned char)0x0F);
5513 emit_int8((unsigned char)0xB8);
5514 emit_int8((unsigned char)(0xC0 | encode));
5515 }
5516
5517 void Assembler::popq(Address dst) {
5518 InstructionMark im(this);
5519 prefixq(dst);
5520 emit_int8((unsigned char)0x8F);
5521 emit_operand(rax, dst);
5522 }
5523
5524 void Assembler::pusha() { // 64bit
5525 // we have to store original rsp. ABI says that 128 bytes
5526 // below rsp are local scratch.
5527 movq(Address(rsp, -5 * wordSize), rsp);
5528
5529 subq(rsp, 16 * wordSize);
5530
5531 movq(Address(rsp, 15 * wordSize), rax);
5532 movq(Address(rsp, 14 * wordSize), rcx);
5533 movq(Address(rsp, 13 * wordSize), rdx);
5534 movq(Address(rsp, 12 * wordSize), rbx);
5535 // skip rsp
5536 movq(Address(rsp, 10 * wordSize), rbp);
5537 movq(Address(rsp, 9 * wordSize), rsi);
5538 movq(Address(rsp, 8 * wordSize), rdi);
5539 movq(Address(rsp, 7 * wordSize), r8);
5540 movq(Address(rsp, 6 * wordSize), r9);
5541 movq(Address(rsp, 5 * wordSize), r10);
5542 movq(Address(rsp, 4 * wordSize), r11);
5543 movq(Address(rsp, 3 * wordSize), r12);
5544 movq(Address(rsp, 2 * wordSize), r13);
5545 movq(Address(rsp, wordSize), r14);
5546 movq(Address(rsp, 0), r15);
5547 }
5548
5549 void Assembler::pushq(Address src) {
5550 InstructionMark im(this);
5551 prefixq(src);
5552 emit_int8((unsigned char)0xFF);
5553 emit_operand(rsi, src);
5554 }
5555
5556 void Assembler::rclq(Register dst, int imm8) {
5557 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5558 int encode = prefixq_and_encode(dst->encoding());
5559 if (imm8 == 1) {
5560 emit_int8((unsigned char)0xD1);
5561 emit_int8((unsigned char)(0xD0 | encode));
5562 } else {
5563 emit_int8((unsigned char)0xC1);
5564 emit_int8((unsigned char)(0xD0 | encode));
5565 emit_int8(imm8);
5566 }
5567 }
5568 void Assembler::sarq(Register dst, int imm8) {
5569 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5570 int encode = prefixq_and_encode(dst->encoding());
5571 if (imm8 == 1) {
5572 emit_int8((unsigned char)0xD1);
5573 emit_int8((unsigned char)(0xF8 | encode));
5574 } else {
5575 emit_int8((unsigned char)0xC1);
5576 emit_int8((unsigned char)(0xF8 | encode));
5577 emit_int8(imm8);
5578 }
5579 }
5580
5581 void Assembler::sarq(Register dst) {
5582 int encode = prefixq_and_encode(dst->encoding());
5583 emit_int8((unsigned char)0xD3);
5584 emit_int8((unsigned char)(0xF8 | encode));
5585 }
5586
5587 void Assembler::sbbq(Address dst, int32_t imm32) {
5588 InstructionMark im(this);
5589 prefixq(dst);
5590 emit_arith_operand(0x81, rbx, dst, imm32);
5591 }
5592
5593 void Assembler::sbbq(Register dst, int32_t imm32) {
5594 (void) prefixq_and_encode(dst->encoding());
5595 emit_arith(0x81, 0xD8, dst, imm32);
5596 }
5597
5598 void Assembler::sbbq(Register dst, Address src) {
5599 InstructionMark im(this);
5600 prefixq(src, dst);
5601 emit_int8(0x1B);
5602 emit_operand(dst, src);
5603 }
5604
5605 void Assembler::sbbq(Register dst, Register src) {
5606 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5607 emit_arith(0x1B, 0xC0, dst, src);
5608 }
5609
5610 void Assembler::shlq(Register dst, int imm8) {
5611 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5612 int encode = prefixq_and_encode(dst->encoding());
5613 if (imm8 == 1) {
5614 emit_int8((unsigned char)0xD1);
5615 emit_int8((unsigned char)(0xE0 | encode));
5616 } else {
5617 emit_int8((unsigned char)0xC1);
5618 emit_int8((unsigned char)(0xE0 | encode));
5619 emit_int8(imm8);
5620 }
5621 }
5622
5623 void Assembler::shlq(Register dst) {
5624 int encode = prefixq_and_encode(dst->encoding());
5625 emit_int8((unsigned char)0xD3);
5626 emit_int8((unsigned char)(0xE0 | encode));
5627 }
5628
5629 void Assembler::shrq(Register dst, int imm8) {
5630 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5631 int encode = prefixq_and_encode(dst->encoding());
5632 emit_int8((unsigned char)0xC1);
5633 emit_int8((unsigned char)(0xE8 | encode));
5634 emit_int8(imm8);
5635 }
5636
5637 void Assembler::shrq(Register dst) {
5638 int encode = prefixq_and_encode(dst->encoding());
5639 emit_int8((unsigned char)0xD3);
5640 emit_int8(0xE8 | encode);
5641 }
5642
5643 void Assembler::subq(Address dst, int32_t imm32) {
5644 InstructionMark im(this);
5645 prefixq(dst);
5646 emit_arith_operand(0x81, rbp, dst, imm32);
5647 }
5648
5649 void Assembler::subq(Address dst, Register src) {
5650 InstructionMark im(this);
5651 prefixq(dst, src);
5652 emit_int8(0x29);
5653 emit_operand(src, dst);
5654 }
5655
5656 void Assembler::subq(Register dst, int32_t imm32) {
5657 (void) prefixq_and_encode(dst->encoding());
5658 emit_arith(0x81, 0xE8, dst, imm32);
5659 }
5660
5661 // Force generation of a 4 byte immediate value even if it fits into 8bit
5662 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5663 (void) prefixq_and_encode(dst->encoding());
5664 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5665 }
5666
5667 void Assembler::subq(Register dst, Address src) {
5668 InstructionMark im(this);
5669 prefixq(src, dst);
5670 emit_int8(0x2B);
5671 emit_operand(dst, src);
5672 }
5673
5674 void Assembler::subq(Register dst, Register src) {
5675 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5676 emit_arith(0x2B, 0xC0, dst, src);
5677 }
5678
5679 void Assembler::testq(Register dst, int32_t imm32) {
5680 // not using emit_arith because test
5681 // doesn't support sign-extension of
5682 // 8bit operands
5683 int encode = dst->encoding();
5684 if (encode == 0) {
5685 prefix(REX_W);
5686 emit_int8((unsigned char)0xA9);
5687 } else {
5688 encode = prefixq_and_encode(encode);
5689 emit_int8((unsigned char)0xF7);
5690 emit_int8((unsigned char)(0xC0 | encode));
5691 }
5692 emit_int32(imm32);
5693 }
5694
5695 void Assembler::testq(Register dst, Register src) {
5696 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5697 emit_arith(0x85, 0xC0, dst, src);
5698 }
5699
5700 void Assembler::xaddq(Address dst, Register src) {
5701 InstructionMark im(this);
5702 prefixq(dst, src);
5703 emit_int8(0x0F);
5704 emit_int8((unsigned char)0xC1);
5705 emit_operand(src, dst);
5706 }
5707
5708 void Assembler::xchgq(Register dst, Address src) {
5709 InstructionMark im(this);
5710 prefixq(src, dst);
5711 emit_int8((unsigned char)0x87);
5712 emit_operand(dst, src);
5713 }
5714
5715 void Assembler::xchgq(Register dst, Register src) {
5716 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5717 emit_int8((unsigned char)0x87);
5718 emit_int8((unsigned char)(0xc0 | encode));
5719 }
5720
5721 void Assembler::xorq(Register dst, Register src) {
5722 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5723 emit_arith(0x33, 0xC0, dst, src);
5724 }
5725
5726 void Assembler::xorq(Register dst, Address src) {
5727 InstructionMark im(this);
5728 prefixq(src, dst);
5729 emit_int8(0x33);
5730 emit_operand(dst, src);
5731 }
5732
5733 #endif // !LP64