1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1116 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1117 emit_int8(0x0F);
1118 emit_int8((unsigned char)0xBD);
1119 emit_int8((unsigned char)(0xC0 | encode));
1120 }
1121
1122 void Assembler::bswapl(Register reg) { // bswap
1123 int encode = prefix_and_encode(reg->encoding());
1124 emit_int8(0x0F);
1125 emit_int8((unsigned char)(0xC8 | encode));
1126 }
1127
1128 void Assembler::blsil(Register dst, Register src) {
1129 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1130 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1131 emit_int8((unsigned char)0xF3);
1132 emit_int8((unsigned char)(0xC0 | encode));
1133 }
1134
1135 void Assembler::blsil(Register dst, Address src) {
4960 emit_int8((unsigned char)0xF2);
4961 emit_int8((unsigned char)(0xC0 | encode));
4962 }
4963
4964 void Assembler::andnq(Register dst, Register src1, Address src2) {
4965 InstructionMark im(this);
4966 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4967 vex_prefix_0F38_q(dst, src1, src2);
4968 emit_int8((unsigned char)0xF2);
4969 emit_operand(dst, src2);
4970 }
4971
4972 void Assembler::bsfq(Register dst, Register src) {
4973 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4974 emit_int8(0x0F);
4975 emit_int8((unsigned char)0xBC);
4976 emit_int8((unsigned char)(0xC0 | encode));
4977 }
4978
4979 void Assembler::bsrq(Register dst, Register src) {
4980 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4981 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4982 emit_int8(0x0F);
4983 emit_int8((unsigned char)0xBD);
4984 emit_int8((unsigned char)(0xC0 | encode));
4985 }
4986
4987 void Assembler::bswapq(Register reg) {
4988 int encode = prefixq_and_encode(reg->encoding());
4989 emit_int8(0x0F);
4990 emit_int8((unsigned char)(0xC8 | encode));
4991 }
4992
4993 void Assembler::blsiq(Register dst, Register src) {
4994 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4995 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4996 emit_int8((unsigned char)0xF3);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 }
4999
5000 void Assembler::blsiq(Register dst, Address src) {
|
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)0xBD);
1118 emit_int8((unsigned char)(0xC0 | encode));
1119 }
1120
1121 void Assembler::bswapl(Register reg) { // bswap
1122 int encode = prefix_and_encode(reg->encoding());
1123 emit_int8(0x0F);
1124 emit_int8((unsigned char)(0xC8 | encode));
1125 }
1126
1127 void Assembler::blsil(Register dst, Register src) {
1128 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1129 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1130 emit_int8((unsigned char)0xF3);
1131 emit_int8((unsigned char)(0xC0 | encode));
1132 }
1133
1134 void Assembler::blsil(Register dst, Address src) {
4959 emit_int8((unsigned char)0xF2);
4960 emit_int8((unsigned char)(0xC0 | encode));
4961 }
4962
4963 void Assembler::andnq(Register dst, Register src1, Address src2) {
4964 InstructionMark im(this);
4965 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4966 vex_prefix_0F38_q(dst, src1, src2);
4967 emit_int8((unsigned char)0xF2);
4968 emit_operand(dst, src2);
4969 }
4970
4971 void Assembler::bsfq(Register dst, Register src) {
4972 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4973 emit_int8(0x0F);
4974 emit_int8((unsigned char)0xBC);
4975 emit_int8((unsigned char)(0xC0 | encode));
4976 }
4977
4978 void Assembler::bsrq(Register dst, Register src) {
4979 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4980 emit_int8(0x0F);
4981 emit_int8((unsigned char)0xBD);
4982 emit_int8((unsigned char)(0xC0 | encode));
4983 }
4984
4985 void Assembler::bswapq(Register reg) {
4986 int encode = prefixq_and_encode(reg->encoding());
4987 emit_int8(0x0F);
4988 emit_int8((unsigned char)(0xC8 | encode));
4989 }
4990
4991 void Assembler::blsiq(Register dst, Register src) {
4992 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4993 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4994 emit_int8((unsigned char)0xF3);
4995 emit_int8((unsigned char)(0xC0 | encode));
4996 }
4997
4998 void Assembler::blsiq(Register dst, Address src) {
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