1 /* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef SHARE_VM_OPTO_MACHNODE_HPP 26 #define SHARE_VM_OPTO_MACHNODE_HPP 27 28 #include "opto/callnode.hpp" 29 #include "opto/matcher.hpp" 30 #include "opto/multnode.hpp" 31 #include "opto/node.hpp" 32 #include "opto/regmask.hpp" 33 34 class BiasedLockingCounters; 35 class BufferBlob; 36 class CodeBuffer; 37 class JVMState; 38 class MachCallDynamicJavaNode; 39 class MachCallJavaNode; 40 class MachCallLeafNode; 41 class MachCallNode; 42 class MachCallRuntimeNode; 43 class MachCallStaticJavaNode; 44 class MachEpilogNode; 45 class MachIfNode; 46 class MachNullCheckNode; 47 class MachOper; 48 class MachProjNode; 49 class MachPrologNode; 50 class MachReturnNode; 51 class MachSafePointNode; 52 class MachSpillCopyNode; 53 class Matcher; 54 class PhaseRegAlloc; 55 class RegMask; 56 class RTMLockingCounters; 57 class State; 58 59 //---------------------------MachOper------------------------------------------ 60 class MachOper : public ResourceObj { 61 public: 62 // Allocate right next to the MachNodes in the same arena 63 void *operator new( size_t x, Compile* C ) throw() { return C->node_arena()->Amalloc_D(x); } 64 65 // Opcode 66 virtual uint opcode() const = 0; 67 68 // Number of input edges. 69 // Generally at least 1 70 virtual uint num_edges() const { return 1; } 71 // Array of Register masks 72 virtual const RegMask *in_RegMask(int index) const; 73 74 // Methods to output the encoding of the operand 75 76 // Negate conditional branches. Error for non-branch Nodes 77 virtual void negate(); 78 79 // Return the value requested 80 // result register lookup, corresponding to int_format 81 virtual int reg(PhaseRegAlloc *ra_, const Node *node) const; 82 // input register lookup, corresponding to ext_format 83 virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const; 84 85 // helpers for MacroAssembler generation from ADLC 86 Register as_Register(PhaseRegAlloc *ra_, const Node *node) const { 87 return ::as_Register(reg(ra_, node)); 88 } 89 Register as_Register(PhaseRegAlloc *ra_, const Node *node, int idx) const { 90 return ::as_Register(reg(ra_, node, idx)); 91 } 92 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node) const { 93 return ::as_FloatRegister(reg(ra_, node)); 94 } 95 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 96 return ::as_FloatRegister(reg(ra_, node, idx)); 97 } 98 99 #if defined(IA32) || defined(AMD64) 100 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node) const { 101 return ::as_XMMRegister(reg(ra_, node)); 102 } 103 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 104 return ::as_XMMRegister(reg(ra_, node, idx)); 105 } 106 #endif 107 // CondRegister reg converter 108 #if defined(PPC64) 109 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const { 110 return ::as_ConditionRegister(reg(ra_, node)); 111 } 112 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 113 return ::as_ConditionRegister(reg(ra_, node, idx)); 114 } 115 #endif 116 117 virtual intptr_t constant() const; 118 virtual relocInfo::relocType constant_reloc() const; 119 virtual jdouble constantD() const; 120 virtual jfloat constantF() const; 121 virtual jlong constantL() const; 122 virtual TypeOopPtr *oop() const; 123 virtual int ccode() const; 124 // A zero, default, indicates this value is not needed. 125 // May need to lookup the base register, as done in int_ and ext_format 126 virtual int base (PhaseRegAlloc *ra_, const Node *node, int idx) const; 127 virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const; 128 virtual int scale() const; 129 // Parameters needed to support MEMORY_INTERFACE access to stackSlot 130 virtual int disp (PhaseRegAlloc *ra_, const Node *node, int idx) const; 131 // Check for PC-Relative displacement 132 virtual relocInfo::relocType disp_reloc() const; 133 virtual int constant_disp() const; // usu. 0, may return Type::OffsetBot 134 virtual int base_position() const; // base edge position, or -1 135 virtual int index_position() const; // index edge position, or -1 136 137 // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP 138 // Only returns non-null value for i486.ad's indOffset32X 139 virtual const TypePtr *disp_as_type() const { return NULL; } 140 141 // Return the label 142 virtual Label *label() const; 143 144 // Return the method's address 145 virtual intptr_t method() const; 146 147 // Hash and compare over operands are currently identical 148 virtual uint hash() const; 149 virtual uint cmp( const MachOper &oper ) const; 150 151 // Virtual clone, since I do not know how big the MachOper is. 152 virtual MachOper *clone(Compile* C) const = 0; 153 154 // Return ideal Type from simple operands. Fail for complex operands. 155 virtual const Type *type() const; 156 157 // Set an integer offset if we have one, or error otherwise 158 virtual void set_con( jint c0 ) { ShouldNotReachHere(); } 159 160 #ifndef PRODUCT 161 // Return name of operand 162 virtual const char *Name() const { return "???";} 163 164 // Methods to output the text version of the operand 165 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0; 166 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0; 167 168 virtual void dump_spec(outputStream *st) const; // Print per-operand info 169 170 // Check whether o is a valid oper. 171 static bool notAnOper(const MachOper *o) { 172 if (o == NULL) return true; 173 if (((intptr_t)o & 1) != 0) return true; 174 if (*(address*)o == badAddress) return true; // kill by Node::destruct 175 return false; 176 } 177 #endif // !PRODUCT 178 }; 179 180 //------------------------------MachNode--------------------------------------- 181 // Base type for all machine specific nodes. All node classes generated by the 182 // ADLC inherit from this class. 183 class MachNode : public Node { 184 public: 185 MachNode() : Node((uint)0), _num_opnds(0), _opnds(NULL) { 186 init_class_id(Class_Mach); 187 } 188 // Required boilerplate 189 virtual uint size_of() const { return sizeof(MachNode); } 190 virtual int Opcode() const; // Always equal to MachNode 191 virtual uint rule() const = 0; // Machine-specific opcode 192 // Number of inputs which come before the first operand. 193 // Generally at least 1, to skip the Control input 194 virtual uint oper_input_base() const { return 1; } 195 // Position of constant base node in node's inputs. -1 if 196 // no constant base node input. 197 virtual uint mach_constant_base_node_input() const { return (uint)-1; } 198 199 // Copy inputs and operands to new node of instruction. 200 // Called from cisc_version() and short_branch_version(). 201 // !!!! The method's body is defined in ad_<arch>.cpp file. 202 void fill_new_machnode(MachNode *n, Compile* C) const; 203 204 // Return an equivalent instruction using memory for cisc_operand position 205 virtual MachNode *cisc_version(int offset, Compile* C); 206 // Modify this instruction's register mask to use stack version for cisc_operand 207 virtual void use_cisc_RegMask(); 208 209 // Support for short branches 210 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; } 211 212 // Avoid back to back some instructions on some CPUs. 213 bool avoid_back_to_back() const { return (flags() & Flag_avoid_back_to_back) != 0; } 214 215 // instruction implemented with a call 216 bool has_call() const { return (flags() & Flag_has_call) != 0; } 217 218 // First index in _in[] corresponding to operand, or -1 if there is none 219 int operand_index(uint operand) const; 220 int operand_index(const MachOper *oper) const; 221 222 // Register class input is expected in 223 virtual const RegMask &in_RegMask(uint) const; 224 225 // cisc-spillable instructions redefine for use by in_RegMask 226 virtual const RegMask *cisc_RegMask() const { return NULL; } 227 228 // If this instruction is a 2-address instruction, then return the 229 // index of the input which must match the output. Not nessecary 230 // for instructions which bind the input and output register to the 231 // same singleton regiser (e.g., Intel IDIV which binds AX to be 232 // both an input and an output). It is nessecary when the input and 233 // output have choices - but they must use the same choice. 234 virtual uint two_adr( ) const { return 0; } 235 236 // Array of complex operand pointers. Each corresponds to zero or 237 // more leafs. Must be set by MachNode constructor to point to an 238 // internal array of MachOpers. The MachOper array is sized by 239 // specific MachNodes described in the ADL. 240 uint _num_opnds; 241 MachOper **_opnds; 242 uint num_opnds() const { return _num_opnds; } 243 244 // Emit bytes into cbuf 245 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 246 // Expand node after register allocation. 247 // Node is replaced by several nodes in the postalloc expand phase. 248 // Corresponding methods are generated for nodes if they specify 249 // postalloc_expand. See block.cpp for more documentation. 250 virtual bool requires_postalloc_expand() const { return false; } 251 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_); 252 // Size of instruction in bytes 253 virtual uint size(PhaseRegAlloc *ra_) const; 254 // Helper function that computes size by emitting code 255 virtual uint emit_size(PhaseRegAlloc *ra_) const; 256 257 // Return the alignment required (in units of relocInfo::addr_unit()) 258 // for this instruction (must be a power of 2) 259 virtual int alignment_required() const { return 1; } 260 261 // Return the padding (in bytes) to be emitted before this 262 // instruction to properly align it. 263 virtual int compute_padding(int current_offset) const { return 0; } 264 265 // Return number of relocatable values contained in this instruction 266 virtual int reloc() const { return 0; } 267 268 // Return number of words used for double constants in this instruction 269 virtual int ins_num_consts() const { return 0; } 270 271 // Hash and compare over operands. Used to do GVN on machine Nodes. 272 virtual uint hash() const; 273 virtual uint cmp( const Node &n ) const; 274 275 // Expand method for MachNode, replaces nodes representing pseudo 276 // instructions with a set of nodes which represent real machine 277 // instructions and compute the same value. 278 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; } 279 280 // Bottom_type call; value comes from operand0 281 virtual const class Type *bottom_type() const { return _opnds[0]->type(); } 282 virtual uint ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Op_RegFlags : t->ideal_reg(); } 283 284 // If this is a memory op, return the base pointer and fixed offset. 285 // If there are no such, return NULL. If there are multiple addresses 286 // or the address is indeterminate (rare cases) then return (Node*)-1, 287 // which serves as node bottom. 288 // If the offset is not statically determined, set it to Type::OffsetBot. 289 // This method is free to ignore stack slots if that helps. 290 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1) 291 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible 292 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const; 293 294 // Helper for get_base_and_disp: find the base and index input nodes. 295 // Returns the MachOper as determined by memory_operand(), for use, if 296 // needed by the caller. If (MachOper *)-1 is returned, base and index 297 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and 298 // index are set to NULL. 299 const MachOper* memory_inputs(Node* &base, Node* &index) const; 300 301 // Helper for memory_inputs: Which operand carries the necessary info? 302 // By default, returns NULL, which means there is no such operand. 303 // If it returns (MachOper*)-1, this means there are multiple memories. 304 virtual const MachOper* memory_operand() const { return NULL; } 305 306 // Call "get_base_and_disp" to decide which category of memory is used here. 307 virtual const class TypePtr *adr_type() const; 308 309 // Apply peephole rule(s) to this instruction 310 virtual MachNode *peephole( Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted, Compile* C ); 311 312 // Top-level ideal Opcode matched 313 virtual int ideal_Opcode() const { return Op_Node; } 314 315 // Adds the label for the case 316 virtual void add_case_label( int switch_val, Label* blockLabel); 317 318 // Set the absolute address for methods 319 virtual void method_set( intptr_t addr ); 320 321 // Should we clone rather than spill this instruction? 322 bool rematerialize() const; 323 324 // Get the pipeline info 325 static const Pipeline *pipeline_class(); 326 virtual const Pipeline *pipeline() const; 327 328 // Returns true if this node is a check that can be implemented with a trap. 329 virtual bool is_TrapBasedCheckNode() const { return false; } 330 331 #ifndef PRODUCT 332 virtual const char *Name() const = 0; // Machine-specific name 333 virtual void dump_spec(outputStream *st) const; // Print per-node info 334 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual 335 #endif 336 }; 337 338 //------------------------------MachIdealNode---------------------------- 339 // Machine specific versions of nodes that must be defined by user. 340 // These are not converted by matcher from ideal nodes to machine nodes 341 // but are inserted into the code by the compiler. 342 class MachIdealNode : public MachNode { 343 public: 344 MachIdealNode( ) {} 345 346 // Define the following defaults for non-matched machine nodes 347 virtual uint oper_input_base() const { return 0; } 348 virtual uint rule() const { return 9999999; } 349 virtual const class Type *bottom_type() const { return _opnds == NULL ? Type::CONTROL : MachNode::bottom_type(); } 350 }; 351 352 //------------------------------MachTypeNode---------------------------- 353 // Machine Nodes that need to retain a known Type. 354 class MachTypeNode : public MachNode { 355 virtual uint size_of() const { return sizeof(*this); } // Size is bigger 356 public: 357 MachTypeNode( ) {} 358 const Type *_bottom_type; 359 360 virtual const class Type *bottom_type() const { return _bottom_type; } 361 #ifndef PRODUCT 362 virtual void dump_spec(outputStream *st) const; 363 #endif 364 }; 365 366 //------------------------------MachBreakpointNode---------------------------- 367 // Machine breakpoint or interrupt Node 368 class MachBreakpointNode : public MachIdealNode { 369 public: 370 MachBreakpointNode( ) {} 371 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 372 virtual uint size(PhaseRegAlloc *ra_) const; 373 374 #ifndef PRODUCT 375 virtual const char *Name() const { return "Breakpoint"; } 376 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 377 #endif 378 }; 379 380 //------------------------------MachConstantBaseNode-------------------------- 381 // Machine node that represents the base address of the constant table. 382 class MachConstantBaseNode : public MachIdealNode { 383 public: 384 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask(). 385 386 public: 387 MachConstantBaseNode() : MachIdealNode() { 388 init_class_id(Class_MachConstantBase); 389 } 390 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; } 391 virtual uint ideal_reg() const { return Op_RegP; } 392 virtual uint oper_input_base() const { return 1; } 393 394 virtual bool requires_postalloc_expand() const; 395 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_); 396 397 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const; 398 virtual uint size(PhaseRegAlloc* ra_) const; 399 virtual bool pinned() const { return UseRDPCForConstantTableBase; } 400 401 static const RegMask& static_out_RegMask() { return _out_RegMask; } 402 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); } 403 404 #ifndef PRODUCT 405 virtual const char* Name() const { return "MachConstantBaseNode"; } 406 virtual void format(PhaseRegAlloc*, outputStream* st) const; 407 #endif 408 }; 409 410 //------------------------------MachConstantNode------------------------------- 411 // Machine node that holds a constant which is stored in the constant table. 412 class MachConstantNode : public MachTypeNode { 413 protected: 414 Compile::Constant _constant; // This node's constant. 415 416 public: 417 MachConstantNode() : MachTypeNode() { 418 init_class_id(Class_MachConstant); 419 } 420 421 virtual void eval_constant(Compile* C) { 422 #ifdef ASSERT 423 tty->print("missing MachConstantNode eval_constant function: "); 424 dump(); 425 #endif 426 ShouldNotCallThis(); 427 } 428 429 virtual const RegMask &in_RegMask(uint idx) const { 430 if (idx == mach_constant_base_node_input()) 431 return MachConstantBaseNode::static_out_RegMask(); 432 return MachNode::in_RegMask(idx); 433 } 434 435 // Input edge of MachConstantBaseNode. 436 virtual uint mach_constant_base_node_input() const { return req() - 1; } 437 438 int constant_offset(); 439 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); } 440 // Unchecked version to avoid assertions in debug output. 441 int constant_offset_unchecked() const; 442 }; 443 444 //------------------------------MachUEPNode----------------------------------- 445 // Machine Unvalidated Entry Point Node 446 class MachUEPNode : public MachIdealNode { 447 public: 448 MachUEPNode( ) {} 449 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 450 virtual uint size(PhaseRegAlloc *ra_) const; 451 452 #ifndef PRODUCT 453 virtual const char *Name() const { return "Unvalidated-Entry-Point"; } 454 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 455 #endif 456 }; 457 458 //------------------------------MachPrologNode-------------------------------- 459 // Machine function Prolog Node 460 class MachPrologNode : public MachIdealNode { 461 public: 462 MachPrologNode( ) {} 463 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 464 virtual uint size(PhaseRegAlloc *ra_) const; 465 virtual int reloc() const; 466 467 #ifndef PRODUCT 468 virtual const char *Name() const { return "Prolog"; } 469 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 470 #endif 471 }; 472 473 //------------------------------MachEpilogNode-------------------------------- 474 // Machine function Epilog Node 475 class MachEpilogNode : public MachIdealNode { 476 public: 477 MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {} 478 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 479 virtual uint size(PhaseRegAlloc *ra_) const; 480 virtual int reloc() const; 481 virtual const Pipeline *pipeline() const; 482 483 private: 484 bool _do_polling; 485 486 public: 487 bool do_polling() const { return _do_polling; } 488 489 // Offset of safepoint from the beginning of the node 490 int safepoint_offset() const; 491 492 #ifndef PRODUCT 493 virtual const char *Name() const { return "Epilog"; } 494 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 495 #endif 496 }; 497 498 //------------------------------MachNopNode----------------------------------- 499 // Machine function Nop Node 500 class MachNopNode : public MachIdealNode { 501 private: 502 int _count; 503 public: 504 MachNopNode( ) : _count(1) {} 505 MachNopNode( int count ) : _count(count) {} 506 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 507 virtual uint size(PhaseRegAlloc *ra_) const; 508 509 virtual const class Type *bottom_type() const { return Type::CONTROL; } 510 511 virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp 512 virtual const Pipeline *pipeline() const; 513 #ifndef PRODUCT 514 virtual const char *Name() const { return "Nop"; } 515 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 516 virtual void dump_spec(outputStream *st) const { } // No per-operand info 517 #endif 518 }; 519 520 //------------------------------MachSpillCopyNode------------------------------ 521 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any 522 // location (stack or register). 523 class MachSpillCopyNode : public MachIdealNode { 524 public: 525 enum SpillType { 526 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails 527 PhiInput, // Inserted when coalescing of a phi node and its input fails 528 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks 529 LoopPhiInput, // Pre-split compares of loop-phis 530 Definition, // An lrg marked as spilled will be spilled to memory right after its definition, 531 // if in high pressure region or the lrg is bound 532 RegToReg, // A register to register move 533 RegToMem, // A register to memory move 534 MemToReg, // A memory to register move 535 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if 536 // the phi and its input resides at different locations (i.e. reg or mem) 537 BasePointerToMem, // Spill base pointer to memory at safepoint 538 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be 539 // stretched beyond a new definition point, therefore we split out new copies instead 540 CallUse, // Spill use at a call 541 Bound // An lrg marked as spill that is bound and needs to be spilled at a use 542 }; 543 private: 544 const RegMask *_in; // RegMask for input 545 const RegMask *_out; // RegMask for output 546 const Type *_type; 547 const SpillType _spill_type; 548 public: 549 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) : 550 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) { 551 init_class_id(Class_MachSpillCopy); 552 init_flags(Flag_is_Copy); 553 add_req(NULL); 554 add_req(n); 555 } 556 virtual uint size_of() const { return sizeof(*this); } 557 void set_out_RegMask(const RegMask &out) { _out = &out; } 558 void set_in_RegMask(const RegMask &in) { _in = ∈ } 559 virtual const RegMask &out_RegMask() const { return *_out; } 560 virtual const RegMask &in_RegMask(uint) const { return *_in; } 561 virtual const class Type *bottom_type() const { return _type; } 562 virtual uint ideal_reg() const { return _type->ideal_reg(); } 563 virtual uint oper_input_base() const { return 1; } 564 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const; 565 566 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 567 virtual uint size(PhaseRegAlloc *ra_) const; 568 569 570 #ifndef PRODUCT 571 virtual const char *Name() const { 572 switch (_spill_type) { 573 case TwoAddress: 574 return "TwoAddressSpillCopy"; 575 case PhiInput: 576 return "PhiInputSpillCopy"; 577 case DebugUse: 578 return "DebugUseSpillCopy"; 579 case LoopPhiInput: 580 return "LoopPhiInputSpillCopy"; 581 case Definition: 582 return "DefinitionSpillCopy"; 583 case RegToReg: 584 return "RegToRegSpillCopy"; 585 case RegToMem: 586 return "RegToMemSpillCopy"; 587 case MemToReg: 588 return "MemToRegSpillCopy"; 589 case PhiLocationDifferToInputLocation: 590 return "PhiLocationDifferToInputLocationSpillCopy"; 591 case BasePointerToMem: 592 return "BasePointerToMemSpillCopy"; 593 case InputToRematerialization: 594 return "InputToRematerializationSpillCopy"; 595 case CallUse: 596 return "CallUseSpillCopy"; 597 case Bound: 598 return "BoundSpillCopy"; 599 default: 600 assert(false, "Must have valid spill type"); 601 return "MachSpillCopy"; 602 } 603 } 604 605 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 606 #endif 607 }; 608 609 //------------------------------MachBranchNode-------------------------------- 610 // Abstract machine branch Node 611 class MachBranchNode : public MachIdealNode { 612 public: 613 MachBranchNode() : MachIdealNode() { 614 init_class_id(Class_MachBranch); 615 } 616 virtual void label_set(Label* label, uint block_num) = 0; 617 virtual void save_label(Label** label, uint* block_num) = 0; 618 619 // Support for short branches 620 virtual MachNode *short_branch_version(Compile* C) { return NULL; } 621 622 virtual bool pinned() const { return true; }; 623 }; 624 625 //------------------------------MachNullChkNode-------------------------------- 626 // Machine-dependent null-pointer-check Node. Points a real MachNode that is 627 // also some kind of memory op. Turns the indicated MachNode into a 628 // conditional branch with good latency on the ptr-not-null path and awful 629 // latency on the pointer-is-null path. 630 631 class MachNullCheckNode : public MachBranchNode { 632 public: 633 const uint _vidx; // Index of memop being tested 634 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) { 635 init_class_id(Class_MachNullCheck); 636 add_req(ctrl); 637 add_req(memop); 638 } 639 virtual uint size_of() const { return sizeof(*this); } 640 641 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 642 virtual void label_set(Label* label, uint block_num); 643 virtual void save_label(Label** label, uint* block_num); 644 virtual void negate() { } 645 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; } 646 virtual uint ideal_reg() const { return NotAMachineReg; } 647 virtual const RegMask &in_RegMask(uint) const; 648 virtual const RegMask &out_RegMask() const { return RegMask::Empty; } 649 #ifndef PRODUCT 650 virtual const char *Name() const { return "NullCheck"; } 651 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 652 #endif 653 }; 654 655 //------------------------------MachProjNode---------------------------------- 656 // Machine-dependent Ideal projections (how is that for an oxymoron). Really 657 // just MachNodes made by the Ideal world that replicate simple projections 658 // but with machine-dependent input & output register masks. Generally 659 // produced as part of calling conventions. Normally I make MachNodes as part 660 // of the Matcher process, but the Matcher is ill suited to issues involving 661 // frame handling, so frame handling is all done in the Ideal world with 662 // occasional callbacks to the machine model for important info. 663 class MachProjNode : public ProjNode { 664 public: 665 MachProjNode( Node *multi, uint con, const RegMask &out, uint ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) { 666 init_class_id(Class_MachProj); 667 } 668 RegMask _rout; 669 const uint _ideal_reg; 670 enum projType { 671 unmatched_proj = 0, // Projs for Control, I/O, memory not matched 672 fat_proj = 999 // Projs killing many regs, defined by _rout 673 }; 674 virtual int Opcode() const; 675 virtual const Type *bottom_type() const; 676 virtual const TypePtr *adr_type() const; 677 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; } 678 virtual const RegMask &out_RegMask() const { return _rout; } 679 virtual uint ideal_reg() const { return _ideal_reg; } 680 // Need size_of() for virtual ProjNode::clone() 681 virtual uint size_of() const { return sizeof(MachProjNode); } 682 #ifndef PRODUCT 683 virtual void dump_spec(outputStream *st) const; 684 #endif 685 }; 686 687 //------------------------------MachIfNode------------------------------------- 688 // Machine-specific versions of IfNodes 689 class MachIfNode : public MachBranchNode { 690 virtual uint size_of() const { return sizeof(*this); } // Size is bigger 691 public: 692 float _prob; // Probability branch goes either way 693 float _fcnt; // Frequency counter 694 MachIfNode() : MachBranchNode() { 695 init_class_id(Class_MachIf); 696 } 697 // Negate conditional branches. 698 virtual void negate() = 0; 699 #ifndef PRODUCT 700 virtual void dump_spec(outputStream *st) const; 701 #endif 702 }; 703 704 //------------------------------MachGotoNode----------------------------------- 705 // Machine-specific versions of GotoNodes 706 class MachGotoNode : public MachBranchNode { 707 public: 708 MachGotoNode() : MachBranchNode() { 709 init_class_id(Class_MachGoto); 710 } 711 }; 712 713 //------------------------------MachFastLockNode------------------------------------- 714 // Machine-specific versions of FastLockNodes 715 class MachFastLockNode : public MachNode { 716 virtual uint size_of() const { return sizeof(*this); } // Size is bigger 717 public: 718 BiasedLockingCounters* _counters; 719 RTMLockingCounters* _rtm_counters; // RTM lock counters for inflated locks 720 RTMLockingCounters* _stack_rtm_counters; // RTM lock counters for stack locks 721 MachFastLockNode() : MachNode() {} 722 }; 723 724 //------------------------------MachReturnNode-------------------------------- 725 // Machine-specific versions of subroutine returns 726 class MachReturnNode : public MachNode { 727 virtual uint size_of() const; // Size is bigger 728 public: 729 RegMask *_in_rms; // Input register masks, set during allocation 730 ReallocMark _nesting; // assertion check for reallocations 731 const TypePtr* _adr_type; // memory effects of call or return 732 MachReturnNode() : MachNode() { 733 init_class_id(Class_MachReturn); 734 _adr_type = TypePtr::BOTTOM; // the default: all of memory 735 } 736 737 void set_adr_type(const TypePtr* atp) { _adr_type = atp; } 738 739 virtual const RegMask &in_RegMask(uint) const; 740 virtual bool pinned() const { return true; }; 741 virtual const TypePtr *adr_type() const; 742 }; 743 744 //------------------------------MachSafePointNode----------------------------- 745 // Machine-specific versions of safepoints 746 class MachSafePointNode : public MachReturnNode { 747 public: 748 OopMap* _oop_map; // Array of OopMap info (8-bit char) for GC 749 JVMState* _jvms; // Pointer to list of JVM State Objects 750 uint _jvmadj; // Extra delta to jvms indexes (mach. args) 751 OopMap* oop_map() const { return _oop_map; } 752 void set_oop_map(OopMap* om) { _oop_map = om; } 753 754 MachSafePointNode() : MachReturnNode(), _oop_map(NULL), _jvms(NULL), _jvmadj(0) { 755 init_class_id(Class_MachSafePoint); 756 } 757 758 virtual JVMState* jvms() const { return _jvms; } 759 void set_jvms(JVMState* s) { 760 _jvms = s; 761 } 762 virtual const Type *bottom_type() const; 763 764 virtual const RegMask &in_RegMask(uint) const; 765 766 // Functionality from old debug nodes 767 Node *returnadr() const { return in(TypeFunc::ReturnAdr); } 768 Node *frameptr () const { return in(TypeFunc::FramePtr); } 769 770 Node *local(const JVMState* jvms, uint idx) const { 771 assert(verify_jvms(jvms), "jvms must match"); 772 return in(_jvmadj + jvms->locoff() + idx); 773 } 774 Node *stack(const JVMState* jvms, uint idx) const { 775 assert(verify_jvms(jvms), "jvms must match"); 776 return in(_jvmadj + jvms->stkoff() + idx); 777 } 778 Node *monitor_obj(const JVMState* jvms, uint idx) const { 779 assert(verify_jvms(jvms), "jvms must match"); 780 return in(_jvmadj + jvms->monitor_obj_offset(idx)); 781 } 782 Node *monitor_box(const JVMState* jvms, uint idx) const { 783 assert(verify_jvms(jvms), "jvms must match"); 784 return in(_jvmadj + jvms->monitor_box_offset(idx)); 785 } 786 void set_local(const JVMState* jvms, uint idx, Node *c) { 787 assert(verify_jvms(jvms), "jvms must match"); 788 set_req(_jvmadj + jvms->locoff() + idx, c); 789 } 790 void set_stack(const JVMState* jvms, uint idx, Node *c) { 791 assert(verify_jvms(jvms), "jvms must match"); 792 set_req(_jvmadj + jvms->stkoff() + idx, c); 793 } 794 void set_monitor(const JVMState* jvms, uint idx, Node *c) { 795 assert(verify_jvms(jvms), "jvms must match"); 796 set_req(_jvmadj + jvms->monoff() + idx, c); 797 } 798 }; 799 800 //------------------------------MachCallNode---------------------------------- 801 // Machine-specific versions of subroutine calls 802 class MachCallNode : public MachSafePointNode { 803 protected: 804 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash 805 virtual uint cmp( const Node &n ) const; 806 virtual uint size_of() const = 0; // Size is bigger 807 public: 808 const TypeFunc *_tf; // Function type 809 address _entry_point; // Address of the method being called 810 float _cnt; // Estimate of number of times called 811 uint _argsize; // Size of argument block on stack 812 813 const TypeFunc* tf() const { return _tf; } 814 const address entry_point() const { return _entry_point; } 815 const float cnt() const { return _cnt; } 816 uint argsize() const { return _argsize; } 817 818 void set_tf(const TypeFunc* tf) { _tf = tf; } 819 void set_entry_point(address p) { _entry_point = p; } 820 void set_cnt(float c) { _cnt = c; } 821 void set_argsize(int s) { _argsize = s; } 822 823 MachCallNode() : MachSafePointNode() { 824 init_class_id(Class_MachCall); 825 } 826 827 virtual const Type *bottom_type() const; 828 virtual bool pinned() const { return false; } 829 virtual const Type *Value( PhaseTransform *phase ) const; 830 virtual const RegMask &in_RegMask(uint) const; 831 virtual int ret_addr_offset() { return 0; } 832 833 bool returns_long() const { return tf()->return_type() == T_LONG; } 834 bool return_value_is_used() const; 835 #ifndef PRODUCT 836 virtual void dump_spec(outputStream *st) const; 837 #endif 838 }; 839 840 //------------------------------MachCallJavaNode------------------------------ 841 // "Base" class for machine-specific versions of subroutine calls 842 class MachCallJavaNode : public MachCallNode { 843 protected: 844 virtual uint cmp( const Node &n ) const; 845 virtual uint size_of() const; // Size is bigger 846 public: 847 ciMethod* _method; // Method being direct called 848 int _bci; // Byte Code index of call byte code 849 bool _optimized_virtual; // Tells if node is a static call or an optimized virtual 850 bool _method_handle_invoke; // Tells if the call has to preserve SP 851 MachCallJavaNode() : MachCallNode() { 852 init_class_id(Class_MachCallJava); 853 } 854 855 virtual const RegMask &in_RegMask(uint) const; 856 857 #ifndef PRODUCT 858 virtual void dump_spec(outputStream *st) const; 859 #endif 860 }; 861 862 //------------------------------MachCallStaticJavaNode------------------------ 863 // Machine-specific versions of monomorphic subroutine calls 864 class MachCallStaticJavaNode : public MachCallJavaNode { 865 virtual uint cmp( const Node &n ) const; 866 virtual uint size_of() const; // Size is bigger 867 public: 868 const char *_name; // Runtime wrapper name 869 MachCallStaticJavaNode() : MachCallJavaNode() { 870 init_class_id(Class_MachCallStaticJava); 871 } 872 873 // If this is an uncommon trap, return the request code, else zero. 874 int uncommon_trap_request() const; 875 876 virtual int ret_addr_offset(); 877 #ifndef PRODUCT 878 virtual void dump_spec(outputStream *st) const; 879 void dump_trap_args(outputStream *st) const; 880 #endif 881 }; 882 883 //------------------------------MachCallDynamicJavaNode------------------------ 884 // Machine-specific versions of possibly megamorphic subroutine calls 885 class MachCallDynamicJavaNode : public MachCallJavaNode { 886 public: 887 int _vtable_index; 888 MachCallDynamicJavaNode() : MachCallJavaNode() { 889 init_class_id(Class_MachCallDynamicJava); 890 DEBUG_ONLY(_vtable_index = -99); // throw an assert if uninitialized 891 } 892 virtual int ret_addr_offset(); 893 #ifndef PRODUCT 894 virtual void dump_spec(outputStream *st) const; 895 #endif 896 }; 897 898 //------------------------------MachCallRuntimeNode---------------------------- 899 // Machine-specific versions of subroutine calls 900 class MachCallRuntimeNode : public MachCallNode { 901 virtual uint cmp( const Node &n ) const; 902 virtual uint size_of() const; // Size is bigger 903 public: 904 const char *_name; // Printable name, if _method is NULL 905 MachCallRuntimeNode() : MachCallNode() { 906 init_class_id(Class_MachCallRuntime); 907 } 908 virtual int ret_addr_offset(); 909 #ifndef PRODUCT 910 virtual void dump_spec(outputStream *st) const; 911 #endif 912 }; 913 914 class MachCallLeafNode: public MachCallRuntimeNode { 915 public: 916 MachCallLeafNode() : MachCallRuntimeNode() { 917 init_class_id(Class_MachCallLeaf); 918 } 919 }; 920 921 //------------------------------MachHaltNode----------------------------------- 922 // Machine-specific versions of halt nodes 923 class MachHaltNode : public MachReturnNode { 924 public: 925 virtual JVMState* jvms() const; 926 }; 927 928 929 //------------------------------MachTempNode----------------------------------- 930 // Node used by the adlc to construct inputs to represent temporary registers 931 class MachTempNode : public MachNode { 932 private: 933 MachOper *_opnd_array[1]; 934 935 public: 936 virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); } 937 virtual uint rule() const { return 9999999; } 938 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {} 939 940 MachTempNode(MachOper* oper) { 941 init_class_id(Class_MachTemp); 942 _num_opnds = 1; 943 _opnds = _opnd_array; 944 add_req(NULL); 945 _opnds[0] = oper; 946 } 947 virtual uint size_of() const { return sizeof(MachTempNode); } 948 949 #ifndef PRODUCT 950 virtual void format(PhaseRegAlloc *, outputStream *st ) const {} 951 virtual const char *Name() const { return "MachTemp";} 952 #endif 953 }; 954 955 956 957 //------------------------------labelOper-------------------------------------- 958 // Machine-independent version of label operand 959 class labelOper : public MachOper { 960 private: 961 virtual uint num_edges() const { return 0; } 962 public: 963 // Supported for fixed size branches 964 Label* _label; // Label for branch(es) 965 966 uint _block_num; 967 968 labelOper() : _block_num(0), _label(0) {} 969 970 labelOper(Label* label, uint block_num) : _label(label), _block_num(block_num) {} 971 972 labelOper(labelOper* l) : _label(l->_label) , _block_num(l->_block_num) {} 973 974 virtual MachOper *clone(Compile* C) const; 975 976 virtual Label *label() const { assert(_label != NULL, "need Label"); return _label; } 977 978 virtual uint opcode() const; 979 980 virtual uint hash() const; 981 virtual uint cmp( const MachOper &oper ) const; 982 #ifndef PRODUCT 983 virtual const char *Name() const { return "Label";} 984 985 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; 986 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); } 987 #endif 988 }; 989 990 991 //------------------------------methodOper-------------------------------------- 992 // Machine-independent version of method operand 993 class methodOper : public MachOper { 994 private: 995 virtual uint num_edges() const { return 0; } 996 public: 997 intptr_t _method; // Address of method 998 methodOper() : _method(0) {} 999 methodOper(intptr_t method) : _method(method) {} 1000 1001 virtual MachOper *clone(Compile* C) const; 1002 1003 virtual intptr_t method() const { return _method; } 1004 1005 virtual uint opcode() const; 1006 1007 virtual uint hash() const; 1008 virtual uint cmp( const MachOper &oper ) const; 1009 #ifndef PRODUCT 1010 virtual const char *Name() const { return "Method";} 1011 1012 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; 1013 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); } 1014 #endif 1015 }; 1016 1017 #endif // SHARE_VM_OPTO_MACHNODE_HPP